1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 33 #include <asm/div64.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46 }; 47 48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51 }; 52 53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55 { 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57 } 58 59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60 { 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69 } 70 71 static int ravb_config(struct net_device *ndev) 72 { 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83 } 84 85 static void ravb_set_duplex(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); 90 } 91 92 static void ravb_set_rate(struct net_device *ndev) 93 { 94 struct ravb_private *priv = netdev_priv(ndev); 95 96 switch (priv->speed) { 97 case 100: /* 100BASE */ 98 ravb_write(ndev, GECMR_SPEED_100, GECMR); 99 break; 100 case 1000: /* 1000BASE */ 101 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 102 break; 103 } 104 } 105 106 static void ravb_set_buffer_align(struct sk_buff *skb) 107 { 108 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 109 110 if (reserve) 111 skb_reserve(skb, RAVB_ALIGN - reserve); 112 } 113 114 /* Get MAC address from the MAC address registers 115 * 116 * Ethernet AVB device doesn't have ROM for MAC address. 117 * This function gets the MAC address that was used by a bootloader. 118 */ 119 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 120 { 121 if (mac) { 122 ether_addr_copy(ndev->dev_addr, mac); 123 } else { 124 u32 mahr = ravb_read(ndev, MAHR); 125 u32 malr = ravb_read(ndev, MALR); 126 127 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 128 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 129 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 130 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 131 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 132 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 133 } 134 } 135 136 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 137 { 138 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 139 mdiobb); 140 141 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 142 } 143 144 /* MDC pin control */ 145 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 146 { 147 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 148 } 149 150 /* Data I/O pin control */ 151 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 152 { 153 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 154 } 155 156 /* Set data bit */ 157 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 158 { 159 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 160 } 161 162 /* Get data bit */ 163 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 164 { 165 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 166 mdiobb); 167 168 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 169 } 170 171 /* MDIO bus control struct */ 172 static struct mdiobb_ops bb_ops = { 173 .owner = THIS_MODULE, 174 .set_mdc = ravb_set_mdc, 175 .set_mdio_dir = ravb_set_mdio_dir, 176 .set_mdio_data = ravb_set_mdio_data, 177 .get_mdio_data = ravb_get_mdio_data, 178 }; 179 180 /* Free TX skb function for AVB-IP */ 181 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 182 { 183 struct ravb_private *priv = netdev_priv(ndev); 184 struct net_device_stats *stats = &priv->stats[q]; 185 struct ravb_tx_desc *desc; 186 int free_num = 0; 187 int entry; 188 u32 size; 189 190 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 191 bool txed; 192 193 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 194 NUM_TX_DESC); 195 desc = &priv->tx_ring[q][entry]; 196 txed = desc->die_dt == DT_FEMPTY; 197 if (free_txed_only && !txed) 198 break; 199 /* Descriptor type must be checked before all other reads */ 200 dma_rmb(); 201 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 202 /* Free the original skb. */ 203 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 204 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 205 size, DMA_TO_DEVICE); 206 /* Last packet descriptor? */ 207 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 208 entry /= NUM_TX_DESC; 209 dev_kfree_skb_any(priv->tx_skb[q][entry]); 210 priv->tx_skb[q][entry] = NULL; 211 if (txed) 212 stats->tx_packets++; 213 } 214 free_num++; 215 } 216 if (txed) 217 stats->tx_bytes += size; 218 desc->die_dt = DT_EEMPTY; 219 } 220 return free_num; 221 } 222 223 /* Free skb's and DMA buffers for Ethernet AVB */ 224 static void ravb_ring_free(struct net_device *ndev, int q) 225 { 226 struct ravb_private *priv = netdev_priv(ndev); 227 int ring_size; 228 int i; 229 230 if (priv->rx_ring[q]) { 231 for (i = 0; i < priv->num_rx_ring[q]; i++) { 232 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 233 234 if (!dma_mapping_error(ndev->dev.parent, 235 le32_to_cpu(desc->dptr))) 236 dma_unmap_single(ndev->dev.parent, 237 le32_to_cpu(desc->dptr), 238 priv->rx_buf_sz, 239 DMA_FROM_DEVICE); 240 } 241 ring_size = sizeof(struct ravb_ex_rx_desc) * 242 (priv->num_rx_ring[q] + 1); 243 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 244 priv->rx_desc_dma[q]); 245 priv->rx_ring[q] = NULL; 246 } 247 248 if (priv->tx_ring[q]) { 249 ravb_tx_free(ndev, q, false); 250 251 ring_size = sizeof(struct ravb_tx_desc) * 252 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 253 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 254 priv->tx_desc_dma[q]); 255 priv->tx_ring[q] = NULL; 256 } 257 258 /* Free RX skb ringbuffer */ 259 if (priv->rx_skb[q]) { 260 for (i = 0; i < priv->num_rx_ring[q]; i++) 261 dev_kfree_skb(priv->rx_skb[q][i]); 262 } 263 kfree(priv->rx_skb[q]); 264 priv->rx_skb[q] = NULL; 265 266 /* Free aligned TX buffers */ 267 kfree(priv->tx_align[q]); 268 priv->tx_align[q] = NULL; 269 270 /* Free TX skb ringbuffer. 271 * SKBs are freed by ravb_tx_free() call above. 272 */ 273 kfree(priv->tx_skb[q]); 274 priv->tx_skb[q] = NULL; 275 } 276 277 /* Format skb and descriptor buffer for Ethernet AVB */ 278 static void ravb_ring_format(struct net_device *ndev, int q) 279 { 280 struct ravb_private *priv = netdev_priv(ndev); 281 struct ravb_ex_rx_desc *rx_desc; 282 struct ravb_tx_desc *tx_desc; 283 struct ravb_desc *desc; 284 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 285 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 286 NUM_TX_DESC; 287 dma_addr_t dma_addr; 288 int i; 289 290 priv->cur_rx[q] = 0; 291 priv->cur_tx[q] = 0; 292 priv->dirty_rx[q] = 0; 293 priv->dirty_tx[q] = 0; 294 295 memset(priv->rx_ring[q], 0, rx_ring_size); 296 /* Build RX ring buffer */ 297 for (i = 0; i < priv->num_rx_ring[q]; i++) { 298 /* RX descriptor */ 299 rx_desc = &priv->rx_ring[q][i]; 300 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 301 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 302 priv->rx_buf_sz, 303 DMA_FROM_DEVICE); 304 /* We just set the data size to 0 for a failed mapping which 305 * should prevent DMA from happening... 306 */ 307 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 308 rx_desc->ds_cc = cpu_to_le16(0); 309 rx_desc->dptr = cpu_to_le32(dma_addr); 310 rx_desc->die_dt = DT_FEMPTY; 311 } 312 rx_desc = &priv->rx_ring[q][i]; 313 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 314 rx_desc->die_dt = DT_LINKFIX; /* type */ 315 316 memset(priv->tx_ring[q], 0, tx_ring_size); 317 /* Build TX ring buffer */ 318 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 319 i++, tx_desc++) { 320 tx_desc->die_dt = DT_EEMPTY; 321 tx_desc++; 322 tx_desc->die_dt = DT_EEMPTY; 323 } 324 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 325 tx_desc->die_dt = DT_LINKFIX; /* type */ 326 327 /* RX descriptor base address for best effort */ 328 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 329 desc->die_dt = DT_LINKFIX; /* type */ 330 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 331 332 /* TX descriptor base address for best effort */ 333 desc = &priv->desc_bat[q]; 334 desc->die_dt = DT_LINKFIX; /* type */ 335 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 336 } 337 338 /* Init skb and descriptor buffer for Ethernet AVB */ 339 static int ravb_ring_init(struct net_device *ndev, int q) 340 { 341 struct ravb_private *priv = netdev_priv(ndev); 342 struct sk_buff *skb; 343 int ring_size; 344 int i; 345 346 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) + 347 ETH_HLEN + VLAN_HLEN; 348 349 /* Allocate RX and TX skb rings */ 350 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 351 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 352 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 353 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 354 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 355 goto error; 356 357 for (i = 0; i < priv->num_rx_ring[q]; i++) { 358 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1); 359 if (!skb) 360 goto error; 361 ravb_set_buffer_align(skb); 362 priv->rx_skb[q][i] = skb; 363 } 364 365 /* Allocate rings for the aligned buffers */ 366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 367 DPTR_ALIGN - 1, GFP_KERNEL); 368 if (!priv->tx_align[q]) 369 goto error; 370 371 /* Allocate all RX descriptors. */ 372 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 373 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 374 &priv->rx_desc_dma[q], 375 GFP_KERNEL); 376 if (!priv->rx_ring[q]) 377 goto error; 378 379 priv->dirty_rx[q] = 0; 380 381 /* Allocate all TX descriptors. */ 382 ring_size = sizeof(struct ravb_tx_desc) * 383 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 384 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 385 &priv->tx_desc_dma[q], 386 GFP_KERNEL); 387 if (!priv->tx_ring[q]) 388 goto error; 389 390 return 0; 391 392 error: 393 ravb_ring_free(ndev, q); 394 395 return -ENOMEM; 396 } 397 398 /* E-MAC init function */ 399 static void ravb_emac_init(struct net_device *ndev) 400 { 401 struct ravb_private *priv = netdev_priv(ndev); 402 403 /* Receive frame limit set register */ 404 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 405 406 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 407 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 408 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 409 ECMR_TE | ECMR_RE, ECMR); 410 411 ravb_set_rate(ndev); 412 413 /* Set MAC address */ 414 ravb_write(ndev, 415 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 416 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 417 ravb_write(ndev, 418 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 419 420 /* E-MAC status register clear */ 421 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 422 423 /* E-MAC interrupt enable register */ 424 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 425 } 426 427 /* Device init function for Ethernet AVB */ 428 static int ravb_dmac_init(struct net_device *ndev) 429 { 430 struct ravb_private *priv = netdev_priv(ndev); 431 int error; 432 433 /* Set CONFIG mode */ 434 error = ravb_config(ndev); 435 if (error) 436 return error; 437 438 error = ravb_ring_init(ndev, RAVB_BE); 439 if (error) 440 return error; 441 error = ravb_ring_init(ndev, RAVB_NC); 442 if (error) { 443 ravb_ring_free(ndev, RAVB_BE); 444 return error; 445 } 446 447 /* Descriptor format */ 448 ravb_ring_format(ndev, RAVB_BE); 449 ravb_ring_format(ndev, RAVB_NC); 450 451 #if defined(__LITTLE_ENDIAN) 452 ravb_modify(ndev, CCC, CCC_BOC, 0); 453 #else 454 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 455 #endif 456 457 /* Set AVB RX */ 458 ravb_write(ndev, 459 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 460 461 /* Set FIFO size */ 462 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 463 464 /* Timestamp enable */ 465 ravb_write(ndev, TCCR_TFEN, TCCR); 466 467 /* Interrupt init: */ 468 if (priv->chip_id == RCAR_GEN3) { 469 /* Clear DIL.DPLx */ 470 ravb_write(ndev, 0, DIL); 471 /* Set queue specific interrupt */ 472 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 473 } 474 /* Frame receive */ 475 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 476 /* Disable FIFO full warning */ 477 ravb_write(ndev, 0, RIC1); 478 /* Receive FIFO full error, descriptor empty */ 479 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 480 /* Frame transmitted, timestamp FIFO updated */ 481 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 482 483 /* Setting the control will start the AVB-DMAC process. */ 484 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 485 486 return 0; 487 } 488 489 static void ravb_get_tx_tstamp(struct net_device *ndev) 490 { 491 struct ravb_private *priv = netdev_priv(ndev); 492 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 493 struct skb_shared_hwtstamps shhwtstamps; 494 struct sk_buff *skb; 495 struct timespec64 ts; 496 u16 tag, tfa_tag; 497 int count; 498 u32 tfa2; 499 500 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 501 while (count--) { 502 tfa2 = ravb_read(ndev, TFA2); 503 tfa_tag = (tfa2 & TFA2_TST) >> 16; 504 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 505 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 506 ravb_read(ndev, TFA1); 507 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 508 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 509 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 510 list) { 511 skb = ts_skb->skb; 512 tag = ts_skb->tag; 513 list_del(&ts_skb->list); 514 kfree(ts_skb); 515 if (tag == tfa_tag) { 516 skb_tstamp_tx(skb, &shhwtstamps); 517 break; 518 } 519 } 520 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 521 } 522 } 523 524 static void ravb_rx_csum(struct sk_buff *skb) 525 { 526 u8 *hw_csum; 527 528 /* The hardware checksum is 2 bytes appended to packet data */ 529 if (unlikely(skb->len < 2)) 530 return; 531 hw_csum = skb_tail_pointer(skb) - 2; 532 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 533 skb->ip_summed = CHECKSUM_COMPLETE; 534 skb_trim(skb, skb->len - 2); 535 } 536 537 /* Packet receive function for Ethernet AVB */ 538 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 539 { 540 struct ravb_private *priv = netdev_priv(ndev); 541 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 542 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 543 priv->cur_rx[q]; 544 struct net_device_stats *stats = &priv->stats[q]; 545 struct ravb_ex_rx_desc *desc; 546 struct sk_buff *skb; 547 dma_addr_t dma_addr; 548 struct timespec64 ts; 549 u8 desc_status; 550 u16 pkt_len; 551 int limit; 552 553 boguscnt = min(boguscnt, *quota); 554 limit = boguscnt; 555 desc = &priv->rx_ring[q][entry]; 556 while (desc->die_dt != DT_FEMPTY) { 557 /* Descriptor type must be checked before all other reads */ 558 dma_rmb(); 559 desc_status = desc->msc; 560 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 561 562 if (--boguscnt < 0) 563 break; 564 565 /* We use 0-byte descriptors to mark the DMA mapping errors */ 566 if (!pkt_len) 567 continue; 568 569 if (desc_status & MSC_MC) 570 stats->multicast++; 571 572 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 573 MSC_CEEF)) { 574 stats->rx_errors++; 575 if (desc_status & MSC_CRC) 576 stats->rx_crc_errors++; 577 if (desc_status & MSC_RFE) 578 stats->rx_frame_errors++; 579 if (desc_status & (MSC_RTLF | MSC_RTSF)) 580 stats->rx_length_errors++; 581 if (desc_status & MSC_CEEF) 582 stats->rx_missed_errors++; 583 } else { 584 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 585 586 skb = priv->rx_skb[q][entry]; 587 priv->rx_skb[q][entry] = NULL; 588 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 589 priv->rx_buf_sz, 590 DMA_FROM_DEVICE); 591 get_ts &= (q == RAVB_NC) ? 592 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 593 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 594 if (get_ts) { 595 struct skb_shared_hwtstamps *shhwtstamps; 596 597 shhwtstamps = skb_hwtstamps(skb); 598 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 599 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 600 32) | le32_to_cpu(desc->ts_sl); 601 ts.tv_nsec = le32_to_cpu(desc->ts_n); 602 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 603 } 604 605 skb_put(skb, pkt_len); 606 skb->protocol = eth_type_trans(skb, ndev); 607 if (ndev->features & NETIF_F_RXCSUM) 608 ravb_rx_csum(skb); 609 napi_gro_receive(&priv->napi[q], skb); 610 stats->rx_packets++; 611 stats->rx_bytes += pkt_len; 612 } 613 614 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 615 desc = &priv->rx_ring[q][entry]; 616 } 617 618 /* Refill the RX ring buffers. */ 619 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 620 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 621 desc = &priv->rx_ring[q][entry]; 622 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 623 624 if (!priv->rx_skb[q][entry]) { 625 skb = netdev_alloc_skb(ndev, 626 priv->rx_buf_sz + 627 RAVB_ALIGN - 1); 628 if (!skb) 629 break; /* Better luck next round. */ 630 ravb_set_buffer_align(skb); 631 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 632 le16_to_cpu(desc->ds_cc), 633 DMA_FROM_DEVICE); 634 skb_checksum_none_assert(skb); 635 /* We just set the data size to 0 for a failed mapping 636 * which should prevent DMA from happening... 637 */ 638 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 639 desc->ds_cc = cpu_to_le16(0); 640 desc->dptr = cpu_to_le32(dma_addr); 641 priv->rx_skb[q][entry] = skb; 642 } 643 /* Descriptor type must be set after all the above writes */ 644 dma_wmb(); 645 desc->die_dt = DT_FEMPTY; 646 } 647 648 *quota -= limit - (++boguscnt); 649 650 return boguscnt <= 0; 651 } 652 653 static void ravb_rcv_snd_disable(struct net_device *ndev) 654 { 655 /* Disable TX and RX */ 656 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 657 } 658 659 static void ravb_rcv_snd_enable(struct net_device *ndev) 660 { 661 /* Enable TX and RX */ 662 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 663 } 664 665 /* function for waiting dma process finished */ 666 static int ravb_stop_dma(struct net_device *ndev) 667 { 668 int error; 669 670 /* Wait for stopping the hardware TX process */ 671 error = ravb_wait(ndev, TCCR, 672 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 673 if (error) 674 return error; 675 676 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 677 0); 678 if (error) 679 return error; 680 681 /* Stop the E-MAC's RX/TX processes. */ 682 ravb_rcv_snd_disable(ndev); 683 684 /* Wait for stopping the RX DMA process */ 685 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 686 if (error) 687 return error; 688 689 /* Stop AVB-DMAC process */ 690 return ravb_config(ndev); 691 } 692 693 /* E-MAC interrupt handler */ 694 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 695 { 696 struct ravb_private *priv = netdev_priv(ndev); 697 u32 ecsr, psr; 698 699 ecsr = ravb_read(ndev, ECSR); 700 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 701 702 if (ecsr & ECSR_MPD) 703 pm_wakeup_event(&priv->pdev->dev, 0); 704 if (ecsr & ECSR_ICD) 705 ndev->stats.tx_carrier_errors++; 706 if (ecsr & ECSR_LCHNG) { 707 /* Link changed */ 708 if (priv->no_avb_link) 709 return; 710 psr = ravb_read(ndev, PSR); 711 if (priv->avb_link_active_low) 712 psr ^= PSR_LMON; 713 if (!(psr & PSR_LMON)) { 714 /* DIsable RX and TX */ 715 ravb_rcv_snd_disable(ndev); 716 } else { 717 /* Enable RX and TX */ 718 ravb_rcv_snd_enable(ndev); 719 } 720 } 721 } 722 723 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 724 { 725 struct net_device *ndev = dev_id; 726 struct ravb_private *priv = netdev_priv(ndev); 727 728 spin_lock(&priv->lock); 729 ravb_emac_interrupt_unlocked(ndev); 730 mmiowb(); 731 spin_unlock(&priv->lock); 732 return IRQ_HANDLED; 733 } 734 735 /* Error interrupt handler */ 736 static void ravb_error_interrupt(struct net_device *ndev) 737 { 738 struct ravb_private *priv = netdev_priv(ndev); 739 u32 eis, ris2; 740 741 eis = ravb_read(ndev, EIS); 742 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 743 if (eis & EIS_QFS) { 744 ris2 = ravb_read(ndev, RIS2); 745 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 746 RIS2); 747 748 /* Receive Descriptor Empty int */ 749 if (ris2 & RIS2_QFF0) 750 priv->stats[RAVB_BE].rx_over_errors++; 751 752 /* Receive Descriptor Empty int */ 753 if (ris2 & RIS2_QFF1) 754 priv->stats[RAVB_NC].rx_over_errors++; 755 756 /* Receive FIFO Overflow int */ 757 if (ris2 & RIS2_RFFF) 758 priv->rx_fifo_errors++; 759 } 760 } 761 762 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 763 { 764 struct ravb_private *priv = netdev_priv(ndev); 765 u32 ris0 = ravb_read(ndev, RIS0); 766 u32 ric0 = ravb_read(ndev, RIC0); 767 u32 tis = ravb_read(ndev, TIS); 768 u32 tic = ravb_read(ndev, TIC); 769 770 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 771 if (napi_schedule_prep(&priv->napi[q])) { 772 /* Mask RX and TX interrupts */ 773 if (priv->chip_id == RCAR_GEN2) { 774 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 775 ravb_write(ndev, tic & ~BIT(q), TIC); 776 } else { 777 ravb_write(ndev, BIT(q), RID0); 778 ravb_write(ndev, BIT(q), TID); 779 } 780 __napi_schedule(&priv->napi[q]); 781 } else { 782 netdev_warn(ndev, 783 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 784 ris0, ric0); 785 netdev_warn(ndev, 786 " tx status 0x%08x, tx mask 0x%08x.\n", 787 tis, tic); 788 } 789 return true; 790 } 791 return false; 792 } 793 794 static bool ravb_timestamp_interrupt(struct net_device *ndev) 795 { 796 u32 tis = ravb_read(ndev, TIS); 797 798 if (tis & TIS_TFUF) { 799 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 800 ravb_get_tx_tstamp(ndev); 801 return true; 802 } 803 return false; 804 } 805 806 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 807 { 808 struct net_device *ndev = dev_id; 809 struct ravb_private *priv = netdev_priv(ndev); 810 irqreturn_t result = IRQ_NONE; 811 u32 iss; 812 813 spin_lock(&priv->lock); 814 /* Get interrupt status */ 815 iss = ravb_read(ndev, ISS); 816 817 /* Received and transmitted interrupts */ 818 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 819 int q; 820 821 /* Timestamp updated */ 822 if (ravb_timestamp_interrupt(ndev)) 823 result = IRQ_HANDLED; 824 825 /* Network control and best effort queue RX/TX */ 826 for (q = RAVB_NC; q >= RAVB_BE; q--) { 827 if (ravb_queue_interrupt(ndev, q)) 828 result = IRQ_HANDLED; 829 } 830 } 831 832 /* E-MAC status summary */ 833 if (iss & ISS_MS) { 834 ravb_emac_interrupt_unlocked(ndev); 835 result = IRQ_HANDLED; 836 } 837 838 /* Error status summary */ 839 if (iss & ISS_ES) { 840 ravb_error_interrupt(ndev); 841 result = IRQ_HANDLED; 842 } 843 844 /* gPTP interrupt status summary */ 845 if (iss & ISS_CGIS) { 846 ravb_ptp_interrupt(ndev); 847 result = IRQ_HANDLED; 848 } 849 850 mmiowb(); 851 spin_unlock(&priv->lock); 852 return result; 853 } 854 855 /* Timestamp/Error/gPTP interrupt handler */ 856 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 857 { 858 struct net_device *ndev = dev_id; 859 struct ravb_private *priv = netdev_priv(ndev); 860 irqreturn_t result = IRQ_NONE; 861 u32 iss; 862 863 spin_lock(&priv->lock); 864 /* Get interrupt status */ 865 iss = ravb_read(ndev, ISS); 866 867 /* Timestamp updated */ 868 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 869 result = IRQ_HANDLED; 870 871 /* Error status summary */ 872 if (iss & ISS_ES) { 873 ravb_error_interrupt(ndev); 874 result = IRQ_HANDLED; 875 } 876 877 /* gPTP interrupt status summary */ 878 if (iss & ISS_CGIS) { 879 ravb_ptp_interrupt(ndev); 880 result = IRQ_HANDLED; 881 } 882 883 mmiowb(); 884 spin_unlock(&priv->lock); 885 return result; 886 } 887 888 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 889 { 890 struct net_device *ndev = dev_id; 891 struct ravb_private *priv = netdev_priv(ndev); 892 irqreturn_t result = IRQ_NONE; 893 894 spin_lock(&priv->lock); 895 896 /* Network control/Best effort queue RX/TX */ 897 if (ravb_queue_interrupt(ndev, q)) 898 result = IRQ_HANDLED; 899 900 mmiowb(); 901 spin_unlock(&priv->lock); 902 return result; 903 } 904 905 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 906 { 907 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 908 } 909 910 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 911 { 912 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 913 } 914 915 static int ravb_poll(struct napi_struct *napi, int budget) 916 { 917 struct net_device *ndev = napi->dev; 918 struct ravb_private *priv = netdev_priv(ndev); 919 unsigned long flags; 920 int q = napi - priv->napi; 921 int mask = BIT(q); 922 int quota = budget; 923 u32 ris0, tis; 924 925 for (;;) { 926 tis = ravb_read(ndev, TIS); 927 ris0 = ravb_read(ndev, RIS0); 928 if (!((ris0 & mask) || (tis & mask))) 929 break; 930 931 /* Processing RX Descriptor Ring */ 932 if (ris0 & mask) { 933 /* Clear RX interrupt */ 934 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 935 if (ravb_rx(ndev, "a, q)) 936 goto out; 937 } 938 /* Processing TX Descriptor Ring */ 939 if (tis & mask) { 940 spin_lock_irqsave(&priv->lock, flags); 941 /* Clear TX interrupt */ 942 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 943 ravb_tx_free(ndev, q, true); 944 netif_wake_subqueue(ndev, q); 945 mmiowb(); 946 spin_unlock_irqrestore(&priv->lock, flags); 947 } 948 } 949 950 napi_complete(napi); 951 952 /* Re-enable RX/TX interrupts */ 953 spin_lock_irqsave(&priv->lock, flags); 954 if (priv->chip_id == RCAR_GEN2) { 955 ravb_modify(ndev, RIC0, mask, mask); 956 ravb_modify(ndev, TIC, mask, mask); 957 } else { 958 ravb_write(ndev, mask, RIE0); 959 ravb_write(ndev, mask, TIE); 960 } 961 mmiowb(); 962 spin_unlock_irqrestore(&priv->lock, flags); 963 964 /* Receive error message handling */ 965 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 966 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 967 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 968 ndev->stats.rx_over_errors = priv->rx_over_errors; 969 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 970 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 971 out: 972 return budget - quota; 973 } 974 975 /* PHY state control function */ 976 static void ravb_adjust_link(struct net_device *ndev) 977 { 978 struct ravb_private *priv = netdev_priv(ndev); 979 struct phy_device *phydev = ndev->phydev; 980 bool new_state = false; 981 unsigned long flags; 982 983 spin_lock_irqsave(&priv->lock, flags); 984 985 /* Disable TX and RX right over here, if E-MAC change is ignored */ 986 if (priv->no_avb_link) 987 ravb_rcv_snd_disable(ndev); 988 989 if (phydev->link) { 990 if (phydev->duplex != priv->duplex) { 991 new_state = true; 992 priv->duplex = phydev->duplex; 993 ravb_set_duplex(ndev); 994 } 995 996 if (phydev->speed != priv->speed) { 997 new_state = true; 998 priv->speed = phydev->speed; 999 ravb_set_rate(ndev); 1000 } 1001 if (!priv->link) { 1002 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1003 new_state = true; 1004 priv->link = phydev->link; 1005 } 1006 } else if (priv->link) { 1007 new_state = true; 1008 priv->link = 0; 1009 priv->speed = 0; 1010 priv->duplex = -1; 1011 } 1012 1013 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1014 if (priv->no_avb_link && phydev->link) 1015 ravb_rcv_snd_enable(ndev); 1016 1017 mmiowb(); 1018 spin_unlock_irqrestore(&priv->lock, flags); 1019 1020 if (new_state && netif_msg_link(priv)) 1021 phy_print_status(phydev); 1022 } 1023 1024 static const struct soc_device_attribute r8a7795es10[] = { 1025 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1026 { /* sentinel */ } 1027 }; 1028 1029 /* PHY init function */ 1030 static int ravb_phy_init(struct net_device *ndev) 1031 { 1032 struct device_node *np = ndev->dev.parent->of_node; 1033 struct ravb_private *priv = netdev_priv(ndev); 1034 struct phy_device *phydev; 1035 struct device_node *pn; 1036 int err; 1037 1038 priv->link = 0; 1039 priv->speed = 0; 1040 priv->duplex = -1; 1041 1042 /* Try connecting to PHY */ 1043 pn = of_parse_phandle(np, "phy-handle", 0); 1044 if (!pn) { 1045 /* In the case of a fixed PHY, the DT node associated 1046 * to the PHY is the Ethernet MAC DT node. 1047 */ 1048 if (of_phy_is_fixed_link(np)) { 1049 err = of_phy_register_fixed_link(np); 1050 if (err) 1051 return err; 1052 } 1053 pn = of_node_get(np); 1054 } 1055 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1056 priv->phy_interface); 1057 of_node_put(pn); 1058 if (!phydev) { 1059 netdev_err(ndev, "failed to connect PHY\n"); 1060 err = -ENOENT; 1061 goto err_deregister_fixed_link; 1062 } 1063 1064 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1065 * at this time. 1066 */ 1067 if (soc_device_match(r8a7795es10)) { 1068 err = phy_set_max_speed(phydev, SPEED_100); 1069 if (err) { 1070 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1071 goto err_phy_disconnect; 1072 } 1073 1074 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1075 } 1076 1077 /* 10BASE is not supported */ 1078 phydev->supported &= ~PHY_10BT_FEATURES; 1079 1080 phy_attached_info(phydev); 1081 1082 return 0; 1083 1084 err_phy_disconnect: 1085 phy_disconnect(phydev); 1086 err_deregister_fixed_link: 1087 if (of_phy_is_fixed_link(np)) 1088 of_phy_deregister_fixed_link(np); 1089 1090 return err; 1091 } 1092 1093 /* PHY control start function */ 1094 static int ravb_phy_start(struct net_device *ndev) 1095 { 1096 int error; 1097 1098 error = ravb_phy_init(ndev); 1099 if (error) 1100 return error; 1101 1102 phy_start(ndev->phydev); 1103 1104 return 0; 1105 } 1106 1107 static u32 ravb_get_msglevel(struct net_device *ndev) 1108 { 1109 struct ravb_private *priv = netdev_priv(ndev); 1110 1111 return priv->msg_enable; 1112 } 1113 1114 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1115 { 1116 struct ravb_private *priv = netdev_priv(ndev); 1117 1118 priv->msg_enable = value; 1119 } 1120 1121 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1122 "rx_queue_0_current", 1123 "tx_queue_0_current", 1124 "rx_queue_0_dirty", 1125 "tx_queue_0_dirty", 1126 "rx_queue_0_packets", 1127 "tx_queue_0_packets", 1128 "rx_queue_0_bytes", 1129 "tx_queue_0_bytes", 1130 "rx_queue_0_mcast_packets", 1131 "rx_queue_0_errors", 1132 "rx_queue_0_crc_errors", 1133 "rx_queue_0_frame_errors", 1134 "rx_queue_0_length_errors", 1135 "rx_queue_0_missed_errors", 1136 "rx_queue_0_over_errors", 1137 1138 "rx_queue_1_current", 1139 "tx_queue_1_current", 1140 "rx_queue_1_dirty", 1141 "tx_queue_1_dirty", 1142 "rx_queue_1_packets", 1143 "tx_queue_1_packets", 1144 "rx_queue_1_bytes", 1145 "tx_queue_1_bytes", 1146 "rx_queue_1_mcast_packets", 1147 "rx_queue_1_errors", 1148 "rx_queue_1_crc_errors", 1149 "rx_queue_1_frame_errors", 1150 "rx_queue_1_length_errors", 1151 "rx_queue_1_missed_errors", 1152 "rx_queue_1_over_errors", 1153 }; 1154 1155 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1156 1157 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1158 { 1159 switch (sset) { 1160 case ETH_SS_STATS: 1161 return RAVB_STATS_LEN; 1162 default: 1163 return -EOPNOTSUPP; 1164 } 1165 } 1166 1167 static void ravb_get_ethtool_stats(struct net_device *ndev, 1168 struct ethtool_stats *estats, u64 *data) 1169 { 1170 struct ravb_private *priv = netdev_priv(ndev); 1171 int i = 0; 1172 int q; 1173 1174 /* Device-specific stats */ 1175 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1176 struct net_device_stats *stats = &priv->stats[q]; 1177 1178 data[i++] = priv->cur_rx[q]; 1179 data[i++] = priv->cur_tx[q]; 1180 data[i++] = priv->dirty_rx[q]; 1181 data[i++] = priv->dirty_tx[q]; 1182 data[i++] = stats->rx_packets; 1183 data[i++] = stats->tx_packets; 1184 data[i++] = stats->rx_bytes; 1185 data[i++] = stats->tx_bytes; 1186 data[i++] = stats->multicast; 1187 data[i++] = stats->rx_errors; 1188 data[i++] = stats->rx_crc_errors; 1189 data[i++] = stats->rx_frame_errors; 1190 data[i++] = stats->rx_length_errors; 1191 data[i++] = stats->rx_missed_errors; 1192 data[i++] = stats->rx_over_errors; 1193 } 1194 } 1195 1196 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1197 { 1198 switch (stringset) { 1199 case ETH_SS_STATS: 1200 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1201 break; 1202 } 1203 } 1204 1205 static void ravb_get_ringparam(struct net_device *ndev, 1206 struct ethtool_ringparam *ring) 1207 { 1208 struct ravb_private *priv = netdev_priv(ndev); 1209 1210 ring->rx_max_pending = BE_RX_RING_MAX; 1211 ring->tx_max_pending = BE_TX_RING_MAX; 1212 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1213 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1214 } 1215 1216 static int ravb_set_ringparam(struct net_device *ndev, 1217 struct ethtool_ringparam *ring) 1218 { 1219 struct ravb_private *priv = netdev_priv(ndev); 1220 int error; 1221 1222 if (ring->tx_pending > BE_TX_RING_MAX || 1223 ring->rx_pending > BE_RX_RING_MAX || 1224 ring->tx_pending < BE_TX_RING_MIN || 1225 ring->rx_pending < BE_RX_RING_MIN) 1226 return -EINVAL; 1227 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1228 return -EINVAL; 1229 1230 if (netif_running(ndev)) { 1231 netif_device_detach(ndev); 1232 /* Stop PTP Clock driver */ 1233 if (priv->chip_id == RCAR_GEN2) 1234 ravb_ptp_stop(ndev); 1235 /* Wait for DMA stopping */ 1236 error = ravb_stop_dma(ndev); 1237 if (error) { 1238 netdev_err(ndev, 1239 "cannot set ringparam! Any AVB processes are still running?\n"); 1240 return error; 1241 } 1242 synchronize_irq(ndev->irq); 1243 1244 /* Free all the skb's in the RX queue and the DMA buffers. */ 1245 ravb_ring_free(ndev, RAVB_BE); 1246 ravb_ring_free(ndev, RAVB_NC); 1247 } 1248 1249 /* Set new parameters */ 1250 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1251 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1252 1253 if (netif_running(ndev)) { 1254 error = ravb_dmac_init(ndev); 1255 if (error) { 1256 netdev_err(ndev, 1257 "%s: ravb_dmac_init() failed, error %d\n", 1258 __func__, error); 1259 return error; 1260 } 1261 1262 ravb_emac_init(ndev); 1263 1264 /* Initialise PTP Clock driver */ 1265 if (priv->chip_id == RCAR_GEN2) 1266 ravb_ptp_init(ndev, priv->pdev); 1267 1268 netif_device_attach(ndev); 1269 } 1270 1271 return 0; 1272 } 1273 1274 static int ravb_get_ts_info(struct net_device *ndev, 1275 struct ethtool_ts_info *info) 1276 { 1277 struct ravb_private *priv = netdev_priv(ndev); 1278 1279 info->so_timestamping = 1280 SOF_TIMESTAMPING_TX_SOFTWARE | 1281 SOF_TIMESTAMPING_RX_SOFTWARE | 1282 SOF_TIMESTAMPING_SOFTWARE | 1283 SOF_TIMESTAMPING_TX_HARDWARE | 1284 SOF_TIMESTAMPING_RX_HARDWARE | 1285 SOF_TIMESTAMPING_RAW_HARDWARE; 1286 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1287 info->rx_filters = 1288 (1 << HWTSTAMP_FILTER_NONE) | 1289 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1290 (1 << HWTSTAMP_FILTER_ALL); 1291 info->phc_index = ptp_clock_index(priv->ptp.clock); 1292 1293 return 0; 1294 } 1295 1296 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1297 { 1298 struct ravb_private *priv = netdev_priv(ndev); 1299 1300 wol->supported = WAKE_MAGIC; 1301 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1302 } 1303 1304 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1305 { 1306 struct ravb_private *priv = netdev_priv(ndev); 1307 1308 if (wol->wolopts & ~WAKE_MAGIC) 1309 return -EOPNOTSUPP; 1310 1311 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1312 1313 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1314 1315 return 0; 1316 } 1317 1318 static const struct ethtool_ops ravb_ethtool_ops = { 1319 .nway_reset = phy_ethtool_nway_reset, 1320 .get_msglevel = ravb_get_msglevel, 1321 .set_msglevel = ravb_set_msglevel, 1322 .get_link = ethtool_op_get_link, 1323 .get_strings = ravb_get_strings, 1324 .get_ethtool_stats = ravb_get_ethtool_stats, 1325 .get_sset_count = ravb_get_sset_count, 1326 .get_ringparam = ravb_get_ringparam, 1327 .set_ringparam = ravb_set_ringparam, 1328 .get_ts_info = ravb_get_ts_info, 1329 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1330 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1331 .get_wol = ravb_get_wol, 1332 .set_wol = ravb_set_wol, 1333 }; 1334 1335 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1336 struct net_device *ndev, struct device *dev, 1337 const char *ch) 1338 { 1339 char *name; 1340 int error; 1341 1342 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1343 if (!name) 1344 return -ENOMEM; 1345 error = request_irq(irq, handler, 0, name, ndev); 1346 if (error) 1347 netdev_err(ndev, "cannot request IRQ %s\n", name); 1348 1349 return error; 1350 } 1351 1352 /* Network device open function for Ethernet AVB */ 1353 static int ravb_open(struct net_device *ndev) 1354 { 1355 struct ravb_private *priv = netdev_priv(ndev); 1356 struct platform_device *pdev = priv->pdev; 1357 struct device *dev = &pdev->dev; 1358 int error; 1359 1360 napi_enable(&priv->napi[RAVB_BE]); 1361 napi_enable(&priv->napi[RAVB_NC]); 1362 1363 if (priv->chip_id == RCAR_GEN2) { 1364 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1365 ndev->name, ndev); 1366 if (error) { 1367 netdev_err(ndev, "cannot request IRQ\n"); 1368 goto out_napi_off; 1369 } 1370 } else { 1371 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1372 dev, "ch22:multi"); 1373 if (error) 1374 goto out_napi_off; 1375 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1376 dev, "ch24:emac"); 1377 if (error) 1378 goto out_free_irq; 1379 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1380 ndev, dev, "ch0:rx_be"); 1381 if (error) 1382 goto out_free_irq_emac; 1383 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1384 ndev, dev, "ch18:tx_be"); 1385 if (error) 1386 goto out_free_irq_be_rx; 1387 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1388 ndev, dev, "ch1:rx_nc"); 1389 if (error) 1390 goto out_free_irq_be_tx; 1391 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1392 ndev, dev, "ch19:tx_nc"); 1393 if (error) 1394 goto out_free_irq_nc_rx; 1395 } 1396 1397 /* Device init */ 1398 error = ravb_dmac_init(ndev); 1399 if (error) 1400 goto out_free_irq_nc_tx; 1401 ravb_emac_init(ndev); 1402 1403 /* Initialise PTP Clock driver */ 1404 if (priv->chip_id == RCAR_GEN2) 1405 ravb_ptp_init(ndev, priv->pdev); 1406 1407 netif_tx_start_all_queues(ndev); 1408 1409 /* PHY control start */ 1410 error = ravb_phy_start(ndev); 1411 if (error) 1412 goto out_ptp_stop; 1413 1414 return 0; 1415 1416 out_ptp_stop: 1417 /* Stop PTP Clock driver */ 1418 if (priv->chip_id == RCAR_GEN2) 1419 ravb_ptp_stop(ndev); 1420 out_free_irq_nc_tx: 1421 if (priv->chip_id == RCAR_GEN2) 1422 goto out_free_irq; 1423 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1424 out_free_irq_nc_rx: 1425 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1426 out_free_irq_be_tx: 1427 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1428 out_free_irq_be_rx: 1429 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1430 out_free_irq_emac: 1431 free_irq(priv->emac_irq, ndev); 1432 out_free_irq: 1433 free_irq(ndev->irq, ndev); 1434 out_napi_off: 1435 napi_disable(&priv->napi[RAVB_NC]); 1436 napi_disable(&priv->napi[RAVB_BE]); 1437 return error; 1438 } 1439 1440 /* Timeout function for Ethernet AVB */ 1441 static void ravb_tx_timeout(struct net_device *ndev) 1442 { 1443 struct ravb_private *priv = netdev_priv(ndev); 1444 1445 netif_err(priv, tx_err, ndev, 1446 "transmit timed out, status %08x, resetting...\n", 1447 ravb_read(ndev, ISS)); 1448 1449 /* tx_errors count up */ 1450 ndev->stats.tx_errors++; 1451 1452 schedule_work(&priv->work); 1453 } 1454 1455 static void ravb_tx_timeout_work(struct work_struct *work) 1456 { 1457 struct ravb_private *priv = container_of(work, struct ravb_private, 1458 work); 1459 struct net_device *ndev = priv->ndev; 1460 1461 netif_tx_stop_all_queues(ndev); 1462 1463 /* Stop PTP Clock driver */ 1464 if (priv->chip_id == RCAR_GEN2) 1465 ravb_ptp_stop(ndev); 1466 1467 /* Wait for DMA stopping */ 1468 ravb_stop_dma(ndev); 1469 1470 ravb_ring_free(ndev, RAVB_BE); 1471 ravb_ring_free(ndev, RAVB_NC); 1472 1473 /* Device init */ 1474 ravb_dmac_init(ndev); 1475 ravb_emac_init(ndev); 1476 1477 /* Initialise PTP Clock driver */ 1478 if (priv->chip_id == RCAR_GEN2) 1479 ravb_ptp_init(ndev, priv->pdev); 1480 1481 netif_tx_start_all_queues(ndev); 1482 } 1483 1484 /* Packet transmit function for Ethernet AVB */ 1485 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1486 { 1487 struct ravb_private *priv = netdev_priv(ndev); 1488 u16 q = skb_get_queue_mapping(skb); 1489 struct ravb_tstamp_skb *ts_skb; 1490 struct ravb_tx_desc *desc; 1491 unsigned long flags; 1492 u32 dma_addr; 1493 void *buffer; 1494 u32 entry; 1495 u32 len; 1496 1497 spin_lock_irqsave(&priv->lock, flags); 1498 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1499 NUM_TX_DESC) { 1500 netif_err(priv, tx_queued, ndev, 1501 "still transmitting with the full ring!\n"); 1502 netif_stop_subqueue(ndev, q); 1503 spin_unlock_irqrestore(&priv->lock, flags); 1504 return NETDEV_TX_BUSY; 1505 } 1506 1507 if (skb_put_padto(skb, ETH_ZLEN)) 1508 goto exit; 1509 1510 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1511 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1512 1513 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1514 entry / NUM_TX_DESC * DPTR_ALIGN; 1515 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1516 /* Zero length DMA descriptors are problematic as they seem to 1517 * terminate DMA transfers. Avoid them by simply using a length of 1518 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN. 1519 * 1520 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of 1521 * data by the call to skb_put_padto() above this is safe with 1522 * respect to both the length of the first DMA descriptor (len) 1523 * overflowing the available data and the length of the second DMA 1524 * descriptor (skb->len - len) being negative. 1525 */ 1526 if (len == 0) 1527 len = DPTR_ALIGN; 1528 1529 memcpy(buffer, skb->data, len); 1530 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1531 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1532 goto drop; 1533 1534 desc = &priv->tx_ring[q][entry]; 1535 desc->ds_tagl = cpu_to_le16(len); 1536 desc->dptr = cpu_to_le32(dma_addr); 1537 1538 buffer = skb->data + len; 1539 len = skb->len - len; 1540 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1541 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1542 goto unmap; 1543 1544 desc++; 1545 desc->ds_tagl = cpu_to_le16(len); 1546 desc->dptr = cpu_to_le32(dma_addr); 1547 1548 /* TX timestamp required */ 1549 if (q == RAVB_NC) { 1550 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1551 if (!ts_skb) { 1552 desc--; 1553 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1554 DMA_TO_DEVICE); 1555 goto unmap; 1556 } 1557 ts_skb->skb = skb; 1558 ts_skb->tag = priv->ts_skb_tag++; 1559 priv->ts_skb_tag &= 0x3ff; 1560 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1561 1562 /* TAG and timestamp required flag */ 1563 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1564 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1565 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1566 } 1567 1568 skb_tx_timestamp(skb); 1569 /* Descriptor type must be set after all the above writes */ 1570 dma_wmb(); 1571 desc->die_dt = DT_FEND; 1572 desc--; 1573 desc->die_dt = DT_FSTART; 1574 1575 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1576 1577 priv->cur_tx[q] += NUM_TX_DESC; 1578 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1579 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && 1580 !ravb_tx_free(ndev, q, true)) 1581 netif_stop_subqueue(ndev, q); 1582 1583 exit: 1584 mmiowb(); 1585 spin_unlock_irqrestore(&priv->lock, flags); 1586 return NETDEV_TX_OK; 1587 1588 unmap: 1589 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1590 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1591 drop: 1592 dev_kfree_skb_any(skb); 1593 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1594 goto exit; 1595 } 1596 1597 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1598 struct net_device *sb_dev, 1599 select_queue_fallback_t fallback) 1600 { 1601 /* If skb needs TX timestamp, it is handled in network control queue */ 1602 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1603 RAVB_BE; 1604 1605 } 1606 1607 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1608 { 1609 struct ravb_private *priv = netdev_priv(ndev); 1610 struct net_device_stats *nstats, *stats0, *stats1; 1611 1612 nstats = &ndev->stats; 1613 stats0 = &priv->stats[RAVB_BE]; 1614 stats1 = &priv->stats[RAVB_NC]; 1615 1616 nstats->tx_dropped += ravb_read(ndev, TROCR); 1617 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1618 nstats->collisions += ravb_read(ndev, CDCR); 1619 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1620 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1621 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1622 1623 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1624 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1625 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1626 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1627 1628 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1629 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1630 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1631 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1632 nstats->multicast = stats0->multicast + stats1->multicast; 1633 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1634 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1635 nstats->rx_frame_errors = 1636 stats0->rx_frame_errors + stats1->rx_frame_errors; 1637 nstats->rx_length_errors = 1638 stats0->rx_length_errors + stats1->rx_length_errors; 1639 nstats->rx_missed_errors = 1640 stats0->rx_missed_errors + stats1->rx_missed_errors; 1641 nstats->rx_over_errors = 1642 stats0->rx_over_errors + stats1->rx_over_errors; 1643 1644 return nstats; 1645 } 1646 1647 /* Update promiscuous bit */ 1648 static void ravb_set_rx_mode(struct net_device *ndev) 1649 { 1650 struct ravb_private *priv = netdev_priv(ndev); 1651 unsigned long flags; 1652 1653 spin_lock_irqsave(&priv->lock, flags); 1654 ravb_modify(ndev, ECMR, ECMR_PRM, 1655 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1656 mmiowb(); 1657 spin_unlock_irqrestore(&priv->lock, flags); 1658 } 1659 1660 /* Device close function for Ethernet AVB */ 1661 static int ravb_close(struct net_device *ndev) 1662 { 1663 struct device_node *np = ndev->dev.parent->of_node; 1664 struct ravb_private *priv = netdev_priv(ndev); 1665 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1666 1667 netif_tx_stop_all_queues(ndev); 1668 1669 /* Disable interrupts by clearing the interrupt masks. */ 1670 ravb_write(ndev, 0, RIC0); 1671 ravb_write(ndev, 0, RIC2); 1672 ravb_write(ndev, 0, TIC); 1673 1674 /* Stop PTP Clock driver */ 1675 if (priv->chip_id == RCAR_GEN2) 1676 ravb_ptp_stop(ndev); 1677 1678 /* Set the config mode to stop the AVB-DMAC's processes */ 1679 if (ravb_stop_dma(ndev) < 0) 1680 netdev_err(ndev, 1681 "device will be stopped after h/w processes are done.\n"); 1682 1683 /* Clear the timestamp list */ 1684 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1685 list_del(&ts_skb->list); 1686 kfree(ts_skb); 1687 } 1688 1689 /* PHY disconnect */ 1690 if (ndev->phydev) { 1691 phy_stop(ndev->phydev); 1692 phy_disconnect(ndev->phydev); 1693 if (of_phy_is_fixed_link(np)) 1694 of_phy_deregister_fixed_link(np); 1695 } 1696 1697 if (priv->chip_id != RCAR_GEN2) { 1698 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1699 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1700 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1701 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1702 free_irq(priv->emac_irq, ndev); 1703 } 1704 free_irq(ndev->irq, ndev); 1705 1706 napi_disable(&priv->napi[RAVB_NC]); 1707 napi_disable(&priv->napi[RAVB_BE]); 1708 1709 /* Free all the skb's in the RX queue and the DMA buffers. */ 1710 ravb_ring_free(ndev, RAVB_BE); 1711 ravb_ring_free(ndev, RAVB_NC); 1712 1713 return 0; 1714 } 1715 1716 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1717 { 1718 struct ravb_private *priv = netdev_priv(ndev); 1719 struct hwtstamp_config config; 1720 1721 config.flags = 0; 1722 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1723 HWTSTAMP_TX_OFF; 1724 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1725 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1726 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1727 config.rx_filter = HWTSTAMP_FILTER_ALL; 1728 else 1729 config.rx_filter = HWTSTAMP_FILTER_NONE; 1730 1731 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1732 -EFAULT : 0; 1733 } 1734 1735 /* Control hardware time stamping */ 1736 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1737 { 1738 struct ravb_private *priv = netdev_priv(ndev); 1739 struct hwtstamp_config config; 1740 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1741 u32 tstamp_tx_ctrl; 1742 1743 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1744 return -EFAULT; 1745 1746 /* Reserved for future extensions */ 1747 if (config.flags) 1748 return -EINVAL; 1749 1750 switch (config.tx_type) { 1751 case HWTSTAMP_TX_OFF: 1752 tstamp_tx_ctrl = 0; 1753 break; 1754 case HWTSTAMP_TX_ON: 1755 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1756 break; 1757 default: 1758 return -ERANGE; 1759 } 1760 1761 switch (config.rx_filter) { 1762 case HWTSTAMP_FILTER_NONE: 1763 tstamp_rx_ctrl = 0; 1764 break; 1765 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1766 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1767 break; 1768 default: 1769 config.rx_filter = HWTSTAMP_FILTER_ALL; 1770 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1771 } 1772 1773 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1774 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1775 1776 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1777 -EFAULT : 0; 1778 } 1779 1780 /* ioctl to device function */ 1781 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1782 { 1783 struct phy_device *phydev = ndev->phydev; 1784 1785 if (!netif_running(ndev)) 1786 return -EINVAL; 1787 1788 if (!phydev) 1789 return -ENODEV; 1790 1791 switch (cmd) { 1792 case SIOCGHWTSTAMP: 1793 return ravb_hwtstamp_get(ndev, req); 1794 case SIOCSHWTSTAMP: 1795 return ravb_hwtstamp_set(ndev, req); 1796 } 1797 1798 return phy_mii_ioctl(phydev, req, cmd); 1799 } 1800 1801 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1802 { 1803 if (netif_running(ndev)) 1804 return -EBUSY; 1805 1806 ndev->mtu = new_mtu; 1807 netdev_update_features(ndev); 1808 1809 return 0; 1810 } 1811 1812 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1813 { 1814 struct ravb_private *priv = netdev_priv(ndev); 1815 unsigned long flags; 1816 1817 spin_lock_irqsave(&priv->lock, flags); 1818 1819 /* Disable TX and RX */ 1820 ravb_rcv_snd_disable(ndev); 1821 1822 /* Modify RX Checksum setting */ 1823 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1824 1825 /* Enable TX and RX */ 1826 ravb_rcv_snd_enable(ndev); 1827 1828 spin_unlock_irqrestore(&priv->lock, flags); 1829 } 1830 1831 static int ravb_set_features(struct net_device *ndev, 1832 netdev_features_t features) 1833 { 1834 netdev_features_t changed = ndev->features ^ features; 1835 1836 if (changed & NETIF_F_RXCSUM) 1837 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1838 1839 ndev->features = features; 1840 1841 return 0; 1842 } 1843 1844 static const struct net_device_ops ravb_netdev_ops = { 1845 .ndo_open = ravb_open, 1846 .ndo_stop = ravb_close, 1847 .ndo_start_xmit = ravb_start_xmit, 1848 .ndo_select_queue = ravb_select_queue, 1849 .ndo_get_stats = ravb_get_stats, 1850 .ndo_set_rx_mode = ravb_set_rx_mode, 1851 .ndo_tx_timeout = ravb_tx_timeout, 1852 .ndo_do_ioctl = ravb_do_ioctl, 1853 .ndo_change_mtu = ravb_change_mtu, 1854 .ndo_validate_addr = eth_validate_addr, 1855 .ndo_set_mac_address = eth_mac_addr, 1856 .ndo_set_features = ravb_set_features, 1857 }; 1858 1859 /* MDIO bus init function */ 1860 static int ravb_mdio_init(struct ravb_private *priv) 1861 { 1862 struct platform_device *pdev = priv->pdev; 1863 struct device *dev = &pdev->dev; 1864 int error; 1865 1866 /* Bitbang init */ 1867 priv->mdiobb.ops = &bb_ops; 1868 1869 /* MII controller setting */ 1870 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1871 if (!priv->mii_bus) 1872 return -ENOMEM; 1873 1874 /* Hook up MII support for ethtool */ 1875 priv->mii_bus->name = "ravb_mii"; 1876 priv->mii_bus->parent = dev; 1877 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1878 pdev->name, pdev->id); 1879 1880 /* Register MDIO bus */ 1881 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1882 if (error) 1883 goto out_free_bus; 1884 1885 return 0; 1886 1887 out_free_bus: 1888 free_mdio_bitbang(priv->mii_bus); 1889 return error; 1890 } 1891 1892 /* MDIO bus release function */ 1893 static int ravb_mdio_release(struct ravb_private *priv) 1894 { 1895 /* Unregister mdio bus */ 1896 mdiobus_unregister(priv->mii_bus); 1897 1898 /* Free bitbang info */ 1899 free_mdio_bitbang(priv->mii_bus); 1900 1901 return 0; 1902 } 1903 1904 static const struct of_device_id ravb_match_table[] = { 1905 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1906 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1907 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1908 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1909 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1910 { } 1911 }; 1912 MODULE_DEVICE_TABLE(of, ravb_match_table); 1913 1914 static int ravb_set_gti(struct net_device *ndev) 1915 { 1916 struct ravb_private *priv = netdev_priv(ndev); 1917 struct device *dev = ndev->dev.parent; 1918 unsigned long rate; 1919 uint64_t inc; 1920 1921 rate = clk_get_rate(priv->clk); 1922 if (!rate) 1923 return -EINVAL; 1924 1925 inc = 1000000000ULL << 20; 1926 do_div(inc, rate); 1927 1928 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1929 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1930 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1931 return -EINVAL; 1932 } 1933 1934 ravb_write(ndev, inc, GTI); 1935 1936 return 0; 1937 } 1938 1939 static void ravb_set_config_mode(struct net_device *ndev) 1940 { 1941 struct ravb_private *priv = netdev_priv(ndev); 1942 1943 if (priv->chip_id == RCAR_GEN2) { 1944 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1945 /* Set CSEL value */ 1946 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1947 } else { 1948 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1949 CCC_GAC | CCC_CSEL_HPB); 1950 } 1951 } 1952 1953 /* Set tx and rx clock internal delay modes */ 1954 static void ravb_set_delay_mode(struct net_device *ndev) 1955 { 1956 struct ravb_private *priv = netdev_priv(ndev); 1957 int set = 0; 1958 1959 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1960 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1961 set |= APSR_DM_RDM; 1962 1963 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1964 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1965 set |= APSR_DM_TDM; 1966 1967 ravb_modify(ndev, APSR, APSR_DM, set); 1968 } 1969 1970 static int ravb_probe(struct platform_device *pdev) 1971 { 1972 struct device_node *np = pdev->dev.of_node; 1973 struct ravb_private *priv; 1974 enum ravb_chip_id chip_id; 1975 struct net_device *ndev; 1976 int error, irq, q; 1977 struct resource *res; 1978 int i; 1979 1980 if (!np) { 1981 dev_err(&pdev->dev, 1982 "this driver is required to be instantiated from device tree\n"); 1983 return -EINVAL; 1984 } 1985 1986 /* Get base address */ 1987 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1988 if (!res) { 1989 dev_err(&pdev->dev, "invalid resource\n"); 1990 return -EINVAL; 1991 } 1992 1993 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 1994 NUM_TX_QUEUE, NUM_RX_QUEUE); 1995 if (!ndev) 1996 return -ENOMEM; 1997 1998 ndev->features = NETIF_F_RXCSUM; 1999 ndev->hw_features = NETIF_F_RXCSUM; 2000 2001 pm_runtime_enable(&pdev->dev); 2002 pm_runtime_get_sync(&pdev->dev); 2003 2004 /* The Ether-specific entries in the device structure. */ 2005 ndev->base_addr = res->start; 2006 2007 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2008 2009 if (chip_id == RCAR_GEN3) 2010 irq = platform_get_irq_byname(pdev, "ch22"); 2011 else 2012 irq = platform_get_irq(pdev, 0); 2013 if (irq < 0) { 2014 error = irq; 2015 goto out_release; 2016 } 2017 ndev->irq = irq; 2018 2019 SET_NETDEV_DEV(ndev, &pdev->dev); 2020 2021 priv = netdev_priv(ndev); 2022 priv->ndev = ndev; 2023 priv->pdev = pdev; 2024 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2025 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2026 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2027 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2028 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2029 if (IS_ERR(priv->addr)) { 2030 error = PTR_ERR(priv->addr); 2031 goto out_release; 2032 } 2033 2034 spin_lock_init(&priv->lock); 2035 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2036 2037 priv->phy_interface = of_get_phy_mode(np); 2038 2039 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2040 priv->avb_link_active_low = 2041 of_property_read_bool(np, "renesas,ether-link-active-low"); 2042 2043 if (chip_id == RCAR_GEN3) { 2044 irq = platform_get_irq_byname(pdev, "ch24"); 2045 if (irq < 0) { 2046 error = irq; 2047 goto out_release; 2048 } 2049 priv->emac_irq = irq; 2050 for (i = 0; i < NUM_RX_QUEUE; i++) { 2051 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2052 if (irq < 0) { 2053 error = irq; 2054 goto out_release; 2055 } 2056 priv->rx_irqs[i] = irq; 2057 } 2058 for (i = 0; i < NUM_TX_QUEUE; i++) { 2059 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2060 if (irq < 0) { 2061 error = irq; 2062 goto out_release; 2063 } 2064 priv->tx_irqs[i] = irq; 2065 } 2066 } 2067 2068 priv->chip_id = chip_id; 2069 2070 priv->clk = devm_clk_get(&pdev->dev, NULL); 2071 if (IS_ERR(priv->clk)) { 2072 error = PTR_ERR(priv->clk); 2073 goto out_release; 2074 } 2075 2076 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2077 ndev->min_mtu = ETH_MIN_MTU; 2078 2079 /* Set function */ 2080 ndev->netdev_ops = &ravb_netdev_ops; 2081 ndev->ethtool_ops = &ravb_ethtool_ops; 2082 2083 /* Set AVB config mode */ 2084 ravb_set_config_mode(ndev); 2085 2086 /* Set GTI value */ 2087 error = ravb_set_gti(ndev); 2088 if (error) 2089 goto out_release; 2090 2091 /* Request GTI loading */ 2092 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2093 2094 if (priv->chip_id != RCAR_GEN2) 2095 ravb_set_delay_mode(ndev); 2096 2097 /* Allocate descriptor base address table */ 2098 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2099 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2100 &priv->desc_bat_dma, GFP_KERNEL); 2101 if (!priv->desc_bat) { 2102 dev_err(&pdev->dev, 2103 "Cannot allocate desc base address table (size %d bytes)\n", 2104 priv->desc_bat_size); 2105 error = -ENOMEM; 2106 goto out_release; 2107 } 2108 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2109 priv->desc_bat[q].die_dt = DT_EOS; 2110 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2111 2112 /* Initialise HW timestamp list */ 2113 INIT_LIST_HEAD(&priv->ts_skb_list); 2114 2115 /* Initialise PTP Clock driver */ 2116 if (chip_id != RCAR_GEN2) 2117 ravb_ptp_init(ndev, pdev); 2118 2119 /* Debug message level */ 2120 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2121 2122 /* Read and set MAC address */ 2123 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2124 if (!is_valid_ether_addr(ndev->dev_addr)) { 2125 dev_warn(&pdev->dev, 2126 "no valid MAC address supplied, using a random one\n"); 2127 eth_hw_addr_random(ndev); 2128 } 2129 2130 /* MDIO bus init */ 2131 error = ravb_mdio_init(priv); 2132 if (error) { 2133 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2134 goto out_dma_free; 2135 } 2136 2137 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2138 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2139 2140 /* Network device register */ 2141 error = register_netdev(ndev); 2142 if (error) 2143 goto out_napi_del; 2144 2145 device_set_wakeup_capable(&pdev->dev, 1); 2146 2147 /* Print device information */ 2148 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2149 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2150 2151 platform_set_drvdata(pdev, ndev); 2152 2153 return 0; 2154 2155 out_napi_del: 2156 netif_napi_del(&priv->napi[RAVB_NC]); 2157 netif_napi_del(&priv->napi[RAVB_BE]); 2158 ravb_mdio_release(priv); 2159 out_dma_free: 2160 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2161 priv->desc_bat_dma); 2162 2163 /* Stop PTP Clock driver */ 2164 if (chip_id != RCAR_GEN2) 2165 ravb_ptp_stop(ndev); 2166 out_release: 2167 free_netdev(ndev); 2168 2169 pm_runtime_put(&pdev->dev); 2170 pm_runtime_disable(&pdev->dev); 2171 return error; 2172 } 2173 2174 static int ravb_remove(struct platform_device *pdev) 2175 { 2176 struct net_device *ndev = platform_get_drvdata(pdev); 2177 struct ravb_private *priv = netdev_priv(ndev); 2178 2179 /* Stop PTP Clock driver */ 2180 if (priv->chip_id != RCAR_GEN2) 2181 ravb_ptp_stop(ndev); 2182 2183 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2184 priv->desc_bat_dma); 2185 /* Set reset mode */ 2186 ravb_write(ndev, CCC_OPC_RESET, CCC); 2187 pm_runtime_put_sync(&pdev->dev); 2188 unregister_netdev(ndev); 2189 netif_napi_del(&priv->napi[RAVB_NC]); 2190 netif_napi_del(&priv->napi[RAVB_BE]); 2191 ravb_mdio_release(priv); 2192 pm_runtime_disable(&pdev->dev); 2193 free_netdev(ndev); 2194 platform_set_drvdata(pdev, NULL); 2195 2196 return 0; 2197 } 2198 2199 static int ravb_wol_setup(struct net_device *ndev) 2200 { 2201 struct ravb_private *priv = netdev_priv(ndev); 2202 2203 /* Disable interrupts by clearing the interrupt masks. */ 2204 ravb_write(ndev, 0, RIC0); 2205 ravb_write(ndev, 0, RIC2); 2206 ravb_write(ndev, 0, TIC); 2207 2208 /* Only allow ECI interrupts */ 2209 synchronize_irq(priv->emac_irq); 2210 napi_disable(&priv->napi[RAVB_NC]); 2211 napi_disable(&priv->napi[RAVB_BE]); 2212 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2213 2214 /* Enable MagicPacket */ 2215 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2216 2217 return enable_irq_wake(priv->emac_irq); 2218 } 2219 2220 static int ravb_wol_restore(struct net_device *ndev) 2221 { 2222 struct ravb_private *priv = netdev_priv(ndev); 2223 int ret; 2224 2225 napi_enable(&priv->napi[RAVB_NC]); 2226 napi_enable(&priv->napi[RAVB_BE]); 2227 2228 /* Disable MagicPacket */ 2229 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2230 2231 ret = ravb_close(ndev); 2232 if (ret < 0) 2233 return ret; 2234 2235 return disable_irq_wake(priv->emac_irq); 2236 } 2237 2238 static int __maybe_unused ravb_suspend(struct device *dev) 2239 { 2240 struct net_device *ndev = dev_get_drvdata(dev); 2241 struct ravb_private *priv = netdev_priv(ndev); 2242 int ret; 2243 2244 if (!netif_running(ndev)) 2245 return 0; 2246 2247 netif_device_detach(ndev); 2248 2249 if (priv->wol_enabled) 2250 ret = ravb_wol_setup(ndev); 2251 else 2252 ret = ravb_close(ndev); 2253 2254 return ret; 2255 } 2256 2257 static int __maybe_unused ravb_resume(struct device *dev) 2258 { 2259 struct net_device *ndev = dev_get_drvdata(dev); 2260 struct ravb_private *priv = netdev_priv(ndev); 2261 int ret = 0; 2262 2263 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2264 if (priv->wol_enabled) 2265 ravb_write(ndev, CCC_OPC_RESET, CCC); 2266 2267 /* All register have been reset to default values. 2268 * Restore all registers which where setup at probe time and 2269 * reopen device if it was running before system suspended. 2270 */ 2271 2272 /* Set AVB config mode */ 2273 ravb_set_config_mode(ndev); 2274 2275 /* Set GTI value */ 2276 ret = ravb_set_gti(ndev); 2277 if (ret) 2278 return ret; 2279 2280 /* Request GTI loading */ 2281 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2282 2283 if (priv->chip_id != RCAR_GEN2) 2284 ravb_set_delay_mode(ndev); 2285 2286 /* Restore descriptor base address table */ 2287 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2288 2289 if (netif_running(ndev)) { 2290 if (priv->wol_enabled) { 2291 ret = ravb_wol_restore(ndev); 2292 if (ret) 2293 return ret; 2294 } 2295 ret = ravb_open(ndev); 2296 if (ret < 0) 2297 return ret; 2298 netif_device_attach(ndev); 2299 } 2300 2301 return ret; 2302 } 2303 2304 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2305 { 2306 /* Runtime PM callback shared between ->runtime_suspend() 2307 * and ->runtime_resume(). Simply returns success. 2308 * 2309 * This driver re-initializes all registers after 2310 * pm_runtime_get_sync() anyway so there is no need 2311 * to save and restore registers here. 2312 */ 2313 return 0; 2314 } 2315 2316 static const struct dev_pm_ops ravb_dev_pm_ops = { 2317 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2318 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2319 }; 2320 2321 static struct platform_driver ravb_driver = { 2322 .probe = ravb_probe, 2323 .remove = ravb_remove, 2324 .driver = { 2325 .name = "ravb", 2326 .pm = &ravb_dev_pm_ops, 2327 .of_match_table = ravb_match_table, 2328 }, 2329 }; 2330 2331 module_platform_driver(ravb_driver); 2332 2333 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2334 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2335 MODULE_LICENSE("GPL v2"); 2336