1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 33 #include <asm/div64.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46 }; 47 48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51 }; 52 53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55 { 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57 } 58 59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60 { 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69 } 70 71 static int ravb_config(struct net_device *ndev) 72 { 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83 } 84 85 static void ravb_set_duplex(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); 90 } 91 92 static void ravb_set_rate(struct net_device *ndev) 93 { 94 struct ravb_private *priv = netdev_priv(ndev); 95 96 switch (priv->speed) { 97 case 100: /* 100BASE */ 98 ravb_write(ndev, GECMR_SPEED_100, GECMR); 99 break; 100 case 1000: /* 1000BASE */ 101 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 102 break; 103 } 104 } 105 106 static void ravb_set_buffer_align(struct sk_buff *skb) 107 { 108 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 109 110 if (reserve) 111 skb_reserve(skb, RAVB_ALIGN - reserve); 112 } 113 114 /* Get MAC address from the MAC address registers 115 * 116 * Ethernet AVB device doesn't have ROM for MAC address. 117 * This function gets the MAC address that was used by a bootloader. 118 */ 119 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 120 { 121 if (mac) { 122 ether_addr_copy(ndev->dev_addr, mac); 123 } else { 124 u32 mahr = ravb_read(ndev, MAHR); 125 u32 malr = ravb_read(ndev, MALR); 126 127 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 128 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 129 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 130 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 131 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 132 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 133 } 134 } 135 136 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 137 { 138 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 139 mdiobb); 140 141 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 142 } 143 144 /* MDC pin control */ 145 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 146 { 147 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 148 } 149 150 /* Data I/O pin control */ 151 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 152 { 153 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 154 } 155 156 /* Set data bit */ 157 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 158 { 159 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 160 } 161 162 /* Get data bit */ 163 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 164 { 165 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 166 mdiobb); 167 168 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 169 } 170 171 /* MDIO bus control struct */ 172 static struct mdiobb_ops bb_ops = { 173 .owner = THIS_MODULE, 174 .set_mdc = ravb_set_mdc, 175 .set_mdio_dir = ravb_set_mdio_dir, 176 .set_mdio_data = ravb_set_mdio_data, 177 .get_mdio_data = ravb_get_mdio_data, 178 }; 179 180 /* Free TX skb function for AVB-IP */ 181 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 182 { 183 struct ravb_private *priv = netdev_priv(ndev); 184 struct net_device_stats *stats = &priv->stats[q]; 185 int num_tx_desc = priv->num_tx_desc; 186 struct ravb_tx_desc *desc; 187 int free_num = 0; 188 int entry; 189 u32 size; 190 191 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 192 bool txed; 193 194 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 195 num_tx_desc); 196 desc = &priv->tx_ring[q][entry]; 197 txed = desc->die_dt == DT_FEMPTY; 198 if (free_txed_only && !txed) 199 break; 200 /* Descriptor type must be checked before all other reads */ 201 dma_rmb(); 202 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 203 /* Free the original skb. */ 204 if (priv->tx_skb[q][entry / num_tx_desc]) { 205 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 206 size, DMA_TO_DEVICE); 207 /* Last packet descriptor? */ 208 if (entry % num_tx_desc == num_tx_desc - 1) { 209 entry /= num_tx_desc; 210 dev_kfree_skb_any(priv->tx_skb[q][entry]); 211 priv->tx_skb[q][entry] = NULL; 212 if (txed) 213 stats->tx_packets++; 214 } 215 free_num++; 216 } 217 if (txed) 218 stats->tx_bytes += size; 219 desc->die_dt = DT_EEMPTY; 220 } 221 return free_num; 222 } 223 224 /* Free skb's and DMA buffers for Ethernet AVB */ 225 static void ravb_ring_free(struct net_device *ndev, int q) 226 { 227 struct ravb_private *priv = netdev_priv(ndev); 228 int num_tx_desc = priv->num_tx_desc; 229 int ring_size; 230 int i; 231 232 if (priv->rx_ring[q]) { 233 for (i = 0; i < priv->num_rx_ring[q]; i++) { 234 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 235 236 if (!dma_mapping_error(ndev->dev.parent, 237 le32_to_cpu(desc->dptr))) 238 dma_unmap_single(ndev->dev.parent, 239 le32_to_cpu(desc->dptr), 240 priv->rx_buf_sz, 241 DMA_FROM_DEVICE); 242 } 243 ring_size = sizeof(struct ravb_ex_rx_desc) * 244 (priv->num_rx_ring[q] + 1); 245 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 246 priv->rx_desc_dma[q]); 247 priv->rx_ring[q] = NULL; 248 } 249 250 if (priv->tx_ring[q]) { 251 ravb_tx_free(ndev, q, false); 252 253 ring_size = sizeof(struct ravb_tx_desc) * 254 (priv->num_tx_ring[q] * num_tx_desc + 1); 255 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 256 priv->tx_desc_dma[q]); 257 priv->tx_ring[q] = NULL; 258 } 259 260 /* Free RX skb ringbuffer */ 261 if (priv->rx_skb[q]) { 262 for (i = 0; i < priv->num_rx_ring[q]; i++) 263 dev_kfree_skb(priv->rx_skb[q][i]); 264 } 265 kfree(priv->rx_skb[q]); 266 priv->rx_skb[q] = NULL; 267 268 /* Free aligned TX buffers */ 269 kfree(priv->tx_align[q]); 270 priv->tx_align[q] = NULL; 271 272 /* Free TX skb ringbuffer. 273 * SKBs are freed by ravb_tx_free() call above. 274 */ 275 kfree(priv->tx_skb[q]); 276 priv->tx_skb[q] = NULL; 277 } 278 279 /* Format skb and descriptor buffer for Ethernet AVB */ 280 static void ravb_ring_format(struct net_device *ndev, int q) 281 { 282 struct ravb_private *priv = netdev_priv(ndev); 283 int num_tx_desc = priv->num_tx_desc; 284 struct ravb_ex_rx_desc *rx_desc; 285 struct ravb_tx_desc *tx_desc; 286 struct ravb_desc *desc; 287 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 288 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 289 num_tx_desc; 290 dma_addr_t dma_addr; 291 int i; 292 293 priv->cur_rx[q] = 0; 294 priv->cur_tx[q] = 0; 295 priv->dirty_rx[q] = 0; 296 priv->dirty_tx[q] = 0; 297 298 memset(priv->rx_ring[q], 0, rx_ring_size); 299 /* Build RX ring buffer */ 300 for (i = 0; i < priv->num_rx_ring[q]; i++) { 301 /* RX descriptor */ 302 rx_desc = &priv->rx_ring[q][i]; 303 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 304 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 305 priv->rx_buf_sz, 306 DMA_FROM_DEVICE); 307 /* We just set the data size to 0 for a failed mapping which 308 * should prevent DMA from happening... 309 */ 310 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 311 rx_desc->ds_cc = cpu_to_le16(0); 312 rx_desc->dptr = cpu_to_le32(dma_addr); 313 rx_desc->die_dt = DT_FEMPTY; 314 } 315 rx_desc = &priv->rx_ring[q][i]; 316 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 317 rx_desc->die_dt = DT_LINKFIX; /* type */ 318 319 memset(priv->tx_ring[q], 0, tx_ring_size); 320 /* Build TX ring buffer */ 321 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 322 i++, tx_desc++) { 323 tx_desc->die_dt = DT_EEMPTY; 324 if (num_tx_desc > 1) { 325 tx_desc++; 326 tx_desc->die_dt = DT_EEMPTY; 327 } 328 } 329 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 330 tx_desc->die_dt = DT_LINKFIX; /* type */ 331 332 /* RX descriptor base address for best effort */ 333 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 334 desc->die_dt = DT_LINKFIX; /* type */ 335 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 336 337 /* TX descriptor base address for best effort */ 338 desc = &priv->desc_bat[q]; 339 desc->die_dt = DT_LINKFIX; /* type */ 340 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 341 } 342 343 /* Init skb and descriptor buffer for Ethernet AVB */ 344 static int ravb_ring_init(struct net_device *ndev, int q) 345 { 346 struct ravb_private *priv = netdev_priv(ndev); 347 int num_tx_desc = priv->num_tx_desc; 348 struct sk_buff *skb; 349 int ring_size; 350 int i; 351 352 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) + 353 ETH_HLEN + VLAN_HLEN; 354 355 /* Allocate RX and TX skb rings */ 356 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 357 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 358 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 359 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 360 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 361 goto error; 362 363 for (i = 0; i < priv->num_rx_ring[q]; i++) { 364 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1); 365 if (!skb) 366 goto error; 367 ravb_set_buffer_align(skb); 368 priv->rx_skb[q][i] = skb; 369 } 370 371 if (num_tx_desc > 1) { 372 /* Allocate rings for the aligned buffers */ 373 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 374 DPTR_ALIGN - 1, GFP_KERNEL); 375 if (!priv->tx_align[q]) 376 goto error; 377 } 378 379 /* Allocate all RX descriptors. */ 380 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 381 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 382 &priv->rx_desc_dma[q], 383 GFP_KERNEL); 384 if (!priv->rx_ring[q]) 385 goto error; 386 387 priv->dirty_rx[q] = 0; 388 389 /* Allocate all TX descriptors. */ 390 ring_size = sizeof(struct ravb_tx_desc) * 391 (priv->num_tx_ring[q] * num_tx_desc + 1); 392 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 393 &priv->tx_desc_dma[q], 394 GFP_KERNEL); 395 if (!priv->tx_ring[q]) 396 goto error; 397 398 return 0; 399 400 error: 401 ravb_ring_free(ndev, q); 402 403 return -ENOMEM; 404 } 405 406 /* E-MAC init function */ 407 static void ravb_emac_init(struct net_device *ndev) 408 { 409 struct ravb_private *priv = netdev_priv(ndev); 410 411 /* Receive frame limit set register */ 412 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 413 414 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 415 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 416 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 417 ECMR_TE | ECMR_RE, ECMR); 418 419 ravb_set_rate(ndev); 420 421 /* Set MAC address */ 422 ravb_write(ndev, 423 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 424 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 425 ravb_write(ndev, 426 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 427 428 /* E-MAC status register clear */ 429 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 430 431 /* E-MAC interrupt enable register */ 432 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 433 } 434 435 /* Device init function for Ethernet AVB */ 436 static int ravb_dmac_init(struct net_device *ndev) 437 { 438 struct ravb_private *priv = netdev_priv(ndev); 439 int error; 440 441 /* Set CONFIG mode */ 442 error = ravb_config(ndev); 443 if (error) 444 return error; 445 446 error = ravb_ring_init(ndev, RAVB_BE); 447 if (error) 448 return error; 449 error = ravb_ring_init(ndev, RAVB_NC); 450 if (error) { 451 ravb_ring_free(ndev, RAVB_BE); 452 return error; 453 } 454 455 /* Descriptor format */ 456 ravb_ring_format(ndev, RAVB_BE); 457 ravb_ring_format(ndev, RAVB_NC); 458 459 #if defined(__LITTLE_ENDIAN) 460 ravb_modify(ndev, CCC, CCC_BOC, 0); 461 #else 462 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 463 #endif 464 465 /* Set AVB RX */ 466 ravb_write(ndev, 467 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 468 469 /* Set FIFO size */ 470 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 471 472 /* Timestamp enable */ 473 ravb_write(ndev, TCCR_TFEN, TCCR); 474 475 /* Interrupt init: */ 476 if (priv->chip_id == RCAR_GEN3) { 477 /* Clear DIL.DPLx */ 478 ravb_write(ndev, 0, DIL); 479 /* Set queue specific interrupt */ 480 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 481 } 482 /* Frame receive */ 483 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 484 /* Disable FIFO full warning */ 485 ravb_write(ndev, 0, RIC1); 486 /* Receive FIFO full error, descriptor empty */ 487 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 488 /* Frame transmitted, timestamp FIFO updated */ 489 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 490 491 /* Setting the control will start the AVB-DMAC process. */ 492 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 493 494 return 0; 495 } 496 497 static void ravb_get_tx_tstamp(struct net_device *ndev) 498 { 499 struct ravb_private *priv = netdev_priv(ndev); 500 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 501 struct skb_shared_hwtstamps shhwtstamps; 502 struct sk_buff *skb; 503 struct timespec64 ts; 504 u16 tag, tfa_tag; 505 int count; 506 u32 tfa2; 507 508 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 509 while (count--) { 510 tfa2 = ravb_read(ndev, TFA2); 511 tfa_tag = (tfa2 & TFA2_TST) >> 16; 512 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 513 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 514 ravb_read(ndev, TFA1); 515 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 516 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 517 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 518 list) { 519 skb = ts_skb->skb; 520 tag = ts_skb->tag; 521 list_del(&ts_skb->list); 522 kfree(ts_skb); 523 if (tag == tfa_tag) { 524 skb_tstamp_tx(skb, &shhwtstamps); 525 break; 526 } 527 } 528 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 529 } 530 } 531 532 static void ravb_rx_csum(struct sk_buff *skb) 533 { 534 u8 *hw_csum; 535 536 /* The hardware checksum is 2 bytes appended to packet data */ 537 if (unlikely(skb->len < 2)) 538 return; 539 hw_csum = skb_tail_pointer(skb) - 2; 540 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 541 skb->ip_summed = CHECKSUM_COMPLETE; 542 skb_trim(skb, skb->len - 2); 543 } 544 545 /* Packet receive function for Ethernet AVB */ 546 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 547 { 548 struct ravb_private *priv = netdev_priv(ndev); 549 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 550 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 551 priv->cur_rx[q]; 552 struct net_device_stats *stats = &priv->stats[q]; 553 struct ravb_ex_rx_desc *desc; 554 struct sk_buff *skb; 555 dma_addr_t dma_addr; 556 struct timespec64 ts; 557 u8 desc_status; 558 u16 pkt_len; 559 int limit; 560 561 boguscnt = min(boguscnt, *quota); 562 limit = boguscnt; 563 desc = &priv->rx_ring[q][entry]; 564 while (desc->die_dt != DT_FEMPTY) { 565 /* Descriptor type must be checked before all other reads */ 566 dma_rmb(); 567 desc_status = desc->msc; 568 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 569 570 if (--boguscnt < 0) 571 break; 572 573 /* We use 0-byte descriptors to mark the DMA mapping errors */ 574 if (!pkt_len) 575 continue; 576 577 if (desc_status & MSC_MC) 578 stats->multicast++; 579 580 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 581 MSC_CEEF)) { 582 stats->rx_errors++; 583 if (desc_status & MSC_CRC) 584 stats->rx_crc_errors++; 585 if (desc_status & MSC_RFE) 586 stats->rx_frame_errors++; 587 if (desc_status & (MSC_RTLF | MSC_RTSF)) 588 stats->rx_length_errors++; 589 if (desc_status & MSC_CEEF) 590 stats->rx_missed_errors++; 591 } else { 592 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 593 594 skb = priv->rx_skb[q][entry]; 595 priv->rx_skb[q][entry] = NULL; 596 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 597 priv->rx_buf_sz, 598 DMA_FROM_DEVICE); 599 get_ts &= (q == RAVB_NC) ? 600 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 601 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 602 if (get_ts) { 603 struct skb_shared_hwtstamps *shhwtstamps; 604 605 shhwtstamps = skb_hwtstamps(skb); 606 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 607 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 608 32) | le32_to_cpu(desc->ts_sl); 609 ts.tv_nsec = le32_to_cpu(desc->ts_n); 610 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 611 } 612 613 skb_put(skb, pkt_len); 614 skb->protocol = eth_type_trans(skb, ndev); 615 if (ndev->features & NETIF_F_RXCSUM) 616 ravb_rx_csum(skb); 617 napi_gro_receive(&priv->napi[q], skb); 618 stats->rx_packets++; 619 stats->rx_bytes += pkt_len; 620 } 621 622 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 623 desc = &priv->rx_ring[q][entry]; 624 } 625 626 /* Refill the RX ring buffers. */ 627 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 628 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 629 desc = &priv->rx_ring[q][entry]; 630 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 631 632 if (!priv->rx_skb[q][entry]) { 633 skb = netdev_alloc_skb(ndev, 634 priv->rx_buf_sz + 635 RAVB_ALIGN - 1); 636 if (!skb) 637 break; /* Better luck next round. */ 638 ravb_set_buffer_align(skb); 639 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 640 le16_to_cpu(desc->ds_cc), 641 DMA_FROM_DEVICE); 642 skb_checksum_none_assert(skb); 643 /* We just set the data size to 0 for a failed mapping 644 * which should prevent DMA from happening... 645 */ 646 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 647 desc->ds_cc = cpu_to_le16(0); 648 desc->dptr = cpu_to_le32(dma_addr); 649 priv->rx_skb[q][entry] = skb; 650 } 651 /* Descriptor type must be set after all the above writes */ 652 dma_wmb(); 653 desc->die_dt = DT_FEMPTY; 654 } 655 656 *quota -= limit - (++boguscnt); 657 658 return boguscnt <= 0; 659 } 660 661 static void ravb_rcv_snd_disable(struct net_device *ndev) 662 { 663 /* Disable TX and RX */ 664 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 665 } 666 667 static void ravb_rcv_snd_enable(struct net_device *ndev) 668 { 669 /* Enable TX and RX */ 670 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 671 } 672 673 /* function for waiting dma process finished */ 674 static int ravb_stop_dma(struct net_device *ndev) 675 { 676 int error; 677 678 /* Wait for stopping the hardware TX process */ 679 error = ravb_wait(ndev, TCCR, 680 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 681 if (error) 682 return error; 683 684 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 685 0); 686 if (error) 687 return error; 688 689 /* Stop the E-MAC's RX/TX processes. */ 690 ravb_rcv_snd_disable(ndev); 691 692 /* Wait for stopping the RX DMA process */ 693 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 694 if (error) 695 return error; 696 697 /* Stop AVB-DMAC process */ 698 return ravb_config(ndev); 699 } 700 701 /* E-MAC interrupt handler */ 702 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 703 { 704 struct ravb_private *priv = netdev_priv(ndev); 705 u32 ecsr, psr; 706 707 ecsr = ravb_read(ndev, ECSR); 708 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 709 710 if (ecsr & ECSR_MPD) 711 pm_wakeup_event(&priv->pdev->dev, 0); 712 if (ecsr & ECSR_ICD) 713 ndev->stats.tx_carrier_errors++; 714 if (ecsr & ECSR_LCHNG) { 715 /* Link changed */ 716 if (priv->no_avb_link) 717 return; 718 psr = ravb_read(ndev, PSR); 719 if (priv->avb_link_active_low) 720 psr ^= PSR_LMON; 721 if (!(psr & PSR_LMON)) { 722 /* DIsable RX and TX */ 723 ravb_rcv_snd_disable(ndev); 724 } else { 725 /* Enable RX and TX */ 726 ravb_rcv_snd_enable(ndev); 727 } 728 } 729 } 730 731 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 732 { 733 struct net_device *ndev = dev_id; 734 struct ravb_private *priv = netdev_priv(ndev); 735 736 spin_lock(&priv->lock); 737 ravb_emac_interrupt_unlocked(ndev); 738 mmiowb(); 739 spin_unlock(&priv->lock); 740 return IRQ_HANDLED; 741 } 742 743 /* Error interrupt handler */ 744 static void ravb_error_interrupt(struct net_device *ndev) 745 { 746 struct ravb_private *priv = netdev_priv(ndev); 747 u32 eis, ris2; 748 749 eis = ravb_read(ndev, EIS); 750 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 751 if (eis & EIS_QFS) { 752 ris2 = ravb_read(ndev, RIS2); 753 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 754 RIS2); 755 756 /* Receive Descriptor Empty int */ 757 if (ris2 & RIS2_QFF0) 758 priv->stats[RAVB_BE].rx_over_errors++; 759 760 /* Receive Descriptor Empty int */ 761 if (ris2 & RIS2_QFF1) 762 priv->stats[RAVB_NC].rx_over_errors++; 763 764 /* Receive FIFO Overflow int */ 765 if (ris2 & RIS2_RFFF) 766 priv->rx_fifo_errors++; 767 } 768 } 769 770 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 771 { 772 struct ravb_private *priv = netdev_priv(ndev); 773 u32 ris0 = ravb_read(ndev, RIS0); 774 u32 ric0 = ravb_read(ndev, RIC0); 775 u32 tis = ravb_read(ndev, TIS); 776 u32 tic = ravb_read(ndev, TIC); 777 778 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 779 if (napi_schedule_prep(&priv->napi[q])) { 780 /* Mask RX and TX interrupts */ 781 if (priv->chip_id == RCAR_GEN2) { 782 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 783 ravb_write(ndev, tic & ~BIT(q), TIC); 784 } else { 785 ravb_write(ndev, BIT(q), RID0); 786 ravb_write(ndev, BIT(q), TID); 787 } 788 __napi_schedule(&priv->napi[q]); 789 } else { 790 netdev_warn(ndev, 791 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 792 ris0, ric0); 793 netdev_warn(ndev, 794 " tx status 0x%08x, tx mask 0x%08x.\n", 795 tis, tic); 796 } 797 return true; 798 } 799 return false; 800 } 801 802 static bool ravb_timestamp_interrupt(struct net_device *ndev) 803 { 804 u32 tis = ravb_read(ndev, TIS); 805 806 if (tis & TIS_TFUF) { 807 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 808 ravb_get_tx_tstamp(ndev); 809 return true; 810 } 811 return false; 812 } 813 814 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 815 { 816 struct net_device *ndev = dev_id; 817 struct ravb_private *priv = netdev_priv(ndev); 818 irqreturn_t result = IRQ_NONE; 819 u32 iss; 820 821 spin_lock(&priv->lock); 822 /* Get interrupt status */ 823 iss = ravb_read(ndev, ISS); 824 825 /* Received and transmitted interrupts */ 826 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 827 int q; 828 829 /* Timestamp updated */ 830 if (ravb_timestamp_interrupt(ndev)) 831 result = IRQ_HANDLED; 832 833 /* Network control and best effort queue RX/TX */ 834 for (q = RAVB_NC; q >= RAVB_BE; q--) { 835 if (ravb_queue_interrupt(ndev, q)) 836 result = IRQ_HANDLED; 837 } 838 } 839 840 /* E-MAC status summary */ 841 if (iss & ISS_MS) { 842 ravb_emac_interrupt_unlocked(ndev); 843 result = IRQ_HANDLED; 844 } 845 846 /* Error status summary */ 847 if (iss & ISS_ES) { 848 ravb_error_interrupt(ndev); 849 result = IRQ_HANDLED; 850 } 851 852 /* gPTP interrupt status summary */ 853 if (iss & ISS_CGIS) { 854 ravb_ptp_interrupt(ndev); 855 result = IRQ_HANDLED; 856 } 857 858 mmiowb(); 859 spin_unlock(&priv->lock); 860 return result; 861 } 862 863 /* Timestamp/Error/gPTP interrupt handler */ 864 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 865 { 866 struct net_device *ndev = dev_id; 867 struct ravb_private *priv = netdev_priv(ndev); 868 irqreturn_t result = IRQ_NONE; 869 u32 iss; 870 871 spin_lock(&priv->lock); 872 /* Get interrupt status */ 873 iss = ravb_read(ndev, ISS); 874 875 /* Timestamp updated */ 876 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 877 result = IRQ_HANDLED; 878 879 /* Error status summary */ 880 if (iss & ISS_ES) { 881 ravb_error_interrupt(ndev); 882 result = IRQ_HANDLED; 883 } 884 885 /* gPTP interrupt status summary */ 886 if (iss & ISS_CGIS) { 887 ravb_ptp_interrupt(ndev); 888 result = IRQ_HANDLED; 889 } 890 891 mmiowb(); 892 spin_unlock(&priv->lock); 893 return result; 894 } 895 896 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 897 { 898 struct net_device *ndev = dev_id; 899 struct ravb_private *priv = netdev_priv(ndev); 900 irqreturn_t result = IRQ_NONE; 901 902 spin_lock(&priv->lock); 903 904 /* Network control/Best effort queue RX/TX */ 905 if (ravb_queue_interrupt(ndev, q)) 906 result = IRQ_HANDLED; 907 908 mmiowb(); 909 spin_unlock(&priv->lock); 910 return result; 911 } 912 913 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 914 { 915 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 916 } 917 918 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 919 { 920 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 921 } 922 923 static int ravb_poll(struct napi_struct *napi, int budget) 924 { 925 struct net_device *ndev = napi->dev; 926 struct ravb_private *priv = netdev_priv(ndev); 927 unsigned long flags; 928 int q = napi - priv->napi; 929 int mask = BIT(q); 930 int quota = budget; 931 u32 ris0, tis; 932 933 for (;;) { 934 tis = ravb_read(ndev, TIS); 935 ris0 = ravb_read(ndev, RIS0); 936 if (!((ris0 & mask) || (tis & mask))) 937 break; 938 939 /* Processing RX Descriptor Ring */ 940 if (ris0 & mask) { 941 /* Clear RX interrupt */ 942 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 943 if (ravb_rx(ndev, "a, q)) 944 goto out; 945 } 946 /* Processing TX Descriptor Ring */ 947 if (tis & mask) { 948 spin_lock_irqsave(&priv->lock, flags); 949 /* Clear TX interrupt */ 950 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 951 ravb_tx_free(ndev, q, true); 952 netif_wake_subqueue(ndev, q); 953 mmiowb(); 954 spin_unlock_irqrestore(&priv->lock, flags); 955 } 956 } 957 958 napi_complete(napi); 959 960 /* Re-enable RX/TX interrupts */ 961 spin_lock_irqsave(&priv->lock, flags); 962 if (priv->chip_id == RCAR_GEN2) { 963 ravb_modify(ndev, RIC0, mask, mask); 964 ravb_modify(ndev, TIC, mask, mask); 965 } else { 966 ravb_write(ndev, mask, RIE0); 967 ravb_write(ndev, mask, TIE); 968 } 969 mmiowb(); 970 spin_unlock_irqrestore(&priv->lock, flags); 971 972 /* Receive error message handling */ 973 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 974 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 975 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 976 ndev->stats.rx_over_errors = priv->rx_over_errors; 977 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 978 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 979 out: 980 return budget - quota; 981 } 982 983 /* PHY state control function */ 984 static void ravb_adjust_link(struct net_device *ndev) 985 { 986 struct ravb_private *priv = netdev_priv(ndev); 987 struct phy_device *phydev = ndev->phydev; 988 bool new_state = false; 989 unsigned long flags; 990 991 spin_lock_irqsave(&priv->lock, flags); 992 993 /* Disable TX and RX right over here, if E-MAC change is ignored */ 994 if (priv->no_avb_link) 995 ravb_rcv_snd_disable(ndev); 996 997 if (phydev->link) { 998 if (phydev->duplex != priv->duplex) { 999 new_state = true; 1000 priv->duplex = phydev->duplex; 1001 ravb_set_duplex(ndev); 1002 } 1003 1004 if (phydev->speed != priv->speed) { 1005 new_state = true; 1006 priv->speed = phydev->speed; 1007 ravb_set_rate(ndev); 1008 } 1009 if (!priv->link) { 1010 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1011 new_state = true; 1012 priv->link = phydev->link; 1013 } 1014 } else if (priv->link) { 1015 new_state = true; 1016 priv->link = 0; 1017 priv->speed = 0; 1018 priv->duplex = -1; 1019 } 1020 1021 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1022 if (priv->no_avb_link && phydev->link) 1023 ravb_rcv_snd_enable(ndev); 1024 1025 mmiowb(); 1026 spin_unlock_irqrestore(&priv->lock, flags); 1027 1028 if (new_state && netif_msg_link(priv)) 1029 phy_print_status(phydev); 1030 } 1031 1032 static const struct soc_device_attribute r8a7795es10[] = { 1033 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1034 { /* sentinel */ } 1035 }; 1036 1037 /* PHY init function */ 1038 static int ravb_phy_init(struct net_device *ndev) 1039 { 1040 struct device_node *np = ndev->dev.parent->of_node; 1041 struct ravb_private *priv = netdev_priv(ndev); 1042 struct phy_device *phydev; 1043 struct device_node *pn; 1044 int err; 1045 1046 priv->link = 0; 1047 priv->speed = 0; 1048 priv->duplex = -1; 1049 1050 /* Try connecting to PHY */ 1051 pn = of_parse_phandle(np, "phy-handle", 0); 1052 if (!pn) { 1053 /* In the case of a fixed PHY, the DT node associated 1054 * to the PHY is the Ethernet MAC DT node. 1055 */ 1056 if (of_phy_is_fixed_link(np)) { 1057 err = of_phy_register_fixed_link(np); 1058 if (err) 1059 return err; 1060 } 1061 pn = of_node_get(np); 1062 } 1063 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1064 priv->phy_interface); 1065 of_node_put(pn); 1066 if (!phydev) { 1067 netdev_err(ndev, "failed to connect PHY\n"); 1068 err = -ENOENT; 1069 goto err_deregister_fixed_link; 1070 } 1071 1072 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1073 * at this time. 1074 */ 1075 if (soc_device_match(r8a7795es10)) { 1076 err = phy_set_max_speed(phydev, SPEED_100); 1077 if (err) { 1078 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1079 goto err_phy_disconnect; 1080 } 1081 1082 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1083 } 1084 1085 /* 10BASE, Pause and Asym Pause is not supported */ 1086 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1087 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1088 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1089 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1090 1091 phy_attached_info(phydev); 1092 1093 return 0; 1094 1095 err_phy_disconnect: 1096 phy_disconnect(phydev); 1097 err_deregister_fixed_link: 1098 if (of_phy_is_fixed_link(np)) 1099 of_phy_deregister_fixed_link(np); 1100 1101 return err; 1102 } 1103 1104 /* PHY control start function */ 1105 static int ravb_phy_start(struct net_device *ndev) 1106 { 1107 int error; 1108 1109 error = ravb_phy_init(ndev); 1110 if (error) 1111 return error; 1112 1113 phy_start(ndev->phydev); 1114 1115 return 0; 1116 } 1117 1118 static u32 ravb_get_msglevel(struct net_device *ndev) 1119 { 1120 struct ravb_private *priv = netdev_priv(ndev); 1121 1122 return priv->msg_enable; 1123 } 1124 1125 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1126 { 1127 struct ravb_private *priv = netdev_priv(ndev); 1128 1129 priv->msg_enable = value; 1130 } 1131 1132 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1133 "rx_queue_0_current", 1134 "tx_queue_0_current", 1135 "rx_queue_0_dirty", 1136 "tx_queue_0_dirty", 1137 "rx_queue_0_packets", 1138 "tx_queue_0_packets", 1139 "rx_queue_0_bytes", 1140 "tx_queue_0_bytes", 1141 "rx_queue_0_mcast_packets", 1142 "rx_queue_0_errors", 1143 "rx_queue_0_crc_errors", 1144 "rx_queue_0_frame_errors", 1145 "rx_queue_0_length_errors", 1146 "rx_queue_0_missed_errors", 1147 "rx_queue_0_over_errors", 1148 1149 "rx_queue_1_current", 1150 "tx_queue_1_current", 1151 "rx_queue_1_dirty", 1152 "tx_queue_1_dirty", 1153 "rx_queue_1_packets", 1154 "tx_queue_1_packets", 1155 "rx_queue_1_bytes", 1156 "tx_queue_1_bytes", 1157 "rx_queue_1_mcast_packets", 1158 "rx_queue_1_errors", 1159 "rx_queue_1_crc_errors", 1160 "rx_queue_1_frame_errors", 1161 "rx_queue_1_length_errors", 1162 "rx_queue_1_missed_errors", 1163 "rx_queue_1_over_errors", 1164 }; 1165 1166 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1167 1168 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1169 { 1170 switch (sset) { 1171 case ETH_SS_STATS: 1172 return RAVB_STATS_LEN; 1173 default: 1174 return -EOPNOTSUPP; 1175 } 1176 } 1177 1178 static void ravb_get_ethtool_stats(struct net_device *ndev, 1179 struct ethtool_stats *estats, u64 *data) 1180 { 1181 struct ravb_private *priv = netdev_priv(ndev); 1182 int i = 0; 1183 int q; 1184 1185 /* Device-specific stats */ 1186 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1187 struct net_device_stats *stats = &priv->stats[q]; 1188 1189 data[i++] = priv->cur_rx[q]; 1190 data[i++] = priv->cur_tx[q]; 1191 data[i++] = priv->dirty_rx[q]; 1192 data[i++] = priv->dirty_tx[q]; 1193 data[i++] = stats->rx_packets; 1194 data[i++] = stats->tx_packets; 1195 data[i++] = stats->rx_bytes; 1196 data[i++] = stats->tx_bytes; 1197 data[i++] = stats->multicast; 1198 data[i++] = stats->rx_errors; 1199 data[i++] = stats->rx_crc_errors; 1200 data[i++] = stats->rx_frame_errors; 1201 data[i++] = stats->rx_length_errors; 1202 data[i++] = stats->rx_missed_errors; 1203 data[i++] = stats->rx_over_errors; 1204 } 1205 } 1206 1207 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1208 { 1209 switch (stringset) { 1210 case ETH_SS_STATS: 1211 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1212 break; 1213 } 1214 } 1215 1216 static void ravb_get_ringparam(struct net_device *ndev, 1217 struct ethtool_ringparam *ring) 1218 { 1219 struct ravb_private *priv = netdev_priv(ndev); 1220 1221 ring->rx_max_pending = BE_RX_RING_MAX; 1222 ring->tx_max_pending = BE_TX_RING_MAX; 1223 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1224 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1225 } 1226 1227 static int ravb_set_ringparam(struct net_device *ndev, 1228 struct ethtool_ringparam *ring) 1229 { 1230 struct ravb_private *priv = netdev_priv(ndev); 1231 int error; 1232 1233 if (ring->tx_pending > BE_TX_RING_MAX || 1234 ring->rx_pending > BE_RX_RING_MAX || 1235 ring->tx_pending < BE_TX_RING_MIN || 1236 ring->rx_pending < BE_RX_RING_MIN) 1237 return -EINVAL; 1238 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1239 return -EINVAL; 1240 1241 if (netif_running(ndev)) { 1242 netif_device_detach(ndev); 1243 /* Stop PTP Clock driver */ 1244 if (priv->chip_id == RCAR_GEN2) 1245 ravb_ptp_stop(ndev); 1246 /* Wait for DMA stopping */ 1247 error = ravb_stop_dma(ndev); 1248 if (error) { 1249 netdev_err(ndev, 1250 "cannot set ringparam! Any AVB processes are still running?\n"); 1251 return error; 1252 } 1253 synchronize_irq(ndev->irq); 1254 1255 /* Free all the skb's in the RX queue and the DMA buffers. */ 1256 ravb_ring_free(ndev, RAVB_BE); 1257 ravb_ring_free(ndev, RAVB_NC); 1258 } 1259 1260 /* Set new parameters */ 1261 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1262 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1263 1264 if (netif_running(ndev)) { 1265 error = ravb_dmac_init(ndev); 1266 if (error) { 1267 netdev_err(ndev, 1268 "%s: ravb_dmac_init() failed, error %d\n", 1269 __func__, error); 1270 return error; 1271 } 1272 1273 ravb_emac_init(ndev); 1274 1275 /* Initialise PTP Clock driver */ 1276 if (priv->chip_id == RCAR_GEN2) 1277 ravb_ptp_init(ndev, priv->pdev); 1278 1279 netif_device_attach(ndev); 1280 } 1281 1282 return 0; 1283 } 1284 1285 static int ravb_get_ts_info(struct net_device *ndev, 1286 struct ethtool_ts_info *info) 1287 { 1288 struct ravb_private *priv = netdev_priv(ndev); 1289 1290 info->so_timestamping = 1291 SOF_TIMESTAMPING_TX_SOFTWARE | 1292 SOF_TIMESTAMPING_RX_SOFTWARE | 1293 SOF_TIMESTAMPING_SOFTWARE | 1294 SOF_TIMESTAMPING_TX_HARDWARE | 1295 SOF_TIMESTAMPING_RX_HARDWARE | 1296 SOF_TIMESTAMPING_RAW_HARDWARE; 1297 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1298 info->rx_filters = 1299 (1 << HWTSTAMP_FILTER_NONE) | 1300 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1301 (1 << HWTSTAMP_FILTER_ALL); 1302 info->phc_index = ptp_clock_index(priv->ptp.clock); 1303 1304 return 0; 1305 } 1306 1307 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1308 { 1309 struct ravb_private *priv = netdev_priv(ndev); 1310 1311 wol->supported = WAKE_MAGIC; 1312 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1313 } 1314 1315 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1316 { 1317 struct ravb_private *priv = netdev_priv(ndev); 1318 1319 if (wol->wolopts & ~WAKE_MAGIC) 1320 return -EOPNOTSUPP; 1321 1322 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1323 1324 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1325 1326 return 0; 1327 } 1328 1329 static const struct ethtool_ops ravb_ethtool_ops = { 1330 .nway_reset = phy_ethtool_nway_reset, 1331 .get_msglevel = ravb_get_msglevel, 1332 .set_msglevel = ravb_set_msglevel, 1333 .get_link = ethtool_op_get_link, 1334 .get_strings = ravb_get_strings, 1335 .get_ethtool_stats = ravb_get_ethtool_stats, 1336 .get_sset_count = ravb_get_sset_count, 1337 .get_ringparam = ravb_get_ringparam, 1338 .set_ringparam = ravb_set_ringparam, 1339 .get_ts_info = ravb_get_ts_info, 1340 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1341 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1342 .get_wol = ravb_get_wol, 1343 .set_wol = ravb_set_wol, 1344 }; 1345 1346 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1347 struct net_device *ndev, struct device *dev, 1348 const char *ch) 1349 { 1350 char *name; 1351 int error; 1352 1353 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1354 if (!name) 1355 return -ENOMEM; 1356 error = request_irq(irq, handler, 0, name, ndev); 1357 if (error) 1358 netdev_err(ndev, "cannot request IRQ %s\n", name); 1359 1360 return error; 1361 } 1362 1363 /* Network device open function for Ethernet AVB */ 1364 static int ravb_open(struct net_device *ndev) 1365 { 1366 struct ravb_private *priv = netdev_priv(ndev); 1367 struct platform_device *pdev = priv->pdev; 1368 struct device *dev = &pdev->dev; 1369 int error; 1370 1371 napi_enable(&priv->napi[RAVB_BE]); 1372 napi_enable(&priv->napi[RAVB_NC]); 1373 1374 if (priv->chip_id == RCAR_GEN2) { 1375 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1376 ndev->name, ndev); 1377 if (error) { 1378 netdev_err(ndev, "cannot request IRQ\n"); 1379 goto out_napi_off; 1380 } 1381 } else { 1382 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1383 dev, "ch22:multi"); 1384 if (error) 1385 goto out_napi_off; 1386 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1387 dev, "ch24:emac"); 1388 if (error) 1389 goto out_free_irq; 1390 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1391 ndev, dev, "ch0:rx_be"); 1392 if (error) 1393 goto out_free_irq_emac; 1394 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1395 ndev, dev, "ch18:tx_be"); 1396 if (error) 1397 goto out_free_irq_be_rx; 1398 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1399 ndev, dev, "ch1:rx_nc"); 1400 if (error) 1401 goto out_free_irq_be_tx; 1402 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1403 ndev, dev, "ch19:tx_nc"); 1404 if (error) 1405 goto out_free_irq_nc_rx; 1406 } 1407 1408 /* Device init */ 1409 error = ravb_dmac_init(ndev); 1410 if (error) 1411 goto out_free_irq_nc_tx; 1412 ravb_emac_init(ndev); 1413 1414 /* Initialise PTP Clock driver */ 1415 if (priv->chip_id == RCAR_GEN2) 1416 ravb_ptp_init(ndev, priv->pdev); 1417 1418 netif_tx_start_all_queues(ndev); 1419 1420 /* PHY control start */ 1421 error = ravb_phy_start(ndev); 1422 if (error) 1423 goto out_ptp_stop; 1424 1425 return 0; 1426 1427 out_ptp_stop: 1428 /* Stop PTP Clock driver */ 1429 if (priv->chip_id == RCAR_GEN2) 1430 ravb_ptp_stop(ndev); 1431 out_free_irq_nc_tx: 1432 if (priv->chip_id == RCAR_GEN2) 1433 goto out_free_irq; 1434 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1435 out_free_irq_nc_rx: 1436 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1437 out_free_irq_be_tx: 1438 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1439 out_free_irq_be_rx: 1440 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1441 out_free_irq_emac: 1442 free_irq(priv->emac_irq, ndev); 1443 out_free_irq: 1444 free_irq(ndev->irq, ndev); 1445 out_napi_off: 1446 napi_disable(&priv->napi[RAVB_NC]); 1447 napi_disable(&priv->napi[RAVB_BE]); 1448 return error; 1449 } 1450 1451 /* Timeout function for Ethernet AVB */ 1452 static void ravb_tx_timeout(struct net_device *ndev) 1453 { 1454 struct ravb_private *priv = netdev_priv(ndev); 1455 1456 netif_err(priv, tx_err, ndev, 1457 "transmit timed out, status %08x, resetting...\n", 1458 ravb_read(ndev, ISS)); 1459 1460 /* tx_errors count up */ 1461 ndev->stats.tx_errors++; 1462 1463 schedule_work(&priv->work); 1464 } 1465 1466 static void ravb_tx_timeout_work(struct work_struct *work) 1467 { 1468 struct ravb_private *priv = container_of(work, struct ravb_private, 1469 work); 1470 struct net_device *ndev = priv->ndev; 1471 1472 netif_tx_stop_all_queues(ndev); 1473 1474 /* Stop PTP Clock driver */ 1475 if (priv->chip_id == RCAR_GEN2) 1476 ravb_ptp_stop(ndev); 1477 1478 /* Wait for DMA stopping */ 1479 ravb_stop_dma(ndev); 1480 1481 ravb_ring_free(ndev, RAVB_BE); 1482 ravb_ring_free(ndev, RAVB_NC); 1483 1484 /* Device init */ 1485 ravb_dmac_init(ndev); 1486 ravb_emac_init(ndev); 1487 1488 /* Initialise PTP Clock driver */ 1489 if (priv->chip_id == RCAR_GEN2) 1490 ravb_ptp_init(ndev, priv->pdev); 1491 1492 netif_tx_start_all_queues(ndev); 1493 } 1494 1495 /* Packet transmit function for Ethernet AVB */ 1496 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1497 { 1498 struct ravb_private *priv = netdev_priv(ndev); 1499 int num_tx_desc = priv->num_tx_desc; 1500 u16 q = skb_get_queue_mapping(skb); 1501 struct ravb_tstamp_skb *ts_skb; 1502 struct ravb_tx_desc *desc; 1503 unsigned long flags; 1504 u32 dma_addr; 1505 void *buffer; 1506 u32 entry; 1507 u32 len; 1508 1509 spin_lock_irqsave(&priv->lock, flags); 1510 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1511 num_tx_desc) { 1512 netif_err(priv, tx_queued, ndev, 1513 "still transmitting with the full ring!\n"); 1514 netif_stop_subqueue(ndev, q); 1515 spin_unlock_irqrestore(&priv->lock, flags); 1516 return NETDEV_TX_BUSY; 1517 } 1518 1519 if (skb_put_padto(skb, ETH_ZLEN)) 1520 goto exit; 1521 1522 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1523 priv->tx_skb[q][entry / num_tx_desc] = skb; 1524 1525 if (num_tx_desc > 1) { 1526 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1527 entry / num_tx_desc * DPTR_ALIGN; 1528 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1529 1530 /* Zero length DMA descriptors are problematic as they seem 1531 * to terminate DMA transfers. Avoid them by simply using a 1532 * length of DPTR_ALIGN (4) when skb data is aligned to 1533 * DPTR_ALIGN. 1534 * 1535 * As skb is guaranteed to have at least ETH_ZLEN (60) 1536 * bytes of data by the call to skb_put_padto() above this 1537 * is safe with respect to both the length of the first DMA 1538 * descriptor (len) overflowing the available data and the 1539 * length of the second DMA descriptor (skb->len - len) 1540 * being negative. 1541 */ 1542 if (len == 0) 1543 len = DPTR_ALIGN; 1544 1545 memcpy(buffer, skb->data, len); 1546 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1547 DMA_TO_DEVICE); 1548 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1549 goto drop; 1550 1551 desc = &priv->tx_ring[q][entry]; 1552 desc->ds_tagl = cpu_to_le16(len); 1553 desc->dptr = cpu_to_le32(dma_addr); 1554 1555 buffer = skb->data + len; 1556 len = skb->len - len; 1557 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1558 DMA_TO_DEVICE); 1559 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1560 goto unmap; 1561 1562 desc++; 1563 } else { 1564 desc = &priv->tx_ring[q][entry]; 1565 len = skb->len; 1566 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1567 DMA_TO_DEVICE); 1568 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1569 goto drop; 1570 } 1571 desc->ds_tagl = cpu_to_le16(len); 1572 desc->dptr = cpu_to_le32(dma_addr); 1573 1574 /* TX timestamp required */ 1575 if (q == RAVB_NC) { 1576 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1577 if (!ts_skb) { 1578 if (num_tx_desc > 1) { 1579 desc--; 1580 dma_unmap_single(ndev->dev.parent, dma_addr, 1581 len, DMA_TO_DEVICE); 1582 } 1583 goto unmap; 1584 } 1585 ts_skb->skb = skb; 1586 ts_skb->tag = priv->ts_skb_tag++; 1587 priv->ts_skb_tag &= 0x3ff; 1588 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1589 1590 /* TAG and timestamp required flag */ 1591 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1592 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1593 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1594 } 1595 1596 skb_tx_timestamp(skb); 1597 /* Descriptor type must be set after all the above writes */ 1598 dma_wmb(); 1599 if (num_tx_desc > 1) { 1600 desc->die_dt = DT_FEND; 1601 desc--; 1602 desc->die_dt = DT_FSTART; 1603 } else { 1604 desc->die_dt = DT_FSINGLE; 1605 } 1606 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1607 1608 priv->cur_tx[q] += num_tx_desc; 1609 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1610 (priv->num_tx_ring[q] - 1) * num_tx_desc && 1611 !ravb_tx_free(ndev, q, true)) 1612 netif_stop_subqueue(ndev, q); 1613 1614 exit: 1615 mmiowb(); 1616 spin_unlock_irqrestore(&priv->lock, flags); 1617 return NETDEV_TX_OK; 1618 1619 unmap: 1620 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1621 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1622 drop: 1623 dev_kfree_skb_any(skb); 1624 priv->tx_skb[q][entry / num_tx_desc] = NULL; 1625 goto exit; 1626 } 1627 1628 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1629 struct net_device *sb_dev, 1630 select_queue_fallback_t fallback) 1631 { 1632 /* If skb needs TX timestamp, it is handled in network control queue */ 1633 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1634 RAVB_BE; 1635 1636 } 1637 1638 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1639 { 1640 struct ravb_private *priv = netdev_priv(ndev); 1641 struct net_device_stats *nstats, *stats0, *stats1; 1642 1643 nstats = &ndev->stats; 1644 stats0 = &priv->stats[RAVB_BE]; 1645 stats1 = &priv->stats[RAVB_NC]; 1646 1647 nstats->tx_dropped += ravb_read(ndev, TROCR); 1648 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1649 nstats->collisions += ravb_read(ndev, CDCR); 1650 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1651 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1652 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1653 1654 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1655 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1656 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1657 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1658 1659 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1660 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1661 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1662 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1663 nstats->multicast = stats0->multicast + stats1->multicast; 1664 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1665 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1666 nstats->rx_frame_errors = 1667 stats0->rx_frame_errors + stats1->rx_frame_errors; 1668 nstats->rx_length_errors = 1669 stats0->rx_length_errors + stats1->rx_length_errors; 1670 nstats->rx_missed_errors = 1671 stats0->rx_missed_errors + stats1->rx_missed_errors; 1672 nstats->rx_over_errors = 1673 stats0->rx_over_errors + stats1->rx_over_errors; 1674 1675 return nstats; 1676 } 1677 1678 /* Update promiscuous bit */ 1679 static void ravb_set_rx_mode(struct net_device *ndev) 1680 { 1681 struct ravb_private *priv = netdev_priv(ndev); 1682 unsigned long flags; 1683 1684 spin_lock_irqsave(&priv->lock, flags); 1685 ravb_modify(ndev, ECMR, ECMR_PRM, 1686 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1687 mmiowb(); 1688 spin_unlock_irqrestore(&priv->lock, flags); 1689 } 1690 1691 /* Device close function for Ethernet AVB */ 1692 static int ravb_close(struct net_device *ndev) 1693 { 1694 struct device_node *np = ndev->dev.parent->of_node; 1695 struct ravb_private *priv = netdev_priv(ndev); 1696 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1697 1698 netif_tx_stop_all_queues(ndev); 1699 1700 /* Disable interrupts by clearing the interrupt masks. */ 1701 ravb_write(ndev, 0, RIC0); 1702 ravb_write(ndev, 0, RIC2); 1703 ravb_write(ndev, 0, TIC); 1704 1705 /* Stop PTP Clock driver */ 1706 if (priv->chip_id == RCAR_GEN2) 1707 ravb_ptp_stop(ndev); 1708 1709 /* Set the config mode to stop the AVB-DMAC's processes */ 1710 if (ravb_stop_dma(ndev) < 0) 1711 netdev_err(ndev, 1712 "device will be stopped after h/w processes are done.\n"); 1713 1714 /* Clear the timestamp list */ 1715 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1716 list_del(&ts_skb->list); 1717 kfree(ts_skb); 1718 } 1719 1720 /* PHY disconnect */ 1721 if (ndev->phydev) { 1722 phy_stop(ndev->phydev); 1723 phy_disconnect(ndev->phydev); 1724 if (of_phy_is_fixed_link(np)) 1725 of_phy_deregister_fixed_link(np); 1726 } 1727 1728 if (priv->chip_id != RCAR_GEN2) { 1729 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1730 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1731 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1732 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1733 free_irq(priv->emac_irq, ndev); 1734 } 1735 free_irq(ndev->irq, ndev); 1736 1737 napi_disable(&priv->napi[RAVB_NC]); 1738 napi_disable(&priv->napi[RAVB_BE]); 1739 1740 /* Free all the skb's in the RX queue and the DMA buffers. */ 1741 ravb_ring_free(ndev, RAVB_BE); 1742 ravb_ring_free(ndev, RAVB_NC); 1743 1744 return 0; 1745 } 1746 1747 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1748 { 1749 struct ravb_private *priv = netdev_priv(ndev); 1750 struct hwtstamp_config config; 1751 1752 config.flags = 0; 1753 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1754 HWTSTAMP_TX_OFF; 1755 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1756 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1757 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1758 config.rx_filter = HWTSTAMP_FILTER_ALL; 1759 else 1760 config.rx_filter = HWTSTAMP_FILTER_NONE; 1761 1762 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1763 -EFAULT : 0; 1764 } 1765 1766 /* Control hardware time stamping */ 1767 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1768 { 1769 struct ravb_private *priv = netdev_priv(ndev); 1770 struct hwtstamp_config config; 1771 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1772 u32 tstamp_tx_ctrl; 1773 1774 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1775 return -EFAULT; 1776 1777 /* Reserved for future extensions */ 1778 if (config.flags) 1779 return -EINVAL; 1780 1781 switch (config.tx_type) { 1782 case HWTSTAMP_TX_OFF: 1783 tstamp_tx_ctrl = 0; 1784 break; 1785 case HWTSTAMP_TX_ON: 1786 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1787 break; 1788 default: 1789 return -ERANGE; 1790 } 1791 1792 switch (config.rx_filter) { 1793 case HWTSTAMP_FILTER_NONE: 1794 tstamp_rx_ctrl = 0; 1795 break; 1796 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1797 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1798 break; 1799 default: 1800 config.rx_filter = HWTSTAMP_FILTER_ALL; 1801 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1802 } 1803 1804 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1805 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1806 1807 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1808 -EFAULT : 0; 1809 } 1810 1811 /* ioctl to device function */ 1812 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1813 { 1814 struct phy_device *phydev = ndev->phydev; 1815 1816 if (!netif_running(ndev)) 1817 return -EINVAL; 1818 1819 if (!phydev) 1820 return -ENODEV; 1821 1822 switch (cmd) { 1823 case SIOCGHWTSTAMP: 1824 return ravb_hwtstamp_get(ndev, req); 1825 case SIOCSHWTSTAMP: 1826 return ravb_hwtstamp_set(ndev, req); 1827 } 1828 1829 return phy_mii_ioctl(phydev, req, cmd); 1830 } 1831 1832 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1833 { 1834 if (netif_running(ndev)) 1835 return -EBUSY; 1836 1837 ndev->mtu = new_mtu; 1838 netdev_update_features(ndev); 1839 1840 return 0; 1841 } 1842 1843 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1844 { 1845 struct ravb_private *priv = netdev_priv(ndev); 1846 unsigned long flags; 1847 1848 spin_lock_irqsave(&priv->lock, flags); 1849 1850 /* Disable TX and RX */ 1851 ravb_rcv_snd_disable(ndev); 1852 1853 /* Modify RX Checksum setting */ 1854 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1855 1856 /* Enable TX and RX */ 1857 ravb_rcv_snd_enable(ndev); 1858 1859 spin_unlock_irqrestore(&priv->lock, flags); 1860 } 1861 1862 static int ravb_set_features(struct net_device *ndev, 1863 netdev_features_t features) 1864 { 1865 netdev_features_t changed = ndev->features ^ features; 1866 1867 if (changed & NETIF_F_RXCSUM) 1868 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1869 1870 ndev->features = features; 1871 1872 return 0; 1873 } 1874 1875 static const struct net_device_ops ravb_netdev_ops = { 1876 .ndo_open = ravb_open, 1877 .ndo_stop = ravb_close, 1878 .ndo_start_xmit = ravb_start_xmit, 1879 .ndo_select_queue = ravb_select_queue, 1880 .ndo_get_stats = ravb_get_stats, 1881 .ndo_set_rx_mode = ravb_set_rx_mode, 1882 .ndo_tx_timeout = ravb_tx_timeout, 1883 .ndo_do_ioctl = ravb_do_ioctl, 1884 .ndo_change_mtu = ravb_change_mtu, 1885 .ndo_validate_addr = eth_validate_addr, 1886 .ndo_set_mac_address = eth_mac_addr, 1887 .ndo_set_features = ravb_set_features, 1888 }; 1889 1890 /* MDIO bus init function */ 1891 static int ravb_mdio_init(struct ravb_private *priv) 1892 { 1893 struct platform_device *pdev = priv->pdev; 1894 struct device *dev = &pdev->dev; 1895 int error; 1896 1897 /* Bitbang init */ 1898 priv->mdiobb.ops = &bb_ops; 1899 1900 /* MII controller setting */ 1901 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1902 if (!priv->mii_bus) 1903 return -ENOMEM; 1904 1905 /* Hook up MII support for ethtool */ 1906 priv->mii_bus->name = "ravb_mii"; 1907 priv->mii_bus->parent = dev; 1908 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1909 pdev->name, pdev->id); 1910 1911 /* Register MDIO bus */ 1912 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1913 if (error) 1914 goto out_free_bus; 1915 1916 return 0; 1917 1918 out_free_bus: 1919 free_mdio_bitbang(priv->mii_bus); 1920 return error; 1921 } 1922 1923 /* MDIO bus release function */ 1924 static int ravb_mdio_release(struct ravb_private *priv) 1925 { 1926 /* Unregister mdio bus */ 1927 mdiobus_unregister(priv->mii_bus); 1928 1929 /* Free bitbang info */ 1930 free_mdio_bitbang(priv->mii_bus); 1931 1932 return 0; 1933 } 1934 1935 static const struct of_device_id ravb_match_table[] = { 1936 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1937 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1938 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1939 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1940 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1941 { } 1942 }; 1943 MODULE_DEVICE_TABLE(of, ravb_match_table); 1944 1945 static int ravb_set_gti(struct net_device *ndev) 1946 { 1947 struct ravb_private *priv = netdev_priv(ndev); 1948 struct device *dev = ndev->dev.parent; 1949 unsigned long rate; 1950 uint64_t inc; 1951 1952 rate = clk_get_rate(priv->clk); 1953 if (!rate) 1954 return -EINVAL; 1955 1956 inc = 1000000000ULL << 20; 1957 do_div(inc, rate); 1958 1959 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1960 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1961 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1962 return -EINVAL; 1963 } 1964 1965 ravb_write(ndev, inc, GTI); 1966 1967 return 0; 1968 } 1969 1970 static void ravb_set_config_mode(struct net_device *ndev) 1971 { 1972 struct ravb_private *priv = netdev_priv(ndev); 1973 1974 if (priv->chip_id == RCAR_GEN2) { 1975 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1976 /* Set CSEL value */ 1977 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1978 } else { 1979 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1980 CCC_GAC | CCC_CSEL_HPB); 1981 } 1982 } 1983 1984 /* Set tx and rx clock internal delay modes */ 1985 static void ravb_set_delay_mode(struct net_device *ndev) 1986 { 1987 struct ravb_private *priv = netdev_priv(ndev); 1988 int set = 0; 1989 1990 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1991 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1992 set |= APSR_DM_RDM; 1993 1994 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1995 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1996 set |= APSR_DM_TDM; 1997 1998 ravb_modify(ndev, APSR, APSR_DM, set); 1999 } 2000 2001 static int ravb_probe(struct platform_device *pdev) 2002 { 2003 struct device_node *np = pdev->dev.of_node; 2004 struct ravb_private *priv; 2005 enum ravb_chip_id chip_id; 2006 struct net_device *ndev; 2007 int error, irq, q; 2008 struct resource *res; 2009 int i; 2010 2011 if (!np) { 2012 dev_err(&pdev->dev, 2013 "this driver is required to be instantiated from device tree\n"); 2014 return -EINVAL; 2015 } 2016 2017 /* Get base address */ 2018 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2019 if (!res) { 2020 dev_err(&pdev->dev, "invalid resource\n"); 2021 return -EINVAL; 2022 } 2023 2024 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2025 NUM_TX_QUEUE, NUM_RX_QUEUE); 2026 if (!ndev) 2027 return -ENOMEM; 2028 2029 ndev->features = NETIF_F_RXCSUM; 2030 ndev->hw_features = NETIF_F_RXCSUM; 2031 2032 pm_runtime_enable(&pdev->dev); 2033 pm_runtime_get_sync(&pdev->dev); 2034 2035 /* The Ether-specific entries in the device structure. */ 2036 ndev->base_addr = res->start; 2037 2038 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2039 2040 if (chip_id == RCAR_GEN3) 2041 irq = platform_get_irq_byname(pdev, "ch22"); 2042 else 2043 irq = platform_get_irq(pdev, 0); 2044 if (irq < 0) { 2045 error = irq; 2046 goto out_release; 2047 } 2048 ndev->irq = irq; 2049 2050 SET_NETDEV_DEV(ndev, &pdev->dev); 2051 2052 priv = netdev_priv(ndev); 2053 priv->ndev = ndev; 2054 priv->pdev = pdev; 2055 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2056 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2057 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2058 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2059 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2060 if (IS_ERR(priv->addr)) { 2061 error = PTR_ERR(priv->addr); 2062 goto out_release; 2063 } 2064 2065 spin_lock_init(&priv->lock); 2066 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2067 2068 priv->phy_interface = of_get_phy_mode(np); 2069 2070 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2071 priv->avb_link_active_low = 2072 of_property_read_bool(np, "renesas,ether-link-active-low"); 2073 2074 if (chip_id == RCAR_GEN3) { 2075 irq = platform_get_irq_byname(pdev, "ch24"); 2076 if (irq < 0) { 2077 error = irq; 2078 goto out_release; 2079 } 2080 priv->emac_irq = irq; 2081 for (i = 0; i < NUM_RX_QUEUE; i++) { 2082 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2083 if (irq < 0) { 2084 error = irq; 2085 goto out_release; 2086 } 2087 priv->rx_irqs[i] = irq; 2088 } 2089 for (i = 0; i < NUM_TX_QUEUE; i++) { 2090 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2091 if (irq < 0) { 2092 error = irq; 2093 goto out_release; 2094 } 2095 priv->tx_irqs[i] = irq; 2096 } 2097 } 2098 2099 priv->chip_id = chip_id; 2100 2101 priv->clk = devm_clk_get(&pdev->dev, NULL); 2102 if (IS_ERR(priv->clk)) { 2103 error = PTR_ERR(priv->clk); 2104 goto out_release; 2105 } 2106 2107 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2108 ndev->min_mtu = ETH_MIN_MTU; 2109 2110 priv->num_tx_desc = chip_id == RCAR_GEN2 ? 2111 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3; 2112 2113 /* Set function */ 2114 ndev->netdev_ops = &ravb_netdev_ops; 2115 ndev->ethtool_ops = &ravb_ethtool_ops; 2116 2117 /* Set AVB config mode */ 2118 ravb_set_config_mode(ndev); 2119 2120 /* Set GTI value */ 2121 error = ravb_set_gti(ndev); 2122 if (error) 2123 goto out_release; 2124 2125 /* Request GTI loading */ 2126 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2127 2128 if (priv->chip_id != RCAR_GEN2) 2129 ravb_set_delay_mode(ndev); 2130 2131 /* Allocate descriptor base address table */ 2132 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2133 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2134 &priv->desc_bat_dma, GFP_KERNEL); 2135 if (!priv->desc_bat) { 2136 dev_err(&pdev->dev, 2137 "Cannot allocate desc base address table (size %d bytes)\n", 2138 priv->desc_bat_size); 2139 error = -ENOMEM; 2140 goto out_release; 2141 } 2142 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2143 priv->desc_bat[q].die_dt = DT_EOS; 2144 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2145 2146 /* Initialise HW timestamp list */ 2147 INIT_LIST_HEAD(&priv->ts_skb_list); 2148 2149 /* Initialise PTP Clock driver */ 2150 if (chip_id != RCAR_GEN2) 2151 ravb_ptp_init(ndev, pdev); 2152 2153 /* Debug message level */ 2154 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2155 2156 /* Read and set MAC address */ 2157 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2158 if (!is_valid_ether_addr(ndev->dev_addr)) { 2159 dev_warn(&pdev->dev, 2160 "no valid MAC address supplied, using a random one\n"); 2161 eth_hw_addr_random(ndev); 2162 } 2163 2164 /* MDIO bus init */ 2165 error = ravb_mdio_init(priv); 2166 if (error) { 2167 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2168 goto out_dma_free; 2169 } 2170 2171 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2172 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2173 2174 /* Network device register */ 2175 error = register_netdev(ndev); 2176 if (error) 2177 goto out_napi_del; 2178 2179 device_set_wakeup_capable(&pdev->dev, 1); 2180 2181 /* Print device information */ 2182 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2183 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2184 2185 platform_set_drvdata(pdev, ndev); 2186 2187 return 0; 2188 2189 out_napi_del: 2190 netif_napi_del(&priv->napi[RAVB_NC]); 2191 netif_napi_del(&priv->napi[RAVB_BE]); 2192 ravb_mdio_release(priv); 2193 out_dma_free: 2194 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2195 priv->desc_bat_dma); 2196 2197 /* Stop PTP Clock driver */ 2198 if (chip_id != RCAR_GEN2) 2199 ravb_ptp_stop(ndev); 2200 out_release: 2201 free_netdev(ndev); 2202 2203 pm_runtime_put(&pdev->dev); 2204 pm_runtime_disable(&pdev->dev); 2205 return error; 2206 } 2207 2208 static int ravb_remove(struct platform_device *pdev) 2209 { 2210 struct net_device *ndev = platform_get_drvdata(pdev); 2211 struct ravb_private *priv = netdev_priv(ndev); 2212 2213 /* Stop PTP Clock driver */ 2214 if (priv->chip_id != RCAR_GEN2) 2215 ravb_ptp_stop(ndev); 2216 2217 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2218 priv->desc_bat_dma); 2219 /* Set reset mode */ 2220 ravb_write(ndev, CCC_OPC_RESET, CCC); 2221 pm_runtime_put_sync(&pdev->dev); 2222 unregister_netdev(ndev); 2223 netif_napi_del(&priv->napi[RAVB_NC]); 2224 netif_napi_del(&priv->napi[RAVB_BE]); 2225 ravb_mdio_release(priv); 2226 pm_runtime_disable(&pdev->dev); 2227 free_netdev(ndev); 2228 platform_set_drvdata(pdev, NULL); 2229 2230 return 0; 2231 } 2232 2233 static int ravb_wol_setup(struct net_device *ndev) 2234 { 2235 struct ravb_private *priv = netdev_priv(ndev); 2236 2237 /* Disable interrupts by clearing the interrupt masks. */ 2238 ravb_write(ndev, 0, RIC0); 2239 ravb_write(ndev, 0, RIC2); 2240 ravb_write(ndev, 0, TIC); 2241 2242 /* Only allow ECI interrupts */ 2243 synchronize_irq(priv->emac_irq); 2244 napi_disable(&priv->napi[RAVB_NC]); 2245 napi_disable(&priv->napi[RAVB_BE]); 2246 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2247 2248 /* Enable MagicPacket */ 2249 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2250 2251 return enable_irq_wake(priv->emac_irq); 2252 } 2253 2254 static int ravb_wol_restore(struct net_device *ndev) 2255 { 2256 struct ravb_private *priv = netdev_priv(ndev); 2257 int ret; 2258 2259 napi_enable(&priv->napi[RAVB_NC]); 2260 napi_enable(&priv->napi[RAVB_BE]); 2261 2262 /* Disable MagicPacket */ 2263 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2264 2265 ret = ravb_close(ndev); 2266 if (ret < 0) 2267 return ret; 2268 2269 return disable_irq_wake(priv->emac_irq); 2270 } 2271 2272 static int __maybe_unused ravb_suspend(struct device *dev) 2273 { 2274 struct net_device *ndev = dev_get_drvdata(dev); 2275 struct ravb_private *priv = netdev_priv(ndev); 2276 int ret; 2277 2278 if (!netif_running(ndev)) 2279 return 0; 2280 2281 netif_device_detach(ndev); 2282 2283 if (priv->wol_enabled) 2284 ret = ravb_wol_setup(ndev); 2285 else 2286 ret = ravb_close(ndev); 2287 2288 return ret; 2289 } 2290 2291 static int __maybe_unused ravb_resume(struct device *dev) 2292 { 2293 struct net_device *ndev = dev_get_drvdata(dev); 2294 struct ravb_private *priv = netdev_priv(ndev); 2295 int ret = 0; 2296 2297 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2298 if (priv->wol_enabled) 2299 ravb_write(ndev, CCC_OPC_RESET, CCC); 2300 2301 /* All register have been reset to default values. 2302 * Restore all registers which where setup at probe time and 2303 * reopen device if it was running before system suspended. 2304 */ 2305 2306 /* Set AVB config mode */ 2307 ravb_set_config_mode(ndev); 2308 2309 /* Set GTI value */ 2310 ret = ravb_set_gti(ndev); 2311 if (ret) 2312 return ret; 2313 2314 /* Request GTI loading */ 2315 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2316 2317 if (priv->chip_id != RCAR_GEN2) 2318 ravb_set_delay_mode(ndev); 2319 2320 /* Restore descriptor base address table */ 2321 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2322 2323 if (netif_running(ndev)) { 2324 if (priv->wol_enabled) { 2325 ret = ravb_wol_restore(ndev); 2326 if (ret) 2327 return ret; 2328 } 2329 ret = ravb_open(ndev); 2330 if (ret < 0) 2331 return ret; 2332 netif_device_attach(ndev); 2333 } 2334 2335 return ret; 2336 } 2337 2338 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2339 { 2340 /* Runtime PM callback shared between ->runtime_suspend() 2341 * and ->runtime_resume(). Simply returns success. 2342 * 2343 * This driver re-initializes all registers after 2344 * pm_runtime_get_sync() anyway so there is no need 2345 * to save and restore registers here. 2346 */ 2347 return 0; 2348 } 2349 2350 static const struct dev_pm_ops ravb_dev_pm_ops = { 2351 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2352 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2353 }; 2354 2355 static struct platform_driver ravb_driver = { 2356 .probe = ravb_probe, 2357 .remove = ravb_remove, 2358 .driver = { 2359 .name = "ravb", 2360 .pm = &ravb_dev_pm_ops, 2361 .of_match_table = ravb_match_table, 2362 }, 2363 }; 2364 2365 module_platform_driver(ravb_driver); 2366 2367 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2368 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2369 MODULE_LICENSE("GPL v2"); 2370