1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 33 #include <asm/div64.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46 }; 47 48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51 }; 52 53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55 { 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57 } 58 59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60 { 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69 } 70 71 static int ravb_config(struct net_device *ndev) 72 { 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83 } 84 85 static void ravb_set_rate(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 switch (priv->speed) { 90 case 100: /* 100BASE */ 91 ravb_write(ndev, GECMR_SPEED_100, GECMR); 92 break; 93 case 1000: /* 1000BASE */ 94 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 95 break; 96 } 97 } 98 99 static void ravb_set_buffer_align(struct sk_buff *skb) 100 { 101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 102 103 if (reserve) 104 skb_reserve(skb, RAVB_ALIGN - reserve); 105 } 106 107 /* Get MAC address from the MAC address registers 108 * 109 * Ethernet AVB device doesn't have ROM for MAC address. 110 * This function gets the MAC address that was used by a bootloader. 111 */ 112 static void ravb_read_mac_address(struct device_node *np, 113 struct net_device *ndev) 114 { 115 int ret; 116 117 ret = of_get_mac_address(np, ndev->dev_addr); 118 if (ret) { 119 u32 mahr = ravb_read(ndev, MAHR); 120 u32 malr = ravb_read(ndev, MALR); 121 122 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 123 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 124 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 125 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 126 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 127 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 128 } 129 } 130 131 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 132 { 133 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 134 mdiobb); 135 136 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 137 } 138 139 /* MDC pin control */ 140 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 141 { 142 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 143 } 144 145 /* Data I/O pin control */ 146 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 147 { 148 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 149 } 150 151 /* Set data bit */ 152 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 153 { 154 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 155 } 156 157 /* Get data bit */ 158 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 159 { 160 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 161 mdiobb); 162 163 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 164 } 165 166 /* MDIO bus control struct */ 167 static const struct mdiobb_ops bb_ops = { 168 .owner = THIS_MODULE, 169 .set_mdc = ravb_set_mdc, 170 .set_mdio_dir = ravb_set_mdio_dir, 171 .set_mdio_data = ravb_set_mdio_data, 172 .get_mdio_data = ravb_get_mdio_data, 173 }; 174 175 /* Free TX skb function for AVB-IP */ 176 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 177 { 178 struct ravb_private *priv = netdev_priv(ndev); 179 struct net_device_stats *stats = &priv->stats[q]; 180 int num_tx_desc = priv->num_tx_desc; 181 struct ravb_tx_desc *desc; 182 int free_num = 0; 183 int entry; 184 u32 size; 185 186 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 187 bool txed; 188 189 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 190 num_tx_desc); 191 desc = &priv->tx_ring[q][entry]; 192 txed = desc->die_dt == DT_FEMPTY; 193 if (free_txed_only && !txed) 194 break; 195 /* Descriptor type must be checked before all other reads */ 196 dma_rmb(); 197 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 198 /* Free the original skb. */ 199 if (priv->tx_skb[q][entry / num_tx_desc]) { 200 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 201 size, DMA_TO_DEVICE); 202 /* Last packet descriptor? */ 203 if (entry % num_tx_desc == num_tx_desc - 1) { 204 entry /= num_tx_desc; 205 dev_kfree_skb_any(priv->tx_skb[q][entry]); 206 priv->tx_skb[q][entry] = NULL; 207 if (txed) 208 stats->tx_packets++; 209 } 210 free_num++; 211 } 212 if (txed) 213 stats->tx_bytes += size; 214 desc->die_dt = DT_EEMPTY; 215 } 216 return free_num; 217 } 218 219 /* Free skb's and DMA buffers for Ethernet AVB */ 220 static void ravb_ring_free(struct net_device *ndev, int q) 221 { 222 struct ravb_private *priv = netdev_priv(ndev); 223 int num_tx_desc = priv->num_tx_desc; 224 int ring_size; 225 int i; 226 227 if (priv->rx_ring[q]) { 228 for (i = 0; i < priv->num_rx_ring[q]; i++) { 229 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 230 231 if (!dma_mapping_error(ndev->dev.parent, 232 le32_to_cpu(desc->dptr))) 233 dma_unmap_single(ndev->dev.parent, 234 le32_to_cpu(desc->dptr), 235 RX_BUF_SZ, 236 DMA_FROM_DEVICE); 237 } 238 ring_size = sizeof(struct ravb_ex_rx_desc) * 239 (priv->num_rx_ring[q] + 1); 240 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 241 priv->rx_desc_dma[q]); 242 priv->rx_ring[q] = NULL; 243 } 244 245 if (priv->tx_ring[q]) { 246 ravb_tx_free(ndev, q, false); 247 248 ring_size = sizeof(struct ravb_tx_desc) * 249 (priv->num_tx_ring[q] * num_tx_desc + 1); 250 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 251 priv->tx_desc_dma[q]); 252 priv->tx_ring[q] = NULL; 253 } 254 255 /* Free RX skb ringbuffer */ 256 if (priv->rx_skb[q]) { 257 for (i = 0; i < priv->num_rx_ring[q]; i++) 258 dev_kfree_skb(priv->rx_skb[q][i]); 259 } 260 kfree(priv->rx_skb[q]); 261 priv->rx_skb[q] = NULL; 262 263 /* Free aligned TX buffers */ 264 kfree(priv->tx_align[q]); 265 priv->tx_align[q] = NULL; 266 267 /* Free TX skb ringbuffer. 268 * SKBs are freed by ravb_tx_free() call above. 269 */ 270 kfree(priv->tx_skb[q]); 271 priv->tx_skb[q] = NULL; 272 } 273 274 /* Format skb and descriptor buffer for Ethernet AVB */ 275 static void ravb_ring_format(struct net_device *ndev, int q) 276 { 277 struct ravb_private *priv = netdev_priv(ndev); 278 int num_tx_desc = priv->num_tx_desc; 279 struct ravb_ex_rx_desc *rx_desc; 280 struct ravb_tx_desc *tx_desc; 281 struct ravb_desc *desc; 282 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 283 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 284 num_tx_desc; 285 dma_addr_t dma_addr; 286 int i; 287 288 priv->cur_rx[q] = 0; 289 priv->cur_tx[q] = 0; 290 priv->dirty_rx[q] = 0; 291 priv->dirty_tx[q] = 0; 292 293 memset(priv->rx_ring[q], 0, rx_ring_size); 294 /* Build RX ring buffer */ 295 for (i = 0; i < priv->num_rx_ring[q]; i++) { 296 /* RX descriptor */ 297 rx_desc = &priv->rx_ring[q][i]; 298 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 299 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 300 RX_BUF_SZ, 301 DMA_FROM_DEVICE); 302 /* We just set the data size to 0 for a failed mapping which 303 * should prevent DMA from happening... 304 */ 305 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 306 rx_desc->ds_cc = cpu_to_le16(0); 307 rx_desc->dptr = cpu_to_le32(dma_addr); 308 rx_desc->die_dt = DT_FEMPTY; 309 } 310 rx_desc = &priv->rx_ring[q][i]; 311 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 312 rx_desc->die_dt = DT_LINKFIX; /* type */ 313 314 memset(priv->tx_ring[q], 0, tx_ring_size); 315 /* Build TX ring buffer */ 316 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 317 i++, tx_desc++) { 318 tx_desc->die_dt = DT_EEMPTY; 319 if (num_tx_desc > 1) { 320 tx_desc++; 321 tx_desc->die_dt = DT_EEMPTY; 322 } 323 } 324 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 325 tx_desc->die_dt = DT_LINKFIX; /* type */ 326 327 /* RX descriptor base address for best effort */ 328 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 329 desc->die_dt = DT_LINKFIX; /* type */ 330 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 331 332 /* TX descriptor base address for best effort */ 333 desc = &priv->desc_bat[q]; 334 desc->die_dt = DT_LINKFIX; /* type */ 335 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 336 } 337 338 /* Init skb and descriptor buffer for Ethernet AVB */ 339 static int ravb_ring_init(struct net_device *ndev, int q) 340 { 341 struct ravb_private *priv = netdev_priv(ndev); 342 int num_tx_desc = priv->num_tx_desc; 343 struct sk_buff *skb; 344 int ring_size; 345 int i; 346 347 /* Allocate RX and TX skb rings */ 348 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 349 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 350 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 351 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 352 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 353 goto error; 354 355 for (i = 0; i < priv->num_rx_ring[q]; i++) { 356 skb = netdev_alloc_skb(ndev, RX_BUF_SZ + RAVB_ALIGN - 1); 357 if (!skb) 358 goto error; 359 ravb_set_buffer_align(skb); 360 priv->rx_skb[q][i] = skb; 361 } 362 363 if (num_tx_desc > 1) { 364 /* Allocate rings for the aligned buffers */ 365 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 366 DPTR_ALIGN - 1, GFP_KERNEL); 367 if (!priv->tx_align[q]) 368 goto error; 369 } 370 371 /* Allocate all RX descriptors. */ 372 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 373 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 374 &priv->rx_desc_dma[q], 375 GFP_KERNEL); 376 if (!priv->rx_ring[q]) 377 goto error; 378 379 priv->dirty_rx[q] = 0; 380 381 /* Allocate all TX descriptors. */ 382 ring_size = sizeof(struct ravb_tx_desc) * 383 (priv->num_tx_ring[q] * num_tx_desc + 1); 384 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 385 &priv->tx_desc_dma[q], 386 GFP_KERNEL); 387 if (!priv->tx_ring[q]) 388 goto error; 389 390 return 0; 391 392 error: 393 ravb_ring_free(ndev, q); 394 395 return -ENOMEM; 396 } 397 398 /* E-MAC init function */ 399 static void ravb_emac_init(struct net_device *ndev) 400 { 401 /* Receive frame limit set register */ 402 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 403 404 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 405 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 406 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 407 ECMR_TE | ECMR_RE, ECMR); 408 409 ravb_set_rate(ndev); 410 411 /* Set MAC address */ 412 ravb_write(ndev, 413 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 414 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 415 ravb_write(ndev, 416 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 417 418 /* E-MAC status register clear */ 419 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 420 421 /* E-MAC interrupt enable register */ 422 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 423 } 424 425 /* Device init function for Ethernet AVB */ 426 static int ravb_dmac_init(struct net_device *ndev) 427 { 428 struct ravb_private *priv = netdev_priv(ndev); 429 int error; 430 431 /* Set CONFIG mode */ 432 error = ravb_config(ndev); 433 if (error) 434 return error; 435 436 error = ravb_ring_init(ndev, RAVB_BE); 437 if (error) 438 return error; 439 error = ravb_ring_init(ndev, RAVB_NC); 440 if (error) { 441 ravb_ring_free(ndev, RAVB_BE); 442 return error; 443 } 444 445 /* Descriptor format */ 446 ravb_ring_format(ndev, RAVB_BE); 447 ravb_ring_format(ndev, RAVB_NC); 448 449 /* Set AVB RX */ 450 ravb_write(ndev, 451 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 452 453 /* Set FIFO size */ 454 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 455 456 /* Timestamp enable */ 457 ravb_write(ndev, TCCR_TFEN, TCCR); 458 459 /* Interrupt init: */ 460 if (priv->chip_id == RCAR_GEN3) { 461 /* Clear DIL.DPLx */ 462 ravb_write(ndev, 0, DIL); 463 /* Set queue specific interrupt */ 464 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 465 } 466 /* Frame receive */ 467 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 468 /* Disable FIFO full warning */ 469 ravb_write(ndev, 0, RIC1); 470 /* Receive FIFO full error, descriptor empty */ 471 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 472 /* Frame transmitted, timestamp FIFO updated */ 473 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 474 475 /* Setting the control will start the AVB-DMAC process. */ 476 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 477 478 return 0; 479 } 480 481 static void ravb_get_tx_tstamp(struct net_device *ndev) 482 { 483 struct ravb_private *priv = netdev_priv(ndev); 484 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 485 struct skb_shared_hwtstamps shhwtstamps; 486 struct sk_buff *skb; 487 struct timespec64 ts; 488 u16 tag, tfa_tag; 489 int count; 490 u32 tfa2; 491 492 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 493 while (count--) { 494 tfa2 = ravb_read(ndev, TFA2); 495 tfa_tag = (tfa2 & TFA2_TST) >> 16; 496 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 497 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 498 ravb_read(ndev, TFA1); 499 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 500 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 501 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 502 list) { 503 skb = ts_skb->skb; 504 tag = ts_skb->tag; 505 list_del(&ts_skb->list); 506 kfree(ts_skb); 507 if (tag == tfa_tag) { 508 skb_tstamp_tx(skb, &shhwtstamps); 509 dev_consume_skb_any(skb); 510 break; 511 } else { 512 dev_kfree_skb_any(skb); 513 } 514 } 515 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 516 } 517 } 518 519 static void ravb_rx_csum(struct sk_buff *skb) 520 { 521 u8 *hw_csum; 522 523 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 524 * appended to packet data 525 */ 526 if (unlikely(skb->len < sizeof(__sum16))) 527 return; 528 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 529 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 530 skb->ip_summed = CHECKSUM_COMPLETE; 531 skb_trim(skb, skb->len - sizeof(__sum16)); 532 } 533 534 /* Packet receive function for Ethernet AVB */ 535 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 536 { 537 struct ravb_private *priv = netdev_priv(ndev); 538 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 539 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 540 priv->cur_rx[q]; 541 struct net_device_stats *stats = &priv->stats[q]; 542 struct ravb_ex_rx_desc *desc; 543 struct sk_buff *skb; 544 dma_addr_t dma_addr; 545 struct timespec64 ts; 546 u8 desc_status; 547 u16 pkt_len; 548 int limit; 549 550 boguscnt = min(boguscnt, *quota); 551 limit = boguscnt; 552 desc = &priv->rx_ring[q][entry]; 553 while (desc->die_dt != DT_FEMPTY) { 554 /* Descriptor type must be checked before all other reads */ 555 dma_rmb(); 556 desc_status = desc->msc; 557 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 558 559 if (--boguscnt < 0) 560 break; 561 562 /* We use 0-byte descriptors to mark the DMA mapping errors */ 563 if (!pkt_len) 564 continue; 565 566 if (desc_status & MSC_MC) 567 stats->multicast++; 568 569 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 570 MSC_CEEF)) { 571 stats->rx_errors++; 572 if (desc_status & MSC_CRC) 573 stats->rx_crc_errors++; 574 if (desc_status & MSC_RFE) 575 stats->rx_frame_errors++; 576 if (desc_status & (MSC_RTLF | MSC_RTSF)) 577 stats->rx_length_errors++; 578 if (desc_status & MSC_CEEF) 579 stats->rx_missed_errors++; 580 } else { 581 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 582 583 skb = priv->rx_skb[q][entry]; 584 priv->rx_skb[q][entry] = NULL; 585 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 586 RX_BUF_SZ, 587 DMA_FROM_DEVICE); 588 get_ts &= (q == RAVB_NC) ? 589 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 590 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 591 if (get_ts) { 592 struct skb_shared_hwtstamps *shhwtstamps; 593 594 shhwtstamps = skb_hwtstamps(skb); 595 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 596 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 597 32) | le32_to_cpu(desc->ts_sl); 598 ts.tv_nsec = le32_to_cpu(desc->ts_n); 599 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 600 } 601 602 skb_put(skb, pkt_len); 603 skb->protocol = eth_type_trans(skb, ndev); 604 if (ndev->features & NETIF_F_RXCSUM) 605 ravb_rx_csum(skb); 606 napi_gro_receive(&priv->napi[q], skb); 607 stats->rx_packets++; 608 stats->rx_bytes += pkt_len; 609 } 610 611 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 612 desc = &priv->rx_ring[q][entry]; 613 } 614 615 /* Refill the RX ring buffers. */ 616 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 617 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 618 desc = &priv->rx_ring[q][entry]; 619 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 620 621 if (!priv->rx_skb[q][entry]) { 622 skb = netdev_alloc_skb(ndev, 623 RX_BUF_SZ + 624 RAVB_ALIGN - 1); 625 if (!skb) 626 break; /* Better luck next round. */ 627 ravb_set_buffer_align(skb); 628 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 629 le16_to_cpu(desc->ds_cc), 630 DMA_FROM_DEVICE); 631 skb_checksum_none_assert(skb); 632 /* We just set the data size to 0 for a failed mapping 633 * which should prevent DMA from happening... 634 */ 635 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 636 desc->ds_cc = cpu_to_le16(0); 637 desc->dptr = cpu_to_le32(dma_addr); 638 priv->rx_skb[q][entry] = skb; 639 } 640 /* Descriptor type must be set after all the above writes */ 641 dma_wmb(); 642 desc->die_dt = DT_FEMPTY; 643 } 644 645 *quota -= limit - (++boguscnt); 646 647 return boguscnt <= 0; 648 } 649 650 static void ravb_rcv_snd_disable(struct net_device *ndev) 651 { 652 /* Disable TX and RX */ 653 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 654 } 655 656 static void ravb_rcv_snd_enable(struct net_device *ndev) 657 { 658 /* Enable TX and RX */ 659 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 660 } 661 662 /* function for waiting dma process finished */ 663 static int ravb_stop_dma(struct net_device *ndev) 664 { 665 int error; 666 667 /* Wait for stopping the hardware TX process */ 668 error = ravb_wait(ndev, TCCR, 669 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 670 if (error) 671 return error; 672 673 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 674 0); 675 if (error) 676 return error; 677 678 /* Stop the E-MAC's RX/TX processes. */ 679 ravb_rcv_snd_disable(ndev); 680 681 /* Wait for stopping the RX DMA process */ 682 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 683 if (error) 684 return error; 685 686 /* Stop AVB-DMAC process */ 687 return ravb_config(ndev); 688 } 689 690 /* E-MAC interrupt handler */ 691 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 692 { 693 struct ravb_private *priv = netdev_priv(ndev); 694 u32 ecsr, psr; 695 696 ecsr = ravb_read(ndev, ECSR); 697 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 698 699 if (ecsr & ECSR_MPD) 700 pm_wakeup_event(&priv->pdev->dev, 0); 701 if (ecsr & ECSR_ICD) 702 ndev->stats.tx_carrier_errors++; 703 if (ecsr & ECSR_LCHNG) { 704 /* Link changed */ 705 if (priv->no_avb_link) 706 return; 707 psr = ravb_read(ndev, PSR); 708 if (priv->avb_link_active_low) 709 psr ^= PSR_LMON; 710 if (!(psr & PSR_LMON)) { 711 /* DIsable RX and TX */ 712 ravb_rcv_snd_disable(ndev); 713 } else { 714 /* Enable RX and TX */ 715 ravb_rcv_snd_enable(ndev); 716 } 717 } 718 } 719 720 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 721 { 722 struct net_device *ndev = dev_id; 723 struct ravb_private *priv = netdev_priv(ndev); 724 725 spin_lock(&priv->lock); 726 ravb_emac_interrupt_unlocked(ndev); 727 spin_unlock(&priv->lock); 728 return IRQ_HANDLED; 729 } 730 731 /* Error interrupt handler */ 732 static void ravb_error_interrupt(struct net_device *ndev) 733 { 734 struct ravb_private *priv = netdev_priv(ndev); 735 u32 eis, ris2; 736 737 eis = ravb_read(ndev, EIS); 738 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 739 if (eis & EIS_QFS) { 740 ris2 = ravb_read(ndev, RIS2); 741 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 742 RIS2); 743 744 /* Receive Descriptor Empty int */ 745 if (ris2 & RIS2_QFF0) 746 priv->stats[RAVB_BE].rx_over_errors++; 747 748 /* Receive Descriptor Empty int */ 749 if (ris2 & RIS2_QFF1) 750 priv->stats[RAVB_NC].rx_over_errors++; 751 752 /* Receive FIFO Overflow int */ 753 if (ris2 & RIS2_RFFF) 754 priv->rx_fifo_errors++; 755 } 756 } 757 758 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 759 { 760 struct ravb_private *priv = netdev_priv(ndev); 761 u32 ris0 = ravb_read(ndev, RIS0); 762 u32 ric0 = ravb_read(ndev, RIC0); 763 u32 tis = ravb_read(ndev, TIS); 764 u32 tic = ravb_read(ndev, TIC); 765 766 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 767 if (napi_schedule_prep(&priv->napi[q])) { 768 /* Mask RX and TX interrupts */ 769 if (priv->chip_id == RCAR_GEN2) { 770 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 771 ravb_write(ndev, tic & ~BIT(q), TIC); 772 } else { 773 ravb_write(ndev, BIT(q), RID0); 774 ravb_write(ndev, BIT(q), TID); 775 } 776 __napi_schedule(&priv->napi[q]); 777 } else { 778 netdev_warn(ndev, 779 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 780 ris0, ric0); 781 netdev_warn(ndev, 782 " tx status 0x%08x, tx mask 0x%08x.\n", 783 tis, tic); 784 } 785 return true; 786 } 787 return false; 788 } 789 790 static bool ravb_timestamp_interrupt(struct net_device *ndev) 791 { 792 u32 tis = ravb_read(ndev, TIS); 793 794 if (tis & TIS_TFUF) { 795 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 796 ravb_get_tx_tstamp(ndev); 797 return true; 798 } 799 return false; 800 } 801 802 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 803 { 804 struct net_device *ndev = dev_id; 805 struct ravb_private *priv = netdev_priv(ndev); 806 irqreturn_t result = IRQ_NONE; 807 u32 iss; 808 809 spin_lock(&priv->lock); 810 /* Get interrupt status */ 811 iss = ravb_read(ndev, ISS); 812 813 /* Received and transmitted interrupts */ 814 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 815 int q; 816 817 /* Timestamp updated */ 818 if (ravb_timestamp_interrupt(ndev)) 819 result = IRQ_HANDLED; 820 821 /* Network control and best effort queue RX/TX */ 822 for (q = RAVB_NC; q >= RAVB_BE; q--) { 823 if (ravb_queue_interrupt(ndev, q)) 824 result = IRQ_HANDLED; 825 } 826 } 827 828 /* E-MAC status summary */ 829 if (iss & ISS_MS) { 830 ravb_emac_interrupt_unlocked(ndev); 831 result = IRQ_HANDLED; 832 } 833 834 /* Error status summary */ 835 if (iss & ISS_ES) { 836 ravb_error_interrupt(ndev); 837 result = IRQ_HANDLED; 838 } 839 840 /* gPTP interrupt status summary */ 841 if (iss & ISS_CGIS) { 842 ravb_ptp_interrupt(ndev); 843 result = IRQ_HANDLED; 844 } 845 846 spin_unlock(&priv->lock); 847 return result; 848 } 849 850 /* Timestamp/Error/gPTP interrupt handler */ 851 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 852 { 853 struct net_device *ndev = dev_id; 854 struct ravb_private *priv = netdev_priv(ndev); 855 irqreturn_t result = IRQ_NONE; 856 u32 iss; 857 858 spin_lock(&priv->lock); 859 /* Get interrupt status */ 860 iss = ravb_read(ndev, ISS); 861 862 /* Timestamp updated */ 863 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 864 result = IRQ_HANDLED; 865 866 /* Error status summary */ 867 if (iss & ISS_ES) { 868 ravb_error_interrupt(ndev); 869 result = IRQ_HANDLED; 870 } 871 872 /* gPTP interrupt status summary */ 873 if (iss & ISS_CGIS) { 874 ravb_ptp_interrupt(ndev); 875 result = IRQ_HANDLED; 876 } 877 878 spin_unlock(&priv->lock); 879 return result; 880 } 881 882 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 883 { 884 struct net_device *ndev = dev_id; 885 struct ravb_private *priv = netdev_priv(ndev); 886 irqreturn_t result = IRQ_NONE; 887 888 spin_lock(&priv->lock); 889 890 /* Network control/Best effort queue RX/TX */ 891 if (ravb_queue_interrupt(ndev, q)) 892 result = IRQ_HANDLED; 893 894 spin_unlock(&priv->lock); 895 return result; 896 } 897 898 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 899 { 900 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 901 } 902 903 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 904 { 905 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 906 } 907 908 static int ravb_poll(struct napi_struct *napi, int budget) 909 { 910 struct net_device *ndev = napi->dev; 911 struct ravb_private *priv = netdev_priv(ndev); 912 unsigned long flags; 913 int q = napi - priv->napi; 914 int mask = BIT(q); 915 int quota = budget; 916 u32 ris0, tis; 917 918 for (;;) { 919 tis = ravb_read(ndev, TIS); 920 ris0 = ravb_read(ndev, RIS0); 921 if (!((ris0 & mask) || (tis & mask))) 922 break; 923 924 /* Processing RX Descriptor Ring */ 925 if (ris0 & mask) { 926 /* Clear RX interrupt */ 927 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 928 if (ravb_rx(ndev, "a, q)) 929 goto out; 930 } 931 /* Processing TX Descriptor Ring */ 932 if (tis & mask) { 933 spin_lock_irqsave(&priv->lock, flags); 934 /* Clear TX interrupt */ 935 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 936 ravb_tx_free(ndev, q, true); 937 netif_wake_subqueue(ndev, q); 938 spin_unlock_irqrestore(&priv->lock, flags); 939 } 940 } 941 942 napi_complete(napi); 943 944 /* Re-enable RX/TX interrupts */ 945 spin_lock_irqsave(&priv->lock, flags); 946 if (priv->chip_id == RCAR_GEN2) { 947 ravb_modify(ndev, RIC0, mask, mask); 948 ravb_modify(ndev, TIC, mask, mask); 949 } else { 950 ravb_write(ndev, mask, RIE0); 951 ravb_write(ndev, mask, TIE); 952 } 953 spin_unlock_irqrestore(&priv->lock, flags); 954 955 /* Receive error message handling */ 956 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 957 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 958 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 959 ndev->stats.rx_over_errors = priv->rx_over_errors; 960 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 961 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 962 out: 963 return budget - quota; 964 } 965 966 /* PHY state control function */ 967 static void ravb_adjust_link(struct net_device *ndev) 968 { 969 struct ravb_private *priv = netdev_priv(ndev); 970 struct phy_device *phydev = ndev->phydev; 971 bool new_state = false; 972 unsigned long flags; 973 974 spin_lock_irqsave(&priv->lock, flags); 975 976 /* Disable TX and RX right over here, if E-MAC change is ignored */ 977 if (priv->no_avb_link) 978 ravb_rcv_snd_disable(ndev); 979 980 if (phydev->link) { 981 if (phydev->speed != priv->speed) { 982 new_state = true; 983 priv->speed = phydev->speed; 984 ravb_set_rate(ndev); 985 } 986 if (!priv->link) { 987 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 988 new_state = true; 989 priv->link = phydev->link; 990 } 991 } else if (priv->link) { 992 new_state = true; 993 priv->link = 0; 994 priv->speed = 0; 995 } 996 997 /* Enable TX and RX right over here, if E-MAC change is ignored */ 998 if (priv->no_avb_link && phydev->link) 999 ravb_rcv_snd_enable(ndev); 1000 1001 spin_unlock_irqrestore(&priv->lock, flags); 1002 1003 if (new_state && netif_msg_link(priv)) 1004 phy_print_status(phydev); 1005 } 1006 1007 static const struct soc_device_attribute r8a7795es10[] = { 1008 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1009 { /* sentinel */ } 1010 }; 1011 1012 /* PHY init function */ 1013 static int ravb_phy_init(struct net_device *ndev) 1014 { 1015 struct device_node *np = ndev->dev.parent->of_node; 1016 struct ravb_private *priv = netdev_priv(ndev); 1017 struct phy_device *phydev; 1018 struct device_node *pn; 1019 phy_interface_t iface; 1020 int err; 1021 1022 priv->link = 0; 1023 priv->speed = 0; 1024 1025 /* Try connecting to PHY */ 1026 pn = of_parse_phandle(np, "phy-handle", 0); 1027 if (!pn) { 1028 /* In the case of a fixed PHY, the DT node associated 1029 * to the PHY is the Ethernet MAC DT node. 1030 */ 1031 if (of_phy_is_fixed_link(np)) { 1032 err = of_phy_register_fixed_link(np); 1033 if (err) 1034 return err; 1035 } 1036 pn = of_node_get(np); 1037 } 1038 1039 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1040 : priv->phy_interface; 1041 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1042 of_node_put(pn); 1043 if (!phydev) { 1044 netdev_err(ndev, "failed to connect PHY\n"); 1045 err = -ENOENT; 1046 goto err_deregister_fixed_link; 1047 } 1048 1049 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1050 * at this time. 1051 */ 1052 if (soc_device_match(r8a7795es10)) { 1053 err = phy_set_max_speed(phydev, SPEED_100); 1054 if (err) { 1055 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1056 goto err_phy_disconnect; 1057 } 1058 1059 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1060 } 1061 1062 /* 10BASE, Pause and Asym Pause is not supported */ 1063 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1064 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1065 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1066 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1067 1068 /* Half Duplex is not supported */ 1069 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1070 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1071 1072 phy_attached_info(phydev); 1073 1074 return 0; 1075 1076 err_phy_disconnect: 1077 phy_disconnect(phydev); 1078 err_deregister_fixed_link: 1079 if (of_phy_is_fixed_link(np)) 1080 of_phy_deregister_fixed_link(np); 1081 1082 return err; 1083 } 1084 1085 /* PHY control start function */ 1086 static int ravb_phy_start(struct net_device *ndev) 1087 { 1088 int error; 1089 1090 error = ravb_phy_init(ndev); 1091 if (error) 1092 return error; 1093 1094 phy_start(ndev->phydev); 1095 1096 return 0; 1097 } 1098 1099 static u32 ravb_get_msglevel(struct net_device *ndev) 1100 { 1101 struct ravb_private *priv = netdev_priv(ndev); 1102 1103 return priv->msg_enable; 1104 } 1105 1106 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1107 { 1108 struct ravb_private *priv = netdev_priv(ndev); 1109 1110 priv->msg_enable = value; 1111 } 1112 1113 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1114 "rx_queue_0_current", 1115 "tx_queue_0_current", 1116 "rx_queue_0_dirty", 1117 "tx_queue_0_dirty", 1118 "rx_queue_0_packets", 1119 "tx_queue_0_packets", 1120 "rx_queue_0_bytes", 1121 "tx_queue_0_bytes", 1122 "rx_queue_0_mcast_packets", 1123 "rx_queue_0_errors", 1124 "rx_queue_0_crc_errors", 1125 "rx_queue_0_frame_errors", 1126 "rx_queue_0_length_errors", 1127 "rx_queue_0_missed_errors", 1128 "rx_queue_0_over_errors", 1129 1130 "rx_queue_1_current", 1131 "tx_queue_1_current", 1132 "rx_queue_1_dirty", 1133 "tx_queue_1_dirty", 1134 "rx_queue_1_packets", 1135 "tx_queue_1_packets", 1136 "rx_queue_1_bytes", 1137 "tx_queue_1_bytes", 1138 "rx_queue_1_mcast_packets", 1139 "rx_queue_1_errors", 1140 "rx_queue_1_crc_errors", 1141 "rx_queue_1_frame_errors", 1142 "rx_queue_1_length_errors", 1143 "rx_queue_1_missed_errors", 1144 "rx_queue_1_over_errors", 1145 }; 1146 1147 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1148 1149 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1150 { 1151 switch (sset) { 1152 case ETH_SS_STATS: 1153 return RAVB_STATS_LEN; 1154 default: 1155 return -EOPNOTSUPP; 1156 } 1157 } 1158 1159 static void ravb_get_ethtool_stats(struct net_device *ndev, 1160 struct ethtool_stats *estats, u64 *data) 1161 { 1162 struct ravb_private *priv = netdev_priv(ndev); 1163 int i = 0; 1164 int q; 1165 1166 /* Device-specific stats */ 1167 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1168 struct net_device_stats *stats = &priv->stats[q]; 1169 1170 data[i++] = priv->cur_rx[q]; 1171 data[i++] = priv->cur_tx[q]; 1172 data[i++] = priv->dirty_rx[q]; 1173 data[i++] = priv->dirty_tx[q]; 1174 data[i++] = stats->rx_packets; 1175 data[i++] = stats->tx_packets; 1176 data[i++] = stats->rx_bytes; 1177 data[i++] = stats->tx_bytes; 1178 data[i++] = stats->multicast; 1179 data[i++] = stats->rx_errors; 1180 data[i++] = stats->rx_crc_errors; 1181 data[i++] = stats->rx_frame_errors; 1182 data[i++] = stats->rx_length_errors; 1183 data[i++] = stats->rx_missed_errors; 1184 data[i++] = stats->rx_over_errors; 1185 } 1186 } 1187 1188 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1189 { 1190 switch (stringset) { 1191 case ETH_SS_STATS: 1192 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1193 break; 1194 } 1195 } 1196 1197 static void ravb_get_ringparam(struct net_device *ndev, 1198 struct ethtool_ringparam *ring) 1199 { 1200 struct ravb_private *priv = netdev_priv(ndev); 1201 1202 ring->rx_max_pending = BE_RX_RING_MAX; 1203 ring->tx_max_pending = BE_TX_RING_MAX; 1204 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1205 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1206 } 1207 1208 static int ravb_set_ringparam(struct net_device *ndev, 1209 struct ethtool_ringparam *ring) 1210 { 1211 struct ravb_private *priv = netdev_priv(ndev); 1212 int error; 1213 1214 if (ring->tx_pending > BE_TX_RING_MAX || 1215 ring->rx_pending > BE_RX_RING_MAX || 1216 ring->tx_pending < BE_TX_RING_MIN || 1217 ring->rx_pending < BE_RX_RING_MIN) 1218 return -EINVAL; 1219 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1220 return -EINVAL; 1221 1222 if (netif_running(ndev)) { 1223 netif_device_detach(ndev); 1224 /* Stop PTP Clock driver */ 1225 if (priv->chip_id == RCAR_GEN2) 1226 ravb_ptp_stop(ndev); 1227 /* Wait for DMA stopping */ 1228 error = ravb_stop_dma(ndev); 1229 if (error) { 1230 netdev_err(ndev, 1231 "cannot set ringparam! Any AVB processes are still running?\n"); 1232 return error; 1233 } 1234 synchronize_irq(ndev->irq); 1235 1236 /* Free all the skb's in the RX queue and the DMA buffers. */ 1237 ravb_ring_free(ndev, RAVB_BE); 1238 ravb_ring_free(ndev, RAVB_NC); 1239 } 1240 1241 /* Set new parameters */ 1242 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1243 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1244 1245 if (netif_running(ndev)) { 1246 error = ravb_dmac_init(ndev); 1247 if (error) { 1248 netdev_err(ndev, 1249 "%s: ravb_dmac_init() failed, error %d\n", 1250 __func__, error); 1251 return error; 1252 } 1253 1254 ravb_emac_init(ndev); 1255 1256 /* Initialise PTP Clock driver */ 1257 if (priv->chip_id == RCAR_GEN2) 1258 ravb_ptp_init(ndev, priv->pdev); 1259 1260 netif_device_attach(ndev); 1261 } 1262 1263 return 0; 1264 } 1265 1266 static int ravb_get_ts_info(struct net_device *ndev, 1267 struct ethtool_ts_info *info) 1268 { 1269 struct ravb_private *priv = netdev_priv(ndev); 1270 1271 info->so_timestamping = 1272 SOF_TIMESTAMPING_TX_SOFTWARE | 1273 SOF_TIMESTAMPING_RX_SOFTWARE | 1274 SOF_TIMESTAMPING_SOFTWARE | 1275 SOF_TIMESTAMPING_TX_HARDWARE | 1276 SOF_TIMESTAMPING_RX_HARDWARE | 1277 SOF_TIMESTAMPING_RAW_HARDWARE; 1278 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1279 info->rx_filters = 1280 (1 << HWTSTAMP_FILTER_NONE) | 1281 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1282 (1 << HWTSTAMP_FILTER_ALL); 1283 info->phc_index = ptp_clock_index(priv->ptp.clock); 1284 1285 return 0; 1286 } 1287 1288 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1289 { 1290 struct ravb_private *priv = netdev_priv(ndev); 1291 1292 wol->supported = WAKE_MAGIC; 1293 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1294 } 1295 1296 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1297 { 1298 struct ravb_private *priv = netdev_priv(ndev); 1299 1300 if (wol->wolopts & ~WAKE_MAGIC) 1301 return -EOPNOTSUPP; 1302 1303 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1304 1305 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1306 1307 return 0; 1308 } 1309 1310 static const struct ethtool_ops ravb_ethtool_ops = { 1311 .nway_reset = phy_ethtool_nway_reset, 1312 .get_msglevel = ravb_get_msglevel, 1313 .set_msglevel = ravb_set_msglevel, 1314 .get_link = ethtool_op_get_link, 1315 .get_strings = ravb_get_strings, 1316 .get_ethtool_stats = ravb_get_ethtool_stats, 1317 .get_sset_count = ravb_get_sset_count, 1318 .get_ringparam = ravb_get_ringparam, 1319 .set_ringparam = ravb_set_ringparam, 1320 .get_ts_info = ravb_get_ts_info, 1321 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1322 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1323 .get_wol = ravb_get_wol, 1324 .set_wol = ravb_set_wol, 1325 }; 1326 1327 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1328 struct net_device *ndev, struct device *dev, 1329 const char *ch) 1330 { 1331 char *name; 1332 int error; 1333 1334 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1335 if (!name) 1336 return -ENOMEM; 1337 error = request_irq(irq, handler, 0, name, ndev); 1338 if (error) 1339 netdev_err(ndev, "cannot request IRQ %s\n", name); 1340 1341 return error; 1342 } 1343 1344 /* Network device open function for Ethernet AVB */ 1345 static int ravb_open(struct net_device *ndev) 1346 { 1347 struct ravb_private *priv = netdev_priv(ndev); 1348 struct platform_device *pdev = priv->pdev; 1349 struct device *dev = &pdev->dev; 1350 int error; 1351 1352 napi_enable(&priv->napi[RAVB_BE]); 1353 napi_enable(&priv->napi[RAVB_NC]); 1354 1355 if (priv->chip_id == RCAR_GEN2) { 1356 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1357 ndev->name, ndev); 1358 if (error) { 1359 netdev_err(ndev, "cannot request IRQ\n"); 1360 goto out_napi_off; 1361 } 1362 } else { 1363 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1364 dev, "ch22:multi"); 1365 if (error) 1366 goto out_napi_off; 1367 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1368 dev, "ch24:emac"); 1369 if (error) 1370 goto out_free_irq; 1371 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1372 ndev, dev, "ch0:rx_be"); 1373 if (error) 1374 goto out_free_irq_emac; 1375 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1376 ndev, dev, "ch18:tx_be"); 1377 if (error) 1378 goto out_free_irq_be_rx; 1379 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1380 ndev, dev, "ch1:rx_nc"); 1381 if (error) 1382 goto out_free_irq_be_tx; 1383 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1384 ndev, dev, "ch19:tx_nc"); 1385 if (error) 1386 goto out_free_irq_nc_rx; 1387 } 1388 1389 /* Device init */ 1390 error = ravb_dmac_init(ndev); 1391 if (error) 1392 goto out_free_irq_nc_tx; 1393 ravb_emac_init(ndev); 1394 1395 /* Initialise PTP Clock driver */ 1396 if (priv->chip_id == RCAR_GEN2) 1397 ravb_ptp_init(ndev, priv->pdev); 1398 1399 netif_tx_start_all_queues(ndev); 1400 1401 /* PHY control start */ 1402 error = ravb_phy_start(ndev); 1403 if (error) 1404 goto out_ptp_stop; 1405 1406 return 0; 1407 1408 out_ptp_stop: 1409 /* Stop PTP Clock driver */ 1410 if (priv->chip_id == RCAR_GEN2) 1411 ravb_ptp_stop(ndev); 1412 out_free_irq_nc_tx: 1413 if (priv->chip_id == RCAR_GEN2) 1414 goto out_free_irq; 1415 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1416 out_free_irq_nc_rx: 1417 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1418 out_free_irq_be_tx: 1419 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1420 out_free_irq_be_rx: 1421 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1422 out_free_irq_emac: 1423 free_irq(priv->emac_irq, ndev); 1424 out_free_irq: 1425 free_irq(ndev->irq, ndev); 1426 out_napi_off: 1427 napi_disable(&priv->napi[RAVB_NC]); 1428 napi_disable(&priv->napi[RAVB_BE]); 1429 return error; 1430 } 1431 1432 /* Timeout function for Ethernet AVB */ 1433 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1434 { 1435 struct ravb_private *priv = netdev_priv(ndev); 1436 1437 netif_err(priv, tx_err, ndev, 1438 "transmit timed out, status %08x, resetting...\n", 1439 ravb_read(ndev, ISS)); 1440 1441 /* tx_errors count up */ 1442 ndev->stats.tx_errors++; 1443 1444 schedule_work(&priv->work); 1445 } 1446 1447 static void ravb_tx_timeout_work(struct work_struct *work) 1448 { 1449 struct ravb_private *priv = container_of(work, struct ravb_private, 1450 work); 1451 struct net_device *ndev = priv->ndev; 1452 int error; 1453 1454 netif_tx_stop_all_queues(ndev); 1455 1456 /* Stop PTP Clock driver */ 1457 if (priv->chip_id == RCAR_GEN2) 1458 ravb_ptp_stop(ndev); 1459 1460 /* Wait for DMA stopping */ 1461 if (ravb_stop_dma(ndev)) { 1462 /* If ravb_stop_dma() fails, the hardware is still operating 1463 * for TX and/or RX. So, this should not call the following 1464 * functions because ravb_dmac_init() is possible to fail too. 1465 * Also, this should not retry ravb_stop_dma() again and again 1466 * here because it's possible to wait forever. So, this just 1467 * re-enables the TX and RX and skip the following 1468 * re-initialization procedure. 1469 */ 1470 ravb_rcv_snd_enable(ndev); 1471 goto out; 1472 } 1473 1474 ravb_ring_free(ndev, RAVB_BE); 1475 ravb_ring_free(ndev, RAVB_NC); 1476 1477 /* Device init */ 1478 error = ravb_dmac_init(ndev); 1479 if (error) { 1480 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1481 * should return here to avoid re-enabling the TX and RX in 1482 * ravb_emac_init(). 1483 */ 1484 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1485 __func__, error); 1486 return; 1487 } 1488 ravb_emac_init(ndev); 1489 1490 out: 1491 /* Initialise PTP Clock driver */ 1492 if (priv->chip_id == RCAR_GEN2) 1493 ravb_ptp_init(ndev, priv->pdev); 1494 1495 netif_tx_start_all_queues(ndev); 1496 } 1497 1498 /* Packet transmit function for Ethernet AVB */ 1499 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1500 { 1501 struct ravb_private *priv = netdev_priv(ndev); 1502 int num_tx_desc = priv->num_tx_desc; 1503 u16 q = skb_get_queue_mapping(skb); 1504 struct ravb_tstamp_skb *ts_skb; 1505 struct ravb_tx_desc *desc; 1506 unsigned long flags; 1507 u32 dma_addr; 1508 void *buffer; 1509 u32 entry; 1510 u32 len; 1511 1512 spin_lock_irqsave(&priv->lock, flags); 1513 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1514 num_tx_desc) { 1515 netif_err(priv, tx_queued, ndev, 1516 "still transmitting with the full ring!\n"); 1517 netif_stop_subqueue(ndev, q); 1518 spin_unlock_irqrestore(&priv->lock, flags); 1519 return NETDEV_TX_BUSY; 1520 } 1521 1522 if (skb_put_padto(skb, ETH_ZLEN)) 1523 goto exit; 1524 1525 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1526 priv->tx_skb[q][entry / num_tx_desc] = skb; 1527 1528 if (num_tx_desc > 1) { 1529 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1530 entry / num_tx_desc * DPTR_ALIGN; 1531 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1532 1533 /* Zero length DMA descriptors are problematic as they seem 1534 * to terminate DMA transfers. Avoid them by simply using a 1535 * length of DPTR_ALIGN (4) when skb data is aligned to 1536 * DPTR_ALIGN. 1537 * 1538 * As skb is guaranteed to have at least ETH_ZLEN (60) 1539 * bytes of data by the call to skb_put_padto() above this 1540 * is safe with respect to both the length of the first DMA 1541 * descriptor (len) overflowing the available data and the 1542 * length of the second DMA descriptor (skb->len - len) 1543 * being negative. 1544 */ 1545 if (len == 0) 1546 len = DPTR_ALIGN; 1547 1548 memcpy(buffer, skb->data, len); 1549 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1550 DMA_TO_DEVICE); 1551 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1552 goto drop; 1553 1554 desc = &priv->tx_ring[q][entry]; 1555 desc->ds_tagl = cpu_to_le16(len); 1556 desc->dptr = cpu_to_le32(dma_addr); 1557 1558 buffer = skb->data + len; 1559 len = skb->len - len; 1560 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1561 DMA_TO_DEVICE); 1562 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1563 goto unmap; 1564 1565 desc++; 1566 } else { 1567 desc = &priv->tx_ring[q][entry]; 1568 len = skb->len; 1569 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1570 DMA_TO_DEVICE); 1571 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1572 goto drop; 1573 } 1574 desc->ds_tagl = cpu_to_le16(len); 1575 desc->dptr = cpu_to_le32(dma_addr); 1576 1577 /* TX timestamp required */ 1578 if (q == RAVB_NC) { 1579 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1580 if (!ts_skb) { 1581 if (num_tx_desc > 1) { 1582 desc--; 1583 dma_unmap_single(ndev->dev.parent, dma_addr, 1584 len, DMA_TO_DEVICE); 1585 } 1586 goto unmap; 1587 } 1588 ts_skb->skb = skb_get(skb); 1589 ts_skb->tag = priv->ts_skb_tag++; 1590 priv->ts_skb_tag &= 0x3ff; 1591 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1592 1593 /* TAG and timestamp required flag */ 1594 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1595 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1596 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1597 } 1598 1599 skb_tx_timestamp(skb); 1600 /* Descriptor type must be set after all the above writes */ 1601 dma_wmb(); 1602 if (num_tx_desc > 1) { 1603 desc->die_dt = DT_FEND; 1604 desc--; 1605 desc->die_dt = DT_FSTART; 1606 } else { 1607 desc->die_dt = DT_FSINGLE; 1608 } 1609 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1610 1611 priv->cur_tx[q] += num_tx_desc; 1612 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1613 (priv->num_tx_ring[q] - 1) * num_tx_desc && 1614 !ravb_tx_free(ndev, q, true)) 1615 netif_stop_subqueue(ndev, q); 1616 1617 exit: 1618 spin_unlock_irqrestore(&priv->lock, flags); 1619 return NETDEV_TX_OK; 1620 1621 unmap: 1622 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1623 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1624 drop: 1625 dev_kfree_skb_any(skb); 1626 priv->tx_skb[q][entry / num_tx_desc] = NULL; 1627 goto exit; 1628 } 1629 1630 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1631 struct net_device *sb_dev) 1632 { 1633 /* If skb needs TX timestamp, it is handled in network control queue */ 1634 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1635 RAVB_BE; 1636 1637 } 1638 1639 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1640 { 1641 struct ravb_private *priv = netdev_priv(ndev); 1642 struct net_device_stats *nstats, *stats0, *stats1; 1643 1644 nstats = &ndev->stats; 1645 stats0 = &priv->stats[RAVB_BE]; 1646 stats1 = &priv->stats[RAVB_NC]; 1647 1648 if (priv->chip_id == RCAR_GEN3) { 1649 nstats->tx_dropped += ravb_read(ndev, TROCR); 1650 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1651 } 1652 1653 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1654 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1655 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1656 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1657 nstats->multicast = stats0->multicast + stats1->multicast; 1658 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1659 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1660 nstats->rx_frame_errors = 1661 stats0->rx_frame_errors + stats1->rx_frame_errors; 1662 nstats->rx_length_errors = 1663 stats0->rx_length_errors + stats1->rx_length_errors; 1664 nstats->rx_missed_errors = 1665 stats0->rx_missed_errors + stats1->rx_missed_errors; 1666 nstats->rx_over_errors = 1667 stats0->rx_over_errors + stats1->rx_over_errors; 1668 1669 return nstats; 1670 } 1671 1672 /* Update promiscuous bit */ 1673 static void ravb_set_rx_mode(struct net_device *ndev) 1674 { 1675 struct ravb_private *priv = netdev_priv(ndev); 1676 unsigned long flags; 1677 1678 spin_lock_irqsave(&priv->lock, flags); 1679 ravb_modify(ndev, ECMR, ECMR_PRM, 1680 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1681 spin_unlock_irqrestore(&priv->lock, flags); 1682 } 1683 1684 /* Device close function for Ethernet AVB */ 1685 static int ravb_close(struct net_device *ndev) 1686 { 1687 struct device_node *np = ndev->dev.parent->of_node; 1688 struct ravb_private *priv = netdev_priv(ndev); 1689 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1690 1691 netif_tx_stop_all_queues(ndev); 1692 1693 /* Disable interrupts by clearing the interrupt masks. */ 1694 ravb_write(ndev, 0, RIC0); 1695 ravb_write(ndev, 0, RIC2); 1696 ravb_write(ndev, 0, TIC); 1697 1698 /* Stop PTP Clock driver */ 1699 if (priv->chip_id == RCAR_GEN2) 1700 ravb_ptp_stop(ndev); 1701 1702 /* Set the config mode to stop the AVB-DMAC's processes */ 1703 if (ravb_stop_dma(ndev) < 0) 1704 netdev_err(ndev, 1705 "device will be stopped after h/w processes are done.\n"); 1706 1707 /* Clear the timestamp list */ 1708 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1709 list_del(&ts_skb->list); 1710 kfree_skb(ts_skb->skb); 1711 kfree(ts_skb); 1712 } 1713 1714 /* PHY disconnect */ 1715 if (ndev->phydev) { 1716 phy_stop(ndev->phydev); 1717 phy_disconnect(ndev->phydev); 1718 if (of_phy_is_fixed_link(np)) 1719 of_phy_deregister_fixed_link(np); 1720 } 1721 1722 if (priv->chip_id != RCAR_GEN2) { 1723 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1724 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1725 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1726 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1727 free_irq(priv->emac_irq, ndev); 1728 } 1729 free_irq(ndev->irq, ndev); 1730 1731 napi_disable(&priv->napi[RAVB_NC]); 1732 napi_disable(&priv->napi[RAVB_BE]); 1733 1734 /* Free all the skb's in the RX queue and the DMA buffers. */ 1735 ravb_ring_free(ndev, RAVB_BE); 1736 ravb_ring_free(ndev, RAVB_NC); 1737 1738 return 0; 1739 } 1740 1741 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1742 { 1743 struct ravb_private *priv = netdev_priv(ndev); 1744 struct hwtstamp_config config; 1745 1746 config.flags = 0; 1747 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1748 HWTSTAMP_TX_OFF; 1749 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 1750 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 1751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1752 break; 1753 case RAVB_RXTSTAMP_TYPE_ALL: 1754 config.rx_filter = HWTSTAMP_FILTER_ALL; 1755 break; 1756 default: 1757 config.rx_filter = HWTSTAMP_FILTER_NONE; 1758 } 1759 1760 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1761 -EFAULT : 0; 1762 } 1763 1764 /* Control hardware time stamping */ 1765 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1766 { 1767 struct ravb_private *priv = netdev_priv(ndev); 1768 struct hwtstamp_config config; 1769 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1770 u32 tstamp_tx_ctrl; 1771 1772 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1773 return -EFAULT; 1774 1775 /* Reserved for future extensions */ 1776 if (config.flags) 1777 return -EINVAL; 1778 1779 switch (config.tx_type) { 1780 case HWTSTAMP_TX_OFF: 1781 tstamp_tx_ctrl = 0; 1782 break; 1783 case HWTSTAMP_TX_ON: 1784 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1785 break; 1786 default: 1787 return -ERANGE; 1788 } 1789 1790 switch (config.rx_filter) { 1791 case HWTSTAMP_FILTER_NONE: 1792 tstamp_rx_ctrl = 0; 1793 break; 1794 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1795 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1796 break; 1797 default: 1798 config.rx_filter = HWTSTAMP_FILTER_ALL; 1799 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1800 } 1801 1802 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1803 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1804 1805 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1806 -EFAULT : 0; 1807 } 1808 1809 /* ioctl to device function */ 1810 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1811 { 1812 struct phy_device *phydev = ndev->phydev; 1813 1814 if (!netif_running(ndev)) 1815 return -EINVAL; 1816 1817 if (!phydev) 1818 return -ENODEV; 1819 1820 switch (cmd) { 1821 case SIOCGHWTSTAMP: 1822 return ravb_hwtstamp_get(ndev, req); 1823 case SIOCSHWTSTAMP: 1824 return ravb_hwtstamp_set(ndev, req); 1825 } 1826 1827 return phy_mii_ioctl(phydev, req, cmd); 1828 } 1829 1830 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1831 { 1832 struct ravb_private *priv = netdev_priv(ndev); 1833 1834 ndev->mtu = new_mtu; 1835 1836 if (netif_running(ndev)) { 1837 synchronize_irq(priv->emac_irq); 1838 ravb_emac_init(ndev); 1839 } 1840 1841 netdev_update_features(ndev); 1842 1843 return 0; 1844 } 1845 1846 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1847 { 1848 struct ravb_private *priv = netdev_priv(ndev); 1849 unsigned long flags; 1850 1851 spin_lock_irqsave(&priv->lock, flags); 1852 1853 /* Disable TX and RX */ 1854 ravb_rcv_snd_disable(ndev); 1855 1856 /* Modify RX Checksum setting */ 1857 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1858 1859 /* Enable TX and RX */ 1860 ravb_rcv_snd_enable(ndev); 1861 1862 spin_unlock_irqrestore(&priv->lock, flags); 1863 } 1864 1865 static int ravb_set_features(struct net_device *ndev, 1866 netdev_features_t features) 1867 { 1868 netdev_features_t changed = ndev->features ^ features; 1869 1870 if (changed & NETIF_F_RXCSUM) 1871 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1872 1873 ndev->features = features; 1874 1875 return 0; 1876 } 1877 1878 static const struct net_device_ops ravb_netdev_ops = { 1879 .ndo_open = ravb_open, 1880 .ndo_stop = ravb_close, 1881 .ndo_start_xmit = ravb_start_xmit, 1882 .ndo_select_queue = ravb_select_queue, 1883 .ndo_get_stats = ravb_get_stats, 1884 .ndo_set_rx_mode = ravb_set_rx_mode, 1885 .ndo_tx_timeout = ravb_tx_timeout, 1886 .ndo_do_ioctl = ravb_do_ioctl, 1887 .ndo_change_mtu = ravb_change_mtu, 1888 .ndo_validate_addr = eth_validate_addr, 1889 .ndo_set_mac_address = eth_mac_addr, 1890 .ndo_set_features = ravb_set_features, 1891 }; 1892 1893 /* MDIO bus init function */ 1894 static int ravb_mdio_init(struct ravb_private *priv) 1895 { 1896 struct platform_device *pdev = priv->pdev; 1897 struct device *dev = &pdev->dev; 1898 int error; 1899 1900 /* Bitbang init */ 1901 priv->mdiobb.ops = &bb_ops; 1902 1903 /* MII controller setting */ 1904 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1905 if (!priv->mii_bus) 1906 return -ENOMEM; 1907 1908 /* Hook up MII support for ethtool */ 1909 priv->mii_bus->name = "ravb_mii"; 1910 priv->mii_bus->parent = dev; 1911 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1912 pdev->name, pdev->id); 1913 1914 /* Register MDIO bus */ 1915 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1916 if (error) 1917 goto out_free_bus; 1918 1919 return 0; 1920 1921 out_free_bus: 1922 free_mdio_bitbang(priv->mii_bus); 1923 return error; 1924 } 1925 1926 /* MDIO bus release function */ 1927 static int ravb_mdio_release(struct ravb_private *priv) 1928 { 1929 /* Unregister mdio bus */ 1930 mdiobus_unregister(priv->mii_bus); 1931 1932 /* Free bitbang info */ 1933 free_mdio_bitbang(priv->mii_bus); 1934 1935 return 0; 1936 } 1937 1938 static const struct of_device_id ravb_match_table[] = { 1939 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1940 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1941 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1942 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1943 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1944 { } 1945 }; 1946 MODULE_DEVICE_TABLE(of, ravb_match_table); 1947 1948 static int ravb_set_gti(struct net_device *ndev) 1949 { 1950 struct ravb_private *priv = netdev_priv(ndev); 1951 struct device *dev = ndev->dev.parent; 1952 unsigned long rate; 1953 uint64_t inc; 1954 1955 rate = clk_get_rate(priv->clk); 1956 if (!rate) 1957 return -EINVAL; 1958 1959 inc = 1000000000ULL << 20; 1960 do_div(inc, rate); 1961 1962 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1963 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1964 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1965 return -EINVAL; 1966 } 1967 1968 ravb_write(ndev, inc, GTI); 1969 1970 return 0; 1971 } 1972 1973 static void ravb_set_config_mode(struct net_device *ndev) 1974 { 1975 struct ravb_private *priv = netdev_priv(ndev); 1976 1977 if (priv->chip_id == RCAR_GEN2) { 1978 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1979 /* Set CSEL value */ 1980 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1981 } else { 1982 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1983 CCC_GAC | CCC_CSEL_HPB); 1984 } 1985 } 1986 1987 static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = { 1988 { .soc_id = "r8a774c0" }, 1989 { .soc_id = "r8a77990" }, 1990 { .soc_id = "r8a77995" }, 1991 { /* sentinel */ } 1992 }; 1993 1994 /* Set tx and rx clock internal delay modes */ 1995 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1996 { 1997 struct ravb_private *priv = netdev_priv(ndev); 1998 bool explicit_delay = false; 1999 u32 delay; 2000 2001 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2002 /* Valid values are 0 and 1800, according to DT bindings */ 2003 priv->rxcidm = !!delay; 2004 explicit_delay = true; 2005 } 2006 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2007 /* Valid values are 0 and 2000, according to DT bindings */ 2008 priv->txcidm = !!delay; 2009 explicit_delay = true; 2010 } 2011 2012 if (explicit_delay) 2013 return; 2014 2015 /* Fall back to legacy rgmii-*id behavior */ 2016 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2017 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2018 priv->rxcidm = 1; 2019 priv->rgmii_override = 1; 2020 } 2021 2022 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2023 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2024 if (!WARN(soc_device_match(ravb_delay_mode_quirk_match), 2025 "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree", 2026 phy_modes(priv->phy_interface))) { 2027 priv->txcidm = 1; 2028 priv->rgmii_override = 1; 2029 } 2030 } 2031 } 2032 2033 static void ravb_set_delay_mode(struct net_device *ndev) 2034 { 2035 struct ravb_private *priv = netdev_priv(ndev); 2036 u32 set = 0; 2037 2038 if (priv->rxcidm) 2039 set |= APSR_RDM; 2040 if (priv->txcidm) 2041 set |= APSR_TDM; 2042 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2043 } 2044 2045 static int ravb_probe(struct platform_device *pdev) 2046 { 2047 struct device_node *np = pdev->dev.of_node; 2048 struct ravb_private *priv; 2049 enum ravb_chip_id chip_id; 2050 struct net_device *ndev; 2051 int error, irq, q; 2052 struct resource *res; 2053 int i; 2054 2055 if (!np) { 2056 dev_err(&pdev->dev, 2057 "this driver is required to be instantiated from device tree\n"); 2058 return -EINVAL; 2059 } 2060 2061 /* Get base address */ 2062 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2063 if (!res) { 2064 dev_err(&pdev->dev, "invalid resource\n"); 2065 return -EINVAL; 2066 } 2067 2068 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2069 NUM_TX_QUEUE, NUM_RX_QUEUE); 2070 if (!ndev) 2071 return -ENOMEM; 2072 2073 ndev->features = NETIF_F_RXCSUM; 2074 ndev->hw_features = NETIF_F_RXCSUM; 2075 2076 pm_runtime_enable(&pdev->dev); 2077 pm_runtime_get_sync(&pdev->dev); 2078 2079 /* The Ether-specific entries in the device structure. */ 2080 ndev->base_addr = res->start; 2081 2082 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2083 2084 if (chip_id == RCAR_GEN3) 2085 irq = platform_get_irq_byname(pdev, "ch22"); 2086 else 2087 irq = platform_get_irq(pdev, 0); 2088 if (irq < 0) { 2089 error = irq; 2090 goto out_release; 2091 } 2092 ndev->irq = irq; 2093 2094 SET_NETDEV_DEV(ndev, &pdev->dev); 2095 2096 priv = netdev_priv(ndev); 2097 priv->ndev = ndev; 2098 priv->pdev = pdev; 2099 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2100 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2101 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2102 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2103 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2104 if (IS_ERR(priv->addr)) { 2105 error = PTR_ERR(priv->addr); 2106 goto out_release; 2107 } 2108 2109 spin_lock_init(&priv->lock); 2110 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2111 2112 error = of_get_phy_mode(np, &priv->phy_interface); 2113 if (error && error != -ENODEV) 2114 goto out_release; 2115 2116 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2117 priv->avb_link_active_low = 2118 of_property_read_bool(np, "renesas,ether-link-active-low"); 2119 2120 if (chip_id == RCAR_GEN3) { 2121 irq = platform_get_irq_byname(pdev, "ch24"); 2122 if (irq < 0) { 2123 error = irq; 2124 goto out_release; 2125 } 2126 priv->emac_irq = irq; 2127 for (i = 0; i < NUM_RX_QUEUE; i++) { 2128 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2129 if (irq < 0) { 2130 error = irq; 2131 goto out_release; 2132 } 2133 priv->rx_irqs[i] = irq; 2134 } 2135 for (i = 0; i < NUM_TX_QUEUE; i++) { 2136 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2137 if (irq < 0) { 2138 error = irq; 2139 goto out_release; 2140 } 2141 priv->tx_irqs[i] = irq; 2142 } 2143 } 2144 2145 priv->chip_id = chip_id; 2146 2147 priv->clk = devm_clk_get(&pdev->dev, NULL); 2148 if (IS_ERR(priv->clk)) { 2149 error = PTR_ERR(priv->clk); 2150 goto out_release; 2151 } 2152 2153 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2154 if (IS_ERR(priv->refclk)) { 2155 error = PTR_ERR(priv->refclk); 2156 goto out_release; 2157 } 2158 clk_prepare_enable(priv->refclk); 2159 2160 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2161 ndev->min_mtu = ETH_MIN_MTU; 2162 2163 priv->num_tx_desc = chip_id == RCAR_GEN2 ? 2164 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3; 2165 2166 /* Set function */ 2167 ndev->netdev_ops = &ravb_netdev_ops; 2168 ndev->ethtool_ops = &ravb_ethtool_ops; 2169 2170 /* Set AVB config mode */ 2171 ravb_set_config_mode(ndev); 2172 2173 /* Set GTI value */ 2174 error = ravb_set_gti(ndev); 2175 if (error) 2176 goto out_release; 2177 2178 /* Request GTI loading */ 2179 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2180 2181 if (priv->chip_id != RCAR_GEN2) { 2182 ravb_parse_delay_mode(np, ndev); 2183 ravb_set_delay_mode(ndev); 2184 } 2185 2186 /* Allocate descriptor base address table */ 2187 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2188 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2189 &priv->desc_bat_dma, GFP_KERNEL); 2190 if (!priv->desc_bat) { 2191 dev_err(&pdev->dev, 2192 "Cannot allocate desc base address table (size %d bytes)\n", 2193 priv->desc_bat_size); 2194 error = -ENOMEM; 2195 goto out_release; 2196 } 2197 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2198 priv->desc_bat[q].die_dt = DT_EOS; 2199 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2200 2201 /* Initialise HW timestamp list */ 2202 INIT_LIST_HEAD(&priv->ts_skb_list); 2203 2204 /* Initialise PTP Clock driver */ 2205 if (chip_id != RCAR_GEN2) 2206 ravb_ptp_init(ndev, pdev); 2207 2208 /* Debug message level */ 2209 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2210 2211 /* Read and set MAC address */ 2212 ravb_read_mac_address(np, ndev); 2213 if (!is_valid_ether_addr(ndev->dev_addr)) { 2214 dev_warn(&pdev->dev, 2215 "no valid MAC address supplied, using a random one\n"); 2216 eth_hw_addr_random(ndev); 2217 } 2218 2219 /* MDIO bus init */ 2220 error = ravb_mdio_init(priv); 2221 if (error) { 2222 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2223 goto out_dma_free; 2224 } 2225 2226 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2227 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2228 2229 /* Network device register */ 2230 error = register_netdev(ndev); 2231 if (error) 2232 goto out_napi_del; 2233 2234 device_set_wakeup_capable(&pdev->dev, 1); 2235 2236 /* Print device information */ 2237 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2238 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2239 2240 platform_set_drvdata(pdev, ndev); 2241 2242 return 0; 2243 2244 out_napi_del: 2245 netif_napi_del(&priv->napi[RAVB_NC]); 2246 netif_napi_del(&priv->napi[RAVB_BE]); 2247 ravb_mdio_release(priv); 2248 out_dma_free: 2249 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2250 priv->desc_bat_dma); 2251 2252 /* Stop PTP Clock driver */ 2253 if (chip_id != RCAR_GEN2) 2254 ravb_ptp_stop(ndev); 2255 out_release: 2256 clk_disable_unprepare(priv->refclk); 2257 free_netdev(ndev); 2258 2259 pm_runtime_put(&pdev->dev); 2260 pm_runtime_disable(&pdev->dev); 2261 return error; 2262 } 2263 2264 static int ravb_remove(struct platform_device *pdev) 2265 { 2266 struct net_device *ndev = platform_get_drvdata(pdev); 2267 struct ravb_private *priv = netdev_priv(ndev); 2268 2269 /* Stop PTP Clock driver */ 2270 if (priv->chip_id != RCAR_GEN2) 2271 ravb_ptp_stop(ndev); 2272 2273 clk_disable_unprepare(priv->refclk); 2274 2275 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2276 priv->desc_bat_dma); 2277 /* Set reset mode */ 2278 ravb_write(ndev, CCC_OPC_RESET, CCC); 2279 pm_runtime_put_sync(&pdev->dev); 2280 unregister_netdev(ndev); 2281 netif_napi_del(&priv->napi[RAVB_NC]); 2282 netif_napi_del(&priv->napi[RAVB_BE]); 2283 ravb_mdio_release(priv); 2284 pm_runtime_disable(&pdev->dev); 2285 free_netdev(ndev); 2286 platform_set_drvdata(pdev, NULL); 2287 2288 return 0; 2289 } 2290 2291 static int ravb_wol_setup(struct net_device *ndev) 2292 { 2293 struct ravb_private *priv = netdev_priv(ndev); 2294 2295 /* Disable interrupts by clearing the interrupt masks. */ 2296 ravb_write(ndev, 0, RIC0); 2297 ravb_write(ndev, 0, RIC2); 2298 ravb_write(ndev, 0, TIC); 2299 2300 /* Only allow ECI interrupts */ 2301 synchronize_irq(priv->emac_irq); 2302 napi_disable(&priv->napi[RAVB_NC]); 2303 napi_disable(&priv->napi[RAVB_BE]); 2304 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2305 2306 /* Enable MagicPacket */ 2307 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2308 2309 return enable_irq_wake(priv->emac_irq); 2310 } 2311 2312 static int ravb_wol_restore(struct net_device *ndev) 2313 { 2314 struct ravb_private *priv = netdev_priv(ndev); 2315 int ret; 2316 2317 napi_enable(&priv->napi[RAVB_NC]); 2318 napi_enable(&priv->napi[RAVB_BE]); 2319 2320 /* Disable MagicPacket */ 2321 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2322 2323 ret = ravb_close(ndev); 2324 if (ret < 0) 2325 return ret; 2326 2327 return disable_irq_wake(priv->emac_irq); 2328 } 2329 2330 static int __maybe_unused ravb_suspend(struct device *dev) 2331 { 2332 struct net_device *ndev = dev_get_drvdata(dev); 2333 struct ravb_private *priv = netdev_priv(ndev); 2334 int ret; 2335 2336 if (!netif_running(ndev)) 2337 return 0; 2338 2339 netif_device_detach(ndev); 2340 2341 if (priv->wol_enabled) 2342 ret = ravb_wol_setup(ndev); 2343 else 2344 ret = ravb_close(ndev); 2345 2346 return ret; 2347 } 2348 2349 static int __maybe_unused ravb_resume(struct device *dev) 2350 { 2351 struct net_device *ndev = dev_get_drvdata(dev); 2352 struct ravb_private *priv = netdev_priv(ndev); 2353 int ret = 0; 2354 2355 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2356 if (priv->wol_enabled) 2357 ravb_write(ndev, CCC_OPC_RESET, CCC); 2358 2359 /* All register have been reset to default values. 2360 * Restore all registers which where setup at probe time and 2361 * reopen device if it was running before system suspended. 2362 */ 2363 2364 /* Set AVB config mode */ 2365 ravb_set_config_mode(ndev); 2366 2367 /* Set GTI value */ 2368 ret = ravb_set_gti(ndev); 2369 if (ret) 2370 return ret; 2371 2372 /* Request GTI loading */ 2373 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2374 2375 if (priv->chip_id != RCAR_GEN2) 2376 ravb_set_delay_mode(ndev); 2377 2378 /* Restore descriptor base address table */ 2379 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2380 2381 if (netif_running(ndev)) { 2382 if (priv->wol_enabled) { 2383 ret = ravb_wol_restore(ndev); 2384 if (ret) 2385 return ret; 2386 } 2387 ret = ravb_open(ndev); 2388 if (ret < 0) 2389 return ret; 2390 netif_device_attach(ndev); 2391 } 2392 2393 return ret; 2394 } 2395 2396 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2397 { 2398 /* Runtime PM callback shared between ->runtime_suspend() 2399 * and ->runtime_resume(). Simply returns success. 2400 * 2401 * This driver re-initializes all registers after 2402 * pm_runtime_get_sync() anyway so there is no need 2403 * to save and restore registers here. 2404 */ 2405 return 0; 2406 } 2407 2408 static const struct dev_pm_ops ravb_dev_pm_ops = { 2409 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2410 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2411 }; 2412 2413 static struct platform_driver ravb_driver = { 2414 .probe = ravb_probe, 2415 .remove = ravb_remove, 2416 .driver = { 2417 .name = "ravb", 2418 .pm = &ravb_dev_pm_ops, 2419 .of_match_table = ravb_match_table, 2420 }, 2421 }; 2422 2423 module_platform_driver(ravb_driver); 2424 2425 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2426 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2427 MODULE_LICENSE("GPL v2"); 2428