1 /* Renesas Ethernet AVB device driver 2 * 3 * Copyright (C) 2014-2015 Renesas Electronics Corporation 4 * Copyright (C) 2015 Renesas Solutions Corp. 5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 6 * 7 * Based on the SuperH Ethernet driver 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License version 2, 11 * as published by the Free Software Foundation. 12 */ 13 14 #include <linux/cache.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/err.h> 19 #include <linux/etherdevice.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/kernel.h> 23 #include <linux/list.h> 24 #include <linux/module.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_mdio.h> 30 #include <linux/of_net.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 35 #include <asm/div64.h> 36 37 #include "ravb.h" 38 39 #define RAVB_DEF_MSG_ENABLE \ 40 (NETIF_MSG_LINK | \ 41 NETIF_MSG_TIMER | \ 42 NETIF_MSG_RX_ERR | \ 43 NETIF_MSG_TX_ERR) 44 45 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 46 "ch0", /* RAVB_BE */ 47 "ch1", /* RAVB_NC */ 48 }; 49 50 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 51 "ch18", /* RAVB_BE */ 52 "ch19", /* RAVB_NC */ 53 }; 54 55 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 56 u32 set) 57 { 58 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 59 } 60 61 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 62 { 63 int i; 64 65 for (i = 0; i < 10000; i++) { 66 if ((ravb_read(ndev, reg) & mask) == value) 67 return 0; 68 udelay(10); 69 } 70 return -ETIMEDOUT; 71 } 72 73 static int ravb_config(struct net_device *ndev) 74 { 75 int error; 76 77 /* Set config mode */ 78 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 79 /* Check if the operating mode is changed to the config mode */ 80 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 81 if (error) 82 netdev_err(ndev, "failed to switch device to config mode\n"); 83 84 return error; 85 } 86 87 static void ravb_set_duplex(struct net_device *ndev) 88 { 89 struct ravb_private *priv = netdev_priv(ndev); 90 91 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); 92 } 93 94 static void ravb_set_rate(struct net_device *ndev) 95 { 96 struct ravb_private *priv = netdev_priv(ndev); 97 98 switch (priv->speed) { 99 case 100: /* 100BASE */ 100 ravb_write(ndev, GECMR_SPEED_100, GECMR); 101 break; 102 case 1000: /* 1000BASE */ 103 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 104 break; 105 } 106 } 107 108 static void ravb_set_buffer_align(struct sk_buff *skb) 109 { 110 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 111 112 if (reserve) 113 skb_reserve(skb, RAVB_ALIGN - reserve); 114 } 115 116 /* Get MAC address from the MAC address registers 117 * 118 * Ethernet AVB device doesn't have ROM for MAC address. 119 * This function gets the MAC address that was used by a bootloader. 120 */ 121 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 122 { 123 if (mac) { 124 ether_addr_copy(ndev->dev_addr, mac); 125 } else { 126 u32 mahr = ravb_read(ndev, MAHR); 127 u32 malr = ravb_read(ndev, MALR); 128 129 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 130 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 131 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 132 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 133 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 134 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 135 } 136 } 137 138 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 139 { 140 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 141 mdiobb); 142 143 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 144 } 145 146 /* MDC pin control */ 147 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 148 { 149 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 150 } 151 152 /* Data I/O pin control */ 153 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 154 { 155 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 156 } 157 158 /* Set data bit */ 159 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 160 { 161 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 162 } 163 164 /* Get data bit */ 165 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 166 { 167 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 168 mdiobb); 169 170 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 171 } 172 173 /* MDIO bus control struct */ 174 static struct mdiobb_ops bb_ops = { 175 .owner = THIS_MODULE, 176 .set_mdc = ravb_set_mdc, 177 .set_mdio_dir = ravb_set_mdio_dir, 178 .set_mdio_data = ravb_set_mdio_data, 179 .get_mdio_data = ravb_get_mdio_data, 180 }; 181 182 /* Free skb's and DMA buffers for Ethernet AVB */ 183 static void ravb_ring_free(struct net_device *ndev, int q) 184 { 185 struct ravb_private *priv = netdev_priv(ndev); 186 int ring_size; 187 int i; 188 189 /* Free RX skb ringbuffer */ 190 if (priv->rx_skb[q]) { 191 for (i = 0; i < priv->num_rx_ring[q]; i++) 192 dev_kfree_skb(priv->rx_skb[q][i]); 193 } 194 kfree(priv->rx_skb[q]); 195 priv->rx_skb[q] = NULL; 196 197 /* Free TX skb ringbuffer */ 198 if (priv->tx_skb[q]) { 199 for (i = 0; i < priv->num_tx_ring[q]; i++) 200 dev_kfree_skb(priv->tx_skb[q][i]); 201 } 202 kfree(priv->tx_skb[q]); 203 priv->tx_skb[q] = NULL; 204 205 /* Free aligned TX buffers */ 206 kfree(priv->tx_align[q]); 207 priv->tx_align[q] = NULL; 208 209 if (priv->rx_ring[q]) { 210 ring_size = sizeof(struct ravb_ex_rx_desc) * 211 (priv->num_rx_ring[q] + 1); 212 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 213 priv->rx_desc_dma[q]); 214 priv->rx_ring[q] = NULL; 215 } 216 217 if (priv->tx_ring[q]) { 218 ring_size = sizeof(struct ravb_tx_desc) * 219 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 220 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 221 priv->tx_desc_dma[q]); 222 priv->tx_ring[q] = NULL; 223 } 224 } 225 226 /* Format skb and descriptor buffer for Ethernet AVB */ 227 static void ravb_ring_format(struct net_device *ndev, int q) 228 { 229 struct ravb_private *priv = netdev_priv(ndev); 230 struct ravb_ex_rx_desc *rx_desc; 231 struct ravb_tx_desc *tx_desc; 232 struct ravb_desc *desc; 233 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 234 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 235 NUM_TX_DESC; 236 dma_addr_t dma_addr; 237 int i; 238 239 priv->cur_rx[q] = 0; 240 priv->cur_tx[q] = 0; 241 priv->dirty_rx[q] = 0; 242 priv->dirty_tx[q] = 0; 243 244 memset(priv->rx_ring[q], 0, rx_ring_size); 245 /* Build RX ring buffer */ 246 for (i = 0; i < priv->num_rx_ring[q]; i++) { 247 /* RX descriptor */ 248 rx_desc = &priv->rx_ring[q][i]; 249 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 250 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 251 PKT_BUF_SZ, 252 DMA_FROM_DEVICE); 253 /* We just set the data size to 0 for a failed mapping which 254 * should prevent DMA from happening... 255 */ 256 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 257 rx_desc->ds_cc = cpu_to_le16(0); 258 rx_desc->dptr = cpu_to_le32(dma_addr); 259 rx_desc->die_dt = DT_FEMPTY; 260 } 261 rx_desc = &priv->rx_ring[q][i]; 262 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 263 rx_desc->die_dt = DT_LINKFIX; /* type */ 264 265 memset(priv->tx_ring[q], 0, tx_ring_size); 266 /* Build TX ring buffer */ 267 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 268 i++, tx_desc++) { 269 tx_desc->die_dt = DT_EEMPTY; 270 tx_desc++; 271 tx_desc->die_dt = DT_EEMPTY; 272 } 273 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 274 tx_desc->die_dt = DT_LINKFIX; /* type */ 275 276 /* RX descriptor base address for best effort */ 277 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 278 desc->die_dt = DT_LINKFIX; /* type */ 279 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 280 281 /* TX descriptor base address for best effort */ 282 desc = &priv->desc_bat[q]; 283 desc->die_dt = DT_LINKFIX; /* type */ 284 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 285 } 286 287 /* Init skb and descriptor buffer for Ethernet AVB */ 288 static int ravb_ring_init(struct net_device *ndev, int q) 289 { 290 struct ravb_private *priv = netdev_priv(ndev); 291 struct sk_buff *skb; 292 int ring_size; 293 int i; 294 295 /* Allocate RX and TX skb rings */ 296 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 297 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 298 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 299 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 300 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 301 goto error; 302 303 for (i = 0; i < priv->num_rx_ring[q]; i++) { 304 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); 305 if (!skb) 306 goto error; 307 ravb_set_buffer_align(skb); 308 priv->rx_skb[q][i] = skb; 309 } 310 311 /* Allocate rings for the aligned buffers */ 312 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 313 DPTR_ALIGN - 1, GFP_KERNEL); 314 if (!priv->tx_align[q]) 315 goto error; 316 317 /* Allocate all RX descriptors. */ 318 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 319 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 320 &priv->rx_desc_dma[q], 321 GFP_KERNEL); 322 if (!priv->rx_ring[q]) 323 goto error; 324 325 priv->dirty_rx[q] = 0; 326 327 /* Allocate all TX descriptors. */ 328 ring_size = sizeof(struct ravb_tx_desc) * 329 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 330 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 331 &priv->tx_desc_dma[q], 332 GFP_KERNEL); 333 if (!priv->tx_ring[q]) 334 goto error; 335 336 return 0; 337 338 error: 339 ravb_ring_free(ndev, q); 340 341 return -ENOMEM; 342 } 343 344 /* E-MAC init function */ 345 static void ravb_emac_init(struct net_device *ndev) 346 { 347 struct ravb_private *priv = netdev_priv(ndev); 348 349 /* Receive frame limit set register */ 350 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 351 352 /* PAUSE prohibition */ 353 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 354 ECMR_TE | ECMR_RE, ECMR); 355 356 ravb_set_rate(ndev); 357 358 /* Set MAC address */ 359 ravb_write(ndev, 360 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 361 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 362 ravb_write(ndev, 363 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 364 365 /* E-MAC status register clear */ 366 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 367 368 /* E-MAC interrupt enable register */ 369 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 370 } 371 372 /* Device init function for Ethernet AVB */ 373 static int ravb_dmac_init(struct net_device *ndev) 374 { 375 struct ravb_private *priv = netdev_priv(ndev); 376 int error; 377 378 /* Set CONFIG mode */ 379 error = ravb_config(ndev); 380 if (error) 381 return error; 382 383 error = ravb_ring_init(ndev, RAVB_BE); 384 if (error) 385 return error; 386 error = ravb_ring_init(ndev, RAVB_NC); 387 if (error) { 388 ravb_ring_free(ndev, RAVB_BE); 389 return error; 390 } 391 392 /* Descriptor format */ 393 ravb_ring_format(ndev, RAVB_BE); 394 ravb_ring_format(ndev, RAVB_NC); 395 396 #if defined(__LITTLE_ENDIAN) 397 ravb_modify(ndev, CCC, CCC_BOC, 0); 398 #else 399 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 400 #endif 401 402 /* Set AVB RX */ 403 ravb_write(ndev, 404 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 405 406 /* Set FIFO size */ 407 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 408 409 /* Timestamp enable */ 410 ravb_write(ndev, TCCR_TFEN, TCCR); 411 412 /* Interrupt init: */ 413 if (priv->chip_id == RCAR_GEN3) { 414 /* Clear DIL.DPLx */ 415 ravb_write(ndev, 0, DIL); 416 /* Set queue specific interrupt */ 417 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 418 } 419 /* Frame receive */ 420 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 421 /* Disable FIFO full warning */ 422 ravb_write(ndev, 0, RIC1); 423 /* Receive FIFO full error, descriptor empty */ 424 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 425 /* Frame transmitted, timestamp FIFO updated */ 426 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 427 428 /* Setting the control will start the AVB-DMAC process. */ 429 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 430 431 return 0; 432 } 433 434 /* Free TX skb function for AVB-IP */ 435 static int ravb_tx_free(struct net_device *ndev, int q) 436 { 437 struct ravb_private *priv = netdev_priv(ndev); 438 struct net_device_stats *stats = &priv->stats[q]; 439 struct ravb_tx_desc *desc; 440 int free_num = 0; 441 int entry; 442 u32 size; 443 444 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 445 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 446 NUM_TX_DESC); 447 desc = &priv->tx_ring[q][entry]; 448 if (desc->die_dt != DT_FEMPTY) 449 break; 450 /* Descriptor type must be checked before all other reads */ 451 dma_rmb(); 452 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 453 /* Free the original skb. */ 454 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 455 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 456 size, DMA_TO_DEVICE); 457 /* Last packet descriptor? */ 458 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 459 entry /= NUM_TX_DESC; 460 dev_kfree_skb_any(priv->tx_skb[q][entry]); 461 priv->tx_skb[q][entry] = NULL; 462 stats->tx_packets++; 463 } 464 free_num++; 465 } 466 stats->tx_bytes += size; 467 desc->die_dt = DT_EEMPTY; 468 } 469 return free_num; 470 } 471 472 static void ravb_get_tx_tstamp(struct net_device *ndev) 473 { 474 struct ravb_private *priv = netdev_priv(ndev); 475 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 476 struct skb_shared_hwtstamps shhwtstamps; 477 struct sk_buff *skb; 478 struct timespec64 ts; 479 u16 tag, tfa_tag; 480 int count; 481 u32 tfa2; 482 483 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 484 while (count--) { 485 tfa2 = ravb_read(ndev, TFA2); 486 tfa_tag = (tfa2 & TFA2_TST) >> 16; 487 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 488 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 489 ravb_read(ndev, TFA1); 490 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 491 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 492 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 493 list) { 494 skb = ts_skb->skb; 495 tag = ts_skb->tag; 496 list_del(&ts_skb->list); 497 kfree(ts_skb); 498 if (tag == tfa_tag) { 499 skb_tstamp_tx(skb, &shhwtstamps); 500 break; 501 } 502 } 503 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 504 } 505 } 506 507 /* Packet receive function for Ethernet AVB */ 508 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 509 { 510 struct ravb_private *priv = netdev_priv(ndev); 511 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 512 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 513 priv->cur_rx[q]; 514 struct net_device_stats *stats = &priv->stats[q]; 515 struct ravb_ex_rx_desc *desc; 516 struct sk_buff *skb; 517 dma_addr_t dma_addr; 518 struct timespec64 ts; 519 u8 desc_status; 520 u16 pkt_len; 521 int limit; 522 523 boguscnt = min(boguscnt, *quota); 524 limit = boguscnt; 525 desc = &priv->rx_ring[q][entry]; 526 while (desc->die_dt != DT_FEMPTY) { 527 /* Descriptor type must be checked before all other reads */ 528 dma_rmb(); 529 desc_status = desc->msc; 530 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 531 532 if (--boguscnt < 0) 533 break; 534 535 /* We use 0-byte descriptors to mark the DMA mapping errors */ 536 if (!pkt_len) 537 continue; 538 539 if (desc_status & MSC_MC) 540 stats->multicast++; 541 542 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 543 MSC_CEEF)) { 544 stats->rx_errors++; 545 if (desc_status & MSC_CRC) 546 stats->rx_crc_errors++; 547 if (desc_status & MSC_RFE) 548 stats->rx_frame_errors++; 549 if (desc_status & (MSC_RTLF | MSC_RTSF)) 550 stats->rx_length_errors++; 551 if (desc_status & MSC_CEEF) 552 stats->rx_missed_errors++; 553 } else { 554 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 555 556 skb = priv->rx_skb[q][entry]; 557 priv->rx_skb[q][entry] = NULL; 558 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 559 PKT_BUF_SZ, 560 DMA_FROM_DEVICE); 561 get_ts &= (q == RAVB_NC) ? 562 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 563 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 564 if (get_ts) { 565 struct skb_shared_hwtstamps *shhwtstamps; 566 567 shhwtstamps = skb_hwtstamps(skb); 568 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 569 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 570 32) | le32_to_cpu(desc->ts_sl); 571 ts.tv_nsec = le32_to_cpu(desc->ts_n); 572 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 573 } 574 skb_put(skb, pkt_len); 575 skb->protocol = eth_type_trans(skb, ndev); 576 napi_gro_receive(&priv->napi[q], skb); 577 stats->rx_packets++; 578 stats->rx_bytes += pkt_len; 579 } 580 581 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 582 desc = &priv->rx_ring[q][entry]; 583 } 584 585 /* Refill the RX ring buffers. */ 586 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 587 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 588 desc = &priv->rx_ring[q][entry]; 589 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 590 591 if (!priv->rx_skb[q][entry]) { 592 skb = netdev_alloc_skb(ndev, 593 PKT_BUF_SZ + RAVB_ALIGN - 1); 594 if (!skb) 595 break; /* Better luck next round. */ 596 ravb_set_buffer_align(skb); 597 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 598 le16_to_cpu(desc->ds_cc), 599 DMA_FROM_DEVICE); 600 skb_checksum_none_assert(skb); 601 /* We just set the data size to 0 for a failed mapping 602 * which should prevent DMA from happening... 603 */ 604 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 605 desc->ds_cc = cpu_to_le16(0); 606 desc->dptr = cpu_to_le32(dma_addr); 607 priv->rx_skb[q][entry] = skb; 608 } 609 /* Descriptor type must be set after all the above writes */ 610 dma_wmb(); 611 desc->die_dt = DT_FEMPTY; 612 } 613 614 *quota -= limit - (++boguscnt); 615 616 return boguscnt <= 0; 617 } 618 619 static void ravb_rcv_snd_disable(struct net_device *ndev) 620 { 621 /* Disable TX and RX */ 622 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 623 } 624 625 static void ravb_rcv_snd_enable(struct net_device *ndev) 626 { 627 /* Enable TX and RX */ 628 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 629 } 630 631 /* function for waiting dma process finished */ 632 static int ravb_stop_dma(struct net_device *ndev) 633 { 634 int error; 635 636 /* Wait for stopping the hardware TX process */ 637 error = ravb_wait(ndev, TCCR, 638 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 639 if (error) 640 return error; 641 642 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 643 0); 644 if (error) 645 return error; 646 647 /* Stop the E-MAC's RX/TX processes. */ 648 ravb_rcv_snd_disable(ndev); 649 650 /* Wait for stopping the RX DMA process */ 651 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 652 if (error) 653 return error; 654 655 /* Stop AVB-DMAC process */ 656 return ravb_config(ndev); 657 } 658 659 /* E-MAC interrupt handler */ 660 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 661 { 662 struct ravb_private *priv = netdev_priv(ndev); 663 u32 ecsr, psr; 664 665 ecsr = ravb_read(ndev, ECSR); 666 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 667 if (ecsr & ECSR_ICD) 668 ndev->stats.tx_carrier_errors++; 669 if (ecsr & ECSR_LCHNG) { 670 /* Link changed */ 671 if (priv->no_avb_link) 672 return; 673 psr = ravb_read(ndev, PSR); 674 if (priv->avb_link_active_low) 675 psr ^= PSR_LMON; 676 if (!(psr & PSR_LMON)) { 677 /* DIsable RX and TX */ 678 ravb_rcv_snd_disable(ndev); 679 } else { 680 /* Enable RX and TX */ 681 ravb_rcv_snd_enable(ndev); 682 } 683 } 684 } 685 686 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 687 { 688 struct net_device *ndev = dev_id; 689 struct ravb_private *priv = netdev_priv(ndev); 690 691 spin_lock(&priv->lock); 692 ravb_emac_interrupt_unlocked(ndev); 693 mmiowb(); 694 spin_unlock(&priv->lock); 695 return IRQ_HANDLED; 696 } 697 698 /* Error interrupt handler */ 699 static void ravb_error_interrupt(struct net_device *ndev) 700 { 701 struct ravb_private *priv = netdev_priv(ndev); 702 u32 eis, ris2; 703 704 eis = ravb_read(ndev, EIS); 705 ravb_write(ndev, ~EIS_QFS, EIS); 706 if (eis & EIS_QFS) { 707 ris2 = ravb_read(ndev, RIS2); 708 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); 709 710 /* Receive Descriptor Empty int */ 711 if (ris2 & RIS2_QFF0) 712 priv->stats[RAVB_BE].rx_over_errors++; 713 714 /* Receive Descriptor Empty int */ 715 if (ris2 & RIS2_QFF1) 716 priv->stats[RAVB_NC].rx_over_errors++; 717 718 /* Receive FIFO Overflow int */ 719 if (ris2 & RIS2_RFFF) 720 priv->rx_fifo_errors++; 721 } 722 } 723 724 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 725 { 726 struct ravb_private *priv = netdev_priv(ndev); 727 u32 ris0 = ravb_read(ndev, RIS0); 728 u32 ric0 = ravb_read(ndev, RIC0); 729 u32 tis = ravb_read(ndev, TIS); 730 u32 tic = ravb_read(ndev, TIC); 731 732 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 733 if (napi_schedule_prep(&priv->napi[q])) { 734 /* Mask RX and TX interrupts */ 735 if (priv->chip_id == RCAR_GEN2) { 736 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 737 ravb_write(ndev, tic & ~BIT(q), TIC); 738 } else { 739 ravb_write(ndev, BIT(q), RID0); 740 ravb_write(ndev, BIT(q), TID); 741 } 742 __napi_schedule(&priv->napi[q]); 743 } else { 744 netdev_warn(ndev, 745 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 746 ris0, ric0); 747 netdev_warn(ndev, 748 " tx status 0x%08x, tx mask 0x%08x.\n", 749 tis, tic); 750 } 751 return true; 752 } 753 return false; 754 } 755 756 static bool ravb_timestamp_interrupt(struct net_device *ndev) 757 { 758 u32 tis = ravb_read(ndev, TIS); 759 760 if (tis & TIS_TFUF) { 761 ravb_write(ndev, ~TIS_TFUF, TIS); 762 ravb_get_tx_tstamp(ndev); 763 return true; 764 } 765 return false; 766 } 767 768 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 769 { 770 struct net_device *ndev = dev_id; 771 struct ravb_private *priv = netdev_priv(ndev); 772 irqreturn_t result = IRQ_NONE; 773 u32 iss; 774 775 spin_lock(&priv->lock); 776 /* Get interrupt status */ 777 iss = ravb_read(ndev, ISS); 778 779 /* Received and transmitted interrupts */ 780 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 781 int q; 782 783 /* Timestamp updated */ 784 if (ravb_timestamp_interrupt(ndev)) 785 result = IRQ_HANDLED; 786 787 /* Network control and best effort queue RX/TX */ 788 for (q = RAVB_NC; q >= RAVB_BE; q--) { 789 if (ravb_queue_interrupt(ndev, q)) 790 result = IRQ_HANDLED; 791 } 792 } 793 794 /* E-MAC status summary */ 795 if (iss & ISS_MS) { 796 ravb_emac_interrupt_unlocked(ndev); 797 result = IRQ_HANDLED; 798 } 799 800 /* Error status summary */ 801 if (iss & ISS_ES) { 802 ravb_error_interrupt(ndev); 803 result = IRQ_HANDLED; 804 } 805 806 /* gPTP interrupt status summary */ 807 if (iss & ISS_CGIS) { 808 ravb_ptp_interrupt(ndev); 809 result = IRQ_HANDLED; 810 } 811 812 mmiowb(); 813 spin_unlock(&priv->lock); 814 return result; 815 } 816 817 /* Timestamp/Error/gPTP interrupt handler */ 818 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 819 { 820 struct net_device *ndev = dev_id; 821 struct ravb_private *priv = netdev_priv(ndev); 822 irqreturn_t result = IRQ_NONE; 823 u32 iss; 824 825 spin_lock(&priv->lock); 826 /* Get interrupt status */ 827 iss = ravb_read(ndev, ISS); 828 829 /* Timestamp updated */ 830 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 831 result = IRQ_HANDLED; 832 833 /* Error status summary */ 834 if (iss & ISS_ES) { 835 ravb_error_interrupt(ndev); 836 result = IRQ_HANDLED; 837 } 838 839 /* gPTP interrupt status summary */ 840 if (iss & ISS_CGIS) { 841 ravb_ptp_interrupt(ndev); 842 result = IRQ_HANDLED; 843 } 844 845 mmiowb(); 846 spin_unlock(&priv->lock); 847 return result; 848 } 849 850 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 851 { 852 struct net_device *ndev = dev_id; 853 struct ravb_private *priv = netdev_priv(ndev); 854 irqreturn_t result = IRQ_NONE; 855 856 spin_lock(&priv->lock); 857 858 /* Network control/Best effort queue RX/TX */ 859 if (ravb_queue_interrupt(ndev, q)) 860 result = IRQ_HANDLED; 861 862 mmiowb(); 863 spin_unlock(&priv->lock); 864 return result; 865 } 866 867 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 868 { 869 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 870 } 871 872 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 873 { 874 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 875 } 876 877 static int ravb_poll(struct napi_struct *napi, int budget) 878 { 879 struct net_device *ndev = napi->dev; 880 struct ravb_private *priv = netdev_priv(ndev); 881 unsigned long flags; 882 int q = napi - priv->napi; 883 int mask = BIT(q); 884 int quota = budget; 885 u32 ris0, tis; 886 887 for (;;) { 888 tis = ravb_read(ndev, TIS); 889 ris0 = ravb_read(ndev, RIS0); 890 if (!((ris0 & mask) || (tis & mask))) 891 break; 892 893 /* Processing RX Descriptor Ring */ 894 if (ris0 & mask) { 895 /* Clear RX interrupt */ 896 ravb_write(ndev, ~mask, RIS0); 897 if (ravb_rx(ndev, "a, q)) 898 goto out; 899 } 900 /* Processing TX Descriptor Ring */ 901 if (tis & mask) { 902 spin_lock_irqsave(&priv->lock, flags); 903 /* Clear TX interrupt */ 904 ravb_write(ndev, ~mask, TIS); 905 ravb_tx_free(ndev, q); 906 netif_wake_subqueue(ndev, q); 907 mmiowb(); 908 spin_unlock_irqrestore(&priv->lock, flags); 909 } 910 } 911 912 napi_complete(napi); 913 914 /* Re-enable RX/TX interrupts */ 915 spin_lock_irqsave(&priv->lock, flags); 916 if (priv->chip_id == RCAR_GEN2) { 917 ravb_modify(ndev, RIC0, mask, mask); 918 ravb_modify(ndev, TIC, mask, mask); 919 } else { 920 ravb_write(ndev, mask, RIE0); 921 ravb_write(ndev, mask, TIE); 922 } 923 mmiowb(); 924 spin_unlock_irqrestore(&priv->lock, flags); 925 926 /* Receive error message handling */ 927 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 928 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 929 if (priv->rx_over_errors != ndev->stats.rx_over_errors) { 930 ndev->stats.rx_over_errors = priv->rx_over_errors; 931 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n"); 932 } 933 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) { 934 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 935 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n"); 936 } 937 out: 938 return budget - quota; 939 } 940 941 /* PHY state control function */ 942 static void ravb_adjust_link(struct net_device *ndev) 943 { 944 struct ravb_private *priv = netdev_priv(ndev); 945 struct phy_device *phydev = priv->phydev; 946 bool new_state = false; 947 948 if (phydev->link) { 949 if (phydev->duplex != priv->duplex) { 950 new_state = true; 951 priv->duplex = phydev->duplex; 952 ravb_set_duplex(ndev); 953 } 954 955 if (phydev->speed != priv->speed) { 956 new_state = true; 957 priv->speed = phydev->speed; 958 ravb_set_rate(ndev); 959 } 960 if (!priv->link) { 961 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 962 new_state = true; 963 priv->link = phydev->link; 964 if (priv->no_avb_link) 965 ravb_rcv_snd_enable(ndev); 966 } 967 } else if (priv->link) { 968 new_state = true; 969 priv->link = 0; 970 priv->speed = 0; 971 priv->duplex = -1; 972 if (priv->no_avb_link) 973 ravb_rcv_snd_disable(ndev); 974 } 975 976 if (new_state && netif_msg_link(priv)) 977 phy_print_status(phydev); 978 } 979 980 /* PHY init function */ 981 static int ravb_phy_init(struct net_device *ndev) 982 { 983 struct device_node *np = ndev->dev.parent->of_node; 984 struct ravb_private *priv = netdev_priv(ndev); 985 struct phy_device *phydev; 986 struct device_node *pn; 987 int err; 988 989 priv->link = 0; 990 priv->speed = 0; 991 priv->duplex = -1; 992 993 /* Try connecting to PHY */ 994 pn = of_parse_phandle(np, "phy-handle", 0); 995 if (!pn) { 996 /* In the case of a fixed PHY, the DT node associated 997 * to the PHY is the Ethernet MAC DT node. 998 */ 999 if (of_phy_is_fixed_link(np)) { 1000 err = of_phy_register_fixed_link(np); 1001 if (err) 1002 return err; 1003 } 1004 pn = of_node_get(np); 1005 } 1006 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1007 priv->phy_interface); 1008 of_node_put(pn); 1009 if (!phydev) { 1010 netdev_err(ndev, "failed to connect PHY\n"); 1011 return -ENOENT; 1012 } 1013 1014 /* This driver only support 10/100Mbit speeds on Gen3 1015 * at this time. 1016 */ 1017 if (priv->chip_id == RCAR_GEN3) { 1018 int err; 1019 1020 err = phy_set_max_speed(phydev, SPEED_100); 1021 if (err) { 1022 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1023 phy_disconnect(phydev); 1024 return err; 1025 } 1026 1027 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1028 } 1029 1030 /* 10BASE is not supported */ 1031 phydev->supported &= ~PHY_10BT_FEATURES; 1032 1033 phy_attached_info(phydev); 1034 1035 priv->phydev = phydev; 1036 1037 return 0; 1038 } 1039 1040 /* PHY control start function */ 1041 static int ravb_phy_start(struct net_device *ndev) 1042 { 1043 struct ravb_private *priv = netdev_priv(ndev); 1044 int error; 1045 1046 error = ravb_phy_init(ndev); 1047 if (error) 1048 return error; 1049 1050 phy_start(priv->phydev); 1051 1052 return 0; 1053 } 1054 1055 static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1056 { 1057 struct ravb_private *priv = netdev_priv(ndev); 1058 int error = -ENODEV; 1059 unsigned long flags; 1060 1061 if (priv->phydev) { 1062 spin_lock_irqsave(&priv->lock, flags); 1063 error = phy_ethtool_gset(priv->phydev, ecmd); 1064 spin_unlock_irqrestore(&priv->lock, flags); 1065 } 1066 1067 return error; 1068 } 1069 1070 static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1071 { 1072 struct ravb_private *priv = netdev_priv(ndev); 1073 unsigned long flags; 1074 int error; 1075 1076 if (!priv->phydev) 1077 return -ENODEV; 1078 1079 spin_lock_irqsave(&priv->lock, flags); 1080 1081 /* Disable TX and RX */ 1082 ravb_rcv_snd_disable(ndev); 1083 1084 error = phy_ethtool_sset(priv->phydev, ecmd); 1085 if (error) 1086 goto error_exit; 1087 1088 if (ecmd->duplex == DUPLEX_FULL) 1089 priv->duplex = 1; 1090 else 1091 priv->duplex = 0; 1092 1093 ravb_set_duplex(ndev); 1094 1095 error_exit: 1096 mdelay(1); 1097 1098 /* Enable TX and RX */ 1099 ravb_rcv_snd_enable(ndev); 1100 1101 mmiowb(); 1102 spin_unlock_irqrestore(&priv->lock, flags); 1103 1104 return error; 1105 } 1106 1107 static int ravb_nway_reset(struct net_device *ndev) 1108 { 1109 struct ravb_private *priv = netdev_priv(ndev); 1110 int error = -ENODEV; 1111 unsigned long flags; 1112 1113 if (priv->phydev) { 1114 spin_lock_irqsave(&priv->lock, flags); 1115 error = phy_start_aneg(priv->phydev); 1116 spin_unlock_irqrestore(&priv->lock, flags); 1117 } 1118 1119 return error; 1120 } 1121 1122 static u32 ravb_get_msglevel(struct net_device *ndev) 1123 { 1124 struct ravb_private *priv = netdev_priv(ndev); 1125 1126 return priv->msg_enable; 1127 } 1128 1129 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1130 { 1131 struct ravb_private *priv = netdev_priv(ndev); 1132 1133 priv->msg_enable = value; 1134 } 1135 1136 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1137 "rx_queue_0_current", 1138 "tx_queue_0_current", 1139 "rx_queue_0_dirty", 1140 "tx_queue_0_dirty", 1141 "rx_queue_0_packets", 1142 "tx_queue_0_packets", 1143 "rx_queue_0_bytes", 1144 "tx_queue_0_bytes", 1145 "rx_queue_0_mcast_packets", 1146 "rx_queue_0_errors", 1147 "rx_queue_0_crc_errors", 1148 "rx_queue_0_frame_errors", 1149 "rx_queue_0_length_errors", 1150 "rx_queue_0_missed_errors", 1151 "rx_queue_0_over_errors", 1152 1153 "rx_queue_1_current", 1154 "tx_queue_1_current", 1155 "rx_queue_1_dirty", 1156 "tx_queue_1_dirty", 1157 "rx_queue_1_packets", 1158 "tx_queue_1_packets", 1159 "rx_queue_1_bytes", 1160 "tx_queue_1_bytes", 1161 "rx_queue_1_mcast_packets", 1162 "rx_queue_1_errors", 1163 "rx_queue_1_crc_errors", 1164 "rx_queue_1_frame_errors", 1165 "rx_queue_1_length_errors", 1166 "rx_queue_1_missed_errors", 1167 "rx_queue_1_over_errors", 1168 }; 1169 1170 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1171 1172 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1173 { 1174 switch (sset) { 1175 case ETH_SS_STATS: 1176 return RAVB_STATS_LEN; 1177 default: 1178 return -EOPNOTSUPP; 1179 } 1180 } 1181 1182 static void ravb_get_ethtool_stats(struct net_device *ndev, 1183 struct ethtool_stats *stats, u64 *data) 1184 { 1185 struct ravb_private *priv = netdev_priv(ndev); 1186 int i = 0; 1187 int q; 1188 1189 /* Device-specific stats */ 1190 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1191 struct net_device_stats *stats = &priv->stats[q]; 1192 1193 data[i++] = priv->cur_rx[q]; 1194 data[i++] = priv->cur_tx[q]; 1195 data[i++] = priv->dirty_rx[q]; 1196 data[i++] = priv->dirty_tx[q]; 1197 data[i++] = stats->rx_packets; 1198 data[i++] = stats->tx_packets; 1199 data[i++] = stats->rx_bytes; 1200 data[i++] = stats->tx_bytes; 1201 data[i++] = stats->multicast; 1202 data[i++] = stats->rx_errors; 1203 data[i++] = stats->rx_crc_errors; 1204 data[i++] = stats->rx_frame_errors; 1205 data[i++] = stats->rx_length_errors; 1206 data[i++] = stats->rx_missed_errors; 1207 data[i++] = stats->rx_over_errors; 1208 } 1209 } 1210 1211 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1212 { 1213 switch (stringset) { 1214 case ETH_SS_STATS: 1215 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1216 break; 1217 } 1218 } 1219 1220 static void ravb_get_ringparam(struct net_device *ndev, 1221 struct ethtool_ringparam *ring) 1222 { 1223 struct ravb_private *priv = netdev_priv(ndev); 1224 1225 ring->rx_max_pending = BE_RX_RING_MAX; 1226 ring->tx_max_pending = BE_TX_RING_MAX; 1227 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1228 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1229 } 1230 1231 static int ravb_set_ringparam(struct net_device *ndev, 1232 struct ethtool_ringparam *ring) 1233 { 1234 struct ravb_private *priv = netdev_priv(ndev); 1235 int error; 1236 1237 if (ring->tx_pending > BE_TX_RING_MAX || 1238 ring->rx_pending > BE_RX_RING_MAX || 1239 ring->tx_pending < BE_TX_RING_MIN || 1240 ring->rx_pending < BE_RX_RING_MIN) 1241 return -EINVAL; 1242 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1243 return -EINVAL; 1244 1245 if (netif_running(ndev)) { 1246 netif_device_detach(ndev); 1247 /* Stop PTP Clock driver */ 1248 if (priv->chip_id == RCAR_GEN2) 1249 ravb_ptp_stop(ndev); 1250 /* Wait for DMA stopping */ 1251 error = ravb_stop_dma(ndev); 1252 if (error) { 1253 netdev_err(ndev, 1254 "cannot set ringparam! Any AVB processes are still running?\n"); 1255 return error; 1256 } 1257 synchronize_irq(ndev->irq); 1258 1259 /* Free all the skb's in the RX queue and the DMA buffers. */ 1260 ravb_ring_free(ndev, RAVB_BE); 1261 ravb_ring_free(ndev, RAVB_NC); 1262 } 1263 1264 /* Set new parameters */ 1265 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1266 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1267 1268 if (netif_running(ndev)) { 1269 error = ravb_dmac_init(ndev); 1270 if (error) { 1271 netdev_err(ndev, 1272 "%s: ravb_dmac_init() failed, error %d\n", 1273 __func__, error); 1274 return error; 1275 } 1276 1277 ravb_emac_init(ndev); 1278 1279 /* Initialise PTP Clock driver */ 1280 if (priv->chip_id == RCAR_GEN2) 1281 ravb_ptp_init(ndev, priv->pdev); 1282 1283 netif_device_attach(ndev); 1284 } 1285 1286 return 0; 1287 } 1288 1289 static int ravb_get_ts_info(struct net_device *ndev, 1290 struct ethtool_ts_info *info) 1291 { 1292 struct ravb_private *priv = netdev_priv(ndev); 1293 1294 info->so_timestamping = 1295 SOF_TIMESTAMPING_TX_SOFTWARE | 1296 SOF_TIMESTAMPING_RX_SOFTWARE | 1297 SOF_TIMESTAMPING_SOFTWARE | 1298 SOF_TIMESTAMPING_TX_HARDWARE | 1299 SOF_TIMESTAMPING_RX_HARDWARE | 1300 SOF_TIMESTAMPING_RAW_HARDWARE; 1301 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1302 info->rx_filters = 1303 (1 << HWTSTAMP_FILTER_NONE) | 1304 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1305 (1 << HWTSTAMP_FILTER_ALL); 1306 info->phc_index = ptp_clock_index(priv->ptp.clock); 1307 1308 return 0; 1309 } 1310 1311 static const struct ethtool_ops ravb_ethtool_ops = { 1312 .get_settings = ravb_get_settings, 1313 .set_settings = ravb_set_settings, 1314 .nway_reset = ravb_nway_reset, 1315 .get_msglevel = ravb_get_msglevel, 1316 .set_msglevel = ravb_set_msglevel, 1317 .get_link = ethtool_op_get_link, 1318 .get_strings = ravb_get_strings, 1319 .get_ethtool_stats = ravb_get_ethtool_stats, 1320 .get_sset_count = ravb_get_sset_count, 1321 .get_ringparam = ravb_get_ringparam, 1322 .set_ringparam = ravb_set_ringparam, 1323 .get_ts_info = ravb_get_ts_info, 1324 }; 1325 1326 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1327 struct net_device *ndev, struct device *dev, 1328 const char *ch) 1329 { 1330 char *name; 1331 int error; 1332 1333 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1334 if (!name) 1335 return -ENOMEM; 1336 error = request_irq(irq, handler, 0, name, ndev); 1337 if (error) 1338 netdev_err(ndev, "cannot request IRQ %s\n", name); 1339 1340 return error; 1341 } 1342 1343 /* Network device open function for Ethernet AVB */ 1344 static int ravb_open(struct net_device *ndev) 1345 { 1346 struct ravb_private *priv = netdev_priv(ndev); 1347 struct platform_device *pdev = priv->pdev; 1348 struct device *dev = &pdev->dev; 1349 int error; 1350 1351 napi_enable(&priv->napi[RAVB_BE]); 1352 napi_enable(&priv->napi[RAVB_NC]); 1353 1354 if (priv->chip_id == RCAR_GEN2) { 1355 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1356 ndev->name, ndev); 1357 if (error) { 1358 netdev_err(ndev, "cannot request IRQ\n"); 1359 goto out_napi_off; 1360 } 1361 } else { 1362 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1363 dev, "ch22:multi"); 1364 if (error) 1365 goto out_napi_off; 1366 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1367 dev, "ch24:emac"); 1368 if (error) 1369 goto out_free_irq; 1370 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1371 ndev, dev, "ch0:rx_be"); 1372 if (error) 1373 goto out_free_irq_emac; 1374 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1375 ndev, dev, "ch18:tx_be"); 1376 if (error) 1377 goto out_free_irq_be_rx; 1378 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1379 ndev, dev, "ch1:rx_nc"); 1380 if (error) 1381 goto out_free_irq_be_tx; 1382 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1383 ndev, dev, "ch19:tx_nc"); 1384 if (error) 1385 goto out_free_irq_nc_rx; 1386 } 1387 1388 /* Device init */ 1389 error = ravb_dmac_init(ndev); 1390 if (error) 1391 goto out_free_irq_nc_tx; 1392 ravb_emac_init(ndev); 1393 1394 /* Initialise PTP Clock driver */ 1395 if (priv->chip_id == RCAR_GEN2) 1396 ravb_ptp_init(ndev, priv->pdev); 1397 1398 netif_tx_start_all_queues(ndev); 1399 1400 /* PHY control start */ 1401 error = ravb_phy_start(ndev); 1402 if (error) 1403 goto out_ptp_stop; 1404 1405 return 0; 1406 1407 out_ptp_stop: 1408 /* Stop PTP Clock driver */ 1409 if (priv->chip_id == RCAR_GEN2) 1410 ravb_ptp_stop(ndev); 1411 out_free_irq_nc_tx: 1412 if (priv->chip_id == RCAR_GEN2) 1413 goto out_free_irq; 1414 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1415 out_free_irq_nc_rx: 1416 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1417 out_free_irq_be_tx: 1418 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1419 out_free_irq_be_rx: 1420 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1421 out_free_irq_emac: 1422 free_irq(priv->emac_irq, ndev); 1423 out_free_irq: 1424 free_irq(ndev->irq, ndev); 1425 out_napi_off: 1426 napi_disable(&priv->napi[RAVB_NC]); 1427 napi_disable(&priv->napi[RAVB_BE]); 1428 return error; 1429 } 1430 1431 /* Timeout function for Ethernet AVB */ 1432 static void ravb_tx_timeout(struct net_device *ndev) 1433 { 1434 struct ravb_private *priv = netdev_priv(ndev); 1435 1436 netif_err(priv, tx_err, ndev, 1437 "transmit timed out, status %08x, resetting...\n", 1438 ravb_read(ndev, ISS)); 1439 1440 /* tx_errors count up */ 1441 ndev->stats.tx_errors++; 1442 1443 schedule_work(&priv->work); 1444 } 1445 1446 static void ravb_tx_timeout_work(struct work_struct *work) 1447 { 1448 struct ravb_private *priv = container_of(work, struct ravb_private, 1449 work); 1450 struct net_device *ndev = priv->ndev; 1451 1452 netif_tx_stop_all_queues(ndev); 1453 1454 /* Stop PTP Clock driver */ 1455 if (priv->chip_id == RCAR_GEN2) 1456 ravb_ptp_stop(ndev); 1457 1458 /* Wait for DMA stopping */ 1459 ravb_stop_dma(ndev); 1460 1461 ravb_ring_free(ndev, RAVB_BE); 1462 ravb_ring_free(ndev, RAVB_NC); 1463 1464 /* Device init */ 1465 ravb_dmac_init(ndev); 1466 ravb_emac_init(ndev); 1467 1468 /* Initialise PTP Clock driver */ 1469 if (priv->chip_id == RCAR_GEN2) 1470 ravb_ptp_init(ndev, priv->pdev); 1471 1472 netif_tx_start_all_queues(ndev); 1473 } 1474 1475 /* Packet transmit function for Ethernet AVB */ 1476 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1477 { 1478 struct ravb_private *priv = netdev_priv(ndev); 1479 u16 q = skb_get_queue_mapping(skb); 1480 struct ravb_tstamp_skb *ts_skb; 1481 struct ravb_tx_desc *desc; 1482 unsigned long flags; 1483 u32 dma_addr; 1484 void *buffer; 1485 u32 entry; 1486 u32 len; 1487 1488 spin_lock_irqsave(&priv->lock, flags); 1489 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1490 NUM_TX_DESC) { 1491 netif_err(priv, tx_queued, ndev, 1492 "still transmitting with the full ring!\n"); 1493 netif_stop_subqueue(ndev, q); 1494 spin_unlock_irqrestore(&priv->lock, flags); 1495 return NETDEV_TX_BUSY; 1496 } 1497 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1498 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1499 1500 if (skb_put_padto(skb, ETH_ZLEN)) 1501 goto drop; 1502 1503 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1504 entry / NUM_TX_DESC * DPTR_ALIGN; 1505 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1506 memcpy(buffer, skb->data, len); 1507 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1508 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1509 goto drop; 1510 1511 desc = &priv->tx_ring[q][entry]; 1512 desc->ds_tagl = cpu_to_le16(len); 1513 desc->dptr = cpu_to_le32(dma_addr); 1514 1515 buffer = skb->data + len; 1516 len = skb->len - len; 1517 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1518 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1519 goto unmap; 1520 1521 desc++; 1522 desc->ds_tagl = cpu_to_le16(len); 1523 desc->dptr = cpu_to_le32(dma_addr); 1524 1525 /* TX timestamp required */ 1526 if (q == RAVB_NC) { 1527 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1528 if (!ts_skb) { 1529 desc--; 1530 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1531 DMA_TO_DEVICE); 1532 goto unmap; 1533 } 1534 ts_skb->skb = skb; 1535 ts_skb->tag = priv->ts_skb_tag++; 1536 priv->ts_skb_tag &= 0x3ff; 1537 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1538 1539 /* TAG and timestamp required flag */ 1540 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1541 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1542 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); 1543 } 1544 1545 skb_tx_timestamp(skb); 1546 /* Descriptor type must be set after all the above writes */ 1547 dma_wmb(); 1548 desc->die_dt = DT_FEND; 1549 desc--; 1550 desc->die_dt = DT_FSTART; 1551 1552 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1553 1554 priv->cur_tx[q] += NUM_TX_DESC; 1555 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1556 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q)) 1557 netif_stop_subqueue(ndev, q); 1558 1559 exit: 1560 mmiowb(); 1561 spin_unlock_irqrestore(&priv->lock, flags); 1562 return NETDEV_TX_OK; 1563 1564 unmap: 1565 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1566 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1567 drop: 1568 dev_kfree_skb_any(skb); 1569 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1570 goto exit; 1571 } 1572 1573 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1574 void *accel_priv, select_queue_fallback_t fallback) 1575 { 1576 /* If skb needs TX timestamp, it is handled in network control queue */ 1577 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1578 RAVB_BE; 1579 1580 } 1581 1582 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1583 { 1584 struct ravb_private *priv = netdev_priv(ndev); 1585 struct net_device_stats *nstats, *stats0, *stats1; 1586 1587 nstats = &ndev->stats; 1588 stats0 = &priv->stats[RAVB_BE]; 1589 stats1 = &priv->stats[RAVB_NC]; 1590 1591 nstats->tx_dropped += ravb_read(ndev, TROCR); 1592 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1593 nstats->collisions += ravb_read(ndev, CDCR); 1594 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1595 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1596 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1597 1598 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1599 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1600 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1601 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1602 1603 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1604 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1605 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1606 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1607 nstats->multicast = stats0->multicast + stats1->multicast; 1608 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1609 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1610 nstats->rx_frame_errors = 1611 stats0->rx_frame_errors + stats1->rx_frame_errors; 1612 nstats->rx_length_errors = 1613 stats0->rx_length_errors + stats1->rx_length_errors; 1614 nstats->rx_missed_errors = 1615 stats0->rx_missed_errors + stats1->rx_missed_errors; 1616 nstats->rx_over_errors = 1617 stats0->rx_over_errors + stats1->rx_over_errors; 1618 1619 return nstats; 1620 } 1621 1622 /* Update promiscuous bit */ 1623 static void ravb_set_rx_mode(struct net_device *ndev) 1624 { 1625 struct ravb_private *priv = netdev_priv(ndev); 1626 unsigned long flags; 1627 1628 spin_lock_irqsave(&priv->lock, flags); 1629 ravb_modify(ndev, ECMR, ECMR_PRM, 1630 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1631 mmiowb(); 1632 spin_unlock_irqrestore(&priv->lock, flags); 1633 } 1634 1635 /* Device close function for Ethernet AVB */ 1636 static int ravb_close(struct net_device *ndev) 1637 { 1638 struct ravb_private *priv = netdev_priv(ndev); 1639 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1640 1641 netif_tx_stop_all_queues(ndev); 1642 1643 /* Disable interrupts by clearing the interrupt masks. */ 1644 ravb_write(ndev, 0, RIC0); 1645 ravb_write(ndev, 0, RIC2); 1646 ravb_write(ndev, 0, TIC); 1647 1648 /* Stop PTP Clock driver */ 1649 if (priv->chip_id == RCAR_GEN2) 1650 ravb_ptp_stop(ndev); 1651 1652 /* Set the config mode to stop the AVB-DMAC's processes */ 1653 if (ravb_stop_dma(ndev) < 0) 1654 netdev_err(ndev, 1655 "device will be stopped after h/w processes are done.\n"); 1656 1657 /* Clear the timestamp list */ 1658 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1659 list_del(&ts_skb->list); 1660 kfree(ts_skb); 1661 } 1662 1663 /* PHY disconnect */ 1664 if (priv->phydev) { 1665 phy_stop(priv->phydev); 1666 phy_disconnect(priv->phydev); 1667 priv->phydev = NULL; 1668 } 1669 1670 if (priv->chip_id != RCAR_GEN2) { 1671 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1672 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1673 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1674 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1675 free_irq(priv->emac_irq, ndev); 1676 } 1677 free_irq(ndev->irq, ndev); 1678 1679 napi_disable(&priv->napi[RAVB_NC]); 1680 napi_disable(&priv->napi[RAVB_BE]); 1681 1682 /* Free all the skb's in the RX queue and the DMA buffers. */ 1683 ravb_ring_free(ndev, RAVB_BE); 1684 ravb_ring_free(ndev, RAVB_NC); 1685 1686 return 0; 1687 } 1688 1689 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1690 { 1691 struct ravb_private *priv = netdev_priv(ndev); 1692 struct hwtstamp_config config; 1693 1694 config.flags = 0; 1695 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1696 HWTSTAMP_TX_OFF; 1697 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1698 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1699 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1700 config.rx_filter = HWTSTAMP_FILTER_ALL; 1701 else 1702 config.rx_filter = HWTSTAMP_FILTER_NONE; 1703 1704 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1705 -EFAULT : 0; 1706 } 1707 1708 /* Control hardware time stamping */ 1709 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1710 { 1711 struct ravb_private *priv = netdev_priv(ndev); 1712 struct hwtstamp_config config; 1713 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1714 u32 tstamp_tx_ctrl; 1715 1716 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1717 return -EFAULT; 1718 1719 /* Reserved for future extensions */ 1720 if (config.flags) 1721 return -EINVAL; 1722 1723 switch (config.tx_type) { 1724 case HWTSTAMP_TX_OFF: 1725 tstamp_tx_ctrl = 0; 1726 break; 1727 case HWTSTAMP_TX_ON: 1728 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1729 break; 1730 default: 1731 return -ERANGE; 1732 } 1733 1734 switch (config.rx_filter) { 1735 case HWTSTAMP_FILTER_NONE: 1736 tstamp_rx_ctrl = 0; 1737 break; 1738 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1739 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1740 break; 1741 default: 1742 config.rx_filter = HWTSTAMP_FILTER_ALL; 1743 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1744 } 1745 1746 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1747 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1748 1749 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1750 -EFAULT : 0; 1751 } 1752 1753 /* ioctl to device function */ 1754 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1755 { 1756 struct ravb_private *priv = netdev_priv(ndev); 1757 struct phy_device *phydev = priv->phydev; 1758 1759 if (!netif_running(ndev)) 1760 return -EINVAL; 1761 1762 if (!phydev) 1763 return -ENODEV; 1764 1765 switch (cmd) { 1766 case SIOCGHWTSTAMP: 1767 return ravb_hwtstamp_get(ndev, req); 1768 case SIOCSHWTSTAMP: 1769 return ravb_hwtstamp_set(ndev, req); 1770 } 1771 1772 return phy_mii_ioctl(phydev, req, cmd); 1773 } 1774 1775 static const struct net_device_ops ravb_netdev_ops = { 1776 .ndo_open = ravb_open, 1777 .ndo_stop = ravb_close, 1778 .ndo_start_xmit = ravb_start_xmit, 1779 .ndo_select_queue = ravb_select_queue, 1780 .ndo_get_stats = ravb_get_stats, 1781 .ndo_set_rx_mode = ravb_set_rx_mode, 1782 .ndo_tx_timeout = ravb_tx_timeout, 1783 .ndo_do_ioctl = ravb_do_ioctl, 1784 .ndo_validate_addr = eth_validate_addr, 1785 .ndo_set_mac_address = eth_mac_addr, 1786 .ndo_change_mtu = eth_change_mtu, 1787 }; 1788 1789 /* MDIO bus init function */ 1790 static int ravb_mdio_init(struct ravb_private *priv) 1791 { 1792 struct platform_device *pdev = priv->pdev; 1793 struct device *dev = &pdev->dev; 1794 int error; 1795 1796 /* Bitbang init */ 1797 priv->mdiobb.ops = &bb_ops; 1798 1799 /* MII controller setting */ 1800 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1801 if (!priv->mii_bus) 1802 return -ENOMEM; 1803 1804 /* Hook up MII support for ethtool */ 1805 priv->mii_bus->name = "ravb_mii"; 1806 priv->mii_bus->parent = dev; 1807 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1808 pdev->name, pdev->id); 1809 1810 /* Register MDIO bus */ 1811 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1812 if (error) 1813 goto out_free_bus; 1814 1815 return 0; 1816 1817 out_free_bus: 1818 free_mdio_bitbang(priv->mii_bus); 1819 return error; 1820 } 1821 1822 /* MDIO bus release function */ 1823 static int ravb_mdio_release(struct ravb_private *priv) 1824 { 1825 /* Unregister mdio bus */ 1826 mdiobus_unregister(priv->mii_bus); 1827 1828 /* Free bitbang info */ 1829 free_mdio_bitbang(priv->mii_bus); 1830 1831 return 0; 1832 } 1833 1834 static const struct of_device_id ravb_match_table[] = { 1835 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1836 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1837 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1838 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1839 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1840 { } 1841 }; 1842 MODULE_DEVICE_TABLE(of, ravb_match_table); 1843 1844 static int ravb_set_gti(struct net_device *ndev) 1845 { 1846 1847 struct device *dev = ndev->dev.parent; 1848 struct device_node *np = dev->of_node; 1849 unsigned long rate; 1850 struct clk *clk; 1851 uint64_t inc; 1852 1853 clk = of_clk_get(np, 0); 1854 if (IS_ERR(clk)) { 1855 dev_err(dev, "could not get clock\n"); 1856 return PTR_ERR(clk); 1857 } 1858 1859 rate = clk_get_rate(clk); 1860 clk_put(clk); 1861 1862 if (!rate) 1863 return -EINVAL; 1864 1865 inc = 1000000000ULL << 20; 1866 do_div(inc, rate); 1867 1868 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1869 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1870 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1871 return -EINVAL; 1872 } 1873 1874 ravb_write(ndev, inc, GTI); 1875 1876 return 0; 1877 } 1878 1879 static int ravb_probe(struct platform_device *pdev) 1880 { 1881 struct device_node *np = pdev->dev.of_node; 1882 struct ravb_private *priv; 1883 enum ravb_chip_id chip_id; 1884 struct net_device *ndev; 1885 int error, irq, q; 1886 struct resource *res; 1887 int i; 1888 1889 if (!np) { 1890 dev_err(&pdev->dev, 1891 "this driver is required to be instantiated from device tree\n"); 1892 return -EINVAL; 1893 } 1894 1895 /* Get base address */ 1896 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1897 if (!res) { 1898 dev_err(&pdev->dev, "invalid resource\n"); 1899 return -EINVAL; 1900 } 1901 1902 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 1903 NUM_TX_QUEUE, NUM_RX_QUEUE); 1904 if (!ndev) 1905 return -ENOMEM; 1906 1907 pm_runtime_enable(&pdev->dev); 1908 pm_runtime_get_sync(&pdev->dev); 1909 1910 /* The Ether-specific entries in the device structure. */ 1911 ndev->base_addr = res->start; 1912 1913 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 1914 1915 if (chip_id == RCAR_GEN3) 1916 irq = platform_get_irq_byname(pdev, "ch22"); 1917 else 1918 irq = platform_get_irq(pdev, 0); 1919 if (irq < 0) { 1920 error = irq; 1921 goto out_release; 1922 } 1923 ndev->irq = irq; 1924 1925 SET_NETDEV_DEV(ndev, &pdev->dev); 1926 1927 priv = netdev_priv(ndev); 1928 priv->ndev = ndev; 1929 priv->pdev = pdev; 1930 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 1931 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 1932 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 1933 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 1934 priv->addr = devm_ioremap_resource(&pdev->dev, res); 1935 if (IS_ERR(priv->addr)) { 1936 error = PTR_ERR(priv->addr); 1937 goto out_release; 1938 } 1939 1940 spin_lock_init(&priv->lock); 1941 INIT_WORK(&priv->work, ravb_tx_timeout_work); 1942 1943 priv->phy_interface = of_get_phy_mode(np); 1944 1945 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 1946 priv->avb_link_active_low = 1947 of_property_read_bool(np, "renesas,ether-link-active-low"); 1948 1949 if (chip_id == RCAR_GEN3) { 1950 irq = platform_get_irq_byname(pdev, "ch24"); 1951 if (irq < 0) { 1952 error = irq; 1953 goto out_release; 1954 } 1955 priv->emac_irq = irq; 1956 for (i = 0; i < NUM_RX_QUEUE; i++) { 1957 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 1958 if (irq < 0) { 1959 error = irq; 1960 goto out_release; 1961 } 1962 priv->rx_irqs[i] = irq; 1963 } 1964 for (i = 0; i < NUM_TX_QUEUE; i++) { 1965 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 1966 if (irq < 0) { 1967 error = irq; 1968 goto out_release; 1969 } 1970 priv->tx_irqs[i] = irq; 1971 } 1972 } 1973 1974 priv->chip_id = chip_id; 1975 1976 /* Set function */ 1977 ndev->netdev_ops = &ravb_netdev_ops; 1978 ndev->ethtool_ops = &ravb_ethtool_ops; 1979 1980 /* Set AVB config mode */ 1981 if (chip_id == RCAR_GEN2) { 1982 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1983 /* Set CSEL value */ 1984 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1985 } else { 1986 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1987 CCC_GAC | CCC_CSEL_HPB); 1988 } 1989 1990 /* Set GTI value */ 1991 error = ravb_set_gti(ndev); 1992 if (error) 1993 goto out_release; 1994 1995 /* Request GTI loading */ 1996 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 1997 1998 /* Allocate descriptor base address table */ 1999 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2000 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2001 &priv->desc_bat_dma, GFP_KERNEL); 2002 if (!priv->desc_bat) { 2003 dev_err(&pdev->dev, 2004 "Cannot allocate desc base address table (size %d bytes)\n", 2005 priv->desc_bat_size); 2006 error = -ENOMEM; 2007 goto out_release; 2008 } 2009 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2010 priv->desc_bat[q].die_dt = DT_EOS; 2011 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2012 2013 /* Initialise HW timestamp list */ 2014 INIT_LIST_HEAD(&priv->ts_skb_list); 2015 2016 /* Initialise PTP Clock driver */ 2017 if (chip_id != RCAR_GEN2) 2018 ravb_ptp_init(ndev, pdev); 2019 2020 /* Debug message level */ 2021 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2022 2023 /* Read and set MAC address */ 2024 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2025 if (!is_valid_ether_addr(ndev->dev_addr)) { 2026 dev_warn(&pdev->dev, 2027 "no valid MAC address supplied, using a random one\n"); 2028 eth_hw_addr_random(ndev); 2029 } 2030 2031 /* MDIO bus init */ 2032 error = ravb_mdio_init(priv); 2033 if (error) { 2034 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2035 goto out_dma_free; 2036 } 2037 2038 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2039 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2040 2041 /* Network device register */ 2042 error = register_netdev(ndev); 2043 if (error) 2044 goto out_napi_del; 2045 2046 /* Print device information */ 2047 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2048 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2049 2050 platform_set_drvdata(pdev, ndev); 2051 2052 return 0; 2053 2054 out_napi_del: 2055 netif_napi_del(&priv->napi[RAVB_NC]); 2056 netif_napi_del(&priv->napi[RAVB_BE]); 2057 ravb_mdio_release(priv); 2058 out_dma_free: 2059 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2060 priv->desc_bat_dma); 2061 2062 /* Stop PTP Clock driver */ 2063 if (chip_id != RCAR_GEN2) 2064 ravb_ptp_stop(ndev); 2065 out_release: 2066 if (ndev) 2067 free_netdev(ndev); 2068 2069 pm_runtime_put(&pdev->dev); 2070 pm_runtime_disable(&pdev->dev); 2071 return error; 2072 } 2073 2074 static int ravb_remove(struct platform_device *pdev) 2075 { 2076 struct net_device *ndev = platform_get_drvdata(pdev); 2077 struct ravb_private *priv = netdev_priv(ndev); 2078 2079 /* Stop PTP Clock driver */ 2080 if (priv->chip_id != RCAR_GEN2) 2081 ravb_ptp_stop(ndev); 2082 2083 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2084 priv->desc_bat_dma); 2085 /* Set reset mode */ 2086 ravb_write(ndev, CCC_OPC_RESET, CCC); 2087 pm_runtime_put_sync(&pdev->dev); 2088 unregister_netdev(ndev); 2089 netif_napi_del(&priv->napi[RAVB_NC]); 2090 netif_napi_del(&priv->napi[RAVB_BE]); 2091 ravb_mdio_release(priv); 2092 pm_runtime_disable(&pdev->dev); 2093 free_netdev(ndev); 2094 platform_set_drvdata(pdev, NULL); 2095 2096 return 0; 2097 } 2098 2099 #ifdef CONFIG_PM 2100 static int ravb_runtime_nop(struct device *dev) 2101 { 2102 /* Runtime PM callback shared between ->runtime_suspend() 2103 * and ->runtime_resume(). Simply returns success. 2104 * 2105 * This driver re-initializes all registers after 2106 * pm_runtime_get_sync() anyway so there is no need 2107 * to save and restore registers here. 2108 */ 2109 return 0; 2110 } 2111 2112 static const struct dev_pm_ops ravb_dev_pm_ops = { 2113 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2114 }; 2115 2116 #define RAVB_PM_OPS (&ravb_dev_pm_ops) 2117 #else 2118 #define RAVB_PM_OPS NULL 2119 #endif 2120 2121 static struct platform_driver ravb_driver = { 2122 .probe = ravb_probe, 2123 .remove = ravb_remove, 2124 .driver = { 2125 .name = "ravb", 2126 .pm = RAVB_PM_OPS, 2127 .of_match_table = ravb_match_table, 2128 }, 2129 }; 2130 2131 module_platform_driver(ravb_driver); 2132 2133 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2134 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2135 MODULE_LICENSE("GPL v2"); 2136