1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 #include <linux/reset.h> 33 34 #include <asm/div64.h> 35 36 #include "ravb.h" 37 38 #define RAVB_DEF_MSG_ENABLE \ 39 (NETIF_MSG_LINK | \ 40 NETIF_MSG_TIMER | \ 41 NETIF_MSG_RX_ERR | \ 42 NETIF_MSG_TX_ERR) 43 44 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 45 "ch0", /* RAVB_BE */ 46 "ch1", /* RAVB_NC */ 47 }; 48 49 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 50 "ch18", /* RAVB_BE */ 51 "ch19", /* RAVB_NC */ 52 }; 53 54 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 55 u32 set) 56 { 57 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 58 } 59 60 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 61 { 62 int i; 63 64 for (i = 0; i < 10000; i++) { 65 if ((ravb_read(ndev, reg) & mask) == value) 66 return 0; 67 udelay(10); 68 } 69 return -ETIMEDOUT; 70 } 71 72 static int ravb_config(struct net_device *ndev) 73 { 74 int error; 75 76 /* Set config mode */ 77 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 78 /* Check if the operating mode is changed to the config mode */ 79 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 80 if (error) 81 netdev_err(ndev, "failed to switch device to config mode\n"); 82 83 return error; 84 } 85 86 static void ravb_set_rate_gbeth(struct net_device *ndev) 87 { 88 struct ravb_private *priv = netdev_priv(ndev); 89 90 switch (priv->speed) { 91 case 10: /* 10BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 93 break; 94 case 100: /* 100BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 96 break; 97 case 1000: /* 1000BASE */ 98 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 99 break; 100 } 101 } 102 103 static void ravb_set_rate_rcar(struct net_device *ndev) 104 { 105 struct ravb_private *priv = netdev_priv(ndev); 106 107 switch (priv->speed) { 108 case 100: /* 100BASE */ 109 ravb_write(ndev, GECMR_SPEED_100, GECMR); 110 break; 111 case 1000: /* 1000BASE */ 112 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 113 break; 114 } 115 } 116 117 static void ravb_set_buffer_align(struct sk_buff *skb) 118 { 119 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 120 121 if (reserve) 122 skb_reserve(skb, RAVB_ALIGN - reserve); 123 } 124 125 /* Get MAC address from the MAC address registers 126 * 127 * Ethernet AVB device doesn't have ROM for MAC address. 128 * This function gets the MAC address that was used by a bootloader. 129 */ 130 static void ravb_read_mac_address(struct device_node *np, 131 struct net_device *ndev) 132 { 133 int ret; 134 135 ret = of_get_ethdev_address(np, ndev); 136 if (ret) { 137 u32 mahr = ravb_read(ndev, MAHR); 138 u32 malr = ravb_read(ndev, MALR); 139 140 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 141 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 142 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 143 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 144 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 145 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 146 } 147 } 148 149 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 150 { 151 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 152 mdiobb); 153 154 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 155 } 156 157 /* MDC pin control */ 158 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 161 } 162 163 /* Data I/O pin control */ 164 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 167 } 168 169 /* Set data bit */ 170 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 171 { 172 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 173 } 174 175 /* Get data bit */ 176 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 177 { 178 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 179 mdiobb); 180 181 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 182 } 183 184 /* MDIO bus control struct */ 185 static const struct mdiobb_ops bb_ops = { 186 .owner = THIS_MODULE, 187 .set_mdc = ravb_set_mdc, 188 .set_mdio_dir = ravb_set_mdio_dir, 189 .set_mdio_data = ravb_set_mdio_data, 190 .get_mdio_data = ravb_get_mdio_data, 191 }; 192 193 /* Free TX skb function for AVB-IP */ 194 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 195 { 196 struct ravb_private *priv = netdev_priv(ndev); 197 struct net_device_stats *stats = &priv->stats[q]; 198 unsigned int num_tx_desc = priv->num_tx_desc; 199 struct ravb_tx_desc *desc; 200 unsigned int entry; 201 int free_num = 0; 202 u32 size; 203 204 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 205 bool txed; 206 207 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 208 num_tx_desc); 209 desc = &priv->tx_ring[q][entry]; 210 txed = desc->die_dt == DT_FEMPTY; 211 if (free_txed_only && !txed) 212 break; 213 /* Descriptor type must be checked before all other reads */ 214 dma_rmb(); 215 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 216 /* Free the original skb. */ 217 if (priv->tx_skb[q][entry / num_tx_desc]) { 218 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 219 size, DMA_TO_DEVICE); 220 /* Last packet descriptor? */ 221 if (entry % num_tx_desc == num_tx_desc - 1) { 222 entry /= num_tx_desc; 223 dev_kfree_skb_any(priv->tx_skb[q][entry]); 224 priv->tx_skb[q][entry] = NULL; 225 if (txed) 226 stats->tx_packets++; 227 } 228 free_num++; 229 } 230 if (txed) 231 stats->tx_bytes += size; 232 desc->die_dt = DT_EEMPTY; 233 } 234 return free_num; 235 } 236 237 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 238 { 239 struct ravb_private *priv = netdev_priv(ndev); 240 unsigned int ring_size; 241 unsigned int i; 242 243 if (!priv->gbeth_rx_ring) 244 return; 245 246 for (i = 0; i < priv->num_rx_ring[q]; i++) { 247 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i]; 248 249 if (!dma_mapping_error(ndev->dev.parent, 250 le32_to_cpu(desc->dptr))) 251 dma_unmap_single(ndev->dev.parent, 252 le32_to_cpu(desc->dptr), 253 GBETH_RX_BUFF_MAX, 254 DMA_FROM_DEVICE); 255 } 256 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 257 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring, 258 priv->rx_desc_dma[q]); 259 priv->gbeth_rx_ring = NULL; 260 } 261 262 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q) 263 { 264 struct ravb_private *priv = netdev_priv(ndev); 265 unsigned int ring_size; 266 unsigned int i; 267 268 if (!priv->rx_ring[q]) 269 return; 270 271 for (i = 0; i < priv->num_rx_ring[q]; i++) { 272 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 273 274 if (!dma_mapping_error(ndev->dev.parent, 275 le32_to_cpu(desc->dptr))) 276 dma_unmap_single(ndev->dev.parent, 277 le32_to_cpu(desc->dptr), 278 RX_BUF_SZ, 279 DMA_FROM_DEVICE); 280 } 281 ring_size = sizeof(struct ravb_ex_rx_desc) * 282 (priv->num_rx_ring[q] + 1); 283 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 284 priv->rx_desc_dma[q]); 285 priv->rx_ring[q] = NULL; 286 } 287 288 /* Free skb's and DMA buffers for Ethernet AVB */ 289 static void ravb_ring_free(struct net_device *ndev, int q) 290 { 291 struct ravb_private *priv = netdev_priv(ndev); 292 const struct ravb_hw_info *info = priv->info; 293 unsigned int num_tx_desc = priv->num_tx_desc; 294 unsigned int ring_size; 295 unsigned int i; 296 297 info->rx_ring_free(ndev, q); 298 299 if (priv->tx_ring[q]) { 300 ravb_tx_free(ndev, q, false); 301 302 ring_size = sizeof(struct ravb_tx_desc) * 303 (priv->num_tx_ring[q] * num_tx_desc + 1); 304 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 305 priv->tx_desc_dma[q]); 306 priv->tx_ring[q] = NULL; 307 } 308 309 /* Free RX skb ringbuffer */ 310 if (priv->rx_skb[q]) { 311 for (i = 0; i < priv->num_rx_ring[q]; i++) 312 dev_kfree_skb(priv->rx_skb[q][i]); 313 } 314 kfree(priv->rx_skb[q]); 315 priv->rx_skb[q] = NULL; 316 317 /* Free aligned TX buffers */ 318 kfree(priv->tx_align[q]); 319 priv->tx_align[q] = NULL; 320 321 /* Free TX skb ringbuffer. 322 * SKBs are freed by ravb_tx_free() call above. 323 */ 324 kfree(priv->tx_skb[q]); 325 priv->tx_skb[q] = NULL; 326 } 327 328 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 329 { 330 struct ravb_private *priv = netdev_priv(ndev); 331 struct ravb_rx_desc *rx_desc; 332 unsigned int rx_ring_size; 333 dma_addr_t dma_addr; 334 unsigned int i; 335 336 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 337 memset(priv->gbeth_rx_ring, 0, rx_ring_size); 338 /* Build RX ring buffer */ 339 for (i = 0; i < priv->num_rx_ring[q]; i++) { 340 /* RX descriptor */ 341 rx_desc = &priv->gbeth_rx_ring[i]; 342 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 343 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 344 GBETH_RX_BUFF_MAX, 345 DMA_FROM_DEVICE); 346 /* We just set the data size to 0 for a failed mapping which 347 * should prevent DMA from happening... 348 */ 349 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 350 rx_desc->ds_cc = cpu_to_le16(0); 351 rx_desc->dptr = cpu_to_le32(dma_addr); 352 rx_desc->die_dt = DT_FEMPTY; 353 } 354 rx_desc = &priv->gbeth_rx_ring[i]; 355 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 356 rx_desc->die_dt = DT_LINKFIX; /* type */ 357 } 358 359 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q) 360 { 361 struct ravb_private *priv = netdev_priv(ndev); 362 struct ravb_ex_rx_desc *rx_desc; 363 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 364 dma_addr_t dma_addr; 365 unsigned int i; 366 367 memset(priv->rx_ring[q], 0, rx_ring_size); 368 /* Build RX ring buffer */ 369 for (i = 0; i < priv->num_rx_ring[q]; i++) { 370 /* RX descriptor */ 371 rx_desc = &priv->rx_ring[q][i]; 372 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 373 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 374 RX_BUF_SZ, 375 DMA_FROM_DEVICE); 376 /* We just set the data size to 0 for a failed mapping which 377 * should prevent DMA from happening... 378 */ 379 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 380 rx_desc->ds_cc = cpu_to_le16(0); 381 rx_desc->dptr = cpu_to_le32(dma_addr); 382 rx_desc->die_dt = DT_FEMPTY; 383 } 384 rx_desc = &priv->rx_ring[q][i]; 385 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 386 rx_desc->die_dt = DT_LINKFIX; /* type */ 387 } 388 389 /* Format skb and descriptor buffer for Ethernet AVB */ 390 static void ravb_ring_format(struct net_device *ndev, int q) 391 { 392 struct ravb_private *priv = netdev_priv(ndev); 393 const struct ravb_hw_info *info = priv->info; 394 unsigned int num_tx_desc = priv->num_tx_desc; 395 struct ravb_tx_desc *tx_desc; 396 struct ravb_desc *desc; 397 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 398 num_tx_desc; 399 unsigned int i; 400 401 priv->cur_rx[q] = 0; 402 priv->cur_tx[q] = 0; 403 priv->dirty_rx[q] = 0; 404 priv->dirty_tx[q] = 0; 405 406 info->rx_ring_format(ndev, q); 407 408 memset(priv->tx_ring[q], 0, tx_ring_size); 409 /* Build TX ring buffer */ 410 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 411 i++, tx_desc++) { 412 tx_desc->die_dt = DT_EEMPTY; 413 if (num_tx_desc > 1) { 414 tx_desc++; 415 tx_desc->die_dt = DT_EEMPTY; 416 } 417 } 418 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 419 tx_desc->die_dt = DT_LINKFIX; /* type */ 420 421 /* RX descriptor base address for best effort */ 422 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 423 desc->die_dt = DT_LINKFIX; /* type */ 424 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 425 426 /* TX descriptor base address for best effort */ 427 desc = &priv->desc_bat[q]; 428 desc->die_dt = DT_LINKFIX; /* type */ 429 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 430 } 431 432 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 433 { 434 struct ravb_private *priv = netdev_priv(ndev); 435 unsigned int ring_size; 436 437 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 438 439 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size, 440 &priv->rx_desc_dma[q], 441 GFP_KERNEL); 442 return priv->gbeth_rx_ring; 443 } 444 445 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q) 446 { 447 struct ravb_private *priv = netdev_priv(ndev); 448 unsigned int ring_size; 449 450 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 451 452 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 453 &priv->rx_desc_dma[q], 454 GFP_KERNEL); 455 return priv->rx_ring[q]; 456 } 457 458 /* Init skb and descriptor buffer for Ethernet AVB */ 459 static int ravb_ring_init(struct net_device *ndev, int q) 460 { 461 struct ravb_private *priv = netdev_priv(ndev); 462 const struct ravb_hw_info *info = priv->info; 463 unsigned int num_tx_desc = priv->num_tx_desc; 464 unsigned int ring_size; 465 struct sk_buff *skb; 466 unsigned int i; 467 468 /* Allocate RX and TX skb rings */ 469 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 470 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 471 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 472 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 473 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 474 goto error; 475 476 for (i = 0; i < priv->num_rx_ring[q]; i++) { 477 skb = netdev_alloc_skb(ndev, info->max_rx_len); 478 if (!skb) 479 goto error; 480 ravb_set_buffer_align(skb); 481 priv->rx_skb[q][i] = skb; 482 } 483 484 if (num_tx_desc > 1) { 485 /* Allocate rings for the aligned buffers */ 486 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 487 DPTR_ALIGN - 1, GFP_KERNEL); 488 if (!priv->tx_align[q]) 489 goto error; 490 } 491 492 /* Allocate all RX descriptors. */ 493 if (!info->alloc_rx_desc(ndev, q)) 494 goto error; 495 496 priv->dirty_rx[q] = 0; 497 498 /* Allocate all TX descriptors. */ 499 ring_size = sizeof(struct ravb_tx_desc) * 500 (priv->num_tx_ring[q] * num_tx_desc + 1); 501 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 502 &priv->tx_desc_dma[q], 503 GFP_KERNEL); 504 if (!priv->tx_ring[q]) 505 goto error; 506 507 return 0; 508 509 error: 510 ravb_ring_free(ndev, q); 511 512 return -ENOMEM; 513 } 514 515 static void ravb_emac_init_gbeth(struct net_device *ndev) 516 { 517 struct ravb_private *priv = netdev_priv(ndev); 518 519 /* Receive frame limit set register */ 520 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 521 522 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 523 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 524 ECMR_TE | ECMR_RE | ECMR_RCPT | 525 ECMR_TXF | ECMR_RXF, ECMR); 526 527 ravb_set_rate_gbeth(ndev); 528 529 /* Set MAC address */ 530 ravb_write(ndev, 531 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 532 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 533 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 534 535 /* E-MAC status register clear */ 536 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 537 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 538 539 /* E-MAC interrupt enable register */ 540 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 541 542 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, CXR31_SEL_LINK0); 543 } 544 545 static void ravb_emac_init_rcar(struct net_device *ndev) 546 { 547 /* Receive frame limit set register */ 548 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 549 550 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 551 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 552 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 553 ECMR_TE | ECMR_RE, ECMR); 554 555 ravb_set_rate_rcar(ndev); 556 557 /* Set MAC address */ 558 ravb_write(ndev, 559 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 560 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 561 ravb_write(ndev, 562 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 563 564 /* E-MAC status register clear */ 565 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 566 567 /* E-MAC interrupt enable register */ 568 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 569 } 570 571 /* E-MAC init function */ 572 static void ravb_emac_init(struct net_device *ndev) 573 { 574 struct ravb_private *priv = netdev_priv(ndev); 575 const struct ravb_hw_info *info = priv->info; 576 577 info->emac_init(ndev); 578 } 579 580 static int ravb_dmac_init_gbeth(struct net_device *ndev) 581 { 582 int error; 583 584 error = ravb_ring_init(ndev, RAVB_BE); 585 if (error) 586 return error; 587 588 /* Descriptor format */ 589 ravb_ring_format(ndev, RAVB_BE); 590 591 /* Set DMAC RX */ 592 ravb_write(ndev, 0x60000000, RCR); 593 594 /* Set Max Frame Length (RTC) */ 595 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 596 597 /* Set FIFO size */ 598 ravb_write(ndev, 0x00222200, TGC); 599 600 ravb_write(ndev, 0, TCCR); 601 602 /* Frame receive */ 603 ravb_write(ndev, RIC0_FRE0, RIC0); 604 /* Disable FIFO full warning */ 605 ravb_write(ndev, 0x0, RIC1); 606 /* Receive FIFO full error, descriptor empty */ 607 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 608 609 ravb_write(ndev, TIC_FTE0, TIC); 610 611 return 0; 612 } 613 614 static int ravb_dmac_init_rcar(struct net_device *ndev) 615 { 616 struct ravb_private *priv = netdev_priv(ndev); 617 const struct ravb_hw_info *info = priv->info; 618 int error; 619 620 error = ravb_ring_init(ndev, RAVB_BE); 621 if (error) 622 return error; 623 error = ravb_ring_init(ndev, RAVB_NC); 624 if (error) { 625 ravb_ring_free(ndev, RAVB_BE); 626 return error; 627 } 628 629 /* Descriptor format */ 630 ravb_ring_format(ndev, RAVB_BE); 631 ravb_ring_format(ndev, RAVB_NC); 632 633 /* Set AVB RX */ 634 ravb_write(ndev, 635 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 636 637 /* Set FIFO size */ 638 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 639 640 /* Timestamp enable */ 641 ravb_write(ndev, TCCR_TFEN, TCCR); 642 643 /* Interrupt init: */ 644 if (info->multi_irqs) { 645 /* Clear DIL.DPLx */ 646 ravb_write(ndev, 0, DIL); 647 /* Set queue specific interrupt */ 648 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 649 } 650 /* Frame receive */ 651 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 652 /* Disable FIFO full warning */ 653 ravb_write(ndev, 0, RIC1); 654 /* Receive FIFO full error, descriptor empty */ 655 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 656 /* Frame transmitted, timestamp FIFO updated */ 657 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 658 659 return 0; 660 } 661 662 /* Device init function for Ethernet AVB */ 663 static int ravb_dmac_init(struct net_device *ndev) 664 { 665 struct ravb_private *priv = netdev_priv(ndev); 666 const struct ravb_hw_info *info = priv->info; 667 int error; 668 669 /* Set CONFIG mode */ 670 error = ravb_config(ndev); 671 if (error) 672 return error; 673 674 error = info->dmac_init(ndev); 675 if (error) 676 return error; 677 678 /* Setting the control will start the AVB-DMAC process. */ 679 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 680 681 return 0; 682 } 683 684 static void ravb_get_tx_tstamp(struct net_device *ndev) 685 { 686 struct ravb_private *priv = netdev_priv(ndev); 687 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 688 struct skb_shared_hwtstamps shhwtstamps; 689 struct sk_buff *skb; 690 struct timespec64 ts; 691 u16 tag, tfa_tag; 692 int count; 693 u32 tfa2; 694 695 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 696 while (count--) { 697 tfa2 = ravb_read(ndev, TFA2); 698 tfa_tag = (tfa2 & TFA2_TST) >> 16; 699 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 700 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 701 ravb_read(ndev, TFA1); 702 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 703 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 704 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 705 list) { 706 skb = ts_skb->skb; 707 tag = ts_skb->tag; 708 list_del(&ts_skb->list); 709 kfree(ts_skb); 710 if (tag == tfa_tag) { 711 skb_tstamp_tx(skb, &shhwtstamps); 712 dev_consume_skb_any(skb); 713 break; 714 } else { 715 dev_kfree_skb_any(skb); 716 } 717 } 718 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 719 } 720 } 721 722 static void ravb_rx_csum(struct sk_buff *skb) 723 { 724 u8 *hw_csum; 725 726 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 727 * appended to packet data 728 */ 729 if (unlikely(skb->len < sizeof(__sum16))) 730 return; 731 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 732 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 733 skb->ip_summed = CHECKSUM_COMPLETE; 734 skb_trim(skb, skb->len - sizeof(__sum16)); 735 } 736 737 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 738 struct ravb_rx_desc *desc) 739 { 740 struct ravb_private *priv = netdev_priv(ndev); 741 struct sk_buff *skb; 742 743 skb = priv->rx_skb[RAVB_BE][entry]; 744 priv->rx_skb[RAVB_BE][entry] = NULL; 745 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 746 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE); 747 748 return skb; 749 } 750 751 /* Packet receive function for Gigabit Ethernet */ 752 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 753 { 754 struct ravb_private *priv = netdev_priv(ndev); 755 const struct ravb_hw_info *info = priv->info; 756 struct net_device_stats *stats; 757 struct ravb_rx_desc *desc; 758 struct sk_buff *skb; 759 dma_addr_t dma_addr; 760 u8 desc_status; 761 int boguscnt; 762 u16 pkt_len; 763 u8 die_dt; 764 int entry; 765 int limit; 766 767 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 768 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 769 stats = &priv->stats[q]; 770 771 boguscnt = min(boguscnt, *quota); 772 limit = boguscnt; 773 desc = &priv->gbeth_rx_ring[entry]; 774 while (desc->die_dt != DT_FEMPTY) { 775 /* Descriptor type must be checked before all other reads */ 776 dma_rmb(); 777 desc_status = desc->msc; 778 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 779 780 if (--boguscnt < 0) 781 break; 782 783 /* We use 0-byte descriptors to mark the DMA mapping errors */ 784 if (!pkt_len) 785 continue; 786 787 if (desc_status & MSC_MC) 788 stats->multicast++; 789 790 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 791 stats->rx_errors++; 792 if (desc_status & MSC_CRC) 793 stats->rx_crc_errors++; 794 if (desc_status & MSC_RFE) 795 stats->rx_frame_errors++; 796 if (desc_status & (MSC_RTLF | MSC_RTSF)) 797 stats->rx_length_errors++; 798 if (desc_status & MSC_CEEF) 799 stats->rx_missed_errors++; 800 } else { 801 die_dt = desc->die_dt & 0xF0; 802 switch (die_dt) { 803 case DT_FSINGLE: 804 skb = ravb_get_skb_gbeth(ndev, entry, desc); 805 skb_put(skb, pkt_len); 806 skb->protocol = eth_type_trans(skb, ndev); 807 napi_gro_receive(&priv->napi[q], skb); 808 stats->rx_packets++; 809 stats->rx_bytes += pkt_len; 810 break; 811 case DT_FSTART: 812 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 813 skb_put(priv->rx_1st_skb, pkt_len); 814 break; 815 case DT_FMID: 816 skb = ravb_get_skb_gbeth(ndev, entry, desc); 817 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 818 priv->rx_1st_skb->len, 819 skb->data, 820 pkt_len); 821 skb_put(priv->rx_1st_skb, pkt_len); 822 dev_kfree_skb(skb); 823 break; 824 case DT_FEND: 825 skb = ravb_get_skb_gbeth(ndev, entry, desc); 826 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 827 priv->rx_1st_skb->len, 828 skb->data, 829 pkt_len); 830 skb_put(priv->rx_1st_skb, pkt_len); 831 dev_kfree_skb(skb); 832 priv->rx_1st_skb->protocol = 833 eth_type_trans(priv->rx_1st_skb, ndev); 834 napi_gro_receive(&priv->napi[q], 835 priv->rx_1st_skb); 836 stats->rx_packets++; 837 stats->rx_bytes += priv->rx_1st_skb->len; 838 break; 839 } 840 } 841 842 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 843 desc = &priv->gbeth_rx_ring[entry]; 844 } 845 846 /* Refill the RX ring buffers. */ 847 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 848 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 849 desc = &priv->gbeth_rx_ring[entry]; 850 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 851 852 if (!priv->rx_skb[q][entry]) { 853 skb = netdev_alloc_skb(ndev, info->max_rx_len); 854 if (!skb) 855 break; 856 ravb_set_buffer_align(skb); 857 dma_addr = dma_map_single(ndev->dev.parent, 858 skb->data, 859 GBETH_RX_BUFF_MAX, 860 DMA_FROM_DEVICE); 861 skb_checksum_none_assert(skb); 862 /* We just set the data size to 0 for a failed mapping 863 * which should prevent DMA from happening... 864 */ 865 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 866 desc->ds_cc = cpu_to_le16(0); 867 desc->dptr = cpu_to_le32(dma_addr); 868 priv->rx_skb[q][entry] = skb; 869 } 870 /* Descriptor type must be set after all the above writes */ 871 dma_wmb(); 872 desc->die_dt = DT_FEMPTY; 873 } 874 875 *quota -= limit - (++boguscnt); 876 877 return boguscnt <= 0; 878 } 879 880 /* Packet receive function for Ethernet AVB */ 881 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 882 { 883 struct ravb_private *priv = netdev_priv(ndev); 884 const struct ravb_hw_info *info = priv->info; 885 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 886 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 887 priv->cur_rx[q]; 888 struct net_device_stats *stats = &priv->stats[q]; 889 struct ravb_ex_rx_desc *desc; 890 struct sk_buff *skb; 891 dma_addr_t dma_addr; 892 struct timespec64 ts; 893 u8 desc_status; 894 u16 pkt_len; 895 int limit; 896 897 boguscnt = min(boguscnt, *quota); 898 limit = boguscnt; 899 desc = &priv->rx_ring[q][entry]; 900 while (desc->die_dt != DT_FEMPTY) { 901 /* Descriptor type must be checked before all other reads */ 902 dma_rmb(); 903 desc_status = desc->msc; 904 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 905 906 if (--boguscnt < 0) 907 break; 908 909 /* We use 0-byte descriptors to mark the DMA mapping errors */ 910 if (!pkt_len) 911 continue; 912 913 if (desc_status & MSC_MC) 914 stats->multicast++; 915 916 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 917 MSC_CEEF)) { 918 stats->rx_errors++; 919 if (desc_status & MSC_CRC) 920 stats->rx_crc_errors++; 921 if (desc_status & MSC_RFE) 922 stats->rx_frame_errors++; 923 if (desc_status & (MSC_RTLF | MSC_RTSF)) 924 stats->rx_length_errors++; 925 if (desc_status & MSC_CEEF) 926 stats->rx_missed_errors++; 927 } else { 928 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 929 930 skb = priv->rx_skb[q][entry]; 931 priv->rx_skb[q][entry] = NULL; 932 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 933 RX_BUF_SZ, 934 DMA_FROM_DEVICE); 935 get_ts &= (q == RAVB_NC) ? 936 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 937 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 938 if (get_ts) { 939 struct skb_shared_hwtstamps *shhwtstamps; 940 941 shhwtstamps = skb_hwtstamps(skb); 942 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 943 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 944 32) | le32_to_cpu(desc->ts_sl); 945 ts.tv_nsec = le32_to_cpu(desc->ts_n); 946 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 947 } 948 949 skb_put(skb, pkt_len); 950 skb->protocol = eth_type_trans(skb, ndev); 951 if (ndev->features & NETIF_F_RXCSUM) 952 ravb_rx_csum(skb); 953 napi_gro_receive(&priv->napi[q], skb); 954 stats->rx_packets++; 955 stats->rx_bytes += pkt_len; 956 } 957 958 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 959 desc = &priv->rx_ring[q][entry]; 960 } 961 962 /* Refill the RX ring buffers. */ 963 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 964 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 965 desc = &priv->rx_ring[q][entry]; 966 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 967 968 if (!priv->rx_skb[q][entry]) { 969 skb = netdev_alloc_skb(ndev, info->max_rx_len); 970 if (!skb) 971 break; /* Better luck next round. */ 972 ravb_set_buffer_align(skb); 973 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 974 le16_to_cpu(desc->ds_cc), 975 DMA_FROM_DEVICE); 976 skb_checksum_none_assert(skb); 977 /* We just set the data size to 0 for a failed mapping 978 * which should prevent DMA from happening... 979 */ 980 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 981 desc->ds_cc = cpu_to_le16(0); 982 desc->dptr = cpu_to_le32(dma_addr); 983 priv->rx_skb[q][entry] = skb; 984 } 985 /* Descriptor type must be set after all the above writes */ 986 dma_wmb(); 987 desc->die_dt = DT_FEMPTY; 988 } 989 990 *quota -= limit - (++boguscnt); 991 992 return boguscnt <= 0; 993 } 994 995 /* Packet receive function for Ethernet AVB */ 996 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 997 { 998 struct ravb_private *priv = netdev_priv(ndev); 999 const struct ravb_hw_info *info = priv->info; 1000 1001 return info->receive(ndev, quota, q); 1002 } 1003 1004 static void ravb_rcv_snd_disable(struct net_device *ndev) 1005 { 1006 /* Disable TX and RX */ 1007 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1008 } 1009 1010 static void ravb_rcv_snd_enable(struct net_device *ndev) 1011 { 1012 /* Enable TX and RX */ 1013 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1014 } 1015 1016 /* function for waiting dma process finished */ 1017 static int ravb_stop_dma(struct net_device *ndev) 1018 { 1019 struct ravb_private *priv = netdev_priv(ndev); 1020 const struct ravb_hw_info *info = priv->info; 1021 int error; 1022 1023 /* Wait for stopping the hardware TX process */ 1024 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1025 1026 if (error) 1027 return error; 1028 1029 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1030 0); 1031 if (error) 1032 return error; 1033 1034 /* Stop the E-MAC's RX/TX processes. */ 1035 ravb_rcv_snd_disable(ndev); 1036 1037 /* Wait for stopping the RX DMA process */ 1038 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1039 if (error) 1040 return error; 1041 1042 /* Stop AVB-DMAC process */ 1043 return ravb_config(ndev); 1044 } 1045 1046 /* E-MAC interrupt handler */ 1047 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1048 { 1049 struct ravb_private *priv = netdev_priv(ndev); 1050 u32 ecsr, psr; 1051 1052 ecsr = ravb_read(ndev, ECSR); 1053 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1054 1055 if (ecsr & ECSR_MPD) 1056 pm_wakeup_event(&priv->pdev->dev, 0); 1057 if (ecsr & ECSR_ICD) 1058 ndev->stats.tx_carrier_errors++; 1059 if (ecsr & ECSR_LCHNG) { 1060 /* Link changed */ 1061 if (priv->no_avb_link) 1062 return; 1063 psr = ravb_read(ndev, PSR); 1064 if (priv->avb_link_active_low) 1065 psr ^= PSR_LMON; 1066 if (!(psr & PSR_LMON)) { 1067 /* DIsable RX and TX */ 1068 ravb_rcv_snd_disable(ndev); 1069 } else { 1070 /* Enable RX and TX */ 1071 ravb_rcv_snd_enable(ndev); 1072 } 1073 } 1074 } 1075 1076 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1077 { 1078 struct net_device *ndev = dev_id; 1079 struct ravb_private *priv = netdev_priv(ndev); 1080 1081 spin_lock(&priv->lock); 1082 ravb_emac_interrupt_unlocked(ndev); 1083 spin_unlock(&priv->lock); 1084 return IRQ_HANDLED; 1085 } 1086 1087 /* Error interrupt handler */ 1088 static void ravb_error_interrupt(struct net_device *ndev) 1089 { 1090 struct ravb_private *priv = netdev_priv(ndev); 1091 u32 eis, ris2; 1092 1093 eis = ravb_read(ndev, EIS); 1094 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1095 if (eis & EIS_QFS) { 1096 ris2 = ravb_read(ndev, RIS2); 1097 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 1098 RIS2); 1099 1100 /* Receive Descriptor Empty int */ 1101 if (ris2 & RIS2_QFF0) 1102 priv->stats[RAVB_BE].rx_over_errors++; 1103 1104 /* Receive Descriptor Empty int */ 1105 if (ris2 & RIS2_QFF1) 1106 priv->stats[RAVB_NC].rx_over_errors++; 1107 1108 /* Receive FIFO Overflow int */ 1109 if (ris2 & RIS2_RFFF) 1110 priv->rx_fifo_errors++; 1111 } 1112 } 1113 1114 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1115 { 1116 struct ravb_private *priv = netdev_priv(ndev); 1117 const struct ravb_hw_info *info = priv->info; 1118 u32 ris0 = ravb_read(ndev, RIS0); 1119 u32 ric0 = ravb_read(ndev, RIC0); 1120 u32 tis = ravb_read(ndev, TIS); 1121 u32 tic = ravb_read(ndev, TIC); 1122 1123 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1124 if (napi_schedule_prep(&priv->napi[q])) { 1125 /* Mask RX and TX interrupts */ 1126 if (!info->multi_irqs) { 1127 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1128 ravb_write(ndev, tic & ~BIT(q), TIC); 1129 } else { 1130 ravb_write(ndev, BIT(q), RID0); 1131 ravb_write(ndev, BIT(q), TID); 1132 } 1133 __napi_schedule(&priv->napi[q]); 1134 } else { 1135 netdev_warn(ndev, 1136 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1137 ris0, ric0); 1138 netdev_warn(ndev, 1139 " tx status 0x%08x, tx mask 0x%08x.\n", 1140 tis, tic); 1141 } 1142 return true; 1143 } 1144 return false; 1145 } 1146 1147 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1148 { 1149 u32 tis = ravb_read(ndev, TIS); 1150 1151 if (tis & TIS_TFUF) { 1152 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1153 ravb_get_tx_tstamp(ndev); 1154 return true; 1155 } 1156 return false; 1157 } 1158 1159 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1160 { 1161 struct net_device *ndev = dev_id; 1162 struct ravb_private *priv = netdev_priv(ndev); 1163 const struct ravb_hw_info *info = priv->info; 1164 irqreturn_t result = IRQ_NONE; 1165 u32 iss; 1166 1167 spin_lock(&priv->lock); 1168 /* Get interrupt status */ 1169 iss = ravb_read(ndev, ISS); 1170 1171 /* Received and transmitted interrupts */ 1172 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1173 int q; 1174 1175 /* Timestamp updated */ 1176 if (ravb_timestamp_interrupt(ndev)) 1177 result = IRQ_HANDLED; 1178 1179 /* Network control and best effort queue RX/TX */ 1180 if (info->nc_queues) { 1181 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1182 if (ravb_queue_interrupt(ndev, q)) 1183 result = IRQ_HANDLED; 1184 } 1185 } else { 1186 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1187 result = IRQ_HANDLED; 1188 } 1189 } 1190 1191 /* E-MAC status summary */ 1192 if (iss & ISS_MS) { 1193 ravb_emac_interrupt_unlocked(ndev); 1194 result = IRQ_HANDLED; 1195 } 1196 1197 /* Error status summary */ 1198 if (iss & ISS_ES) { 1199 ravb_error_interrupt(ndev); 1200 result = IRQ_HANDLED; 1201 } 1202 1203 /* gPTP interrupt status summary */ 1204 if (iss & ISS_CGIS) { 1205 ravb_ptp_interrupt(ndev); 1206 result = IRQ_HANDLED; 1207 } 1208 1209 spin_unlock(&priv->lock); 1210 return result; 1211 } 1212 1213 /* Timestamp/Error/gPTP interrupt handler */ 1214 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1215 { 1216 struct net_device *ndev = dev_id; 1217 struct ravb_private *priv = netdev_priv(ndev); 1218 irqreturn_t result = IRQ_NONE; 1219 u32 iss; 1220 1221 spin_lock(&priv->lock); 1222 /* Get interrupt status */ 1223 iss = ravb_read(ndev, ISS); 1224 1225 /* Timestamp updated */ 1226 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1227 result = IRQ_HANDLED; 1228 1229 /* Error status summary */ 1230 if (iss & ISS_ES) { 1231 ravb_error_interrupt(ndev); 1232 result = IRQ_HANDLED; 1233 } 1234 1235 /* gPTP interrupt status summary */ 1236 if (iss & ISS_CGIS) { 1237 ravb_ptp_interrupt(ndev); 1238 result = IRQ_HANDLED; 1239 } 1240 1241 spin_unlock(&priv->lock); 1242 return result; 1243 } 1244 1245 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1246 { 1247 struct net_device *ndev = dev_id; 1248 struct ravb_private *priv = netdev_priv(ndev); 1249 irqreturn_t result = IRQ_NONE; 1250 1251 spin_lock(&priv->lock); 1252 1253 /* Network control/Best effort queue RX/TX */ 1254 if (ravb_queue_interrupt(ndev, q)) 1255 result = IRQ_HANDLED; 1256 1257 spin_unlock(&priv->lock); 1258 return result; 1259 } 1260 1261 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1262 { 1263 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1264 } 1265 1266 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1267 { 1268 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1269 } 1270 1271 static int ravb_poll(struct napi_struct *napi, int budget) 1272 { 1273 struct net_device *ndev = napi->dev; 1274 struct ravb_private *priv = netdev_priv(ndev); 1275 const struct ravb_hw_info *info = priv->info; 1276 bool gptp = info->gptp || info->ccc_gac; 1277 struct ravb_rx_desc *desc; 1278 unsigned long flags; 1279 int q = napi - priv->napi; 1280 int mask = BIT(q); 1281 int quota = budget; 1282 unsigned int entry; 1283 1284 if (!gptp) { 1285 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 1286 desc = &priv->gbeth_rx_ring[entry]; 1287 } 1288 /* Processing RX Descriptor Ring */ 1289 /* Clear RX interrupt */ 1290 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1291 if (gptp || desc->die_dt != DT_FEMPTY) { 1292 if (ravb_rx(ndev, "a, q)) 1293 goto out; 1294 } 1295 1296 /* Processing TX Descriptor Ring */ 1297 spin_lock_irqsave(&priv->lock, flags); 1298 /* Clear TX interrupt */ 1299 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1300 ravb_tx_free(ndev, q, true); 1301 netif_wake_subqueue(ndev, q); 1302 spin_unlock_irqrestore(&priv->lock, flags); 1303 1304 napi_complete(napi); 1305 1306 /* Re-enable RX/TX interrupts */ 1307 spin_lock_irqsave(&priv->lock, flags); 1308 if (!info->multi_irqs) { 1309 ravb_modify(ndev, RIC0, mask, mask); 1310 ravb_modify(ndev, TIC, mask, mask); 1311 } else { 1312 ravb_write(ndev, mask, RIE0); 1313 ravb_write(ndev, mask, TIE); 1314 } 1315 spin_unlock_irqrestore(&priv->lock, flags); 1316 1317 /* Receive error message handling */ 1318 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1319 if (info->nc_queues) 1320 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1321 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1322 ndev->stats.rx_over_errors = priv->rx_over_errors; 1323 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1324 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1325 out: 1326 return budget - quota; 1327 } 1328 1329 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1330 { 1331 struct ravb_private *priv = netdev_priv(ndev); 1332 1333 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1334 } 1335 1336 /* PHY state control function */ 1337 static void ravb_adjust_link(struct net_device *ndev) 1338 { 1339 struct ravb_private *priv = netdev_priv(ndev); 1340 const struct ravb_hw_info *info = priv->info; 1341 struct phy_device *phydev = ndev->phydev; 1342 bool new_state = false; 1343 unsigned long flags; 1344 1345 spin_lock_irqsave(&priv->lock, flags); 1346 1347 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1348 if (priv->no_avb_link) 1349 ravb_rcv_snd_disable(ndev); 1350 1351 if (phydev->link) { 1352 if (info->half_duplex && phydev->duplex != priv->duplex) { 1353 new_state = true; 1354 priv->duplex = phydev->duplex; 1355 ravb_set_duplex_gbeth(ndev); 1356 } 1357 1358 if (phydev->speed != priv->speed) { 1359 new_state = true; 1360 priv->speed = phydev->speed; 1361 info->set_rate(ndev); 1362 } 1363 if (!priv->link) { 1364 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1365 new_state = true; 1366 priv->link = phydev->link; 1367 } 1368 } else if (priv->link) { 1369 new_state = true; 1370 priv->link = 0; 1371 priv->speed = 0; 1372 if (info->half_duplex) 1373 priv->duplex = -1; 1374 } 1375 1376 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1377 if (priv->no_avb_link && phydev->link) 1378 ravb_rcv_snd_enable(ndev); 1379 1380 spin_unlock_irqrestore(&priv->lock, flags); 1381 1382 if (new_state && netif_msg_link(priv)) 1383 phy_print_status(phydev); 1384 } 1385 1386 static const struct soc_device_attribute r8a7795es10[] = { 1387 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1388 { /* sentinel */ } 1389 }; 1390 1391 /* PHY init function */ 1392 static int ravb_phy_init(struct net_device *ndev) 1393 { 1394 struct device_node *np = ndev->dev.parent->of_node; 1395 struct ravb_private *priv = netdev_priv(ndev); 1396 const struct ravb_hw_info *info = priv->info; 1397 struct phy_device *phydev; 1398 struct device_node *pn; 1399 phy_interface_t iface; 1400 int err; 1401 1402 priv->link = 0; 1403 priv->speed = 0; 1404 priv->duplex = -1; 1405 1406 /* Try connecting to PHY */ 1407 pn = of_parse_phandle(np, "phy-handle", 0); 1408 if (!pn) { 1409 /* In the case of a fixed PHY, the DT node associated 1410 * to the PHY is the Ethernet MAC DT node. 1411 */ 1412 if (of_phy_is_fixed_link(np)) { 1413 err = of_phy_register_fixed_link(np); 1414 if (err) 1415 return err; 1416 } 1417 pn = of_node_get(np); 1418 } 1419 1420 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1421 : priv->phy_interface; 1422 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1423 of_node_put(pn); 1424 if (!phydev) { 1425 netdev_err(ndev, "failed to connect PHY\n"); 1426 err = -ENOENT; 1427 goto err_deregister_fixed_link; 1428 } 1429 1430 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1431 * at this time. 1432 */ 1433 if (soc_device_match(r8a7795es10)) { 1434 err = phy_set_max_speed(phydev, SPEED_100); 1435 if (err) { 1436 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1437 goto err_phy_disconnect; 1438 } 1439 1440 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1441 } 1442 1443 if (!info->half_duplex) { 1444 /* 10BASE, Pause and Asym Pause is not supported */ 1445 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1446 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1447 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1448 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1449 1450 /* Half Duplex is not supported */ 1451 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1452 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1453 } 1454 1455 phy_attached_info(phydev); 1456 1457 return 0; 1458 1459 err_phy_disconnect: 1460 phy_disconnect(phydev); 1461 err_deregister_fixed_link: 1462 if (of_phy_is_fixed_link(np)) 1463 of_phy_deregister_fixed_link(np); 1464 1465 return err; 1466 } 1467 1468 /* PHY control start function */ 1469 static int ravb_phy_start(struct net_device *ndev) 1470 { 1471 int error; 1472 1473 error = ravb_phy_init(ndev); 1474 if (error) 1475 return error; 1476 1477 phy_start(ndev->phydev); 1478 1479 return 0; 1480 } 1481 1482 static u32 ravb_get_msglevel(struct net_device *ndev) 1483 { 1484 struct ravb_private *priv = netdev_priv(ndev); 1485 1486 return priv->msg_enable; 1487 } 1488 1489 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1490 { 1491 struct ravb_private *priv = netdev_priv(ndev); 1492 1493 priv->msg_enable = value; 1494 } 1495 1496 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1497 "rx_queue_0_current", 1498 "tx_queue_0_current", 1499 "rx_queue_0_dirty", 1500 "tx_queue_0_dirty", 1501 "rx_queue_0_packets", 1502 "tx_queue_0_packets", 1503 "rx_queue_0_bytes", 1504 "tx_queue_0_bytes", 1505 "rx_queue_0_mcast_packets", 1506 "rx_queue_0_errors", 1507 "rx_queue_0_crc_errors", 1508 "rx_queue_0_frame_errors", 1509 "rx_queue_0_length_errors", 1510 "rx_queue_0_csum_offload_errors", 1511 "rx_queue_0_over_errors", 1512 }; 1513 1514 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1515 "rx_queue_0_current", 1516 "tx_queue_0_current", 1517 "rx_queue_0_dirty", 1518 "tx_queue_0_dirty", 1519 "rx_queue_0_packets", 1520 "tx_queue_0_packets", 1521 "rx_queue_0_bytes", 1522 "tx_queue_0_bytes", 1523 "rx_queue_0_mcast_packets", 1524 "rx_queue_0_errors", 1525 "rx_queue_0_crc_errors", 1526 "rx_queue_0_frame_errors", 1527 "rx_queue_0_length_errors", 1528 "rx_queue_0_missed_errors", 1529 "rx_queue_0_over_errors", 1530 1531 "rx_queue_1_current", 1532 "tx_queue_1_current", 1533 "rx_queue_1_dirty", 1534 "tx_queue_1_dirty", 1535 "rx_queue_1_packets", 1536 "tx_queue_1_packets", 1537 "rx_queue_1_bytes", 1538 "tx_queue_1_bytes", 1539 "rx_queue_1_mcast_packets", 1540 "rx_queue_1_errors", 1541 "rx_queue_1_crc_errors", 1542 "rx_queue_1_frame_errors", 1543 "rx_queue_1_length_errors", 1544 "rx_queue_1_missed_errors", 1545 "rx_queue_1_over_errors", 1546 }; 1547 1548 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1549 { 1550 struct ravb_private *priv = netdev_priv(netdev); 1551 const struct ravb_hw_info *info = priv->info; 1552 1553 switch (sset) { 1554 case ETH_SS_STATS: 1555 return info->stats_len; 1556 default: 1557 return -EOPNOTSUPP; 1558 } 1559 } 1560 1561 static void ravb_get_ethtool_stats(struct net_device *ndev, 1562 struct ethtool_stats *estats, u64 *data) 1563 { 1564 struct ravb_private *priv = netdev_priv(ndev); 1565 const struct ravb_hw_info *info = priv->info; 1566 int num_rx_q; 1567 int i = 0; 1568 int q; 1569 1570 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1571 /* Device-specific stats */ 1572 for (q = RAVB_BE; q < num_rx_q; q++) { 1573 struct net_device_stats *stats = &priv->stats[q]; 1574 1575 data[i++] = priv->cur_rx[q]; 1576 data[i++] = priv->cur_tx[q]; 1577 data[i++] = priv->dirty_rx[q]; 1578 data[i++] = priv->dirty_tx[q]; 1579 data[i++] = stats->rx_packets; 1580 data[i++] = stats->tx_packets; 1581 data[i++] = stats->rx_bytes; 1582 data[i++] = stats->tx_bytes; 1583 data[i++] = stats->multicast; 1584 data[i++] = stats->rx_errors; 1585 data[i++] = stats->rx_crc_errors; 1586 data[i++] = stats->rx_frame_errors; 1587 data[i++] = stats->rx_length_errors; 1588 data[i++] = stats->rx_missed_errors; 1589 data[i++] = stats->rx_over_errors; 1590 } 1591 } 1592 1593 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1594 { 1595 struct ravb_private *priv = netdev_priv(ndev); 1596 const struct ravb_hw_info *info = priv->info; 1597 1598 switch (stringset) { 1599 case ETH_SS_STATS: 1600 memcpy(data, info->gstrings_stats, info->gstrings_size); 1601 break; 1602 } 1603 } 1604 1605 static void ravb_get_ringparam(struct net_device *ndev, 1606 struct ethtool_ringparam *ring) 1607 { 1608 struct ravb_private *priv = netdev_priv(ndev); 1609 1610 ring->rx_max_pending = BE_RX_RING_MAX; 1611 ring->tx_max_pending = BE_TX_RING_MAX; 1612 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1613 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1614 } 1615 1616 static int ravb_set_ringparam(struct net_device *ndev, 1617 struct ethtool_ringparam *ring) 1618 { 1619 struct ravb_private *priv = netdev_priv(ndev); 1620 const struct ravb_hw_info *info = priv->info; 1621 int error; 1622 1623 if (ring->tx_pending > BE_TX_RING_MAX || 1624 ring->rx_pending > BE_RX_RING_MAX || 1625 ring->tx_pending < BE_TX_RING_MIN || 1626 ring->rx_pending < BE_RX_RING_MIN) 1627 return -EINVAL; 1628 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1629 return -EINVAL; 1630 1631 if (netif_running(ndev)) { 1632 netif_device_detach(ndev); 1633 /* Stop PTP Clock driver */ 1634 if (info->gptp) 1635 ravb_ptp_stop(ndev); 1636 /* Wait for DMA stopping */ 1637 error = ravb_stop_dma(ndev); 1638 if (error) { 1639 netdev_err(ndev, 1640 "cannot set ringparam! Any AVB processes are still running?\n"); 1641 return error; 1642 } 1643 synchronize_irq(ndev->irq); 1644 1645 /* Free all the skb's in the RX queue and the DMA buffers. */ 1646 ravb_ring_free(ndev, RAVB_BE); 1647 if (info->nc_queues) 1648 ravb_ring_free(ndev, RAVB_NC); 1649 } 1650 1651 /* Set new parameters */ 1652 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1653 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1654 1655 if (netif_running(ndev)) { 1656 error = ravb_dmac_init(ndev); 1657 if (error) { 1658 netdev_err(ndev, 1659 "%s: ravb_dmac_init() failed, error %d\n", 1660 __func__, error); 1661 return error; 1662 } 1663 1664 ravb_emac_init(ndev); 1665 1666 /* Initialise PTP Clock driver */ 1667 if (info->gptp) 1668 ravb_ptp_init(ndev, priv->pdev); 1669 1670 netif_device_attach(ndev); 1671 } 1672 1673 return 0; 1674 } 1675 1676 static int ravb_get_ts_info(struct net_device *ndev, 1677 struct ethtool_ts_info *info) 1678 { 1679 struct ravb_private *priv = netdev_priv(ndev); 1680 const struct ravb_hw_info *hw_info = priv->info; 1681 1682 info->so_timestamping = 1683 SOF_TIMESTAMPING_TX_SOFTWARE | 1684 SOF_TIMESTAMPING_RX_SOFTWARE | 1685 SOF_TIMESTAMPING_SOFTWARE | 1686 SOF_TIMESTAMPING_TX_HARDWARE | 1687 SOF_TIMESTAMPING_RX_HARDWARE | 1688 SOF_TIMESTAMPING_RAW_HARDWARE; 1689 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1690 info->rx_filters = 1691 (1 << HWTSTAMP_FILTER_NONE) | 1692 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1693 (1 << HWTSTAMP_FILTER_ALL); 1694 if (hw_info->gptp || hw_info->ccc_gac) 1695 info->phc_index = ptp_clock_index(priv->ptp.clock); 1696 1697 return 0; 1698 } 1699 1700 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1701 { 1702 struct ravb_private *priv = netdev_priv(ndev); 1703 1704 wol->supported = WAKE_MAGIC; 1705 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1706 } 1707 1708 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1709 { 1710 struct ravb_private *priv = netdev_priv(ndev); 1711 const struct ravb_hw_info *info = priv->info; 1712 1713 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1714 return -EOPNOTSUPP; 1715 1716 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1717 1718 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1719 1720 return 0; 1721 } 1722 1723 static const struct ethtool_ops ravb_ethtool_ops = { 1724 .nway_reset = phy_ethtool_nway_reset, 1725 .get_msglevel = ravb_get_msglevel, 1726 .set_msglevel = ravb_set_msglevel, 1727 .get_link = ethtool_op_get_link, 1728 .get_strings = ravb_get_strings, 1729 .get_ethtool_stats = ravb_get_ethtool_stats, 1730 .get_sset_count = ravb_get_sset_count, 1731 .get_ringparam = ravb_get_ringparam, 1732 .set_ringparam = ravb_set_ringparam, 1733 .get_ts_info = ravb_get_ts_info, 1734 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1735 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1736 .get_wol = ravb_get_wol, 1737 .set_wol = ravb_set_wol, 1738 }; 1739 1740 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1741 struct net_device *ndev, struct device *dev, 1742 const char *ch) 1743 { 1744 char *name; 1745 int error; 1746 1747 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1748 if (!name) 1749 return -ENOMEM; 1750 error = request_irq(irq, handler, 0, name, ndev); 1751 if (error) 1752 netdev_err(ndev, "cannot request IRQ %s\n", name); 1753 1754 return error; 1755 } 1756 1757 /* Network device open function for Ethernet AVB */ 1758 static int ravb_open(struct net_device *ndev) 1759 { 1760 struct ravb_private *priv = netdev_priv(ndev); 1761 const struct ravb_hw_info *info = priv->info; 1762 struct platform_device *pdev = priv->pdev; 1763 struct device *dev = &pdev->dev; 1764 int error; 1765 1766 napi_enable(&priv->napi[RAVB_BE]); 1767 if (info->nc_queues) 1768 napi_enable(&priv->napi[RAVB_NC]); 1769 1770 if (!info->multi_irqs) { 1771 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1772 ndev->name, ndev); 1773 if (error) { 1774 netdev_err(ndev, "cannot request IRQ\n"); 1775 goto out_napi_off; 1776 } 1777 } else { 1778 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1779 dev, "ch22:multi"); 1780 if (error) 1781 goto out_napi_off; 1782 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1783 dev, "ch24:emac"); 1784 if (error) 1785 goto out_free_irq; 1786 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1787 ndev, dev, "ch0:rx_be"); 1788 if (error) 1789 goto out_free_irq_emac; 1790 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1791 ndev, dev, "ch18:tx_be"); 1792 if (error) 1793 goto out_free_irq_be_rx; 1794 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1795 ndev, dev, "ch1:rx_nc"); 1796 if (error) 1797 goto out_free_irq_be_tx; 1798 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1799 ndev, dev, "ch19:tx_nc"); 1800 if (error) 1801 goto out_free_irq_nc_rx; 1802 } 1803 1804 /* Device init */ 1805 error = ravb_dmac_init(ndev); 1806 if (error) 1807 goto out_free_irq_nc_tx; 1808 ravb_emac_init(ndev); 1809 1810 /* Initialise PTP Clock driver */ 1811 if (info->gptp) 1812 ravb_ptp_init(ndev, priv->pdev); 1813 1814 netif_tx_start_all_queues(ndev); 1815 1816 /* PHY control start */ 1817 error = ravb_phy_start(ndev); 1818 if (error) 1819 goto out_ptp_stop; 1820 1821 return 0; 1822 1823 out_ptp_stop: 1824 /* Stop PTP Clock driver */ 1825 if (info->gptp) 1826 ravb_ptp_stop(ndev); 1827 out_free_irq_nc_tx: 1828 if (!info->multi_irqs) 1829 goto out_free_irq; 1830 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1831 out_free_irq_nc_rx: 1832 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1833 out_free_irq_be_tx: 1834 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1835 out_free_irq_be_rx: 1836 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1837 out_free_irq_emac: 1838 free_irq(priv->emac_irq, ndev); 1839 out_free_irq: 1840 free_irq(ndev->irq, ndev); 1841 out_napi_off: 1842 if (info->nc_queues) 1843 napi_disable(&priv->napi[RAVB_NC]); 1844 napi_disable(&priv->napi[RAVB_BE]); 1845 return error; 1846 } 1847 1848 /* Timeout function for Ethernet AVB */ 1849 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1850 { 1851 struct ravb_private *priv = netdev_priv(ndev); 1852 1853 netif_err(priv, tx_err, ndev, 1854 "transmit timed out, status %08x, resetting...\n", 1855 ravb_read(ndev, ISS)); 1856 1857 /* tx_errors count up */ 1858 ndev->stats.tx_errors++; 1859 1860 schedule_work(&priv->work); 1861 } 1862 1863 static void ravb_tx_timeout_work(struct work_struct *work) 1864 { 1865 struct ravb_private *priv = container_of(work, struct ravb_private, 1866 work); 1867 const struct ravb_hw_info *info = priv->info; 1868 struct net_device *ndev = priv->ndev; 1869 int error; 1870 1871 netif_tx_stop_all_queues(ndev); 1872 1873 /* Stop PTP Clock driver */ 1874 if (info->gptp) 1875 ravb_ptp_stop(ndev); 1876 1877 /* Wait for DMA stopping */ 1878 if (ravb_stop_dma(ndev)) { 1879 /* If ravb_stop_dma() fails, the hardware is still operating 1880 * for TX and/or RX. So, this should not call the following 1881 * functions because ravb_dmac_init() is possible to fail too. 1882 * Also, this should not retry ravb_stop_dma() again and again 1883 * here because it's possible to wait forever. So, this just 1884 * re-enables the TX and RX and skip the following 1885 * re-initialization procedure. 1886 */ 1887 ravb_rcv_snd_enable(ndev); 1888 goto out; 1889 } 1890 1891 ravb_ring_free(ndev, RAVB_BE); 1892 if (info->nc_queues) 1893 ravb_ring_free(ndev, RAVB_NC); 1894 1895 /* Device init */ 1896 error = ravb_dmac_init(ndev); 1897 if (error) { 1898 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1899 * should return here to avoid re-enabling the TX and RX in 1900 * ravb_emac_init(). 1901 */ 1902 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1903 __func__, error); 1904 return; 1905 } 1906 ravb_emac_init(ndev); 1907 1908 out: 1909 /* Initialise PTP Clock driver */ 1910 if (info->gptp) 1911 ravb_ptp_init(ndev, priv->pdev); 1912 1913 netif_tx_start_all_queues(ndev); 1914 } 1915 1916 /* Packet transmit function for Ethernet AVB */ 1917 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1918 { 1919 struct ravb_private *priv = netdev_priv(ndev); 1920 const struct ravb_hw_info *info = priv->info; 1921 unsigned int num_tx_desc = priv->num_tx_desc; 1922 u16 q = skb_get_queue_mapping(skb); 1923 struct ravb_tstamp_skb *ts_skb; 1924 struct ravb_tx_desc *desc; 1925 unsigned long flags; 1926 u32 dma_addr; 1927 void *buffer; 1928 u32 entry; 1929 u32 len; 1930 1931 spin_lock_irqsave(&priv->lock, flags); 1932 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1933 num_tx_desc) { 1934 netif_err(priv, tx_queued, ndev, 1935 "still transmitting with the full ring!\n"); 1936 netif_stop_subqueue(ndev, q); 1937 spin_unlock_irqrestore(&priv->lock, flags); 1938 return NETDEV_TX_BUSY; 1939 } 1940 1941 if (skb_put_padto(skb, ETH_ZLEN)) 1942 goto exit; 1943 1944 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1945 priv->tx_skb[q][entry / num_tx_desc] = skb; 1946 1947 if (num_tx_desc > 1) { 1948 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1949 entry / num_tx_desc * DPTR_ALIGN; 1950 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1951 1952 /* Zero length DMA descriptors are problematic as they seem 1953 * to terminate DMA transfers. Avoid them by simply using a 1954 * length of DPTR_ALIGN (4) when skb data is aligned to 1955 * DPTR_ALIGN. 1956 * 1957 * As skb is guaranteed to have at least ETH_ZLEN (60) 1958 * bytes of data by the call to skb_put_padto() above this 1959 * is safe with respect to both the length of the first DMA 1960 * descriptor (len) overflowing the available data and the 1961 * length of the second DMA descriptor (skb->len - len) 1962 * being negative. 1963 */ 1964 if (len == 0) 1965 len = DPTR_ALIGN; 1966 1967 memcpy(buffer, skb->data, len); 1968 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1969 DMA_TO_DEVICE); 1970 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1971 goto drop; 1972 1973 desc = &priv->tx_ring[q][entry]; 1974 desc->ds_tagl = cpu_to_le16(len); 1975 desc->dptr = cpu_to_le32(dma_addr); 1976 1977 buffer = skb->data + len; 1978 len = skb->len - len; 1979 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1980 DMA_TO_DEVICE); 1981 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1982 goto unmap; 1983 1984 desc++; 1985 } else { 1986 desc = &priv->tx_ring[q][entry]; 1987 len = skb->len; 1988 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1989 DMA_TO_DEVICE); 1990 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1991 goto drop; 1992 } 1993 desc->ds_tagl = cpu_to_le16(len); 1994 desc->dptr = cpu_to_le32(dma_addr); 1995 1996 /* TX timestamp required */ 1997 if (info->gptp || info->ccc_gac) { 1998 if (q == RAVB_NC) { 1999 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2000 if (!ts_skb) { 2001 if (num_tx_desc > 1) { 2002 desc--; 2003 dma_unmap_single(ndev->dev.parent, dma_addr, 2004 len, DMA_TO_DEVICE); 2005 } 2006 goto unmap; 2007 } 2008 ts_skb->skb = skb_get(skb); 2009 ts_skb->tag = priv->ts_skb_tag++; 2010 priv->ts_skb_tag &= 0x3ff; 2011 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2012 2013 /* TAG and timestamp required flag */ 2014 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2015 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2016 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2017 } 2018 2019 skb_tx_timestamp(skb); 2020 } 2021 /* Descriptor type must be set after all the above writes */ 2022 dma_wmb(); 2023 if (num_tx_desc > 1) { 2024 desc->die_dt = DT_FEND; 2025 desc--; 2026 desc->die_dt = DT_FSTART; 2027 } else { 2028 desc->die_dt = DT_FSINGLE; 2029 } 2030 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2031 2032 priv->cur_tx[q] += num_tx_desc; 2033 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2034 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2035 !ravb_tx_free(ndev, q, true)) 2036 netif_stop_subqueue(ndev, q); 2037 2038 exit: 2039 spin_unlock_irqrestore(&priv->lock, flags); 2040 return NETDEV_TX_OK; 2041 2042 unmap: 2043 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2044 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2045 drop: 2046 dev_kfree_skb_any(skb); 2047 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2048 goto exit; 2049 } 2050 2051 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2052 struct net_device *sb_dev) 2053 { 2054 /* If skb needs TX timestamp, it is handled in network control queue */ 2055 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2056 RAVB_BE; 2057 2058 } 2059 2060 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2061 { 2062 struct ravb_private *priv = netdev_priv(ndev); 2063 const struct ravb_hw_info *info = priv->info; 2064 struct net_device_stats *nstats, *stats0, *stats1; 2065 2066 nstats = &ndev->stats; 2067 stats0 = &priv->stats[RAVB_BE]; 2068 2069 if (info->tx_counters) { 2070 nstats->tx_dropped += ravb_read(ndev, TROCR); 2071 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2072 } 2073 2074 if (info->carrier_counters) { 2075 nstats->collisions += ravb_read(ndev, CXR41); 2076 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2077 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2078 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2079 } 2080 2081 nstats->rx_packets = stats0->rx_packets; 2082 nstats->tx_packets = stats0->tx_packets; 2083 nstats->rx_bytes = stats0->rx_bytes; 2084 nstats->tx_bytes = stats0->tx_bytes; 2085 nstats->multicast = stats0->multicast; 2086 nstats->rx_errors = stats0->rx_errors; 2087 nstats->rx_crc_errors = stats0->rx_crc_errors; 2088 nstats->rx_frame_errors = stats0->rx_frame_errors; 2089 nstats->rx_length_errors = stats0->rx_length_errors; 2090 nstats->rx_missed_errors = stats0->rx_missed_errors; 2091 nstats->rx_over_errors = stats0->rx_over_errors; 2092 if (info->nc_queues) { 2093 stats1 = &priv->stats[RAVB_NC]; 2094 2095 nstats->rx_packets += stats1->rx_packets; 2096 nstats->tx_packets += stats1->tx_packets; 2097 nstats->rx_bytes += stats1->rx_bytes; 2098 nstats->tx_bytes += stats1->tx_bytes; 2099 nstats->multicast += stats1->multicast; 2100 nstats->rx_errors += stats1->rx_errors; 2101 nstats->rx_crc_errors += stats1->rx_crc_errors; 2102 nstats->rx_frame_errors += stats1->rx_frame_errors; 2103 nstats->rx_length_errors += stats1->rx_length_errors; 2104 nstats->rx_missed_errors += stats1->rx_missed_errors; 2105 nstats->rx_over_errors += stats1->rx_over_errors; 2106 } 2107 2108 return nstats; 2109 } 2110 2111 /* Update promiscuous bit */ 2112 static void ravb_set_rx_mode(struct net_device *ndev) 2113 { 2114 struct ravb_private *priv = netdev_priv(ndev); 2115 unsigned long flags; 2116 2117 spin_lock_irqsave(&priv->lock, flags); 2118 ravb_modify(ndev, ECMR, ECMR_PRM, 2119 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2120 spin_unlock_irqrestore(&priv->lock, flags); 2121 } 2122 2123 /* Device close function for Ethernet AVB */ 2124 static int ravb_close(struct net_device *ndev) 2125 { 2126 struct device_node *np = ndev->dev.parent->of_node; 2127 struct ravb_private *priv = netdev_priv(ndev); 2128 const struct ravb_hw_info *info = priv->info; 2129 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2130 2131 netif_tx_stop_all_queues(ndev); 2132 2133 /* Disable interrupts by clearing the interrupt masks. */ 2134 ravb_write(ndev, 0, RIC0); 2135 ravb_write(ndev, 0, RIC2); 2136 ravb_write(ndev, 0, TIC); 2137 2138 /* Stop PTP Clock driver */ 2139 if (info->gptp) 2140 ravb_ptp_stop(ndev); 2141 2142 /* Set the config mode to stop the AVB-DMAC's processes */ 2143 if (ravb_stop_dma(ndev) < 0) 2144 netdev_err(ndev, 2145 "device will be stopped after h/w processes are done.\n"); 2146 2147 /* Clear the timestamp list */ 2148 if (info->gptp || info->ccc_gac) { 2149 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2150 list_del(&ts_skb->list); 2151 kfree_skb(ts_skb->skb); 2152 kfree(ts_skb); 2153 } 2154 } 2155 2156 /* PHY disconnect */ 2157 if (ndev->phydev) { 2158 phy_stop(ndev->phydev); 2159 phy_disconnect(ndev->phydev); 2160 if (of_phy_is_fixed_link(np)) 2161 of_phy_deregister_fixed_link(np); 2162 } 2163 2164 if (info->multi_irqs) { 2165 free_irq(priv->tx_irqs[RAVB_NC], ndev); 2166 free_irq(priv->rx_irqs[RAVB_NC], ndev); 2167 free_irq(priv->tx_irqs[RAVB_BE], ndev); 2168 free_irq(priv->rx_irqs[RAVB_BE], ndev); 2169 free_irq(priv->emac_irq, ndev); 2170 } 2171 free_irq(ndev->irq, ndev); 2172 2173 if (info->nc_queues) 2174 napi_disable(&priv->napi[RAVB_NC]); 2175 napi_disable(&priv->napi[RAVB_BE]); 2176 2177 /* Free all the skb's in the RX queue and the DMA buffers. */ 2178 ravb_ring_free(ndev, RAVB_BE); 2179 if (info->nc_queues) 2180 ravb_ring_free(ndev, RAVB_NC); 2181 2182 return 0; 2183 } 2184 2185 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2186 { 2187 struct ravb_private *priv = netdev_priv(ndev); 2188 struct hwtstamp_config config; 2189 2190 config.flags = 0; 2191 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2192 HWTSTAMP_TX_OFF; 2193 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2194 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2195 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2196 break; 2197 case RAVB_RXTSTAMP_TYPE_ALL: 2198 config.rx_filter = HWTSTAMP_FILTER_ALL; 2199 break; 2200 default: 2201 config.rx_filter = HWTSTAMP_FILTER_NONE; 2202 } 2203 2204 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2205 -EFAULT : 0; 2206 } 2207 2208 /* Control hardware time stamping */ 2209 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2210 { 2211 struct ravb_private *priv = netdev_priv(ndev); 2212 struct hwtstamp_config config; 2213 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2214 u32 tstamp_tx_ctrl; 2215 2216 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2217 return -EFAULT; 2218 2219 /* Reserved for future extensions */ 2220 if (config.flags) 2221 return -EINVAL; 2222 2223 switch (config.tx_type) { 2224 case HWTSTAMP_TX_OFF: 2225 tstamp_tx_ctrl = 0; 2226 break; 2227 case HWTSTAMP_TX_ON: 2228 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2229 break; 2230 default: 2231 return -ERANGE; 2232 } 2233 2234 switch (config.rx_filter) { 2235 case HWTSTAMP_FILTER_NONE: 2236 tstamp_rx_ctrl = 0; 2237 break; 2238 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2239 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2240 break; 2241 default: 2242 config.rx_filter = HWTSTAMP_FILTER_ALL; 2243 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2244 } 2245 2246 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2247 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2248 2249 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2250 -EFAULT : 0; 2251 } 2252 2253 /* ioctl to device function */ 2254 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2255 { 2256 struct phy_device *phydev = ndev->phydev; 2257 2258 if (!netif_running(ndev)) 2259 return -EINVAL; 2260 2261 if (!phydev) 2262 return -ENODEV; 2263 2264 switch (cmd) { 2265 case SIOCGHWTSTAMP: 2266 return ravb_hwtstamp_get(ndev, req); 2267 case SIOCSHWTSTAMP: 2268 return ravb_hwtstamp_set(ndev, req); 2269 } 2270 2271 return phy_mii_ioctl(phydev, req, cmd); 2272 } 2273 2274 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2275 { 2276 struct ravb_private *priv = netdev_priv(ndev); 2277 2278 ndev->mtu = new_mtu; 2279 2280 if (netif_running(ndev)) { 2281 synchronize_irq(priv->emac_irq); 2282 ravb_emac_init(ndev); 2283 } 2284 2285 netdev_update_features(ndev); 2286 2287 return 0; 2288 } 2289 2290 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2291 { 2292 struct ravb_private *priv = netdev_priv(ndev); 2293 unsigned long flags; 2294 2295 spin_lock_irqsave(&priv->lock, flags); 2296 2297 /* Disable TX and RX */ 2298 ravb_rcv_snd_disable(ndev); 2299 2300 /* Modify RX Checksum setting */ 2301 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2302 2303 /* Enable TX and RX */ 2304 ravb_rcv_snd_enable(ndev); 2305 2306 spin_unlock_irqrestore(&priv->lock, flags); 2307 } 2308 2309 static int ravb_set_features_gbeth(struct net_device *ndev, 2310 netdev_features_t features) 2311 { 2312 /* Place holder */ 2313 return 0; 2314 } 2315 2316 static int ravb_set_features_rcar(struct net_device *ndev, 2317 netdev_features_t features) 2318 { 2319 netdev_features_t changed = ndev->features ^ features; 2320 2321 if (changed & NETIF_F_RXCSUM) 2322 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2323 2324 ndev->features = features; 2325 2326 return 0; 2327 } 2328 2329 static int ravb_set_features(struct net_device *ndev, 2330 netdev_features_t features) 2331 { 2332 struct ravb_private *priv = netdev_priv(ndev); 2333 const struct ravb_hw_info *info = priv->info; 2334 2335 return info->set_feature(ndev, features); 2336 } 2337 2338 static const struct net_device_ops ravb_netdev_ops = { 2339 .ndo_open = ravb_open, 2340 .ndo_stop = ravb_close, 2341 .ndo_start_xmit = ravb_start_xmit, 2342 .ndo_select_queue = ravb_select_queue, 2343 .ndo_get_stats = ravb_get_stats, 2344 .ndo_set_rx_mode = ravb_set_rx_mode, 2345 .ndo_tx_timeout = ravb_tx_timeout, 2346 .ndo_eth_ioctl = ravb_do_ioctl, 2347 .ndo_change_mtu = ravb_change_mtu, 2348 .ndo_validate_addr = eth_validate_addr, 2349 .ndo_set_mac_address = eth_mac_addr, 2350 .ndo_set_features = ravb_set_features, 2351 }; 2352 2353 /* MDIO bus init function */ 2354 static int ravb_mdio_init(struct ravb_private *priv) 2355 { 2356 struct platform_device *pdev = priv->pdev; 2357 struct device *dev = &pdev->dev; 2358 int error; 2359 2360 /* Bitbang init */ 2361 priv->mdiobb.ops = &bb_ops; 2362 2363 /* MII controller setting */ 2364 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2365 if (!priv->mii_bus) 2366 return -ENOMEM; 2367 2368 /* Hook up MII support for ethtool */ 2369 priv->mii_bus->name = "ravb_mii"; 2370 priv->mii_bus->parent = dev; 2371 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2372 pdev->name, pdev->id); 2373 2374 /* Register MDIO bus */ 2375 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2376 if (error) 2377 goto out_free_bus; 2378 2379 return 0; 2380 2381 out_free_bus: 2382 free_mdio_bitbang(priv->mii_bus); 2383 return error; 2384 } 2385 2386 /* MDIO bus release function */ 2387 static int ravb_mdio_release(struct ravb_private *priv) 2388 { 2389 /* Unregister mdio bus */ 2390 mdiobus_unregister(priv->mii_bus); 2391 2392 /* Free bitbang info */ 2393 free_mdio_bitbang(priv->mii_bus); 2394 2395 return 0; 2396 } 2397 2398 static const struct ravb_hw_info ravb_gen3_hw_info = { 2399 .rx_ring_free = ravb_rx_ring_free_rcar, 2400 .rx_ring_format = ravb_rx_ring_format_rcar, 2401 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2402 .receive = ravb_rx_rcar, 2403 .set_rate = ravb_set_rate_rcar, 2404 .set_feature = ravb_set_features_rcar, 2405 .dmac_init = ravb_dmac_init_rcar, 2406 .emac_init = ravb_emac_init_rcar, 2407 .gstrings_stats = ravb_gstrings_stats, 2408 .gstrings_size = sizeof(ravb_gstrings_stats), 2409 .net_hw_features = NETIF_F_RXCSUM, 2410 .net_features = NETIF_F_RXCSUM, 2411 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2412 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2413 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2414 .rx_max_buf_size = SZ_2K, 2415 .internal_delay = 1, 2416 .tx_counters = 1, 2417 .multi_irqs = 1, 2418 .ccc_gac = 1, 2419 .nc_queues = 1, 2420 .magic_pkt = 1, 2421 }; 2422 2423 static const struct ravb_hw_info ravb_gen2_hw_info = { 2424 .rx_ring_free = ravb_rx_ring_free_rcar, 2425 .rx_ring_format = ravb_rx_ring_format_rcar, 2426 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2427 .receive = ravb_rx_rcar, 2428 .set_rate = ravb_set_rate_rcar, 2429 .set_feature = ravb_set_features_rcar, 2430 .dmac_init = ravb_dmac_init_rcar, 2431 .emac_init = ravb_emac_init_rcar, 2432 .gstrings_stats = ravb_gstrings_stats, 2433 .gstrings_size = sizeof(ravb_gstrings_stats), 2434 .net_hw_features = NETIF_F_RXCSUM, 2435 .net_features = NETIF_F_RXCSUM, 2436 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2437 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2438 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2439 .rx_max_buf_size = SZ_2K, 2440 .aligned_tx = 1, 2441 .gptp = 1, 2442 .nc_queues = 1, 2443 .magic_pkt = 1, 2444 }; 2445 2446 static const struct ravb_hw_info gbeth_hw_info = { 2447 .rx_ring_free = ravb_rx_ring_free_gbeth, 2448 .rx_ring_format = ravb_rx_ring_format_gbeth, 2449 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2450 .receive = ravb_rx_gbeth, 2451 .set_rate = ravb_set_rate_gbeth, 2452 .set_feature = ravb_set_features_gbeth, 2453 .dmac_init = ravb_dmac_init_gbeth, 2454 .emac_init = ravb_emac_init_gbeth, 2455 .gstrings_stats = ravb_gstrings_stats_gbeth, 2456 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2457 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2458 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), 2459 .tccr_mask = TCCR_TSRQ0, 2460 .rx_max_buf_size = SZ_8K, 2461 .aligned_tx = 1, 2462 .tx_counters = 1, 2463 .carrier_counters = 1, 2464 .half_duplex = 1, 2465 }; 2466 2467 static const struct of_device_id ravb_match_table[] = { 2468 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2469 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2470 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2471 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2472 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2473 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2474 { } 2475 }; 2476 MODULE_DEVICE_TABLE(of, ravb_match_table); 2477 2478 static int ravb_set_gti(struct net_device *ndev) 2479 { 2480 struct ravb_private *priv = netdev_priv(ndev); 2481 struct device *dev = ndev->dev.parent; 2482 unsigned long rate; 2483 uint64_t inc; 2484 2485 rate = clk_get_rate(priv->clk); 2486 if (!rate) 2487 return -EINVAL; 2488 2489 inc = 1000000000ULL << 20; 2490 do_div(inc, rate); 2491 2492 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 2493 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 2494 inc, GTI_TIV_MIN, GTI_TIV_MAX); 2495 return -EINVAL; 2496 } 2497 2498 ravb_write(ndev, inc, GTI); 2499 2500 return 0; 2501 } 2502 2503 static void ravb_set_config_mode(struct net_device *ndev) 2504 { 2505 struct ravb_private *priv = netdev_priv(ndev); 2506 const struct ravb_hw_info *info = priv->info; 2507 2508 if (info->gptp) { 2509 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2510 /* Set CSEL value */ 2511 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 2512 } else if (info->ccc_gac) { 2513 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 2514 CCC_GAC | CCC_CSEL_HPB); 2515 } else { 2516 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2517 } 2518 } 2519 2520 /* Set tx and rx clock internal delay modes */ 2521 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2522 { 2523 struct ravb_private *priv = netdev_priv(ndev); 2524 bool explicit_delay = false; 2525 u32 delay; 2526 2527 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2528 /* Valid values are 0 and 1800, according to DT bindings */ 2529 priv->rxcidm = !!delay; 2530 explicit_delay = true; 2531 } 2532 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2533 /* Valid values are 0 and 2000, according to DT bindings */ 2534 priv->txcidm = !!delay; 2535 explicit_delay = true; 2536 } 2537 2538 if (explicit_delay) 2539 return; 2540 2541 /* Fall back to legacy rgmii-*id behavior */ 2542 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2543 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2544 priv->rxcidm = 1; 2545 priv->rgmii_override = 1; 2546 } 2547 2548 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2549 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2550 priv->txcidm = 1; 2551 priv->rgmii_override = 1; 2552 } 2553 } 2554 2555 static void ravb_set_delay_mode(struct net_device *ndev) 2556 { 2557 struct ravb_private *priv = netdev_priv(ndev); 2558 u32 set = 0; 2559 2560 if (priv->rxcidm) 2561 set |= APSR_RDM; 2562 if (priv->txcidm) 2563 set |= APSR_TDM; 2564 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2565 } 2566 2567 static int ravb_probe(struct platform_device *pdev) 2568 { 2569 struct device_node *np = pdev->dev.of_node; 2570 const struct ravb_hw_info *info; 2571 struct reset_control *rstc; 2572 struct ravb_private *priv; 2573 struct net_device *ndev; 2574 int error, irq, q; 2575 struct resource *res; 2576 int i; 2577 2578 if (!np) { 2579 dev_err(&pdev->dev, 2580 "this driver is required to be instantiated from device tree\n"); 2581 return -EINVAL; 2582 } 2583 2584 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2585 if (IS_ERR(rstc)) 2586 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2587 "failed to get cpg reset\n"); 2588 2589 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2590 NUM_TX_QUEUE, NUM_RX_QUEUE); 2591 if (!ndev) 2592 return -ENOMEM; 2593 2594 info = of_device_get_match_data(&pdev->dev); 2595 2596 ndev->features = info->net_features; 2597 ndev->hw_features = info->net_hw_features; 2598 2599 reset_control_deassert(rstc); 2600 pm_runtime_enable(&pdev->dev); 2601 pm_runtime_get_sync(&pdev->dev); 2602 2603 if (info->multi_irqs) 2604 irq = platform_get_irq_byname(pdev, "ch22"); 2605 else 2606 irq = platform_get_irq(pdev, 0); 2607 if (irq < 0) { 2608 error = irq; 2609 goto out_release; 2610 } 2611 ndev->irq = irq; 2612 2613 SET_NETDEV_DEV(ndev, &pdev->dev); 2614 2615 priv = netdev_priv(ndev); 2616 priv->info = info; 2617 priv->rstc = rstc; 2618 priv->ndev = ndev; 2619 priv->pdev = pdev; 2620 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2621 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2622 if (info->nc_queues) { 2623 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2624 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2625 } 2626 2627 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2628 if (IS_ERR(priv->addr)) { 2629 error = PTR_ERR(priv->addr); 2630 goto out_release; 2631 } 2632 2633 /* The Ether-specific entries in the device structure. */ 2634 ndev->base_addr = res->start; 2635 2636 spin_lock_init(&priv->lock); 2637 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2638 2639 error = of_get_phy_mode(np, &priv->phy_interface); 2640 if (error && error != -ENODEV) 2641 goto out_release; 2642 2643 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2644 priv->avb_link_active_low = 2645 of_property_read_bool(np, "renesas,ether-link-active-low"); 2646 2647 if (info->multi_irqs) { 2648 irq = platform_get_irq_byname(pdev, "ch24"); 2649 if (irq < 0) { 2650 error = irq; 2651 goto out_release; 2652 } 2653 priv->emac_irq = irq; 2654 for (i = 0; i < NUM_RX_QUEUE; i++) { 2655 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2656 if (irq < 0) { 2657 error = irq; 2658 goto out_release; 2659 } 2660 priv->rx_irqs[i] = irq; 2661 } 2662 for (i = 0; i < NUM_TX_QUEUE; i++) { 2663 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2664 if (irq < 0) { 2665 error = irq; 2666 goto out_release; 2667 } 2668 priv->tx_irqs[i] = irq; 2669 } 2670 } 2671 2672 priv->clk = devm_clk_get(&pdev->dev, NULL); 2673 if (IS_ERR(priv->clk)) { 2674 error = PTR_ERR(priv->clk); 2675 goto out_release; 2676 } 2677 2678 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2679 if (IS_ERR(priv->refclk)) { 2680 error = PTR_ERR(priv->refclk); 2681 goto out_release; 2682 } 2683 clk_prepare_enable(priv->refclk); 2684 2685 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2686 ndev->min_mtu = ETH_MIN_MTU; 2687 2688 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2689 * Use two descriptor to handle such situation. First descriptor to 2690 * handle aligned data buffer and second descriptor to handle the 2691 * overflow data because of alignment. 2692 */ 2693 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2694 2695 /* Set function */ 2696 ndev->netdev_ops = &ravb_netdev_ops; 2697 ndev->ethtool_ops = &ravb_ethtool_ops; 2698 2699 /* Set AVB config mode */ 2700 ravb_set_config_mode(ndev); 2701 2702 if (info->gptp || info->ccc_gac) { 2703 /* Set GTI value */ 2704 error = ravb_set_gti(ndev); 2705 if (error) 2706 goto out_disable_refclk; 2707 2708 /* Request GTI loading */ 2709 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2710 } 2711 2712 if (info->internal_delay) { 2713 ravb_parse_delay_mode(np, ndev); 2714 ravb_set_delay_mode(ndev); 2715 } 2716 2717 /* Allocate descriptor base address table */ 2718 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2719 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2720 &priv->desc_bat_dma, GFP_KERNEL); 2721 if (!priv->desc_bat) { 2722 dev_err(&pdev->dev, 2723 "Cannot allocate desc base address table (size %d bytes)\n", 2724 priv->desc_bat_size); 2725 error = -ENOMEM; 2726 goto out_disable_refclk; 2727 } 2728 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2729 priv->desc_bat[q].die_dt = DT_EOS; 2730 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2731 2732 /* Initialise HW timestamp list */ 2733 INIT_LIST_HEAD(&priv->ts_skb_list); 2734 2735 /* Initialise PTP Clock driver */ 2736 if (info->ccc_gac) 2737 ravb_ptp_init(ndev, pdev); 2738 2739 /* Debug message level */ 2740 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2741 2742 /* Read and set MAC address */ 2743 ravb_read_mac_address(np, ndev); 2744 if (!is_valid_ether_addr(ndev->dev_addr)) { 2745 dev_warn(&pdev->dev, 2746 "no valid MAC address supplied, using a random one\n"); 2747 eth_hw_addr_random(ndev); 2748 } 2749 2750 /* MDIO bus init */ 2751 error = ravb_mdio_init(priv); 2752 if (error) { 2753 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2754 goto out_dma_free; 2755 } 2756 2757 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2758 if (info->nc_queues) 2759 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2760 2761 /* Network device register */ 2762 error = register_netdev(ndev); 2763 if (error) 2764 goto out_napi_del; 2765 2766 device_set_wakeup_capable(&pdev->dev, 1); 2767 2768 /* Print device information */ 2769 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2770 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2771 2772 platform_set_drvdata(pdev, ndev); 2773 2774 return 0; 2775 2776 out_napi_del: 2777 if (info->nc_queues) 2778 netif_napi_del(&priv->napi[RAVB_NC]); 2779 2780 netif_napi_del(&priv->napi[RAVB_BE]); 2781 ravb_mdio_release(priv); 2782 out_dma_free: 2783 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2784 priv->desc_bat_dma); 2785 2786 /* Stop PTP Clock driver */ 2787 if (info->ccc_gac) 2788 ravb_ptp_stop(ndev); 2789 out_disable_refclk: 2790 clk_disable_unprepare(priv->refclk); 2791 out_release: 2792 free_netdev(ndev); 2793 2794 pm_runtime_put(&pdev->dev); 2795 pm_runtime_disable(&pdev->dev); 2796 reset_control_assert(rstc); 2797 return error; 2798 } 2799 2800 static int ravb_remove(struct platform_device *pdev) 2801 { 2802 struct net_device *ndev = platform_get_drvdata(pdev); 2803 struct ravb_private *priv = netdev_priv(ndev); 2804 const struct ravb_hw_info *info = priv->info; 2805 2806 /* Stop PTP Clock driver */ 2807 if (info->ccc_gac) 2808 ravb_ptp_stop(ndev); 2809 2810 clk_disable_unprepare(priv->refclk); 2811 2812 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2813 priv->desc_bat_dma); 2814 /* Set reset mode */ 2815 ravb_write(ndev, CCC_OPC_RESET, CCC); 2816 pm_runtime_put_sync(&pdev->dev); 2817 unregister_netdev(ndev); 2818 if (info->nc_queues) 2819 netif_napi_del(&priv->napi[RAVB_NC]); 2820 netif_napi_del(&priv->napi[RAVB_BE]); 2821 ravb_mdio_release(priv); 2822 pm_runtime_disable(&pdev->dev); 2823 reset_control_assert(priv->rstc); 2824 free_netdev(ndev); 2825 platform_set_drvdata(pdev, NULL); 2826 2827 return 0; 2828 } 2829 2830 static int ravb_wol_setup(struct net_device *ndev) 2831 { 2832 struct ravb_private *priv = netdev_priv(ndev); 2833 const struct ravb_hw_info *info = priv->info; 2834 2835 /* Disable interrupts by clearing the interrupt masks. */ 2836 ravb_write(ndev, 0, RIC0); 2837 ravb_write(ndev, 0, RIC2); 2838 ravb_write(ndev, 0, TIC); 2839 2840 /* Only allow ECI interrupts */ 2841 synchronize_irq(priv->emac_irq); 2842 if (info->nc_queues) 2843 napi_disable(&priv->napi[RAVB_NC]); 2844 napi_disable(&priv->napi[RAVB_BE]); 2845 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2846 2847 /* Enable MagicPacket */ 2848 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2849 2850 return enable_irq_wake(priv->emac_irq); 2851 } 2852 2853 static int ravb_wol_restore(struct net_device *ndev) 2854 { 2855 struct ravb_private *priv = netdev_priv(ndev); 2856 const struct ravb_hw_info *info = priv->info; 2857 int ret; 2858 2859 if (info->nc_queues) 2860 napi_enable(&priv->napi[RAVB_NC]); 2861 napi_enable(&priv->napi[RAVB_BE]); 2862 2863 /* Disable MagicPacket */ 2864 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2865 2866 ret = ravb_close(ndev); 2867 if (ret < 0) 2868 return ret; 2869 2870 return disable_irq_wake(priv->emac_irq); 2871 } 2872 2873 static int __maybe_unused ravb_suspend(struct device *dev) 2874 { 2875 struct net_device *ndev = dev_get_drvdata(dev); 2876 struct ravb_private *priv = netdev_priv(ndev); 2877 int ret; 2878 2879 if (!netif_running(ndev)) 2880 return 0; 2881 2882 netif_device_detach(ndev); 2883 2884 if (priv->wol_enabled) 2885 ret = ravb_wol_setup(ndev); 2886 else 2887 ret = ravb_close(ndev); 2888 2889 return ret; 2890 } 2891 2892 static int __maybe_unused ravb_resume(struct device *dev) 2893 { 2894 struct net_device *ndev = dev_get_drvdata(dev); 2895 struct ravb_private *priv = netdev_priv(ndev); 2896 const struct ravb_hw_info *info = priv->info; 2897 int ret = 0; 2898 2899 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2900 if (priv->wol_enabled) 2901 ravb_write(ndev, CCC_OPC_RESET, CCC); 2902 2903 /* All register have been reset to default values. 2904 * Restore all registers which where setup at probe time and 2905 * reopen device if it was running before system suspended. 2906 */ 2907 2908 /* Set AVB config mode */ 2909 ravb_set_config_mode(ndev); 2910 2911 if (info->gptp || info->ccc_gac) { 2912 /* Set GTI value */ 2913 ret = ravb_set_gti(ndev); 2914 if (ret) 2915 return ret; 2916 2917 /* Request GTI loading */ 2918 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2919 } 2920 2921 if (info->internal_delay) 2922 ravb_set_delay_mode(ndev); 2923 2924 /* Restore descriptor base address table */ 2925 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2926 2927 if (netif_running(ndev)) { 2928 if (priv->wol_enabled) { 2929 ret = ravb_wol_restore(ndev); 2930 if (ret) 2931 return ret; 2932 } 2933 ret = ravb_open(ndev); 2934 if (ret < 0) 2935 return ret; 2936 netif_device_attach(ndev); 2937 } 2938 2939 return ret; 2940 } 2941 2942 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2943 { 2944 /* Runtime PM callback shared between ->runtime_suspend() 2945 * and ->runtime_resume(). Simply returns success. 2946 * 2947 * This driver re-initializes all registers after 2948 * pm_runtime_get_sync() anyway so there is no need 2949 * to save and restore registers here. 2950 */ 2951 return 0; 2952 } 2953 2954 static const struct dev_pm_ops ravb_dev_pm_ops = { 2955 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2956 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2957 }; 2958 2959 static struct platform_driver ravb_driver = { 2960 .probe = ravb_probe, 2961 .remove = ravb_remove, 2962 .driver = { 2963 .name = "ravb", 2964 .pm = &ravb_dev_pm_ops, 2965 .of_match_table = ravb_match_table, 2966 }, 2967 }; 2968 2969 module_platform_driver(ravb_driver); 2970 2971 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2972 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2973 MODULE_LICENSE("GPL v2"); 2974