1 /* Renesas Ethernet AVB device driver
2  *
3  * Copyright (C) 2014-2015 Renesas Electronics Corporation
4  * Copyright (C) 2015 Renesas Solutions Corp.
5  * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
6  *
7  * Based on the SuperH Ethernet driver
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms and conditions of the GNU General Public License version 2,
11  * as published by the Free Software Foundation.
12  */
13 
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34 #include <linux/sys_soc.h>
35 
36 #include <asm/div64.h>
37 
38 #include "ravb.h"
39 
40 #define RAVB_DEF_MSG_ENABLE \
41 		(NETIF_MSG_LINK	  | \
42 		 NETIF_MSG_TIMER  | \
43 		 NETIF_MSG_RX_ERR | \
44 		 NETIF_MSG_TX_ERR)
45 
46 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
47 	"ch0", /* RAVB_BE */
48 	"ch1", /* RAVB_NC */
49 };
50 
51 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
52 	"ch18", /* RAVB_BE */
53 	"ch19", /* RAVB_NC */
54 };
55 
56 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
57 		 u32 set)
58 {
59 	ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
60 }
61 
62 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
63 {
64 	int i;
65 
66 	for (i = 0; i < 10000; i++) {
67 		if ((ravb_read(ndev, reg) & mask) == value)
68 			return 0;
69 		udelay(10);
70 	}
71 	return -ETIMEDOUT;
72 }
73 
74 static int ravb_config(struct net_device *ndev)
75 {
76 	int error;
77 
78 	/* Set config mode */
79 	ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
80 	/* Check if the operating mode is changed to the config mode */
81 	error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
82 	if (error)
83 		netdev_err(ndev, "failed to switch device to config mode\n");
84 
85 	return error;
86 }
87 
88 static void ravb_set_duplex(struct net_device *ndev)
89 {
90 	struct ravb_private *priv = netdev_priv(ndev);
91 
92 	ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
93 }
94 
95 static void ravb_set_rate(struct net_device *ndev)
96 {
97 	struct ravb_private *priv = netdev_priv(ndev);
98 
99 	switch (priv->speed) {
100 	case 100:		/* 100BASE */
101 		ravb_write(ndev, GECMR_SPEED_100, GECMR);
102 		break;
103 	case 1000:		/* 1000BASE */
104 		ravb_write(ndev, GECMR_SPEED_1000, GECMR);
105 		break;
106 	}
107 }
108 
109 static void ravb_set_buffer_align(struct sk_buff *skb)
110 {
111 	u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
112 
113 	if (reserve)
114 		skb_reserve(skb, RAVB_ALIGN - reserve);
115 }
116 
117 /* Get MAC address from the MAC address registers
118  *
119  * Ethernet AVB device doesn't have ROM for MAC address.
120  * This function gets the MAC address that was used by a bootloader.
121  */
122 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
123 {
124 	if (mac) {
125 		ether_addr_copy(ndev->dev_addr, mac);
126 	} else {
127 		u32 mahr = ravb_read(ndev, MAHR);
128 		u32 malr = ravb_read(ndev, MALR);
129 
130 		ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
131 		ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
132 		ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
133 		ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
134 		ndev->dev_addr[4] = (malr >>  8) & 0xFF;
135 		ndev->dev_addr[5] = (malr >>  0) & 0xFF;
136 	}
137 }
138 
139 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
140 {
141 	struct ravb_private *priv = container_of(ctrl, struct ravb_private,
142 						 mdiobb);
143 
144 	ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
145 }
146 
147 /* MDC pin control */
148 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
149 {
150 	ravb_mdio_ctrl(ctrl, PIR_MDC, level);
151 }
152 
153 /* Data I/O pin control */
154 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
155 {
156 	ravb_mdio_ctrl(ctrl, PIR_MMD, output);
157 }
158 
159 /* Set data bit */
160 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
161 {
162 	ravb_mdio_ctrl(ctrl, PIR_MDO, value);
163 }
164 
165 /* Get data bit */
166 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
167 {
168 	struct ravb_private *priv = container_of(ctrl, struct ravb_private,
169 						 mdiobb);
170 
171 	return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
172 }
173 
174 /* MDIO bus control struct */
175 static struct mdiobb_ops bb_ops = {
176 	.owner = THIS_MODULE,
177 	.set_mdc = ravb_set_mdc,
178 	.set_mdio_dir = ravb_set_mdio_dir,
179 	.set_mdio_data = ravb_set_mdio_data,
180 	.get_mdio_data = ravb_get_mdio_data,
181 };
182 
183 /* Free TX skb function for AVB-IP */
184 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
185 {
186 	struct ravb_private *priv = netdev_priv(ndev);
187 	struct net_device_stats *stats = &priv->stats[q];
188 	struct ravb_tx_desc *desc;
189 	int free_num = 0;
190 	int entry;
191 	u32 size;
192 
193 	for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
194 		bool txed;
195 
196 		entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
197 					     NUM_TX_DESC);
198 		desc = &priv->tx_ring[q][entry];
199 		txed = desc->die_dt == DT_FEMPTY;
200 		if (free_txed_only && !txed)
201 			break;
202 		/* Descriptor type must be checked before all other reads */
203 		dma_rmb();
204 		size = le16_to_cpu(desc->ds_tagl) & TX_DS;
205 		/* Free the original skb. */
206 		if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
207 			dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
208 					 size, DMA_TO_DEVICE);
209 			/* Last packet descriptor? */
210 			if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
211 				entry /= NUM_TX_DESC;
212 				dev_kfree_skb_any(priv->tx_skb[q][entry]);
213 				priv->tx_skb[q][entry] = NULL;
214 				if (txed)
215 					stats->tx_packets++;
216 			}
217 			free_num++;
218 		}
219 		if (txed)
220 			stats->tx_bytes += size;
221 		desc->die_dt = DT_EEMPTY;
222 	}
223 	return free_num;
224 }
225 
226 /* Free skb's and DMA buffers for Ethernet AVB */
227 static void ravb_ring_free(struct net_device *ndev, int q)
228 {
229 	struct ravb_private *priv = netdev_priv(ndev);
230 	int ring_size;
231 	int i;
232 
233 	if (priv->rx_ring[q]) {
234 		for (i = 0; i < priv->num_rx_ring[q]; i++) {
235 			struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
236 
237 			if (!dma_mapping_error(ndev->dev.parent,
238 					       le32_to_cpu(desc->dptr)))
239 				dma_unmap_single(ndev->dev.parent,
240 						 le32_to_cpu(desc->dptr),
241 						 PKT_BUF_SZ,
242 						 DMA_FROM_DEVICE);
243 		}
244 		ring_size = sizeof(struct ravb_ex_rx_desc) *
245 			    (priv->num_rx_ring[q] + 1);
246 		dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
247 				  priv->rx_desc_dma[q]);
248 		priv->rx_ring[q] = NULL;
249 	}
250 
251 	if (priv->tx_ring[q]) {
252 		ravb_tx_free(ndev, q, false);
253 
254 		ring_size = sizeof(struct ravb_tx_desc) *
255 			    (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
256 		dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
257 				  priv->tx_desc_dma[q]);
258 		priv->tx_ring[q] = NULL;
259 	}
260 
261 	/* Free RX skb ringbuffer */
262 	if (priv->rx_skb[q]) {
263 		for (i = 0; i < priv->num_rx_ring[q]; i++)
264 			dev_kfree_skb(priv->rx_skb[q][i]);
265 	}
266 	kfree(priv->rx_skb[q]);
267 	priv->rx_skb[q] = NULL;
268 
269 	/* Free aligned TX buffers */
270 	kfree(priv->tx_align[q]);
271 	priv->tx_align[q] = NULL;
272 
273 	/* Free TX skb ringbuffer.
274 	 * SKBs are freed by ravb_tx_free() call above.
275 	 */
276 	kfree(priv->tx_skb[q]);
277 	priv->tx_skb[q] = NULL;
278 }
279 
280 /* Format skb and descriptor buffer for Ethernet AVB */
281 static void ravb_ring_format(struct net_device *ndev, int q)
282 {
283 	struct ravb_private *priv = netdev_priv(ndev);
284 	struct ravb_ex_rx_desc *rx_desc;
285 	struct ravb_tx_desc *tx_desc;
286 	struct ravb_desc *desc;
287 	int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
288 	int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
289 			   NUM_TX_DESC;
290 	dma_addr_t dma_addr;
291 	int i;
292 
293 	priv->cur_rx[q] = 0;
294 	priv->cur_tx[q] = 0;
295 	priv->dirty_rx[q] = 0;
296 	priv->dirty_tx[q] = 0;
297 
298 	memset(priv->rx_ring[q], 0, rx_ring_size);
299 	/* Build RX ring buffer */
300 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
301 		/* RX descriptor */
302 		rx_desc = &priv->rx_ring[q][i];
303 		rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
304 		dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
305 					  PKT_BUF_SZ,
306 					  DMA_FROM_DEVICE);
307 		/* We just set the data size to 0 for a failed mapping which
308 		 * should prevent DMA from happening...
309 		 */
310 		if (dma_mapping_error(ndev->dev.parent, dma_addr))
311 			rx_desc->ds_cc = cpu_to_le16(0);
312 		rx_desc->dptr = cpu_to_le32(dma_addr);
313 		rx_desc->die_dt = DT_FEMPTY;
314 	}
315 	rx_desc = &priv->rx_ring[q][i];
316 	rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
317 	rx_desc->die_dt = DT_LINKFIX; /* type */
318 
319 	memset(priv->tx_ring[q], 0, tx_ring_size);
320 	/* Build TX ring buffer */
321 	for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
322 	     i++, tx_desc++) {
323 		tx_desc->die_dt = DT_EEMPTY;
324 		tx_desc++;
325 		tx_desc->die_dt = DT_EEMPTY;
326 	}
327 	tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
328 	tx_desc->die_dt = DT_LINKFIX; /* type */
329 
330 	/* RX descriptor base address for best effort */
331 	desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
332 	desc->die_dt = DT_LINKFIX; /* type */
333 	desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
334 
335 	/* TX descriptor base address for best effort */
336 	desc = &priv->desc_bat[q];
337 	desc->die_dt = DT_LINKFIX; /* type */
338 	desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
339 }
340 
341 /* Init skb and descriptor buffer for Ethernet AVB */
342 static int ravb_ring_init(struct net_device *ndev, int q)
343 {
344 	struct ravb_private *priv = netdev_priv(ndev);
345 	struct sk_buff *skb;
346 	int ring_size;
347 	int i;
348 
349 	/* Allocate RX and TX skb rings */
350 	priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
351 				  sizeof(*priv->rx_skb[q]), GFP_KERNEL);
352 	priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
353 				  sizeof(*priv->tx_skb[q]), GFP_KERNEL);
354 	if (!priv->rx_skb[q] || !priv->tx_skb[q])
355 		goto error;
356 
357 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
358 		skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
359 		if (!skb)
360 			goto error;
361 		ravb_set_buffer_align(skb);
362 		priv->rx_skb[q][i] = skb;
363 	}
364 
365 	/* Allocate rings for the aligned buffers */
366 	priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
367 				    DPTR_ALIGN - 1, GFP_KERNEL);
368 	if (!priv->tx_align[q])
369 		goto error;
370 
371 	/* Allocate all RX descriptors. */
372 	ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
373 	priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
374 					      &priv->rx_desc_dma[q],
375 					      GFP_KERNEL);
376 	if (!priv->rx_ring[q])
377 		goto error;
378 
379 	priv->dirty_rx[q] = 0;
380 
381 	/* Allocate all TX descriptors. */
382 	ring_size = sizeof(struct ravb_tx_desc) *
383 		    (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
384 	priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
385 					      &priv->tx_desc_dma[q],
386 					      GFP_KERNEL);
387 	if (!priv->tx_ring[q])
388 		goto error;
389 
390 	return 0;
391 
392 error:
393 	ravb_ring_free(ndev, q);
394 
395 	return -ENOMEM;
396 }
397 
398 /* E-MAC init function */
399 static void ravb_emac_init(struct net_device *ndev)
400 {
401 	struct ravb_private *priv = netdev_priv(ndev);
402 
403 	/* Receive frame limit set register */
404 	ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
405 
406 	/* PAUSE prohibition */
407 	ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
408 		   ECMR_TE | ECMR_RE, ECMR);
409 
410 	ravb_set_rate(ndev);
411 
412 	/* Set MAC address */
413 	ravb_write(ndev,
414 		   (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
415 		   (ndev->dev_addr[2] << 8)  | (ndev->dev_addr[3]), MAHR);
416 	ravb_write(ndev,
417 		   (ndev->dev_addr[4] << 8)  | (ndev->dev_addr[5]), MALR);
418 
419 	/* E-MAC status register clear */
420 	ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
421 
422 	/* E-MAC interrupt enable register */
423 	ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
424 }
425 
426 /* Device init function for Ethernet AVB */
427 static int ravb_dmac_init(struct net_device *ndev)
428 {
429 	struct ravb_private *priv = netdev_priv(ndev);
430 	int error;
431 
432 	/* Set CONFIG mode */
433 	error = ravb_config(ndev);
434 	if (error)
435 		return error;
436 
437 	error = ravb_ring_init(ndev, RAVB_BE);
438 	if (error)
439 		return error;
440 	error = ravb_ring_init(ndev, RAVB_NC);
441 	if (error) {
442 		ravb_ring_free(ndev, RAVB_BE);
443 		return error;
444 	}
445 
446 	/* Descriptor format */
447 	ravb_ring_format(ndev, RAVB_BE);
448 	ravb_ring_format(ndev, RAVB_NC);
449 
450 #if defined(__LITTLE_ENDIAN)
451 	ravb_modify(ndev, CCC, CCC_BOC, 0);
452 #else
453 	ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
454 #endif
455 
456 	/* Set AVB RX */
457 	ravb_write(ndev,
458 		   RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
459 
460 	/* Set FIFO size */
461 	ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
462 
463 	/* Timestamp enable */
464 	ravb_write(ndev, TCCR_TFEN, TCCR);
465 
466 	/* Interrupt init: */
467 	if (priv->chip_id == RCAR_GEN3) {
468 		/* Clear DIL.DPLx */
469 		ravb_write(ndev, 0, DIL);
470 		/* Set queue specific interrupt */
471 		ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
472 	}
473 	/* Frame receive */
474 	ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
475 	/* Disable FIFO full warning */
476 	ravb_write(ndev, 0, RIC1);
477 	/* Receive FIFO full error, descriptor empty */
478 	ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
479 	/* Frame transmitted, timestamp FIFO updated */
480 	ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
481 
482 	/* Setting the control will start the AVB-DMAC process. */
483 	ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
484 
485 	return 0;
486 }
487 
488 static void ravb_get_tx_tstamp(struct net_device *ndev)
489 {
490 	struct ravb_private *priv = netdev_priv(ndev);
491 	struct ravb_tstamp_skb *ts_skb, *ts_skb2;
492 	struct skb_shared_hwtstamps shhwtstamps;
493 	struct sk_buff *skb;
494 	struct timespec64 ts;
495 	u16 tag, tfa_tag;
496 	int count;
497 	u32 tfa2;
498 
499 	count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
500 	while (count--) {
501 		tfa2 = ravb_read(ndev, TFA2);
502 		tfa_tag = (tfa2 & TFA2_TST) >> 16;
503 		ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
504 		ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
505 			    ravb_read(ndev, TFA1);
506 		memset(&shhwtstamps, 0, sizeof(shhwtstamps));
507 		shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
508 		list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
509 					 list) {
510 			skb = ts_skb->skb;
511 			tag = ts_skb->tag;
512 			list_del(&ts_skb->list);
513 			kfree(ts_skb);
514 			if (tag == tfa_tag) {
515 				skb_tstamp_tx(skb, &shhwtstamps);
516 				break;
517 			}
518 		}
519 		ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
520 	}
521 }
522 
523 /* Packet receive function for Ethernet AVB */
524 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
525 {
526 	struct ravb_private *priv = netdev_priv(ndev);
527 	int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
528 	int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
529 			priv->cur_rx[q];
530 	struct net_device_stats *stats = &priv->stats[q];
531 	struct ravb_ex_rx_desc *desc;
532 	struct sk_buff *skb;
533 	dma_addr_t dma_addr;
534 	struct timespec64 ts;
535 	u8  desc_status;
536 	u16 pkt_len;
537 	int limit;
538 
539 	boguscnt = min(boguscnt, *quota);
540 	limit = boguscnt;
541 	desc = &priv->rx_ring[q][entry];
542 	while (desc->die_dt != DT_FEMPTY) {
543 		/* Descriptor type must be checked before all other reads */
544 		dma_rmb();
545 		desc_status = desc->msc;
546 		pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
547 
548 		if (--boguscnt < 0)
549 			break;
550 
551 		/* We use 0-byte descriptors to mark the DMA mapping errors */
552 		if (!pkt_len)
553 			continue;
554 
555 		if (desc_status & MSC_MC)
556 			stats->multicast++;
557 
558 		if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
559 				   MSC_CEEF)) {
560 			stats->rx_errors++;
561 			if (desc_status & MSC_CRC)
562 				stats->rx_crc_errors++;
563 			if (desc_status & MSC_RFE)
564 				stats->rx_frame_errors++;
565 			if (desc_status & (MSC_RTLF | MSC_RTSF))
566 				stats->rx_length_errors++;
567 			if (desc_status & MSC_CEEF)
568 				stats->rx_missed_errors++;
569 		} else {
570 			u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
571 
572 			skb = priv->rx_skb[q][entry];
573 			priv->rx_skb[q][entry] = NULL;
574 			dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
575 					 PKT_BUF_SZ,
576 					 DMA_FROM_DEVICE);
577 			get_ts &= (q == RAVB_NC) ?
578 					RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
579 					~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
580 			if (get_ts) {
581 				struct skb_shared_hwtstamps *shhwtstamps;
582 
583 				shhwtstamps = skb_hwtstamps(skb);
584 				memset(shhwtstamps, 0, sizeof(*shhwtstamps));
585 				ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
586 					     32) | le32_to_cpu(desc->ts_sl);
587 				ts.tv_nsec = le32_to_cpu(desc->ts_n);
588 				shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
589 			}
590 			skb_put(skb, pkt_len);
591 			skb->protocol = eth_type_trans(skb, ndev);
592 			napi_gro_receive(&priv->napi[q], skb);
593 			stats->rx_packets++;
594 			stats->rx_bytes += pkt_len;
595 		}
596 
597 		entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
598 		desc = &priv->rx_ring[q][entry];
599 	}
600 
601 	/* Refill the RX ring buffers. */
602 	for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
603 		entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
604 		desc = &priv->rx_ring[q][entry];
605 		desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
606 
607 		if (!priv->rx_skb[q][entry]) {
608 			skb = netdev_alloc_skb(ndev,
609 					       PKT_BUF_SZ + RAVB_ALIGN - 1);
610 			if (!skb)
611 				break;	/* Better luck next round. */
612 			ravb_set_buffer_align(skb);
613 			dma_addr = dma_map_single(ndev->dev.parent, skb->data,
614 						  le16_to_cpu(desc->ds_cc),
615 						  DMA_FROM_DEVICE);
616 			skb_checksum_none_assert(skb);
617 			/* We just set the data size to 0 for a failed mapping
618 			 * which should prevent DMA  from happening...
619 			 */
620 			if (dma_mapping_error(ndev->dev.parent, dma_addr))
621 				desc->ds_cc = cpu_to_le16(0);
622 			desc->dptr = cpu_to_le32(dma_addr);
623 			priv->rx_skb[q][entry] = skb;
624 		}
625 		/* Descriptor type must be set after all the above writes */
626 		dma_wmb();
627 		desc->die_dt = DT_FEMPTY;
628 	}
629 
630 	*quota -= limit - (++boguscnt);
631 
632 	return boguscnt <= 0;
633 }
634 
635 static void ravb_rcv_snd_disable(struct net_device *ndev)
636 {
637 	/* Disable TX and RX */
638 	ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
639 }
640 
641 static void ravb_rcv_snd_enable(struct net_device *ndev)
642 {
643 	/* Enable TX and RX */
644 	ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
645 }
646 
647 /* function for waiting dma process finished */
648 static int ravb_stop_dma(struct net_device *ndev)
649 {
650 	int error;
651 
652 	/* Wait for stopping the hardware TX process */
653 	error = ravb_wait(ndev, TCCR,
654 			  TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
655 	if (error)
656 		return error;
657 
658 	error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
659 			  0);
660 	if (error)
661 		return error;
662 
663 	/* Stop the E-MAC's RX/TX processes. */
664 	ravb_rcv_snd_disable(ndev);
665 
666 	/* Wait for stopping the RX DMA process */
667 	error = ravb_wait(ndev, CSR, CSR_RPO, 0);
668 	if (error)
669 		return error;
670 
671 	/* Stop AVB-DMAC process */
672 	return ravb_config(ndev);
673 }
674 
675 /* E-MAC interrupt handler */
676 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
677 {
678 	struct ravb_private *priv = netdev_priv(ndev);
679 	u32 ecsr, psr;
680 
681 	ecsr = ravb_read(ndev, ECSR);
682 	ravb_write(ndev, ecsr, ECSR);	/* clear interrupt */
683 	if (ecsr & ECSR_ICD)
684 		ndev->stats.tx_carrier_errors++;
685 	if (ecsr & ECSR_LCHNG) {
686 		/* Link changed */
687 		if (priv->no_avb_link)
688 			return;
689 		psr = ravb_read(ndev, PSR);
690 		if (priv->avb_link_active_low)
691 			psr ^= PSR_LMON;
692 		if (!(psr & PSR_LMON)) {
693 			/* DIsable RX and TX */
694 			ravb_rcv_snd_disable(ndev);
695 		} else {
696 			/* Enable RX and TX */
697 			ravb_rcv_snd_enable(ndev);
698 		}
699 	}
700 }
701 
702 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
703 {
704 	struct net_device *ndev = dev_id;
705 	struct ravb_private *priv = netdev_priv(ndev);
706 
707 	spin_lock(&priv->lock);
708 	ravb_emac_interrupt_unlocked(ndev);
709 	mmiowb();
710 	spin_unlock(&priv->lock);
711 	return IRQ_HANDLED;
712 }
713 
714 /* Error interrupt handler */
715 static void ravb_error_interrupt(struct net_device *ndev)
716 {
717 	struct ravb_private *priv = netdev_priv(ndev);
718 	u32 eis, ris2;
719 
720 	eis = ravb_read(ndev, EIS);
721 	ravb_write(ndev, ~EIS_QFS, EIS);
722 	if (eis & EIS_QFS) {
723 		ris2 = ravb_read(ndev, RIS2);
724 		ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
725 
726 		/* Receive Descriptor Empty int */
727 		if (ris2 & RIS2_QFF0)
728 			priv->stats[RAVB_BE].rx_over_errors++;
729 
730 		    /* Receive Descriptor Empty int */
731 		if (ris2 & RIS2_QFF1)
732 			priv->stats[RAVB_NC].rx_over_errors++;
733 
734 		/* Receive FIFO Overflow int */
735 		if (ris2 & RIS2_RFFF)
736 			priv->rx_fifo_errors++;
737 	}
738 }
739 
740 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
741 {
742 	struct ravb_private *priv = netdev_priv(ndev);
743 	u32 ris0 = ravb_read(ndev, RIS0);
744 	u32 ric0 = ravb_read(ndev, RIC0);
745 	u32 tis  = ravb_read(ndev, TIS);
746 	u32 tic  = ravb_read(ndev, TIC);
747 
748 	if (((ris0 & ric0) & BIT(q)) || ((tis  & tic)  & BIT(q))) {
749 		if (napi_schedule_prep(&priv->napi[q])) {
750 			/* Mask RX and TX interrupts */
751 			if (priv->chip_id == RCAR_GEN2) {
752 				ravb_write(ndev, ric0 & ~BIT(q), RIC0);
753 				ravb_write(ndev, tic & ~BIT(q), TIC);
754 			} else {
755 				ravb_write(ndev, BIT(q), RID0);
756 				ravb_write(ndev, BIT(q), TID);
757 			}
758 			__napi_schedule(&priv->napi[q]);
759 		} else {
760 			netdev_warn(ndev,
761 				    "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
762 				    ris0, ric0);
763 			netdev_warn(ndev,
764 				    "                    tx status 0x%08x, tx mask 0x%08x.\n",
765 				    tis, tic);
766 		}
767 		return true;
768 	}
769 	return false;
770 }
771 
772 static bool ravb_timestamp_interrupt(struct net_device *ndev)
773 {
774 	u32 tis = ravb_read(ndev, TIS);
775 
776 	if (tis & TIS_TFUF) {
777 		ravb_write(ndev, ~TIS_TFUF, TIS);
778 		ravb_get_tx_tstamp(ndev);
779 		return true;
780 	}
781 	return false;
782 }
783 
784 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
785 {
786 	struct net_device *ndev = dev_id;
787 	struct ravb_private *priv = netdev_priv(ndev);
788 	irqreturn_t result = IRQ_NONE;
789 	u32 iss;
790 
791 	spin_lock(&priv->lock);
792 	/* Get interrupt status */
793 	iss = ravb_read(ndev, ISS);
794 
795 	/* Received and transmitted interrupts */
796 	if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
797 		int q;
798 
799 		/* Timestamp updated */
800 		if (ravb_timestamp_interrupt(ndev))
801 			result = IRQ_HANDLED;
802 
803 		/* Network control and best effort queue RX/TX */
804 		for (q = RAVB_NC; q >= RAVB_BE; q--) {
805 			if (ravb_queue_interrupt(ndev, q))
806 				result = IRQ_HANDLED;
807 		}
808 	}
809 
810 	/* E-MAC status summary */
811 	if (iss & ISS_MS) {
812 		ravb_emac_interrupt_unlocked(ndev);
813 		result = IRQ_HANDLED;
814 	}
815 
816 	/* Error status summary */
817 	if (iss & ISS_ES) {
818 		ravb_error_interrupt(ndev);
819 		result = IRQ_HANDLED;
820 	}
821 
822 	/* gPTP interrupt status summary */
823 	if (iss & ISS_CGIS) {
824 		ravb_ptp_interrupt(ndev);
825 		result = IRQ_HANDLED;
826 	}
827 
828 	mmiowb();
829 	spin_unlock(&priv->lock);
830 	return result;
831 }
832 
833 /* Timestamp/Error/gPTP interrupt handler */
834 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
835 {
836 	struct net_device *ndev = dev_id;
837 	struct ravb_private *priv = netdev_priv(ndev);
838 	irqreturn_t result = IRQ_NONE;
839 	u32 iss;
840 
841 	spin_lock(&priv->lock);
842 	/* Get interrupt status */
843 	iss = ravb_read(ndev, ISS);
844 
845 	/* Timestamp updated */
846 	if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
847 		result = IRQ_HANDLED;
848 
849 	/* Error status summary */
850 	if (iss & ISS_ES) {
851 		ravb_error_interrupt(ndev);
852 		result = IRQ_HANDLED;
853 	}
854 
855 	/* gPTP interrupt status summary */
856 	if (iss & ISS_CGIS) {
857 		ravb_ptp_interrupt(ndev);
858 		result = IRQ_HANDLED;
859 	}
860 
861 	mmiowb();
862 	spin_unlock(&priv->lock);
863 	return result;
864 }
865 
866 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
867 {
868 	struct net_device *ndev = dev_id;
869 	struct ravb_private *priv = netdev_priv(ndev);
870 	irqreturn_t result = IRQ_NONE;
871 
872 	spin_lock(&priv->lock);
873 
874 	/* Network control/Best effort queue RX/TX */
875 	if (ravb_queue_interrupt(ndev, q))
876 		result = IRQ_HANDLED;
877 
878 	mmiowb();
879 	spin_unlock(&priv->lock);
880 	return result;
881 }
882 
883 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
884 {
885 	return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
886 }
887 
888 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
889 {
890 	return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
891 }
892 
893 static int ravb_poll(struct napi_struct *napi, int budget)
894 {
895 	struct net_device *ndev = napi->dev;
896 	struct ravb_private *priv = netdev_priv(ndev);
897 	unsigned long flags;
898 	int q = napi - priv->napi;
899 	int mask = BIT(q);
900 	int quota = budget;
901 	u32 ris0, tis;
902 
903 	for (;;) {
904 		tis = ravb_read(ndev, TIS);
905 		ris0 = ravb_read(ndev, RIS0);
906 		if (!((ris0 & mask) || (tis & mask)))
907 			break;
908 
909 		/* Processing RX Descriptor Ring */
910 		if (ris0 & mask) {
911 			/* Clear RX interrupt */
912 			ravb_write(ndev, ~mask, RIS0);
913 			if (ravb_rx(ndev, &quota, q))
914 				goto out;
915 		}
916 		/* Processing TX Descriptor Ring */
917 		if (tis & mask) {
918 			spin_lock_irqsave(&priv->lock, flags);
919 			/* Clear TX interrupt */
920 			ravb_write(ndev, ~mask, TIS);
921 			ravb_tx_free(ndev, q, true);
922 			netif_wake_subqueue(ndev, q);
923 			mmiowb();
924 			spin_unlock_irqrestore(&priv->lock, flags);
925 		}
926 	}
927 
928 	napi_complete(napi);
929 
930 	/* Re-enable RX/TX interrupts */
931 	spin_lock_irqsave(&priv->lock, flags);
932 	if (priv->chip_id == RCAR_GEN2) {
933 		ravb_modify(ndev, RIC0, mask, mask);
934 		ravb_modify(ndev, TIC,  mask, mask);
935 	} else {
936 		ravb_write(ndev, mask, RIE0);
937 		ravb_write(ndev, mask, TIE);
938 	}
939 	mmiowb();
940 	spin_unlock_irqrestore(&priv->lock, flags);
941 
942 	/* Receive error message handling */
943 	priv->rx_over_errors =  priv->stats[RAVB_BE].rx_over_errors;
944 	priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
945 	if (priv->rx_over_errors != ndev->stats.rx_over_errors)
946 		ndev->stats.rx_over_errors = priv->rx_over_errors;
947 	if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
948 		ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
949 out:
950 	return budget - quota;
951 }
952 
953 /* PHY state control function */
954 static void ravb_adjust_link(struct net_device *ndev)
955 {
956 	struct ravb_private *priv = netdev_priv(ndev);
957 	struct phy_device *phydev = ndev->phydev;
958 	bool new_state = false;
959 
960 	if (phydev->link) {
961 		if (phydev->duplex != priv->duplex) {
962 			new_state = true;
963 			priv->duplex = phydev->duplex;
964 			ravb_set_duplex(ndev);
965 		}
966 
967 		if (phydev->speed != priv->speed) {
968 			new_state = true;
969 			priv->speed = phydev->speed;
970 			ravb_set_rate(ndev);
971 		}
972 		if (!priv->link) {
973 			ravb_modify(ndev, ECMR, ECMR_TXF, 0);
974 			new_state = true;
975 			priv->link = phydev->link;
976 			if (priv->no_avb_link)
977 				ravb_rcv_snd_enable(ndev);
978 		}
979 	} else if (priv->link) {
980 		new_state = true;
981 		priv->link = 0;
982 		priv->speed = 0;
983 		priv->duplex = -1;
984 		if (priv->no_avb_link)
985 			ravb_rcv_snd_disable(ndev);
986 	}
987 
988 	if (new_state && netif_msg_link(priv))
989 		phy_print_status(phydev);
990 }
991 
992 static const struct soc_device_attribute r8a7795es10[] = {
993 	{ .soc_id = "r8a7795", .revision = "ES1.0", },
994 	{ /* sentinel */ }
995 };
996 
997 /* PHY init function */
998 static int ravb_phy_init(struct net_device *ndev)
999 {
1000 	struct device_node *np = ndev->dev.parent->of_node;
1001 	struct ravb_private *priv = netdev_priv(ndev);
1002 	struct phy_device *phydev;
1003 	struct device_node *pn;
1004 	int err;
1005 
1006 	priv->link = 0;
1007 	priv->speed = 0;
1008 	priv->duplex = -1;
1009 
1010 	/* Try connecting to PHY */
1011 	pn = of_parse_phandle(np, "phy-handle", 0);
1012 	if (!pn) {
1013 		/* In the case of a fixed PHY, the DT node associated
1014 		 * to the PHY is the Ethernet MAC DT node.
1015 		 */
1016 		if (of_phy_is_fixed_link(np)) {
1017 			err = of_phy_register_fixed_link(np);
1018 			if (err)
1019 				return err;
1020 		}
1021 		pn = of_node_get(np);
1022 	}
1023 	phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1024 				priv->phy_interface);
1025 	of_node_put(pn);
1026 	if (!phydev) {
1027 		netdev_err(ndev, "failed to connect PHY\n");
1028 		err = -ENOENT;
1029 		goto err_deregister_fixed_link;
1030 	}
1031 
1032 	/* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1033 	 * at this time.
1034 	 */
1035 	if (soc_device_match(r8a7795es10)) {
1036 		err = phy_set_max_speed(phydev, SPEED_100);
1037 		if (err) {
1038 			netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1039 			goto err_phy_disconnect;
1040 		}
1041 
1042 		netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1043 	}
1044 
1045 	/* 10BASE is not supported */
1046 	phydev->supported &= ~PHY_10BT_FEATURES;
1047 
1048 	phy_attached_info(phydev);
1049 
1050 	return 0;
1051 
1052 err_phy_disconnect:
1053 	phy_disconnect(phydev);
1054 err_deregister_fixed_link:
1055 	if (of_phy_is_fixed_link(np))
1056 		of_phy_deregister_fixed_link(np);
1057 
1058 	return err;
1059 }
1060 
1061 /* PHY control start function */
1062 static int ravb_phy_start(struct net_device *ndev)
1063 {
1064 	int error;
1065 
1066 	error = ravb_phy_init(ndev);
1067 	if (error)
1068 		return error;
1069 
1070 	phy_start(ndev->phydev);
1071 
1072 	return 0;
1073 }
1074 
1075 static int ravb_get_link_ksettings(struct net_device *ndev,
1076 				   struct ethtool_link_ksettings *cmd)
1077 {
1078 	struct ravb_private *priv = netdev_priv(ndev);
1079 	unsigned long flags;
1080 
1081 	if (!ndev->phydev)
1082 		return -ENODEV;
1083 
1084 	spin_lock_irqsave(&priv->lock, flags);
1085 	phy_ethtool_ksettings_get(ndev->phydev, cmd);
1086 	spin_unlock_irqrestore(&priv->lock, flags);
1087 
1088 	return 0;
1089 }
1090 
1091 static int ravb_set_link_ksettings(struct net_device *ndev,
1092 				   const struct ethtool_link_ksettings *cmd)
1093 {
1094 	struct ravb_private *priv = netdev_priv(ndev);
1095 	unsigned long flags;
1096 	int error;
1097 
1098 	if (!ndev->phydev)
1099 		return -ENODEV;
1100 
1101 	spin_lock_irqsave(&priv->lock, flags);
1102 
1103 	/* Disable TX and RX */
1104 	ravb_rcv_snd_disable(ndev);
1105 
1106 	error = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1107 	if (error)
1108 		goto error_exit;
1109 
1110 	if (cmd->base.duplex == DUPLEX_FULL)
1111 		priv->duplex = 1;
1112 	else
1113 		priv->duplex = 0;
1114 
1115 	ravb_set_duplex(ndev);
1116 
1117 error_exit:
1118 	mdelay(1);
1119 
1120 	/* Enable TX and RX */
1121 	ravb_rcv_snd_enable(ndev);
1122 
1123 	mmiowb();
1124 	spin_unlock_irqrestore(&priv->lock, flags);
1125 
1126 	return error;
1127 }
1128 
1129 static int ravb_nway_reset(struct net_device *ndev)
1130 {
1131 	struct ravb_private *priv = netdev_priv(ndev);
1132 	int error = -ENODEV;
1133 	unsigned long flags;
1134 
1135 	if (ndev->phydev) {
1136 		spin_lock_irqsave(&priv->lock, flags);
1137 		error = phy_start_aneg(ndev->phydev);
1138 		spin_unlock_irqrestore(&priv->lock, flags);
1139 	}
1140 
1141 	return error;
1142 }
1143 
1144 static u32 ravb_get_msglevel(struct net_device *ndev)
1145 {
1146 	struct ravb_private *priv = netdev_priv(ndev);
1147 
1148 	return priv->msg_enable;
1149 }
1150 
1151 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1152 {
1153 	struct ravb_private *priv = netdev_priv(ndev);
1154 
1155 	priv->msg_enable = value;
1156 }
1157 
1158 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1159 	"rx_queue_0_current",
1160 	"tx_queue_0_current",
1161 	"rx_queue_0_dirty",
1162 	"tx_queue_0_dirty",
1163 	"rx_queue_0_packets",
1164 	"tx_queue_0_packets",
1165 	"rx_queue_0_bytes",
1166 	"tx_queue_0_bytes",
1167 	"rx_queue_0_mcast_packets",
1168 	"rx_queue_0_errors",
1169 	"rx_queue_0_crc_errors",
1170 	"rx_queue_0_frame_errors",
1171 	"rx_queue_0_length_errors",
1172 	"rx_queue_0_missed_errors",
1173 	"rx_queue_0_over_errors",
1174 
1175 	"rx_queue_1_current",
1176 	"tx_queue_1_current",
1177 	"rx_queue_1_dirty",
1178 	"tx_queue_1_dirty",
1179 	"rx_queue_1_packets",
1180 	"tx_queue_1_packets",
1181 	"rx_queue_1_bytes",
1182 	"tx_queue_1_bytes",
1183 	"rx_queue_1_mcast_packets",
1184 	"rx_queue_1_errors",
1185 	"rx_queue_1_crc_errors",
1186 	"rx_queue_1_frame_errors",
1187 	"rx_queue_1_length_errors",
1188 	"rx_queue_1_missed_errors",
1189 	"rx_queue_1_over_errors",
1190 };
1191 
1192 #define RAVB_STATS_LEN	ARRAY_SIZE(ravb_gstrings_stats)
1193 
1194 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1195 {
1196 	switch (sset) {
1197 	case ETH_SS_STATS:
1198 		return RAVB_STATS_LEN;
1199 	default:
1200 		return -EOPNOTSUPP;
1201 	}
1202 }
1203 
1204 static void ravb_get_ethtool_stats(struct net_device *ndev,
1205 				   struct ethtool_stats *stats, u64 *data)
1206 {
1207 	struct ravb_private *priv = netdev_priv(ndev);
1208 	int i = 0;
1209 	int q;
1210 
1211 	/* Device-specific stats */
1212 	for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1213 		struct net_device_stats *stats = &priv->stats[q];
1214 
1215 		data[i++] = priv->cur_rx[q];
1216 		data[i++] = priv->cur_tx[q];
1217 		data[i++] = priv->dirty_rx[q];
1218 		data[i++] = priv->dirty_tx[q];
1219 		data[i++] = stats->rx_packets;
1220 		data[i++] = stats->tx_packets;
1221 		data[i++] = stats->rx_bytes;
1222 		data[i++] = stats->tx_bytes;
1223 		data[i++] = stats->multicast;
1224 		data[i++] = stats->rx_errors;
1225 		data[i++] = stats->rx_crc_errors;
1226 		data[i++] = stats->rx_frame_errors;
1227 		data[i++] = stats->rx_length_errors;
1228 		data[i++] = stats->rx_missed_errors;
1229 		data[i++] = stats->rx_over_errors;
1230 	}
1231 }
1232 
1233 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1234 {
1235 	switch (stringset) {
1236 	case ETH_SS_STATS:
1237 		memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1238 		break;
1239 	}
1240 }
1241 
1242 static void ravb_get_ringparam(struct net_device *ndev,
1243 			       struct ethtool_ringparam *ring)
1244 {
1245 	struct ravb_private *priv = netdev_priv(ndev);
1246 
1247 	ring->rx_max_pending = BE_RX_RING_MAX;
1248 	ring->tx_max_pending = BE_TX_RING_MAX;
1249 	ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1250 	ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1251 }
1252 
1253 static int ravb_set_ringparam(struct net_device *ndev,
1254 			      struct ethtool_ringparam *ring)
1255 {
1256 	struct ravb_private *priv = netdev_priv(ndev);
1257 	int error;
1258 
1259 	if (ring->tx_pending > BE_TX_RING_MAX ||
1260 	    ring->rx_pending > BE_RX_RING_MAX ||
1261 	    ring->tx_pending < BE_TX_RING_MIN ||
1262 	    ring->rx_pending < BE_RX_RING_MIN)
1263 		return -EINVAL;
1264 	if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1265 		return -EINVAL;
1266 
1267 	if (netif_running(ndev)) {
1268 		netif_device_detach(ndev);
1269 		/* Stop PTP Clock driver */
1270 		if (priv->chip_id == RCAR_GEN2)
1271 			ravb_ptp_stop(ndev);
1272 		/* Wait for DMA stopping */
1273 		error = ravb_stop_dma(ndev);
1274 		if (error) {
1275 			netdev_err(ndev,
1276 				   "cannot set ringparam! Any AVB processes are still running?\n");
1277 			return error;
1278 		}
1279 		synchronize_irq(ndev->irq);
1280 
1281 		/* Free all the skb's in the RX queue and the DMA buffers. */
1282 		ravb_ring_free(ndev, RAVB_BE);
1283 		ravb_ring_free(ndev, RAVB_NC);
1284 	}
1285 
1286 	/* Set new parameters */
1287 	priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1288 	priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1289 
1290 	if (netif_running(ndev)) {
1291 		error = ravb_dmac_init(ndev);
1292 		if (error) {
1293 			netdev_err(ndev,
1294 				   "%s: ravb_dmac_init() failed, error %d\n",
1295 				   __func__, error);
1296 			return error;
1297 		}
1298 
1299 		ravb_emac_init(ndev);
1300 
1301 		/* Initialise PTP Clock driver */
1302 		if (priv->chip_id == RCAR_GEN2)
1303 			ravb_ptp_init(ndev, priv->pdev);
1304 
1305 		netif_device_attach(ndev);
1306 	}
1307 
1308 	return 0;
1309 }
1310 
1311 static int ravb_get_ts_info(struct net_device *ndev,
1312 			    struct ethtool_ts_info *info)
1313 {
1314 	struct ravb_private *priv = netdev_priv(ndev);
1315 
1316 	info->so_timestamping =
1317 		SOF_TIMESTAMPING_TX_SOFTWARE |
1318 		SOF_TIMESTAMPING_RX_SOFTWARE |
1319 		SOF_TIMESTAMPING_SOFTWARE |
1320 		SOF_TIMESTAMPING_TX_HARDWARE |
1321 		SOF_TIMESTAMPING_RX_HARDWARE |
1322 		SOF_TIMESTAMPING_RAW_HARDWARE;
1323 	info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1324 	info->rx_filters =
1325 		(1 << HWTSTAMP_FILTER_NONE) |
1326 		(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1327 		(1 << HWTSTAMP_FILTER_ALL);
1328 	info->phc_index = ptp_clock_index(priv->ptp.clock);
1329 
1330 	return 0;
1331 }
1332 
1333 static const struct ethtool_ops ravb_ethtool_ops = {
1334 	.nway_reset		= ravb_nway_reset,
1335 	.get_msglevel		= ravb_get_msglevel,
1336 	.set_msglevel		= ravb_set_msglevel,
1337 	.get_link		= ethtool_op_get_link,
1338 	.get_strings		= ravb_get_strings,
1339 	.get_ethtool_stats	= ravb_get_ethtool_stats,
1340 	.get_sset_count		= ravb_get_sset_count,
1341 	.get_ringparam		= ravb_get_ringparam,
1342 	.set_ringparam		= ravb_set_ringparam,
1343 	.get_ts_info		= ravb_get_ts_info,
1344 	.get_link_ksettings	= ravb_get_link_ksettings,
1345 	.set_link_ksettings	= ravb_set_link_ksettings,
1346 };
1347 
1348 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1349 				struct net_device *ndev, struct device *dev,
1350 				const char *ch)
1351 {
1352 	char *name;
1353 	int error;
1354 
1355 	name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1356 	if (!name)
1357 		return -ENOMEM;
1358 	error = request_irq(irq, handler, 0, name, ndev);
1359 	if (error)
1360 		netdev_err(ndev, "cannot request IRQ %s\n", name);
1361 
1362 	return error;
1363 }
1364 
1365 /* Network device open function for Ethernet AVB */
1366 static int ravb_open(struct net_device *ndev)
1367 {
1368 	struct ravb_private *priv = netdev_priv(ndev);
1369 	struct platform_device *pdev = priv->pdev;
1370 	struct device *dev = &pdev->dev;
1371 	int error;
1372 
1373 	napi_enable(&priv->napi[RAVB_BE]);
1374 	napi_enable(&priv->napi[RAVB_NC]);
1375 
1376 	if (priv->chip_id == RCAR_GEN2) {
1377 		error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1378 				    ndev->name, ndev);
1379 		if (error) {
1380 			netdev_err(ndev, "cannot request IRQ\n");
1381 			goto out_napi_off;
1382 		}
1383 	} else {
1384 		error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1385 				      dev, "ch22:multi");
1386 		if (error)
1387 			goto out_napi_off;
1388 		error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1389 				      dev, "ch24:emac");
1390 		if (error)
1391 			goto out_free_irq;
1392 		error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1393 				      ndev, dev, "ch0:rx_be");
1394 		if (error)
1395 			goto out_free_irq_emac;
1396 		error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1397 				      ndev, dev, "ch18:tx_be");
1398 		if (error)
1399 			goto out_free_irq_be_rx;
1400 		error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1401 				      ndev, dev, "ch1:rx_nc");
1402 		if (error)
1403 			goto out_free_irq_be_tx;
1404 		error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1405 				      ndev, dev, "ch19:tx_nc");
1406 		if (error)
1407 			goto out_free_irq_nc_rx;
1408 	}
1409 
1410 	/* Device init */
1411 	error = ravb_dmac_init(ndev);
1412 	if (error)
1413 		goto out_free_irq_nc_tx;
1414 	ravb_emac_init(ndev);
1415 
1416 	/* Initialise PTP Clock driver */
1417 	if (priv->chip_id == RCAR_GEN2)
1418 		ravb_ptp_init(ndev, priv->pdev);
1419 
1420 	netif_tx_start_all_queues(ndev);
1421 
1422 	/* PHY control start */
1423 	error = ravb_phy_start(ndev);
1424 	if (error)
1425 		goto out_ptp_stop;
1426 
1427 	return 0;
1428 
1429 out_ptp_stop:
1430 	/* Stop PTP Clock driver */
1431 	if (priv->chip_id == RCAR_GEN2)
1432 		ravb_ptp_stop(ndev);
1433 out_free_irq_nc_tx:
1434 	if (priv->chip_id == RCAR_GEN2)
1435 		goto out_free_irq;
1436 	free_irq(priv->tx_irqs[RAVB_NC], ndev);
1437 out_free_irq_nc_rx:
1438 	free_irq(priv->rx_irqs[RAVB_NC], ndev);
1439 out_free_irq_be_tx:
1440 	free_irq(priv->tx_irqs[RAVB_BE], ndev);
1441 out_free_irq_be_rx:
1442 	free_irq(priv->rx_irqs[RAVB_BE], ndev);
1443 out_free_irq_emac:
1444 	free_irq(priv->emac_irq, ndev);
1445 out_free_irq:
1446 	free_irq(ndev->irq, ndev);
1447 out_napi_off:
1448 	napi_disable(&priv->napi[RAVB_NC]);
1449 	napi_disable(&priv->napi[RAVB_BE]);
1450 	return error;
1451 }
1452 
1453 /* Timeout function for Ethernet AVB */
1454 static void ravb_tx_timeout(struct net_device *ndev)
1455 {
1456 	struct ravb_private *priv = netdev_priv(ndev);
1457 
1458 	netif_err(priv, tx_err, ndev,
1459 		  "transmit timed out, status %08x, resetting...\n",
1460 		  ravb_read(ndev, ISS));
1461 
1462 	/* tx_errors count up */
1463 	ndev->stats.tx_errors++;
1464 
1465 	schedule_work(&priv->work);
1466 }
1467 
1468 static void ravb_tx_timeout_work(struct work_struct *work)
1469 {
1470 	struct ravb_private *priv = container_of(work, struct ravb_private,
1471 						 work);
1472 	struct net_device *ndev = priv->ndev;
1473 
1474 	netif_tx_stop_all_queues(ndev);
1475 
1476 	/* Stop PTP Clock driver */
1477 	if (priv->chip_id == RCAR_GEN2)
1478 		ravb_ptp_stop(ndev);
1479 
1480 	/* Wait for DMA stopping */
1481 	ravb_stop_dma(ndev);
1482 
1483 	ravb_ring_free(ndev, RAVB_BE);
1484 	ravb_ring_free(ndev, RAVB_NC);
1485 
1486 	/* Device init */
1487 	ravb_dmac_init(ndev);
1488 	ravb_emac_init(ndev);
1489 
1490 	/* Initialise PTP Clock driver */
1491 	if (priv->chip_id == RCAR_GEN2)
1492 		ravb_ptp_init(ndev, priv->pdev);
1493 
1494 	netif_tx_start_all_queues(ndev);
1495 }
1496 
1497 /* Packet transmit function for Ethernet AVB */
1498 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1499 {
1500 	struct ravb_private *priv = netdev_priv(ndev);
1501 	u16 q = skb_get_queue_mapping(skb);
1502 	struct ravb_tstamp_skb *ts_skb;
1503 	struct ravb_tx_desc *desc;
1504 	unsigned long flags;
1505 	u32 dma_addr;
1506 	void *buffer;
1507 	u32 entry;
1508 	u32 len;
1509 
1510 	spin_lock_irqsave(&priv->lock, flags);
1511 	if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1512 	    NUM_TX_DESC) {
1513 		netif_err(priv, tx_queued, ndev,
1514 			  "still transmitting with the full ring!\n");
1515 		netif_stop_subqueue(ndev, q);
1516 		spin_unlock_irqrestore(&priv->lock, flags);
1517 		return NETDEV_TX_BUSY;
1518 	}
1519 
1520 	if (skb_put_padto(skb, ETH_ZLEN))
1521 		goto exit;
1522 
1523 	entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1524 	priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1525 
1526 	buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1527 		 entry / NUM_TX_DESC * DPTR_ALIGN;
1528 	len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1529 	/* Zero length DMA descriptors are problematic as they seem to
1530 	 * terminate DMA transfers. Avoid them by simply using a length of
1531 	 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1532 	 *
1533 	 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1534 	 * data by the call to skb_put_padto() above this is safe with
1535 	 * respect to both the length of the first DMA descriptor (len)
1536 	 * overflowing the available data and the length of the second DMA
1537 	 * descriptor (skb->len - len) being negative.
1538 	 */
1539 	if (len == 0)
1540 		len = DPTR_ALIGN;
1541 
1542 	memcpy(buffer, skb->data, len);
1543 	dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1544 	if (dma_mapping_error(ndev->dev.parent, dma_addr))
1545 		goto drop;
1546 
1547 	desc = &priv->tx_ring[q][entry];
1548 	desc->ds_tagl = cpu_to_le16(len);
1549 	desc->dptr = cpu_to_le32(dma_addr);
1550 
1551 	buffer = skb->data + len;
1552 	len = skb->len - len;
1553 	dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1554 	if (dma_mapping_error(ndev->dev.parent, dma_addr))
1555 		goto unmap;
1556 
1557 	desc++;
1558 	desc->ds_tagl = cpu_to_le16(len);
1559 	desc->dptr = cpu_to_le32(dma_addr);
1560 
1561 	/* TX timestamp required */
1562 	if (q == RAVB_NC) {
1563 		ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1564 		if (!ts_skb) {
1565 			desc--;
1566 			dma_unmap_single(ndev->dev.parent, dma_addr, len,
1567 					 DMA_TO_DEVICE);
1568 			goto unmap;
1569 		}
1570 		ts_skb->skb = skb;
1571 		ts_skb->tag = priv->ts_skb_tag++;
1572 		priv->ts_skb_tag &= 0x3ff;
1573 		list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1574 
1575 		/* TAG and timestamp required flag */
1576 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1577 		desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1578 		desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1579 	}
1580 
1581 	skb_tx_timestamp(skb);
1582 	/* Descriptor type must be set after all the above writes */
1583 	dma_wmb();
1584 	desc->die_dt = DT_FEND;
1585 	desc--;
1586 	desc->die_dt = DT_FSTART;
1587 
1588 	ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1589 
1590 	priv->cur_tx[q] += NUM_TX_DESC;
1591 	if (priv->cur_tx[q] - priv->dirty_tx[q] >
1592 	    (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1593 	    !ravb_tx_free(ndev, q, true))
1594 		netif_stop_subqueue(ndev, q);
1595 
1596 exit:
1597 	mmiowb();
1598 	spin_unlock_irqrestore(&priv->lock, flags);
1599 	return NETDEV_TX_OK;
1600 
1601 unmap:
1602 	dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1603 			 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1604 drop:
1605 	dev_kfree_skb_any(skb);
1606 	priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1607 	goto exit;
1608 }
1609 
1610 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1611 			     void *accel_priv, select_queue_fallback_t fallback)
1612 {
1613 	/* If skb needs TX timestamp, it is handled in network control queue */
1614 	return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1615 							       RAVB_BE;
1616 
1617 }
1618 
1619 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1620 {
1621 	struct ravb_private *priv = netdev_priv(ndev);
1622 	struct net_device_stats *nstats, *stats0, *stats1;
1623 
1624 	nstats = &ndev->stats;
1625 	stats0 = &priv->stats[RAVB_BE];
1626 	stats1 = &priv->stats[RAVB_NC];
1627 
1628 	nstats->tx_dropped += ravb_read(ndev, TROCR);
1629 	ravb_write(ndev, 0, TROCR);	/* (write clear) */
1630 	nstats->collisions += ravb_read(ndev, CDCR);
1631 	ravb_write(ndev, 0, CDCR);	/* (write clear) */
1632 	nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1633 	ravb_write(ndev, 0, LCCR);	/* (write clear) */
1634 
1635 	nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1636 	ravb_write(ndev, 0, CERCR);	/* (write clear) */
1637 	nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1638 	ravb_write(ndev, 0, CEECR);	/* (write clear) */
1639 
1640 	nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1641 	nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1642 	nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1643 	nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1644 	nstats->multicast = stats0->multicast + stats1->multicast;
1645 	nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1646 	nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1647 	nstats->rx_frame_errors =
1648 		stats0->rx_frame_errors + stats1->rx_frame_errors;
1649 	nstats->rx_length_errors =
1650 		stats0->rx_length_errors + stats1->rx_length_errors;
1651 	nstats->rx_missed_errors =
1652 		stats0->rx_missed_errors + stats1->rx_missed_errors;
1653 	nstats->rx_over_errors =
1654 		stats0->rx_over_errors + stats1->rx_over_errors;
1655 
1656 	return nstats;
1657 }
1658 
1659 /* Update promiscuous bit */
1660 static void ravb_set_rx_mode(struct net_device *ndev)
1661 {
1662 	struct ravb_private *priv = netdev_priv(ndev);
1663 	unsigned long flags;
1664 
1665 	spin_lock_irqsave(&priv->lock, flags);
1666 	ravb_modify(ndev, ECMR, ECMR_PRM,
1667 		    ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1668 	mmiowb();
1669 	spin_unlock_irqrestore(&priv->lock, flags);
1670 }
1671 
1672 /* Device close function for Ethernet AVB */
1673 static int ravb_close(struct net_device *ndev)
1674 {
1675 	struct device_node *np = ndev->dev.parent->of_node;
1676 	struct ravb_private *priv = netdev_priv(ndev);
1677 	struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1678 
1679 	netif_tx_stop_all_queues(ndev);
1680 
1681 	/* Disable interrupts by clearing the interrupt masks. */
1682 	ravb_write(ndev, 0, RIC0);
1683 	ravb_write(ndev, 0, RIC2);
1684 	ravb_write(ndev, 0, TIC);
1685 
1686 	/* Stop PTP Clock driver */
1687 	if (priv->chip_id == RCAR_GEN2)
1688 		ravb_ptp_stop(ndev);
1689 
1690 	/* Set the config mode to stop the AVB-DMAC's processes */
1691 	if (ravb_stop_dma(ndev) < 0)
1692 		netdev_err(ndev,
1693 			   "device will be stopped after h/w processes are done.\n");
1694 
1695 	/* Clear the timestamp list */
1696 	list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1697 		list_del(&ts_skb->list);
1698 		kfree(ts_skb);
1699 	}
1700 
1701 	/* PHY disconnect */
1702 	if (ndev->phydev) {
1703 		phy_stop(ndev->phydev);
1704 		phy_disconnect(ndev->phydev);
1705 		if (of_phy_is_fixed_link(np))
1706 			of_phy_deregister_fixed_link(np);
1707 	}
1708 
1709 	if (priv->chip_id != RCAR_GEN2) {
1710 		free_irq(priv->tx_irqs[RAVB_NC], ndev);
1711 		free_irq(priv->rx_irqs[RAVB_NC], ndev);
1712 		free_irq(priv->tx_irqs[RAVB_BE], ndev);
1713 		free_irq(priv->rx_irqs[RAVB_BE], ndev);
1714 		free_irq(priv->emac_irq, ndev);
1715 	}
1716 	free_irq(ndev->irq, ndev);
1717 
1718 	napi_disable(&priv->napi[RAVB_NC]);
1719 	napi_disable(&priv->napi[RAVB_BE]);
1720 
1721 	/* Free all the skb's in the RX queue and the DMA buffers. */
1722 	ravb_ring_free(ndev, RAVB_BE);
1723 	ravb_ring_free(ndev, RAVB_NC);
1724 
1725 	return 0;
1726 }
1727 
1728 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1729 {
1730 	struct ravb_private *priv = netdev_priv(ndev);
1731 	struct hwtstamp_config config;
1732 
1733 	config.flags = 0;
1734 	config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1735 						HWTSTAMP_TX_OFF;
1736 	if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1737 		config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1738 	else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1739 		config.rx_filter = HWTSTAMP_FILTER_ALL;
1740 	else
1741 		config.rx_filter = HWTSTAMP_FILTER_NONE;
1742 
1743 	return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1744 		-EFAULT : 0;
1745 }
1746 
1747 /* Control hardware time stamping */
1748 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1749 {
1750 	struct ravb_private *priv = netdev_priv(ndev);
1751 	struct hwtstamp_config config;
1752 	u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1753 	u32 tstamp_tx_ctrl;
1754 
1755 	if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1756 		return -EFAULT;
1757 
1758 	/* Reserved for future extensions */
1759 	if (config.flags)
1760 		return -EINVAL;
1761 
1762 	switch (config.tx_type) {
1763 	case HWTSTAMP_TX_OFF:
1764 		tstamp_tx_ctrl = 0;
1765 		break;
1766 	case HWTSTAMP_TX_ON:
1767 		tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1768 		break;
1769 	default:
1770 		return -ERANGE;
1771 	}
1772 
1773 	switch (config.rx_filter) {
1774 	case HWTSTAMP_FILTER_NONE:
1775 		tstamp_rx_ctrl = 0;
1776 		break;
1777 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1778 		tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1779 		break;
1780 	default:
1781 		config.rx_filter = HWTSTAMP_FILTER_ALL;
1782 		tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1783 	}
1784 
1785 	priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1786 	priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1787 
1788 	return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1789 		-EFAULT : 0;
1790 }
1791 
1792 /* ioctl to device function */
1793 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1794 {
1795 	struct phy_device *phydev = ndev->phydev;
1796 
1797 	if (!netif_running(ndev))
1798 		return -EINVAL;
1799 
1800 	if (!phydev)
1801 		return -ENODEV;
1802 
1803 	switch (cmd) {
1804 	case SIOCGHWTSTAMP:
1805 		return ravb_hwtstamp_get(ndev, req);
1806 	case SIOCSHWTSTAMP:
1807 		return ravb_hwtstamp_set(ndev, req);
1808 	}
1809 
1810 	return phy_mii_ioctl(phydev, req, cmd);
1811 }
1812 
1813 static const struct net_device_ops ravb_netdev_ops = {
1814 	.ndo_open		= ravb_open,
1815 	.ndo_stop		= ravb_close,
1816 	.ndo_start_xmit		= ravb_start_xmit,
1817 	.ndo_select_queue	= ravb_select_queue,
1818 	.ndo_get_stats		= ravb_get_stats,
1819 	.ndo_set_rx_mode	= ravb_set_rx_mode,
1820 	.ndo_tx_timeout		= ravb_tx_timeout,
1821 	.ndo_do_ioctl		= ravb_do_ioctl,
1822 	.ndo_validate_addr	= eth_validate_addr,
1823 	.ndo_set_mac_address	= eth_mac_addr,
1824 };
1825 
1826 /* MDIO bus init function */
1827 static int ravb_mdio_init(struct ravb_private *priv)
1828 {
1829 	struct platform_device *pdev = priv->pdev;
1830 	struct device *dev = &pdev->dev;
1831 	int error;
1832 
1833 	/* Bitbang init */
1834 	priv->mdiobb.ops = &bb_ops;
1835 
1836 	/* MII controller setting */
1837 	priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1838 	if (!priv->mii_bus)
1839 		return -ENOMEM;
1840 
1841 	/* Hook up MII support for ethtool */
1842 	priv->mii_bus->name = "ravb_mii";
1843 	priv->mii_bus->parent = dev;
1844 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1845 		 pdev->name, pdev->id);
1846 
1847 	/* Register MDIO bus */
1848 	error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1849 	if (error)
1850 		goto out_free_bus;
1851 
1852 	return 0;
1853 
1854 out_free_bus:
1855 	free_mdio_bitbang(priv->mii_bus);
1856 	return error;
1857 }
1858 
1859 /* MDIO bus release function */
1860 static int ravb_mdio_release(struct ravb_private *priv)
1861 {
1862 	/* Unregister mdio bus */
1863 	mdiobus_unregister(priv->mii_bus);
1864 
1865 	/* Free bitbang info */
1866 	free_mdio_bitbang(priv->mii_bus);
1867 
1868 	return 0;
1869 }
1870 
1871 static const struct of_device_id ravb_match_table[] = {
1872 	{ .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1873 	{ .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1874 	{ .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1875 	{ .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1876 	{ .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1877 	{ }
1878 };
1879 MODULE_DEVICE_TABLE(of, ravb_match_table);
1880 
1881 static int ravb_set_gti(struct net_device *ndev)
1882 {
1883 
1884 	struct device *dev = ndev->dev.parent;
1885 	struct device_node *np = dev->of_node;
1886 	unsigned long rate;
1887 	struct clk *clk;
1888 	uint64_t inc;
1889 
1890 	clk = of_clk_get(np, 0);
1891 	if (IS_ERR(clk)) {
1892 		dev_err(dev, "could not get clock\n");
1893 		return PTR_ERR(clk);
1894 	}
1895 
1896 	rate = clk_get_rate(clk);
1897 	clk_put(clk);
1898 
1899 	if (!rate)
1900 		return -EINVAL;
1901 
1902 	inc = 1000000000ULL << 20;
1903 	do_div(inc, rate);
1904 
1905 	if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1906 		dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1907 			inc, GTI_TIV_MIN, GTI_TIV_MAX);
1908 		return -EINVAL;
1909 	}
1910 
1911 	ravb_write(ndev, inc, GTI);
1912 
1913 	return 0;
1914 }
1915 
1916 static void ravb_set_config_mode(struct net_device *ndev)
1917 {
1918 	struct ravb_private *priv = netdev_priv(ndev);
1919 
1920 	if (priv->chip_id == RCAR_GEN2) {
1921 		ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1922 		/* Set CSEL value */
1923 		ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1924 	} else {
1925 		ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1926 			    CCC_GAC | CCC_CSEL_HPB);
1927 	}
1928 }
1929 
1930 /* Set tx and rx clock internal delay modes */
1931 static void ravb_set_delay_mode(struct net_device *ndev)
1932 {
1933 	struct ravb_private *priv = netdev_priv(ndev);
1934 	int set = 0;
1935 
1936 	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1937 	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
1938 		set |= APSR_DM_RDM;
1939 
1940 	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1941 	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1942 		set |= APSR_DM_TDM;
1943 
1944 	ravb_modify(ndev, APSR, APSR_DM, set);
1945 }
1946 
1947 static int ravb_probe(struct platform_device *pdev)
1948 {
1949 	struct device_node *np = pdev->dev.of_node;
1950 	struct ravb_private *priv;
1951 	enum ravb_chip_id chip_id;
1952 	struct net_device *ndev;
1953 	int error, irq, q;
1954 	struct resource *res;
1955 	int i;
1956 
1957 	if (!np) {
1958 		dev_err(&pdev->dev,
1959 			"this driver is required to be instantiated from device tree\n");
1960 		return -EINVAL;
1961 	}
1962 
1963 	/* Get base address */
1964 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1965 	if (!res) {
1966 		dev_err(&pdev->dev, "invalid resource\n");
1967 		return -EINVAL;
1968 	}
1969 
1970 	ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1971 				  NUM_TX_QUEUE, NUM_RX_QUEUE);
1972 	if (!ndev)
1973 		return -ENOMEM;
1974 
1975 	pm_runtime_enable(&pdev->dev);
1976 	pm_runtime_get_sync(&pdev->dev);
1977 
1978 	/* The Ether-specific entries in the device structure. */
1979 	ndev->base_addr = res->start;
1980 
1981 	chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
1982 
1983 	if (chip_id == RCAR_GEN3)
1984 		irq = platform_get_irq_byname(pdev, "ch22");
1985 	else
1986 		irq = platform_get_irq(pdev, 0);
1987 	if (irq < 0) {
1988 		error = irq;
1989 		goto out_release;
1990 	}
1991 	ndev->irq = irq;
1992 
1993 	SET_NETDEV_DEV(ndev, &pdev->dev);
1994 
1995 	priv = netdev_priv(ndev);
1996 	priv->ndev = ndev;
1997 	priv->pdev = pdev;
1998 	priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1999 	priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2000 	priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2001 	priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2002 	priv->addr = devm_ioremap_resource(&pdev->dev, res);
2003 	if (IS_ERR(priv->addr)) {
2004 		error = PTR_ERR(priv->addr);
2005 		goto out_release;
2006 	}
2007 
2008 	spin_lock_init(&priv->lock);
2009 	INIT_WORK(&priv->work, ravb_tx_timeout_work);
2010 
2011 	priv->phy_interface = of_get_phy_mode(np);
2012 
2013 	priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2014 	priv->avb_link_active_low =
2015 		of_property_read_bool(np, "renesas,ether-link-active-low");
2016 
2017 	if (chip_id == RCAR_GEN3) {
2018 		irq = platform_get_irq_byname(pdev, "ch24");
2019 		if (irq < 0) {
2020 			error = irq;
2021 			goto out_release;
2022 		}
2023 		priv->emac_irq = irq;
2024 		for (i = 0; i < NUM_RX_QUEUE; i++) {
2025 			irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2026 			if (irq < 0) {
2027 				error = irq;
2028 				goto out_release;
2029 			}
2030 			priv->rx_irqs[i] = irq;
2031 		}
2032 		for (i = 0; i < NUM_TX_QUEUE; i++) {
2033 			irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2034 			if (irq < 0) {
2035 				error = irq;
2036 				goto out_release;
2037 			}
2038 			priv->tx_irqs[i] = irq;
2039 		}
2040 	}
2041 
2042 	priv->chip_id = chip_id;
2043 
2044 	/* Set function */
2045 	ndev->netdev_ops = &ravb_netdev_ops;
2046 	ndev->ethtool_ops = &ravb_ethtool_ops;
2047 
2048 	/* Set AVB config mode */
2049 	ravb_set_config_mode(ndev);
2050 
2051 	/* Set GTI value */
2052 	error = ravb_set_gti(ndev);
2053 	if (error)
2054 		goto out_release;
2055 
2056 	/* Request GTI loading */
2057 	ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2058 
2059 	if (priv->chip_id != RCAR_GEN2)
2060 		ravb_set_delay_mode(ndev);
2061 
2062 	/* Allocate descriptor base address table */
2063 	priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2064 	priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2065 					    &priv->desc_bat_dma, GFP_KERNEL);
2066 	if (!priv->desc_bat) {
2067 		dev_err(&pdev->dev,
2068 			"Cannot allocate desc base address table (size %d bytes)\n",
2069 			priv->desc_bat_size);
2070 		error = -ENOMEM;
2071 		goto out_release;
2072 	}
2073 	for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2074 		priv->desc_bat[q].die_dt = DT_EOS;
2075 	ravb_write(ndev, priv->desc_bat_dma, DBAT);
2076 
2077 	/* Initialise HW timestamp list */
2078 	INIT_LIST_HEAD(&priv->ts_skb_list);
2079 
2080 	/* Initialise PTP Clock driver */
2081 	if (chip_id != RCAR_GEN2)
2082 		ravb_ptp_init(ndev, pdev);
2083 
2084 	/* Debug message level */
2085 	priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2086 
2087 	/* Read and set MAC address */
2088 	ravb_read_mac_address(ndev, of_get_mac_address(np));
2089 	if (!is_valid_ether_addr(ndev->dev_addr)) {
2090 		dev_warn(&pdev->dev,
2091 			 "no valid MAC address supplied, using a random one\n");
2092 		eth_hw_addr_random(ndev);
2093 	}
2094 
2095 	/* MDIO bus init */
2096 	error = ravb_mdio_init(priv);
2097 	if (error) {
2098 		dev_err(&pdev->dev, "failed to initialize MDIO\n");
2099 		goto out_dma_free;
2100 	}
2101 
2102 	netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2103 	netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2104 
2105 	/* Network device register */
2106 	error = register_netdev(ndev);
2107 	if (error)
2108 		goto out_napi_del;
2109 
2110 	/* Print device information */
2111 	netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2112 		    (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2113 
2114 	platform_set_drvdata(pdev, ndev);
2115 
2116 	return 0;
2117 
2118 out_napi_del:
2119 	netif_napi_del(&priv->napi[RAVB_NC]);
2120 	netif_napi_del(&priv->napi[RAVB_BE]);
2121 	ravb_mdio_release(priv);
2122 out_dma_free:
2123 	dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2124 			  priv->desc_bat_dma);
2125 
2126 	/* Stop PTP Clock driver */
2127 	if (chip_id != RCAR_GEN2)
2128 		ravb_ptp_stop(ndev);
2129 out_release:
2130 	if (ndev)
2131 		free_netdev(ndev);
2132 
2133 	pm_runtime_put(&pdev->dev);
2134 	pm_runtime_disable(&pdev->dev);
2135 	return error;
2136 }
2137 
2138 static int ravb_remove(struct platform_device *pdev)
2139 {
2140 	struct net_device *ndev = platform_get_drvdata(pdev);
2141 	struct ravb_private *priv = netdev_priv(ndev);
2142 
2143 	/* Stop PTP Clock driver */
2144 	if (priv->chip_id != RCAR_GEN2)
2145 		ravb_ptp_stop(ndev);
2146 
2147 	dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2148 			  priv->desc_bat_dma);
2149 	/* Set reset mode */
2150 	ravb_write(ndev, CCC_OPC_RESET, CCC);
2151 	pm_runtime_put_sync(&pdev->dev);
2152 	unregister_netdev(ndev);
2153 	netif_napi_del(&priv->napi[RAVB_NC]);
2154 	netif_napi_del(&priv->napi[RAVB_BE]);
2155 	ravb_mdio_release(priv);
2156 	pm_runtime_disable(&pdev->dev);
2157 	free_netdev(ndev);
2158 	platform_set_drvdata(pdev, NULL);
2159 
2160 	return 0;
2161 }
2162 
2163 static int __maybe_unused ravb_suspend(struct device *dev)
2164 {
2165 	struct net_device *ndev = dev_get_drvdata(dev);
2166 	int ret = 0;
2167 
2168 	if (netif_running(ndev)) {
2169 		netif_device_detach(ndev);
2170 		ret = ravb_close(ndev);
2171 	}
2172 
2173 	return ret;
2174 }
2175 
2176 static int __maybe_unused ravb_resume(struct device *dev)
2177 {
2178 	struct net_device *ndev = dev_get_drvdata(dev);
2179 	struct ravb_private *priv = netdev_priv(ndev);
2180 	int ret = 0;
2181 
2182 	/* All register have been reset to default values.
2183 	 * Restore all registers which where setup at probe time and
2184 	 * reopen device if it was running before system suspended.
2185 	 */
2186 
2187 	/* Set AVB config mode */
2188 	ravb_set_config_mode(ndev);
2189 
2190 	/* Set GTI value */
2191 	ret = ravb_set_gti(ndev);
2192 	if (ret)
2193 		return ret;
2194 
2195 	/* Request GTI loading */
2196 	ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2197 
2198 	if (priv->chip_id != RCAR_GEN2)
2199 		ravb_set_delay_mode(ndev);
2200 
2201 	/* Restore descriptor base address table */
2202 	ravb_write(ndev, priv->desc_bat_dma, DBAT);
2203 
2204 	if (netif_running(ndev)) {
2205 		ret = ravb_open(ndev);
2206 		if (ret < 0)
2207 			return ret;
2208 		netif_device_attach(ndev);
2209 	}
2210 
2211 	return ret;
2212 }
2213 
2214 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2215 {
2216 	/* Runtime PM callback shared between ->runtime_suspend()
2217 	 * and ->runtime_resume(). Simply returns success.
2218 	 *
2219 	 * This driver re-initializes all registers after
2220 	 * pm_runtime_get_sync() anyway so there is no need
2221 	 * to save and restore registers here.
2222 	 */
2223 	return 0;
2224 }
2225 
2226 static const struct dev_pm_ops ravb_dev_pm_ops = {
2227 	SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2228 	SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2229 };
2230 
2231 static struct platform_driver ravb_driver = {
2232 	.probe		= ravb_probe,
2233 	.remove		= ravb_remove,
2234 	.driver = {
2235 		.name	= "ravb",
2236 		.pm	= &ravb_dev_pm_ops,
2237 		.of_match_table = ravb_match_table,
2238 	},
2239 };
2240 
2241 module_platform_driver(ravb_driver);
2242 
2243 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2244 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2245 MODULE_LICENSE("GPL v2");
2246