1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 33 #include <asm/div64.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46 }; 47 48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51 }; 52 53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55 { 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57 } 58 59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60 { 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69 } 70 71 static int ravb_config(struct net_device *ndev) 72 { 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83 } 84 85 static void ravb_set_rate(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 switch (priv->speed) { 90 case 100: /* 100BASE */ 91 ravb_write(ndev, GECMR_SPEED_100, GECMR); 92 break; 93 case 1000: /* 1000BASE */ 94 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 95 break; 96 } 97 } 98 99 static void ravb_set_buffer_align(struct sk_buff *skb) 100 { 101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 102 103 if (reserve) 104 skb_reserve(skb, RAVB_ALIGN - reserve); 105 } 106 107 /* Get MAC address from the MAC address registers 108 * 109 * Ethernet AVB device doesn't have ROM for MAC address. 110 * This function gets the MAC address that was used by a bootloader. 111 */ 112 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 113 { 114 if (mac) { 115 ether_addr_copy(ndev->dev_addr, mac); 116 } else { 117 u32 mahr = ravb_read(ndev, MAHR); 118 u32 malr = ravb_read(ndev, MALR); 119 120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 124 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 125 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 126 } 127 } 128 129 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 130 { 131 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 132 mdiobb); 133 134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 135 } 136 137 /* MDC pin control */ 138 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 139 { 140 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 141 } 142 143 /* Data I/O pin control */ 144 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 145 { 146 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 147 } 148 149 /* Set data bit */ 150 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 151 { 152 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 153 } 154 155 /* Get data bit */ 156 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 157 { 158 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 159 mdiobb); 160 161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 162 } 163 164 /* MDIO bus control struct */ 165 static struct mdiobb_ops bb_ops = { 166 .owner = THIS_MODULE, 167 .set_mdc = ravb_set_mdc, 168 .set_mdio_dir = ravb_set_mdio_dir, 169 .set_mdio_data = ravb_set_mdio_data, 170 .get_mdio_data = ravb_get_mdio_data, 171 }; 172 173 /* Free TX skb function for AVB-IP */ 174 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 175 { 176 struct ravb_private *priv = netdev_priv(ndev); 177 struct net_device_stats *stats = &priv->stats[q]; 178 int num_tx_desc = priv->num_tx_desc; 179 struct ravb_tx_desc *desc; 180 int free_num = 0; 181 int entry; 182 u32 size; 183 184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 185 bool txed; 186 187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 188 num_tx_desc); 189 desc = &priv->tx_ring[q][entry]; 190 txed = desc->die_dt == DT_FEMPTY; 191 if (free_txed_only && !txed) 192 break; 193 /* Descriptor type must be checked before all other reads */ 194 dma_rmb(); 195 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 196 /* Free the original skb. */ 197 if (priv->tx_skb[q][entry / num_tx_desc]) { 198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 199 size, DMA_TO_DEVICE); 200 /* Last packet descriptor? */ 201 if (entry % num_tx_desc == num_tx_desc - 1) { 202 entry /= num_tx_desc; 203 dev_kfree_skb_any(priv->tx_skb[q][entry]); 204 priv->tx_skb[q][entry] = NULL; 205 if (txed) 206 stats->tx_packets++; 207 } 208 free_num++; 209 } 210 if (txed) 211 stats->tx_bytes += size; 212 desc->die_dt = DT_EEMPTY; 213 } 214 return free_num; 215 } 216 217 /* Free skb's and DMA buffers for Ethernet AVB */ 218 static void ravb_ring_free(struct net_device *ndev, int q) 219 { 220 struct ravb_private *priv = netdev_priv(ndev); 221 int num_tx_desc = priv->num_tx_desc; 222 int ring_size; 223 int i; 224 225 if (priv->rx_ring[q]) { 226 for (i = 0; i < priv->num_rx_ring[q]; i++) { 227 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 228 229 if (!dma_mapping_error(ndev->dev.parent, 230 le32_to_cpu(desc->dptr))) 231 dma_unmap_single(ndev->dev.parent, 232 le32_to_cpu(desc->dptr), 233 priv->rx_buf_sz, 234 DMA_FROM_DEVICE); 235 } 236 ring_size = sizeof(struct ravb_ex_rx_desc) * 237 (priv->num_rx_ring[q] + 1); 238 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 239 priv->rx_desc_dma[q]); 240 priv->rx_ring[q] = NULL; 241 } 242 243 if (priv->tx_ring[q]) { 244 ravb_tx_free(ndev, q, false); 245 246 ring_size = sizeof(struct ravb_tx_desc) * 247 (priv->num_tx_ring[q] * num_tx_desc + 1); 248 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 249 priv->tx_desc_dma[q]); 250 priv->tx_ring[q] = NULL; 251 } 252 253 /* Free RX skb ringbuffer */ 254 if (priv->rx_skb[q]) { 255 for (i = 0; i < priv->num_rx_ring[q]; i++) 256 dev_kfree_skb(priv->rx_skb[q][i]); 257 } 258 kfree(priv->rx_skb[q]); 259 priv->rx_skb[q] = NULL; 260 261 /* Free aligned TX buffers */ 262 kfree(priv->tx_align[q]); 263 priv->tx_align[q] = NULL; 264 265 /* Free TX skb ringbuffer. 266 * SKBs are freed by ravb_tx_free() call above. 267 */ 268 kfree(priv->tx_skb[q]); 269 priv->tx_skb[q] = NULL; 270 } 271 272 /* Format skb and descriptor buffer for Ethernet AVB */ 273 static void ravb_ring_format(struct net_device *ndev, int q) 274 { 275 struct ravb_private *priv = netdev_priv(ndev); 276 int num_tx_desc = priv->num_tx_desc; 277 struct ravb_ex_rx_desc *rx_desc; 278 struct ravb_tx_desc *tx_desc; 279 struct ravb_desc *desc; 280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 282 num_tx_desc; 283 dma_addr_t dma_addr; 284 int i; 285 286 priv->cur_rx[q] = 0; 287 priv->cur_tx[q] = 0; 288 priv->dirty_rx[q] = 0; 289 priv->dirty_tx[q] = 0; 290 291 memset(priv->rx_ring[q], 0, rx_ring_size); 292 /* Build RX ring buffer */ 293 for (i = 0; i < priv->num_rx_ring[q]; i++) { 294 /* RX descriptor */ 295 rx_desc = &priv->rx_ring[q][i]; 296 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 298 priv->rx_buf_sz, 299 DMA_FROM_DEVICE); 300 /* We just set the data size to 0 for a failed mapping which 301 * should prevent DMA from happening... 302 */ 303 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 304 rx_desc->ds_cc = cpu_to_le16(0); 305 rx_desc->dptr = cpu_to_le32(dma_addr); 306 rx_desc->die_dt = DT_FEMPTY; 307 } 308 rx_desc = &priv->rx_ring[q][i]; 309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 310 rx_desc->die_dt = DT_LINKFIX; /* type */ 311 312 memset(priv->tx_ring[q], 0, tx_ring_size); 313 /* Build TX ring buffer */ 314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 315 i++, tx_desc++) { 316 tx_desc->die_dt = DT_EEMPTY; 317 if (num_tx_desc > 1) { 318 tx_desc++; 319 tx_desc->die_dt = DT_EEMPTY; 320 } 321 } 322 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 323 tx_desc->die_dt = DT_LINKFIX; /* type */ 324 325 /* RX descriptor base address for best effort */ 326 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 327 desc->die_dt = DT_LINKFIX; /* type */ 328 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 329 330 /* TX descriptor base address for best effort */ 331 desc = &priv->desc_bat[q]; 332 desc->die_dt = DT_LINKFIX; /* type */ 333 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 334 } 335 336 /* Init skb and descriptor buffer for Ethernet AVB */ 337 static int ravb_ring_init(struct net_device *ndev, int q) 338 { 339 struct ravb_private *priv = netdev_priv(ndev); 340 int num_tx_desc = priv->num_tx_desc; 341 struct sk_buff *skb; 342 int ring_size; 343 int i; 344 345 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) + 346 ETH_HLEN + VLAN_HLEN + sizeof(__sum16); 347 348 /* Allocate RX and TX skb rings */ 349 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 350 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 351 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 352 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 353 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 354 goto error; 355 356 for (i = 0; i < priv->num_rx_ring[q]; i++) { 357 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1); 358 if (!skb) 359 goto error; 360 ravb_set_buffer_align(skb); 361 priv->rx_skb[q][i] = skb; 362 } 363 364 if (num_tx_desc > 1) { 365 /* Allocate rings for the aligned buffers */ 366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 367 DPTR_ALIGN - 1, GFP_KERNEL); 368 if (!priv->tx_align[q]) 369 goto error; 370 } 371 372 /* Allocate all RX descriptors. */ 373 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 374 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 375 &priv->rx_desc_dma[q], 376 GFP_KERNEL); 377 if (!priv->rx_ring[q]) 378 goto error; 379 380 priv->dirty_rx[q] = 0; 381 382 /* Allocate all TX descriptors. */ 383 ring_size = sizeof(struct ravb_tx_desc) * 384 (priv->num_tx_ring[q] * num_tx_desc + 1); 385 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 386 &priv->tx_desc_dma[q], 387 GFP_KERNEL); 388 if (!priv->tx_ring[q]) 389 goto error; 390 391 return 0; 392 393 error: 394 ravb_ring_free(ndev, q); 395 396 return -ENOMEM; 397 } 398 399 /* E-MAC init function */ 400 static void ravb_emac_init(struct net_device *ndev) 401 { 402 /* Receive frame limit set register */ 403 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 404 405 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 406 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 407 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 408 ECMR_TE | ECMR_RE, ECMR); 409 410 ravb_set_rate(ndev); 411 412 /* Set MAC address */ 413 ravb_write(ndev, 414 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 415 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 416 ravb_write(ndev, 417 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 418 419 /* E-MAC status register clear */ 420 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 421 422 /* E-MAC interrupt enable register */ 423 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 424 } 425 426 /* Device init function for Ethernet AVB */ 427 static int ravb_dmac_init(struct net_device *ndev) 428 { 429 struct ravb_private *priv = netdev_priv(ndev); 430 int error; 431 432 /* Set CONFIG mode */ 433 error = ravb_config(ndev); 434 if (error) 435 return error; 436 437 error = ravb_ring_init(ndev, RAVB_BE); 438 if (error) 439 return error; 440 error = ravb_ring_init(ndev, RAVB_NC); 441 if (error) { 442 ravb_ring_free(ndev, RAVB_BE); 443 return error; 444 } 445 446 /* Descriptor format */ 447 ravb_ring_format(ndev, RAVB_BE); 448 ravb_ring_format(ndev, RAVB_NC); 449 450 #if defined(__LITTLE_ENDIAN) 451 ravb_modify(ndev, CCC, CCC_BOC, 0); 452 #else 453 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 454 #endif 455 456 /* Set AVB RX */ 457 ravb_write(ndev, 458 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 459 460 /* Set FIFO size */ 461 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 462 463 /* Timestamp enable */ 464 ravb_write(ndev, TCCR_TFEN, TCCR); 465 466 /* Interrupt init: */ 467 if (priv->chip_id == RCAR_GEN3) { 468 /* Clear DIL.DPLx */ 469 ravb_write(ndev, 0, DIL); 470 /* Set queue specific interrupt */ 471 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 472 } 473 /* Frame receive */ 474 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 475 /* Disable FIFO full warning */ 476 ravb_write(ndev, 0, RIC1); 477 /* Receive FIFO full error, descriptor empty */ 478 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 479 /* Frame transmitted, timestamp FIFO updated */ 480 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 481 482 /* Setting the control will start the AVB-DMAC process. */ 483 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 484 485 return 0; 486 } 487 488 static void ravb_get_tx_tstamp(struct net_device *ndev) 489 { 490 struct ravb_private *priv = netdev_priv(ndev); 491 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 492 struct skb_shared_hwtstamps shhwtstamps; 493 struct sk_buff *skb; 494 struct timespec64 ts; 495 u16 tag, tfa_tag; 496 int count; 497 u32 tfa2; 498 499 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 500 while (count--) { 501 tfa2 = ravb_read(ndev, TFA2); 502 tfa_tag = (tfa2 & TFA2_TST) >> 16; 503 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 504 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 505 ravb_read(ndev, TFA1); 506 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 507 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 508 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 509 list) { 510 skb = ts_skb->skb; 511 tag = ts_skb->tag; 512 list_del(&ts_skb->list); 513 kfree(ts_skb); 514 if (tag == tfa_tag) { 515 skb_tstamp_tx(skb, &shhwtstamps); 516 break; 517 } 518 } 519 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 520 } 521 } 522 523 static void ravb_rx_csum(struct sk_buff *skb) 524 { 525 u8 *hw_csum; 526 527 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 528 * appended to packet data 529 */ 530 if (unlikely(skb->len < sizeof(__sum16))) 531 return; 532 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 533 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 534 skb->ip_summed = CHECKSUM_COMPLETE; 535 skb_trim(skb, skb->len - sizeof(__sum16)); 536 } 537 538 /* Packet receive function for Ethernet AVB */ 539 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 540 { 541 struct ravb_private *priv = netdev_priv(ndev); 542 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 543 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 544 priv->cur_rx[q]; 545 struct net_device_stats *stats = &priv->stats[q]; 546 struct ravb_ex_rx_desc *desc; 547 struct sk_buff *skb; 548 dma_addr_t dma_addr; 549 struct timespec64 ts; 550 u8 desc_status; 551 u16 pkt_len; 552 int limit; 553 554 boguscnt = min(boguscnt, *quota); 555 limit = boguscnt; 556 desc = &priv->rx_ring[q][entry]; 557 while (desc->die_dt != DT_FEMPTY) { 558 /* Descriptor type must be checked before all other reads */ 559 dma_rmb(); 560 desc_status = desc->msc; 561 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 562 563 if (--boguscnt < 0) 564 break; 565 566 /* We use 0-byte descriptors to mark the DMA mapping errors */ 567 if (!pkt_len) 568 continue; 569 570 if (desc_status & MSC_MC) 571 stats->multicast++; 572 573 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 574 MSC_CEEF)) { 575 stats->rx_errors++; 576 if (desc_status & MSC_CRC) 577 stats->rx_crc_errors++; 578 if (desc_status & MSC_RFE) 579 stats->rx_frame_errors++; 580 if (desc_status & (MSC_RTLF | MSC_RTSF)) 581 stats->rx_length_errors++; 582 if (desc_status & MSC_CEEF) 583 stats->rx_missed_errors++; 584 } else { 585 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 586 587 skb = priv->rx_skb[q][entry]; 588 priv->rx_skb[q][entry] = NULL; 589 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 590 priv->rx_buf_sz, 591 DMA_FROM_DEVICE); 592 get_ts &= (q == RAVB_NC) ? 593 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 594 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 595 if (get_ts) { 596 struct skb_shared_hwtstamps *shhwtstamps; 597 598 shhwtstamps = skb_hwtstamps(skb); 599 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 600 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 601 32) | le32_to_cpu(desc->ts_sl); 602 ts.tv_nsec = le32_to_cpu(desc->ts_n); 603 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 604 } 605 606 skb_put(skb, pkt_len); 607 skb->protocol = eth_type_trans(skb, ndev); 608 if (ndev->features & NETIF_F_RXCSUM) 609 ravb_rx_csum(skb); 610 napi_gro_receive(&priv->napi[q], skb); 611 stats->rx_packets++; 612 stats->rx_bytes += pkt_len; 613 } 614 615 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 616 desc = &priv->rx_ring[q][entry]; 617 } 618 619 /* Refill the RX ring buffers. */ 620 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 621 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 622 desc = &priv->rx_ring[q][entry]; 623 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 624 625 if (!priv->rx_skb[q][entry]) { 626 skb = netdev_alloc_skb(ndev, 627 priv->rx_buf_sz + 628 RAVB_ALIGN - 1); 629 if (!skb) 630 break; /* Better luck next round. */ 631 ravb_set_buffer_align(skb); 632 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 633 le16_to_cpu(desc->ds_cc), 634 DMA_FROM_DEVICE); 635 skb_checksum_none_assert(skb); 636 /* We just set the data size to 0 for a failed mapping 637 * which should prevent DMA from happening... 638 */ 639 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 640 desc->ds_cc = cpu_to_le16(0); 641 desc->dptr = cpu_to_le32(dma_addr); 642 priv->rx_skb[q][entry] = skb; 643 } 644 /* Descriptor type must be set after all the above writes */ 645 dma_wmb(); 646 desc->die_dt = DT_FEMPTY; 647 } 648 649 *quota -= limit - (++boguscnt); 650 651 return boguscnt <= 0; 652 } 653 654 static void ravb_rcv_snd_disable(struct net_device *ndev) 655 { 656 /* Disable TX and RX */ 657 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 658 } 659 660 static void ravb_rcv_snd_enable(struct net_device *ndev) 661 { 662 /* Enable TX and RX */ 663 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 664 } 665 666 /* function for waiting dma process finished */ 667 static int ravb_stop_dma(struct net_device *ndev) 668 { 669 int error; 670 671 /* Wait for stopping the hardware TX process */ 672 error = ravb_wait(ndev, TCCR, 673 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 674 if (error) 675 return error; 676 677 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 678 0); 679 if (error) 680 return error; 681 682 /* Stop the E-MAC's RX/TX processes. */ 683 ravb_rcv_snd_disable(ndev); 684 685 /* Wait for stopping the RX DMA process */ 686 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 687 if (error) 688 return error; 689 690 /* Stop AVB-DMAC process */ 691 return ravb_config(ndev); 692 } 693 694 /* E-MAC interrupt handler */ 695 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 696 { 697 struct ravb_private *priv = netdev_priv(ndev); 698 u32 ecsr, psr; 699 700 ecsr = ravb_read(ndev, ECSR); 701 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 702 703 if (ecsr & ECSR_MPD) 704 pm_wakeup_event(&priv->pdev->dev, 0); 705 if (ecsr & ECSR_ICD) 706 ndev->stats.tx_carrier_errors++; 707 if (ecsr & ECSR_LCHNG) { 708 /* Link changed */ 709 if (priv->no_avb_link) 710 return; 711 psr = ravb_read(ndev, PSR); 712 if (priv->avb_link_active_low) 713 psr ^= PSR_LMON; 714 if (!(psr & PSR_LMON)) { 715 /* DIsable RX and TX */ 716 ravb_rcv_snd_disable(ndev); 717 } else { 718 /* Enable RX and TX */ 719 ravb_rcv_snd_enable(ndev); 720 } 721 } 722 } 723 724 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 725 { 726 struct net_device *ndev = dev_id; 727 struct ravb_private *priv = netdev_priv(ndev); 728 729 spin_lock(&priv->lock); 730 ravb_emac_interrupt_unlocked(ndev); 731 mmiowb(); 732 spin_unlock(&priv->lock); 733 return IRQ_HANDLED; 734 } 735 736 /* Error interrupt handler */ 737 static void ravb_error_interrupt(struct net_device *ndev) 738 { 739 struct ravb_private *priv = netdev_priv(ndev); 740 u32 eis, ris2; 741 742 eis = ravb_read(ndev, EIS); 743 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 744 if (eis & EIS_QFS) { 745 ris2 = ravb_read(ndev, RIS2); 746 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 747 RIS2); 748 749 /* Receive Descriptor Empty int */ 750 if (ris2 & RIS2_QFF0) 751 priv->stats[RAVB_BE].rx_over_errors++; 752 753 /* Receive Descriptor Empty int */ 754 if (ris2 & RIS2_QFF1) 755 priv->stats[RAVB_NC].rx_over_errors++; 756 757 /* Receive FIFO Overflow int */ 758 if (ris2 & RIS2_RFFF) 759 priv->rx_fifo_errors++; 760 } 761 } 762 763 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 764 { 765 struct ravb_private *priv = netdev_priv(ndev); 766 u32 ris0 = ravb_read(ndev, RIS0); 767 u32 ric0 = ravb_read(ndev, RIC0); 768 u32 tis = ravb_read(ndev, TIS); 769 u32 tic = ravb_read(ndev, TIC); 770 771 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 772 if (napi_schedule_prep(&priv->napi[q])) { 773 /* Mask RX and TX interrupts */ 774 if (priv->chip_id == RCAR_GEN2) { 775 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 776 ravb_write(ndev, tic & ~BIT(q), TIC); 777 } else { 778 ravb_write(ndev, BIT(q), RID0); 779 ravb_write(ndev, BIT(q), TID); 780 } 781 __napi_schedule(&priv->napi[q]); 782 } else { 783 netdev_warn(ndev, 784 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 785 ris0, ric0); 786 netdev_warn(ndev, 787 " tx status 0x%08x, tx mask 0x%08x.\n", 788 tis, tic); 789 } 790 return true; 791 } 792 return false; 793 } 794 795 static bool ravb_timestamp_interrupt(struct net_device *ndev) 796 { 797 u32 tis = ravb_read(ndev, TIS); 798 799 if (tis & TIS_TFUF) { 800 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 801 ravb_get_tx_tstamp(ndev); 802 return true; 803 } 804 return false; 805 } 806 807 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 808 { 809 struct net_device *ndev = dev_id; 810 struct ravb_private *priv = netdev_priv(ndev); 811 irqreturn_t result = IRQ_NONE; 812 u32 iss; 813 814 spin_lock(&priv->lock); 815 /* Get interrupt status */ 816 iss = ravb_read(ndev, ISS); 817 818 /* Received and transmitted interrupts */ 819 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 820 int q; 821 822 /* Timestamp updated */ 823 if (ravb_timestamp_interrupt(ndev)) 824 result = IRQ_HANDLED; 825 826 /* Network control and best effort queue RX/TX */ 827 for (q = RAVB_NC; q >= RAVB_BE; q--) { 828 if (ravb_queue_interrupt(ndev, q)) 829 result = IRQ_HANDLED; 830 } 831 } 832 833 /* E-MAC status summary */ 834 if (iss & ISS_MS) { 835 ravb_emac_interrupt_unlocked(ndev); 836 result = IRQ_HANDLED; 837 } 838 839 /* Error status summary */ 840 if (iss & ISS_ES) { 841 ravb_error_interrupt(ndev); 842 result = IRQ_HANDLED; 843 } 844 845 /* gPTP interrupt status summary */ 846 if (iss & ISS_CGIS) { 847 ravb_ptp_interrupt(ndev); 848 result = IRQ_HANDLED; 849 } 850 851 mmiowb(); 852 spin_unlock(&priv->lock); 853 return result; 854 } 855 856 /* Timestamp/Error/gPTP interrupt handler */ 857 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 858 { 859 struct net_device *ndev = dev_id; 860 struct ravb_private *priv = netdev_priv(ndev); 861 irqreturn_t result = IRQ_NONE; 862 u32 iss; 863 864 spin_lock(&priv->lock); 865 /* Get interrupt status */ 866 iss = ravb_read(ndev, ISS); 867 868 /* Timestamp updated */ 869 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 870 result = IRQ_HANDLED; 871 872 /* Error status summary */ 873 if (iss & ISS_ES) { 874 ravb_error_interrupt(ndev); 875 result = IRQ_HANDLED; 876 } 877 878 /* gPTP interrupt status summary */ 879 if (iss & ISS_CGIS) { 880 ravb_ptp_interrupt(ndev); 881 result = IRQ_HANDLED; 882 } 883 884 mmiowb(); 885 spin_unlock(&priv->lock); 886 return result; 887 } 888 889 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 890 { 891 struct net_device *ndev = dev_id; 892 struct ravb_private *priv = netdev_priv(ndev); 893 irqreturn_t result = IRQ_NONE; 894 895 spin_lock(&priv->lock); 896 897 /* Network control/Best effort queue RX/TX */ 898 if (ravb_queue_interrupt(ndev, q)) 899 result = IRQ_HANDLED; 900 901 mmiowb(); 902 spin_unlock(&priv->lock); 903 return result; 904 } 905 906 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 907 { 908 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 909 } 910 911 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 912 { 913 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 914 } 915 916 static int ravb_poll(struct napi_struct *napi, int budget) 917 { 918 struct net_device *ndev = napi->dev; 919 struct ravb_private *priv = netdev_priv(ndev); 920 unsigned long flags; 921 int q = napi - priv->napi; 922 int mask = BIT(q); 923 int quota = budget; 924 u32 ris0, tis; 925 926 for (;;) { 927 tis = ravb_read(ndev, TIS); 928 ris0 = ravb_read(ndev, RIS0); 929 if (!((ris0 & mask) || (tis & mask))) 930 break; 931 932 /* Processing RX Descriptor Ring */ 933 if (ris0 & mask) { 934 /* Clear RX interrupt */ 935 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 936 if (ravb_rx(ndev, "a, q)) 937 goto out; 938 } 939 /* Processing TX Descriptor Ring */ 940 if (tis & mask) { 941 spin_lock_irqsave(&priv->lock, flags); 942 /* Clear TX interrupt */ 943 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 944 ravb_tx_free(ndev, q, true); 945 netif_wake_subqueue(ndev, q); 946 mmiowb(); 947 spin_unlock_irqrestore(&priv->lock, flags); 948 } 949 } 950 951 napi_complete(napi); 952 953 /* Re-enable RX/TX interrupts */ 954 spin_lock_irqsave(&priv->lock, flags); 955 if (priv->chip_id == RCAR_GEN2) { 956 ravb_modify(ndev, RIC0, mask, mask); 957 ravb_modify(ndev, TIC, mask, mask); 958 } else { 959 ravb_write(ndev, mask, RIE0); 960 ravb_write(ndev, mask, TIE); 961 } 962 mmiowb(); 963 spin_unlock_irqrestore(&priv->lock, flags); 964 965 /* Receive error message handling */ 966 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 967 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 968 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 969 ndev->stats.rx_over_errors = priv->rx_over_errors; 970 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 971 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 972 out: 973 return budget - quota; 974 } 975 976 /* PHY state control function */ 977 static void ravb_adjust_link(struct net_device *ndev) 978 { 979 struct ravb_private *priv = netdev_priv(ndev); 980 struct phy_device *phydev = ndev->phydev; 981 bool new_state = false; 982 unsigned long flags; 983 984 spin_lock_irqsave(&priv->lock, flags); 985 986 /* Disable TX and RX right over here, if E-MAC change is ignored */ 987 if (priv->no_avb_link) 988 ravb_rcv_snd_disable(ndev); 989 990 if (phydev->link) { 991 if (phydev->speed != priv->speed) { 992 new_state = true; 993 priv->speed = phydev->speed; 994 ravb_set_rate(ndev); 995 } 996 if (!priv->link) { 997 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 998 new_state = true; 999 priv->link = phydev->link; 1000 } 1001 } else if (priv->link) { 1002 new_state = true; 1003 priv->link = 0; 1004 priv->speed = 0; 1005 } 1006 1007 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1008 if (priv->no_avb_link && phydev->link) 1009 ravb_rcv_snd_enable(ndev); 1010 1011 mmiowb(); 1012 spin_unlock_irqrestore(&priv->lock, flags); 1013 1014 if (new_state && netif_msg_link(priv)) 1015 phy_print_status(phydev); 1016 } 1017 1018 static const struct soc_device_attribute r8a7795es10[] = { 1019 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1020 { /* sentinel */ } 1021 }; 1022 1023 /* PHY init function */ 1024 static int ravb_phy_init(struct net_device *ndev) 1025 { 1026 struct device_node *np = ndev->dev.parent->of_node; 1027 struct ravb_private *priv = netdev_priv(ndev); 1028 struct phy_device *phydev; 1029 struct device_node *pn; 1030 int err; 1031 1032 priv->link = 0; 1033 priv->speed = 0; 1034 1035 /* Try connecting to PHY */ 1036 pn = of_parse_phandle(np, "phy-handle", 0); 1037 if (!pn) { 1038 /* In the case of a fixed PHY, the DT node associated 1039 * to the PHY is the Ethernet MAC DT node. 1040 */ 1041 if (of_phy_is_fixed_link(np)) { 1042 err = of_phy_register_fixed_link(np); 1043 if (err) 1044 return err; 1045 } 1046 pn = of_node_get(np); 1047 } 1048 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1049 priv->phy_interface); 1050 of_node_put(pn); 1051 if (!phydev) { 1052 netdev_err(ndev, "failed to connect PHY\n"); 1053 err = -ENOENT; 1054 goto err_deregister_fixed_link; 1055 } 1056 1057 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1058 * at this time. 1059 */ 1060 if (soc_device_match(r8a7795es10)) { 1061 err = phy_set_max_speed(phydev, SPEED_100); 1062 if (err) { 1063 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1064 goto err_phy_disconnect; 1065 } 1066 1067 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1068 } 1069 1070 /* 10BASE, Pause and Asym Pause is not supported */ 1071 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1072 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1073 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1074 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1075 1076 /* Half Duplex is not supported */ 1077 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1078 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1079 1080 phy_attached_info(phydev); 1081 1082 return 0; 1083 1084 err_phy_disconnect: 1085 phy_disconnect(phydev); 1086 err_deregister_fixed_link: 1087 if (of_phy_is_fixed_link(np)) 1088 of_phy_deregister_fixed_link(np); 1089 1090 return err; 1091 } 1092 1093 /* PHY control start function */ 1094 static int ravb_phy_start(struct net_device *ndev) 1095 { 1096 int error; 1097 1098 error = ravb_phy_init(ndev); 1099 if (error) 1100 return error; 1101 1102 phy_start(ndev->phydev); 1103 1104 return 0; 1105 } 1106 1107 static u32 ravb_get_msglevel(struct net_device *ndev) 1108 { 1109 struct ravb_private *priv = netdev_priv(ndev); 1110 1111 return priv->msg_enable; 1112 } 1113 1114 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1115 { 1116 struct ravb_private *priv = netdev_priv(ndev); 1117 1118 priv->msg_enable = value; 1119 } 1120 1121 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1122 "rx_queue_0_current", 1123 "tx_queue_0_current", 1124 "rx_queue_0_dirty", 1125 "tx_queue_0_dirty", 1126 "rx_queue_0_packets", 1127 "tx_queue_0_packets", 1128 "rx_queue_0_bytes", 1129 "tx_queue_0_bytes", 1130 "rx_queue_0_mcast_packets", 1131 "rx_queue_0_errors", 1132 "rx_queue_0_crc_errors", 1133 "rx_queue_0_frame_errors", 1134 "rx_queue_0_length_errors", 1135 "rx_queue_0_missed_errors", 1136 "rx_queue_0_over_errors", 1137 1138 "rx_queue_1_current", 1139 "tx_queue_1_current", 1140 "rx_queue_1_dirty", 1141 "tx_queue_1_dirty", 1142 "rx_queue_1_packets", 1143 "tx_queue_1_packets", 1144 "rx_queue_1_bytes", 1145 "tx_queue_1_bytes", 1146 "rx_queue_1_mcast_packets", 1147 "rx_queue_1_errors", 1148 "rx_queue_1_crc_errors", 1149 "rx_queue_1_frame_errors", 1150 "rx_queue_1_length_errors", 1151 "rx_queue_1_missed_errors", 1152 "rx_queue_1_over_errors", 1153 }; 1154 1155 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1156 1157 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1158 { 1159 switch (sset) { 1160 case ETH_SS_STATS: 1161 return RAVB_STATS_LEN; 1162 default: 1163 return -EOPNOTSUPP; 1164 } 1165 } 1166 1167 static void ravb_get_ethtool_stats(struct net_device *ndev, 1168 struct ethtool_stats *estats, u64 *data) 1169 { 1170 struct ravb_private *priv = netdev_priv(ndev); 1171 int i = 0; 1172 int q; 1173 1174 /* Device-specific stats */ 1175 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1176 struct net_device_stats *stats = &priv->stats[q]; 1177 1178 data[i++] = priv->cur_rx[q]; 1179 data[i++] = priv->cur_tx[q]; 1180 data[i++] = priv->dirty_rx[q]; 1181 data[i++] = priv->dirty_tx[q]; 1182 data[i++] = stats->rx_packets; 1183 data[i++] = stats->tx_packets; 1184 data[i++] = stats->rx_bytes; 1185 data[i++] = stats->tx_bytes; 1186 data[i++] = stats->multicast; 1187 data[i++] = stats->rx_errors; 1188 data[i++] = stats->rx_crc_errors; 1189 data[i++] = stats->rx_frame_errors; 1190 data[i++] = stats->rx_length_errors; 1191 data[i++] = stats->rx_missed_errors; 1192 data[i++] = stats->rx_over_errors; 1193 } 1194 } 1195 1196 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1197 { 1198 switch (stringset) { 1199 case ETH_SS_STATS: 1200 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1201 break; 1202 } 1203 } 1204 1205 static void ravb_get_ringparam(struct net_device *ndev, 1206 struct ethtool_ringparam *ring) 1207 { 1208 struct ravb_private *priv = netdev_priv(ndev); 1209 1210 ring->rx_max_pending = BE_RX_RING_MAX; 1211 ring->tx_max_pending = BE_TX_RING_MAX; 1212 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1213 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1214 } 1215 1216 static int ravb_set_ringparam(struct net_device *ndev, 1217 struct ethtool_ringparam *ring) 1218 { 1219 struct ravb_private *priv = netdev_priv(ndev); 1220 int error; 1221 1222 if (ring->tx_pending > BE_TX_RING_MAX || 1223 ring->rx_pending > BE_RX_RING_MAX || 1224 ring->tx_pending < BE_TX_RING_MIN || 1225 ring->rx_pending < BE_RX_RING_MIN) 1226 return -EINVAL; 1227 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1228 return -EINVAL; 1229 1230 if (netif_running(ndev)) { 1231 netif_device_detach(ndev); 1232 /* Stop PTP Clock driver */ 1233 if (priv->chip_id == RCAR_GEN2) 1234 ravb_ptp_stop(ndev); 1235 /* Wait for DMA stopping */ 1236 error = ravb_stop_dma(ndev); 1237 if (error) { 1238 netdev_err(ndev, 1239 "cannot set ringparam! Any AVB processes are still running?\n"); 1240 return error; 1241 } 1242 synchronize_irq(ndev->irq); 1243 1244 /* Free all the skb's in the RX queue and the DMA buffers. */ 1245 ravb_ring_free(ndev, RAVB_BE); 1246 ravb_ring_free(ndev, RAVB_NC); 1247 } 1248 1249 /* Set new parameters */ 1250 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1251 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1252 1253 if (netif_running(ndev)) { 1254 error = ravb_dmac_init(ndev); 1255 if (error) { 1256 netdev_err(ndev, 1257 "%s: ravb_dmac_init() failed, error %d\n", 1258 __func__, error); 1259 return error; 1260 } 1261 1262 ravb_emac_init(ndev); 1263 1264 /* Initialise PTP Clock driver */ 1265 if (priv->chip_id == RCAR_GEN2) 1266 ravb_ptp_init(ndev, priv->pdev); 1267 1268 netif_device_attach(ndev); 1269 } 1270 1271 return 0; 1272 } 1273 1274 static int ravb_get_ts_info(struct net_device *ndev, 1275 struct ethtool_ts_info *info) 1276 { 1277 struct ravb_private *priv = netdev_priv(ndev); 1278 1279 info->so_timestamping = 1280 SOF_TIMESTAMPING_TX_SOFTWARE | 1281 SOF_TIMESTAMPING_RX_SOFTWARE | 1282 SOF_TIMESTAMPING_SOFTWARE | 1283 SOF_TIMESTAMPING_TX_HARDWARE | 1284 SOF_TIMESTAMPING_RX_HARDWARE | 1285 SOF_TIMESTAMPING_RAW_HARDWARE; 1286 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1287 info->rx_filters = 1288 (1 << HWTSTAMP_FILTER_NONE) | 1289 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1290 (1 << HWTSTAMP_FILTER_ALL); 1291 info->phc_index = ptp_clock_index(priv->ptp.clock); 1292 1293 return 0; 1294 } 1295 1296 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1297 { 1298 struct ravb_private *priv = netdev_priv(ndev); 1299 1300 wol->supported = WAKE_MAGIC; 1301 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1302 } 1303 1304 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1305 { 1306 struct ravb_private *priv = netdev_priv(ndev); 1307 1308 if (wol->wolopts & ~WAKE_MAGIC) 1309 return -EOPNOTSUPP; 1310 1311 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1312 1313 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1314 1315 return 0; 1316 } 1317 1318 static const struct ethtool_ops ravb_ethtool_ops = { 1319 .nway_reset = phy_ethtool_nway_reset, 1320 .get_msglevel = ravb_get_msglevel, 1321 .set_msglevel = ravb_set_msglevel, 1322 .get_link = ethtool_op_get_link, 1323 .get_strings = ravb_get_strings, 1324 .get_ethtool_stats = ravb_get_ethtool_stats, 1325 .get_sset_count = ravb_get_sset_count, 1326 .get_ringparam = ravb_get_ringparam, 1327 .set_ringparam = ravb_set_ringparam, 1328 .get_ts_info = ravb_get_ts_info, 1329 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1330 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1331 .get_wol = ravb_get_wol, 1332 .set_wol = ravb_set_wol, 1333 }; 1334 1335 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1336 struct net_device *ndev, struct device *dev, 1337 const char *ch) 1338 { 1339 char *name; 1340 int error; 1341 1342 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1343 if (!name) 1344 return -ENOMEM; 1345 error = request_irq(irq, handler, 0, name, ndev); 1346 if (error) 1347 netdev_err(ndev, "cannot request IRQ %s\n", name); 1348 1349 return error; 1350 } 1351 1352 /* Network device open function for Ethernet AVB */ 1353 static int ravb_open(struct net_device *ndev) 1354 { 1355 struct ravb_private *priv = netdev_priv(ndev); 1356 struct platform_device *pdev = priv->pdev; 1357 struct device *dev = &pdev->dev; 1358 int error; 1359 1360 napi_enable(&priv->napi[RAVB_BE]); 1361 napi_enable(&priv->napi[RAVB_NC]); 1362 1363 if (priv->chip_id == RCAR_GEN2) { 1364 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1365 ndev->name, ndev); 1366 if (error) { 1367 netdev_err(ndev, "cannot request IRQ\n"); 1368 goto out_napi_off; 1369 } 1370 } else { 1371 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1372 dev, "ch22:multi"); 1373 if (error) 1374 goto out_napi_off; 1375 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1376 dev, "ch24:emac"); 1377 if (error) 1378 goto out_free_irq; 1379 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1380 ndev, dev, "ch0:rx_be"); 1381 if (error) 1382 goto out_free_irq_emac; 1383 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1384 ndev, dev, "ch18:tx_be"); 1385 if (error) 1386 goto out_free_irq_be_rx; 1387 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1388 ndev, dev, "ch1:rx_nc"); 1389 if (error) 1390 goto out_free_irq_be_tx; 1391 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1392 ndev, dev, "ch19:tx_nc"); 1393 if (error) 1394 goto out_free_irq_nc_rx; 1395 } 1396 1397 /* Device init */ 1398 error = ravb_dmac_init(ndev); 1399 if (error) 1400 goto out_free_irq_nc_tx; 1401 ravb_emac_init(ndev); 1402 1403 /* Initialise PTP Clock driver */ 1404 if (priv->chip_id == RCAR_GEN2) 1405 ravb_ptp_init(ndev, priv->pdev); 1406 1407 netif_tx_start_all_queues(ndev); 1408 1409 /* PHY control start */ 1410 error = ravb_phy_start(ndev); 1411 if (error) 1412 goto out_ptp_stop; 1413 1414 return 0; 1415 1416 out_ptp_stop: 1417 /* Stop PTP Clock driver */ 1418 if (priv->chip_id == RCAR_GEN2) 1419 ravb_ptp_stop(ndev); 1420 out_free_irq_nc_tx: 1421 if (priv->chip_id == RCAR_GEN2) 1422 goto out_free_irq; 1423 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1424 out_free_irq_nc_rx: 1425 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1426 out_free_irq_be_tx: 1427 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1428 out_free_irq_be_rx: 1429 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1430 out_free_irq_emac: 1431 free_irq(priv->emac_irq, ndev); 1432 out_free_irq: 1433 free_irq(ndev->irq, ndev); 1434 out_napi_off: 1435 napi_disable(&priv->napi[RAVB_NC]); 1436 napi_disable(&priv->napi[RAVB_BE]); 1437 return error; 1438 } 1439 1440 /* Timeout function for Ethernet AVB */ 1441 static void ravb_tx_timeout(struct net_device *ndev) 1442 { 1443 struct ravb_private *priv = netdev_priv(ndev); 1444 1445 netif_err(priv, tx_err, ndev, 1446 "transmit timed out, status %08x, resetting...\n", 1447 ravb_read(ndev, ISS)); 1448 1449 /* tx_errors count up */ 1450 ndev->stats.tx_errors++; 1451 1452 schedule_work(&priv->work); 1453 } 1454 1455 static void ravb_tx_timeout_work(struct work_struct *work) 1456 { 1457 struct ravb_private *priv = container_of(work, struct ravb_private, 1458 work); 1459 struct net_device *ndev = priv->ndev; 1460 1461 netif_tx_stop_all_queues(ndev); 1462 1463 /* Stop PTP Clock driver */ 1464 if (priv->chip_id == RCAR_GEN2) 1465 ravb_ptp_stop(ndev); 1466 1467 /* Wait for DMA stopping */ 1468 ravb_stop_dma(ndev); 1469 1470 ravb_ring_free(ndev, RAVB_BE); 1471 ravb_ring_free(ndev, RAVB_NC); 1472 1473 /* Device init */ 1474 ravb_dmac_init(ndev); 1475 ravb_emac_init(ndev); 1476 1477 /* Initialise PTP Clock driver */ 1478 if (priv->chip_id == RCAR_GEN2) 1479 ravb_ptp_init(ndev, priv->pdev); 1480 1481 netif_tx_start_all_queues(ndev); 1482 } 1483 1484 /* Packet transmit function for Ethernet AVB */ 1485 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1486 { 1487 struct ravb_private *priv = netdev_priv(ndev); 1488 int num_tx_desc = priv->num_tx_desc; 1489 u16 q = skb_get_queue_mapping(skb); 1490 struct ravb_tstamp_skb *ts_skb; 1491 struct ravb_tx_desc *desc; 1492 unsigned long flags; 1493 u32 dma_addr; 1494 void *buffer; 1495 u32 entry; 1496 u32 len; 1497 1498 spin_lock_irqsave(&priv->lock, flags); 1499 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1500 num_tx_desc) { 1501 netif_err(priv, tx_queued, ndev, 1502 "still transmitting with the full ring!\n"); 1503 netif_stop_subqueue(ndev, q); 1504 spin_unlock_irqrestore(&priv->lock, flags); 1505 return NETDEV_TX_BUSY; 1506 } 1507 1508 if (skb_put_padto(skb, ETH_ZLEN)) 1509 goto exit; 1510 1511 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1512 priv->tx_skb[q][entry / num_tx_desc] = skb; 1513 1514 if (num_tx_desc > 1) { 1515 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1516 entry / num_tx_desc * DPTR_ALIGN; 1517 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1518 1519 /* Zero length DMA descriptors are problematic as they seem 1520 * to terminate DMA transfers. Avoid them by simply using a 1521 * length of DPTR_ALIGN (4) when skb data is aligned to 1522 * DPTR_ALIGN. 1523 * 1524 * As skb is guaranteed to have at least ETH_ZLEN (60) 1525 * bytes of data by the call to skb_put_padto() above this 1526 * is safe with respect to both the length of the first DMA 1527 * descriptor (len) overflowing the available data and the 1528 * length of the second DMA descriptor (skb->len - len) 1529 * being negative. 1530 */ 1531 if (len == 0) 1532 len = DPTR_ALIGN; 1533 1534 memcpy(buffer, skb->data, len); 1535 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1536 DMA_TO_DEVICE); 1537 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1538 goto drop; 1539 1540 desc = &priv->tx_ring[q][entry]; 1541 desc->ds_tagl = cpu_to_le16(len); 1542 desc->dptr = cpu_to_le32(dma_addr); 1543 1544 buffer = skb->data + len; 1545 len = skb->len - len; 1546 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1547 DMA_TO_DEVICE); 1548 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1549 goto unmap; 1550 1551 desc++; 1552 } else { 1553 desc = &priv->tx_ring[q][entry]; 1554 len = skb->len; 1555 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1556 DMA_TO_DEVICE); 1557 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1558 goto drop; 1559 } 1560 desc->ds_tagl = cpu_to_le16(len); 1561 desc->dptr = cpu_to_le32(dma_addr); 1562 1563 /* TX timestamp required */ 1564 if (q == RAVB_NC) { 1565 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1566 if (!ts_skb) { 1567 if (num_tx_desc > 1) { 1568 desc--; 1569 dma_unmap_single(ndev->dev.parent, dma_addr, 1570 len, DMA_TO_DEVICE); 1571 } 1572 goto unmap; 1573 } 1574 ts_skb->skb = skb; 1575 ts_skb->tag = priv->ts_skb_tag++; 1576 priv->ts_skb_tag &= 0x3ff; 1577 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1578 1579 /* TAG and timestamp required flag */ 1580 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1581 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1582 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1583 } 1584 1585 skb_tx_timestamp(skb); 1586 /* Descriptor type must be set after all the above writes */ 1587 dma_wmb(); 1588 if (num_tx_desc > 1) { 1589 desc->die_dt = DT_FEND; 1590 desc--; 1591 desc->die_dt = DT_FSTART; 1592 } else { 1593 desc->die_dt = DT_FSINGLE; 1594 } 1595 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1596 1597 priv->cur_tx[q] += num_tx_desc; 1598 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1599 (priv->num_tx_ring[q] - 1) * num_tx_desc && 1600 !ravb_tx_free(ndev, q, true)) 1601 netif_stop_subqueue(ndev, q); 1602 1603 exit: 1604 mmiowb(); 1605 spin_unlock_irqrestore(&priv->lock, flags); 1606 return NETDEV_TX_OK; 1607 1608 unmap: 1609 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1610 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1611 drop: 1612 dev_kfree_skb_any(skb); 1613 priv->tx_skb[q][entry / num_tx_desc] = NULL; 1614 goto exit; 1615 } 1616 1617 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1618 struct net_device *sb_dev, 1619 select_queue_fallback_t fallback) 1620 { 1621 /* If skb needs TX timestamp, it is handled in network control queue */ 1622 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1623 RAVB_BE; 1624 1625 } 1626 1627 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1628 { 1629 struct ravb_private *priv = netdev_priv(ndev); 1630 struct net_device_stats *nstats, *stats0, *stats1; 1631 1632 nstats = &ndev->stats; 1633 stats0 = &priv->stats[RAVB_BE]; 1634 stats1 = &priv->stats[RAVB_NC]; 1635 1636 nstats->tx_dropped += ravb_read(ndev, TROCR); 1637 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1638 nstats->collisions += ravb_read(ndev, CDCR); 1639 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1640 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1641 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1642 1643 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1644 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1645 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1646 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1647 1648 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1649 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1650 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1651 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1652 nstats->multicast = stats0->multicast + stats1->multicast; 1653 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1654 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1655 nstats->rx_frame_errors = 1656 stats0->rx_frame_errors + stats1->rx_frame_errors; 1657 nstats->rx_length_errors = 1658 stats0->rx_length_errors + stats1->rx_length_errors; 1659 nstats->rx_missed_errors = 1660 stats0->rx_missed_errors + stats1->rx_missed_errors; 1661 nstats->rx_over_errors = 1662 stats0->rx_over_errors + stats1->rx_over_errors; 1663 1664 return nstats; 1665 } 1666 1667 /* Update promiscuous bit */ 1668 static void ravb_set_rx_mode(struct net_device *ndev) 1669 { 1670 struct ravb_private *priv = netdev_priv(ndev); 1671 unsigned long flags; 1672 1673 spin_lock_irqsave(&priv->lock, flags); 1674 ravb_modify(ndev, ECMR, ECMR_PRM, 1675 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1676 mmiowb(); 1677 spin_unlock_irqrestore(&priv->lock, flags); 1678 } 1679 1680 /* Device close function for Ethernet AVB */ 1681 static int ravb_close(struct net_device *ndev) 1682 { 1683 struct device_node *np = ndev->dev.parent->of_node; 1684 struct ravb_private *priv = netdev_priv(ndev); 1685 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1686 1687 netif_tx_stop_all_queues(ndev); 1688 1689 /* Disable interrupts by clearing the interrupt masks. */ 1690 ravb_write(ndev, 0, RIC0); 1691 ravb_write(ndev, 0, RIC2); 1692 ravb_write(ndev, 0, TIC); 1693 1694 /* Stop PTP Clock driver */ 1695 if (priv->chip_id == RCAR_GEN2) 1696 ravb_ptp_stop(ndev); 1697 1698 /* Set the config mode to stop the AVB-DMAC's processes */ 1699 if (ravb_stop_dma(ndev) < 0) 1700 netdev_err(ndev, 1701 "device will be stopped after h/w processes are done.\n"); 1702 1703 /* Clear the timestamp list */ 1704 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1705 list_del(&ts_skb->list); 1706 kfree(ts_skb); 1707 } 1708 1709 /* PHY disconnect */ 1710 if (ndev->phydev) { 1711 phy_stop(ndev->phydev); 1712 phy_disconnect(ndev->phydev); 1713 if (of_phy_is_fixed_link(np)) 1714 of_phy_deregister_fixed_link(np); 1715 } 1716 1717 if (priv->chip_id != RCAR_GEN2) { 1718 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1719 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1720 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1721 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1722 free_irq(priv->emac_irq, ndev); 1723 } 1724 free_irq(ndev->irq, ndev); 1725 1726 napi_disable(&priv->napi[RAVB_NC]); 1727 napi_disable(&priv->napi[RAVB_BE]); 1728 1729 /* Free all the skb's in the RX queue and the DMA buffers. */ 1730 ravb_ring_free(ndev, RAVB_BE); 1731 ravb_ring_free(ndev, RAVB_NC); 1732 1733 return 0; 1734 } 1735 1736 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1737 { 1738 struct ravb_private *priv = netdev_priv(ndev); 1739 struct hwtstamp_config config; 1740 1741 config.flags = 0; 1742 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1743 HWTSTAMP_TX_OFF; 1744 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1745 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1746 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1747 config.rx_filter = HWTSTAMP_FILTER_ALL; 1748 else 1749 config.rx_filter = HWTSTAMP_FILTER_NONE; 1750 1751 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1752 -EFAULT : 0; 1753 } 1754 1755 /* Control hardware time stamping */ 1756 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1757 { 1758 struct ravb_private *priv = netdev_priv(ndev); 1759 struct hwtstamp_config config; 1760 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1761 u32 tstamp_tx_ctrl; 1762 1763 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1764 return -EFAULT; 1765 1766 /* Reserved for future extensions */ 1767 if (config.flags) 1768 return -EINVAL; 1769 1770 switch (config.tx_type) { 1771 case HWTSTAMP_TX_OFF: 1772 tstamp_tx_ctrl = 0; 1773 break; 1774 case HWTSTAMP_TX_ON: 1775 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1776 break; 1777 default: 1778 return -ERANGE; 1779 } 1780 1781 switch (config.rx_filter) { 1782 case HWTSTAMP_FILTER_NONE: 1783 tstamp_rx_ctrl = 0; 1784 break; 1785 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1786 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1787 break; 1788 default: 1789 config.rx_filter = HWTSTAMP_FILTER_ALL; 1790 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1791 } 1792 1793 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1794 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1795 1796 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1797 -EFAULT : 0; 1798 } 1799 1800 /* ioctl to device function */ 1801 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1802 { 1803 struct phy_device *phydev = ndev->phydev; 1804 1805 if (!netif_running(ndev)) 1806 return -EINVAL; 1807 1808 if (!phydev) 1809 return -ENODEV; 1810 1811 switch (cmd) { 1812 case SIOCGHWTSTAMP: 1813 return ravb_hwtstamp_get(ndev, req); 1814 case SIOCSHWTSTAMP: 1815 return ravb_hwtstamp_set(ndev, req); 1816 } 1817 1818 return phy_mii_ioctl(phydev, req, cmd); 1819 } 1820 1821 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1822 { 1823 if (netif_running(ndev)) 1824 return -EBUSY; 1825 1826 ndev->mtu = new_mtu; 1827 netdev_update_features(ndev); 1828 1829 return 0; 1830 } 1831 1832 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1833 { 1834 struct ravb_private *priv = netdev_priv(ndev); 1835 unsigned long flags; 1836 1837 spin_lock_irqsave(&priv->lock, flags); 1838 1839 /* Disable TX and RX */ 1840 ravb_rcv_snd_disable(ndev); 1841 1842 /* Modify RX Checksum setting */ 1843 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1844 1845 /* Enable TX and RX */ 1846 ravb_rcv_snd_enable(ndev); 1847 1848 spin_unlock_irqrestore(&priv->lock, flags); 1849 } 1850 1851 static int ravb_set_features(struct net_device *ndev, 1852 netdev_features_t features) 1853 { 1854 netdev_features_t changed = ndev->features ^ features; 1855 1856 if (changed & NETIF_F_RXCSUM) 1857 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1858 1859 ndev->features = features; 1860 1861 return 0; 1862 } 1863 1864 static const struct net_device_ops ravb_netdev_ops = { 1865 .ndo_open = ravb_open, 1866 .ndo_stop = ravb_close, 1867 .ndo_start_xmit = ravb_start_xmit, 1868 .ndo_select_queue = ravb_select_queue, 1869 .ndo_get_stats = ravb_get_stats, 1870 .ndo_set_rx_mode = ravb_set_rx_mode, 1871 .ndo_tx_timeout = ravb_tx_timeout, 1872 .ndo_do_ioctl = ravb_do_ioctl, 1873 .ndo_change_mtu = ravb_change_mtu, 1874 .ndo_validate_addr = eth_validate_addr, 1875 .ndo_set_mac_address = eth_mac_addr, 1876 .ndo_set_features = ravb_set_features, 1877 }; 1878 1879 /* MDIO bus init function */ 1880 static int ravb_mdio_init(struct ravb_private *priv) 1881 { 1882 struct platform_device *pdev = priv->pdev; 1883 struct device *dev = &pdev->dev; 1884 int error; 1885 1886 /* Bitbang init */ 1887 priv->mdiobb.ops = &bb_ops; 1888 1889 /* MII controller setting */ 1890 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1891 if (!priv->mii_bus) 1892 return -ENOMEM; 1893 1894 /* Hook up MII support for ethtool */ 1895 priv->mii_bus->name = "ravb_mii"; 1896 priv->mii_bus->parent = dev; 1897 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1898 pdev->name, pdev->id); 1899 1900 /* Register MDIO bus */ 1901 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1902 if (error) 1903 goto out_free_bus; 1904 1905 return 0; 1906 1907 out_free_bus: 1908 free_mdio_bitbang(priv->mii_bus); 1909 return error; 1910 } 1911 1912 /* MDIO bus release function */ 1913 static int ravb_mdio_release(struct ravb_private *priv) 1914 { 1915 /* Unregister mdio bus */ 1916 mdiobus_unregister(priv->mii_bus); 1917 1918 /* Free bitbang info */ 1919 free_mdio_bitbang(priv->mii_bus); 1920 1921 return 0; 1922 } 1923 1924 static const struct of_device_id ravb_match_table[] = { 1925 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1926 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1927 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1928 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1929 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1930 { } 1931 }; 1932 MODULE_DEVICE_TABLE(of, ravb_match_table); 1933 1934 static int ravb_set_gti(struct net_device *ndev) 1935 { 1936 struct ravb_private *priv = netdev_priv(ndev); 1937 struct device *dev = ndev->dev.parent; 1938 unsigned long rate; 1939 uint64_t inc; 1940 1941 rate = clk_get_rate(priv->clk); 1942 if (!rate) 1943 return -EINVAL; 1944 1945 inc = 1000000000ULL << 20; 1946 do_div(inc, rate); 1947 1948 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1949 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1950 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1951 return -EINVAL; 1952 } 1953 1954 ravb_write(ndev, inc, GTI); 1955 1956 return 0; 1957 } 1958 1959 static void ravb_set_config_mode(struct net_device *ndev) 1960 { 1961 struct ravb_private *priv = netdev_priv(ndev); 1962 1963 if (priv->chip_id == RCAR_GEN2) { 1964 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1965 /* Set CSEL value */ 1966 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1967 } else { 1968 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1969 CCC_GAC | CCC_CSEL_HPB); 1970 } 1971 } 1972 1973 /* Set tx and rx clock internal delay modes */ 1974 static void ravb_set_delay_mode(struct net_device *ndev) 1975 { 1976 struct ravb_private *priv = netdev_priv(ndev); 1977 int set = 0; 1978 1979 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1980 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1981 set |= APSR_DM_RDM; 1982 1983 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1984 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1985 set |= APSR_DM_TDM; 1986 1987 ravb_modify(ndev, APSR, APSR_DM, set); 1988 } 1989 1990 static int ravb_probe(struct platform_device *pdev) 1991 { 1992 struct device_node *np = pdev->dev.of_node; 1993 struct ravb_private *priv; 1994 enum ravb_chip_id chip_id; 1995 struct net_device *ndev; 1996 int error, irq, q; 1997 struct resource *res; 1998 int i; 1999 2000 if (!np) { 2001 dev_err(&pdev->dev, 2002 "this driver is required to be instantiated from device tree\n"); 2003 return -EINVAL; 2004 } 2005 2006 /* Get base address */ 2007 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2008 if (!res) { 2009 dev_err(&pdev->dev, "invalid resource\n"); 2010 return -EINVAL; 2011 } 2012 2013 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2014 NUM_TX_QUEUE, NUM_RX_QUEUE); 2015 if (!ndev) 2016 return -ENOMEM; 2017 2018 ndev->features = NETIF_F_RXCSUM; 2019 ndev->hw_features = NETIF_F_RXCSUM; 2020 2021 pm_runtime_enable(&pdev->dev); 2022 pm_runtime_get_sync(&pdev->dev); 2023 2024 /* The Ether-specific entries in the device structure. */ 2025 ndev->base_addr = res->start; 2026 2027 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2028 2029 if (chip_id == RCAR_GEN3) 2030 irq = platform_get_irq_byname(pdev, "ch22"); 2031 else 2032 irq = platform_get_irq(pdev, 0); 2033 if (irq < 0) { 2034 error = irq; 2035 goto out_release; 2036 } 2037 ndev->irq = irq; 2038 2039 SET_NETDEV_DEV(ndev, &pdev->dev); 2040 2041 priv = netdev_priv(ndev); 2042 priv->ndev = ndev; 2043 priv->pdev = pdev; 2044 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2045 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2046 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2047 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2048 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2049 if (IS_ERR(priv->addr)) { 2050 error = PTR_ERR(priv->addr); 2051 goto out_release; 2052 } 2053 2054 spin_lock_init(&priv->lock); 2055 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2056 2057 priv->phy_interface = of_get_phy_mode(np); 2058 2059 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2060 priv->avb_link_active_low = 2061 of_property_read_bool(np, "renesas,ether-link-active-low"); 2062 2063 if (chip_id == RCAR_GEN3) { 2064 irq = platform_get_irq_byname(pdev, "ch24"); 2065 if (irq < 0) { 2066 error = irq; 2067 goto out_release; 2068 } 2069 priv->emac_irq = irq; 2070 for (i = 0; i < NUM_RX_QUEUE; i++) { 2071 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2072 if (irq < 0) { 2073 error = irq; 2074 goto out_release; 2075 } 2076 priv->rx_irqs[i] = irq; 2077 } 2078 for (i = 0; i < NUM_TX_QUEUE; i++) { 2079 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2080 if (irq < 0) { 2081 error = irq; 2082 goto out_release; 2083 } 2084 priv->tx_irqs[i] = irq; 2085 } 2086 } 2087 2088 priv->chip_id = chip_id; 2089 2090 priv->clk = devm_clk_get(&pdev->dev, NULL); 2091 if (IS_ERR(priv->clk)) { 2092 error = PTR_ERR(priv->clk); 2093 goto out_release; 2094 } 2095 2096 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2097 ndev->min_mtu = ETH_MIN_MTU; 2098 2099 priv->num_tx_desc = chip_id == RCAR_GEN2 ? 2100 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3; 2101 2102 /* Set function */ 2103 ndev->netdev_ops = &ravb_netdev_ops; 2104 ndev->ethtool_ops = &ravb_ethtool_ops; 2105 2106 /* Set AVB config mode */ 2107 ravb_set_config_mode(ndev); 2108 2109 /* Set GTI value */ 2110 error = ravb_set_gti(ndev); 2111 if (error) 2112 goto out_release; 2113 2114 /* Request GTI loading */ 2115 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2116 2117 if (priv->chip_id != RCAR_GEN2) 2118 ravb_set_delay_mode(ndev); 2119 2120 /* Allocate descriptor base address table */ 2121 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2122 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2123 &priv->desc_bat_dma, GFP_KERNEL); 2124 if (!priv->desc_bat) { 2125 dev_err(&pdev->dev, 2126 "Cannot allocate desc base address table (size %d bytes)\n", 2127 priv->desc_bat_size); 2128 error = -ENOMEM; 2129 goto out_release; 2130 } 2131 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2132 priv->desc_bat[q].die_dt = DT_EOS; 2133 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2134 2135 /* Initialise HW timestamp list */ 2136 INIT_LIST_HEAD(&priv->ts_skb_list); 2137 2138 /* Initialise PTP Clock driver */ 2139 if (chip_id != RCAR_GEN2) 2140 ravb_ptp_init(ndev, pdev); 2141 2142 /* Debug message level */ 2143 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2144 2145 /* Read and set MAC address */ 2146 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2147 if (!is_valid_ether_addr(ndev->dev_addr)) { 2148 dev_warn(&pdev->dev, 2149 "no valid MAC address supplied, using a random one\n"); 2150 eth_hw_addr_random(ndev); 2151 } 2152 2153 /* MDIO bus init */ 2154 error = ravb_mdio_init(priv); 2155 if (error) { 2156 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2157 goto out_dma_free; 2158 } 2159 2160 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2161 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2162 2163 /* Network device register */ 2164 error = register_netdev(ndev); 2165 if (error) 2166 goto out_napi_del; 2167 2168 device_set_wakeup_capable(&pdev->dev, 1); 2169 2170 /* Print device information */ 2171 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2172 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2173 2174 platform_set_drvdata(pdev, ndev); 2175 2176 return 0; 2177 2178 out_napi_del: 2179 netif_napi_del(&priv->napi[RAVB_NC]); 2180 netif_napi_del(&priv->napi[RAVB_BE]); 2181 ravb_mdio_release(priv); 2182 out_dma_free: 2183 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2184 priv->desc_bat_dma); 2185 2186 /* Stop PTP Clock driver */ 2187 if (chip_id != RCAR_GEN2) 2188 ravb_ptp_stop(ndev); 2189 out_release: 2190 free_netdev(ndev); 2191 2192 pm_runtime_put(&pdev->dev); 2193 pm_runtime_disable(&pdev->dev); 2194 return error; 2195 } 2196 2197 static int ravb_remove(struct platform_device *pdev) 2198 { 2199 struct net_device *ndev = platform_get_drvdata(pdev); 2200 struct ravb_private *priv = netdev_priv(ndev); 2201 2202 /* Stop PTP Clock driver */ 2203 if (priv->chip_id != RCAR_GEN2) 2204 ravb_ptp_stop(ndev); 2205 2206 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2207 priv->desc_bat_dma); 2208 /* Set reset mode */ 2209 ravb_write(ndev, CCC_OPC_RESET, CCC); 2210 pm_runtime_put_sync(&pdev->dev); 2211 unregister_netdev(ndev); 2212 netif_napi_del(&priv->napi[RAVB_NC]); 2213 netif_napi_del(&priv->napi[RAVB_BE]); 2214 ravb_mdio_release(priv); 2215 pm_runtime_disable(&pdev->dev); 2216 free_netdev(ndev); 2217 platform_set_drvdata(pdev, NULL); 2218 2219 return 0; 2220 } 2221 2222 static int ravb_wol_setup(struct net_device *ndev) 2223 { 2224 struct ravb_private *priv = netdev_priv(ndev); 2225 2226 /* Disable interrupts by clearing the interrupt masks. */ 2227 ravb_write(ndev, 0, RIC0); 2228 ravb_write(ndev, 0, RIC2); 2229 ravb_write(ndev, 0, TIC); 2230 2231 /* Only allow ECI interrupts */ 2232 synchronize_irq(priv->emac_irq); 2233 napi_disable(&priv->napi[RAVB_NC]); 2234 napi_disable(&priv->napi[RAVB_BE]); 2235 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2236 2237 /* Enable MagicPacket */ 2238 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2239 2240 return enable_irq_wake(priv->emac_irq); 2241 } 2242 2243 static int ravb_wol_restore(struct net_device *ndev) 2244 { 2245 struct ravb_private *priv = netdev_priv(ndev); 2246 int ret; 2247 2248 napi_enable(&priv->napi[RAVB_NC]); 2249 napi_enable(&priv->napi[RAVB_BE]); 2250 2251 /* Disable MagicPacket */ 2252 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2253 2254 ret = ravb_close(ndev); 2255 if (ret < 0) 2256 return ret; 2257 2258 return disable_irq_wake(priv->emac_irq); 2259 } 2260 2261 static int __maybe_unused ravb_suspend(struct device *dev) 2262 { 2263 struct net_device *ndev = dev_get_drvdata(dev); 2264 struct ravb_private *priv = netdev_priv(ndev); 2265 int ret; 2266 2267 if (!netif_running(ndev)) 2268 return 0; 2269 2270 netif_device_detach(ndev); 2271 2272 if (priv->wol_enabled) 2273 ret = ravb_wol_setup(ndev); 2274 else 2275 ret = ravb_close(ndev); 2276 2277 return ret; 2278 } 2279 2280 static int __maybe_unused ravb_resume(struct device *dev) 2281 { 2282 struct net_device *ndev = dev_get_drvdata(dev); 2283 struct ravb_private *priv = netdev_priv(ndev); 2284 int ret = 0; 2285 2286 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2287 if (priv->wol_enabled) 2288 ravb_write(ndev, CCC_OPC_RESET, CCC); 2289 2290 /* All register have been reset to default values. 2291 * Restore all registers which where setup at probe time and 2292 * reopen device if it was running before system suspended. 2293 */ 2294 2295 /* Set AVB config mode */ 2296 ravb_set_config_mode(ndev); 2297 2298 /* Set GTI value */ 2299 ret = ravb_set_gti(ndev); 2300 if (ret) 2301 return ret; 2302 2303 /* Request GTI loading */ 2304 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2305 2306 if (priv->chip_id != RCAR_GEN2) 2307 ravb_set_delay_mode(ndev); 2308 2309 /* Restore descriptor base address table */ 2310 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2311 2312 if (netif_running(ndev)) { 2313 if (priv->wol_enabled) { 2314 ret = ravb_wol_restore(ndev); 2315 if (ret) 2316 return ret; 2317 } 2318 ret = ravb_open(ndev); 2319 if (ret < 0) 2320 return ret; 2321 netif_device_attach(ndev); 2322 } 2323 2324 return ret; 2325 } 2326 2327 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2328 { 2329 /* Runtime PM callback shared between ->runtime_suspend() 2330 * and ->runtime_resume(). Simply returns success. 2331 * 2332 * This driver re-initializes all registers after 2333 * pm_runtime_get_sync() anyway so there is no need 2334 * to save and restore registers here. 2335 */ 2336 return 0; 2337 } 2338 2339 static const struct dev_pm_ops ravb_dev_pm_ops = { 2340 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2341 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2342 }; 2343 2344 static struct platform_driver ravb_driver = { 2345 .probe = ravb_probe, 2346 .remove = ravb_remove, 2347 .driver = { 2348 .name = "ravb", 2349 .pm = &ravb_dev_pm_ops, 2350 .of_match_table = ravb_match_table, 2351 }, 2352 }; 2353 2354 module_platform_driver(ravb_driver); 2355 2356 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2357 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2358 MODULE_LICENSE("GPL v2"); 2359