1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
3  *
4  * Copyright (C) 2014-2019 Renesas Electronics Corporation
5  * Copyright (C) 2015 Renesas Solutions Corp.
6  * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7  *
8  * Based on the SuperH Ethernet driver
9  */
10 
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
23 #include <linux/of.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/slab.h>
29 #include <linux/spinlock.h>
30 #include <linux/reset.h>
31 #include <linux/math64.h>
32 
33 #include "ravb.h"
34 
35 #define RAVB_DEF_MSG_ENABLE \
36 		(NETIF_MSG_LINK	  | \
37 		 NETIF_MSG_TIMER  | \
38 		 NETIF_MSG_RX_ERR | \
39 		 NETIF_MSG_TX_ERR)
40 
41 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
42 	"ch0", /* RAVB_BE */
43 	"ch1", /* RAVB_NC */
44 };
45 
46 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
47 	"ch18", /* RAVB_BE */
48 	"ch19", /* RAVB_NC */
49 };
50 
51 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
52 		 u32 set)
53 {
54 	ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
55 }
56 
57 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
58 {
59 	int i;
60 
61 	for (i = 0; i < 10000; i++) {
62 		if ((ravb_read(ndev, reg) & mask) == value)
63 			return 0;
64 		udelay(10);
65 	}
66 	return -ETIMEDOUT;
67 }
68 
69 static int ravb_set_opmode(struct net_device *ndev, u32 opmode)
70 {
71 	u32 csr_ops = 1U << (opmode & CCC_OPC);
72 	u32 ccc_mask = CCC_OPC;
73 	int error;
74 
75 	/* If gPTP active in config mode is supported it needs to be configured
76 	 * along with CSEL and operating mode in the same access. This is a
77 	 * hardware limitation.
78 	 */
79 	if (opmode & CCC_GAC)
80 		ccc_mask |= CCC_GAC | CCC_CSEL;
81 
82 	/* Set operating mode */
83 	ravb_modify(ndev, CCC, ccc_mask, opmode);
84 	/* Check if the operating mode is changed to the requested one */
85 	error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops);
86 	if (error) {
87 		netdev_err(ndev, "failed to switch device to requested mode (%u)\n",
88 			   opmode & CCC_OPC);
89 	}
90 
91 	return error;
92 }
93 
94 static void ravb_set_rate_gbeth(struct net_device *ndev)
95 {
96 	struct ravb_private *priv = netdev_priv(ndev);
97 
98 	switch (priv->speed) {
99 	case 10:                /* 10BASE */
100 		ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);
101 		break;
102 	case 100:               /* 100BASE */
103 		ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);
104 		break;
105 	case 1000:              /* 1000BASE */
106 		ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);
107 		break;
108 	}
109 }
110 
111 static void ravb_set_rate_rcar(struct net_device *ndev)
112 {
113 	struct ravb_private *priv = netdev_priv(ndev);
114 
115 	switch (priv->speed) {
116 	case 100:		/* 100BASE */
117 		ravb_write(ndev, GECMR_SPEED_100, GECMR);
118 		break;
119 	case 1000:		/* 1000BASE */
120 		ravb_write(ndev, GECMR_SPEED_1000, GECMR);
121 		break;
122 	}
123 }
124 
125 static void ravb_set_buffer_align(struct sk_buff *skb)
126 {
127 	u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
128 
129 	if (reserve)
130 		skb_reserve(skb, RAVB_ALIGN - reserve);
131 }
132 
133 /* Get MAC address from the MAC address registers
134  *
135  * Ethernet AVB device doesn't have ROM for MAC address.
136  * This function gets the MAC address that was used by a bootloader.
137  */
138 static void ravb_read_mac_address(struct device_node *np,
139 				  struct net_device *ndev)
140 {
141 	int ret;
142 
143 	ret = of_get_ethdev_address(np, ndev);
144 	if (ret) {
145 		u32 mahr = ravb_read(ndev, MAHR);
146 		u32 malr = ravb_read(ndev, MALR);
147 		u8 addr[ETH_ALEN];
148 
149 		addr[0] = (mahr >> 24) & 0xFF;
150 		addr[1] = (mahr >> 16) & 0xFF;
151 		addr[2] = (mahr >>  8) & 0xFF;
152 		addr[3] = (mahr >>  0) & 0xFF;
153 		addr[4] = (malr >>  8) & 0xFF;
154 		addr[5] = (malr >>  0) & 0xFF;
155 		eth_hw_addr_set(ndev, addr);
156 	}
157 }
158 
159 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
160 {
161 	struct ravb_private *priv = container_of(ctrl, struct ravb_private,
162 						 mdiobb);
163 
164 	ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
165 }
166 
167 /* MDC pin control */
168 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
169 {
170 	ravb_mdio_ctrl(ctrl, PIR_MDC, level);
171 }
172 
173 /* Data I/O pin control */
174 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
175 {
176 	ravb_mdio_ctrl(ctrl, PIR_MMD, output);
177 }
178 
179 /* Set data bit */
180 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
181 {
182 	ravb_mdio_ctrl(ctrl, PIR_MDO, value);
183 }
184 
185 /* Get data bit */
186 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
187 {
188 	struct ravb_private *priv = container_of(ctrl, struct ravb_private,
189 						 mdiobb);
190 
191 	return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
192 }
193 
194 /* MDIO bus control struct */
195 static const struct mdiobb_ops bb_ops = {
196 	.owner = THIS_MODULE,
197 	.set_mdc = ravb_set_mdc,
198 	.set_mdio_dir = ravb_set_mdio_dir,
199 	.set_mdio_data = ravb_set_mdio_data,
200 	.get_mdio_data = ravb_get_mdio_data,
201 };
202 
203 /* Free TX skb function for AVB-IP */
204 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
205 {
206 	struct ravb_private *priv = netdev_priv(ndev);
207 	struct net_device_stats *stats = &priv->stats[q];
208 	unsigned int num_tx_desc = priv->num_tx_desc;
209 	struct ravb_tx_desc *desc;
210 	unsigned int entry;
211 	int free_num = 0;
212 	u32 size;
213 
214 	for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
215 		bool txed;
216 
217 		entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
218 					     num_tx_desc);
219 		desc = &priv->tx_ring[q][entry];
220 		txed = desc->die_dt == DT_FEMPTY;
221 		if (free_txed_only && !txed)
222 			break;
223 		/* Descriptor type must be checked before all other reads */
224 		dma_rmb();
225 		size = le16_to_cpu(desc->ds_tagl) & TX_DS;
226 		/* Free the original skb. */
227 		if (priv->tx_skb[q][entry / num_tx_desc]) {
228 			dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
229 					 size, DMA_TO_DEVICE);
230 			/* Last packet descriptor? */
231 			if (entry % num_tx_desc == num_tx_desc - 1) {
232 				entry /= num_tx_desc;
233 				dev_kfree_skb_any(priv->tx_skb[q][entry]);
234 				priv->tx_skb[q][entry] = NULL;
235 				if (txed)
236 					stats->tx_packets++;
237 			}
238 			free_num++;
239 		}
240 		if (txed)
241 			stats->tx_bytes += size;
242 		desc->die_dt = DT_EEMPTY;
243 	}
244 	return free_num;
245 }
246 
247 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q)
248 {
249 	struct ravb_private *priv = netdev_priv(ndev);
250 	unsigned int ring_size;
251 	unsigned int i;
252 
253 	if (!priv->gbeth_rx_ring)
254 		return;
255 
256 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
257 		struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i];
258 
259 		if (!dma_mapping_error(ndev->dev.parent,
260 				       le32_to_cpu(desc->dptr)))
261 			dma_unmap_single(ndev->dev.parent,
262 					 le32_to_cpu(desc->dptr),
263 					 GBETH_RX_BUFF_MAX,
264 					 DMA_FROM_DEVICE);
265 	}
266 	ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
267 	dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring,
268 			  priv->rx_desc_dma[q]);
269 	priv->gbeth_rx_ring = NULL;
270 }
271 
272 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q)
273 {
274 	struct ravb_private *priv = netdev_priv(ndev);
275 	unsigned int ring_size;
276 	unsigned int i;
277 
278 	if (!priv->rx_ring[q])
279 		return;
280 
281 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
282 		struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
283 
284 		if (!dma_mapping_error(ndev->dev.parent,
285 				       le32_to_cpu(desc->dptr)))
286 			dma_unmap_single(ndev->dev.parent,
287 					 le32_to_cpu(desc->dptr),
288 					 RX_BUF_SZ,
289 					 DMA_FROM_DEVICE);
290 	}
291 	ring_size = sizeof(struct ravb_ex_rx_desc) *
292 		    (priv->num_rx_ring[q] + 1);
293 	dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
294 			  priv->rx_desc_dma[q]);
295 	priv->rx_ring[q] = NULL;
296 }
297 
298 /* Free skb's and DMA buffers for Ethernet AVB */
299 static void ravb_ring_free(struct net_device *ndev, int q)
300 {
301 	struct ravb_private *priv = netdev_priv(ndev);
302 	const struct ravb_hw_info *info = priv->info;
303 	unsigned int num_tx_desc = priv->num_tx_desc;
304 	unsigned int ring_size;
305 	unsigned int i;
306 
307 	info->rx_ring_free(ndev, q);
308 
309 	if (priv->tx_ring[q]) {
310 		ravb_tx_free(ndev, q, false);
311 
312 		ring_size = sizeof(struct ravb_tx_desc) *
313 			    (priv->num_tx_ring[q] * num_tx_desc + 1);
314 		dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
315 				  priv->tx_desc_dma[q]);
316 		priv->tx_ring[q] = NULL;
317 	}
318 
319 	/* Free RX skb ringbuffer */
320 	if (priv->rx_skb[q]) {
321 		for (i = 0; i < priv->num_rx_ring[q]; i++)
322 			dev_kfree_skb(priv->rx_skb[q][i]);
323 	}
324 	kfree(priv->rx_skb[q]);
325 	priv->rx_skb[q] = NULL;
326 
327 	/* Free aligned TX buffers */
328 	kfree(priv->tx_align[q]);
329 	priv->tx_align[q] = NULL;
330 
331 	/* Free TX skb ringbuffer.
332 	 * SKBs are freed by ravb_tx_free() call above.
333 	 */
334 	kfree(priv->tx_skb[q]);
335 	priv->tx_skb[q] = NULL;
336 }
337 
338 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q)
339 {
340 	struct ravb_private *priv = netdev_priv(ndev);
341 	struct ravb_rx_desc *rx_desc;
342 	unsigned int rx_ring_size;
343 	dma_addr_t dma_addr;
344 	unsigned int i;
345 
346 	rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
347 	memset(priv->gbeth_rx_ring, 0, rx_ring_size);
348 	/* Build RX ring buffer */
349 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
350 		/* RX descriptor */
351 		rx_desc = &priv->gbeth_rx_ring[i];
352 		rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
353 		dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
354 					  GBETH_RX_BUFF_MAX,
355 					  DMA_FROM_DEVICE);
356 		/* We just set the data size to 0 for a failed mapping which
357 		 * should prevent DMA from happening...
358 		 */
359 		if (dma_mapping_error(ndev->dev.parent, dma_addr))
360 			rx_desc->ds_cc = cpu_to_le16(0);
361 		rx_desc->dptr = cpu_to_le32(dma_addr);
362 		rx_desc->die_dt = DT_FEMPTY;
363 	}
364 	rx_desc = &priv->gbeth_rx_ring[i];
365 	rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
366 	rx_desc->die_dt = DT_LINKFIX; /* type */
367 }
368 
369 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q)
370 {
371 	struct ravb_private *priv = netdev_priv(ndev);
372 	struct ravb_ex_rx_desc *rx_desc;
373 	unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
374 	dma_addr_t dma_addr;
375 	unsigned int i;
376 
377 	memset(priv->rx_ring[q], 0, rx_ring_size);
378 	/* Build RX ring buffer */
379 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
380 		/* RX descriptor */
381 		rx_desc = &priv->rx_ring[q][i];
382 		rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
383 		dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
384 					  RX_BUF_SZ,
385 					  DMA_FROM_DEVICE);
386 		/* We just set the data size to 0 for a failed mapping which
387 		 * should prevent DMA from happening...
388 		 */
389 		if (dma_mapping_error(ndev->dev.parent, dma_addr))
390 			rx_desc->ds_cc = cpu_to_le16(0);
391 		rx_desc->dptr = cpu_to_le32(dma_addr);
392 		rx_desc->die_dt = DT_FEMPTY;
393 	}
394 	rx_desc = &priv->rx_ring[q][i];
395 	rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
396 	rx_desc->die_dt = DT_LINKFIX; /* type */
397 }
398 
399 /* Format skb and descriptor buffer for Ethernet AVB */
400 static void ravb_ring_format(struct net_device *ndev, int q)
401 {
402 	struct ravb_private *priv = netdev_priv(ndev);
403 	const struct ravb_hw_info *info = priv->info;
404 	unsigned int num_tx_desc = priv->num_tx_desc;
405 	struct ravb_tx_desc *tx_desc;
406 	struct ravb_desc *desc;
407 	unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
408 				    num_tx_desc;
409 	unsigned int i;
410 
411 	priv->cur_rx[q] = 0;
412 	priv->cur_tx[q] = 0;
413 	priv->dirty_rx[q] = 0;
414 	priv->dirty_tx[q] = 0;
415 
416 	info->rx_ring_format(ndev, q);
417 
418 	memset(priv->tx_ring[q], 0, tx_ring_size);
419 	/* Build TX ring buffer */
420 	for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
421 	     i++, tx_desc++) {
422 		tx_desc->die_dt = DT_EEMPTY;
423 		if (num_tx_desc > 1) {
424 			tx_desc++;
425 			tx_desc->die_dt = DT_EEMPTY;
426 		}
427 	}
428 	tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
429 	tx_desc->die_dt = DT_LINKFIX; /* type */
430 
431 	/* RX descriptor base address for best effort */
432 	desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
433 	desc->die_dt = DT_LINKFIX; /* type */
434 	desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
435 
436 	/* TX descriptor base address for best effort */
437 	desc = &priv->desc_bat[q];
438 	desc->die_dt = DT_LINKFIX; /* type */
439 	desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
440 }
441 
442 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q)
443 {
444 	struct ravb_private *priv = netdev_priv(ndev);
445 	unsigned int ring_size;
446 
447 	ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
448 
449 	priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size,
450 						 &priv->rx_desc_dma[q],
451 						 GFP_KERNEL);
452 	return priv->gbeth_rx_ring;
453 }
454 
455 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q)
456 {
457 	struct ravb_private *priv = netdev_priv(ndev);
458 	unsigned int ring_size;
459 
460 	ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
461 
462 	priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
463 					      &priv->rx_desc_dma[q],
464 					      GFP_KERNEL);
465 	return priv->rx_ring[q];
466 }
467 
468 /* Init skb and descriptor buffer for Ethernet AVB */
469 static int ravb_ring_init(struct net_device *ndev, int q)
470 {
471 	struct ravb_private *priv = netdev_priv(ndev);
472 	const struct ravb_hw_info *info = priv->info;
473 	unsigned int num_tx_desc = priv->num_tx_desc;
474 	unsigned int ring_size;
475 	struct sk_buff *skb;
476 	unsigned int i;
477 
478 	/* Allocate RX and TX skb rings */
479 	priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
480 				  sizeof(*priv->rx_skb[q]), GFP_KERNEL);
481 	priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
482 				  sizeof(*priv->tx_skb[q]), GFP_KERNEL);
483 	if (!priv->rx_skb[q] || !priv->tx_skb[q])
484 		goto error;
485 
486 	for (i = 0; i < priv->num_rx_ring[q]; i++) {
487 		skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL);
488 		if (!skb)
489 			goto error;
490 		ravb_set_buffer_align(skb);
491 		priv->rx_skb[q][i] = skb;
492 	}
493 
494 	if (num_tx_desc > 1) {
495 		/* Allocate rings for the aligned buffers */
496 		priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
497 					    DPTR_ALIGN - 1, GFP_KERNEL);
498 		if (!priv->tx_align[q])
499 			goto error;
500 	}
501 
502 	/* Allocate all RX descriptors. */
503 	if (!info->alloc_rx_desc(ndev, q))
504 		goto error;
505 
506 	priv->dirty_rx[q] = 0;
507 
508 	/* Allocate all TX descriptors. */
509 	ring_size = sizeof(struct ravb_tx_desc) *
510 		    (priv->num_tx_ring[q] * num_tx_desc + 1);
511 	priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
512 					      &priv->tx_desc_dma[q],
513 					      GFP_KERNEL);
514 	if (!priv->tx_ring[q])
515 		goto error;
516 
517 	return 0;
518 
519 error:
520 	ravb_ring_free(ndev, q);
521 
522 	return -ENOMEM;
523 }
524 
525 static void ravb_emac_init_gbeth(struct net_device *ndev)
526 {
527 	struct ravb_private *priv = netdev_priv(ndev);
528 
529 	if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
530 		ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
531 		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
532 	} else {
533 		ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35);
534 		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
535 			    CXR31_SEL_LINK0);
536 	}
537 
538 	/* Receive frame limit set register */
539 	ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);
540 
541 	/* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */
542 	ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
543 			 ECMR_TE | ECMR_RE | ECMR_RCPT |
544 			 ECMR_TXF | ECMR_RXF, ECMR);
545 
546 	ravb_set_rate_gbeth(ndev);
547 
548 	/* Set MAC address */
549 	ravb_write(ndev,
550 		   (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
551 		   (ndev->dev_addr[2] << 8)  | (ndev->dev_addr[3]), MAHR);
552 	ravb_write(ndev, (ndev->dev_addr[4] << 8)  | (ndev->dev_addr[5]), MALR);
553 
554 	/* E-MAC status register clear */
555 	ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
556 	ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
557 
558 	/* E-MAC interrupt enable register */
559 	ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
560 }
561 
562 static void ravb_emac_init_rcar(struct net_device *ndev)
563 {
564 	/* Receive frame limit set register */
565 	ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
566 
567 	/* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
568 	ravb_write(ndev, ECMR_ZPF | ECMR_DM |
569 		   (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
570 		   ECMR_TE | ECMR_RE, ECMR);
571 
572 	ravb_set_rate_rcar(ndev);
573 
574 	/* Set MAC address */
575 	ravb_write(ndev,
576 		   (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
577 		   (ndev->dev_addr[2] << 8)  | (ndev->dev_addr[3]), MAHR);
578 	ravb_write(ndev,
579 		   (ndev->dev_addr[4] << 8)  | (ndev->dev_addr[5]), MALR);
580 
581 	/* E-MAC status register clear */
582 	ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
583 
584 	/* E-MAC interrupt enable register */
585 	ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
586 }
587 
588 /* E-MAC init function */
589 static void ravb_emac_init(struct net_device *ndev)
590 {
591 	struct ravb_private *priv = netdev_priv(ndev);
592 	const struct ravb_hw_info *info = priv->info;
593 
594 	info->emac_init(ndev);
595 }
596 
597 static int ravb_dmac_init_gbeth(struct net_device *ndev)
598 {
599 	int error;
600 
601 	error = ravb_ring_init(ndev, RAVB_BE);
602 	if (error)
603 		return error;
604 
605 	/* Descriptor format */
606 	ravb_ring_format(ndev, RAVB_BE);
607 
608 	/* Set DMAC RX */
609 	ravb_write(ndev, 0x60000000, RCR);
610 
611 	/* Set Max Frame Length (RTC) */
612 	ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC);
613 
614 	/* Set FIFO size */
615 	ravb_write(ndev, 0x00222200, TGC);
616 
617 	ravb_write(ndev, 0, TCCR);
618 
619 	/* Frame receive */
620 	ravb_write(ndev, RIC0_FRE0, RIC0);
621 	/* Disable FIFO full warning */
622 	ravb_write(ndev, 0x0, RIC1);
623 	/* Receive FIFO full error, descriptor empty */
624 	ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);
625 
626 	ravb_write(ndev, TIC_FTE0, TIC);
627 
628 	return 0;
629 }
630 
631 static int ravb_dmac_init_rcar(struct net_device *ndev)
632 {
633 	struct ravb_private *priv = netdev_priv(ndev);
634 	const struct ravb_hw_info *info = priv->info;
635 	int error;
636 
637 	error = ravb_ring_init(ndev, RAVB_BE);
638 	if (error)
639 		return error;
640 	error = ravb_ring_init(ndev, RAVB_NC);
641 	if (error) {
642 		ravb_ring_free(ndev, RAVB_BE);
643 		return error;
644 	}
645 
646 	/* Descriptor format */
647 	ravb_ring_format(ndev, RAVB_BE);
648 	ravb_ring_format(ndev, RAVB_NC);
649 
650 	/* Set AVB RX */
651 	ravb_write(ndev,
652 		   RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
653 
654 	/* Set FIFO size */
655 	ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
656 
657 	/* Timestamp enable */
658 	ravb_write(ndev, TCCR_TFEN, TCCR);
659 
660 	/* Interrupt init: */
661 	if (info->multi_irqs) {
662 		/* Clear DIL.DPLx */
663 		ravb_write(ndev, 0, DIL);
664 		/* Set queue specific interrupt */
665 		ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
666 	}
667 	/* Frame receive */
668 	ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
669 	/* Disable FIFO full warning */
670 	ravb_write(ndev, 0, RIC1);
671 	/* Receive FIFO full error, descriptor empty */
672 	ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
673 	/* Frame transmitted, timestamp FIFO updated */
674 	ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
675 
676 	return 0;
677 }
678 
679 /* Device init function for Ethernet AVB */
680 static int ravb_dmac_init(struct net_device *ndev)
681 {
682 	struct ravb_private *priv = netdev_priv(ndev);
683 	const struct ravb_hw_info *info = priv->info;
684 	int error;
685 
686 	/* Set CONFIG mode */
687 	error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);
688 	if (error)
689 		return error;
690 
691 	error = info->dmac_init(ndev);
692 	if (error)
693 		return error;
694 
695 	/* Setting the control will start the AVB-DMAC process. */
696 	return ravb_set_opmode(ndev, CCC_OPC_OPERATION);
697 }
698 
699 static void ravb_get_tx_tstamp(struct net_device *ndev)
700 {
701 	struct ravb_private *priv = netdev_priv(ndev);
702 	struct ravb_tstamp_skb *ts_skb, *ts_skb2;
703 	struct skb_shared_hwtstamps shhwtstamps;
704 	struct sk_buff *skb;
705 	struct timespec64 ts;
706 	u16 tag, tfa_tag;
707 	int count;
708 	u32 tfa2;
709 
710 	count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
711 	while (count--) {
712 		tfa2 = ravb_read(ndev, TFA2);
713 		tfa_tag = (tfa2 & TFA2_TST) >> 16;
714 		ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
715 		ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
716 			    ravb_read(ndev, TFA1);
717 		memset(&shhwtstamps, 0, sizeof(shhwtstamps));
718 		shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
719 		list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
720 					 list) {
721 			skb = ts_skb->skb;
722 			tag = ts_skb->tag;
723 			list_del(&ts_skb->list);
724 			kfree(ts_skb);
725 			if (tag == tfa_tag) {
726 				skb_tstamp_tx(skb, &shhwtstamps);
727 				dev_consume_skb_any(skb);
728 				break;
729 			} else {
730 				dev_kfree_skb_any(skb);
731 			}
732 		}
733 		ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
734 	}
735 }
736 
737 static void ravb_rx_csum(struct sk_buff *skb)
738 {
739 	u8 *hw_csum;
740 
741 	/* The hardware checksum is contained in sizeof(__sum16) (2) bytes
742 	 * appended to packet data
743 	 */
744 	if (unlikely(skb->len < sizeof(__sum16)))
745 		return;
746 	hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
747 	skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
748 	skb->ip_summed = CHECKSUM_COMPLETE;
749 	skb_trim(skb, skb->len - sizeof(__sum16));
750 }
751 
752 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry,
753 					  struct ravb_rx_desc *desc)
754 {
755 	struct ravb_private *priv = netdev_priv(ndev);
756 	struct sk_buff *skb;
757 
758 	skb = priv->rx_skb[RAVB_BE][entry];
759 	priv->rx_skb[RAVB_BE][entry] = NULL;
760 	dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
761 			 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE);
762 
763 	return skb;
764 }
765 
766 /* Packet receive function for Gigabit Ethernet */
767 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q)
768 {
769 	struct ravb_private *priv = netdev_priv(ndev);
770 	const struct ravb_hw_info *info = priv->info;
771 	struct net_device_stats *stats;
772 	struct ravb_rx_desc *desc;
773 	struct sk_buff *skb;
774 	dma_addr_t dma_addr;
775 	u8  desc_status;
776 	int boguscnt;
777 	u16 pkt_len;
778 	u8  die_dt;
779 	int entry;
780 	int limit;
781 
782 	entry = priv->cur_rx[q] % priv->num_rx_ring[q];
783 	boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q];
784 	stats = &priv->stats[q];
785 
786 	boguscnt = min(boguscnt, *quota);
787 	limit = boguscnt;
788 	desc = &priv->gbeth_rx_ring[entry];
789 	while (desc->die_dt != DT_FEMPTY) {
790 		/* Descriptor type must be checked before all other reads */
791 		dma_rmb();
792 		desc_status = desc->msc;
793 		pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
794 
795 		if (--boguscnt < 0)
796 			break;
797 
798 		/* We use 0-byte descriptors to mark the DMA mapping errors */
799 		if (!pkt_len)
800 			continue;
801 
802 		if (desc_status & MSC_MC)
803 			stats->multicast++;
804 
805 		if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) {
806 			stats->rx_errors++;
807 			if (desc_status & MSC_CRC)
808 				stats->rx_crc_errors++;
809 			if (desc_status & MSC_RFE)
810 				stats->rx_frame_errors++;
811 			if (desc_status & (MSC_RTLF | MSC_RTSF))
812 				stats->rx_length_errors++;
813 			if (desc_status & MSC_CEEF)
814 				stats->rx_missed_errors++;
815 		} else {
816 			die_dt = desc->die_dt & 0xF0;
817 			switch (die_dt) {
818 			case DT_FSINGLE:
819 				skb = ravb_get_skb_gbeth(ndev, entry, desc);
820 				skb_put(skb, pkt_len);
821 				skb->protocol = eth_type_trans(skb, ndev);
822 				napi_gro_receive(&priv->napi[q], skb);
823 				stats->rx_packets++;
824 				stats->rx_bytes += pkt_len;
825 				break;
826 			case DT_FSTART:
827 				priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc);
828 				skb_put(priv->rx_1st_skb, pkt_len);
829 				break;
830 			case DT_FMID:
831 				skb = ravb_get_skb_gbeth(ndev, entry, desc);
832 				skb_copy_to_linear_data_offset(priv->rx_1st_skb,
833 							       priv->rx_1st_skb->len,
834 							       skb->data,
835 							       pkt_len);
836 				skb_put(priv->rx_1st_skb, pkt_len);
837 				dev_kfree_skb(skb);
838 				break;
839 			case DT_FEND:
840 				skb = ravb_get_skb_gbeth(ndev, entry, desc);
841 				skb_copy_to_linear_data_offset(priv->rx_1st_skb,
842 							       priv->rx_1st_skb->len,
843 							       skb->data,
844 							       pkt_len);
845 				skb_put(priv->rx_1st_skb, pkt_len);
846 				dev_kfree_skb(skb);
847 				priv->rx_1st_skb->protocol =
848 					eth_type_trans(priv->rx_1st_skb, ndev);
849 				napi_gro_receive(&priv->napi[q],
850 						 priv->rx_1st_skb);
851 				stats->rx_packets++;
852 				stats->rx_bytes += pkt_len;
853 				break;
854 			}
855 		}
856 
857 		entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
858 		desc = &priv->gbeth_rx_ring[entry];
859 	}
860 
861 	/* Refill the RX ring buffers. */
862 	for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
863 		entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
864 		desc = &priv->gbeth_rx_ring[entry];
865 		desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
866 
867 		if (!priv->rx_skb[q][entry]) {
868 			skb = netdev_alloc_skb(ndev, info->max_rx_len);
869 			if (!skb)
870 				break;
871 			ravb_set_buffer_align(skb);
872 			dma_addr = dma_map_single(ndev->dev.parent,
873 						  skb->data,
874 						  GBETH_RX_BUFF_MAX,
875 						  DMA_FROM_DEVICE);
876 			skb_checksum_none_assert(skb);
877 			/* We just set the data size to 0 for a failed mapping
878 			 * which should prevent DMA  from happening...
879 			 */
880 			if (dma_mapping_error(ndev->dev.parent, dma_addr))
881 				desc->ds_cc = cpu_to_le16(0);
882 			desc->dptr = cpu_to_le32(dma_addr);
883 			priv->rx_skb[q][entry] = skb;
884 		}
885 		/* Descriptor type must be set after all the above writes */
886 		dma_wmb();
887 		desc->die_dt = DT_FEMPTY;
888 	}
889 
890 	*quota -= limit - (++boguscnt);
891 
892 	return boguscnt <= 0;
893 }
894 
895 /* Packet receive function for Ethernet AVB */
896 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q)
897 {
898 	struct ravb_private *priv = netdev_priv(ndev);
899 	const struct ravb_hw_info *info = priv->info;
900 	int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
901 	int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
902 			priv->cur_rx[q];
903 	struct net_device_stats *stats = &priv->stats[q];
904 	struct ravb_ex_rx_desc *desc;
905 	struct sk_buff *skb;
906 	dma_addr_t dma_addr;
907 	struct timespec64 ts;
908 	u8  desc_status;
909 	u16 pkt_len;
910 	int limit;
911 
912 	boguscnt = min(boguscnt, *quota);
913 	limit = boguscnt;
914 	desc = &priv->rx_ring[q][entry];
915 	while (desc->die_dt != DT_FEMPTY) {
916 		/* Descriptor type must be checked before all other reads */
917 		dma_rmb();
918 		desc_status = desc->msc;
919 		pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
920 
921 		if (--boguscnt < 0)
922 			break;
923 
924 		/* We use 0-byte descriptors to mark the DMA mapping errors */
925 		if (!pkt_len)
926 			continue;
927 
928 		if (desc_status & MSC_MC)
929 			stats->multicast++;
930 
931 		if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
932 				   MSC_CEEF)) {
933 			stats->rx_errors++;
934 			if (desc_status & MSC_CRC)
935 				stats->rx_crc_errors++;
936 			if (desc_status & MSC_RFE)
937 				stats->rx_frame_errors++;
938 			if (desc_status & (MSC_RTLF | MSC_RTSF))
939 				stats->rx_length_errors++;
940 			if (desc_status & MSC_CEEF)
941 				stats->rx_missed_errors++;
942 		} else {
943 			u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
944 
945 			skb = priv->rx_skb[q][entry];
946 			priv->rx_skb[q][entry] = NULL;
947 			dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
948 					 RX_BUF_SZ,
949 					 DMA_FROM_DEVICE);
950 			get_ts &= (q == RAVB_NC) ?
951 					RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
952 					~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
953 			if (get_ts) {
954 				struct skb_shared_hwtstamps *shhwtstamps;
955 
956 				shhwtstamps = skb_hwtstamps(skb);
957 				memset(shhwtstamps, 0, sizeof(*shhwtstamps));
958 				ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
959 					     32) | le32_to_cpu(desc->ts_sl);
960 				ts.tv_nsec = le32_to_cpu(desc->ts_n);
961 				shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
962 			}
963 
964 			skb_put(skb, pkt_len);
965 			skb->protocol = eth_type_trans(skb, ndev);
966 			if (ndev->features & NETIF_F_RXCSUM)
967 				ravb_rx_csum(skb);
968 			napi_gro_receive(&priv->napi[q], skb);
969 			stats->rx_packets++;
970 			stats->rx_bytes += pkt_len;
971 		}
972 
973 		entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
974 		desc = &priv->rx_ring[q][entry];
975 	}
976 
977 	/* Refill the RX ring buffers. */
978 	for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
979 		entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
980 		desc = &priv->rx_ring[q][entry];
981 		desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
982 
983 		if (!priv->rx_skb[q][entry]) {
984 			skb = netdev_alloc_skb(ndev, info->max_rx_len);
985 			if (!skb)
986 				break;	/* Better luck next round. */
987 			ravb_set_buffer_align(skb);
988 			dma_addr = dma_map_single(ndev->dev.parent, skb->data,
989 						  le16_to_cpu(desc->ds_cc),
990 						  DMA_FROM_DEVICE);
991 			skb_checksum_none_assert(skb);
992 			/* We just set the data size to 0 for a failed mapping
993 			 * which should prevent DMA  from happening...
994 			 */
995 			if (dma_mapping_error(ndev->dev.parent, dma_addr))
996 				desc->ds_cc = cpu_to_le16(0);
997 			desc->dptr = cpu_to_le32(dma_addr);
998 			priv->rx_skb[q][entry] = skb;
999 		}
1000 		/* Descriptor type must be set after all the above writes */
1001 		dma_wmb();
1002 		desc->die_dt = DT_FEMPTY;
1003 	}
1004 
1005 	*quota -= limit - (++boguscnt);
1006 
1007 	return boguscnt <= 0;
1008 }
1009 
1010 /* Packet receive function for Ethernet AVB */
1011 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
1012 {
1013 	struct ravb_private *priv = netdev_priv(ndev);
1014 	const struct ravb_hw_info *info = priv->info;
1015 
1016 	return info->receive(ndev, quota, q);
1017 }
1018 
1019 static void ravb_rcv_snd_disable(struct net_device *ndev)
1020 {
1021 	/* Disable TX and RX */
1022 	ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1023 }
1024 
1025 static void ravb_rcv_snd_enable(struct net_device *ndev)
1026 {
1027 	/* Enable TX and RX */
1028 	ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1029 }
1030 
1031 /* function for waiting dma process finished */
1032 static int ravb_stop_dma(struct net_device *ndev)
1033 {
1034 	struct ravb_private *priv = netdev_priv(ndev);
1035 	const struct ravb_hw_info *info = priv->info;
1036 	int error;
1037 
1038 	/* Wait for stopping the hardware TX process */
1039 	error = ravb_wait(ndev, TCCR, info->tccr_mask, 0);
1040 
1041 	if (error)
1042 		return error;
1043 
1044 	error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
1045 			  0);
1046 	if (error)
1047 		return error;
1048 
1049 	/* Stop the E-MAC's RX/TX processes. */
1050 	ravb_rcv_snd_disable(ndev);
1051 
1052 	/* Wait for stopping the RX DMA process */
1053 	error = ravb_wait(ndev, CSR, CSR_RPO, 0);
1054 	if (error)
1055 		return error;
1056 
1057 	/* Stop AVB-DMAC process */
1058 	return ravb_set_opmode(ndev, CCC_OPC_CONFIG);
1059 }
1060 
1061 /* E-MAC interrupt handler */
1062 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
1063 {
1064 	struct ravb_private *priv = netdev_priv(ndev);
1065 	u32 ecsr, psr;
1066 
1067 	ecsr = ravb_read(ndev, ECSR);
1068 	ravb_write(ndev, ecsr, ECSR);	/* clear interrupt */
1069 
1070 	if (ecsr & ECSR_MPD)
1071 		pm_wakeup_event(&priv->pdev->dev, 0);
1072 	if (ecsr & ECSR_ICD)
1073 		ndev->stats.tx_carrier_errors++;
1074 	if (ecsr & ECSR_LCHNG) {
1075 		/* Link changed */
1076 		if (priv->no_avb_link)
1077 			return;
1078 		psr = ravb_read(ndev, PSR);
1079 		if (priv->avb_link_active_low)
1080 			psr ^= PSR_LMON;
1081 		if (!(psr & PSR_LMON)) {
1082 			/* DIsable RX and TX */
1083 			ravb_rcv_snd_disable(ndev);
1084 		} else {
1085 			/* Enable RX and TX */
1086 			ravb_rcv_snd_enable(ndev);
1087 		}
1088 	}
1089 }
1090 
1091 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
1092 {
1093 	struct net_device *ndev = dev_id;
1094 	struct ravb_private *priv = netdev_priv(ndev);
1095 
1096 	spin_lock(&priv->lock);
1097 	ravb_emac_interrupt_unlocked(ndev);
1098 	spin_unlock(&priv->lock);
1099 	return IRQ_HANDLED;
1100 }
1101 
1102 /* Error interrupt handler */
1103 static void ravb_error_interrupt(struct net_device *ndev)
1104 {
1105 	struct ravb_private *priv = netdev_priv(ndev);
1106 	u32 eis, ris2;
1107 
1108 	eis = ravb_read(ndev, EIS);
1109 	ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
1110 	if (eis & EIS_QFS) {
1111 		ris2 = ravb_read(ndev, RIS2);
1112 		ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),
1113 			   RIS2);
1114 
1115 		/* Receive Descriptor Empty int */
1116 		if (ris2 & RIS2_QFF0)
1117 			priv->stats[RAVB_BE].rx_over_errors++;
1118 
1119 		/* Receive Descriptor Empty int */
1120 		if (ris2 & RIS2_QFF1)
1121 			priv->stats[RAVB_NC].rx_over_errors++;
1122 
1123 		/* Receive FIFO Overflow int */
1124 		if (ris2 & RIS2_RFFF)
1125 			priv->rx_fifo_errors++;
1126 	}
1127 }
1128 
1129 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
1130 {
1131 	struct ravb_private *priv = netdev_priv(ndev);
1132 	const struct ravb_hw_info *info = priv->info;
1133 	u32 ris0 = ravb_read(ndev, RIS0);
1134 	u32 ric0 = ravb_read(ndev, RIC0);
1135 	u32 tis  = ravb_read(ndev, TIS);
1136 	u32 tic  = ravb_read(ndev, TIC);
1137 
1138 	if (((ris0 & ric0) & BIT(q)) || ((tis  & tic)  & BIT(q))) {
1139 		if (napi_schedule_prep(&priv->napi[q])) {
1140 			/* Mask RX and TX interrupts */
1141 			if (!info->irq_en_dis) {
1142 				ravb_write(ndev, ric0 & ~BIT(q), RIC0);
1143 				ravb_write(ndev, tic & ~BIT(q), TIC);
1144 			} else {
1145 				ravb_write(ndev, BIT(q), RID0);
1146 				ravb_write(ndev, BIT(q), TID);
1147 			}
1148 			__napi_schedule(&priv->napi[q]);
1149 		} else {
1150 			netdev_warn(ndev,
1151 				    "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
1152 				    ris0, ric0);
1153 			netdev_warn(ndev,
1154 				    "                    tx status 0x%08x, tx mask 0x%08x.\n",
1155 				    tis, tic);
1156 		}
1157 		return true;
1158 	}
1159 	return false;
1160 }
1161 
1162 static bool ravb_timestamp_interrupt(struct net_device *ndev)
1163 {
1164 	u32 tis = ravb_read(ndev, TIS);
1165 
1166 	if (tis & TIS_TFUF) {
1167 		ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
1168 		ravb_get_tx_tstamp(ndev);
1169 		return true;
1170 	}
1171 	return false;
1172 }
1173 
1174 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
1175 {
1176 	struct net_device *ndev = dev_id;
1177 	struct ravb_private *priv = netdev_priv(ndev);
1178 	const struct ravb_hw_info *info = priv->info;
1179 	irqreturn_t result = IRQ_NONE;
1180 	u32 iss;
1181 
1182 	spin_lock(&priv->lock);
1183 	/* Get interrupt status */
1184 	iss = ravb_read(ndev, ISS);
1185 
1186 	/* Received and transmitted interrupts */
1187 	if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
1188 		int q;
1189 
1190 		/* Timestamp updated */
1191 		if (ravb_timestamp_interrupt(ndev))
1192 			result = IRQ_HANDLED;
1193 
1194 		/* Network control and best effort queue RX/TX */
1195 		if (info->nc_queues) {
1196 			for (q = RAVB_NC; q >= RAVB_BE; q--) {
1197 				if (ravb_queue_interrupt(ndev, q))
1198 					result = IRQ_HANDLED;
1199 			}
1200 		} else {
1201 			if (ravb_queue_interrupt(ndev, RAVB_BE))
1202 				result = IRQ_HANDLED;
1203 		}
1204 	}
1205 
1206 	/* E-MAC status summary */
1207 	if (iss & ISS_MS) {
1208 		ravb_emac_interrupt_unlocked(ndev);
1209 		result = IRQ_HANDLED;
1210 	}
1211 
1212 	/* Error status summary */
1213 	if (iss & ISS_ES) {
1214 		ravb_error_interrupt(ndev);
1215 		result = IRQ_HANDLED;
1216 	}
1217 
1218 	/* gPTP interrupt status summary */
1219 	if (iss & ISS_CGIS) {
1220 		ravb_ptp_interrupt(ndev);
1221 		result = IRQ_HANDLED;
1222 	}
1223 
1224 	spin_unlock(&priv->lock);
1225 	return result;
1226 }
1227 
1228 /* Timestamp/Error/gPTP interrupt handler */
1229 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
1230 {
1231 	struct net_device *ndev = dev_id;
1232 	struct ravb_private *priv = netdev_priv(ndev);
1233 	irqreturn_t result = IRQ_NONE;
1234 	u32 iss;
1235 
1236 	spin_lock(&priv->lock);
1237 	/* Get interrupt status */
1238 	iss = ravb_read(ndev, ISS);
1239 
1240 	/* Timestamp updated */
1241 	if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
1242 		result = IRQ_HANDLED;
1243 
1244 	/* Error status summary */
1245 	if (iss & ISS_ES) {
1246 		ravb_error_interrupt(ndev);
1247 		result = IRQ_HANDLED;
1248 	}
1249 
1250 	/* gPTP interrupt status summary */
1251 	if (iss & ISS_CGIS) {
1252 		ravb_ptp_interrupt(ndev);
1253 		result = IRQ_HANDLED;
1254 	}
1255 
1256 	spin_unlock(&priv->lock);
1257 	return result;
1258 }
1259 
1260 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
1261 {
1262 	struct net_device *ndev = dev_id;
1263 	struct ravb_private *priv = netdev_priv(ndev);
1264 	irqreturn_t result = IRQ_NONE;
1265 
1266 	spin_lock(&priv->lock);
1267 
1268 	/* Network control/Best effort queue RX/TX */
1269 	if (ravb_queue_interrupt(ndev, q))
1270 		result = IRQ_HANDLED;
1271 
1272 	spin_unlock(&priv->lock);
1273 	return result;
1274 }
1275 
1276 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
1277 {
1278 	return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
1279 }
1280 
1281 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
1282 {
1283 	return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
1284 }
1285 
1286 static int ravb_poll(struct napi_struct *napi, int budget)
1287 {
1288 	struct net_device *ndev = napi->dev;
1289 	struct ravb_private *priv = netdev_priv(ndev);
1290 	const struct ravb_hw_info *info = priv->info;
1291 	unsigned long flags;
1292 	int q = napi - priv->napi;
1293 	int mask = BIT(q);
1294 	int quota = budget;
1295 	bool unmask;
1296 
1297 	/* Processing RX Descriptor Ring */
1298 	/* Clear RX interrupt */
1299 	ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
1300 	unmask = !ravb_rx(ndev, &quota, q);
1301 
1302 	/* Processing TX Descriptor Ring */
1303 	spin_lock_irqsave(&priv->lock, flags);
1304 	/* Clear TX interrupt */
1305 	ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
1306 	ravb_tx_free(ndev, q, true);
1307 	netif_wake_subqueue(ndev, q);
1308 	spin_unlock_irqrestore(&priv->lock, flags);
1309 
1310 	/* Receive error message handling */
1311 	priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
1312 	if (info->nc_queues)
1313 		priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
1314 	if (priv->rx_over_errors != ndev->stats.rx_over_errors)
1315 		ndev->stats.rx_over_errors = priv->rx_over_errors;
1316 	if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
1317 		ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
1318 
1319 	if (!unmask)
1320 		goto out;
1321 
1322 	napi_complete(napi);
1323 
1324 	/* Re-enable RX/TX interrupts */
1325 	spin_lock_irqsave(&priv->lock, flags);
1326 	if (!info->irq_en_dis) {
1327 		ravb_modify(ndev, RIC0, mask, mask);
1328 		ravb_modify(ndev, TIC,  mask, mask);
1329 	} else {
1330 		ravb_write(ndev, mask, RIE0);
1331 		ravb_write(ndev, mask, TIE);
1332 	}
1333 	spin_unlock_irqrestore(&priv->lock, flags);
1334 
1335 out:
1336 	return budget - quota;
1337 }
1338 
1339 static void ravb_set_duplex_gbeth(struct net_device *ndev)
1340 {
1341 	struct ravb_private *priv = netdev_priv(ndev);
1342 
1343 	ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0);
1344 }
1345 
1346 /* PHY state control function */
1347 static void ravb_adjust_link(struct net_device *ndev)
1348 {
1349 	struct ravb_private *priv = netdev_priv(ndev);
1350 	const struct ravb_hw_info *info = priv->info;
1351 	struct phy_device *phydev = ndev->phydev;
1352 	bool new_state = false;
1353 	unsigned long flags;
1354 
1355 	spin_lock_irqsave(&priv->lock, flags);
1356 
1357 	/* Disable TX and RX right over here, if E-MAC change is ignored */
1358 	if (priv->no_avb_link)
1359 		ravb_rcv_snd_disable(ndev);
1360 
1361 	if (phydev->link) {
1362 		if (info->half_duplex && phydev->duplex != priv->duplex) {
1363 			new_state = true;
1364 			priv->duplex = phydev->duplex;
1365 			ravb_set_duplex_gbeth(ndev);
1366 		}
1367 
1368 		if (phydev->speed != priv->speed) {
1369 			new_state = true;
1370 			priv->speed = phydev->speed;
1371 			info->set_rate(ndev);
1372 		}
1373 		if (!priv->link) {
1374 			ravb_modify(ndev, ECMR, ECMR_TXF, 0);
1375 			new_state = true;
1376 			priv->link = phydev->link;
1377 		}
1378 	} else if (priv->link) {
1379 		new_state = true;
1380 		priv->link = 0;
1381 		priv->speed = 0;
1382 		if (info->half_duplex)
1383 			priv->duplex = -1;
1384 	}
1385 
1386 	/* Enable TX and RX right over here, if E-MAC change is ignored */
1387 	if (priv->no_avb_link && phydev->link)
1388 		ravb_rcv_snd_enable(ndev);
1389 
1390 	spin_unlock_irqrestore(&priv->lock, flags);
1391 
1392 	if (new_state && netif_msg_link(priv))
1393 		phy_print_status(phydev);
1394 }
1395 
1396 /* PHY init function */
1397 static int ravb_phy_init(struct net_device *ndev)
1398 {
1399 	struct device_node *np = ndev->dev.parent->of_node;
1400 	struct ravb_private *priv = netdev_priv(ndev);
1401 	const struct ravb_hw_info *info = priv->info;
1402 	struct phy_device *phydev;
1403 	struct device_node *pn;
1404 	phy_interface_t iface;
1405 	int err;
1406 
1407 	priv->link = 0;
1408 	priv->speed = 0;
1409 	priv->duplex = -1;
1410 
1411 	/* Try connecting to PHY */
1412 	pn = of_parse_phandle(np, "phy-handle", 0);
1413 	if (!pn) {
1414 		/* In the case of a fixed PHY, the DT node associated
1415 		 * to the PHY is the Ethernet MAC DT node.
1416 		 */
1417 		if (of_phy_is_fixed_link(np)) {
1418 			err = of_phy_register_fixed_link(np);
1419 			if (err)
1420 				return err;
1421 		}
1422 		pn = of_node_get(np);
1423 	}
1424 
1425 	iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1426 				     : priv->phy_interface;
1427 	phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1428 	of_node_put(pn);
1429 	if (!phydev) {
1430 		netdev_err(ndev, "failed to connect PHY\n");
1431 		err = -ENOENT;
1432 		goto err_deregister_fixed_link;
1433 	}
1434 
1435 	if (!info->half_duplex) {
1436 		/* 10BASE, Pause and Asym Pause is not supported */
1437 		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1438 		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1439 		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1440 		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1441 
1442 		/* Half Duplex is not supported */
1443 		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1444 		phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1445 	}
1446 
1447 	phy_attached_info(phydev);
1448 
1449 	return 0;
1450 
1451 err_deregister_fixed_link:
1452 	if (of_phy_is_fixed_link(np))
1453 		of_phy_deregister_fixed_link(np);
1454 
1455 	return err;
1456 }
1457 
1458 /* PHY control start function */
1459 static int ravb_phy_start(struct net_device *ndev)
1460 {
1461 	int error;
1462 
1463 	error = ravb_phy_init(ndev);
1464 	if (error)
1465 		return error;
1466 
1467 	phy_start(ndev->phydev);
1468 
1469 	return 0;
1470 }
1471 
1472 static u32 ravb_get_msglevel(struct net_device *ndev)
1473 {
1474 	struct ravb_private *priv = netdev_priv(ndev);
1475 
1476 	return priv->msg_enable;
1477 }
1478 
1479 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1480 {
1481 	struct ravb_private *priv = netdev_priv(ndev);
1482 
1483 	priv->msg_enable = value;
1484 }
1485 
1486 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = {
1487 	"rx_queue_0_current",
1488 	"tx_queue_0_current",
1489 	"rx_queue_0_dirty",
1490 	"tx_queue_0_dirty",
1491 	"rx_queue_0_packets",
1492 	"tx_queue_0_packets",
1493 	"rx_queue_0_bytes",
1494 	"tx_queue_0_bytes",
1495 	"rx_queue_0_mcast_packets",
1496 	"rx_queue_0_errors",
1497 	"rx_queue_0_crc_errors",
1498 	"rx_queue_0_frame_errors",
1499 	"rx_queue_0_length_errors",
1500 	"rx_queue_0_csum_offload_errors",
1501 	"rx_queue_0_over_errors",
1502 };
1503 
1504 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1505 	"rx_queue_0_current",
1506 	"tx_queue_0_current",
1507 	"rx_queue_0_dirty",
1508 	"tx_queue_0_dirty",
1509 	"rx_queue_0_packets",
1510 	"tx_queue_0_packets",
1511 	"rx_queue_0_bytes",
1512 	"tx_queue_0_bytes",
1513 	"rx_queue_0_mcast_packets",
1514 	"rx_queue_0_errors",
1515 	"rx_queue_0_crc_errors",
1516 	"rx_queue_0_frame_errors",
1517 	"rx_queue_0_length_errors",
1518 	"rx_queue_0_missed_errors",
1519 	"rx_queue_0_over_errors",
1520 
1521 	"rx_queue_1_current",
1522 	"tx_queue_1_current",
1523 	"rx_queue_1_dirty",
1524 	"tx_queue_1_dirty",
1525 	"rx_queue_1_packets",
1526 	"tx_queue_1_packets",
1527 	"rx_queue_1_bytes",
1528 	"tx_queue_1_bytes",
1529 	"rx_queue_1_mcast_packets",
1530 	"rx_queue_1_errors",
1531 	"rx_queue_1_crc_errors",
1532 	"rx_queue_1_frame_errors",
1533 	"rx_queue_1_length_errors",
1534 	"rx_queue_1_missed_errors",
1535 	"rx_queue_1_over_errors",
1536 };
1537 
1538 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1539 {
1540 	struct ravb_private *priv = netdev_priv(netdev);
1541 	const struct ravb_hw_info *info = priv->info;
1542 
1543 	switch (sset) {
1544 	case ETH_SS_STATS:
1545 		return info->stats_len;
1546 	default:
1547 		return -EOPNOTSUPP;
1548 	}
1549 }
1550 
1551 static void ravb_get_ethtool_stats(struct net_device *ndev,
1552 				   struct ethtool_stats *estats, u64 *data)
1553 {
1554 	struct ravb_private *priv = netdev_priv(ndev);
1555 	const struct ravb_hw_info *info = priv->info;
1556 	int num_rx_q;
1557 	int i = 0;
1558 	int q;
1559 
1560 	num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1;
1561 	/* Device-specific stats */
1562 	for (q = RAVB_BE; q < num_rx_q; q++) {
1563 		struct net_device_stats *stats = &priv->stats[q];
1564 
1565 		data[i++] = priv->cur_rx[q];
1566 		data[i++] = priv->cur_tx[q];
1567 		data[i++] = priv->dirty_rx[q];
1568 		data[i++] = priv->dirty_tx[q];
1569 		data[i++] = stats->rx_packets;
1570 		data[i++] = stats->tx_packets;
1571 		data[i++] = stats->rx_bytes;
1572 		data[i++] = stats->tx_bytes;
1573 		data[i++] = stats->multicast;
1574 		data[i++] = stats->rx_errors;
1575 		data[i++] = stats->rx_crc_errors;
1576 		data[i++] = stats->rx_frame_errors;
1577 		data[i++] = stats->rx_length_errors;
1578 		data[i++] = stats->rx_missed_errors;
1579 		data[i++] = stats->rx_over_errors;
1580 	}
1581 }
1582 
1583 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1584 {
1585 	struct ravb_private *priv = netdev_priv(ndev);
1586 	const struct ravb_hw_info *info = priv->info;
1587 
1588 	switch (stringset) {
1589 	case ETH_SS_STATS:
1590 		memcpy(data, info->gstrings_stats, info->gstrings_size);
1591 		break;
1592 	}
1593 }
1594 
1595 static void ravb_get_ringparam(struct net_device *ndev,
1596 			       struct ethtool_ringparam *ring,
1597 			       struct kernel_ethtool_ringparam *kernel_ring,
1598 			       struct netlink_ext_ack *extack)
1599 {
1600 	struct ravb_private *priv = netdev_priv(ndev);
1601 
1602 	ring->rx_max_pending = BE_RX_RING_MAX;
1603 	ring->tx_max_pending = BE_TX_RING_MAX;
1604 	ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1605 	ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1606 }
1607 
1608 static int ravb_set_ringparam(struct net_device *ndev,
1609 			      struct ethtool_ringparam *ring,
1610 			      struct kernel_ethtool_ringparam *kernel_ring,
1611 			      struct netlink_ext_ack *extack)
1612 {
1613 	struct ravb_private *priv = netdev_priv(ndev);
1614 	const struct ravb_hw_info *info = priv->info;
1615 	int error;
1616 
1617 	if (ring->tx_pending > BE_TX_RING_MAX ||
1618 	    ring->rx_pending > BE_RX_RING_MAX ||
1619 	    ring->tx_pending < BE_TX_RING_MIN ||
1620 	    ring->rx_pending < BE_RX_RING_MIN)
1621 		return -EINVAL;
1622 	if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1623 		return -EINVAL;
1624 
1625 	if (netif_running(ndev)) {
1626 		netif_device_detach(ndev);
1627 		/* Stop PTP Clock driver */
1628 		if (info->gptp)
1629 			ravb_ptp_stop(ndev);
1630 		/* Wait for DMA stopping */
1631 		error = ravb_stop_dma(ndev);
1632 		if (error) {
1633 			netdev_err(ndev,
1634 				   "cannot set ringparam! Any AVB processes are still running?\n");
1635 			return error;
1636 		}
1637 		synchronize_irq(ndev->irq);
1638 
1639 		/* Free all the skb's in the RX queue and the DMA buffers. */
1640 		ravb_ring_free(ndev, RAVB_BE);
1641 		if (info->nc_queues)
1642 			ravb_ring_free(ndev, RAVB_NC);
1643 	}
1644 
1645 	/* Set new parameters */
1646 	priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1647 	priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1648 
1649 	if (netif_running(ndev)) {
1650 		error = ravb_dmac_init(ndev);
1651 		if (error) {
1652 			netdev_err(ndev,
1653 				   "%s: ravb_dmac_init() failed, error %d\n",
1654 				   __func__, error);
1655 			return error;
1656 		}
1657 
1658 		ravb_emac_init(ndev);
1659 
1660 		/* Initialise PTP Clock driver */
1661 		if (info->gptp)
1662 			ravb_ptp_init(ndev, priv->pdev);
1663 
1664 		netif_device_attach(ndev);
1665 	}
1666 
1667 	return 0;
1668 }
1669 
1670 static int ravb_get_ts_info(struct net_device *ndev,
1671 			    struct ethtool_ts_info *info)
1672 {
1673 	struct ravb_private *priv = netdev_priv(ndev);
1674 	const struct ravb_hw_info *hw_info = priv->info;
1675 
1676 	info->so_timestamping =
1677 		SOF_TIMESTAMPING_TX_SOFTWARE |
1678 		SOF_TIMESTAMPING_RX_SOFTWARE |
1679 		SOF_TIMESTAMPING_SOFTWARE |
1680 		SOF_TIMESTAMPING_TX_HARDWARE |
1681 		SOF_TIMESTAMPING_RX_HARDWARE |
1682 		SOF_TIMESTAMPING_RAW_HARDWARE;
1683 	info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1684 	info->rx_filters =
1685 		(1 << HWTSTAMP_FILTER_NONE) |
1686 		(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1687 		(1 << HWTSTAMP_FILTER_ALL);
1688 	if (hw_info->gptp || hw_info->ccc_gac)
1689 		info->phc_index = ptp_clock_index(priv->ptp.clock);
1690 
1691 	return 0;
1692 }
1693 
1694 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1695 {
1696 	struct ravb_private *priv = netdev_priv(ndev);
1697 
1698 	wol->supported = WAKE_MAGIC;
1699 	wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1700 }
1701 
1702 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1703 {
1704 	struct ravb_private *priv = netdev_priv(ndev);
1705 	const struct ravb_hw_info *info = priv->info;
1706 
1707 	if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC))
1708 		return -EOPNOTSUPP;
1709 
1710 	priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1711 
1712 	device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1713 
1714 	return 0;
1715 }
1716 
1717 static const struct ethtool_ops ravb_ethtool_ops = {
1718 	.nway_reset		= phy_ethtool_nway_reset,
1719 	.get_msglevel		= ravb_get_msglevel,
1720 	.set_msglevel		= ravb_set_msglevel,
1721 	.get_link		= ethtool_op_get_link,
1722 	.get_strings		= ravb_get_strings,
1723 	.get_ethtool_stats	= ravb_get_ethtool_stats,
1724 	.get_sset_count		= ravb_get_sset_count,
1725 	.get_ringparam		= ravb_get_ringparam,
1726 	.set_ringparam		= ravb_set_ringparam,
1727 	.get_ts_info		= ravb_get_ts_info,
1728 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
1729 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
1730 	.get_wol		= ravb_get_wol,
1731 	.set_wol		= ravb_set_wol,
1732 };
1733 
1734 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1735 				struct net_device *ndev, struct device *dev,
1736 				const char *ch)
1737 {
1738 	char *name;
1739 	int error;
1740 
1741 	name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1742 	if (!name)
1743 		return -ENOMEM;
1744 	error = request_irq(irq, handler, 0, name, ndev);
1745 	if (error)
1746 		netdev_err(ndev, "cannot request IRQ %s\n", name);
1747 
1748 	return error;
1749 }
1750 
1751 /* Network device open function for Ethernet AVB */
1752 static int ravb_open(struct net_device *ndev)
1753 {
1754 	struct ravb_private *priv = netdev_priv(ndev);
1755 	const struct ravb_hw_info *info = priv->info;
1756 	struct platform_device *pdev = priv->pdev;
1757 	struct device *dev = &pdev->dev;
1758 	int error;
1759 
1760 	napi_enable(&priv->napi[RAVB_BE]);
1761 	if (info->nc_queues)
1762 		napi_enable(&priv->napi[RAVB_NC]);
1763 
1764 	if (!info->multi_irqs) {
1765 		error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1766 				    ndev->name, ndev);
1767 		if (error) {
1768 			netdev_err(ndev, "cannot request IRQ\n");
1769 			goto out_napi_off;
1770 		}
1771 	} else {
1772 		error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1773 				      dev, "ch22:multi");
1774 		if (error)
1775 			goto out_napi_off;
1776 		error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1777 				      dev, "ch24:emac");
1778 		if (error)
1779 			goto out_free_irq;
1780 		error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1781 				      ndev, dev, "ch0:rx_be");
1782 		if (error)
1783 			goto out_free_irq_emac;
1784 		error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1785 				      ndev, dev, "ch18:tx_be");
1786 		if (error)
1787 			goto out_free_irq_be_rx;
1788 		error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1789 				      ndev, dev, "ch1:rx_nc");
1790 		if (error)
1791 			goto out_free_irq_be_tx;
1792 		error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1793 				      ndev, dev, "ch19:tx_nc");
1794 		if (error)
1795 			goto out_free_irq_nc_rx;
1796 
1797 		if (info->err_mgmt_irqs) {
1798 			error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt,
1799 					      ndev, dev, "err_a");
1800 			if (error)
1801 				goto out_free_irq_nc_tx;
1802 			error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt,
1803 					      ndev, dev, "mgmt_a");
1804 			if (error)
1805 				goto out_free_irq_erra;
1806 		}
1807 	}
1808 
1809 	/* Device init */
1810 	error = ravb_dmac_init(ndev);
1811 	if (error)
1812 		goto out_free_irq_mgmta;
1813 	ravb_emac_init(ndev);
1814 
1815 	/* Initialise PTP Clock driver */
1816 	if (info->gptp)
1817 		ravb_ptp_init(ndev, priv->pdev);
1818 
1819 	/* PHY control start */
1820 	error = ravb_phy_start(ndev);
1821 	if (error)
1822 		goto out_ptp_stop;
1823 
1824 	netif_tx_start_all_queues(ndev);
1825 
1826 	return 0;
1827 
1828 out_ptp_stop:
1829 	/* Stop PTP Clock driver */
1830 	if (info->gptp)
1831 		ravb_ptp_stop(ndev);
1832 	ravb_stop_dma(ndev);
1833 out_free_irq_mgmta:
1834 	if (!info->multi_irqs)
1835 		goto out_free_irq;
1836 	if (info->err_mgmt_irqs)
1837 		free_irq(priv->mgmta_irq, ndev);
1838 out_free_irq_erra:
1839 	if (info->err_mgmt_irqs)
1840 		free_irq(priv->erra_irq, ndev);
1841 out_free_irq_nc_tx:
1842 	free_irq(priv->tx_irqs[RAVB_NC], ndev);
1843 out_free_irq_nc_rx:
1844 	free_irq(priv->rx_irqs[RAVB_NC], ndev);
1845 out_free_irq_be_tx:
1846 	free_irq(priv->tx_irqs[RAVB_BE], ndev);
1847 out_free_irq_be_rx:
1848 	free_irq(priv->rx_irqs[RAVB_BE], ndev);
1849 out_free_irq_emac:
1850 	free_irq(priv->emac_irq, ndev);
1851 out_free_irq:
1852 	free_irq(ndev->irq, ndev);
1853 out_napi_off:
1854 	if (info->nc_queues)
1855 		napi_disable(&priv->napi[RAVB_NC]);
1856 	napi_disable(&priv->napi[RAVB_BE]);
1857 	return error;
1858 }
1859 
1860 /* Timeout function for Ethernet AVB */
1861 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1862 {
1863 	struct ravb_private *priv = netdev_priv(ndev);
1864 
1865 	netif_err(priv, tx_err, ndev,
1866 		  "transmit timed out, status %08x, resetting...\n",
1867 		  ravb_read(ndev, ISS));
1868 
1869 	/* tx_errors count up */
1870 	ndev->stats.tx_errors++;
1871 
1872 	schedule_work(&priv->work);
1873 }
1874 
1875 static void ravb_tx_timeout_work(struct work_struct *work)
1876 {
1877 	struct ravb_private *priv = container_of(work, struct ravb_private,
1878 						 work);
1879 	const struct ravb_hw_info *info = priv->info;
1880 	struct net_device *ndev = priv->ndev;
1881 	int error;
1882 
1883 	if (!rtnl_trylock()) {
1884 		usleep_range(1000, 2000);
1885 		schedule_work(&priv->work);
1886 		return;
1887 	}
1888 
1889 	netif_tx_stop_all_queues(ndev);
1890 
1891 	/* Stop PTP Clock driver */
1892 	if (info->gptp)
1893 		ravb_ptp_stop(ndev);
1894 
1895 	/* Wait for DMA stopping */
1896 	if (ravb_stop_dma(ndev)) {
1897 		/* If ravb_stop_dma() fails, the hardware is still operating
1898 		 * for TX and/or RX. So, this should not call the following
1899 		 * functions because ravb_dmac_init() is possible to fail too.
1900 		 * Also, this should not retry ravb_stop_dma() again and again
1901 		 * here because it's possible to wait forever. So, this just
1902 		 * re-enables the TX and RX and skip the following
1903 		 * re-initialization procedure.
1904 		 */
1905 		ravb_rcv_snd_enable(ndev);
1906 		goto out;
1907 	}
1908 
1909 	ravb_ring_free(ndev, RAVB_BE);
1910 	if (info->nc_queues)
1911 		ravb_ring_free(ndev, RAVB_NC);
1912 
1913 	/* Device init */
1914 	error = ravb_dmac_init(ndev);
1915 	if (error) {
1916 		/* If ravb_dmac_init() fails, descriptors are freed. So, this
1917 		 * should return here to avoid re-enabling the TX and RX in
1918 		 * ravb_emac_init().
1919 		 */
1920 		netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1921 			   __func__, error);
1922 		goto out_unlock;
1923 	}
1924 	ravb_emac_init(ndev);
1925 
1926 out:
1927 	/* Initialise PTP Clock driver */
1928 	if (info->gptp)
1929 		ravb_ptp_init(ndev, priv->pdev);
1930 
1931 	netif_tx_start_all_queues(ndev);
1932 
1933 out_unlock:
1934 	rtnl_unlock();
1935 }
1936 
1937 /* Packet transmit function for Ethernet AVB */
1938 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1939 {
1940 	struct ravb_private *priv = netdev_priv(ndev);
1941 	const struct ravb_hw_info *info = priv->info;
1942 	unsigned int num_tx_desc = priv->num_tx_desc;
1943 	u16 q = skb_get_queue_mapping(skb);
1944 	struct ravb_tstamp_skb *ts_skb;
1945 	struct ravb_tx_desc *desc;
1946 	unsigned long flags;
1947 	dma_addr_t dma_addr;
1948 	void *buffer;
1949 	u32 entry;
1950 	u32 len;
1951 
1952 	spin_lock_irqsave(&priv->lock, flags);
1953 	if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1954 	    num_tx_desc) {
1955 		netif_err(priv, tx_queued, ndev,
1956 			  "still transmitting with the full ring!\n");
1957 		netif_stop_subqueue(ndev, q);
1958 		spin_unlock_irqrestore(&priv->lock, flags);
1959 		return NETDEV_TX_BUSY;
1960 	}
1961 
1962 	if (skb_put_padto(skb, ETH_ZLEN))
1963 		goto exit;
1964 
1965 	entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1966 	priv->tx_skb[q][entry / num_tx_desc] = skb;
1967 
1968 	if (num_tx_desc > 1) {
1969 		buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1970 			 entry / num_tx_desc * DPTR_ALIGN;
1971 		len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1972 
1973 		/* Zero length DMA descriptors are problematic as they seem
1974 		 * to terminate DMA transfers. Avoid them by simply using a
1975 		 * length of DPTR_ALIGN (4) when skb data is aligned to
1976 		 * DPTR_ALIGN.
1977 		 *
1978 		 * As skb is guaranteed to have at least ETH_ZLEN (60)
1979 		 * bytes of data by the call to skb_put_padto() above this
1980 		 * is safe with respect to both the length of the first DMA
1981 		 * descriptor (len) overflowing the available data and the
1982 		 * length of the second DMA descriptor (skb->len - len)
1983 		 * being negative.
1984 		 */
1985 		if (len == 0)
1986 			len = DPTR_ALIGN;
1987 
1988 		memcpy(buffer, skb->data, len);
1989 		dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1990 					  DMA_TO_DEVICE);
1991 		if (dma_mapping_error(ndev->dev.parent, dma_addr))
1992 			goto drop;
1993 
1994 		desc = &priv->tx_ring[q][entry];
1995 		desc->ds_tagl = cpu_to_le16(len);
1996 		desc->dptr = cpu_to_le32(dma_addr);
1997 
1998 		buffer = skb->data + len;
1999 		len = skb->len - len;
2000 		dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
2001 					  DMA_TO_DEVICE);
2002 		if (dma_mapping_error(ndev->dev.parent, dma_addr))
2003 			goto unmap;
2004 
2005 		desc++;
2006 	} else {
2007 		desc = &priv->tx_ring[q][entry];
2008 		len = skb->len;
2009 		dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
2010 					  DMA_TO_DEVICE);
2011 		if (dma_mapping_error(ndev->dev.parent, dma_addr))
2012 			goto drop;
2013 	}
2014 	desc->ds_tagl = cpu_to_le16(len);
2015 	desc->dptr = cpu_to_le32(dma_addr);
2016 
2017 	/* TX timestamp required */
2018 	if (info->gptp || info->ccc_gac) {
2019 		if (q == RAVB_NC) {
2020 			ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
2021 			if (!ts_skb) {
2022 				if (num_tx_desc > 1) {
2023 					desc--;
2024 					dma_unmap_single(ndev->dev.parent, dma_addr,
2025 							 len, DMA_TO_DEVICE);
2026 				}
2027 				goto unmap;
2028 			}
2029 			ts_skb->skb = skb_get(skb);
2030 			ts_skb->tag = priv->ts_skb_tag++;
2031 			priv->ts_skb_tag &= 0x3ff;
2032 			list_add_tail(&ts_skb->list, &priv->ts_skb_list);
2033 
2034 			/* TAG and timestamp required flag */
2035 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2036 			desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
2037 			desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
2038 		}
2039 
2040 		skb_tx_timestamp(skb);
2041 	}
2042 	/* Descriptor type must be set after all the above writes */
2043 	dma_wmb();
2044 	if (num_tx_desc > 1) {
2045 		desc->die_dt = DT_FEND;
2046 		desc--;
2047 		desc->die_dt = DT_FSTART;
2048 	} else {
2049 		desc->die_dt = DT_FSINGLE;
2050 	}
2051 	ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
2052 
2053 	priv->cur_tx[q] += num_tx_desc;
2054 	if (priv->cur_tx[q] - priv->dirty_tx[q] >
2055 	    (priv->num_tx_ring[q] - 1) * num_tx_desc &&
2056 	    !ravb_tx_free(ndev, q, true))
2057 		netif_stop_subqueue(ndev, q);
2058 
2059 exit:
2060 	spin_unlock_irqrestore(&priv->lock, flags);
2061 	return NETDEV_TX_OK;
2062 
2063 unmap:
2064 	dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2065 			 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
2066 drop:
2067 	dev_kfree_skb_any(skb);
2068 	priv->tx_skb[q][entry / num_tx_desc] = NULL;
2069 	goto exit;
2070 }
2071 
2072 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
2073 			     struct net_device *sb_dev)
2074 {
2075 	/* If skb needs TX timestamp, it is handled in network control queue */
2076 	return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
2077 							       RAVB_BE;
2078 
2079 }
2080 
2081 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
2082 {
2083 	struct ravb_private *priv = netdev_priv(ndev);
2084 	const struct ravb_hw_info *info = priv->info;
2085 	struct net_device_stats *nstats, *stats0, *stats1;
2086 
2087 	nstats = &ndev->stats;
2088 	stats0 = &priv->stats[RAVB_BE];
2089 
2090 	if (info->tx_counters) {
2091 		nstats->tx_dropped += ravb_read(ndev, TROCR);
2092 		ravb_write(ndev, 0, TROCR);	/* (write clear) */
2093 	}
2094 
2095 	if (info->carrier_counters) {
2096 		nstats->collisions += ravb_read(ndev, CXR41);
2097 		ravb_write(ndev, 0, CXR41);	/* (write clear) */
2098 		nstats->tx_carrier_errors += ravb_read(ndev, CXR42);
2099 		ravb_write(ndev, 0, CXR42);	/* (write clear) */
2100 	}
2101 
2102 	nstats->rx_packets = stats0->rx_packets;
2103 	nstats->tx_packets = stats0->tx_packets;
2104 	nstats->rx_bytes = stats0->rx_bytes;
2105 	nstats->tx_bytes = stats0->tx_bytes;
2106 	nstats->multicast = stats0->multicast;
2107 	nstats->rx_errors = stats0->rx_errors;
2108 	nstats->rx_crc_errors = stats0->rx_crc_errors;
2109 	nstats->rx_frame_errors = stats0->rx_frame_errors;
2110 	nstats->rx_length_errors = stats0->rx_length_errors;
2111 	nstats->rx_missed_errors = stats0->rx_missed_errors;
2112 	nstats->rx_over_errors = stats0->rx_over_errors;
2113 	if (info->nc_queues) {
2114 		stats1 = &priv->stats[RAVB_NC];
2115 
2116 		nstats->rx_packets += stats1->rx_packets;
2117 		nstats->tx_packets += stats1->tx_packets;
2118 		nstats->rx_bytes += stats1->rx_bytes;
2119 		nstats->tx_bytes += stats1->tx_bytes;
2120 		nstats->multicast += stats1->multicast;
2121 		nstats->rx_errors += stats1->rx_errors;
2122 		nstats->rx_crc_errors += stats1->rx_crc_errors;
2123 		nstats->rx_frame_errors += stats1->rx_frame_errors;
2124 		nstats->rx_length_errors += stats1->rx_length_errors;
2125 		nstats->rx_missed_errors += stats1->rx_missed_errors;
2126 		nstats->rx_over_errors += stats1->rx_over_errors;
2127 	}
2128 
2129 	return nstats;
2130 }
2131 
2132 /* Update promiscuous bit */
2133 static void ravb_set_rx_mode(struct net_device *ndev)
2134 {
2135 	struct ravb_private *priv = netdev_priv(ndev);
2136 	unsigned long flags;
2137 
2138 	spin_lock_irqsave(&priv->lock, flags);
2139 	ravb_modify(ndev, ECMR, ECMR_PRM,
2140 		    ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
2141 	spin_unlock_irqrestore(&priv->lock, flags);
2142 }
2143 
2144 /* Device close function for Ethernet AVB */
2145 static int ravb_close(struct net_device *ndev)
2146 {
2147 	struct device_node *np = ndev->dev.parent->of_node;
2148 	struct ravb_private *priv = netdev_priv(ndev);
2149 	const struct ravb_hw_info *info = priv->info;
2150 	struct ravb_tstamp_skb *ts_skb, *ts_skb2;
2151 
2152 	netif_tx_stop_all_queues(ndev);
2153 
2154 	/* Disable interrupts by clearing the interrupt masks. */
2155 	ravb_write(ndev, 0, RIC0);
2156 	ravb_write(ndev, 0, RIC2);
2157 	ravb_write(ndev, 0, TIC);
2158 
2159 	/* Stop PTP Clock driver */
2160 	if (info->gptp)
2161 		ravb_ptp_stop(ndev);
2162 
2163 	/* Set the config mode to stop the AVB-DMAC's processes */
2164 	if (ravb_stop_dma(ndev) < 0)
2165 		netdev_err(ndev,
2166 			   "device will be stopped after h/w processes are done.\n");
2167 
2168 	/* Clear the timestamp list */
2169 	if (info->gptp || info->ccc_gac) {
2170 		list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
2171 			list_del(&ts_skb->list);
2172 			kfree_skb(ts_skb->skb);
2173 			kfree(ts_skb);
2174 		}
2175 	}
2176 
2177 	/* PHY disconnect */
2178 	if (ndev->phydev) {
2179 		phy_stop(ndev->phydev);
2180 		phy_disconnect(ndev->phydev);
2181 		if (of_phy_is_fixed_link(np))
2182 			of_phy_deregister_fixed_link(np);
2183 	}
2184 
2185 	cancel_work_sync(&priv->work);
2186 
2187 	if (info->multi_irqs) {
2188 		free_irq(priv->tx_irqs[RAVB_NC], ndev);
2189 		free_irq(priv->rx_irqs[RAVB_NC], ndev);
2190 		free_irq(priv->tx_irqs[RAVB_BE], ndev);
2191 		free_irq(priv->rx_irqs[RAVB_BE], ndev);
2192 		free_irq(priv->emac_irq, ndev);
2193 		if (info->err_mgmt_irqs) {
2194 			free_irq(priv->erra_irq, ndev);
2195 			free_irq(priv->mgmta_irq, ndev);
2196 		}
2197 	}
2198 	free_irq(ndev->irq, ndev);
2199 
2200 	if (info->nc_queues)
2201 		napi_disable(&priv->napi[RAVB_NC]);
2202 	napi_disable(&priv->napi[RAVB_BE]);
2203 
2204 	/* Free all the skb's in the RX queue and the DMA buffers. */
2205 	ravb_ring_free(ndev, RAVB_BE);
2206 	if (info->nc_queues)
2207 		ravb_ring_free(ndev, RAVB_NC);
2208 
2209 	return 0;
2210 }
2211 
2212 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
2213 {
2214 	struct ravb_private *priv = netdev_priv(ndev);
2215 	struct hwtstamp_config config;
2216 
2217 	config.flags = 0;
2218 	config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
2219 						HWTSTAMP_TX_OFF;
2220 	switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
2221 	case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
2222 		config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
2223 		break;
2224 	case RAVB_RXTSTAMP_TYPE_ALL:
2225 		config.rx_filter = HWTSTAMP_FILTER_ALL;
2226 		break;
2227 	default:
2228 		config.rx_filter = HWTSTAMP_FILTER_NONE;
2229 	}
2230 
2231 	return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2232 		-EFAULT : 0;
2233 }
2234 
2235 /* Control hardware time stamping */
2236 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
2237 {
2238 	struct ravb_private *priv = netdev_priv(ndev);
2239 	struct hwtstamp_config config;
2240 	u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
2241 	u32 tstamp_tx_ctrl;
2242 
2243 	if (copy_from_user(&config, req->ifr_data, sizeof(config)))
2244 		return -EFAULT;
2245 
2246 	switch (config.tx_type) {
2247 	case HWTSTAMP_TX_OFF:
2248 		tstamp_tx_ctrl = 0;
2249 		break;
2250 	case HWTSTAMP_TX_ON:
2251 		tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
2252 		break;
2253 	default:
2254 		return -ERANGE;
2255 	}
2256 
2257 	switch (config.rx_filter) {
2258 	case HWTSTAMP_FILTER_NONE:
2259 		tstamp_rx_ctrl = 0;
2260 		break;
2261 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2262 		tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
2263 		break;
2264 	default:
2265 		config.rx_filter = HWTSTAMP_FILTER_ALL;
2266 		tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
2267 	}
2268 
2269 	priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
2270 	priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
2271 
2272 	return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2273 		-EFAULT : 0;
2274 }
2275 
2276 /* ioctl to device function */
2277 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
2278 {
2279 	struct phy_device *phydev = ndev->phydev;
2280 
2281 	if (!netif_running(ndev))
2282 		return -EINVAL;
2283 
2284 	if (!phydev)
2285 		return -ENODEV;
2286 
2287 	switch (cmd) {
2288 	case SIOCGHWTSTAMP:
2289 		return ravb_hwtstamp_get(ndev, req);
2290 	case SIOCSHWTSTAMP:
2291 		return ravb_hwtstamp_set(ndev, req);
2292 	}
2293 
2294 	return phy_mii_ioctl(phydev, req, cmd);
2295 }
2296 
2297 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
2298 {
2299 	struct ravb_private *priv = netdev_priv(ndev);
2300 
2301 	ndev->mtu = new_mtu;
2302 
2303 	if (netif_running(ndev)) {
2304 		synchronize_irq(priv->emac_irq);
2305 		ravb_emac_init(ndev);
2306 	}
2307 
2308 	netdev_update_features(ndev);
2309 
2310 	return 0;
2311 }
2312 
2313 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
2314 {
2315 	struct ravb_private *priv = netdev_priv(ndev);
2316 	unsigned long flags;
2317 
2318 	spin_lock_irqsave(&priv->lock, flags);
2319 
2320 	/* Disable TX and RX */
2321 	ravb_rcv_snd_disable(ndev);
2322 
2323 	/* Modify RX Checksum setting */
2324 	ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2325 
2326 	/* Enable TX and RX */
2327 	ravb_rcv_snd_enable(ndev);
2328 
2329 	spin_unlock_irqrestore(&priv->lock, flags);
2330 }
2331 
2332 static int ravb_set_features_gbeth(struct net_device *ndev,
2333 				   netdev_features_t features)
2334 {
2335 	/* Place holder */
2336 	return 0;
2337 }
2338 
2339 static int ravb_set_features_rcar(struct net_device *ndev,
2340 				  netdev_features_t features)
2341 {
2342 	netdev_features_t changed = ndev->features ^ features;
2343 
2344 	if (changed & NETIF_F_RXCSUM)
2345 		ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2346 
2347 	ndev->features = features;
2348 
2349 	return 0;
2350 }
2351 
2352 static int ravb_set_features(struct net_device *ndev,
2353 			     netdev_features_t features)
2354 {
2355 	struct ravb_private *priv = netdev_priv(ndev);
2356 	const struct ravb_hw_info *info = priv->info;
2357 
2358 	return info->set_feature(ndev, features);
2359 }
2360 
2361 static const struct net_device_ops ravb_netdev_ops = {
2362 	.ndo_open		= ravb_open,
2363 	.ndo_stop		= ravb_close,
2364 	.ndo_start_xmit		= ravb_start_xmit,
2365 	.ndo_select_queue	= ravb_select_queue,
2366 	.ndo_get_stats		= ravb_get_stats,
2367 	.ndo_set_rx_mode	= ravb_set_rx_mode,
2368 	.ndo_tx_timeout		= ravb_tx_timeout,
2369 	.ndo_eth_ioctl		= ravb_do_ioctl,
2370 	.ndo_change_mtu		= ravb_change_mtu,
2371 	.ndo_validate_addr	= eth_validate_addr,
2372 	.ndo_set_mac_address	= eth_mac_addr,
2373 	.ndo_set_features	= ravb_set_features,
2374 };
2375 
2376 /* MDIO bus init function */
2377 static int ravb_mdio_init(struct ravb_private *priv)
2378 {
2379 	struct platform_device *pdev = priv->pdev;
2380 	struct device *dev = &pdev->dev;
2381 	struct phy_device *phydev;
2382 	struct device_node *pn;
2383 	int error;
2384 
2385 	/* Bitbang init */
2386 	priv->mdiobb.ops = &bb_ops;
2387 
2388 	/* MII controller setting */
2389 	priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
2390 	if (!priv->mii_bus)
2391 		return -ENOMEM;
2392 
2393 	/* Hook up MII support for ethtool */
2394 	priv->mii_bus->name = "ravb_mii";
2395 	priv->mii_bus->parent = dev;
2396 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2397 		 pdev->name, pdev->id);
2398 
2399 	/* Register MDIO bus */
2400 	error = of_mdiobus_register(priv->mii_bus, dev->of_node);
2401 	if (error)
2402 		goto out_free_bus;
2403 
2404 	pn = of_parse_phandle(dev->of_node, "phy-handle", 0);
2405 	phydev = of_phy_find_device(pn);
2406 	if (phydev) {
2407 		phydev->mac_managed_pm = true;
2408 		put_device(&phydev->mdio.dev);
2409 	}
2410 	of_node_put(pn);
2411 
2412 	return 0;
2413 
2414 out_free_bus:
2415 	free_mdio_bitbang(priv->mii_bus);
2416 	return error;
2417 }
2418 
2419 /* MDIO bus release function */
2420 static int ravb_mdio_release(struct ravb_private *priv)
2421 {
2422 	/* Unregister mdio bus */
2423 	mdiobus_unregister(priv->mii_bus);
2424 
2425 	/* Free bitbang info */
2426 	free_mdio_bitbang(priv->mii_bus);
2427 
2428 	return 0;
2429 }
2430 
2431 static const struct ravb_hw_info ravb_gen3_hw_info = {
2432 	.rx_ring_free = ravb_rx_ring_free_rcar,
2433 	.rx_ring_format = ravb_rx_ring_format_rcar,
2434 	.alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2435 	.receive = ravb_rx_rcar,
2436 	.set_rate = ravb_set_rate_rcar,
2437 	.set_feature = ravb_set_features_rcar,
2438 	.dmac_init = ravb_dmac_init_rcar,
2439 	.emac_init = ravb_emac_init_rcar,
2440 	.gstrings_stats = ravb_gstrings_stats,
2441 	.gstrings_size = sizeof(ravb_gstrings_stats),
2442 	.net_hw_features = NETIF_F_RXCSUM,
2443 	.net_features = NETIF_F_RXCSUM,
2444 	.stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2445 	.max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2446 	.tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2447 	.rx_max_buf_size = SZ_2K,
2448 	.internal_delay = 1,
2449 	.tx_counters = 1,
2450 	.multi_irqs = 1,
2451 	.irq_en_dis = 1,
2452 	.ccc_gac = 1,
2453 	.nc_queues = 1,
2454 	.magic_pkt = 1,
2455 };
2456 
2457 static const struct ravb_hw_info ravb_gen2_hw_info = {
2458 	.rx_ring_free = ravb_rx_ring_free_rcar,
2459 	.rx_ring_format = ravb_rx_ring_format_rcar,
2460 	.alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2461 	.receive = ravb_rx_rcar,
2462 	.set_rate = ravb_set_rate_rcar,
2463 	.set_feature = ravb_set_features_rcar,
2464 	.dmac_init = ravb_dmac_init_rcar,
2465 	.emac_init = ravb_emac_init_rcar,
2466 	.gstrings_stats = ravb_gstrings_stats,
2467 	.gstrings_size = sizeof(ravb_gstrings_stats),
2468 	.net_hw_features = NETIF_F_RXCSUM,
2469 	.net_features = NETIF_F_RXCSUM,
2470 	.stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2471 	.max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2472 	.tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2473 	.rx_max_buf_size = SZ_2K,
2474 	.aligned_tx = 1,
2475 	.gptp = 1,
2476 	.nc_queues = 1,
2477 	.magic_pkt = 1,
2478 };
2479 
2480 static const struct ravb_hw_info ravb_rzv2m_hw_info = {
2481 	.rx_ring_free = ravb_rx_ring_free_rcar,
2482 	.rx_ring_format = ravb_rx_ring_format_rcar,
2483 	.alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2484 	.receive = ravb_rx_rcar,
2485 	.set_rate = ravb_set_rate_rcar,
2486 	.set_feature = ravb_set_features_rcar,
2487 	.dmac_init = ravb_dmac_init_rcar,
2488 	.emac_init = ravb_emac_init_rcar,
2489 	.gstrings_stats = ravb_gstrings_stats,
2490 	.gstrings_size = sizeof(ravb_gstrings_stats),
2491 	.net_hw_features = NETIF_F_RXCSUM,
2492 	.net_features = NETIF_F_RXCSUM,
2493 	.stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2494 	.max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2495 	.tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2496 	.rx_max_buf_size = SZ_2K,
2497 	.multi_irqs = 1,
2498 	.err_mgmt_irqs = 1,
2499 	.gptp = 1,
2500 	.gptp_ref_clk = 1,
2501 	.nc_queues = 1,
2502 	.magic_pkt = 1,
2503 };
2504 
2505 static const struct ravb_hw_info gbeth_hw_info = {
2506 	.rx_ring_free = ravb_rx_ring_free_gbeth,
2507 	.rx_ring_format = ravb_rx_ring_format_gbeth,
2508 	.alloc_rx_desc = ravb_alloc_rx_desc_gbeth,
2509 	.receive = ravb_rx_gbeth,
2510 	.set_rate = ravb_set_rate_gbeth,
2511 	.set_feature = ravb_set_features_gbeth,
2512 	.dmac_init = ravb_dmac_init_gbeth,
2513 	.emac_init = ravb_emac_init_gbeth,
2514 	.gstrings_stats = ravb_gstrings_stats_gbeth,
2515 	.gstrings_size = sizeof(ravb_gstrings_stats_gbeth),
2516 	.stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth),
2517 	.max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN),
2518 	.tccr_mask = TCCR_TSRQ0,
2519 	.rx_max_buf_size = SZ_8K,
2520 	.aligned_tx = 1,
2521 	.tx_counters = 1,
2522 	.carrier_counters = 1,
2523 	.half_duplex = 1,
2524 };
2525 
2526 static const struct of_device_id ravb_match_table[] = {
2527 	{ .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info },
2528 	{ .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info },
2529 	{ .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
2530 	{ .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
2531 	{ .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
2532 	{ .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info },
2533 	{ .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info },
2534 	{ .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info },
2535 	{ }
2536 };
2537 MODULE_DEVICE_TABLE(of, ravb_match_table);
2538 
2539 static int ravb_set_gti(struct net_device *ndev)
2540 {
2541 	struct ravb_private *priv = netdev_priv(ndev);
2542 	const struct ravb_hw_info *info = priv->info;
2543 	struct device *dev = ndev->dev.parent;
2544 	unsigned long rate;
2545 	uint64_t inc;
2546 
2547 	if (info->gptp_ref_clk)
2548 		rate = clk_get_rate(priv->gptp_clk);
2549 	else
2550 		rate = clk_get_rate(priv->clk);
2551 	if (!rate)
2552 		return -EINVAL;
2553 
2554 	inc = div64_ul(1000000000ULL << 20, rate);
2555 
2556 	if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
2557 		dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
2558 			inc, GTI_TIV_MIN, GTI_TIV_MAX);
2559 		return -EINVAL;
2560 	}
2561 
2562 	ravb_write(ndev, inc, GTI);
2563 
2564 	return 0;
2565 }
2566 
2567 static int ravb_set_config_mode(struct net_device *ndev)
2568 {
2569 	struct ravb_private *priv = netdev_priv(ndev);
2570 	const struct ravb_hw_info *info = priv->info;
2571 	int error;
2572 
2573 	if (info->gptp) {
2574 		error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);
2575 		if (error)
2576 			return error;
2577 		/* Set CSEL value */
2578 		ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
2579 	} else if (info->ccc_gac) {
2580 		error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB);
2581 	} else {
2582 		error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);
2583 	}
2584 
2585 	return error;
2586 }
2587 
2588 /* Set tx and rx clock internal delay modes */
2589 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
2590 {
2591 	struct ravb_private *priv = netdev_priv(ndev);
2592 	bool explicit_delay = false;
2593 	u32 delay;
2594 
2595 	if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
2596 		/* Valid values are 0 and 1800, according to DT bindings */
2597 		priv->rxcidm = !!delay;
2598 		explicit_delay = true;
2599 	}
2600 	if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
2601 		/* Valid values are 0 and 2000, according to DT bindings */
2602 		priv->txcidm = !!delay;
2603 		explicit_delay = true;
2604 	}
2605 
2606 	if (explicit_delay)
2607 		return;
2608 
2609 	/* Fall back to legacy rgmii-*id behavior */
2610 	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2611 	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
2612 		priv->rxcidm = 1;
2613 		priv->rgmii_override = 1;
2614 	}
2615 
2616 	if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2617 	    priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2618 		priv->txcidm = 1;
2619 		priv->rgmii_override = 1;
2620 	}
2621 }
2622 
2623 static void ravb_set_delay_mode(struct net_device *ndev)
2624 {
2625 	struct ravb_private *priv = netdev_priv(ndev);
2626 	u32 set = 0;
2627 
2628 	if (priv->rxcidm)
2629 		set |= APSR_RDM;
2630 	if (priv->txcidm)
2631 		set |= APSR_TDM;
2632 	ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set);
2633 }
2634 
2635 static int ravb_probe(struct platform_device *pdev)
2636 {
2637 	struct device_node *np = pdev->dev.of_node;
2638 	const struct ravb_hw_info *info;
2639 	struct reset_control *rstc;
2640 	struct ravb_private *priv;
2641 	struct net_device *ndev;
2642 	int error, irq, q;
2643 	struct resource *res;
2644 	int i;
2645 
2646 	if (!np) {
2647 		dev_err(&pdev->dev,
2648 			"this driver is required to be instantiated from device tree\n");
2649 		return -EINVAL;
2650 	}
2651 
2652 	rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
2653 	if (IS_ERR(rstc))
2654 		return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
2655 				     "failed to get cpg reset\n");
2656 
2657 	ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2658 				  NUM_TX_QUEUE, NUM_RX_QUEUE);
2659 	if (!ndev)
2660 		return -ENOMEM;
2661 
2662 	info = of_device_get_match_data(&pdev->dev);
2663 
2664 	ndev->features = info->net_features;
2665 	ndev->hw_features = info->net_hw_features;
2666 
2667 	error = reset_control_deassert(rstc);
2668 	if (error)
2669 		goto out_free_netdev;
2670 
2671 	pm_runtime_enable(&pdev->dev);
2672 	error = pm_runtime_resume_and_get(&pdev->dev);
2673 	if (error < 0)
2674 		goto out_rpm_disable;
2675 
2676 	if (info->multi_irqs) {
2677 		if (info->err_mgmt_irqs)
2678 			irq = platform_get_irq_byname(pdev, "dia");
2679 		else
2680 			irq = platform_get_irq_byname(pdev, "ch22");
2681 	} else {
2682 		irq = platform_get_irq(pdev, 0);
2683 	}
2684 	if (irq < 0) {
2685 		error = irq;
2686 		goto out_release;
2687 	}
2688 	ndev->irq = irq;
2689 
2690 	SET_NETDEV_DEV(ndev, &pdev->dev);
2691 
2692 	priv = netdev_priv(ndev);
2693 	priv->info = info;
2694 	priv->rstc = rstc;
2695 	priv->ndev = ndev;
2696 	priv->pdev = pdev;
2697 	priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2698 	priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2699 	if (info->nc_queues) {
2700 		priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2701 		priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2702 	}
2703 
2704 	priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2705 	if (IS_ERR(priv->addr)) {
2706 		error = PTR_ERR(priv->addr);
2707 		goto out_release;
2708 	}
2709 
2710 	/* The Ether-specific entries in the device structure. */
2711 	ndev->base_addr = res->start;
2712 
2713 	spin_lock_init(&priv->lock);
2714 	INIT_WORK(&priv->work, ravb_tx_timeout_work);
2715 
2716 	error = of_get_phy_mode(np, &priv->phy_interface);
2717 	if (error && error != -ENODEV)
2718 		goto out_release;
2719 
2720 	priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2721 	priv->avb_link_active_low =
2722 		of_property_read_bool(np, "renesas,ether-link-active-low");
2723 
2724 	if (info->multi_irqs) {
2725 		if (info->err_mgmt_irqs)
2726 			irq = platform_get_irq_byname(pdev, "line3");
2727 		else
2728 			irq = platform_get_irq_byname(pdev, "ch24");
2729 		if (irq < 0) {
2730 			error = irq;
2731 			goto out_release;
2732 		}
2733 		priv->emac_irq = irq;
2734 		for (i = 0; i < NUM_RX_QUEUE; i++) {
2735 			irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2736 			if (irq < 0) {
2737 				error = irq;
2738 				goto out_release;
2739 			}
2740 			priv->rx_irqs[i] = irq;
2741 		}
2742 		for (i = 0; i < NUM_TX_QUEUE; i++) {
2743 			irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2744 			if (irq < 0) {
2745 				error = irq;
2746 				goto out_release;
2747 			}
2748 			priv->tx_irqs[i] = irq;
2749 		}
2750 
2751 		if (info->err_mgmt_irqs) {
2752 			irq = platform_get_irq_byname(pdev, "err_a");
2753 			if (irq < 0) {
2754 				error = irq;
2755 				goto out_release;
2756 			}
2757 			priv->erra_irq = irq;
2758 
2759 			irq = platform_get_irq_byname(pdev, "mgmt_a");
2760 			if (irq < 0) {
2761 				error = irq;
2762 				goto out_release;
2763 			}
2764 			priv->mgmta_irq = irq;
2765 		}
2766 	}
2767 
2768 	priv->clk = devm_clk_get(&pdev->dev, NULL);
2769 	if (IS_ERR(priv->clk)) {
2770 		error = PTR_ERR(priv->clk);
2771 		goto out_release;
2772 	}
2773 
2774 	priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk");
2775 	if (IS_ERR(priv->refclk)) {
2776 		error = PTR_ERR(priv->refclk);
2777 		goto out_release;
2778 	}
2779 	clk_prepare_enable(priv->refclk);
2780 
2781 	if (info->gptp_ref_clk) {
2782 		priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
2783 		if (IS_ERR(priv->gptp_clk)) {
2784 			error = PTR_ERR(priv->gptp_clk);
2785 			goto out_disable_refclk;
2786 		}
2787 		clk_prepare_enable(priv->gptp_clk);
2788 	}
2789 
2790 	ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2791 	ndev->min_mtu = ETH_MIN_MTU;
2792 
2793 	/* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer
2794 	 * Use two descriptor to handle such situation. First descriptor to
2795 	 * handle aligned data buffer and second descriptor to handle the
2796 	 * overflow data because of alignment.
2797 	 */
2798 	priv->num_tx_desc = info->aligned_tx ? 2 : 1;
2799 
2800 	/* Set function */
2801 	ndev->netdev_ops = &ravb_netdev_ops;
2802 	ndev->ethtool_ops = &ravb_ethtool_ops;
2803 
2804 	/* Set AVB config mode */
2805 	error = ravb_set_config_mode(ndev);
2806 	if (error)
2807 		goto out_disable_gptp_clk;
2808 
2809 	if (info->gptp || info->ccc_gac) {
2810 		/* Set GTI value */
2811 		error = ravb_set_gti(ndev);
2812 		if (error)
2813 			goto out_disable_gptp_clk;
2814 
2815 		/* Request GTI loading */
2816 		ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2817 	}
2818 
2819 	if (info->internal_delay) {
2820 		ravb_parse_delay_mode(np, ndev);
2821 		ravb_set_delay_mode(ndev);
2822 	}
2823 
2824 	/* Allocate descriptor base address table */
2825 	priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2826 	priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2827 					    &priv->desc_bat_dma, GFP_KERNEL);
2828 	if (!priv->desc_bat) {
2829 		dev_err(&pdev->dev,
2830 			"Cannot allocate desc base address table (size %d bytes)\n",
2831 			priv->desc_bat_size);
2832 		error = -ENOMEM;
2833 		goto out_disable_gptp_clk;
2834 	}
2835 	for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2836 		priv->desc_bat[q].die_dt = DT_EOS;
2837 	ravb_write(ndev, priv->desc_bat_dma, DBAT);
2838 
2839 	/* Initialise HW timestamp list */
2840 	INIT_LIST_HEAD(&priv->ts_skb_list);
2841 
2842 	/* Initialise PTP Clock driver */
2843 	if (info->ccc_gac)
2844 		ravb_ptp_init(ndev, pdev);
2845 
2846 	/* Debug message level */
2847 	priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2848 
2849 	/* Read and set MAC address */
2850 	ravb_read_mac_address(np, ndev);
2851 	if (!is_valid_ether_addr(ndev->dev_addr)) {
2852 		dev_warn(&pdev->dev,
2853 			 "no valid MAC address supplied, using a random one\n");
2854 		eth_hw_addr_random(ndev);
2855 	}
2856 
2857 	/* MDIO bus init */
2858 	error = ravb_mdio_init(priv);
2859 	if (error) {
2860 		dev_err(&pdev->dev, "failed to initialize MDIO\n");
2861 		goto out_dma_free;
2862 	}
2863 
2864 	netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll);
2865 	if (info->nc_queues)
2866 		netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll);
2867 
2868 	/* Network device register */
2869 	error = register_netdev(ndev);
2870 	if (error)
2871 		goto out_napi_del;
2872 
2873 	device_set_wakeup_capable(&pdev->dev, 1);
2874 
2875 	/* Print device information */
2876 	netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2877 		    (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2878 
2879 	platform_set_drvdata(pdev, ndev);
2880 
2881 	return 0;
2882 
2883 out_napi_del:
2884 	if (info->nc_queues)
2885 		netif_napi_del(&priv->napi[RAVB_NC]);
2886 
2887 	netif_napi_del(&priv->napi[RAVB_BE]);
2888 	ravb_mdio_release(priv);
2889 out_dma_free:
2890 	dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2891 			  priv->desc_bat_dma);
2892 
2893 	/* Stop PTP Clock driver */
2894 	if (info->ccc_gac)
2895 		ravb_ptp_stop(ndev);
2896 out_disable_gptp_clk:
2897 	clk_disable_unprepare(priv->gptp_clk);
2898 out_disable_refclk:
2899 	clk_disable_unprepare(priv->refclk);
2900 out_release:
2901 	pm_runtime_put(&pdev->dev);
2902 out_rpm_disable:
2903 	pm_runtime_disable(&pdev->dev);
2904 	reset_control_assert(rstc);
2905 out_free_netdev:
2906 	free_netdev(ndev);
2907 	return error;
2908 }
2909 
2910 static int ravb_remove(struct platform_device *pdev)
2911 {
2912 	struct net_device *ndev = platform_get_drvdata(pdev);
2913 	struct ravb_private *priv = netdev_priv(ndev);
2914 	const struct ravb_hw_info *info = priv->info;
2915 
2916 	unregister_netdev(ndev);
2917 	if (info->nc_queues)
2918 		netif_napi_del(&priv->napi[RAVB_NC]);
2919 	netif_napi_del(&priv->napi[RAVB_BE]);
2920 
2921 	ravb_mdio_release(priv);
2922 
2923 	/* Stop PTP Clock driver */
2924 	if (info->ccc_gac)
2925 		ravb_ptp_stop(ndev);
2926 
2927 	dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2928 			  priv->desc_bat_dma);
2929 
2930 	ravb_set_opmode(ndev, CCC_OPC_RESET);
2931 
2932 	clk_disable_unprepare(priv->gptp_clk);
2933 	clk_disable_unprepare(priv->refclk);
2934 
2935 	pm_runtime_put_sync(&pdev->dev);
2936 	pm_runtime_disable(&pdev->dev);
2937 	reset_control_assert(priv->rstc);
2938 	free_netdev(ndev);
2939 	platform_set_drvdata(pdev, NULL);
2940 
2941 	return 0;
2942 }
2943 
2944 static int ravb_wol_setup(struct net_device *ndev)
2945 {
2946 	struct ravb_private *priv = netdev_priv(ndev);
2947 	const struct ravb_hw_info *info = priv->info;
2948 
2949 	/* Disable interrupts by clearing the interrupt masks. */
2950 	ravb_write(ndev, 0, RIC0);
2951 	ravb_write(ndev, 0, RIC2);
2952 	ravb_write(ndev, 0, TIC);
2953 
2954 	/* Only allow ECI interrupts */
2955 	synchronize_irq(priv->emac_irq);
2956 	if (info->nc_queues)
2957 		napi_disable(&priv->napi[RAVB_NC]);
2958 	napi_disable(&priv->napi[RAVB_BE]);
2959 	ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2960 
2961 	/* Enable MagicPacket */
2962 	ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2963 
2964 	return enable_irq_wake(priv->emac_irq);
2965 }
2966 
2967 static int ravb_wol_restore(struct net_device *ndev)
2968 {
2969 	struct ravb_private *priv = netdev_priv(ndev);
2970 	const struct ravb_hw_info *info = priv->info;
2971 
2972 	if (info->nc_queues)
2973 		napi_enable(&priv->napi[RAVB_NC]);
2974 	napi_enable(&priv->napi[RAVB_BE]);
2975 
2976 	/* Disable MagicPacket */
2977 	ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2978 
2979 	ravb_close(ndev);
2980 
2981 	return disable_irq_wake(priv->emac_irq);
2982 }
2983 
2984 static int __maybe_unused ravb_suspend(struct device *dev)
2985 {
2986 	struct net_device *ndev = dev_get_drvdata(dev);
2987 	struct ravb_private *priv = netdev_priv(ndev);
2988 	int ret;
2989 
2990 	if (!netif_running(ndev))
2991 		return 0;
2992 
2993 	netif_device_detach(ndev);
2994 
2995 	if (priv->wol_enabled)
2996 		ret = ravb_wol_setup(ndev);
2997 	else
2998 		ret = ravb_close(ndev);
2999 
3000 	if (priv->info->ccc_gac)
3001 		ravb_ptp_stop(ndev);
3002 
3003 	return ret;
3004 }
3005 
3006 static int __maybe_unused ravb_resume(struct device *dev)
3007 {
3008 	struct net_device *ndev = dev_get_drvdata(dev);
3009 	struct ravb_private *priv = netdev_priv(ndev);
3010 	const struct ravb_hw_info *info = priv->info;
3011 	int ret = 0;
3012 
3013 	/* If WoL is enabled set reset mode to rearm the WoL logic */
3014 	if (priv->wol_enabled) {
3015 		ret = ravb_set_opmode(ndev, CCC_OPC_RESET);
3016 		if (ret)
3017 			return ret;
3018 	}
3019 
3020 	/* All register have been reset to default values.
3021 	 * Restore all registers which where setup at probe time and
3022 	 * reopen device if it was running before system suspended.
3023 	 */
3024 
3025 	/* Set AVB config mode */
3026 	ret = ravb_set_config_mode(ndev);
3027 	if (ret)
3028 		return ret;
3029 
3030 	if (info->gptp || info->ccc_gac) {
3031 		/* Set GTI value */
3032 		ret = ravb_set_gti(ndev);
3033 		if (ret)
3034 			return ret;
3035 
3036 		/* Request GTI loading */
3037 		ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
3038 	}
3039 
3040 	if (info->internal_delay)
3041 		ravb_set_delay_mode(ndev);
3042 
3043 	/* Restore descriptor base address table */
3044 	ravb_write(ndev, priv->desc_bat_dma, DBAT);
3045 
3046 	if (priv->info->ccc_gac)
3047 		ravb_ptp_init(ndev, priv->pdev);
3048 
3049 	if (netif_running(ndev)) {
3050 		if (priv->wol_enabled) {
3051 			ret = ravb_wol_restore(ndev);
3052 			if (ret)
3053 				return ret;
3054 		}
3055 		ret = ravb_open(ndev);
3056 		if (ret < 0)
3057 			return ret;
3058 		ravb_set_rx_mode(ndev);
3059 		netif_device_attach(ndev);
3060 	}
3061 
3062 	return ret;
3063 }
3064 
3065 static int __maybe_unused ravb_runtime_nop(struct device *dev)
3066 {
3067 	/* Runtime PM callback shared between ->runtime_suspend()
3068 	 * and ->runtime_resume(). Simply returns success.
3069 	 *
3070 	 * This driver re-initializes all registers after
3071 	 * pm_runtime_get_sync() anyway so there is no need
3072 	 * to save and restore registers here.
3073 	 */
3074 	return 0;
3075 }
3076 
3077 static const struct dev_pm_ops ravb_dev_pm_ops = {
3078 	SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
3079 	SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
3080 };
3081 
3082 static struct platform_driver ravb_driver = {
3083 	.probe		= ravb_probe,
3084 	.remove		= ravb_remove,
3085 	.driver = {
3086 		.name	= "ravb",
3087 		.pm	= &ravb_dev_pm_ops,
3088 		.of_match_table = ravb_match_table,
3089 	},
3090 };
3091 
3092 module_platform_driver(ravb_driver);
3093 
3094 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
3095 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
3096 MODULE_LICENSE("GPL v2");
3097