1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 33 #include "ravb.h" 34 35 #define RAVB_DEF_MSG_ENABLE \ 36 (NETIF_MSG_LINK | \ 37 NETIF_MSG_TIMER | \ 38 NETIF_MSG_RX_ERR | \ 39 NETIF_MSG_TX_ERR) 40 41 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 42 "ch0", /* RAVB_BE */ 43 "ch1", /* RAVB_NC */ 44 }; 45 46 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 47 "ch18", /* RAVB_BE */ 48 "ch19", /* RAVB_NC */ 49 }; 50 51 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 52 u32 set) 53 { 54 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 55 } 56 57 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 58 { 59 int i; 60 61 for (i = 0; i < 10000; i++) { 62 if ((ravb_read(ndev, reg) & mask) == value) 63 return 0; 64 udelay(10); 65 } 66 return -ETIMEDOUT; 67 } 68 69 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 70 { 71 u32 csr_ops = 1U << (opmode & CCC_OPC); 72 u32 ccc_mask = CCC_OPC; 73 int error; 74 75 /* If gPTP active in config mode is supported it needs to be configured 76 * along with CSEL and operating mode in the same access. This is a 77 * hardware limitation. 78 */ 79 if (opmode & CCC_GAC) 80 ccc_mask |= CCC_GAC | CCC_CSEL; 81 82 /* Set operating mode */ 83 ravb_modify(ndev, CCC, ccc_mask, opmode); 84 /* Check if the operating mode is changed to the requested one */ 85 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 86 if (error) { 87 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 88 opmode & CCC_OPC); 89 } 90 91 return error; 92 } 93 94 static void ravb_set_rate_gbeth(struct net_device *ndev) 95 { 96 struct ravb_private *priv = netdev_priv(ndev); 97 98 switch (priv->speed) { 99 case 10: /* 10BASE */ 100 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 101 break; 102 case 100: /* 100BASE */ 103 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 104 break; 105 case 1000: /* 1000BASE */ 106 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 107 break; 108 } 109 } 110 111 static void ravb_set_rate_rcar(struct net_device *ndev) 112 { 113 struct ravb_private *priv = netdev_priv(ndev); 114 115 switch (priv->speed) { 116 case 100: /* 100BASE */ 117 ravb_write(ndev, GECMR_SPEED_100, GECMR); 118 break; 119 case 1000: /* 1000BASE */ 120 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 121 break; 122 } 123 } 124 125 static void ravb_set_buffer_align(struct sk_buff *skb) 126 { 127 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 128 129 if (reserve) 130 skb_reserve(skb, RAVB_ALIGN - reserve); 131 } 132 133 /* Get MAC address from the MAC address registers 134 * 135 * Ethernet AVB device doesn't have ROM for MAC address. 136 * This function gets the MAC address that was used by a bootloader. 137 */ 138 static void ravb_read_mac_address(struct device_node *np, 139 struct net_device *ndev) 140 { 141 int ret; 142 143 ret = of_get_ethdev_address(np, ndev); 144 if (ret) { 145 u32 mahr = ravb_read(ndev, MAHR); 146 u32 malr = ravb_read(ndev, MALR); 147 u8 addr[ETH_ALEN]; 148 149 addr[0] = (mahr >> 24) & 0xFF; 150 addr[1] = (mahr >> 16) & 0xFF; 151 addr[2] = (mahr >> 8) & 0xFF; 152 addr[3] = (mahr >> 0) & 0xFF; 153 addr[4] = (malr >> 8) & 0xFF; 154 addr[5] = (malr >> 0) & 0xFF; 155 eth_hw_addr_set(ndev, addr); 156 } 157 } 158 159 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 160 { 161 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 162 mdiobb); 163 164 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 165 } 166 167 /* MDC pin control */ 168 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 169 { 170 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 171 } 172 173 /* Data I/O pin control */ 174 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 175 { 176 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 177 } 178 179 /* Set data bit */ 180 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 181 { 182 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 183 } 184 185 /* Get data bit */ 186 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 187 { 188 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 189 mdiobb); 190 191 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 192 } 193 194 /* MDIO bus control struct */ 195 static const struct mdiobb_ops bb_ops = { 196 .owner = THIS_MODULE, 197 .set_mdc = ravb_set_mdc, 198 .set_mdio_dir = ravb_set_mdio_dir, 199 .set_mdio_data = ravb_set_mdio_data, 200 .get_mdio_data = ravb_get_mdio_data, 201 }; 202 203 /* Free TX skb function for AVB-IP */ 204 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 205 { 206 struct ravb_private *priv = netdev_priv(ndev); 207 struct net_device_stats *stats = &priv->stats[q]; 208 unsigned int num_tx_desc = priv->num_tx_desc; 209 struct ravb_tx_desc *desc; 210 unsigned int entry; 211 int free_num = 0; 212 u32 size; 213 214 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 215 bool txed; 216 217 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 218 num_tx_desc); 219 desc = &priv->tx_ring[q][entry]; 220 txed = desc->die_dt == DT_FEMPTY; 221 if (free_txed_only && !txed) 222 break; 223 /* Descriptor type must be checked before all other reads */ 224 dma_rmb(); 225 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 226 /* Free the original skb. */ 227 if (priv->tx_skb[q][entry / num_tx_desc]) { 228 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 229 size, DMA_TO_DEVICE); 230 /* Last packet descriptor? */ 231 if (entry % num_tx_desc == num_tx_desc - 1) { 232 entry /= num_tx_desc; 233 dev_kfree_skb_any(priv->tx_skb[q][entry]); 234 priv->tx_skb[q][entry] = NULL; 235 if (txed) 236 stats->tx_packets++; 237 } 238 free_num++; 239 } 240 if (txed) 241 stats->tx_bytes += size; 242 desc->die_dt = DT_EEMPTY; 243 } 244 return free_num; 245 } 246 247 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 248 { 249 struct ravb_private *priv = netdev_priv(ndev); 250 unsigned int ring_size; 251 unsigned int i; 252 253 if (!priv->gbeth_rx_ring) 254 return; 255 256 for (i = 0; i < priv->num_rx_ring[q]; i++) { 257 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i]; 258 259 if (!dma_mapping_error(ndev->dev.parent, 260 le32_to_cpu(desc->dptr))) 261 dma_unmap_single(ndev->dev.parent, 262 le32_to_cpu(desc->dptr), 263 GBETH_RX_BUFF_MAX, 264 DMA_FROM_DEVICE); 265 } 266 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 267 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring, 268 priv->rx_desc_dma[q]); 269 priv->gbeth_rx_ring = NULL; 270 } 271 272 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q) 273 { 274 struct ravb_private *priv = netdev_priv(ndev); 275 unsigned int ring_size; 276 unsigned int i; 277 278 if (!priv->rx_ring[q]) 279 return; 280 281 for (i = 0; i < priv->num_rx_ring[q]; i++) { 282 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 283 284 if (!dma_mapping_error(ndev->dev.parent, 285 le32_to_cpu(desc->dptr))) 286 dma_unmap_single(ndev->dev.parent, 287 le32_to_cpu(desc->dptr), 288 RX_BUF_SZ, 289 DMA_FROM_DEVICE); 290 } 291 ring_size = sizeof(struct ravb_ex_rx_desc) * 292 (priv->num_rx_ring[q] + 1); 293 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 294 priv->rx_desc_dma[q]); 295 priv->rx_ring[q] = NULL; 296 } 297 298 /* Free skb's and DMA buffers for Ethernet AVB */ 299 static void ravb_ring_free(struct net_device *ndev, int q) 300 { 301 struct ravb_private *priv = netdev_priv(ndev); 302 const struct ravb_hw_info *info = priv->info; 303 unsigned int num_tx_desc = priv->num_tx_desc; 304 unsigned int ring_size; 305 unsigned int i; 306 307 info->rx_ring_free(ndev, q); 308 309 if (priv->tx_ring[q]) { 310 ravb_tx_free(ndev, q, false); 311 312 ring_size = sizeof(struct ravb_tx_desc) * 313 (priv->num_tx_ring[q] * num_tx_desc + 1); 314 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 315 priv->tx_desc_dma[q]); 316 priv->tx_ring[q] = NULL; 317 } 318 319 /* Free RX skb ringbuffer */ 320 if (priv->rx_skb[q]) { 321 for (i = 0; i < priv->num_rx_ring[q]; i++) 322 dev_kfree_skb(priv->rx_skb[q][i]); 323 } 324 kfree(priv->rx_skb[q]); 325 priv->rx_skb[q] = NULL; 326 327 /* Free aligned TX buffers */ 328 kfree(priv->tx_align[q]); 329 priv->tx_align[q] = NULL; 330 331 /* Free TX skb ringbuffer. 332 * SKBs are freed by ravb_tx_free() call above. 333 */ 334 kfree(priv->tx_skb[q]); 335 priv->tx_skb[q] = NULL; 336 } 337 338 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 339 { 340 struct ravb_private *priv = netdev_priv(ndev); 341 struct ravb_rx_desc *rx_desc; 342 unsigned int rx_ring_size; 343 dma_addr_t dma_addr; 344 unsigned int i; 345 346 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 347 memset(priv->gbeth_rx_ring, 0, rx_ring_size); 348 /* Build RX ring buffer */ 349 for (i = 0; i < priv->num_rx_ring[q]; i++) { 350 /* RX descriptor */ 351 rx_desc = &priv->gbeth_rx_ring[i]; 352 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 353 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 354 GBETH_RX_BUFF_MAX, 355 DMA_FROM_DEVICE); 356 /* We just set the data size to 0 for a failed mapping which 357 * should prevent DMA from happening... 358 */ 359 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 360 rx_desc->ds_cc = cpu_to_le16(0); 361 rx_desc->dptr = cpu_to_le32(dma_addr); 362 rx_desc->die_dt = DT_FEMPTY; 363 } 364 rx_desc = &priv->gbeth_rx_ring[i]; 365 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 366 rx_desc->die_dt = DT_LINKFIX; /* type */ 367 } 368 369 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q) 370 { 371 struct ravb_private *priv = netdev_priv(ndev); 372 struct ravb_ex_rx_desc *rx_desc; 373 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 374 dma_addr_t dma_addr; 375 unsigned int i; 376 377 memset(priv->rx_ring[q], 0, rx_ring_size); 378 /* Build RX ring buffer */ 379 for (i = 0; i < priv->num_rx_ring[q]; i++) { 380 /* RX descriptor */ 381 rx_desc = &priv->rx_ring[q][i]; 382 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 383 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 384 RX_BUF_SZ, 385 DMA_FROM_DEVICE); 386 /* We just set the data size to 0 for a failed mapping which 387 * should prevent DMA from happening... 388 */ 389 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 390 rx_desc->ds_cc = cpu_to_le16(0); 391 rx_desc->dptr = cpu_to_le32(dma_addr); 392 rx_desc->die_dt = DT_FEMPTY; 393 } 394 rx_desc = &priv->rx_ring[q][i]; 395 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 396 rx_desc->die_dt = DT_LINKFIX; /* type */ 397 } 398 399 /* Format skb and descriptor buffer for Ethernet AVB */ 400 static void ravb_ring_format(struct net_device *ndev, int q) 401 { 402 struct ravb_private *priv = netdev_priv(ndev); 403 const struct ravb_hw_info *info = priv->info; 404 unsigned int num_tx_desc = priv->num_tx_desc; 405 struct ravb_tx_desc *tx_desc; 406 struct ravb_desc *desc; 407 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 408 num_tx_desc; 409 unsigned int i; 410 411 priv->cur_rx[q] = 0; 412 priv->cur_tx[q] = 0; 413 priv->dirty_rx[q] = 0; 414 priv->dirty_tx[q] = 0; 415 416 info->rx_ring_format(ndev, q); 417 418 memset(priv->tx_ring[q], 0, tx_ring_size); 419 /* Build TX ring buffer */ 420 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 421 i++, tx_desc++) { 422 tx_desc->die_dt = DT_EEMPTY; 423 if (num_tx_desc > 1) { 424 tx_desc++; 425 tx_desc->die_dt = DT_EEMPTY; 426 } 427 } 428 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 429 tx_desc->die_dt = DT_LINKFIX; /* type */ 430 431 /* RX descriptor base address for best effort */ 432 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 433 desc->die_dt = DT_LINKFIX; /* type */ 434 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 435 436 /* TX descriptor base address for best effort */ 437 desc = &priv->desc_bat[q]; 438 desc->die_dt = DT_LINKFIX; /* type */ 439 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 440 } 441 442 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 443 { 444 struct ravb_private *priv = netdev_priv(ndev); 445 unsigned int ring_size; 446 447 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 448 449 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size, 450 &priv->rx_desc_dma[q], 451 GFP_KERNEL); 452 return priv->gbeth_rx_ring; 453 } 454 455 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q) 456 { 457 struct ravb_private *priv = netdev_priv(ndev); 458 unsigned int ring_size; 459 460 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 461 462 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 463 &priv->rx_desc_dma[q], 464 GFP_KERNEL); 465 return priv->rx_ring[q]; 466 } 467 468 /* Init skb and descriptor buffer for Ethernet AVB */ 469 static int ravb_ring_init(struct net_device *ndev, int q) 470 { 471 struct ravb_private *priv = netdev_priv(ndev); 472 const struct ravb_hw_info *info = priv->info; 473 unsigned int num_tx_desc = priv->num_tx_desc; 474 unsigned int ring_size; 475 struct sk_buff *skb; 476 unsigned int i; 477 478 /* Allocate RX and TX skb rings */ 479 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 480 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 481 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 482 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 483 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 484 goto error; 485 486 for (i = 0; i < priv->num_rx_ring[q]; i++) { 487 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL); 488 if (!skb) 489 goto error; 490 ravb_set_buffer_align(skb); 491 priv->rx_skb[q][i] = skb; 492 } 493 494 if (num_tx_desc > 1) { 495 /* Allocate rings for the aligned buffers */ 496 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 497 DPTR_ALIGN - 1, GFP_KERNEL); 498 if (!priv->tx_align[q]) 499 goto error; 500 } 501 502 /* Allocate all RX descriptors. */ 503 if (!info->alloc_rx_desc(ndev, q)) 504 goto error; 505 506 priv->dirty_rx[q] = 0; 507 508 /* Allocate all TX descriptors. */ 509 ring_size = sizeof(struct ravb_tx_desc) * 510 (priv->num_tx_ring[q] * num_tx_desc + 1); 511 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 512 &priv->tx_desc_dma[q], 513 GFP_KERNEL); 514 if (!priv->tx_ring[q]) 515 goto error; 516 517 return 0; 518 519 error: 520 ravb_ring_free(ndev, q); 521 522 return -ENOMEM; 523 } 524 525 static void ravb_emac_init_gbeth(struct net_device *ndev) 526 { 527 struct ravb_private *priv = netdev_priv(ndev); 528 529 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 530 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 531 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 532 } else { 533 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 534 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 535 CXR31_SEL_LINK0); 536 } 537 538 /* Receive frame limit set register */ 539 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 540 541 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 542 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 543 ECMR_TE | ECMR_RE | ECMR_RCPT | 544 ECMR_TXF | ECMR_RXF, ECMR); 545 546 ravb_set_rate_gbeth(ndev); 547 548 /* Set MAC address */ 549 ravb_write(ndev, 550 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 551 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 552 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 553 554 /* E-MAC status register clear */ 555 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 556 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 557 558 /* E-MAC interrupt enable register */ 559 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 560 } 561 562 static void ravb_emac_init_rcar(struct net_device *ndev) 563 { 564 /* Receive frame limit set register */ 565 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 566 567 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 568 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 569 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 570 ECMR_TE | ECMR_RE, ECMR); 571 572 ravb_set_rate_rcar(ndev); 573 574 /* Set MAC address */ 575 ravb_write(ndev, 576 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 577 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 578 ravb_write(ndev, 579 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 580 581 /* E-MAC status register clear */ 582 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 583 584 /* E-MAC interrupt enable register */ 585 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 586 } 587 588 /* E-MAC init function */ 589 static void ravb_emac_init(struct net_device *ndev) 590 { 591 struct ravb_private *priv = netdev_priv(ndev); 592 const struct ravb_hw_info *info = priv->info; 593 594 info->emac_init(ndev); 595 } 596 597 static int ravb_dmac_init_gbeth(struct net_device *ndev) 598 { 599 int error; 600 601 error = ravb_ring_init(ndev, RAVB_BE); 602 if (error) 603 return error; 604 605 /* Descriptor format */ 606 ravb_ring_format(ndev, RAVB_BE); 607 608 /* Set DMAC RX */ 609 ravb_write(ndev, 0x60000000, RCR); 610 611 /* Set Max Frame Length (RTC) */ 612 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 613 614 /* Set FIFO size */ 615 ravb_write(ndev, 0x00222200, TGC); 616 617 ravb_write(ndev, 0, TCCR); 618 619 /* Frame receive */ 620 ravb_write(ndev, RIC0_FRE0, RIC0); 621 /* Disable FIFO full warning */ 622 ravb_write(ndev, 0x0, RIC1); 623 /* Receive FIFO full error, descriptor empty */ 624 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 625 626 ravb_write(ndev, TIC_FTE0, TIC); 627 628 return 0; 629 } 630 631 static int ravb_dmac_init_rcar(struct net_device *ndev) 632 { 633 struct ravb_private *priv = netdev_priv(ndev); 634 const struct ravb_hw_info *info = priv->info; 635 int error; 636 637 error = ravb_ring_init(ndev, RAVB_BE); 638 if (error) 639 return error; 640 error = ravb_ring_init(ndev, RAVB_NC); 641 if (error) { 642 ravb_ring_free(ndev, RAVB_BE); 643 return error; 644 } 645 646 /* Descriptor format */ 647 ravb_ring_format(ndev, RAVB_BE); 648 ravb_ring_format(ndev, RAVB_NC); 649 650 /* Set AVB RX */ 651 ravb_write(ndev, 652 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 653 654 /* Set FIFO size */ 655 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 656 657 /* Timestamp enable */ 658 ravb_write(ndev, TCCR_TFEN, TCCR); 659 660 /* Interrupt init: */ 661 if (info->multi_irqs) { 662 /* Clear DIL.DPLx */ 663 ravb_write(ndev, 0, DIL); 664 /* Set queue specific interrupt */ 665 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 666 } 667 /* Frame receive */ 668 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 669 /* Disable FIFO full warning */ 670 ravb_write(ndev, 0, RIC1); 671 /* Receive FIFO full error, descriptor empty */ 672 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 673 /* Frame transmitted, timestamp FIFO updated */ 674 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 675 676 return 0; 677 } 678 679 /* Device init function for Ethernet AVB */ 680 static int ravb_dmac_init(struct net_device *ndev) 681 { 682 struct ravb_private *priv = netdev_priv(ndev); 683 const struct ravb_hw_info *info = priv->info; 684 int error; 685 686 /* Set CONFIG mode */ 687 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 688 if (error) 689 return error; 690 691 error = info->dmac_init(ndev); 692 if (error) 693 return error; 694 695 /* Setting the control will start the AVB-DMAC process. */ 696 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 697 } 698 699 static void ravb_get_tx_tstamp(struct net_device *ndev) 700 { 701 struct ravb_private *priv = netdev_priv(ndev); 702 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 703 struct skb_shared_hwtstamps shhwtstamps; 704 struct sk_buff *skb; 705 struct timespec64 ts; 706 u16 tag, tfa_tag; 707 int count; 708 u32 tfa2; 709 710 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 711 while (count--) { 712 tfa2 = ravb_read(ndev, TFA2); 713 tfa_tag = (tfa2 & TFA2_TST) >> 16; 714 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 715 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 716 ravb_read(ndev, TFA1); 717 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 718 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 719 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 720 list) { 721 skb = ts_skb->skb; 722 tag = ts_skb->tag; 723 list_del(&ts_skb->list); 724 kfree(ts_skb); 725 if (tag == tfa_tag) { 726 skb_tstamp_tx(skb, &shhwtstamps); 727 dev_consume_skb_any(skb); 728 break; 729 } else { 730 dev_kfree_skb_any(skb); 731 } 732 } 733 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 734 } 735 } 736 737 static void ravb_rx_csum(struct sk_buff *skb) 738 { 739 u8 *hw_csum; 740 741 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 742 * appended to packet data 743 */ 744 if (unlikely(skb->len < sizeof(__sum16))) 745 return; 746 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 747 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 748 skb->ip_summed = CHECKSUM_COMPLETE; 749 skb_trim(skb, skb->len - sizeof(__sum16)); 750 } 751 752 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 753 struct ravb_rx_desc *desc) 754 { 755 struct ravb_private *priv = netdev_priv(ndev); 756 struct sk_buff *skb; 757 758 skb = priv->rx_skb[RAVB_BE][entry]; 759 priv->rx_skb[RAVB_BE][entry] = NULL; 760 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 761 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE); 762 763 return skb; 764 } 765 766 /* Packet receive function for Gigabit Ethernet */ 767 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 768 { 769 struct ravb_private *priv = netdev_priv(ndev); 770 const struct ravb_hw_info *info = priv->info; 771 struct net_device_stats *stats; 772 struct ravb_rx_desc *desc; 773 struct sk_buff *skb; 774 dma_addr_t dma_addr; 775 u8 desc_status; 776 int boguscnt; 777 u16 pkt_len; 778 u8 die_dt; 779 int entry; 780 int limit; 781 782 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 783 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 784 stats = &priv->stats[q]; 785 786 boguscnt = min(boguscnt, *quota); 787 limit = boguscnt; 788 desc = &priv->gbeth_rx_ring[entry]; 789 while (desc->die_dt != DT_FEMPTY) { 790 /* Descriptor type must be checked before all other reads */ 791 dma_rmb(); 792 desc_status = desc->msc; 793 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 794 795 if (--boguscnt < 0) 796 break; 797 798 /* We use 0-byte descriptors to mark the DMA mapping errors */ 799 if (!pkt_len) 800 continue; 801 802 if (desc_status & MSC_MC) 803 stats->multicast++; 804 805 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 806 stats->rx_errors++; 807 if (desc_status & MSC_CRC) 808 stats->rx_crc_errors++; 809 if (desc_status & MSC_RFE) 810 stats->rx_frame_errors++; 811 if (desc_status & (MSC_RTLF | MSC_RTSF)) 812 stats->rx_length_errors++; 813 if (desc_status & MSC_CEEF) 814 stats->rx_missed_errors++; 815 } else { 816 die_dt = desc->die_dt & 0xF0; 817 switch (die_dt) { 818 case DT_FSINGLE: 819 skb = ravb_get_skb_gbeth(ndev, entry, desc); 820 skb_put(skb, pkt_len); 821 skb->protocol = eth_type_trans(skb, ndev); 822 napi_gro_receive(&priv->napi[q], skb); 823 stats->rx_packets++; 824 stats->rx_bytes += pkt_len; 825 break; 826 case DT_FSTART: 827 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 828 skb_put(priv->rx_1st_skb, pkt_len); 829 break; 830 case DT_FMID: 831 skb = ravb_get_skb_gbeth(ndev, entry, desc); 832 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 833 priv->rx_1st_skb->len, 834 skb->data, 835 pkt_len); 836 skb_put(priv->rx_1st_skb, pkt_len); 837 dev_kfree_skb(skb); 838 break; 839 case DT_FEND: 840 skb = ravb_get_skb_gbeth(ndev, entry, desc); 841 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 842 priv->rx_1st_skb->len, 843 skb->data, 844 pkt_len); 845 skb_put(priv->rx_1st_skb, pkt_len); 846 dev_kfree_skb(skb); 847 priv->rx_1st_skb->protocol = 848 eth_type_trans(priv->rx_1st_skb, ndev); 849 napi_gro_receive(&priv->napi[q], 850 priv->rx_1st_skb); 851 stats->rx_packets++; 852 stats->rx_bytes += pkt_len; 853 break; 854 } 855 } 856 857 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 858 desc = &priv->gbeth_rx_ring[entry]; 859 } 860 861 /* Refill the RX ring buffers. */ 862 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 863 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 864 desc = &priv->gbeth_rx_ring[entry]; 865 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 866 867 if (!priv->rx_skb[q][entry]) { 868 skb = netdev_alloc_skb(ndev, info->max_rx_len); 869 if (!skb) 870 break; 871 ravb_set_buffer_align(skb); 872 dma_addr = dma_map_single(ndev->dev.parent, 873 skb->data, 874 GBETH_RX_BUFF_MAX, 875 DMA_FROM_DEVICE); 876 skb_checksum_none_assert(skb); 877 /* We just set the data size to 0 for a failed mapping 878 * which should prevent DMA from happening... 879 */ 880 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 881 desc->ds_cc = cpu_to_le16(0); 882 desc->dptr = cpu_to_le32(dma_addr); 883 priv->rx_skb[q][entry] = skb; 884 } 885 /* Descriptor type must be set after all the above writes */ 886 dma_wmb(); 887 desc->die_dt = DT_FEMPTY; 888 } 889 890 *quota -= limit - (++boguscnt); 891 892 return boguscnt <= 0; 893 } 894 895 /* Packet receive function for Ethernet AVB */ 896 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 897 { 898 struct ravb_private *priv = netdev_priv(ndev); 899 const struct ravb_hw_info *info = priv->info; 900 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 901 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 902 priv->cur_rx[q]; 903 struct net_device_stats *stats = &priv->stats[q]; 904 struct ravb_ex_rx_desc *desc; 905 struct sk_buff *skb; 906 dma_addr_t dma_addr; 907 struct timespec64 ts; 908 u8 desc_status; 909 u16 pkt_len; 910 int limit; 911 912 boguscnt = min(boguscnt, *quota); 913 limit = boguscnt; 914 desc = &priv->rx_ring[q][entry]; 915 while (desc->die_dt != DT_FEMPTY) { 916 /* Descriptor type must be checked before all other reads */ 917 dma_rmb(); 918 desc_status = desc->msc; 919 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 920 921 if (--boguscnt < 0) 922 break; 923 924 /* We use 0-byte descriptors to mark the DMA mapping errors */ 925 if (!pkt_len) 926 continue; 927 928 if (desc_status & MSC_MC) 929 stats->multicast++; 930 931 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 932 MSC_CEEF)) { 933 stats->rx_errors++; 934 if (desc_status & MSC_CRC) 935 stats->rx_crc_errors++; 936 if (desc_status & MSC_RFE) 937 stats->rx_frame_errors++; 938 if (desc_status & (MSC_RTLF | MSC_RTSF)) 939 stats->rx_length_errors++; 940 if (desc_status & MSC_CEEF) 941 stats->rx_missed_errors++; 942 } else { 943 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 944 945 skb = priv->rx_skb[q][entry]; 946 priv->rx_skb[q][entry] = NULL; 947 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 948 RX_BUF_SZ, 949 DMA_FROM_DEVICE); 950 get_ts &= (q == RAVB_NC) ? 951 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 952 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 953 if (get_ts) { 954 struct skb_shared_hwtstamps *shhwtstamps; 955 956 shhwtstamps = skb_hwtstamps(skb); 957 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 958 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 959 32) | le32_to_cpu(desc->ts_sl); 960 ts.tv_nsec = le32_to_cpu(desc->ts_n); 961 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 962 } 963 964 skb_put(skb, pkt_len); 965 skb->protocol = eth_type_trans(skb, ndev); 966 if (ndev->features & NETIF_F_RXCSUM) 967 ravb_rx_csum(skb); 968 napi_gro_receive(&priv->napi[q], skb); 969 stats->rx_packets++; 970 stats->rx_bytes += pkt_len; 971 } 972 973 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 974 desc = &priv->rx_ring[q][entry]; 975 } 976 977 /* Refill the RX ring buffers. */ 978 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 979 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 980 desc = &priv->rx_ring[q][entry]; 981 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 982 983 if (!priv->rx_skb[q][entry]) { 984 skb = netdev_alloc_skb(ndev, info->max_rx_len); 985 if (!skb) 986 break; /* Better luck next round. */ 987 ravb_set_buffer_align(skb); 988 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 989 le16_to_cpu(desc->ds_cc), 990 DMA_FROM_DEVICE); 991 skb_checksum_none_assert(skb); 992 /* We just set the data size to 0 for a failed mapping 993 * which should prevent DMA from happening... 994 */ 995 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 996 desc->ds_cc = cpu_to_le16(0); 997 desc->dptr = cpu_to_le32(dma_addr); 998 priv->rx_skb[q][entry] = skb; 999 } 1000 /* Descriptor type must be set after all the above writes */ 1001 dma_wmb(); 1002 desc->die_dt = DT_FEMPTY; 1003 } 1004 1005 *quota -= limit - (++boguscnt); 1006 1007 return boguscnt <= 0; 1008 } 1009 1010 /* Packet receive function for Ethernet AVB */ 1011 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 1012 { 1013 struct ravb_private *priv = netdev_priv(ndev); 1014 const struct ravb_hw_info *info = priv->info; 1015 1016 return info->receive(ndev, quota, q); 1017 } 1018 1019 static void ravb_rcv_snd_disable(struct net_device *ndev) 1020 { 1021 /* Disable TX and RX */ 1022 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1023 } 1024 1025 static void ravb_rcv_snd_enable(struct net_device *ndev) 1026 { 1027 /* Enable TX and RX */ 1028 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1029 } 1030 1031 /* function for waiting dma process finished */ 1032 static int ravb_stop_dma(struct net_device *ndev) 1033 { 1034 struct ravb_private *priv = netdev_priv(ndev); 1035 const struct ravb_hw_info *info = priv->info; 1036 int error; 1037 1038 /* Wait for stopping the hardware TX process */ 1039 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1040 1041 if (error) 1042 return error; 1043 1044 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1045 0); 1046 if (error) 1047 return error; 1048 1049 /* Stop the E-MAC's RX/TX processes. */ 1050 ravb_rcv_snd_disable(ndev); 1051 1052 /* Wait for stopping the RX DMA process */ 1053 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1054 if (error) 1055 return error; 1056 1057 /* Stop AVB-DMAC process */ 1058 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1059 } 1060 1061 /* E-MAC interrupt handler */ 1062 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1063 { 1064 struct ravb_private *priv = netdev_priv(ndev); 1065 u32 ecsr, psr; 1066 1067 ecsr = ravb_read(ndev, ECSR); 1068 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1069 1070 if (ecsr & ECSR_MPD) 1071 pm_wakeup_event(&priv->pdev->dev, 0); 1072 if (ecsr & ECSR_ICD) 1073 ndev->stats.tx_carrier_errors++; 1074 if (ecsr & ECSR_LCHNG) { 1075 /* Link changed */ 1076 if (priv->no_avb_link) 1077 return; 1078 psr = ravb_read(ndev, PSR); 1079 if (priv->avb_link_active_low) 1080 psr ^= PSR_LMON; 1081 if (!(psr & PSR_LMON)) { 1082 /* DIsable RX and TX */ 1083 ravb_rcv_snd_disable(ndev); 1084 } else { 1085 /* Enable RX and TX */ 1086 ravb_rcv_snd_enable(ndev); 1087 } 1088 } 1089 } 1090 1091 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1092 { 1093 struct net_device *ndev = dev_id; 1094 struct ravb_private *priv = netdev_priv(ndev); 1095 1096 spin_lock(&priv->lock); 1097 ravb_emac_interrupt_unlocked(ndev); 1098 spin_unlock(&priv->lock); 1099 return IRQ_HANDLED; 1100 } 1101 1102 /* Error interrupt handler */ 1103 static void ravb_error_interrupt(struct net_device *ndev) 1104 { 1105 struct ravb_private *priv = netdev_priv(ndev); 1106 u32 eis, ris2; 1107 1108 eis = ravb_read(ndev, EIS); 1109 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1110 if (eis & EIS_QFS) { 1111 ris2 = ravb_read(ndev, RIS2); 1112 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1113 RIS2); 1114 1115 /* Receive Descriptor Empty int */ 1116 if (ris2 & RIS2_QFF0) 1117 priv->stats[RAVB_BE].rx_over_errors++; 1118 1119 /* Receive Descriptor Empty int */ 1120 if (ris2 & RIS2_QFF1) 1121 priv->stats[RAVB_NC].rx_over_errors++; 1122 1123 /* Receive FIFO Overflow int */ 1124 if (ris2 & RIS2_RFFF) 1125 priv->rx_fifo_errors++; 1126 } 1127 } 1128 1129 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1130 { 1131 struct ravb_private *priv = netdev_priv(ndev); 1132 const struct ravb_hw_info *info = priv->info; 1133 u32 ris0 = ravb_read(ndev, RIS0); 1134 u32 ric0 = ravb_read(ndev, RIC0); 1135 u32 tis = ravb_read(ndev, TIS); 1136 u32 tic = ravb_read(ndev, TIC); 1137 1138 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1139 if (napi_schedule_prep(&priv->napi[q])) { 1140 /* Mask RX and TX interrupts */ 1141 if (!info->irq_en_dis) { 1142 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1143 ravb_write(ndev, tic & ~BIT(q), TIC); 1144 } else { 1145 ravb_write(ndev, BIT(q), RID0); 1146 ravb_write(ndev, BIT(q), TID); 1147 } 1148 __napi_schedule(&priv->napi[q]); 1149 } else { 1150 netdev_warn(ndev, 1151 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1152 ris0, ric0); 1153 netdev_warn(ndev, 1154 " tx status 0x%08x, tx mask 0x%08x.\n", 1155 tis, tic); 1156 } 1157 return true; 1158 } 1159 return false; 1160 } 1161 1162 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1163 { 1164 u32 tis = ravb_read(ndev, TIS); 1165 1166 if (tis & TIS_TFUF) { 1167 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1168 ravb_get_tx_tstamp(ndev); 1169 return true; 1170 } 1171 return false; 1172 } 1173 1174 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1175 { 1176 struct net_device *ndev = dev_id; 1177 struct ravb_private *priv = netdev_priv(ndev); 1178 const struct ravb_hw_info *info = priv->info; 1179 irqreturn_t result = IRQ_NONE; 1180 u32 iss; 1181 1182 spin_lock(&priv->lock); 1183 /* Get interrupt status */ 1184 iss = ravb_read(ndev, ISS); 1185 1186 /* Received and transmitted interrupts */ 1187 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1188 int q; 1189 1190 /* Timestamp updated */ 1191 if (ravb_timestamp_interrupt(ndev)) 1192 result = IRQ_HANDLED; 1193 1194 /* Network control and best effort queue RX/TX */ 1195 if (info->nc_queues) { 1196 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1197 if (ravb_queue_interrupt(ndev, q)) 1198 result = IRQ_HANDLED; 1199 } 1200 } else { 1201 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1202 result = IRQ_HANDLED; 1203 } 1204 } 1205 1206 /* E-MAC status summary */ 1207 if (iss & ISS_MS) { 1208 ravb_emac_interrupt_unlocked(ndev); 1209 result = IRQ_HANDLED; 1210 } 1211 1212 /* Error status summary */ 1213 if (iss & ISS_ES) { 1214 ravb_error_interrupt(ndev); 1215 result = IRQ_HANDLED; 1216 } 1217 1218 /* gPTP interrupt status summary */ 1219 if (iss & ISS_CGIS) { 1220 ravb_ptp_interrupt(ndev); 1221 result = IRQ_HANDLED; 1222 } 1223 1224 spin_unlock(&priv->lock); 1225 return result; 1226 } 1227 1228 /* Timestamp/Error/gPTP interrupt handler */ 1229 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1230 { 1231 struct net_device *ndev = dev_id; 1232 struct ravb_private *priv = netdev_priv(ndev); 1233 irqreturn_t result = IRQ_NONE; 1234 u32 iss; 1235 1236 spin_lock(&priv->lock); 1237 /* Get interrupt status */ 1238 iss = ravb_read(ndev, ISS); 1239 1240 /* Timestamp updated */ 1241 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1242 result = IRQ_HANDLED; 1243 1244 /* Error status summary */ 1245 if (iss & ISS_ES) { 1246 ravb_error_interrupt(ndev); 1247 result = IRQ_HANDLED; 1248 } 1249 1250 /* gPTP interrupt status summary */ 1251 if (iss & ISS_CGIS) { 1252 ravb_ptp_interrupt(ndev); 1253 result = IRQ_HANDLED; 1254 } 1255 1256 spin_unlock(&priv->lock); 1257 return result; 1258 } 1259 1260 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1261 { 1262 struct net_device *ndev = dev_id; 1263 struct ravb_private *priv = netdev_priv(ndev); 1264 irqreturn_t result = IRQ_NONE; 1265 1266 spin_lock(&priv->lock); 1267 1268 /* Network control/Best effort queue RX/TX */ 1269 if (ravb_queue_interrupt(ndev, q)) 1270 result = IRQ_HANDLED; 1271 1272 spin_unlock(&priv->lock); 1273 return result; 1274 } 1275 1276 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1277 { 1278 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1279 } 1280 1281 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1282 { 1283 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1284 } 1285 1286 static int ravb_poll(struct napi_struct *napi, int budget) 1287 { 1288 struct net_device *ndev = napi->dev; 1289 struct ravb_private *priv = netdev_priv(ndev); 1290 const struct ravb_hw_info *info = priv->info; 1291 unsigned long flags; 1292 int q = napi - priv->napi; 1293 int mask = BIT(q); 1294 int quota = budget; 1295 bool unmask; 1296 1297 /* Processing RX Descriptor Ring */ 1298 /* Clear RX interrupt */ 1299 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1300 unmask = !ravb_rx(ndev, "a, q); 1301 1302 /* Processing TX Descriptor Ring */ 1303 spin_lock_irqsave(&priv->lock, flags); 1304 /* Clear TX interrupt */ 1305 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1306 ravb_tx_free(ndev, q, true); 1307 netif_wake_subqueue(ndev, q); 1308 spin_unlock_irqrestore(&priv->lock, flags); 1309 1310 if (!unmask) 1311 goto out; 1312 1313 napi_complete(napi); 1314 1315 /* Re-enable RX/TX interrupts */ 1316 spin_lock_irqsave(&priv->lock, flags); 1317 if (!info->irq_en_dis) { 1318 ravb_modify(ndev, RIC0, mask, mask); 1319 ravb_modify(ndev, TIC, mask, mask); 1320 } else { 1321 ravb_write(ndev, mask, RIE0); 1322 ravb_write(ndev, mask, TIE); 1323 } 1324 spin_unlock_irqrestore(&priv->lock, flags); 1325 1326 /* Receive error message handling */ 1327 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1328 if (info->nc_queues) 1329 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1330 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1331 ndev->stats.rx_over_errors = priv->rx_over_errors; 1332 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1333 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1334 out: 1335 return budget - quota; 1336 } 1337 1338 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1339 { 1340 struct ravb_private *priv = netdev_priv(ndev); 1341 1342 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1343 } 1344 1345 /* PHY state control function */ 1346 static void ravb_adjust_link(struct net_device *ndev) 1347 { 1348 struct ravb_private *priv = netdev_priv(ndev); 1349 const struct ravb_hw_info *info = priv->info; 1350 struct phy_device *phydev = ndev->phydev; 1351 bool new_state = false; 1352 unsigned long flags; 1353 1354 spin_lock_irqsave(&priv->lock, flags); 1355 1356 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1357 if (priv->no_avb_link) 1358 ravb_rcv_snd_disable(ndev); 1359 1360 if (phydev->link) { 1361 if (info->half_duplex && phydev->duplex != priv->duplex) { 1362 new_state = true; 1363 priv->duplex = phydev->duplex; 1364 ravb_set_duplex_gbeth(ndev); 1365 } 1366 1367 if (phydev->speed != priv->speed) { 1368 new_state = true; 1369 priv->speed = phydev->speed; 1370 info->set_rate(ndev); 1371 } 1372 if (!priv->link) { 1373 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1374 new_state = true; 1375 priv->link = phydev->link; 1376 } 1377 } else if (priv->link) { 1378 new_state = true; 1379 priv->link = 0; 1380 priv->speed = 0; 1381 if (info->half_duplex) 1382 priv->duplex = -1; 1383 } 1384 1385 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1386 if (priv->no_avb_link && phydev->link) 1387 ravb_rcv_snd_enable(ndev); 1388 1389 spin_unlock_irqrestore(&priv->lock, flags); 1390 1391 if (new_state && netif_msg_link(priv)) 1392 phy_print_status(phydev); 1393 } 1394 1395 /* PHY init function */ 1396 static int ravb_phy_init(struct net_device *ndev) 1397 { 1398 struct device_node *np = ndev->dev.parent->of_node; 1399 struct ravb_private *priv = netdev_priv(ndev); 1400 const struct ravb_hw_info *info = priv->info; 1401 struct phy_device *phydev; 1402 struct device_node *pn; 1403 phy_interface_t iface; 1404 int err; 1405 1406 priv->link = 0; 1407 priv->speed = 0; 1408 priv->duplex = -1; 1409 1410 /* Try connecting to PHY */ 1411 pn = of_parse_phandle(np, "phy-handle", 0); 1412 if (!pn) { 1413 /* In the case of a fixed PHY, the DT node associated 1414 * to the PHY is the Ethernet MAC DT node. 1415 */ 1416 if (of_phy_is_fixed_link(np)) { 1417 err = of_phy_register_fixed_link(np); 1418 if (err) 1419 return err; 1420 } 1421 pn = of_node_get(np); 1422 } 1423 1424 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1425 : priv->phy_interface; 1426 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1427 of_node_put(pn); 1428 if (!phydev) { 1429 netdev_err(ndev, "failed to connect PHY\n"); 1430 err = -ENOENT; 1431 goto err_deregister_fixed_link; 1432 } 1433 1434 if (!info->half_duplex) { 1435 /* 10BASE, Pause and Asym Pause is not supported */ 1436 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1437 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1438 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1439 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1440 1441 /* Half Duplex is not supported */ 1442 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1443 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1444 } 1445 1446 phy_attached_info(phydev); 1447 1448 return 0; 1449 1450 err_deregister_fixed_link: 1451 if (of_phy_is_fixed_link(np)) 1452 of_phy_deregister_fixed_link(np); 1453 1454 return err; 1455 } 1456 1457 /* PHY control start function */ 1458 static int ravb_phy_start(struct net_device *ndev) 1459 { 1460 int error; 1461 1462 error = ravb_phy_init(ndev); 1463 if (error) 1464 return error; 1465 1466 phy_start(ndev->phydev); 1467 1468 return 0; 1469 } 1470 1471 static u32 ravb_get_msglevel(struct net_device *ndev) 1472 { 1473 struct ravb_private *priv = netdev_priv(ndev); 1474 1475 return priv->msg_enable; 1476 } 1477 1478 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1479 { 1480 struct ravb_private *priv = netdev_priv(ndev); 1481 1482 priv->msg_enable = value; 1483 } 1484 1485 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1486 "rx_queue_0_current", 1487 "tx_queue_0_current", 1488 "rx_queue_0_dirty", 1489 "tx_queue_0_dirty", 1490 "rx_queue_0_packets", 1491 "tx_queue_0_packets", 1492 "rx_queue_0_bytes", 1493 "tx_queue_0_bytes", 1494 "rx_queue_0_mcast_packets", 1495 "rx_queue_0_errors", 1496 "rx_queue_0_crc_errors", 1497 "rx_queue_0_frame_errors", 1498 "rx_queue_0_length_errors", 1499 "rx_queue_0_csum_offload_errors", 1500 "rx_queue_0_over_errors", 1501 }; 1502 1503 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1504 "rx_queue_0_current", 1505 "tx_queue_0_current", 1506 "rx_queue_0_dirty", 1507 "tx_queue_0_dirty", 1508 "rx_queue_0_packets", 1509 "tx_queue_0_packets", 1510 "rx_queue_0_bytes", 1511 "tx_queue_0_bytes", 1512 "rx_queue_0_mcast_packets", 1513 "rx_queue_0_errors", 1514 "rx_queue_0_crc_errors", 1515 "rx_queue_0_frame_errors", 1516 "rx_queue_0_length_errors", 1517 "rx_queue_0_missed_errors", 1518 "rx_queue_0_over_errors", 1519 1520 "rx_queue_1_current", 1521 "tx_queue_1_current", 1522 "rx_queue_1_dirty", 1523 "tx_queue_1_dirty", 1524 "rx_queue_1_packets", 1525 "tx_queue_1_packets", 1526 "rx_queue_1_bytes", 1527 "tx_queue_1_bytes", 1528 "rx_queue_1_mcast_packets", 1529 "rx_queue_1_errors", 1530 "rx_queue_1_crc_errors", 1531 "rx_queue_1_frame_errors", 1532 "rx_queue_1_length_errors", 1533 "rx_queue_1_missed_errors", 1534 "rx_queue_1_over_errors", 1535 }; 1536 1537 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1538 { 1539 struct ravb_private *priv = netdev_priv(netdev); 1540 const struct ravb_hw_info *info = priv->info; 1541 1542 switch (sset) { 1543 case ETH_SS_STATS: 1544 return info->stats_len; 1545 default: 1546 return -EOPNOTSUPP; 1547 } 1548 } 1549 1550 static void ravb_get_ethtool_stats(struct net_device *ndev, 1551 struct ethtool_stats *estats, u64 *data) 1552 { 1553 struct ravb_private *priv = netdev_priv(ndev); 1554 const struct ravb_hw_info *info = priv->info; 1555 int num_rx_q; 1556 int i = 0; 1557 int q; 1558 1559 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1560 /* Device-specific stats */ 1561 for (q = RAVB_BE; q < num_rx_q; q++) { 1562 struct net_device_stats *stats = &priv->stats[q]; 1563 1564 data[i++] = priv->cur_rx[q]; 1565 data[i++] = priv->cur_tx[q]; 1566 data[i++] = priv->dirty_rx[q]; 1567 data[i++] = priv->dirty_tx[q]; 1568 data[i++] = stats->rx_packets; 1569 data[i++] = stats->tx_packets; 1570 data[i++] = stats->rx_bytes; 1571 data[i++] = stats->tx_bytes; 1572 data[i++] = stats->multicast; 1573 data[i++] = stats->rx_errors; 1574 data[i++] = stats->rx_crc_errors; 1575 data[i++] = stats->rx_frame_errors; 1576 data[i++] = stats->rx_length_errors; 1577 data[i++] = stats->rx_missed_errors; 1578 data[i++] = stats->rx_over_errors; 1579 } 1580 } 1581 1582 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1583 { 1584 struct ravb_private *priv = netdev_priv(ndev); 1585 const struct ravb_hw_info *info = priv->info; 1586 1587 switch (stringset) { 1588 case ETH_SS_STATS: 1589 memcpy(data, info->gstrings_stats, info->gstrings_size); 1590 break; 1591 } 1592 } 1593 1594 static void ravb_get_ringparam(struct net_device *ndev, 1595 struct ethtool_ringparam *ring, 1596 struct kernel_ethtool_ringparam *kernel_ring, 1597 struct netlink_ext_ack *extack) 1598 { 1599 struct ravb_private *priv = netdev_priv(ndev); 1600 1601 ring->rx_max_pending = BE_RX_RING_MAX; 1602 ring->tx_max_pending = BE_TX_RING_MAX; 1603 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1604 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1605 } 1606 1607 static int ravb_set_ringparam(struct net_device *ndev, 1608 struct ethtool_ringparam *ring, 1609 struct kernel_ethtool_ringparam *kernel_ring, 1610 struct netlink_ext_ack *extack) 1611 { 1612 struct ravb_private *priv = netdev_priv(ndev); 1613 const struct ravb_hw_info *info = priv->info; 1614 int error; 1615 1616 if (ring->tx_pending > BE_TX_RING_MAX || 1617 ring->rx_pending > BE_RX_RING_MAX || 1618 ring->tx_pending < BE_TX_RING_MIN || 1619 ring->rx_pending < BE_RX_RING_MIN) 1620 return -EINVAL; 1621 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1622 return -EINVAL; 1623 1624 if (netif_running(ndev)) { 1625 netif_device_detach(ndev); 1626 /* Stop PTP Clock driver */ 1627 if (info->gptp) 1628 ravb_ptp_stop(ndev); 1629 /* Wait for DMA stopping */ 1630 error = ravb_stop_dma(ndev); 1631 if (error) { 1632 netdev_err(ndev, 1633 "cannot set ringparam! Any AVB processes are still running?\n"); 1634 return error; 1635 } 1636 synchronize_irq(ndev->irq); 1637 1638 /* Free all the skb's in the RX queue and the DMA buffers. */ 1639 ravb_ring_free(ndev, RAVB_BE); 1640 if (info->nc_queues) 1641 ravb_ring_free(ndev, RAVB_NC); 1642 } 1643 1644 /* Set new parameters */ 1645 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1646 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1647 1648 if (netif_running(ndev)) { 1649 error = ravb_dmac_init(ndev); 1650 if (error) { 1651 netdev_err(ndev, 1652 "%s: ravb_dmac_init() failed, error %d\n", 1653 __func__, error); 1654 return error; 1655 } 1656 1657 ravb_emac_init(ndev); 1658 1659 /* Initialise PTP Clock driver */ 1660 if (info->gptp) 1661 ravb_ptp_init(ndev, priv->pdev); 1662 1663 netif_device_attach(ndev); 1664 } 1665 1666 return 0; 1667 } 1668 1669 static int ravb_get_ts_info(struct net_device *ndev, 1670 struct ethtool_ts_info *info) 1671 { 1672 struct ravb_private *priv = netdev_priv(ndev); 1673 const struct ravb_hw_info *hw_info = priv->info; 1674 1675 info->so_timestamping = 1676 SOF_TIMESTAMPING_TX_SOFTWARE | 1677 SOF_TIMESTAMPING_RX_SOFTWARE | 1678 SOF_TIMESTAMPING_SOFTWARE | 1679 SOF_TIMESTAMPING_TX_HARDWARE | 1680 SOF_TIMESTAMPING_RX_HARDWARE | 1681 SOF_TIMESTAMPING_RAW_HARDWARE; 1682 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1683 info->rx_filters = 1684 (1 << HWTSTAMP_FILTER_NONE) | 1685 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1686 (1 << HWTSTAMP_FILTER_ALL); 1687 if (hw_info->gptp || hw_info->ccc_gac) 1688 info->phc_index = ptp_clock_index(priv->ptp.clock); 1689 1690 return 0; 1691 } 1692 1693 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1694 { 1695 struct ravb_private *priv = netdev_priv(ndev); 1696 1697 wol->supported = WAKE_MAGIC; 1698 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1699 } 1700 1701 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1702 { 1703 struct ravb_private *priv = netdev_priv(ndev); 1704 const struct ravb_hw_info *info = priv->info; 1705 1706 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1707 return -EOPNOTSUPP; 1708 1709 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1710 1711 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1712 1713 return 0; 1714 } 1715 1716 static const struct ethtool_ops ravb_ethtool_ops = { 1717 .nway_reset = phy_ethtool_nway_reset, 1718 .get_msglevel = ravb_get_msglevel, 1719 .set_msglevel = ravb_set_msglevel, 1720 .get_link = ethtool_op_get_link, 1721 .get_strings = ravb_get_strings, 1722 .get_ethtool_stats = ravb_get_ethtool_stats, 1723 .get_sset_count = ravb_get_sset_count, 1724 .get_ringparam = ravb_get_ringparam, 1725 .set_ringparam = ravb_set_ringparam, 1726 .get_ts_info = ravb_get_ts_info, 1727 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1728 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1729 .get_wol = ravb_get_wol, 1730 .set_wol = ravb_set_wol, 1731 }; 1732 1733 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1734 struct net_device *ndev, struct device *dev, 1735 const char *ch) 1736 { 1737 char *name; 1738 int error; 1739 1740 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1741 if (!name) 1742 return -ENOMEM; 1743 error = request_irq(irq, handler, 0, name, ndev); 1744 if (error) 1745 netdev_err(ndev, "cannot request IRQ %s\n", name); 1746 1747 return error; 1748 } 1749 1750 /* Network device open function for Ethernet AVB */ 1751 static int ravb_open(struct net_device *ndev) 1752 { 1753 struct ravb_private *priv = netdev_priv(ndev); 1754 const struct ravb_hw_info *info = priv->info; 1755 struct platform_device *pdev = priv->pdev; 1756 struct device *dev = &pdev->dev; 1757 int error; 1758 1759 napi_enable(&priv->napi[RAVB_BE]); 1760 if (info->nc_queues) 1761 napi_enable(&priv->napi[RAVB_NC]); 1762 1763 if (!info->multi_irqs) { 1764 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1765 ndev->name, ndev); 1766 if (error) { 1767 netdev_err(ndev, "cannot request IRQ\n"); 1768 goto out_napi_off; 1769 } 1770 } else { 1771 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1772 dev, "ch22:multi"); 1773 if (error) 1774 goto out_napi_off; 1775 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1776 dev, "ch24:emac"); 1777 if (error) 1778 goto out_free_irq; 1779 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1780 ndev, dev, "ch0:rx_be"); 1781 if (error) 1782 goto out_free_irq_emac; 1783 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1784 ndev, dev, "ch18:tx_be"); 1785 if (error) 1786 goto out_free_irq_be_rx; 1787 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1788 ndev, dev, "ch1:rx_nc"); 1789 if (error) 1790 goto out_free_irq_be_tx; 1791 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1792 ndev, dev, "ch19:tx_nc"); 1793 if (error) 1794 goto out_free_irq_nc_rx; 1795 1796 if (info->err_mgmt_irqs) { 1797 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt, 1798 ndev, dev, "err_a"); 1799 if (error) 1800 goto out_free_irq_nc_tx; 1801 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt, 1802 ndev, dev, "mgmt_a"); 1803 if (error) 1804 goto out_free_irq_erra; 1805 } 1806 } 1807 1808 /* Device init */ 1809 error = ravb_dmac_init(ndev); 1810 if (error) 1811 goto out_free_irq_mgmta; 1812 ravb_emac_init(ndev); 1813 1814 /* Initialise PTP Clock driver */ 1815 if (info->gptp) 1816 ravb_ptp_init(ndev, priv->pdev); 1817 1818 /* PHY control start */ 1819 error = ravb_phy_start(ndev); 1820 if (error) 1821 goto out_ptp_stop; 1822 1823 netif_tx_start_all_queues(ndev); 1824 1825 return 0; 1826 1827 out_ptp_stop: 1828 /* Stop PTP Clock driver */ 1829 if (info->gptp) 1830 ravb_ptp_stop(ndev); 1831 ravb_stop_dma(ndev); 1832 out_free_irq_mgmta: 1833 if (!info->multi_irqs) 1834 goto out_free_irq; 1835 if (info->err_mgmt_irqs) 1836 free_irq(priv->mgmta_irq, ndev); 1837 out_free_irq_erra: 1838 if (info->err_mgmt_irqs) 1839 free_irq(priv->erra_irq, ndev); 1840 out_free_irq_nc_tx: 1841 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1842 out_free_irq_nc_rx: 1843 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1844 out_free_irq_be_tx: 1845 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1846 out_free_irq_be_rx: 1847 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1848 out_free_irq_emac: 1849 free_irq(priv->emac_irq, ndev); 1850 out_free_irq: 1851 free_irq(ndev->irq, ndev); 1852 out_napi_off: 1853 if (info->nc_queues) 1854 napi_disable(&priv->napi[RAVB_NC]); 1855 napi_disable(&priv->napi[RAVB_BE]); 1856 return error; 1857 } 1858 1859 /* Timeout function for Ethernet AVB */ 1860 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1861 { 1862 struct ravb_private *priv = netdev_priv(ndev); 1863 1864 netif_err(priv, tx_err, ndev, 1865 "transmit timed out, status %08x, resetting...\n", 1866 ravb_read(ndev, ISS)); 1867 1868 /* tx_errors count up */ 1869 ndev->stats.tx_errors++; 1870 1871 schedule_work(&priv->work); 1872 } 1873 1874 static void ravb_tx_timeout_work(struct work_struct *work) 1875 { 1876 struct ravb_private *priv = container_of(work, struct ravb_private, 1877 work); 1878 const struct ravb_hw_info *info = priv->info; 1879 struct net_device *ndev = priv->ndev; 1880 int error; 1881 1882 if (!rtnl_trylock()) { 1883 usleep_range(1000, 2000); 1884 schedule_work(&priv->work); 1885 return; 1886 } 1887 1888 netif_tx_stop_all_queues(ndev); 1889 1890 /* Stop PTP Clock driver */ 1891 if (info->gptp) 1892 ravb_ptp_stop(ndev); 1893 1894 /* Wait for DMA stopping */ 1895 if (ravb_stop_dma(ndev)) { 1896 /* If ravb_stop_dma() fails, the hardware is still operating 1897 * for TX and/or RX. So, this should not call the following 1898 * functions because ravb_dmac_init() is possible to fail too. 1899 * Also, this should not retry ravb_stop_dma() again and again 1900 * here because it's possible to wait forever. So, this just 1901 * re-enables the TX and RX and skip the following 1902 * re-initialization procedure. 1903 */ 1904 ravb_rcv_snd_enable(ndev); 1905 goto out; 1906 } 1907 1908 ravb_ring_free(ndev, RAVB_BE); 1909 if (info->nc_queues) 1910 ravb_ring_free(ndev, RAVB_NC); 1911 1912 /* Device init */ 1913 error = ravb_dmac_init(ndev); 1914 if (error) { 1915 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1916 * should return here to avoid re-enabling the TX and RX in 1917 * ravb_emac_init(). 1918 */ 1919 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1920 __func__, error); 1921 goto out_unlock; 1922 } 1923 ravb_emac_init(ndev); 1924 1925 out: 1926 /* Initialise PTP Clock driver */ 1927 if (info->gptp) 1928 ravb_ptp_init(ndev, priv->pdev); 1929 1930 netif_tx_start_all_queues(ndev); 1931 1932 out_unlock: 1933 rtnl_unlock(); 1934 } 1935 1936 /* Packet transmit function for Ethernet AVB */ 1937 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1938 { 1939 struct ravb_private *priv = netdev_priv(ndev); 1940 const struct ravb_hw_info *info = priv->info; 1941 unsigned int num_tx_desc = priv->num_tx_desc; 1942 u16 q = skb_get_queue_mapping(skb); 1943 struct ravb_tstamp_skb *ts_skb; 1944 struct ravb_tx_desc *desc; 1945 unsigned long flags; 1946 dma_addr_t dma_addr; 1947 void *buffer; 1948 u32 entry; 1949 u32 len; 1950 1951 spin_lock_irqsave(&priv->lock, flags); 1952 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1953 num_tx_desc) { 1954 netif_err(priv, tx_queued, ndev, 1955 "still transmitting with the full ring!\n"); 1956 netif_stop_subqueue(ndev, q); 1957 spin_unlock_irqrestore(&priv->lock, flags); 1958 return NETDEV_TX_BUSY; 1959 } 1960 1961 if (skb_put_padto(skb, ETH_ZLEN)) 1962 goto exit; 1963 1964 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1965 priv->tx_skb[q][entry / num_tx_desc] = skb; 1966 1967 if (num_tx_desc > 1) { 1968 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1969 entry / num_tx_desc * DPTR_ALIGN; 1970 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1971 1972 /* Zero length DMA descriptors are problematic as they seem 1973 * to terminate DMA transfers. Avoid them by simply using a 1974 * length of DPTR_ALIGN (4) when skb data is aligned to 1975 * DPTR_ALIGN. 1976 * 1977 * As skb is guaranteed to have at least ETH_ZLEN (60) 1978 * bytes of data by the call to skb_put_padto() above this 1979 * is safe with respect to both the length of the first DMA 1980 * descriptor (len) overflowing the available data and the 1981 * length of the second DMA descriptor (skb->len - len) 1982 * being negative. 1983 */ 1984 if (len == 0) 1985 len = DPTR_ALIGN; 1986 1987 memcpy(buffer, skb->data, len); 1988 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1989 DMA_TO_DEVICE); 1990 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1991 goto drop; 1992 1993 desc = &priv->tx_ring[q][entry]; 1994 desc->ds_tagl = cpu_to_le16(len); 1995 desc->dptr = cpu_to_le32(dma_addr); 1996 1997 buffer = skb->data + len; 1998 len = skb->len - len; 1999 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2000 DMA_TO_DEVICE); 2001 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2002 goto unmap; 2003 2004 desc++; 2005 } else { 2006 desc = &priv->tx_ring[q][entry]; 2007 len = skb->len; 2008 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2009 DMA_TO_DEVICE); 2010 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2011 goto drop; 2012 } 2013 desc->ds_tagl = cpu_to_le16(len); 2014 desc->dptr = cpu_to_le32(dma_addr); 2015 2016 /* TX timestamp required */ 2017 if (info->gptp || info->ccc_gac) { 2018 if (q == RAVB_NC) { 2019 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2020 if (!ts_skb) { 2021 if (num_tx_desc > 1) { 2022 desc--; 2023 dma_unmap_single(ndev->dev.parent, dma_addr, 2024 len, DMA_TO_DEVICE); 2025 } 2026 goto unmap; 2027 } 2028 ts_skb->skb = skb_get(skb); 2029 ts_skb->tag = priv->ts_skb_tag++; 2030 priv->ts_skb_tag &= 0x3ff; 2031 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2032 2033 /* TAG and timestamp required flag */ 2034 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2035 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2036 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2037 } 2038 2039 skb_tx_timestamp(skb); 2040 } 2041 /* Descriptor type must be set after all the above writes */ 2042 dma_wmb(); 2043 if (num_tx_desc > 1) { 2044 desc->die_dt = DT_FEND; 2045 desc--; 2046 desc->die_dt = DT_FSTART; 2047 } else { 2048 desc->die_dt = DT_FSINGLE; 2049 } 2050 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2051 2052 priv->cur_tx[q] += num_tx_desc; 2053 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2054 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2055 !ravb_tx_free(ndev, q, true)) 2056 netif_stop_subqueue(ndev, q); 2057 2058 exit: 2059 spin_unlock_irqrestore(&priv->lock, flags); 2060 return NETDEV_TX_OK; 2061 2062 unmap: 2063 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2064 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2065 drop: 2066 dev_kfree_skb_any(skb); 2067 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2068 goto exit; 2069 } 2070 2071 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2072 struct net_device *sb_dev) 2073 { 2074 /* If skb needs TX timestamp, it is handled in network control queue */ 2075 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2076 RAVB_BE; 2077 2078 } 2079 2080 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2081 { 2082 struct ravb_private *priv = netdev_priv(ndev); 2083 const struct ravb_hw_info *info = priv->info; 2084 struct net_device_stats *nstats, *stats0, *stats1; 2085 2086 nstats = &ndev->stats; 2087 stats0 = &priv->stats[RAVB_BE]; 2088 2089 if (info->tx_counters) { 2090 nstats->tx_dropped += ravb_read(ndev, TROCR); 2091 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2092 } 2093 2094 if (info->carrier_counters) { 2095 nstats->collisions += ravb_read(ndev, CXR41); 2096 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2097 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2098 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2099 } 2100 2101 nstats->rx_packets = stats0->rx_packets; 2102 nstats->tx_packets = stats0->tx_packets; 2103 nstats->rx_bytes = stats0->rx_bytes; 2104 nstats->tx_bytes = stats0->tx_bytes; 2105 nstats->multicast = stats0->multicast; 2106 nstats->rx_errors = stats0->rx_errors; 2107 nstats->rx_crc_errors = stats0->rx_crc_errors; 2108 nstats->rx_frame_errors = stats0->rx_frame_errors; 2109 nstats->rx_length_errors = stats0->rx_length_errors; 2110 nstats->rx_missed_errors = stats0->rx_missed_errors; 2111 nstats->rx_over_errors = stats0->rx_over_errors; 2112 if (info->nc_queues) { 2113 stats1 = &priv->stats[RAVB_NC]; 2114 2115 nstats->rx_packets += stats1->rx_packets; 2116 nstats->tx_packets += stats1->tx_packets; 2117 nstats->rx_bytes += stats1->rx_bytes; 2118 nstats->tx_bytes += stats1->tx_bytes; 2119 nstats->multicast += stats1->multicast; 2120 nstats->rx_errors += stats1->rx_errors; 2121 nstats->rx_crc_errors += stats1->rx_crc_errors; 2122 nstats->rx_frame_errors += stats1->rx_frame_errors; 2123 nstats->rx_length_errors += stats1->rx_length_errors; 2124 nstats->rx_missed_errors += stats1->rx_missed_errors; 2125 nstats->rx_over_errors += stats1->rx_over_errors; 2126 } 2127 2128 return nstats; 2129 } 2130 2131 /* Update promiscuous bit */ 2132 static void ravb_set_rx_mode(struct net_device *ndev) 2133 { 2134 struct ravb_private *priv = netdev_priv(ndev); 2135 unsigned long flags; 2136 2137 spin_lock_irqsave(&priv->lock, flags); 2138 ravb_modify(ndev, ECMR, ECMR_PRM, 2139 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2140 spin_unlock_irqrestore(&priv->lock, flags); 2141 } 2142 2143 /* Device close function for Ethernet AVB */ 2144 static int ravb_close(struct net_device *ndev) 2145 { 2146 struct device_node *np = ndev->dev.parent->of_node; 2147 struct ravb_private *priv = netdev_priv(ndev); 2148 const struct ravb_hw_info *info = priv->info; 2149 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2150 2151 netif_tx_stop_all_queues(ndev); 2152 2153 /* Disable interrupts by clearing the interrupt masks. */ 2154 ravb_write(ndev, 0, RIC0); 2155 ravb_write(ndev, 0, RIC2); 2156 ravb_write(ndev, 0, TIC); 2157 2158 /* Stop PTP Clock driver */ 2159 if (info->gptp) 2160 ravb_ptp_stop(ndev); 2161 2162 /* Set the config mode to stop the AVB-DMAC's processes */ 2163 if (ravb_stop_dma(ndev) < 0) 2164 netdev_err(ndev, 2165 "device will be stopped after h/w processes are done.\n"); 2166 2167 /* Clear the timestamp list */ 2168 if (info->gptp || info->ccc_gac) { 2169 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2170 list_del(&ts_skb->list); 2171 kfree_skb(ts_skb->skb); 2172 kfree(ts_skb); 2173 } 2174 } 2175 2176 /* PHY disconnect */ 2177 if (ndev->phydev) { 2178 phy_stop(ndev->phydev); 2179 phy_disconnect(ndev->phydev); 2180 if (of_phy_is_fixed_link(np)) 2181 of_phy_deregister_fixed_link(np); 2182 } 2183 2184 cancel_work_sync(&priv->work); 2185 2186 if (info->multi_irqs) { 2187 free_irq(priv->tx_irqs[RAVB_NC], ndev); 2188 free_irq(priv->rx_irqs[RAVB_NC], ndev); 2189 free_irq(priv->tx_irqs[RAVB_BE], ndev); 2190 free_irq(priv->rx_irqs[RAVB_BE], ndev); 2191 free_irq(priv->emac_irq, ndev); 2192 if (info->err_mgmt_irqs) { 2193 free_irq(priv->erra_irq, ndev); 2194 free_irq(priv->mgmta_irq, ndev); 2195 } 2196 } 2197 free_irq(ndev->irq, ndev); 2198 2199 if (info->nc_queues) 2200 napi_disable(&priv->napi[RAVB_NC]); 2201 napi_disable(&priv->napi[RAVB_BE]); 2202 2203 /* Free all the skb's in the RX queue and the DMA buffers. */ 2204 ravb_ring_free(ndev, RAVB_BE); 2205 if (info->nc_queues) 2206 ravb_ring_free(ndev, RAVB_NC); 2207 2208 return 0; 2209 } 2210 2211 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2212 { 2213 struct ravb_private *priv = netdev_priv(ndev); 2214 struct hwtstamp_config config; 2215 2216 config.flags = 0; 2217 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2218 HWTSTAMP_TX_OFF; 2219 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2220 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2221 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2222 break; 2223 case RAVB_RXTSTAMP_TYPE_ALL: 2224 config.rx_filter = HWTSTAMP_FILTER_ALL; 2225 break; 2226 default: 2227 config.rx_filter = HWTSTAMP_FILTER_NONE; 2228 } 2229 2230 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2231 -EFAULT : 0; 2232 } 2233 2234 /* Control hardware time stamping */ 2235 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2236 { 2237 struct ravb_private *priv = netdev_priv(ndev); 2238 struct hwtstamp_config config; 2239 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2240 u32 tstamp_tx_ctrl; 2241 2242 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2243 return -EFAULT; 2244 2245 switch (config.tx_type) { 2246 case HWTSTAMP_TX_OFF: 2247 tstamp_tx_ctrl = 0; 2248 break; 2249 case HWTSTAMP_TX_ON: 2250 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2251 break; 2252 default: 2253 return -ERANGE; 2254 } 2255 2256 switch (config.rx_filter) { 2257 case HWTSTAMP_FILTER_NONE: 2258 tstamp_rx_ctrl = 0; 2259 break; 2260 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2261 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2262 break; 2263 default: 2264 config.rx_filter = HWTSTAMP_FILTER_ALL; 2265 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2266 } 2267 2268 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2269 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2270 2271 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2272 -EFAULT : 0; 2273 } 2274 2275 /* ioctl to device function */ 2276 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2277 { 2278 struct phy_device *phydev = ndev->phydev; 2279 2280 if (!netif_running(ndev)) 2281 return -EINVAL; 2282 2283 if (!phydev) 2284 return -ENODEV; 2285 2286 switch (cmd) { 2287 case SIOCGHWTSTAMP: 2288 return ravb_hwtstamp_get(ndev, req); 2289 case SIOCSHWTSTAMP: 2290 return ravb_hwtstamp_set(ndev, req); 2291 } 2292 2293 return phy_mii_ioctl(phydev, req, cmd); 2294 } 2295 2296 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2297 { 2298 struct ravb_private *priv = netdev_priv(ndev); 2299 2300 ndev->mtu = new_mtu; 2301 2302 if (netif_running(ndev)) { 2303 synchronize_irq(priv->emac_irq); 2304 ravb_emac_init(ndev); 2305 } 2306 2307 netdev_update_features(ndev); 2308 2309 return 0; 2310 } 2311 2312 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2313 { 2314 struct ravb_private *priv = netdev_priv(ndev); 2315 unsigned long flags; 2316 2317 spin_lock_irqsave(&priv->lock, flags); 2318 2319 /* Disable TX and RX */ 2320 ravb_rcv_snd_disable(ndev); 2321 2322 /* Modify RX Checksum setting */ 2323 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2324 2325 /* Enable TX and RX */ 2326 ravb_rcv_snd_enable(ndev); 2327 2328 spin_unlock_irqrestore(&priv->lock, flags); 2329 } 2330 2331 static int ravb_set_features_gbeth(struct net_device *ndev, 2332 netdev_features_t features) 2333 { 2334 /* Place holder */ 2335 return 0; 2336 } 2337 2338 static int ravb_set_features_rcar(struct net_device *ndev, 2339 netdev_features_t features) 2340 { 2341 netdev_features_t changed = ndev->features ^ features; 2342 2343 if (changed & NETIF_F_RXCSUM) 2344 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2345 2346 ndev->features = features; 2347 2348 return 0; 2349 } 2350 2351 static int ravb_set_features(struct net_device *ndev, 2352 netdev_features_t features) 2353 { 2354 struct ravb_private *priv = netdev_priv(ndev); 2355 const struct ravb_hw_info *info = priv->info; 2356 2357 return info->set_feature(ndev, features); 2358 } 2359 2360 static const struct net_device_ops ravb_netdev_ops = { 2361 .ndo_open = ravb_open, 2362 .ndo_stop = ravb_close, 2363 .ndo_start_xmit = ravb_start_xmit, 2364 .ndo_select_queue = ravb_select_queue, 2365 .ndo_get_stats = ravb_get_stats, 2366 .ndo_set_rx_mode = ravb_set_rx_mode, 2367 .ndo_tx_timeout = ravb_tx_timeout, 2368 .ndo_eth_ioctl = ravb_do_ioctl, 2369 .ndo_change_mtu = ravb_change_mtu, 2370 .ndo_validate_addr = eth_validate_addr, 2371 .ndo_set_mac_address = eth_mac_addr, 2372 .ndo_set_features = ravb_set_features, 2373 }; 2374 2375 /* MDIO bus init function */ 2376 static int ravb_mdio_init(struct ravb_private *priv) 2377 { 2378 struct platform_device *pdev = priv->pdev; 2379 struct device *dev = &pdev->dev; 2380 struct phy_device *phydev; 2381 struct device_node *pn; 2382 int error; 2383 2384 /* Bitbang init */ 2385 priv->mdiobb.ops = &bb_ops; 2386 2387 /* MII controller setting */ 2388 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2389 if (!priv->mii_bus) 2390 return -ENOMEM; 2391 2392 /* Hook up MII support for ethtool */ 2393 priv->mii_bus->name = "ravb_mii"; 2394 priv->mii_bus->parent = dev; 2395 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2396 pdev->name, pdev->id); 2397 2398 /* Register MDIO bus */ 2399 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2400 if (error) 2401 goto out_free_bus; 2402 2403 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2404 phydev = of_phy_find_device(pn); 2405 if (phydev) { 2406 phydev->mac_managed_pm = true; 2407 put_device(&phydev->mdio.dev); 2408 } 2409 of_node_put(pn); 2410 2411 return 0; 2412 2413 out_free_bus: 2414 free_mdio_bitbang(priv->mii_bus); 2415 return error; 2416 } 2417 2418 /* MDIO bus release function */ 2419 static int ravb_mdio_release(struct ravb_private *priv) 2420 { 2421 /* Unregister mdio bus */ 2422 mdiobus_unregister(priv->mii_bus); 2423 2424 /* Free bitbang info */ 2425 free_mdio_bitbang(priv->mii_bus); 2426 2427 return 0; 2428 } 2429 2430 static const struct ravb_hw_info ravb_gen3_hw_info = { 2431 .rx_ring_free = ravb_rx_ring_free_rcar, 2432 .rx_ring_format = ravb_rx_ring_format_rcar, 2433 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2434 .receive = ravb_rx_rcar, 2435 .set_rate = ravb_set_rate_rcar, 2436 .set_feature = ravb_set_features_rcar, 2437 .dmac_init = ravb_dmac_init_rcar, 2438 .emac_init = ravb_emac_init_rcar, 2439 .gstrings_stats = ravb_gstrings_stats, 2440 .gstrings_size = sizeof(ravb_gstrings_stats), 2441 .net_hw_features = NETIF_F_RXCSUM, 2442 .net_features = NETIF_F_RXCSUM, 2443 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2444 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2445 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2446 .rx_max_buf_size = SZ_2K, 2447 .internal_delay = 1, 2448 .tx_counters = 1, 2449 .multi_irqs = 1, 2450 .irq_en_dis = 1, 2451 .ccc_gac = 1, 2452 .nc_queues = 1, 2453 .magic_pkt = 1, 2454 }; 2455 2456 static const struct ravb_hw_info ravb_gen2_hw_info = { 2457 .rx_ring_free = ravb_rx_ring_free_rcar, 2458 .rx_ring_format = ravb_rx_ring_format_rcar, 2459 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2460 .receive = ravb_rx_rcar, 2461 .set_rate = ravb_set_rate_rcar, 2462 .set_feature = ravb_set_features_rcar, 2463 .dmac_init = ravb_dmac_init_rcar, 2464 .emac_init = ravb_emac_init_rcar, 2465 .gstrings_stats = ravb_gstrings_stats, 2466 .gstrings_size = sizeof(ravb_gstrings_stats), 2467 .net_hw_features = NETIF_F_RXCSUM, 2468 .net_features = NETIF_F_RXCSUM, 2469 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2470 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2471 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2472 .rx_max_buf_size = SZ_2K, 2473 .aligned_tx = 1, 2474 .gptp = 1, 2475 .nc_queues = 1, 2476 .magic_pkt = 1, 2477 }; 2478 2479 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2480 .rx_ring_free = ravb_rx_ring_free_rcar, 2481 .rx_ring_format = ravb_rx_ring_format_rcar, 2482 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2483 .receive = ravb_rx_rcar, 2484 .set_rate = ravb_set_rate_rcar, 2485 .set_feature = ravb_set_features_rcar, 2486 .dmac_init = ravb_dmac_init_rcar, 2487 .emac_init = ravb_emac_init_rcar, 2488 .gstrings_stats = ravb_gstrings_stats, 2489 .gstrings_size = sizeof(ravb_gstrings_stats), 2490 .net_hw_features = NETIF_F_RXCSUM, 2491 .net_features = NETIF_F_RXCSUM, 2492 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2493 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2494 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2495 .rx_max_buf_size = SZ_2K, 2496 .multi_irqs = 1, 2497 .err_mgmt_irqs = 1, 2498 .gptp = 1, 2499 .gptp_ref_clk = 1, 2500 .nc_queues = 1, 2501 .magic_pkt = 1, 2502 }; 2503 2504 static const struct ravb_hw_info gbeth_hw_info = { 2505 .rx_ring_free = ravb_rx_ring_free_gbeth, 2506 .rx_ring_format = ravb_rx_ring_format_gbeth, 2507 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2508 .receive = ravb_rx_gbeth, 2509 .set_rate = ravb_set_rate_gbeth, 2510 .set_feature = ravb_set_features_gbeth, 2511 .dmac_init = ravb_dmac_init_gbeth, 2512 .emac_init = ravb_emac_init_gbeth, 2513 .gstrings_stats = ravb_gstrings_stats_gbeth, 2514 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2515 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2516 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), 2517 .tccr_mask = TCCR_TSRQ0, 2518 .rx_max_buf_size = SZ_8K, 2519 .aligned_tx = 1, 2520 .tx_counters = 1, 2521 .carrier_counters = 1, 2522 .half_duplex = 1, 2523 }; 2524 2525 static const struct of_device_id ravb_match_table[] = { 2526 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2527 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2528 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2529 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2530 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2531 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info }, 2532 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2533 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2534 { } 2535 }; 2536 MODULE_DEVICE_TABLE(of, ravb_match_table); 2537 2538 static int ravb_set_gti(struct net_device *ndev) 2539 { 2540 struct ravb_private *priv = netdev_priv(ndev); 2541 const struct ravb_hw_info *info = priv->info; 2542 struct device *dev = ndev->dev.parent; 2543 unsigned long rate; 2544 uint64_t inc; 2545 2546 if (info->gptp_ref_clk) 2547 rate = clk_get_rate(priv->gptp_clk); 2548 else 2549 rate = clk_get_rate(priv->clk); 2550 if (!rate) 2551 return -EINVAL; 2552 2553 inc = div64_ul(1000000000ULL << 20, rate); 2554 2555 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 2556 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 2557 inc, GTI_TIV_MIN, GTI_TIV_MAX); 2558 return -EINVAL; 2559 } 2560 2561 ravb_write(ndev, inc, GTI); 2562 2563 return 0; 2564 } 2565 2566 static int ravb_set_config_mode(struct net_device *ndev) 2567 { 2568 struct ravb_private *priv = netdev_priv(ndev); 2569 const struct ravb_hw_info *info = priv->info; 2570 int error; 2571 2572 if (info->gptp) { 2573 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 2574 if (error) 2575 return error; 2576 /* Set CSEL value */ 2577 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 2578 } else if (info->ccc_gac) { 2579 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 2580 } else { 2581 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 2582 } 2583 2584 return error; 2585 } 2586 2587 /* Set tx and rx clock internal delay modes */ 2588 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2589 { 2590 struct ravb_private *priv = netdev_priv(ndev); 2591 bool explicit_delay = false; 2592 u32 delay; 2593 2594 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2595 /* Valid values are 0 and 1800, according to DT bindings */ 2596 priv->rxcidm = !!delay; 2597 explicit_delay = true; 2598 } 2599 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2600 /* Valid values are 0 and 2000, according to DT bindings */ 2601 priv->txcidm = !!delay; 2602 explicit_delay = true; 2603 } 2604 2605 if (explicit_delay) 2606 return; 2607 2608 /* Fall back to legacy rgmii-*id behavior */ 2609 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2610 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2611 priv->rxcidm = 1; 2612 priv->rgmii_override = 1; 2613 } 2614 2615 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2616 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2617 priv->txcidm = 1; 2618 priv->rgmii_override = 1; 2619 } 2620 } 2621 2622 static void ravb_set_delay_mode(struct net_device *ndev) 2623 { 2624 struct ravb_private *priv = netdev_priv(ndev); 2625 u32 set = 0; 2626 2627 if (priv->rxcidm) 2628 set |= APSR_RDM; 2629 if (priv->txcidm) 2630 set |= APSR_TDM; 2631 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2632 } 2633 2634 static int ravb_probe(struct platform_device *pdev) 2635 { 2636 struct device_node *np = pdev->dev.of_node; 2637 const struct ravb_hw_info *info; 2638 struct reset_control *rstc; 2639 struct ravb_private *priv; 2640 struct net_device *ndev; 2641 int error, irq, q; 2642 struct resource *res; 2643 int i; 2644 2645 if (!np) { 2646 dev_err(&pdev->dev, 2647 "this driver is required to be instantiated from device tree\n"); 2648 return -EINVAL; 2649 } 2650 2651 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2652 if (IS_ERR(rstc)) 2653 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2654 "failed to get cpg reset\n"); 2655 2656 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2657 NUM_TX_QUEUE, NUM_RX_QUEUE); 2658 if (!ndev) 2659 return -ENOMEM; 2660 2661 info = of_device_get_match_data(&pdev->dev); 2662 2663 ndev->features = info->net_features; 2664 ndev->hw_features = info->net_hw_features; 2665 2666 error = reset_control_deassert(rstc); 2667 if (error) 2668 goto out_free_netdev; 2669 2670 pm_runtime_enable(&pdev->dev); 2671 error = pm_runtime_resume_and_get(&pdev->dev); 2672 if (error < 0) 2673 goto out_rpm_disable; 2674 2675 if (info->multi_irqs) { 2676 if (info->err_mgmt_irqs) 2677 irq = platform_get_irq_byname(pdev, "dia"); 2678 else 2679 irq = platform_get_irq_byname(pdev, "ch22"); 2680 } else { 2681 irq = platform_get_irq(pdev, 0); 2682 } 2683 if (irq < 0) { 2684 error = irq; 2685 goto out_release; 2686 } 2687 ndev->irq = irq; 2688 2689 SET_NETDEV_DEV(ndev, &pdev->dev); 2690 2691 priv = netdev_priv(ndev); 2692 priv->info = info; 2693 priv->rstc = rstc; 2694 priv->ndev = ndev; 2695 priv->pdev = pdev; 2696 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2697 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2698 if (info->nc_queues) { 2699 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2700 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2701 } 2702 2703 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2704 if (IS_ERR(priv->addr)) { 2705 error = PTR_ERR(priv->addr); 2706 goto out_release; 2707 } 2708 2709 /* The Ether-specific entries in the device structure. */ 2710 ndev->base_addr = res->start; 2711 2712 spin_lock_init(&priv->lock); 2713 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2714 2715 error = of_get_phy_mode(np, &priv->phy_interface); 2716 if (error && error != -ENODEV) 2717 goto out_release; 2718 2719 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2720 priv->avb_link_active_low = 2721 of_property_read_bool(np, "renesas,ether-link-active-low"); 2722 2723 if (info->multi_irqs) { 2724 if (info->err_mgmt_irqs) 2725 irq = platform_get_irq_byname(pdev, "line3"); 2726 else 2727 irq = platform_get_irq_byname(pdev, "ch24"); 2728 if (irq < 0) { 2729 error = irq; 2730 goto out_release; 2731 } 2732 priv->emac_irq = irq; 2733 for (i = 0; i < NUM_RX_QUEUE; i++) { 2734 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2735 if (irq < 0) { 2736 error = irq; 2737 goto out_release; 2738 } 2739 priv->rx_irqs[i] = irq; 2740 } 2741 for (i = 0; i < NUM_TX_QUEUE; i++) { 2742 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2743 if (irq < 0) { 2744 error = irq; 2745 goto out_release; 2746 } 2747 priv->tx_irqs[i] = irq; 2748 } 2749 2750 if (info->err_mgmt_irqs) { 2751 irq = platform_get_irq_byname(pdev, "err_a"); 2752 if (irq < 0) { 2753 error = irq; 2754 goto out_release; 2755 } 2756 priv->erra_irq = irq; 2757 2758 irq = platform_get_irq_byname(pdev, "mgmt_a"); 2759 if (irq < 0) { 2760 error = irq; 2761 goto out_release; 2762 } 2763 priv->mgmta_irq = irq; 2764 } 2765 } 2766 2767 priv->clk = devm_clk_get(&pdev->dev, NULL); 2768 if (IS_ERR(priv->clk)) { 2769 error = PTR_ERR(priv->clk); 2770 goto out_release; 2771 } 2772 2773 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2774 if (IS_ERR(priv->refclk)) { 2775 error = PTR_ERR(priv->refclk); 2776 goto out_release; 2777 } 2778 clk_prepare_enable(priv->refclk); 2779 2780 if (info->gptp_ref_clk) { 2781 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2782 if (IS_ERR(priv->gptp_clk)) { 2783 error = PTR_ERR(priv->gptp_clk); 2784 goto out_disable_refclk; 2785 } 2786 clk_prepare_enable(priv->gptp_clk); 2787 } 2788 2789 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2790 ndev->min_mtu = ETH_MIN_MTU; 2791 2792 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2793 * Use two descriptor to handle such situation. First descriptor to 2794 * handle aligned data buffer and second descriptor to handle the 2795 * overflow data because of alignment. 2796 */ 2797 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2798 2799 /* Set function */ 2800 ndev->netdev_ops = &ravb_netdev_ops; 2801 ndev->ethtool_ops = &ravb_ethtool_ops; 2802 2803 /* Set AVB config mode */ 2804 error = ravb_set_config_mode(ndev); 2805 if (error) 2806 goto out_disable_gptp_clk; 2807 2808 if (info->gptp || info->ccc_gac) { 2809 /* Set GTI value */ 2810 error = ravb_set_gti(ndev); 2811 if (error) 2812 goto out_disable_gptp_clk; 2813 2814 /* Request GTI loading */ 2815 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2816 } 2817 2818 if (info->internal_delay) { 2819 ravb_parse_delay_mode(np, ndev); 2820 ravb_set_delay_mode(ndev); 2821 } 2822 2823 /* Allocate descriptor base address table */ 2824 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2825 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2826 &priv->desc_bat_dma, GFP_KERNEL); 2827 if (!priv->desc_bat) { 2828 dev_err(&pdev->dev, 2829 "Cannot allocate desc base address table (size %d bytes)\n", 2830 priv->desc_bat_size); 2831 error = -ENOMEM; 2832 goto out_disable_gptp_clk; 2833 } 2834 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2835 priv->desc_bat[q].die_dt = DT_EOS; 2836 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2837 2838 /* Initialise HW timestamp list */ 2839 INIT_LIST_HEAD(&priv->ts_skb_list); 2840 2841 /* Initialise PTP Clock driver */ 2842 if (info->ccc_gac) 2843 ravb_ptp_init(ndev, pdev); 2844 2845 /* Debug message level */ 2846 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2847 2848 /* Read and set MAC address */ 2849 ravb_read_mac_address(np, ndev); 2850 if (!is_valid_ether_addr(ndev->dev_addr)) { 2851 dev_warn(&pdev->dev, 2852 "no valid MAC address supplied, using a random one\n"); 2853 eth_hw_addr_random(ndev); 2854 } 2855 2856 /* MDIO bus init */ 2857 error = ravb_mdio_init(priv); 2858 if (error) { 2859 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2860 goto out_dma_free; 2861 } 2862 2863 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 2864 if (info->nc_queues) 2865 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 2866 2867 /* Network device register */ 2868 error = register_netdev(ndev); 2869 if (error) 2870 goto out_napi_del; 2871 2872 device_set_wakeup_capable(&pdev->dev, 1); 2873 2874 /* Print device information */ 2875 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2876 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2877 2878 platform_set_drvdata(pdev, ndev); 2879 2880 return 0; 2881 2882 out_napi_del: 2883 if (info->nc_queues) 2884 netif_napi_del(&priv->napi[RAVB_NC]); 2885 2886 netif_napi_del(&priv->napi[RAVB_BE]); 2887 ravb_mdio_release(priv); 2888 out_dma_free: 2889 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2890 priv->desc_bat_dma); 2891 2892 /* Stop PTP Clock driver */ 2893 if (info->ccc_gac) 2894 ravb_ptp_stop(ndev); 2895 out_disable_gptp_clk: 2896 clk_disable_unprepare(priv->gptp_clk); 2897 out_disable_refclk: 2898 clk_disable_unprepare(priv->refclk); 2899 out_release: 2900 pm_runtime_put(&pdev->dev); 2901 out_rpm_disable: 2902 pm_runtime_disable(&pdev->dev); 2903 reset_control_assert(rstc); 2904 out_free_netdev: 2905 free_netdev(ndev); 2906 return error; 2907 } 2908 2909 static int ravb_remove(struct platform_device *pdev) 2910 { 2911 struct net_device *ndev = platform_get_drvdata(pdev); 2912 struct ravb_private *priv = netdev_priv(ndev); 2913 const struct ravb_hw_info *info = priv->info; 2914 2915 unregister_netdev(ndev); 2916 if (info->nc_queues) 2917 netif_napi_del(&priv->napi[RAVB_NC]); 2918 netif_napi_del(&priv->napi[RAVB_BE]); 2919 2920 ravb_mdio_release(priv); 2921 2922 /* Stop PTP Clock driver */ 2923 if (info->ccc_gac) 2924 ravb_ptp_stop(ndev); 2925 2926 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2927 priv->desc_bat_dma); 2928 2929 ravb_set_opmode(ndev, CCC_OPC_RESET); 2930 2931 clk_disable_unprepare(priv->gptp_clk); 2932 clk_disable_unprepare(priv->refclk); 2933 2934 pm_runtime_put_sync(&pdev->dev); 2935 pm_runtime_disable(&pdev->dev); 2936 reset_control_assert(priv->rstc); 2937 free_netdev(ndev); 2938 platform_set_drvdata(pdev, NULL); 2939 2940 return 0; 2941 } 2942 2943 static int ravb_wol_setup(struct net_device *ndev) 2944 { 2945 struct ravb_private *priv = netdev_priv(ndev); 2946 const struct ravb_hw_info *info = priv->info; 2947 2948 /* Disable interrupts by clearing the interrupt masks. */ 2949 ravb_write(ndev, 0, RIC0); 2950 ravb_write(ndev, 0, RIC2); 2951 ravb_write(ndev, 0, TIC); 2952 2953 /* Only allow ECI interrupts */ 2954 synchronize_irq(priv->emac_irq); 2955 if (info->nc_queues) 2956 napi_disable(&priv->napi[RAVB_NC]); 2957 napi_disable(&priv->napi[RAVB_BE]); 2958 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2959 2960 /* Enable MagicPacket */ 2961 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2962 2963 return enable_irq_wake(priv->emac_irq); 2964 } 2965 2966 static int ravb_wol_restore(struct net_device *ndev) 2967 { 2968 struct ravb_private *priv = netdev_priv(ndev); 2969 const struct ravb_hw_info *info = priv->info; 2970 2971 if (info->nc_queues) 2972 napi_enable(&priv->napi[RAVB_NC]); 2973 napi_enable(&priv->napi[RAVB_BE]); 2974 2975 /* Disable MagicPacket */ 2976 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2977 2978 ravb_close(ndev); 2979 2980 return disable_irq_wake(priv->emac_irq); 2981 } 2982 2983 static int __maybe_unused ravb_suspend(struct device *dev) 2984 { 2985 struct net_device *ndev = dev_get_drvdata(dev); 2986 struct ravb_private *priv = netdev_priv(ndev); 2987 int ret; 2988 2989 if (!netif_running(ndev)) 2990 return 0; 2991 2992 netif_device_detach(ndev); 2993 2994 if (priv->wol_enabled) 2995 ret = ravb_wol_setup(ndev); 2996 else 2997 ret = ravb_close(ndev); 2998 2999 if (priv->info->ccc_gac) 3000 ravb_ptp_stop(ndev); 3001 3002 return ret; 3003 } 3004 3005 static int __maybe_unused ravb_resume(struct device *dev) 3006 { 3007 struct net_device *ndev = dev_get_drvdata(dev); 3008 struct ravb_private *priv = netdev_priv(ndev); 3009 const struct ravb_hw_info *info = priv->info; 3010 int ret = 0; 3011 3012 /* If WoL is enabled set reset mode to rearm the WoL logic */ 3013 if (priv->wol_enabled) { 3014 ret = ravb_set_opmode(ndev, CCC_OPC_RESET); 3015 if (ret) 3016 return ret; 3017 } 3018 3019 /* All register have been reset to default values. 3020 * Restore all registers which where setup at probe time and 3021 * reopen device if it was running before system suspended. 3022 */ 3023 3024 /* Set AVB config mode */ 3025 ret = ravb_set_config_mode(ndev); 3026 if (ret) 3027 return ret; 3028 3029 if (info->gptp || info->ccc_gac) { 3030 /* Set GTI value */ 3031 ret = ravb_set_gti(ndev); 3032 if (ret) 3033 return ret; 3034 3035 /* Request GTI loading */ 3036 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 3037 } 3038 3039 if (info->internal_delay) 3040 ravb_set_delay_mode(ndev); 3041 3042 /* Restore descriptor base address table */ 3043 ravb_write(ndev, priv->desc_bat_dma, DBAT); 3044 3045 if (priv->info->ccc_gac) 3046 ravb_ptp_init(ndev, priv->pdev); 3047 3048 if (netif_running(ndev)) { 3049 if (priv->wol_enabled) { 3050 ret = ravb_wol_restore(ndev); 3051 if (ret) 3052 return ret; 3053 } 3054 ret = ravb_open(ndev); 3055 if (ret < 0) 3056 return ret; 3057 ravb_set_rx_mode(ndev); 3058 netif_device_attach(ndev); 3059 } 3060 3061 return ret; 3062 } 3063 3064 static int __maybe_unused ravb_runtime_nop(struct device *dev) 3065 { 3066 /* Runtime PM callback shared between ->runtime_suspend() 3067 * and ->runtime_resume(). Simply returns success. 3068 * 3069 * This driver re-initializes all registers after 3070 * pm_runtime_get_sync() anyway so there is no need 3071 * to save and restore registers here. 3072 */ 3073 return 0; 3074 } 3075 3076 static const struct dev_pm_ops ravb_dev_pm_ops = { 3077 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3078 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 3079 }; 3080 3081 static struct platform_driver ravb_driver = { 3082 .probe = ravb_probe, 3083 .remove = ravb_remove, 3084 .driver = { 3085 .name = "ravb", 3086 .pm = &ravb_dev_pm_ops, 3087 .of_match_table = ravb_match_table, 3088 }, 3089 }; 3090 3091 module_platform_driver(ravb_driver); 3092 3093 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3094 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3095 MODULE_LICENSE("GPL v2"); 3096