1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/reset.h> 32 #include <linux/math64.h> 33 34 #include "ravb.h" 35 36 #define RAVB_DEF_MSG_ENABLE \ 37 (NETIF_MSG_LINK | \ 38 NETIF_MSG_TIMER | \ 39 NETIF_MSG_RX_ERR | \ 40 NETIF_MSG_TX_ERR) 41 42 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 43 "ch0", /* RAVB_BE */ 44 "ch1", /* RAVB_NC */ 45 }; 46 47 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 48 "ch18", /* RAVB_BE */ 49 "ch19", /* RAVB_NC */ 50 }; 51 52 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 53 u32 set) 54 { 55 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 56 } 57 58 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 59 { 60 int i; 61 62 for (i = 0; i < 10000; i++) { 63 if ((ravb_read(ndev, reg) & mask) == value) 64 return 0; 65 udelay(10); 66 } 67 return -ETIMEDOUT; 68 } 69 70 static int ravb_config(struct net_device *ndev) 71 { 72 int error; 73 74 /* Set config mode */ 75 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 76 /* Check if the operating mode is changed to the config mode */ 77 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 78 if (error) 79 netdev_err(ndev, "failed to switch device to config mode\n"); 80 81 return error; 82 } 83 84 static void ravb_set_rate_gbeth(struct net_device *ndev) 85 { 86 struct ravb_private *priv = netdev_priv(ndev); 87 88 switch (priv->speed) { 89 case 10: /* 10BASE */ 90 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 91 break; 92 case 100: /* 100BASE */ 93 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 94 break; 95 case 1000: /* 1000BASE */ 96 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 97 break; 98 } 99 } 100 101 static void ravb_set_rate_rcar(struct net_device *ndev) 102 { 103 struct ravb_private *priv = netdev_priv(ndev); 104 105 switch (priv->speed) { 106 case 100: /* 100BASE */ 107 ravb_write(ndev, GECMR_SPEED_100, GECMR); 108 break; 109 case 1000: /* 1000BASE */ 110 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 111 break; 112 } 113 } 114 115 static void ravb_set_buffer_align(struct sk_buff *skb) 116 { 117 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 118 119 if (reserve) 120 skb_reserve(skb, RAVB_ALIGN - reserve); 121 } 122 123 /* Get MAC address from the MAC address registers 124 * 125 * Ethernet AVB device doesn't have ROM for MAC address. 126 * This function gets the MAC address that was used by a bootloader. 127 */ 128 static void ravb_read_mac_address(struct device_node *np, 129 struct net_device *ndev) 130 { 131 int ret; 132 133 ret = of_get_ethdev_address(np, ndev); 134 if (ret) { 135 u32 mahr = ravb_read(ndev, MAHR); 136 u32 malr = ravb_read(ndev, MALR); 137 u8 addr[ETH_ALEN]; 138 139 addr[0] = (mahr >> 24) & 0xFF; 140 addr[1] = (mahr >> 16) & 0xFF; 141 addr[2] = (mahr >> 8) & 0xFF; 142 addr[3] = (mahr >> 0) & 0xFF; 143 addr[4] = (malr >> 8) & 0xFF; 144 addr[5] = (malr >> 0) & 0xFF; 145 eth_hw_addr_set(ndev, addr); 146 } 147 } 148 149 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 150 { 151 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 152 mdiobb); 153 154 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 155 } 156 157 /* MDC pin control */ 158 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 161 } 162 163 /* Data I/O pin control */ 164 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 167 } 168 169 /* Set data bit */ 170 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 171 { 172 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 173 } 174 175 /* Get data bit */ 176 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 177 { 178 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 179 mdiobb); 180 181 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 182 } 183 184 /* MDIO bus control struct */ 185 static const struct mdiobb_ops bb_ops = { 186 .owner = THIS_MODULE, 187 .set_mdc = ravb_set_mdc, 188 .set_mdio_dir = ravb_set_mdio_dir, 189 .set_mdio_data = ravb_set_mdio_data, 190 .get_mdio_data = ravb_get_mdio_data, 191 }; 192 193 /* Free TX skb function for AVB-IP */ 194 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 195 { 196 struct ravb_private *priv = netdev_priv(ndev); 197 struct net_device_stats *stats = &priv->stats[q]; 198 unsigned int num_tx_desc = priv->num_tx_desc; 199 struct ravb_tx_desc *desc; 200 unsigned int entry; 201 int free_num = 0; 202 u32 size; 203 204 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 205 bool txed; 206 207 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 208 num_tx_desc); 209 desc = &priv->tx_ring[q][entry]; 210 txed = desc->die_dt == DT_FEMPTY; 211 if (free_txed_only && !txed) 212 break; 213 /* Descriptor type must be checked before all other reads */ 214 dma_rmb(); 215 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 216 /* Free the original skb. */ 217 if (priv->tx_skb[q][entry / num_tx_desc]) { 218 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 219 size, DMA_TO_DEVICE); 220 /* Last packet descriptor? */ 221 if (entry % num_tx_desc == num_tx_desc - 1) { 222 entry /= num_tx_desc; 223 dev_kfree_skb_any(priv->tx_skb[q][entry]); 224 priv->tx_skb[q][entry] = NULL; 225 if (txed) 226 stats->tx_packets++; 227 } 228 free_num++; 229 } 230 if (txed) 231 stats->tx_bytes += size; 232 desc->die_dt = DT_EEMPTY; 233 } 234 return free_num; 235 } 236 237 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 238 { 239 struct ravb_private *priv = netdev_priv(ndev); 240 unsigned int ring_size; 241 unsigned int i; 242 243 if (!priv->gbeth_rx_ring) 244 return; 245 246 for (i = 0; i < priv->num_rx_ring[q]; i++) { 247 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i]; 248 249 if (!dma_mapping_error(ndev->dev.parent, 250 le32_to_cpu(desc->dptr))) 251 dma_unmap_single(ndev->dev.parent, 252 le32_to_cpu(desc->dptr), 253 GBETH_RX_BUFF_MAX, 254 DMA_FROM_DEVICE); 255 } 256 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 257 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring, 258 priv->rx_desc_dma[q]); 259 priv->gbeth_rx_ring = NULL; 260 } 261 262 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q) 263 { 264 struct ravb_private *priv = netdev_priv(ndev); 265 unsigned int ring_size; 266 unsigned int i; 267 268 if (!priv->rx_ring[q]) 269 return; 270 271 for (i = 0; i < priv->num_rx_ring[q]; i++) { 272 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 273 274 if (!dma_mapping_error(ndev->dev.parent, 275 le32_to_cpu(desc->dptr))) 276 dma_unmap_single(ndev->dev.parent, 277 le32_to_cpu(desc->dptr), 278 RX_BUF_SZ, 279 DMA_FROM_DEVICE); 280 } 281 ring_size = sizeof(struct ravb_ex_rx_desc) * 282 (priv->num_rx_ring[q] + 1); 283 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 284 priv->rx_desc_dma[q]); 285 priv->rx_ring[q] = NULL; 286 } 287 288 /* Free skb's and DMA buffers for Ethernet AVB */ 289 static void ravb_ring_free(struct net_device *ndev, int q) 290 { 291 struct ravb_private *priv = netdev_priv(ndev); 292 const struct ravb_hw_info *info = priv->info; 293 unsigned int num_tx_desc = priv->num_tx_desc; 294 unsigned int ring_size; 295 unsigned int i; 296 297 info->rx_ring_free(ndev, q); 298 299 if (priv->tx_ring[q]) { 300 ravb_tx_free(ndev, q, false); 301 302 ring_size = sizeof(struct ravb_tx_desc) * 303 (priv->num_tx_ring[q] * num_tx_desc + 1); 304 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 305 priv->tx_desc_dma[q]); 306 priv->tx_ring[q] = NULL; 307 } 308 309 /* Free RX skb ringbuffer */ 310 if (priv->rx_skb[q]) { 311 for (i = 0; i < priv->num_rx_ring[q]; i++) 312 dev_kfree_skb(priv->rx_skb[q][i]); 313 } 314 kfree(priv->rx_skb[q]); 315 priv->rx_skb[q] = NULL; 316 317 /* Free aligned TX buffers */ 318 kfree(priv->tx_align[q]); 319 priv->tx_align[q] = NULL; 320 321 /* Free TX skb ringbuffer. 322 * SKBs are freed by ravb_tx_free() call above. 323 */ 324 kfree(priv->tx_skb[q]); 325 priv->tx_skb[q] = NULL; 326 } 327 328 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 329 { 330 struct ravb_private *priv = netdev_priv(ndev); 331 struct ravb_rx_desc *rx_desc; 332 unsigned int rx_ring_size; 333 dma_addr_t dma_addr; 334 unsigned int i; 335 336 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 337 memset(priv->gbeth_rx_ring, 0, rx_ring_size); 338 /* Build RX ring buffer */ 339 for (i = 0; i < priv->num_rx_ring[q]; i++) { 340 /* RX descriptor */ 341 rx_desc = &priv->gbeth_rx_ring[i]; 342 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 343 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 344 GBETH_RX_BUFF_MAX, 345 DMA_FROM_DEVICE); 346 /* We just set the data size to 0 for a failed mapping which 347 * should prevent DMA from happening... 348 */ 349 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 350 rx_desc->ds_cc = cpu_to_le16(0); 351 rx_desc->dptr = cpu_to_le32(dma_addr); 352 rx_desc->die_dt = DT_FEMPTY; 353 } 354 rx_desc = &priv->gbeth_rx_ring[i]; 355 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 356 rx_desc->die_dt = DT_LINKFIX; /* type */ 357 } 358 359 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q) 360 { 361 struct ravb_private *priv = netdev_priv(ndev); 362 struct ravb_ex_rx_desc *rx_desc; 363 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 364 dma_addr_t dma_addr; 365 unsigned int i; 366 367 memset(priv->rx_ring[q], 0, rx_ring_size); 368 /* Build RX ring buffer */ 369 for (i = 0; i < priv->num_rx_ring[q]; i++) { 370 /* RX descriptor */ 371 rx_desc = &priv->rx_ring[q][i]; 372 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 373 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 374 RX_BUF_SZ, 375 DMA_FROM_DEVICE); 376 /* We just set the data size to 0 for a failed mapping which 377 * should prevent DMA from happening... 378 */ 379 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 380 rx_desc->ds_cc = cpu_to_le16(0); 381 rx_desc->dptr = cpu_to_le32(dma_addr); 382 rx_desc->die_dt = DT_FEMPTY; 383 } 384 rx_desc = &priv->rx_ring[q][i]; 385 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 386 rx_desc->die_dt = DT_LINKFIX; /* type */ 387 } 388 389 /* Format skb and descriptor buffer for Ethernet AVB */ 390 static void ravb_ring_format(struct net_device *ndev, int q) 391 { 392 struct ravb_private *priv = netdev_priv(ndev); 393 const struct ravb_hw_info *info = priv->info; 394 unsigned int num_tx_desc = priv->num_tx_desc; 395 struct ravb_tx_desc *tx_desc; 396 struct ravb_desc *desc; 397 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 398 num_tx_desc; 399 unsigned int i; 400 401 priv->cur_rx[q] = 0; 402 priv->cur_tx[q] = 0; 403 priv->dirty_rx[q] = 0; 404 priv->dirty_tx[q] = 0; 405 406 info->rx_ring_format(ndev, q); 407 408 memset(priv->tx_ring[q], 0, tx_ring_size); 409 /* Build TX ring buffer */ 410 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 411 i++, tx_desc++) { 412 tx_desc->die_dt = DT_EEMPTY; 413 if (num_tx_desc > 1) { 414 tx_desc++; 415 tx_desc->die_dt = DT_EEMPTY; 416 } 417 } 418 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 419 tx_desc->die_dt = DT_LINKFIX; /* type */ 420 421 /* RX descriptor base address for best effort */ 422 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 423 desc->die_dt = DT_LINKFIX; /* type */ 424 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 425 426 /* TX descriptor base address for best effort */ 427 desc = &priv->desc_bat[q]; 428 desc->die_dt = DT_LINKFIX; /* type */ 429 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 430 } 431 432 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 433 { 434 struct ravb_private *priv = netdev_priv(ndev); 435 unsigned int ring_size; 436 437 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 438 439 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size, 440 &priv->rx_desc_dma[q], 441 GFP_KERNEL); 442 return priv->gbeth_rx_ring; 443 } 444 445 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q) 446 { 447 struct ravb_private *priv = netdev_priv(ndev); 448 unsigned int ring_size; 449 450 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 451 452 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 453 &priv->rx_desc_dma[q], 454 GFP_KERNEL); 455 return priv->rx_ring[q]; 456 } 457 458 /* Init skb and descriptor buffer for Ethernet AVB */ 459 static int ravb_ring_init(struct net_device *ndev, int q) 460 { 461 struct ravb_private *priv = netdev_priv(ndev); 462 const struct ravb_hw_info *info = priv->info; 463 unsigned int num_tx_desc = priv->num_tx_desc; 464 unsigned int ring_size; 465 struct sk_buff *skb; 466 unsigned int i; 467 468 /* Allocate RX and TX skb rings */ 469 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 470 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 471 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 472 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 473 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 474 goto error; 475 476 for (i = 0; i < priv->num_rx_ring[q]; i++) { 477 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL); 478 if (!skb) 479 goto error; 480 ravb_set_buffer_align(skb); 481 priv->rx_skb[q][i] = skb; 482 } 483 484 if (num_tx_desc > 1) { 485 /* Allocate rings for the aligned buffers */ 486 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 487 DPTR_ALIGN - 1, GFP_KERNEL); 488 if (!priv->tx_align[q]) 489 goto error; 490 } 491 492 /* Allocate all RX descriptors. */ 493 if (!info->alloc_rx_desc(ndev, q)) 494 goto error; 495 496 priv->dirty_rx[q] = 0; 497 498 /* Allocate all TX descriptors. */ 499 ring_size = sizeof(struct ravb_tx_desc) * 500 (priv->num_tx_ring[q] * num_tx_desc + 1); 501 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 502 &priv->tx_desc_dma[q], 503 GFP_KERNEL); 504 if (!priv->tx_ring[q]) 505 goto error; 506 507 return 0; 508 509 error: 510 ravb_ring_free(ndev, q); 511 512 return -ENOMEM; 513 } 514 515 static void ravb_emac_init_gbeth(struct net_device *ndev) 516 { 517 struct ravb_private *priv = netdev_priv(ndev); 518 519 /* Receive frame limit set register */ 520 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 521 522 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 523 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 524 ECMR_TE | ECMR_RE | ECMR_RCPT | 525 ECMR_TXF | ECMR_RXF, ECMR); 526 527 ravb_set_rate_gbeth(ndev); 528 529 /* Set MAC address */ 530 ravb_write(ndev, 531 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 532 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 533 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 534 535 /* E-MAC status register clear */ 536 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 537 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 538 539 /* E-MAC interrupt enable register */ 540 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 541 542 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 543 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 544 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 545 } else { 546 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 547 CXR31_SEL_LINK0); 548 } 549 } 550 551 static void ravb_emac_init_rcar(struct net_device *ndev) 552 { 553 /* Receive frame limit set register */ 554 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 555 556 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 557 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 558 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 559 ECMR_TE | ECMR_RE, ECMR); 560 561 ravb_set_rate_rcar(ndev); 562 563 /* Set MAC address */ 564 ravb_write(ndev, 565 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 566 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 567 ravb_write(ndev, 568 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 569 570 /* E-MAC status register clear */ 571 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 572 573 /* E-MAC interrupt enable register */ 574 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 575 } 576 577 /* E-MAC init function */ 578 static void ravb_emac_init(struct net_device *ndev) 579 { 580 struct ravb_private *priv = netdev_priv(ndev); 581 const struct ravb_hw_info *info = priv->info; 582 583 info->emac_init(ndev); 584 } 585 586 static int ravb_dmac_init_gbeth(struct net_device *ndev) 587 { 588 int error; 589 590 error = ravb_ring_init(ndev, RAVB_BE); 591 if (error) 592 return error; 593 594 /* Descriptor format */ 595 ravb_ring_format(ndev, RAVB_BE); 596 597 /* Set DMAC RX */ 598 ravb_write(ndev, 0x60000000, RCR); 599 600 /* Set Max Frame Length (RTC) */ 601 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 602 603 /* Set FIFO size */ 604 ravb_write(ndev, 0x00222200, TGC); 605 606 ravb_write(ndev, 0, TCCR); 607 608 /* Frame receive */ 609 ravb_write(ndev, RIC0_FRE0, RIC0); 610 /* Disable FIFO full warning */ 611 ravb_write(ndev, 0x0, RIC1); 612 /* Receive FIFO full error, descriptor empty */ 613 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 614 615 ravb_write(ndev, TIC_FTE0, TIC); 616 617 return 0; 618 } 619 620 static int ravb_dmac_init_rcar(struct net_device *ndev) 621 { 622 struct ravb_private *priv = netdev_priv(ndev); 623 const struct ravb_hw_info *info = priv->info; 624 int error; 625 626 error = ravb_ring_init(ndev, RAVB_BE); 627 if (error) 628 return error; 629 error = ravb_ring_init(ndev, RAVB_NC); 630 if (error) { 631 ravb_ring_free(ndev, RAVB_BE); 632 return error; 633 } 634 635 /* Descriptor format */ 636 ravb_ring_format(ndev, RAVB_BE); 637 ravb_ring_format(ndev, RAVB_NC); 638 639 /* Set AVB RX */ 640 ravb_write(ndev, 641 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 642 643 /* Set FIFO size */ 644 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 645 646 /* Timestamp enable */ 647 ravb_write(ndev, TCCR_TFEN, TCCR); 648 649 /* Interrupt init: */ 650 if (info->multi_irqs) { 651 /* Clear DIL.DPLx */ 652 ravb_write(ndev, 0, DIL); 653 /* Set queue specific interrupt */ 654 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 655 } 656 /* Frame receive */ 657 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 658 /* Disable FIFO full warning */ 659 ravb_write(ndev, 0, RIC1); 660 /* Receive FIFO full error, descriptor empty */ 661 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 662 /* Frame transmitted, timestamp FIFO updated */ 663 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 664 665 return 0; 666 } 667 668 /* Device init function for Ethernet AVB */ 669 static int ravb_dmac_init(struct net_device *ndev) 670 { 671 struct ravb_private *priv = netdev_priv(ndev); 672 const struct ravb_hw_info *info = priv->info; 673 int error; 674 675 /* Set CONFIG mode */ 676 error = ravb_config(ndev); 677 if (error) 678 return error; 679 680 error = info->dmac_init(ndev); 681 if (error) 682 return error; 683 684 /* Setting the control will start the AVB-DMAC process. */ 685 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 686 687 return 0; 688 } 689 690 static void ravb_get_tx_tstamp(struct net_device *ndev) 691 { 692 struct ravb_private *priv = netdev_priv(ndev); 693 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 694 struct skb_shared_hwtstamps shhwtstamps; 695 struct sk_buff *skb; 696 struct timespec64 ts; 697 u16 tag, tfa_tag; 698 int count; 699 u32 tfa2; 700 701 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 702 while (count--) { 703 tfa2 = ravb_read(ndev, TFA2); 704 tfa_tag = (tfa2 & TFA2_TST) >> 16; 705 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 706 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 707 ravb_read(ndev, TFA1); 708 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 709 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 710 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 711 list) { 712 skb = ts_skb->skb; 713 tag = ts_skb->tag; 714 list_del(&ts_skb->list); 715 kfree(ts_skb); 716 if (tag == tfa_tag) { 717 skb_tstamp_tx(skb, &shhwtstamps); 718 dev_consume_skb_any(skb); 719 break; 720 } else { 721 dev_kfree_skb_any(skb); 722 } 723 } 724 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 725 } 726 } 727 728 static void ravb_rx_csum(struct sk_buff *skb) 729 { 730 u8 *hw_csum; 731 732 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 733 * appended to packet data 734 */ 735 if (unlikely(skb->len < sizeof(__sum16))) 736 return; 737 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 738 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 739 skb->ip_summed = CHECKSUM_COMPLETE; 740 skb_trim(skb, skb->len - sizeof(__sum16)); 741 } 742 743 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 744 struct ravb_rx_desc *desc) 745 { 746 struct ravb_private *priv = netdev_priv(ndev); 747 struct sk_buff *skb; 748 749 skb = priv->rx_skb[RAVB_BE][entry]; 750 priv->rx_skb[RAVB_BE][entry] = NULL; 751 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 752 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE); 753 754 return skb; 755 } 756 757 /* Packet receive function for Gigabit Ethernet */ 758 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 759 { 760 struct ravb_private *priv = netdev_priv(ndev); 761 const struct ravb_hw_info *info = priv->info; 762 struct net_device_stats *stats; 763 struct ravb_rx_desc *desc; 764 struct sk_buff *skb; 765 dma_addr_t dma_addr; 766 u8 desc_status; 767 int boguscnt; 768 u16 pkt_len; 769 u8 die_dt; 770 int entry; 771 int limit; 772 773 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 774 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 775 stats = &priv->stats[q]; 776 777 boguscnt = min(boguscnt, *quota); 778 limit = boguscnt; 779 desc = &priv->gbeth_rx_ring[entry]; 780 while (desc->die_dt != DT_FEMPTY) { 781 /* Descriptor type must be checked before all other reads */ 782 dma_rmb(); 783 desc_status = desc->msc; 784 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 785 786 if (--boguscnt < 0) 787 break; 788 789 /* We use 0-byte descriptors to mark the DMA mapping errors */ 790 if (!pkt_len) 791 continue; 792 793 if (desc_status & MSC_MC) 794 stats->multicast++; 795 796 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 797 stats->rx_errors++; 798 if (desc_status & MSC_CRC) 799 stats->rx_crc_errors++; 800 if (desc_status & MSC_RFE) 801 stats->rx_frame_errors++; 802 if (desc_status & (MSC_RTLF | MSC_RTSF)) 803 stats->rx_length_errors++; 804 if (desc_status & MSC_CEEF) 805 stats->rx_missed_errors++; 806 } else { 807 die_dt = desc->die_dt & 0xF0; 808 switch (die_dt) { 809 case DT_FSINGLE: 810 skb = ravb_get_skb_gbeth(ndev, entry, desc); 811 skb_put(skb, pkt_len); 812 skb->protocol = eth_type_trans(skb, ndev); 813 napi_gro_receive(&priv->napi[q], skb); 814 stats->rx_packets++; 815 stats->rx_bytes += pkt_len; 816 break; 817 case DT_FSTART: 818 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 819 skb_put(priv->rx_1st_skb, pkt_len); 820 break; 821 case DT_FMID: 822 skb = ravb_get_skb_gbeth(ndev, entry, desc); 823 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 824 priv->rx_1st_skb->len, 825 skb->data, 826 pkt_len); 827 skb_put(priv->rx_1st_skb, pkt_len); 828 dev_kfree_skb(skb); 829 break; 830 case DT_FEND: 831 skb = ravb_get_skb_gbeth(ndev, entry, desc); 832 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 833 priv->rx_1st_skb->len, 834 skb->data, 835 pkt_len); 836 skb_put(priv->rx_1st_skb, pkt_len); 837 dev_kfree_skb(skb); 838 priv->rx_1st_skb->protocol = 839 eth_type_trans(priv->rx_1st_skb, ndev); 840 napi_gro_receive(&priv->napi[q], 841 priv->rx_1st_skb); 842 stats->rx_packets++; 843 stats->rx_bytes += pkt_len; 844 break; 845 } 846 } 847 848 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 849 desc = &priv->gbeth_rx_ring[entry]; 850 } 851 852 /* Refill the RX ring buffers. */ 853 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 854 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 855 desc = &priv->gbeth_rx_ring[entry]; 856 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 857 858 if (!priv->rx_skb[q][entry]) { 859 skb = netdev_alloc_skb(ndev, info->max_rx_len); 860 if (!skb) 861 break; 862 ravb_set_buffer_align(skb); 863 dma_addr = dma_map_single(ndev->dev.parent, 864 skb->data, 865 GBETH_RX_BUFF_MAX, 866 DMA_FROM_DEVICE); 867 skb_checksum_none_assert(skb); 868 /* We just set the data size to 0 for a failed mapping 869 * which should prevent DMA from happening... 870 */ 871 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 872 desc->ds_cc = cpu_to_le16(0); 873 desc->dptr = cpu_to_le32(dma_addr); 874 priv->rx_skb[q][entry] = skb; 875 } 876 /* Descriptor type must be set after all the above writes */ 877 dma_wmb(); 878 desc->die_dt = DT_FEMPTY; 879 } 880 881 *quota -= limit - (++boguscnt); 882 883 return boguscnt <= 0; 884 } 885 886 /* Packet receive function for Ethernet AVB */ 887 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 888 { 889 struct ravb_private *priv = netdev_priv(ndev); 890 const struct ravb_hw_info *info = priv->info; 891 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 892 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 893 priv->cur_rx[q]; 894 struct net_device_stats *stats = &priv->stats[q]; 895 struct ravb_ex_rx_desc *desc; 896 struct sk_buff *skb; 897 dma_addr_t dma_addr; 898 struct timespec64 ts; 899 u8 desc_status; 900 u16 pkt_len; 901 int limit; 902 903 boguscnt = min(boguscnt, *quota); 904 limit = boguscnt; 905 desc = &priv->rx_ring[q][entry]; 906 while (desc->die_dt != DT_FEMPTY) { 907 /* Descriptor type must be checked before all other reads */ 908 dma_rmb(); 909 desc_status = desc->msc; 910 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 911 912 if (--boguscnt < 0) 913 break; 914 915 /* We use 0-byte descriptors to mark the DMA mapping errors */ 916 if (!pkt_len) 917 continue; 918 919 if (desc_status & MSC_MC) 920 stats->multicast++; 921 922 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 923 MSC_CEEF)) { 924 stats->rx_errors++; 925 if (desc_status & MSC_CRC) 926 stats->rx_crc_errors++; 927 if (desc_status & MSC_RFE) 928 stats->rx_frame_errors++; 929 if (desc_status & (MSC_RTLF | MSC_RTSF)) 930 stats->rx_length_errors++; 931 if (desc_status & MSC_CEEF) 932 stats->rx_missed_errors++; 933 } else { 934 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 935 936 skb = priv->rx_skb[q][entry]; 937 priv->rx_skb[q][entry] = NULL; 938 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 939 RX_BUF_SZ, 940 DMA_FROM_DEVICE); 941 get_ts &= (q == RAVB_NC) ? 942 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 943 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 944 if (get_ts) { 945 struct skb_shared_hwtstamps *shhwtstamps; 946 947 shhwtstamps = skb_hwtstamps(skb); 948 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 949 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 950 32) | le32_to_cpu(desc->ts_sl); 951 ts.tv_nsec = le32_to_cpu(desc->ts_n); 952 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 953 } 954 955 skb_put(skb, pkt_len); 956 skb->protocol = eth_type_trans(skb, ndev); 957 if (ndev->features & NETIF_F_RXCSUM) 958 ravb_rx_csum(skb); 959 napi_gro_receive(&priv->napi[q], skb); 960 stats->rx_packets++; 961 stats->rx_bytes += pkt_len; 962 } 963 964 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 965 desc = &priv->rx_ring[q][entry]; 966 } 967 968 /* Refill the RX ring buffers. */ 969 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 970 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 971 desc = &priv->rx_ring[q][entry]; 972 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 973 974 if (!priv->rx_skb[q][entry]) { 975 skb = netdev_alloc_skb(ndev, info->max_rx_len); 976 if (!skb) 977 break; /* Better luck next round. */ 978 ravb_set_buffer_align(skb); 979 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 980 le16_to_cpu(desc->ds_cc), 981 DMA_FROM_DEVICE); 982 skb_checksum_none_assert(skb); 983 /* We just set the data size to 0 for a failed mapping 984 * which should prevent DMA from happening... 985 */ 986 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 987 desc->ds_cc = cpu_to_le16(0); 988 desc->dptr = cpu_to_le32(dma_addr); 989 priv->rx_skb[q][entry] = skb; 990 } 991 /* Descriptor type must be set after all the above writes */ 992 dma_wmb(); 993 desc->die_dt = DT_FEMPTY; 994 } 995 996 *quota -= limit - (++boguscnt); 997 998 return boguscnt <= 0; 999 } 1000 1001 /* Packet receive function for Ethernet AVB */ 1002 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 1003 { 1004 struct ravb_private *priv = netdev_priv(ndev); 1005 const struct ravb_hw_info *info = priv->info; 1006 1007 return info->receive(ndev, quota, q); 1008 } 1009 1010 static void ravb_rcv_snd_disable(struct net_device *ndev) 1011 { 1012 /* Disable TX and RX */ 1013 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1014 } 1015 1016 static void ravb_rcv_snd_enable(struct net_device *ndev) 1017 { 1018 /* Enable TX and RX */ 1019 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1020 } 1021 1022 /* function for waiting dma process finished */ 1023 static int ravb_stop_dma(struct net_device *ndev) 1024 { 1025 struct ravb_private *priv = netdev_priv(ndev); 1026 const struct ravb_hw_info *info = priv->info; 1027 int error; 1028 1029 /* Wait for stopping the hardware TX process */ 1030 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1031 1032 if (error) 1033 return error; 1034 1035 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1036 0); 1037 if (error) 1038 return error; 1039 1040 /* Stop the E-MAC's RX/TX processes. */ 1041 ravb_rcv_snd_disable(ndev); 1042 1043 /* Wait for stopping the RX DMA process */ 1044 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1045 if (error) 1046 return error; 1047 1048 /* Stop AVB-DMAC process */ 1049 return ravb_config(ndev); 1050 } 1051 1052 /* E-MAC interrupt handler */ 1053 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1054 { 1055 struct ravb_private *priv = netdev_priv(ndev); 1056 u32 ecsr, psr; 1057 1058 ecsr = ravb_read(ndev, ECSR); 1059 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1060 1061 if (ecsr & ECSR_MPD) 1062 pm_wakeup_event(&priv->pdev->dev, 0); 1063 if (ecsr & ECSR_ICD) 1064 ndev->stats.tx_carrier_errors++; 1065 if (ecsr & ECSR_LCHNG) { 1066 /* Link changed */ 1067 if (priv->no_avb_link) 1068 return; 1069 psr = ravb_read(ndev, PSR); 1070 if (priv->avb_link_active_low) 1071 psr ^= PSR_LMON; 1072 if (!(psr & PSR_LMON)) { 1073 /* DIsable RX and TX */ 1074 ravb_rcv_snd_disable(ndev); 1075 } else { 1076 /* Enable RX and TX */ 1077 ravb_rcv_snd_enable(ndev); 1078 } 1079 } 1080 } 1081 1082 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1083 { 1084 struct net_device *ndev = dev_id; 1085 struct ravb_private *priv = netdev_priv(ndev); 1086 1087 spin_lock(&priv->lock); 1088 ravb_emac_interrupt_unlocked(ndev); 1089 spin_unlock(&priv->lock); 1090 return IRQ_HANDLED; 1091 } 1092 1093 /* Error interrupt handler */ 1094 static void ravb_error_interrupt(struct net_device *ndev) 1095 { 1096 struct ravb_private *priv = netdev_priv(ndev); 1097 u32 eis, ris2; 1098 1099 eis = ravb_read(ndev, EIS); 1100 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1101 if (eis & EIS_QFS) { 1102 ris2 = ravb_read(ndev, RIS2); 1103 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1104 RIS2); 1105 1106 /* Receive Descriptor Empty int */ 1107 if (ris2 & RIS2_QFF0) 1108 priv->stats[RAVB_BE].rx_over_errors++; 1109 1110 /* Receive Descriptor Empty int */ 1111 if (ris2 & RIS2_QFF1) 1112 priv->stats[RAVB_NC].rx_over_errors++; 1113 1114 /* Receive FIFO Overflow int */ 1115 if (ris2 & RIS2_RFFF) 1116 priv->rx_fifo_errors++; 1117 } 1118 } 1119 1120 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1121 { 1122 struct ravb_private *priv = netdev_priv(ndev); 1123 const struct ravb_hw_info *info = priv->info; 1124 u32 ris0 = ravb_read(ndev, RIS0); 1125 u32 ric0 = ravb_read(ndev, RIC0); 1126 u32 tis = ravb_read(ndev, TIS); 1127 u32 tic = ravb_read(ndev, TIC); 1128 1129 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1130 if (napi_schedule_prep(&priv->napi[q])) { 1131 /* Mask RX and TX interrupts */ 1132 if (!info->irq_en_dis) { 1133 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1134 ravb_write(ndev, tic & ~BIT(q), TIC); 1135 } else { 1136 ravb_write(ndev, BIT(q), RID0); 1137 ravb_write(ndev, BIT(q), TID); 1138 } 1139 __napi_schedule(&priv->napi[q]); 1140 } else { 1141 netdev_warn(ndev, 1142 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1143 ris0, ric0); 1144 netdev_warn(ndev, 1145 " tx status 0x%08x, tx mask 0x%08x.\n", 1146 tis, tic); 1147 } 1148 return true; 1149 } 1150 return false; 1151 } 1152 1153 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1154 { 1155 u32 tis = ravb_read(ndev, TIS); 1156 1157 if (tis & TIS_TFUF) { 1158 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1159 ravb_get_tx_tstamp(ndev); 1160 return true; 1161 } 1162 return false; 1163 } 1164 1165 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1166 { 1167 struct net_device *ndev = dev_id; 1168 struct ravb_private *priv = netdev_priv(ndev); 1169 const struct ravb_hw_info *info = priv->info; 1170 irqreturn_t result = IRQ_NONE; 1171 u32 iss; 1172 1173 spin_lock(&priv->lock); 1174 /* Get interrupt status */ 1175 iss = ravb_read(ndev, ISS); 1176 1177 /* Received and transmitted interrupts */ 1178 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1179 int q; 1180 1181 /* Timestamp updated */ 1182 if (ravb_timestamp_interrupt(ndev)) 1183 result = IRQ_HANDLED; 1184 1185 /* Network control and best effort queue RX/TX */ 1186 if (info->nc_queues) { 1187 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1188 if (ravb_queue_interrupt(ndev, q)) 1189 result = IRQ_HANDLED; 1190 } 1191 } else { 1192 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1193 result = IRQ_HANDLED; 1194 } 1195 } 1196 1197 /* E-MAC status summary */ 1198 if (iss & ISS_MS) { 1199 ravb_emac_interrupt_unlocked(ndev); 1200 result = IRQ_HANDLED; 1201 } 1202 1203 /* Error status summary */ 1204 if (iss & ISS_ES) { 1205 ravb_error_interrupt(ndev); 1206 result = IRQ_HANDLED; 1207 } 1208 1209 /* gPTP interrupt status summary */ 1210 if (iss & ISS_CGIS) { 1211 ravb_ptp_interrupt(ndev); 1212 result = IRQ_HANDLED; 1213 } 1214 1215 spin_unlock(&priv->lock); 1216 return result; 1217 } 1218 1219 /* Timestamp/Error/gPTP interrupt handler */ 1220 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1221 { 1222 struct net_device *ndev = dev_id; 1223 struct ravb_private *priv = netdev_priv(ndev); 1224 irqreturn_t result = IRQ_NONE; 1225 u32 iss; 1226 1227 spin_lock(&priv->lock); 1228 /* Get interrupt status */ 1229 iss = ravb_read(ndev, ISS); 1230 1231 /* Timestamp updated */ 1232 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1233 result = IRQ_HANDLED; 1234 1235 /* Error status summary */ 1236 if (iss & ISS_ES) { 1237 ravb_error_interrupt(ndev); 1238 result = IRQ_HANDLED; 1239 } 1240 1241 /* gPTP interrupt status summary */ 1242 if (iss & ISS_CGIS) { 1243 ravb_ptp_interrupt(ndev); 1244 result = IRQ_HANDLED; 1245 } 1246 1247 spin_unlock(&priv->lock); 1248 return result; 1249 } 1250 1251 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1252 { 1253 struct net_device *ndev = dev_id; 1254 struct ravb_private *priv = netdev_priv(ndev); 1255 irqreturn_t result = IRQ_NONE; 1256 1257 spin_lock(&priv->lock); 1258 1259 /* Network control/Best effort queue RX/TX */ 1260 if (ravb_queue_interrupt(ndev, q)) 1261 result = IRQ_HANDLED; 1262 1263 spin_unlock(&priv->lock); 1264 return result; 1265 } 1266 1267 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1268 { 1269 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1270 } 1271 1272 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1273 { 1274 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1275 } 1276 1277 static int ravb_poll(struct napi_struct *napi, int budget) 1278 { 1279 struct net_device *ndev = napi->dev; 1280 struct ravb_private *priv = netdev_priv(ndev); 1281 const struct ravb_hw_info *info = priv->info; 1282 bool gptp = info->gptp || info->ccc_gac; 1283 struct ravb_rx_desc *desc; 1284 unsigned long flags; 1285 int q = napi - priv->napi; 1286 int mask = BIT(q); 1287 int quota = budget; 1288 unsigned int entry; 1289 1290 if (!gptp) { 1291 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 1292 desc = &priv->gbeth_rx_ring[entry]; 1293 } 1294 /* Processing RX Descriptor Ring */ 1295 /* Clear RX interrupt */ 1296 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1297 if (gptp || desc->die_dt != DT_FEMPTY) { 1298 if (ravb_rx(ndev, "a, q)) 1299 goto out; 1300 } 1301 1302 /* Processing TX Descriptor Ring */ 1303 spin_lock_irqsave(&priv->lock, flags); 1304 /* Clear TX interrupt */ 1305 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1306 ravb_tx_free(ndev, q, true); 1307 netif_wake_subqueue(ndev, q); 1308 spin_unlock_irqrestore(&priv->lock, flags); 1309 1310 napi_complete(napi); 1311 1312 /* Re-enable RX/TX interrupts */ 1313 spin_lock_irqsave(&priv->lock, flags); 1314 if (!info->irq_en_dis) { 1315 ravb_modify(ndev, RIC0, mask, mask); 1316 ravb_modify(ndev, TIC, mask, mask); 1317 } else { 1318 ravb_write(ndev, mask, RIE0); 1319 ravb_write(ndev, mask, TIE); 1320 } 1321 spin_unlock_irqrestore(&priv->lock, flags); 1322 1323 /* Receive error message handling */ 1324 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1325 if (info->nc_queues) 1326 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1327 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1328 ndev->stats.rx_over_errors = priv->rx_over_errors; 1329 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1330 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1331 out: 1332 return budget - quota; 1333 } 1334 1335 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1336 { 1337 struct ravb_private *priv = netdev_priv(ndev); 1338 1339 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1340 } 1341 1342 /* PHY state control function */ 1343 static void ravb_adjust_link(struct net_device *ndev) 1344 { 1345 struct ravb_private *priv = netdev_priv(ndev); 1346 const struct ravb_hw_info *info = priv->info; 1347 struct phy_device *phydev = ndev->phydev; 1348 bool new_state = false; 1349 unsigned long flags; 1350 1351 spin_lock_irqsave(&priv->lock, flags); 1352 1353 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1354 if (priv->no_avb_link) 1355 ravb_rcv_snd_disable(ndev); 1356 1357 if (phydev->link) { 1358 if (info->half_duplex && phydev->duplex != priv->duplex) { 1359 new_state = true; 1360 priv->duplex = phydev->duplex; 1361 ravb_set_duplex_gbeth(ndev); 1362 } 1363 1364 if (phydev->speed != priv->speed) { 1365 new_state = true; 1366 priv->speed = phydev->speed; 1367 info->set_rate(ndev); 1368 } 1369 if (!priv->link) { 1370 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1371 new_state = true; 1372 priv->link = phydev->link; 1373 } 1374 } else if (priv->link) { 1375 new_state = true; 1376 priv->link = 0; 1377 priv->speed = 0; 1378 if (info->half_duplex) 1379 priv->duplex = -1; 1380 } 1381 1382 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1383 if (priv->no_avb_link && phydev->link) 1384 ravb_rcv_snd_enable(ndev); 1385 1386 spin_unlock_irqrestore(&priv->lock, flags); 1387 1388 if (new_state && netif_msg_link(priv)) 1389 phy_print_status(phydev); 1390 } 1391 1392 /* PHY init function */ 1393 static int ravb_phy_init(struct net_device *ndev) 1394 { 1395 struct device_node *np = ndev->dev.parent->of_node; 1396 struct ravb_private *priv = netdev_priv(ndev); 1397 const struct ravb_hw_info *info = priv->info; 1398 struct phy_device *phydev; 1399 struct device_node *pn; 1400 phy_interface_t iface; 1401 int err; 1402 1403 priv->link = 0; 1404 priv->speed = 0; 1405 priv->duplex = -1; 1406 1407 /* Try connecting to PHY */ 1408 pn = of_parse_phandle(np, "phy-handle", 0); 1409 if (!pn) { 1410 /* In the case of a fixed PHY, the DT node associated 1411 * to the PHY is the Ethernet MAC DT node. 1412 */ 1413 if (of_phy_is_fixed_link(np)) { 1414 err = of_phy_register_fixed_link(np); 1415 if (err) 1416 return err; 1417 } 1418 pn = of_node_get(np); 1419 } 1420 1421 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1422 : priv->phy_interface; 1423 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1424 of_node_put(pn); 1425 if (!phydev) { 1426 netdev_err(ndev, "failed to connect PHY\n"); 1427 err = -ENOENT; 1428 goto err_deregister_fixed_link; 1429 } 1430 1431 if (!info->half_duplex) { 1432 /* 10BASE, Pause and Asym Pause is not supported */ 1433 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1434 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1435 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1436 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1437 1438 /* Half Duplex is not supported */ 1439 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1440 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1441 } 1442 1443 /* Indicate that the MAC is responsible for managing PHY PM */ 1444 phydev->mac_managed_pm = true; 1445 phy_attached_info(phydev); 1446 1447 return 0; 1448 1449 err_deregister_fixed_link: 1450 if (of_phy_is_fixed_link(np)) 1451 of_phy_deregister_fixed_link(np); 1452 1453 return err; 1454 } 1455 1456 /* PHY control start function */ 1457 static int ravb_phy_start(struct net_device *ndev) 1458 { 1459 int error; 1460 1461 error = ravb_phy_init(ndev); 1462 if (error) 1463 return error; 1464 1465 phy_start(ndev->phydev); 1466 1467 return 0; 1468 } 1469 1470 static u32 ravb_get_msglevel(struct net_device *ndev) 1471 { 1472 struct ravb_private *priv = netdev_priv(ndev); 1473 1474 return priv->msg_enable; 1475 } 1476 1477 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1478 { 1479 struct ravb_private *priv = netdev_priv(ndev); 1480 1481 priv->msg_enable = value; 1482 } 1483 1484 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1485 "rx_queue_0_current", 1486 "tx_queue_0_current", 1487 "rx_queue_0_dirty", 1488 "tx_queue_0_dirty", 1489 "rx_queue_0_packets", 1490 "tx_queue_0_packets", 1491 "rx_queue_0_bytes", 1492 "tx_queue_0_bytes", 1493 "rx_queue_0_mcast_packets", 1494 "rx_queue_0_errors", 1495 "rx_queue_0_crc_errors", 1496 "rx_queue_0_frame_errors", 1497 "rx_queue_0_length_errors", 1498 "rx_queue_0_csum_offload_errors", 1499 "rx_queue_0_over_errors", 1500 }; 1501 1502 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1503 "rx_queue_0_current", 1504 "tx_queue_0_current", 1505 "rx_queue_0_dirty", 1506 "tx_queue_0_dirty", 1507 "rx_queue_0_packets", 1508 "tx_queue_0_packets", 1509 "rx_queue_0_bytes", 1510 "tx_queue_0_bytes", 1511 "rx_queue_0_mcast_packets", 1512 "rx_queue_0_errors", 1513 "rx_queue_0_crc_errors", 1514 "rx_queue_0_frame_errors", 1515 "rx_queue_0_length_errors", 1516 "rx_queue_0_missed_errors", 1517 "rx_queue_0_over_errors", 1518 1519 "rx_queue_1_current", 1520 "tx_queue_1_current", 1521 "rx_queue_1_dirty", 1522 "tx_queue_1_dirty", 1523 "rx_queue_1_packets", 1524 "tx_queue_1_packets", 1525 "rx_queue_1_bytes", 1526 "tx_queue_1_bytes", 1527 "rx_queue_1_mcast_packets", 1528 "rx_queue_1_errors", 1529 "rx_queue_1_crc_errors", 1530 "rx_queue_1_frame_errors", 1531 "rx_queue_1_length_errors", 1532 "rx_queue_1_missed_errors", 1533 "rx_queue_1_over_errors", 1534 }; 1535 1536 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1537 { 1538 struct ravb_private *priv = netdev_priv(netdev); 1539 const struct ravb_hw_info *info = priv->info; 1540 1541 switch (sset) { 1542 case ETH_SS_STATS: 1543 return info->stats_len; 1544 default: 1545 return -EOPNOTSUPP; 1546 } 1547 } 1548 1549 static void ravb_get_ethtool_stats(struct net_device *ndev, 1550 struct ethtool_stats *estats, u64 *data) 1551 { 1552 struct ravb_private *priv = netdev_priv(ndev); 1553 const struct ravb_hw_info *info = priv->info; 1554 int num_rx_q; 1555 int i = 0; 1556 int q; 1557 1558 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1559 /* Device-specific stats */ 1560 for (q = RAVB_BE; q < num_rx_q; q++) { 1561 struct net_device_stats *stats = &priv->stats[q]; 1562 1563 data[i++] = priv->cur_rx[q]; 1564 data[i++] = priv->cur_tx[q]; 1565 data[i++] = priv->dirty_rx[q]; 1566 data[i++] = priv->dirty_tx[q]; 1567 data[i++] = stats->rx_packets; 1568 data[i++] = stats->tx_packets; 1569 data[i++] = stats->rx_bytes; 1570 data[i++] = stats->tx_bytes; 1571 data[i++] = stats->multicast; 1572 data[i++] = stats->rx_errors; 1573 data[i++] = stats->rx_crc_errors; 1574 data[i++] = stats->rx_frame_errors; 1575 data[i++] = stats->rx_length_errors; 1576 data[i++] = stats->rx_missed_errors; 1577 data[i++] = stats->rx_over_errors; 1578 } 1579 } 1580 1581 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1582 { 1583 struct ravb_private *priv = netdev_priv(ndev); 1584 const struct ravb_hw_info *info = priv->info; 1585 1586 switch (stringset) { 1587 case ETH_SS_STATS: 1588 memcpy(data, info->gstrings_stats, info->gstrings_size); 1589 break; 1590 } 1591 } 1592 1593 static void ravb_get_ringparam(struct net_device *ndev, 1594 struct ethtool_ringparam *ring, 1595 struct kernel_ethtool_ringparam *kernel_ring, 1596 struct netlink_ext_ack *extack) 1597 { 1598 struct ravb_private *priv = netdev_priv(ndev); 1599 1600 ring->rx_max_pending = BE_RX_RING_MAX; 1601 ring->tx_max_pending = BE_TX_RING_MAX; 1602 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1603 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1604 } 1605 1606 static int ravb_set_ringparam(struct net_device *ndev, 1607 struct ethtool_ringparam *ring, 1608 struct kernel_ethtool_ringparam *kernel_ring, 1609 struct netlink_ext_ack *extack) 1610 { 1611 struct ravb_private *priv = netdev_priv(ndev); 1612 const struct ravb_hw_info *info = priv->info; 1613 int error; 1614 1615 if (ring->tx_pending > BE_TX_RING_MAX || 1616 ring->rx_pending > BE_RX_RING_MAX || 1617 ring->tx_pending < BE_TX_RING_MIN || 1618 ring->rx_pending < BE_RX_RING_MIN) 1619 return -EINVAL; 1620 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1621 return -EINVAL; 1622 1623 if (netif_running(ndev)) { 1624 netif_device_detach(ndev); 1625 /* Stop PTP Clock driver */ 1626 if (info->gptp) 1627 ravb_ptp_stop(ndev); 1628 /* Wait for DMA stopping */ 1629 error = ravb_stop_dma(ndev); 1630 if (error) { 1631 netdev_err(ndev, 1632 "cannot set ringparam! Any AVB processes are still running?\n"); 1633 return error; 1634 } 1635 synchronize_irq(ndev->irq); 1636 1637 /* Free all the skb's in the RX queue and the DMA buffers. */ 1638 ravb_ring_free(ndev, RAVB_BE); 1639 if (info->nc_queues) 1640 ravb_ring_free(ndev, RAVB_NC); 1641 } 1642 1643 /* Set new parameters */ 1644 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1645 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1646 1647 if (netif_running(ndev)) { 1648 error = ravb_dmac_init(ndev); 1649 if (error) { 1650 netdev_err(ndev, 1651 "%s: ravb_dmac_init() failed, error %d\n", 1652 __func__, error); 1653 return error; 1654 } 1655 1656 ravb_emac_init(ndev); 1657 1658 /* Initialise PTP Clock driver */ 1659 if (info->gptp) 1660 ravb_ptp_init(ndev, priv->pdev); 1661 1662 netif_device_attach(ndev); 1663 } 1664 1665 return 0; 1666 } 1667 1668 static int ravb_get_ts_info(struct net_device *ndev, 1669 struct ethtool_ts_info *info) 1670 { 1671 struct ravb_private *priv = netdev_priv(ndev); 1672 const struct ravb_hw_info *hw_info = priv->info; 1673 1674 info->so_timestamping = 1675 SOF_TIMESTAMPING_TX_SOFTWARE | 1676 SOF_TIMESTAMPING_RX_SOFTWARE | 1677 SOF_TIMESTAMPING_SOFTWARE | 1678 SOF_TIMESTAMPING_TX_HARDWARE | 1679 SOF_TIMESTAMPING_RX_HARDWARE | 1680 SOF_TIMESTAMPING_RAW_HARDWARE; 1681 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1682 info->rx_filters = 1683 (1 << HWTSTAMP_FILTER_NONE) | 1684 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1685 (1 << HWTSTAMP_FILTER_ALL); 1686 if (hw_info->gptp || hw_info->ccc_gac) 1687 info->phc_index = ptp_clock_index(priv->ptp.clock); 1688 1689 return 0; 1690 } 1691 1692 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1693 { 1694 struct ravb_private *priv = netdev_priv(ndev); 1695 1696 wol->supported = WAKE_MAGIC; 1697 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1698 } 1699 1700 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1701 { 1702 struct ravb_private *priv = netdev_priv(ndev); 1703 const struct ravb_hw_info *info = priv->info; 1704 1705 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1706 return -EOPNOTSUPP; 1707 1708 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1709 1710 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1711 1712 return 0; 1713 } 1714 1715 static const struct ethtool_ops ravb_ethtool_ops = { 1716 .nway_reset = phy_ethtool_nway_reset, 1717 .get_msglevel = ravb_get_msglevel, 1718 .set_msglevel = ravb_set_msglevel, 1719 .get_link = ethtool_op_get_link, 1720 .get_strings = ravb_get_strings, 1721 .get_ethtool_stats = ravb_get_ethtool_stats, 1722 .get_sset_count = ravb_get_sset_count, 1723 .get_ringparam = ravb_get_ringparam, 1724 .set_ringparam = ravb_set_ringparam, 1725 .get_ts_info = ravb_get_ts_info, 1726 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1727 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1728 .get_wol = ravb_get_wol, 1729 .set_wol = ravb_set_wol, 1730 }; 1731 1732 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1733 struct net_device *ndev, struct device *dev, 1734 const char *ch) 1735 { 1736 char *name; 1737 int error; 1738 1739 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1740 if (!name) 1741 return -ENOMEM; 1742 error = request_irq(irq, handler, 0, name, ndev); 1743 if (error) 1744 netdev_err(ndev, "cannot request IRQ %s\n", name); 1745 1746 return error; 1747 } 1748 1749 /* Network device open function for Ethernet AVB */ 1750 static int ravb_open(struct net_device *ndev) 1751 { 1752 struct ravb_private *priv = netdev_priv(ndev); 1753 const struct ravb_hw_info *info = priv->info; 1754 struct platform_device *pdev = priv->pdev; 1755 struct device *dev = &pdev->dev; 1756 int error; 1757 1758 napi_enable(&priv->napi[RAVB_BE]); 1759 if (info->nc_queues) 1760 napi_enable(&priv->napi[RAVB_NC]); 1761 1762 if (!info->multi_irqs) { 1763 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1764 ndev->name, ndev); 1765 if (error) { 1766 netdev_err(ndev, "cannot request IRQ\n"); 1767 goto out_napi_off; 1768 } 1769 } else { 1770 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1771 dev, "ch22:multi"); 1772 if (error) 1773 goto out_napi_off; 1774 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1775 dev, "ch24:emac"); 1776 if (error) 1777 goto out_free_irq; 1778 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1779 ndev, dev, "ch0:rx_be"); 1780 if (error) 1781 goto out_free_irq_emac; 1782 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1783 ndev, dev, "ch18:tx_be"); 1784 if (error) 1785 goto out_free_irq_be_rx; 1786 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1787 ndev, dev, "ch1:rx_nc"); 1788 if (error) 1789 goto out_free_irq_be_tx; 1790 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1791 ndev, dev, "ch19:tx_nc"); 1792 if (error) 1793 goto out_free_irq_nc_rx; 1794 1795 if (info->err_mgmt_irqs) { 1796 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt, 1797 ndev, dev, "err_a"); 1798 if (error) 1799 goto out_free_irq_nc_tx; 1800 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt, 1801 ndev, dev, "mgmt_a"); 1802 if (error) 1803 goto out_free_irq_erra; 1804 } 1805 } 1806 1807 /* Device init */ 1808 error = ravb_dmac_init(ndev); 1809 if (error) 1810 goto out_free_irq_mgmta; 1811 ravb_emac_init(ndev); 1812 1813 /* Initialise PTP Clock driver */ 1814 if (info->gptp) 1815 ravb_ptp_init(ndev, priv->pdev); 1816 1817 netif_tx_start_all_queues(ndev); 1818 1819 /* PHY control start */ 1820 error = ravb_phy_start(ndev); 1821 if (error) 1822 goto out_ptp_stop; 1823 1824 return 0; 1825 1826 out_ptp_stop: 1827 /* Stop PTP Clock driver */ 1828 if (info->gptp) 1829 ravb_ptp_stop(ndev); 1830 out_free_irq_mgmta: 1831 if (!info->multi_irqs) 1832 goto out_free_irq; 1833 if (info->err_mgmt_irqs) 1834 free_irq(priv->mgmta_irq, ndev); 1835 out_free_irq_erra: 1836 if (info->err_mgmt_irqs) 1837 free_irq(priv->erra_irq, ndev); 1838 out_free_irq_nc_tx: 1839 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1840 out_free_irq_nc_rx: 1841 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1842 out_free_irq_be_tx: 1843 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1844 out_free_irq_be_rx: 1845 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1846 out_free_irq_emac: 1847 free_irq(priv->emac_irq, ndev); 1848 out_free_irq: 1849 free_irq(ndev->irq, ndev); 1850 out_napi_off: 1851 if (info->nc_queues) 1852 napi_disable(&priv->napi[RAVB_NC]); 1853 napi_disable(&priv->napi[RAVB_BE]); 1854 return error; 1855 } 1856 1857 /* Timeout function for Ethernet AVB */ 1858 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1859 { 1860 struct ravb_private *priv = netdev_priv(ndev); 1861 1862 netif_err(priv, tx_err, ndev, 1863 "transmit timed out, status %08x, resetting...\n", 1864 ravb_read(ndev, ISS)); 1865 1866 /* tx_errors count up */ 1867 ndev->stats.tx_errors++; 1868 1869 schedule_work(&priv->work); 1870 } 1871 1872 static void ravb_tx_timeout_work(struct work_struct *work) 1873 { 1874 struct ravb_private *priv = container_of(work, struct ravb_private, 1875 work); 1876 const struct ravb_hw_info *info = priv->info; 1877 struct net_device *ndev = priv->ndev; 1878 int error; 1879 1880 netif_tx_stop_all_queues(ndev); 1881 1882 /* Stop PTP Clock driver */ 1883 if (info->gptp) 1884 ravb_ptp_stop(ndev); 1885 1886 /* Wait for DMA stopping */ 1887 if (ravb_stop_dma(ndev)) { 1888 /* If ravb_stop_dma() fails, the hardware is still operating 1889 * for TX and/or RX. So, this should not call the following 1890 * functions because ravb_dmac_init() is possible to fail too. 1891 * Also, this should not retry ravb_stop_dma() again and again 1892 * here because it's possible to wait forever. So, this just 1893 * re-enables the TX and RX and skip the following 1894 * re-initialization procedure. 1895 */ 1896 ravb_rcv_snd_enable(ndev); 1897 goto out; 1898 } 1899 1900 ravb_ring_free(ndev, RAVB_BE); 1901 if (info->nc_queues) 1902 ravb_ring_free(ndev, RAVB_NC); 1903 1904 /* Device init */ 1905 error = ravb_dmac_init(ndev); 1906 if (error) { 1907 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1908 * should return here to avoid re-enabling the TX and RX in 1909 * ravb_emac_init(). 1910 */ 1911 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1912 __func__, error); 1913 return; 1914 } 1915 ravb_emac_init(ndev); 1916 1917 out: 1918 /* Initialise PTP Clock driver */ 1919 if (info->gptp) 1920 ravb_ptp_init(ndev, priv->pdev); 1921 1922 netif_tx_start_all_queues(ndev); 1923 } 1924 1925 /* Packet transmit function for Ethernet AVB */ 1926 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1927 { 1928 struct ravb_private *priv = netdev_priv(ndev); 1929 const struct ravb_hw_info *info = priv->info; 1930 unsigned int num_tx_desc = priv->num_tx_desc; 1931 u16 q = skb_get_queue_mapping(skb); 1932 struct ravb_tstamp_skb *ts_skb; 1933 struct ravb_tx_desc *desc; 1934 unsigned long flags; 1935 u32 dma_addr; 1936 void *buffer; 1937 u32 entry; 1938 u32 len; 1939 1940 spin_lock_irqsave(&priv->lock, flags); 1941 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1942 num_tx_desc) { 1943 netif_err(priv, tx_queued, ndev, 1944 "still transmitting with the full ring!\n"); 1945 netif_stop_subqueue(ndev, q); 1946 spin_unlock_irqrestore(&priv->lock, flags); 1947 return NETDEV_TX_BUSY; 1948 } 1949 1950 if (skb_put_padto(skb, ETH_ZLEN)) 1951 goto exit; 1952 1953 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1954 priv->tx_skb[q][entry / num_tx_desc] = skb; 1955 1956 if (num_tx_desc > 1) { 1957 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1958 entry / num_tx_desc * DPTR_ALIGN; 1959 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1960 1961 /* Zero length DMA descriptors are problematic as they seem 1962 * to terminate DMA transfers. Avoid them by simply using a 1963 * length of DPTR_ALIGN (4) when skb data is aligned to 1964 * DPTR_ALIGN. 1965 * 1966 * As skb is guaranteed to have at least ETH_ZLEN (60) 1967 * bytes of data by the call to skb_put_padto() above this 1968 * is safe with respect to both the length of the first DMA 1969 * descriptor (len) overflowing the available data and the 1970 * length of the second DMA descriptor (skb->len - len) 1971 * being negative. 1972 */ 1973 if (len == 0) 1974 len = DPTR_ALIGN; 1975 1976 memcpy(buffer, skb->data, len); 1977 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1978 DMA_TO_DEVICE); 1979 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1980 goto drop; 1981 1982 desc = &priv->tx_ring[q][entry]; 1983 desc->ds_tagl = cpu_to_le16(len); 1984 desc->dptr = cpu_to_le32(dma_addr); 1985 1986 buffer = skb->data + len; 1987 len = skb->len - len; 1988 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1989 DMA_TO_DEVICE); 1990 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1991 goto unmap; 1992 1993 desc++; 1994 } else { 1995 desc = &priv->tx_ring[q][entry]; 1996 len = skb->len; 1997 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1998 DMA_TO_DEVICE); 1999 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2000 goto drop; 2001 } 2002 desc->ds_tagl = cpu_to_le16(len); 2003 desc->dptr = cpu_to_le32(dma_addr); 2004 2005 /* TX timestamp required */ 2006 if (info->gptp || info->ccc_gac) { 2007 if (q == RAVB_NC) { 2008 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2009 if (!ts_skb) { 2010 if (num_tx_desc > 1) { 2011 desc--; 2012 dma_unmap_single(ndev->dev.parent, dma_addr, 2013 len, DMA_TO_DEVICE); 2014 } 2015 goto unmap; 2016 } 2017 ts_skb->skb = skb_get(skb); 2018 ts_skb->tag = priv->ts_skb_tag++; 2019 priv->ts_skb_tag &= 0x3ff; 2020 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2021 2022 /* TAG and timestamp required flag */ 2023 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2024 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2025 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2026 } 2027 2028 skb_tx_timestamp(skb); 2029 } 2030 /* Descriptor type must be set after all the above writes */ 2031 dma_wmb(); 2032 if (num_tx_desc > 1) { 2033 desc->die_dt = DT_FEND; 2034 desc--; 2035 desc->die_dt = DT_FSTART; 2036 } else { 2037 desc->die_dt = DT_FSINGLE; 2038 } 2039 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2040 2041 priv->cur_tx[q] += num_tx_desc; 2042 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2043 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2044 !ravb_tx_free(ndev, q, true)) 2045 netif_stop_subqueue(ndev, q); 2046 2047 exit: 2048 spin_unlock_irqrestore(&priv->lock, flags); 2049 return NETDEV_TX_OK; 2050 2051 unmap: 2052 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2053 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2054 drop: 2055 dev_kfree_skb_any(skb); 2056 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2057 goto exit; 2058 } 2059 2060 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2061 struct net_device *sb_dev) 2062 { 2063 /* If skb needs TX timestamp, it is handled in network control queue */ 2064 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2065 RAVB_BE; 2066 2067 } 2068 2069 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2070 { 2071 struct ravb_private *priv = netdev_priv(ndev); 2072 const struct ravb_hw_info *info = priv->info; 2073 struct net_device_stats *nstats, *stats0, *stats1; 2074 2075 nstats = &ndev->stats; 2076 stats0 = &priv->stats[RAVB_BE]; 2077 2078 if (info->tx_counters) { 2079 nstats->tx_dropped += ravb_read(ndev, TROCR); 2080 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2081 } 2082 2083 if (info->carrier_counters) { 2084 nstats->collisions += ravb_read(ndev, CXR41); 2085 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2086 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2087 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2088 } 2089 2090 nstats->rx_packets = stats0->rx_packets; 2091 nstats->tx_packets = stats0->tx_packets; 2092 nstats->rx_bytes = stats0->rx_bytes; 2093 nstats->tx_bytes = stats0->tx_bytes; 2094 nstats->multicast = stats0->multicast; 2095 nstats->rx_errors = stats0->rx_errors; 2096 nstats->rx_crc_errors = stats0->rx_crc_errors; 2097 nstats->rx_frame_errors = stats0->rx_frame_errors; 2098 nstats->rx_length_errors = stats0->rx_length_errors; 2099 nstats->rx_missed_errors = stats0->rx_missed_errors; 2100 nstats->rx_over_errors = stats0->rx_over_errors; 2101 if (info->nc_queues) { 2102 stats1 = &priv->stats[RAVB_NC]; 2103 2104 nstats->rx_packets += stats1->rx_packets; 2105 nstats->tx_packets += stats1->tx_packets; 2106 nstats->rx_bytes += stats1->rx_bytes; 2107 nstats->tx_bytes += stats1->tx_bytes; 2108 nstats->multicast += stats1->multicast; 2109 nstats->rx_errors += stats1->rx_errors; 2110 nstats->rx_crc_errors += stats1->rx_crc_errors; 2111 nstats->rx_frame_errors += stats1->rx_frame_errors; 2112 nstats->rx_length_errors += stats1->rx_length_errors; 2113 nstats->rx_missed_errors += stats1->rx_missed_errors; 2114 nstats->rx_over_errors += stats1->rx_over_errors; 2115 } 2116 2117 return nstats; 2118 } 2119 2120 /* Update promiscuous bit */ 2121 static void ravb_set_rx_mode(struct net_device *ndev) 2122 { 2123 struct ravb_private *priv = netdev_priv(ndev); 2124 unsigned long flags; 2125 2126 spin_lock_irqsave(&priv->lock, flags); 2127 ravb_modify(ndev, ECMR, ECMR_PRM, 2128 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2129 spin_unlock_irqrestore(&priv->lock, flags); 2130 } 2131 2132 /* Device close function for Ethernet AVB */ 2133 static int ravb_close(struct net_device *ndev) 2134 { 2135 struct device_node *np = ndev->dev.parent->of_node; 2136 struct ravb_private *priv = netdev_priv(ndev); 2137 const struct ravb_hw_info *info = priv->info; 2138 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2139 2140 netif_tx_stop_all_queues(ndev); 2141 2142 /* Disable interrupts by clearing the interrupt masks. */ 2143 ravb_write(ndev, 0, RIC0); 2144 ravb_write(ndev, 0, RIC2); 2145 ravb_write(ndev, 0, TIC); 2146 2147 /* Stop PTP Clock driver */ 2148 if (info->gptp) 2149 ravb_ptp_stop(ndev); 2150 2151 /* Set the config mode to stop the AVB-DMAC's processes */ 2152 if (ravb_stop_dma(ndev) < 0) 2153 netdev_err(ndev, 2154 "device will be stopped after h/w processes are done.\n"); 2155 2156 /* Clear the timestamp list */ 2157 if (info->gptp || info->ccc_gac) { 2158 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2159 list_del(&ts_skb->list); 2160 kfree_skb(ts_skb->skb); 2161 kfree(ts_skb); 2162 } 2163 } 2164 2165 /* PHY disconnect */ 2166 if (ndev->phydev) { 2167 phy_stop(ndev->phydev); 2168 phy_disconnect(ndev->phydev); 2169 if (of_phy_is_fixed_link(np)) 2170 of_phy_deregister_fixed_link(np); 2171 } 2172 2173 if (info->multi_irqs) { 2174 free_irq(priv->tx_irqs[RAVB_NC], ndev); 2175 free_irq(priv->rx_irqs[RAVB_NC], ndev); 2176 free_irq(priv->tx_irqs[RAVB_BE], ndev); 2177 free_irq(priv->rx_irqs[RAVB_BE], ndev); 2178 free_irq(priv->emac_irq, ndev); 2179 if (info->err_mgmt_irqs) { 2180 free_irq(priv->erra_irq, ndev); 2181 free_irq(priv->mgmta_irq, ndev); 2182 } 2183 } 2184 free_irq(ndev->irq, ndev); 2185 2186 if (info->nc_queues) 2187 napi_disable(&priv->napi[RAVB_NC]); 2188 napi_disable(&priv->napi[RAVB_BE]); 2189 2190 /* Free all the skb's in the RX queue and the DMA buffers. */ 2191 ravb_ring_free(ndev, RAVB_BE); 2192 if (info->nc_queues) 2193 ravb_ring_free(ndev, RAVB_NC); 2194 2195 return 0; 2196 } 2197 2198 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2199 { 2200 struct ravb_private *priv = netdev_priv(ndev); 2201 struct hwtstamp_config config; 2202 2203 config.flags = 0; 2204 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2205 HWTSTAMP_TX_OFF; 2206 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2207 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2208 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2209 break; 2210 case RAVB_RXTSTAMP_TYPE_ALL: 2211 config.rx_filter = HWTSTAMP_FILTER_ALL; 2212 break; 2213 default: 2214 config.rx_filter = HWTSTAMP_FILTER_NONE; 2215 } 2216 2217 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2218 -EFAULT : 0; 2219 } 2220 2221 /* Control hardware time stamping */ 2222 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2223 { 2224 struct ravb_private *priv = netdev_priv(ndev); 2225 struct hwtstamp_config config; 2226 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2227 u32 tstamp_tx_ctrl; 2228 2229 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2230 return -EFAULT; 2231 2232 switch (config.tx_type) { 2233 case HWTSTAMP_TX_OFF: 2234 tstamp_tx_ctrl = 0; 2235 break; 2236 case HWTSTAMP_TX_ON: 2237 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2238 break; 2239 default: 2240 return -ERANGE; 2241 } 2242 2243 switch (config.rx_filter) { 2244 case HWTSTAMP_FILTER_NONE: 2245 tstamp_rx_ctrl = 0; 2246 break; 2247 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2248 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2249 break; 2250 default: 2251 config.rx_filter = HWTSTAMP_FILTER_ALL; 2252 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2253 } 2254 2255 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2256 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2257 2258 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2259 -EFAULT : 0; 2260 } 2261 2262 /* ioctl to device function */ 2263 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2264 { 2265 struct phy_device *phydev = ndev->phydev; 2266 2267 if (!netif_running(ndev)) 2268 return -EINVAL; 2269 2270 if (!phydev) 2271 return -ENODEV; 2272 2273 switch (cmd) { 2274 case SIOCGHWTSTAMP: 2275 return ravb_hwtstamp_get(ndev, req); 2276 case SIOCSHWTSTAMP: 2277 return ravb_hwtstamp_set(ndev, req); 2278 } 2279 2280 return phy_mii_ioctl(phydev, req, cmd); 2281 } 2282 2283 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2284 { 2285 struct ravb_private *priv = netdev_priv(ndev); 2286 2287 ndev->mtu = new_mtu; 2288 2289 if (netif_running(ndev)) { 2290 synchronize_irq(priv->emac_irq); 2291 ravb_emac_init(ndev); 2292 } 2293 2294 netdev_update_features(ndev); 2295 2296 return 0; 2297 } 2298 2299 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2300 { 2301 struct ravb_private *priv = netdev_priv(ndev); 2302 unsigned long flags; 2303 2304 spin_lock_irqsave(&priv->lock, flags); 2305 2306 /* Disable TX and RX */ 2307 ravb_rcv_snd_disable(ndev); 2308 2309 /* Modify RX Checksum setting */ 2310 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2311 2312 /* Enable TX and RX */ 2313 ravb_rcv_snd_enable(ndev); 2314 2315 spin_unlock_irqrestore(&priv->lock, flags); 2316 } 2317 2318 static int ravb_set_features_gbeth(struct net_device *ndev, 2319 netdev_features_t features) 2320 { 2321 /* Place holder */ 2322 return 0; 2323 } 2324 2325 static int ravb_set_features_rcar(struct net_device *ndev, 2326 netdev_features_t features) 2327 { 2328 netdev_features_t changed = ndev->features ^ features; 2329 2330 if (changed & NETIF_F_RXCSUM) 2331 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2332 2333 ndev->features = features; 2334 2335 return 0; 2336 } 2337 2338 static int ravb_set_features(struct net_device *ndev, 2339 netdev_features_t features) 2340 { 2341 struct ravb_private *priv = netdev_priv(ndev); 2342 const struct ravb_hw_info *info = priv->info; 2343 2344 return info->set_feature(ndev, features); 2345 } 2346 2347 static const struct net_device_ops ravb_netdev_ops = { 2348 .ndo_open = ravb_open, 2349 .ndo_stop = ravb_close, 2350 .ndo_start_xmit = ravb_start_xmit, 2351 .ndo_select_queue = ravb_select_queue, 2352 .ndo_get_stats = ravb_get_stats, 2353 .ndo_set_rx_mode = ravb_set_rx_mode, 2354 .ndo_tx_timeout = ravb_tx_timeout, 2355 .ndo_eth_ioctl = ravb_do_ioctl, 2356 .ndo_change_mtu = ravb_change_mtu, 2357 .ndo_validate_addr = eth_validate_addr, 2358 .ndo_set_mac_address = eth_mac_addr, 2359 .ndo_set_features = ravb_set_features, 2360 }; 2361 2362 /* MDIO bus init function */ 2363 static int ravb_mdio_init(struct ravb_private *priv) 2364 { 2365 struct platform_device *pdev = priv->pdev; 2366 struct device *dev = &pdev->dev; 2367 int error; 2368 2369 /* Bitbang init */ 2370 priv->mdiobb.ops = &bb_ops; 2371 2372 /* MII controller setting */ 2373 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2374 if (!priv->mii_bus) 2375 return -ENOMEM; 2376 2377 /* Hook up MII support for ethtool */ 2378 priv->mii_bus->name = "ravb_mii"; 2379 priv->mii_bus->parent = dev; 2380 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2381 pdev->name, pdev->id); 2382 2383 /* Register MDIO bus */ 2384 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2385 if (error) 2386 goto out_free_bus; 2387 2388 return 0; 2389 2390 out_free_bus: 2391 free_mdio_bitbang(priv->mii_bus); 2392 return error; 2393 } 2394 2395 /* MDIO bus release function */ 2396 static int ravb_mdio_release(struct ravb_private *priv) 2397 { 2398 /* Unregister mdio bus */ 2399 mdiobus_unregister(priv->mii_bus); 2400 2401 /* Free bitbang info */ 2402 free_mdio_bitbang(priv->mii_bus); 2403 2404 return 0; 2405 } 2406 2407 static const struct ravb_hw_info ravb_gen3_hw_info = { 2408 .rx_ring_free = ravb_rx_ring_free_rcar, 2409 .rx_ring_format = ravb_rx_ring_format_rcar, 2410 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2411 .receive = ravb_rx_rcar, 2412 .set_rate = ravb_set_rate_rcar, 2413 .set_feature = ravb_set_features_rcar, 2414 .dmac_init = ravb_dmac_init_rcar, 2415 .emac_init = ravb_emac_init_rcar, 2416 .gstrings_stats = ravb_gstrings_stats, 2417 .gstrings_size = sizeof(ravb_gstrings_stats), 2418 .net_hw_features = NETIF_F_RXCSUM, 2419 .net_features = NETIF_F_RXCSUM, 2420 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2421 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2422 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2423 .rx_max_buf_size = SZ_2K, 2424 .internal_delay = 1, 2425 .tx_counters = 1, 2426 .multi_irqs = 1, 2427 .irq_en_dis = 1, 2428 .ccc_gac = 1, 2429 .nc_queues = 1, 2430 .magic_pkt = 1, 2431 }; 2432 2433 static const struct ravb_hw_info ravb_gen2_hw_info = { 2434 .rx_ring_free = ravb_rx_ring_free_rcar, 2435 .rx_ring_format = ravb_rx_ring_format_rcar, 2436 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2437 .receive = ravb_rx_rcar, 2438 .set_rate = ravb_set_rate_rcar, 2439 .set_feature = ravb_set_features_rcar, 2440 .dmac_init = ravb_dmac_init_rcar, 2441 .emac_init = ravb_emac_init_rcar, 2442 .gstrings_stats = ravb_gstrings_stats, 2443 .gstrings_size = sizeof(ravb_gstrings_stats), 2444 .net_hw_features = NETIF_F_RXCSUM, 2445 .net_features = NETIF_F_RXCSUM, 2446 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2447 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2448 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2449 .rx_max_buf_size = SZ_2K, 2450 .aligned_tx = 1, 2451 .gptp = 1, 2452 .nc_queues = 1, 2453 .magic_pkt = 1, 2454 }; 2455 2456 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2457 .rx_ring_free = ravb_rx_ring_free_rcar, 2458 .rx_ring_format = ravb_rx_ring_format_rcar, 2459 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2460 .receive = ravb_rx_rcar, 2461 .set_rate = ravb_set_rate_rcar, 2462 .set_feature = ravb_set_features_rcar, 2463 .dmac_init = ravb_dmac_init_rcar, 2464 .emac_init = ravb_emac_init_rcar, 2465 .gstrings_stats = ravb_gstrings_stats, 2466 .gstrings_size = sizeof(ravb_gstrings_stats), 2467 .net_hw_features = NETIF_F_RXCSUM, 2468 .net_features = NETIF_F_RXCSUM, 2469 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2470 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2471 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2472 .rx_max_buf_size = SZ_2K, 2473 .multi_irqs = 1, 2474 .err_mgmt_irqs = 1, 2475 .gptp = 1, 2476 .gptp_ref_clk = 1, 2477 .nc_queues = 1, 2478 .magic_pkt = 1, 2479 }; 2480 2481 static const struct ravb_hw_info gbeth_hw_info = { 2482 .rx_ring_free = ravb_rx_ring_free_gbeth, 2483 .rx_ring_format = ravb_rx_ring_format_gbeth, 2484 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2485 .receive = ravb_rx_gbeth, 2486 .set_rate = ravb_set_rate_gbeth, 2487 .set_feature = ravb_set_features_gbeth, 2488 .dmac_init = ravb_dmac_init_gbeth, 2489 .emac_init = ravb_emac_init_gbeth, 2490 .gstrings_stats = ravb_gstrings_stats_gbeth, 2491 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2492 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2493 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), 2494 .tccr_mask = TCCR_TSRQ0, 2495 .rx_max_buf_size = SZ_8K, 2496 .aligned_tx = 1, 2497 .tx_counters = 1, 2498 .carrier_counters = 1, 2499 .half_duplex = 1, 2500 }; 2501 2502 static const struct of_device_id ravb_match_table[] = { 2503 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2504 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2505 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2506 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2507 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2508 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info }, 2509 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2510 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2511 { } 2512 }; 2513 MODULE_DEVICE_TABLE(of, ravb_match_table); 2514 2515 static int ravb_set_gti(struct net_device *ndev) 2516 { 2517 struct ravb_private *priv = netdev_priv(ndev); 2518 const struct ravb_hw_info *info = priv->info; 2519 struct device *dev = ndev->dev.parent; 2520 unsigned long rate; 2521 uint64_t inc; 2522 2523 if (info->gptp_ref_clk) 2524 rate = clk_get_rate(priv->gptp_clk); 2525 else 2526 rate = clk_get_rate(priv->clk); 2527 if (!rate) 2528 return -EINVAL; 2529 2530 inc = div64_ul(1000000000ULL << 20, rate); 2531 2532 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 2533 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 2534 inc, GTI_TIV_MIN, GTI_TIV_MAX); 2535 return -EINVAL; 2536 } 2537 2538 ravb_write(ndev, inc, GTI); 2539 2540 return 0; 2541 } 2542 2543 static void ravb_set_config_mode(struct net_device *ndev) 2544 { 2545 struct ravb_private *priv = netdev_priv(ndev); 2546 const struct ravb_hw_info *info = priv->info; 2547 2548 if (info->gptp) { 2549 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2550 /* Set CSEL value */ 2551 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 2552 } else if (info->ccc_gac) { 2553 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 2554 CCC_GAC | CCC_CSEL_HPB); 2555 } else { 2556 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2557 } 2558 } 2559 2560 /* Set tx and rx clock internal delay modes */ 2561 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2562 { 2563 struct ravb_private *priv = netdev_priv(ndev); 2564 bool explicit_delay = false; 2565 u32 delay; 2566 2567 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2568 /* Valid values are 0 and 1800, according to DT bindings */ 2569 priv->rxcidm = !!delay; 2570 explicit_delay = true; 2571 } 2572 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2573 /* Valid values are 0 and 2000, according to DT bindings */ 2574 priv->txcidm = !!delay; 2575 explicit_delay = true; 2576 } 2577 2578 if (explicit_delay) 2579 return; 2580 2581 /* Fall back to legacy rgmii-*id behavior */ 2582 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2583 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2584 priv->rxcidm = 1; 2585 priv->rgmii_override = 1; 2586 } 2587 2588 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2589 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2590 priv->txcidm = 1; 2591 priv->rgmii_override = 1; 2592 } 2593 } 2594 2595 static void ravb_set_delay_mode(struct net_device *ndev) 2596 { 2597 struct ravb_private *priv = netdev_priv(ndev); 2598 u32 set = 0; 2599 2600 if (priv->rxcidm) 2601 set |= APSR_RDM; 2602 if (priv->txcidm) 2603 set |= APSR_TDM; 2604 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2605 } 2606 2607 static int ravb_probe(struct platform_device *pdev) 2608 { 2609 struct device_node *np = pdev->dev.of_node; 2610 const struct ravb_hw_info *info; 2611 struct reset_control *rstc; 2612 struct ravb_private *priv; 2613 struct net_device *ndev; 2614 int error, irq, q; 2615 struct resource *res; 2616 int i; 2617 2618 if (!np) { 2619 dev_err(&pdev->dev, 2620 "this driver is required to be instantiated from device tree\n"); 2621 return -EINVAL; 2622 } 2623 2624 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2625 if (IS_ERR(rstc)) 2626 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2627 "failed to get cpg reset\n"); 2628 2629 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2630 NUM_TX_QUEUE, NUM_RX_QUEUE); 2631 if (!ndev) 2632 return -ENOMEM; 2633 2634 info = of_device_get_match_data(&pdev->dev); 2635 2636 ndev->features = info->net_features; 2637 ndev->hw_features = info->net_hw_features; 2638 2639 reset_control_deassert(rstc); 2640 pm_runtime_enable(&pdev->dev); 2641 pm_runtime_get_sync(&pdev->dev); 2642 2643 if (info->multi_irqs) { 2644 if (info->err_mgmt_irqs) 2645 irq = platform_get_irq_byname(pdev, "dia"); 2646 else 2647 irq = platform_get_irq_byname(pdev, "ch22"); 2648 } else { 2649 irq = platform_get_irq(pdev, 0); 2650 } 2651 if (irq < 0) { 2652 error = irq; 2653 goto out_release; 2654 } 2655 ndev->irq = irq; 2656 2657 SET_NETDEV_DEV(ndev, &pdev->dev); 2658 2659 priv = netdev_priv(ndev); 2660 priv->info = info; 2661 priv->rstc = rstc; 2662 priv->ndev = ndev; 2663 priv->pdev = pdev; 2664 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2665 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2666 if (info->nc_queues) { 2667 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2668 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2669 } 2670 2671 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2672 if (IS_ERR(priv->addr)) { 2673 error = PTR_ERR(priv->addr); 2674 goto out_release; 2675 } 2676 2677 /* The Ether-specific entries in the device structure. */ 2678 ndev->base_addr = res->start; 2679 2680 spin_lock_init(&priv->lock); 2681 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2682 2683 error = of_get_phy_mode(np, &priv->phy_interface); 2684 if (error && error != -ENODEV) 2685 goto out_release; 2686 2687 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2688 priv->avb_link_active_low = 2689 of_property_read_bool(np, "renesas,ether-link-active-low"); 2690 2691 if (info->multi_irqs) { 2692 if (info->err_mgmt_irqs) 2693 irq = platform_get_irq_byname(pdev, "line3"); 2694 else 2695 irq = platform_get_irq_byname(pdev, "ch24"); 2696 if (irq < 0) { 2697 error = irq; 2698 goto out_release; 2699 } 2700 priv->emac_irq = irq; 2701 for (i = 0; i < NUM_RX_QUEUE; i++) { 2702 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2703 if (irq < 0) { 2704 error = irq; 2705 goto out_release; 2706 } 2707 priv->rx_irqs[i] = irq; 2708 } 2709 for (i = 0; i < NUM_TX_QUEUE; i++) { 2710 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2711 if (irq < 0) { 2712 error = irq; 2713 goto out_release; 2714 } 2715 priv->tx_irqs[i] = irq; 2716 } 2717 2718 if (info->err_mgmt_irqs) { 2719 irq = platform_get_irq_byname(pdev, "err_a"); 2720 if (irq < 0) { 2721 error = irq; 2722 goto out_release; 2723 } 2724 priv->erra_irq = irq; 2725 2726 irq = platform_get_irq_byname(pdev, "mgmt_a"); 2727 if (irq < 0) { 2728 error = irq; 2729 goto out_release; 2730 } 2731 priv->mgmta_irq = irq; 2732 } 2733 } 2734 2735 priv->clk = devm_clk_get(&pdev->dev, NULL); 2736 if (IS_ERR(priv->clk)) { 2737 error = PTR_ERR(priv->clk); 2738 goto out_release; 2739 } 2740 2741 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2742 if (IS_ERR(priv->refclk)) { 2743 error = PTR_ERR(priv->refclk); 2744 goto out_release; 2745 } 2746 clk_prepare_enable(priv->refclk); 2747 2748 if (info->gptp_ref_clk) { 2749 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2750 if (IS_ERR(priv->gptp_clk)) { 2751 error = PTR_ERR(priv->gptp_clk); 2752 goto out_disable_refclk; 2753 } 2754 clk_prepare_enable(priv->gptp_clk); 2755 } 2756 2757 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2758 ndev->min_mtu = ETH_MIN_MTU; 2759 2760 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2761 * Use two descriptor to handle such situation. First descriptor to 2762 * handle aligned data buffer and second descriptor to handle the 2763 * overflow data because of alignment. 2764 */ 2765 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2766 2767 /* Set function */ 2768 ndev->netdev_ops = &ravb_netdev_ops; 2769 ndev->ethtool_ops = &ravb_ethtool_ops; 2770 2771 /* Set AVB config mode */ 2772 ravb_set_config_mode(ndev); 2773 2774 if (info->gptp || info->ccc_gac) { 2775 /* Set GTI value */ 2776 error = ravb_set_gti(ndev); 2777 if (error) 2778 goto out_disable_gptp_clk; 2779 2780 /* Request GTI loading */ 2781 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2782 } 2783 2784 if (info->internal_delay) { 2785 ravb_parse_delay_mode(np, ndev); 2786 ravb_set_delay_mode(ndev); 2787 } 2788 2789 /* Allocate descriptor base address table */ 2790 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2791 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2792 &priv->desc_bat_dma, GFP_KERNEL); 2793 if (!priv->desc_bat) { 2794 dev_err(&pdev->dev, 2795 "Cannot allocate desc base address table (size %d bytes)\n", 2796 priv->desc_bat_size); 2797 error = -ENOMEM; 2798 goto out_disable_gptp_clk; 2799 } 2800 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2801 priv->desc_bat[q].die_dt = DT_EOS; 2802 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2803 2804 /* Initialise HW timestamp list */ 2805 INIT_LIST_HEAD(&priv->ts_skb_list); 2806 2807 /* Initialise PTP Clock driver */ 2808 if (info->ccc_gac) 2809 ravb_ptp_init(ndev, pdev); 2810 2811 /* Debug message level */ 2812 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2813 2814 /* Read and set MAC address */ 2815 ravb_read_mac_address(np, ndev); 2816 if (!is_valid_ether_addr(ndev->dev_addr)) { 2817 dev_warn(&pdev->dev, 2818 "no valid MAC address supplied, using a random one\n"); 2819 eth_hw_addr_random(ndev); 2820 } 2821 2822 /* MDIO bus init */ 2823 error = ravb_mdio_init(priv); 2824 if (error) { 2825 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2826 goto out_dma_free; 2827 } 2828 2829 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 2830 if (info->nc_queues) 2831 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 2832 2833 /* Network device register */ 2834 error = register_netdev(ndev); 2835 if (error) 2836 goto out_napi_del; 2837 2838 device_set_wakeup_capable(&pdev->dev, 1); 2839 2840 /* Print device information */ 2841 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2842 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2843 2844 platform_set_drvdata(pdev, ndev); 2845 2846 return 0; 2847 2848 out_napi_del: 2849 if (info->nc_queues) 2850 netif_napi_del(&priv->napi[RAVB_NC]); 2851 2852 netif_napi_del(&priv->napi[RAVB_BE]); 2853 ravb_mdio_release(priv); 2854 out_dma_free: 2855 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2856 priv->desc_bat_dma); 2857 2858 /* Stop PTP Clock driver */ 2859 if (info->ccc_gac) 2860 ravb_ptp_stop(ndev); 2861 out_disable_gptp_clk: 2862 clk_disable_unprepare(priv->gptp_clk); 2863 out_disable_refclk: 2864 clk_disable_unprepare(priv->refclk); 2865 out_release: 2866 free_netdev(ndev); 2867 2868 pm_runtime_put(&pdev->dev); 2869 pm_runtime_disable(&pdev->dev); 2870 reset_control_assert(rstc); 2871 return error; 2872 } 2873 2874 static int ravb_remove(struct platform_device *pdev) 2875 { 2876 struct net_device *ndev = platform_get_drvdata(pdev); 2877 struct ravb_private *priv = netdev_priv(ndev); 2878 const struct ravb_hw_info *info = priv->info; 2879 2880 /* Stop PTP Clock driver */ 2881 if (info->ccc_gac) 2882 ravb_ptp_stop(ndev); 2883 2884 clk_disable_unprepare(priv->gptp_clk); 2885 clk_disable_unprepare(priv->refclk); 2886 2887 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2888 priv->desc_bat_dma); 2889 /* Set reset mode */ 2890 ravb_write(ndev, CCC_OPC_RESET, CCC); 2891 unregister_netdev(ndev); 2892 if (info->nc_queues) 2893 netif_napi_del(&priv->napi[RAVB_NC]); 2894 netif_napi_del(&priv->napi[RAVB_BE]); 2895 ravb_mdio_release(priv); 2896 pm_runtime_put_sync(&pdev->dev); 2897 pm_runtime_disable(&pdev->dev); 2898 reset_control_assert(priv->rstc); 2899 free_netdev(ndev); 2900 platform_set_drvdata(pdev, NULL); 2901 2902 return 0; 2903 } 2904 2905 static int ravb_wol_setup(struct net_device *ndev) 2906 { 2907 struct ravb_private *priv = netdev_priv(ndev); 2908 const struct ravb_hw_info *info = priv->info; 2909 2910 /* Disable interrupts by clearing the interrupt masks. */ 2911 ravb_write(ndev, 0, RIC0); 2912 ravb_write(ndev, 0, RIC2); 2913 ravb_write(ndev, 0, TIC); 2914 2915 /* Only allow ECI interrupts */ 2916 synchronize_irq(priv->emac_irq); 2917 if (info->nc_queues) 2918 napi_disable(&priv->napi[RAVB_NC]); 2919 napi_disable(&priv->napi[RAVB_BE]); 2920 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2921 2922 /* Enable MagicPacket */ 2923 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2924 2925 return enable_irq_wake(priv->emac_irq); 2926 } 2927 2928 static int ravb_wol_restore(struct net_device *ndev) 2929 { 2930 struct ravb_private *priv = netdev_priv(ndev); 2931 const struct ravb_hw_info *info = priv->info; 2932 2933 if (info->nc_queues) 2934 napi_enable(&priv->napi[RAVB_NC]); 2935 napi_enable(&priv->napi[RAVB_BE]); 2936 2937 /* Disable MagicPacket */ 2938 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2939 2940 ravb_close(ndev); 2941 2942 return disable_irq_wake(priv->emac_irq); 2943 } 2944 2945 static int __maybe_unused ravb_suspend(struct device *dev) 2946 { 2947 struct net_device *ndev = dev_get_drvdata(dev); 2948 struct ravb_private *priv = netdev_priv(ndev); 2949 int ret; 2950 2951 if (!netif_running(ndev)) 2952 return 0; 2953 2954 netif_device_detach(ndev); 2955 2956 if (priv->wol_enabled) 2957 ret = ravb_wol_setup(ndev); 2958 else 2959 ret = ravb_close(ndev); 2960 2961 if (priv->info->ccc_gac) 2962 ravb_ptp_stop(ndev); 2963 2964 return ret; 2965 } 2966 2967 static int __maybe_unused ravb_resume(struct device *dev) 2968 { 2969 struct net_device *ndev = dev_get_drvdata(dev); 2970 struct ravb_private *priv = netdev_priv(ndev); 2971 const struct ravb_hw_info *info = priv->info; 2972 int ret = 0; 2973 2974 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2975 if (priv->wol_enabled) 2976 ravb_write(ndev, CCC_OPC_RESET, CCC); 2977 2978 /* All register have been reset to default values. 2979 * Restore all registers which where setup at probe time and 2980 * reopen device if it was running before system suspended. 2981 */ 2982 2983 /* Set AVB config mode */ 2984 ravb_set_config_mode(ndev); 2985 2986 if (info->gptp || info->ccc_gac) { 2987 /* Set GTI value */ 2988 ret = ravb_set_gti(ndev); 2989 if (ret) 2990 return ret; 2991 2992 /* Request GTI loading */ 2993 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2994 } 2995 2996 if (info->internal_delay) 2997 ravb_set_delay_mode(ndev); 2998 2999 /* Restore descriptor base address table */ 3000 ravb_write(ndev, priv->desc_bat_dma, DBAT); 3001 3002 if (priv->info->ccc_gac) 3003 ravb_ptp_init(ndev, priv->pdev); 3004 3005 if (netif_running(ndev)) { 3006 if (priv->wol_enabled) { 3007 ret = ravb_wol_restore(ndev); 3008 if (ret) 3009 return ret; 3010 } 3011 ret = ravb_open(ndev); 3012 if (ret < 0) 3013 return ret; 3014 ravb_set_rx_mode(ndev); 3015 netif_device_attach(ndev); 3016 } 3017 3018 return ret; 3019 } 3020 3021 static int __maybe_unused ravb_runtime_nop(struct device *dev) 3022 { 3023 /* Runtime PM callback shared between ->runtime_suspend() 3024 * and ->runtime_resume(). Simply returns success. 3025 * 3026 * This driver re-initializes all registers after 3027 * pm_runtime_get_sync() anyway so there is no need 3028 * to save and restore registers here. 3029 */ 3030 return 0; 3031 } 3032 3033 static const struct dev_pm_ops ravb_dev_pm_ops = { 3034 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3035 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 3036 }; 3037 3038 static struct platform_driver ravb_driver = { 3039 .probe = ravb_probe, 3040 .remove = ravb_remove, 3041 .driver = { 3042 .name = "ravb", 3043 .pm = &ravb_dev_pm_ops, 3044 .of_match_table = ravb_match_table, 3045 }, 3046 }; 3047 3048 module_platform_driver(ravb_driver); 3049 3050 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3051 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3052 MODULE_LICENSE("GPL v2"); 3053