1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 #include <linux/reset.h> 33 34 #include <asm/div64.h> 35 36 #include "ravb.h" 37 38 #define RAVB_DEF_MSG_ENABLE \ 39 (NETIF_MSG_LINK | \ 40 NETIF_MSG_TIMER | \ 41 NETIF_MSG_RX_ERR | \ 42 NETIF_MSG_TX_ERR) 43 44 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 45 "ch0", /* RAVB_BE */ 46 "ch1", /* RAVB_NC */ 47 }; 48 49 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 50 "ch18", /* RAVB_BE */ 51 "ch19", /* RAVB_NC */ 52 }; 53 54 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 55 u32 set) 56 { 57 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 58 } 59 60 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 61 { 62 int i; 63 64 for (i = 0; i < 10000; i++) { 65 if ((ravb_read(ndev, reg) & mask) == value) 66 return 0; 67 udelay(10); 68 } 69 return -ETIMEDOUT; 70 } 71 72 static int ravb_config(struct net_device *ndev) 73 { 74 int error; 75 76 /* Set config mode */ 77 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 78 /* Check if the operating mode is changed to the config mode */ 79 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 80 if (error) 81 netdev_err(ndev, "failed to switch device to config mode\n"); 82 83 return error; 84 } 85 86 static void ravb_set_rate_gbeth(struct net_device *ndev) 87 { 88 struct ravb_private *priv = netdev_priv(ndev); 89 90 switch (priv->speed) { 91 case 10: /* 10BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 93 break; 94 case 100: /* 100BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 96 break; 97 case 1000: /* 1000BASE */ 98 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 99 break; 100 } 101 } 102 103 static void ravb_set_rate_rcar(struct net_device *ndev) 104 { 105 struct ravb_private *priv = netdev_priv(ndev); 106 107 switch (priv->speed) { 108 case 100: /* 100BASE */ 109 ravb_write(ndev, GECMR_SPEED_100, GECMR); 110 break; 111 case 1000: /* 1000BASE */ 112 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 113 break; 114 } 115 } 116 117 static void ravb_set_buffer_align(struct sk_buff *skb) 118 { 119 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 120 121 if (reserve) 122 skb_reserve(skb, RAVB_ALIGN - reserve); 123 } 124 125 /* Get MAC address from the MAC address registers 126 * 127 * Ethernet AVB device doesn't have ROM for MAC address. 128 * This function gets the MAC address that was used by a bootloader. 129 */ 130 static void ravb_read_mac_address(struct device_node *np, 131 struct net_device *ndev) 132 { 133 int ret; 134 135 ret = of_get_ethdev_address(np, ndev); 136 if (ret) { 137 u32 mahr = ravb_read(ndev, MAHR); 138 u32 malr = ravb_read(ndev, MALR); 139 u8 addr[ETH_ALEN]; 140 141 addr[0] = (mahr >> 24) & 0xFF; 142 addr[1] = (mahr >> 16) & 0xFF; 143 addr[2] = (mahr >> 8) & 0xFF; 144 addr[3] = (mahr >> 0) & 0xFF; 145 addr[4] = (malr >> 8) & 0xFF; 146 addr[5] = (malr >> 0) & 0xFF; 147 eth_hw_addr_set(ndev, addr); 148 } 149 } 150 151 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 152 { 153 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 154 mdiobb); 155 156 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 157 } 158 159 /* MDC pin control */ 160 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 161 { 162 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 163 } 164 165 /* Data I/O pin control */ 166 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 167 { 168 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 169 } 170 171 /* Set data bit */ 172 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 173 { 174 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 175 } 176 177 /* Get data bit */ 178 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 179 { 180 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 181 mdiobb); 182 183 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 184 } 185 186 /* MDIO bus control struct */ 187 static const struct mdiobb_ops bb_ops = { 188 .owner = THIS_MODULE, 189 .set_mdc = ravb_set_mdc, 190 .set_mdio_dir = ravb_set_mdio_dir, 191 .set_mdio_data = ravb_set_mdio_data, 192 .get_mdio_data = ravb_get_mdio_data, 193 }; 194 195 /* Free TX skb function for AVB-IP */ 196 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 197 { 198 struct ravb_private *priv = netdev_priv(ndev); 199 struct net_device_stats *stats = &priv->stats[q]; 200 unsigned int num_tx_desc = priv->num_tx_desc; 201 struct ravb_tx_desc *desc; 202 unsigned int entry; 203 int free_num = 0; 204 u32 size; 205 206 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 207 bool txed; 208 209 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 210 num_tx_desc); 211 desc = &priv->tx_ring[q][entry]; 212 txed = desc->die_dt == DT_FEMPTY; 213 if (free_txed_only && !txed) 214 break; 215 /* Descriptor type must be checked before all other reads */ 216 dma_rmb(); 217 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 218 /* Free the original skb. */ 219 if (priv->tx_skb[q][entry / num_tx_desc]) { 220 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 221 size, DMA_TO_DEVICE); 222 /* Last packet descriptor? */ 223 if (entry % num_tx_desc == num_tx_desc - 1) { 224 entry /= num_tx_desc; 225 dev_kfree_skb_any(priv->tx_skb[q][entry]); 226 priv->tx_skb[q][entry] = NULL; 227 if (txed) 228 stats->tx_packets++; 229 } 230 free_num++; 231 } 232 if (txed) 233 stats->tx_bytes += size; 234 desc->die_dt = DT_EEMPTY; 235 } 236 return free_num; 237 } 238 239 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 240 { 241 struct ravb_private *priv = netdev_priv(ndev); 242 unsigned int ring_size; 243 unsigned int i; 244 245 if (!priv->gbeth_rx_ring) 246 return; 247 248 for (i = 0; i < priv->num_rx_ring[q]; i++) { 249 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i]; 250 251 if (!dma_mapping_error(ndev->dev.parent, 252 le32_to_cpu(desc->dptr))) 253 dma_unmap_single(ndev->dev.parent, 254 le32_to_cpu(desc->dptr), 255 GBETH_RX_BUFF_MAX, 256 DMA_FROM_DEVICE); 257 } 258 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 259 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring, 260 priv->rx_desc_dma[q]); 261 priv->gbeth_rx_ring = NULL; 262 } 263 264 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q) 265 { 266 struct ravb_private *priv = netdev_priv(ndev); 267 unsigned int ring_size; 268 unsigned int i; 269 270 if (!priv->rx_ring[q]) 271 return; 272 273 for (i = 0; i < priv->num_rx_ring[q]; i++) { 274 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 275 276 if (!dma_mapping_error(ndev->dev.parent, 277 le32_to_cpu(desc->dptr))) 278 dma_unmap_single(ndev->dev.parent, 279 le32_to_cpu(desc->dptr), 280 RX_BUF_SZ, 281 DMA_FROM_DEVICE); 282 } 283 ring_size = sizeof(struct ravb_ex_rx_desc) * 284 (priv->num_rx_ring[q] + 1); 285 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 286 priv->rx_desc_dma[q]); 287 priv->rx_ring[q] = NULL; 288 } 289 290 /* Free skb's and DMA buffers for Ethernet AVB */ 291 static void ravb_ring_free(struct net_device *ndev, int q) 292 { 293 struct ravb_private *priv = netdev_priv(ndev); 294 const struct ravb_hw_info *info = priv->info; 295 unsigned int num_tx_desc = priv->num_tx_desc; 296 unsigned int ring_size; 297 unsigned int i; 298 299 info->rx_ring_free(ndev, q); 300 301 if (priv->tx_ring[q]) { 302 ravb_tx_free(ndev, q, false); 303 304 ring_size = sizeof(struct ravb_tx_desc) * 305 (priv->num_tx_ring[q] * num_tx_desc + 1); 306 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 307 priv->tx_desc_dma[q]); 308 priv->tx_ring[q] = NULL; 309 } 310 311 /* Free RX skb ringbuffer */ 312 if (priv->rx_skb[q]) { 313 for (i = 0; i < priv->num_rx_ring[q]; i++) 314 dev_kfree_skb(priv->rx_skb[q][i]); 315 } 316 kfree(priv->rx_skb[q]); 317 priv->rx_skb[q] = NULL; 318 319 /* Free aligned TX buffers */ 320 kfree(priv->tx_align[q]); 321 priv->tx_align[q] = NULL; 322 323 /* Free TX skb ringbuffer. 324 * SKBs are freed by ravb_tx_free() call above. 325 */ 326 kfree(priv->tx_skb[q]); 327 priv->tx_skb[q] = NULL; 328 } 329 330 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 331 { 332 struct ravb_private *priv = netdev_priv(ndev); 333 struct ravb_rx_desc *rx_desc; 334 unsigned int rx_ring_size; 335 dma_addr_t dma_addr; 336 unsigned int i; 337 338 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 339 memset(priv->gbeth_rx_ring, 0, rx_ring_size); 340 /* Build RX ring buffer */ 341 for (i = 0; i < priv->num_rx_ring[q]; i++) { 342 /* RX descriptor */ 343 rx_desc = &priv->gbeth_rx_ring[i]; 344 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 345 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 346 GBETH_RX_BUFF_MAX, 347 DMA_FROM_DEVICE); 348 /* We just set the data size to 0 for a failed mapping which 349 * should prevent DMA from happening... 350 */ 351 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 352 rx_desc->ds_cc = cpu_to_le16(0); 353 rx_desc->dptr = cpu_to_le32(dma_addr); 354 rx_desc->die_dt = DT_FEMPTY; 355 } 356 rx_desc = &priv->gbeth_rx_ring[i]; 357 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 358 rx_desc->die_dt = DT_LINKFIX; /* type */ 359 } 360 361 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q) 362 { 363 struct ravb_private *priv = netdev_priv(ndev); 364 struct ravb_ex_rx_desc *rx_desc; 365 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 366 dma_addr_t dma_addr; 367 unsigned int i; 368 369 memset(priv->rx_ring[q], 0, rx_ring_size); 370 /* Build RX ring buffer */ 371 for (i = 0; i < priv->num_rx_ring[q]; i++) { 372 /* RX descriptor */ 373 rx_desc = &priv->rx_ring[q][i]; 374 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 375 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 376 RX_BUF_SZ, 377 DMA_FROM_DEVICE); 378 /* We just set the data size to 0 for a failed mapping which 379 * should prevent DMA from happening... 380 */ 381 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 382 rx_desc->ds_cc = cpu_to_le16(0); 383 rx_desc->dptr = cpu_to_le32(dma_addr); 384 rx_desc->die_dt = DT_FEMPTY; 385 } 386 rx_desc = &priv->rx_ring[q][i]; 387 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 388 rx_desc->die_dt = DT_LINKFIX; /* type */ 389 } 390 391 /* Format skb and descriptor buffer for Ethernet AVB */ 392 static void ravb_ring_format(struct net_device *ndev, int q) 393 { 394 struct ravb_private *priv = netdev_priv(ndev); 395 const struct ravb_hw_info *info = priv->info; 396 unsigned int num_tx_desc = priv->num_tx_desc; 397 struct ravb_tx_desc *tx_desc; 398 struct ravb_desc *desc; 399 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 400 num_tx_desc; 401 unsigned int i; 402 403 priv->cur_rx[q] = 0; 404 priv->cur_tx[q] = 0; 405 priv->dirty_rx[q] = 0; 406 priv->dirty_tx[q] = 0; 407 408 info->rx_ring_format(ndev, q); 409 410 memset(priv->tx_ring[q], 0, tx_ring_size); 411 /* Build TX ring buffer */ 412 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 413 i++, tx_desc++) { 414 tx_desc->die_dt = DT_EEMPTY; 415 if (num_tx_desc > 1) { 416 tx_desc++; 417 tx_desc->die_dt = DT_EEMPTY; 418 } 419 } 420 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 421 tx_desc->die_dt = DT_LINKFIX; /* type */ 422 423 /* RX descriptor base address for best effort */ 424 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 425 desc->die_dt = DT_LINKFIX; /* type */ 426 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 427 428 /* TX descriptor base address for best effort */ 429 desc = &priv->desc_bat[q]; 430 desc->die_dt = DT_LINKFIX; /* type */ 431 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 432 } 433 434 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 435 { 436 struct ravb_private *priv = netdev_priv(ndev); 437 unsigned int ring_size; 438 439 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 440 441 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size, 442 &priv->rx_desc_dma[q], 443 GFP_KERNEL); 444 return priv->gbeth_rx_ring; 445 } 446 447 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q) 448 { 449 struct ravb_private *priv = netdev_priv(ndev); 450 unsigned int ring_size; 451 452 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 453 454 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 455 &priv->rx_desc_dma[q], 456 GFP_KERNEL); 457 return priv->rx_ring[q]; 458 } 459 460 /* Init skb and descriptor buffer for Ethernet AVB */ 461 static int ravb_ring_init(struct net_device *ndev, int q) 462 { 463 struct ravb_private *priv = netdev_priv(ndev); 464 const struct ravb_hw_info *info = priv->info; 465 unsigned int num_tx_desc = priv->num_tx_desc; 466 unsigned int ring_size; 467 struct sk_buff *skb; 468 unsigned int i; 469 470 /* Allocate RX and TX skb rings */ 471 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 472 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 473 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 474 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 475 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 476 goto error; 477 478 for (i = 0; i < priv->num_rx_ring[q]; i++) { 479 skb = netdev_alloc_skb(ndev, info->max_rx_len); 480 if (!skb) 481 goto error; 482 ravb_set_buffer_align(skb); 483 priv->rx_skb[q][i] = skb; 484 } 485 486 if (num_tx_desc > 1) { 487 /* Allocate rings for the aligned buffers */ 488 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 489 DPTR_ALIGN - 1, GFP_KERNEL); 490 if (!priv->tx_align[q]) 491 goto error; 492 } 493 494 /* Allocate all RX descriptors. */ 495 if (!info->alloc_rx_desc(ndev, q)) 496 goto error; 497 498 priv->dirty_rx[q] = 0; 499 500 /* Allocate all TX descriptors. */ 501 ring_size = sizeof(struct ravb_tx_desc) * 502 (priv->num_tx_ring[q] * num_tx_desc + 1); 503 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 504 &priv->tx_desc_dma[q], 505 GFP_KERNEL); 506 if (!priv->tx_ring[q]) 507 goto error; 508 509 return 0; 510 511 error: 512 ravb_ring_free(ndev, q); 513 514 return -ENOMEM; 515 } 516 517 static void ravb_emac_init_gbeth(struct net_device *ndev) 518 { 519 struct ravb_private *priv = netdev_priv(ndev); 520 521 /* Receive frame limit set register */ 522 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 523 524 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 525 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 526 ECMR_TE | ECMR_RE | ECMR_RCPT | 527 ECMR_TXF | ECMR_RXF, ECMR); 528 529 ravb_set_rate_gbeth(ndev); 530 531 /* Set MAC address */ 532 ravb_write(ndev, 533 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 534 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 535 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 536 537 /* E-MAC status register clear */ 538 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 539 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 540 541 /* E-MAC interrupt enable register */ 542 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 543 544 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, CXR31_SEL_LINK0); 545 } 546 547 static void ravb_emac_init_rcar(struct net_device *ndev) 548 { 549 /* Receive frame limit set register */ 550 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 551 552 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 553 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 554 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 555 ECMR_TE | ECMR_RE, ECMR); 556 557 ravb_set_rate_rcar(ndev); 558 559 /* Set MAC address */ 560 ravb_write(ndev, 561 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 562 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 563 ravb_write(ndev, 564 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 565 566 /* E-MAC status register clear */ 567 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 568 569 /* E-MAC interrupt enable register */ 570 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 571 } 572 573 /* E-MAC init function */ 574 static void ravb_emac_init(struct net_device *ndev) 575 { 576 struct ravb_private *priv = netdev_priv(ndev); 577 const struct ravb_hw_info *info = priv->info; 578 579 info->emac_init(ndev); 580 } 581 582 static int ravb_dmac_init_gbeth(struct net_device *ndev) 583 { 584 int error; 585 586 error = ravb_ring_init(ndev, RAVB_BE); 587 if (error) 588 return error; 589 590 /* Descriptor format */ 591 ravb_ring_format(ndev, RAVB_BE); 592 593 /* Set DMAC RX */ 594 ravb_write(ndev, 0x60000000, RCR); 595 596 /* Set Max Frame Length (RTC) */ 597 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 598 599 /* Set FIFO size */ 600 ravb_write(ndev, 0x00222200, TGC); 601 602 ravb_write(ndev, 0, TCCR); 603 604 /* Frame receive */ 605 ravb_write(ndev, RIC0_FRE0, RIC0); 606 /* Disable FIFO full warning */ 607 ravb_write(ndev, 0x0, RIC1); 608 /* Receive FIFO full error, descriptor empty */ 609 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 610 611 ravb_write(ndev, TIC_FTE0, TIC); 612 613 return 0; 614 } 615 616 static int ravb_dmac_init_rcar(struct net_device *ndev) 617 { 618 struct ravb_private *priv = netdev_priv(ndev); 619 const struct ravb_hw_info *info = priv->info; 620 int error; 621 622 error = ravb_ring_init(ndev, RAVB_BE); 623 if (error) 624 return error; 625 error = ravb_ring_init(ndev, RAVB_NC); 626 if (error) { 627 ravb_ring_free(ndev, RAVB_BE); 628 return error; 629 } 630 631 /* Descriptor format */ 632 ravb_ring_format(ndev, RAVB_BE); 633 ravb_ring_format(ndev, RAVB_NC); 634 635 /* Set AVB RX */ 636 ravb_write(ndev, 637 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 638 639 /* Set FIFO size */ 640 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 641 642 /* Timestamp enable */ 643 ravb_write(ndev, TCCR_TFEN, TCCR); 644 645 /* Interrupt init: */ 646 if (info->multi_irqs) { 647 /* Clear DIL.DPLx */ 648 ravb_write(ndev, 0, DIL); 649 /* Set queue specific interrupt */ 650 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 651 } 652 /* Frame receive */ 653 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 654 /* Disable FIFO full warning */ 655 ravb_write(ndev, 0, RIC1); 656 /* Receive FIFO full error, descriptor empty */ 657 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 658 /* Frame transmitted, timestamp FIFO updated */ 659 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 660 661 return 0; 662 } 663 664 /* Device init function for Ethernet AVB */ 665 static int ravb_dmac_init(struct net_device *ndev) 666 { 667 struct ravb_private *priv = netdev_priv(ndev); 668 const struct ravb_hw_info *info = priv->info; 669 int error; 670 671 /* Set CONFIG mode */ 672 error = ravb_config(ndev); 673 if (error) 674 return error; 675 676 error = info->dmac_init(ndev); 677 if (error) 678 return error; 679 680 /* Setting the control will start the AVB-DMAC process. */ 681 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 682 683 return 0; 684 } 685 686 static void ravb_get_tx_tstamp(struct net_device *ndev) 687 { 688 struct ravb_private *priv = netdev_priv(ndev); 689 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 690 struct skb_shared_hwtstamps shhwtstamps; 691 struct sk_buff *skb; 692 struct timespec64 ts; 693 u16 tag, tfa_tag; 694 int count; 695 u32 tfa2; 696 697 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 698 while (count--) { 699 tfa2 = ravb_read(ndev, TFA2); 700 tfa_tag = (tfa2 & TFA2_TST) >> 16; 701 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 702 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 703 ravb_read(ndev, TFA1); 704 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 705 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 706 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 707 list) { 708 skb = ts_skb->skb; 709 tag = ts_skb->tag; 710 list_del(&ts_skb->list); 711 kfree(ts_skb); 712 if (tag == tfa_tag) { 713 skb_tstamp_tx(skb, &shhwtstamps); 714 dev_consume_skb_any(skb); 715 break; 716 } else { 717 dev_kfree_skb_any(skb); 718 } 719 } 720 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 721 } 722 } 723 724 static void ravb_rx_csum(struct sk_buff *skb) 725 { 726 u8 *hw_csum; 727 728 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 729 * appended to packet data 730 */ 731 if (unlikely(skb->len < sizeof(__sum16))) 732 return; 733 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 734 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 735 skb->ip_summed = CHECKSUM_COMPLETE; 736 skb_trim(skb, skb->len - sizeof(__sum16)); 737 } 738 739 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 740 struct ravb_rx_desc *desc) 741 { 742 struct ravb_private *priv = netdev_priv(ndev); 743 struct sk_buff *skb; 744 745 skb = priv->rx_skb[RAVB_BE][entry]; 746 priv->rx_skb[RAVB_BE][entry] = NULL; 747 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 748 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE); 749 750 return skb; 751 } 752 753 /* Packet receive function for Gigabit Ethernet */ 754 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 755 { 756 struct ravb_private *priv = netdev_priv(ndev); 757 const struct ravb_hw_info *info = priv->info; 758 struct net_device_stats *stats; 759 struct ravb_rx_desc *desc; 760 struct sk_buff *skb; 761 dma_addr_t dma_addr; 762 u8 desc_status; 763 int boguscnt; 764 u16 pkt_len; 765 u8 die_dt; 766 int entry; 767 int limit; 768 769 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 770 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 771 stats = &priv->stats[q]; 772 773 boguscnt = min(boguscnt, *quota); 774 limit = boguscnt; 775 desc = &priv->gbeth_rx_ring[entry]; 776 while (desc->die_dt != DT_FEMPTY) { 777 /* Descriptor type must be checked before all other reads */ 778 dma_rmb(); 779 desc_status = desc->msc; 780 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 781 782 if (--boguscnt < 0) 783 break; 784 785 /* We use 0-byte descriptors to mark the DMA mapping errors */ 786 if (!pkt_len) 787 continue; 788 789 if (desc_status & MSC_MC) 790 stats->multicast++; 791 792 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 793 stats->rx_errors++; 794 if (desc_status & MSC_CRC) 795 stats->rx_crc_errors++; 796 if (desc_status & MSC_RFE) 797 stats->rx_frame_errors++; 798 if (desc_status & (MSC_RTLF | MSC_RTSF)) 799 stats->rx_length_errors++; 800 if (desc_status & MSC_CEEF) 801 stats->rx_missed_errors++; 802 } else { 803 die_dt = desc->die_dt & 0xF0; 804 switch (die_dt) { 805 case DT_FSINGLE: 806 skb = ravb_get_skb_gbeth(ndev, entry, desc); 807 skb_put(skb, pkt_len); 808 skb->protocol = eth_type_trans(skb, ndev); 809 napi_gro_receive(&priv->napi[q], skb); 810 stats->rx_packets++; 811 stats->rx_bytes += pkt_len; 812 break; 813 case DT_FSTART: 814 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 815 skb_put(priv->rx_1st_skb, pkt_len); 816 break; 817 case DT_FMID: 818 skb = ravb_get_skb_gbeth(ndev, entry, desc); 819 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 820 priv->rx_1st_skb->len, 821 skb->data, 822 pkt_len); 823 skb_put(priv->rx_1st_skb, pkt_len); 824 dev_kfree_skb(skb); 825 break; 826 case DT_FEND: 827 skb = ravb_get_skb_gbeth(ndev, entry, desc); 828 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 829 priv->rx_1st_skb->len, 830 skb->data, 831 pkt_len); 832 skb_put(priv->rx_1st_skb, pkt_len); 833 dev_kfree_skb(skb); 834 priv->rx_1st_skb->protocol = 835 eth_type_trans(priv->rx_1st_skb, ndev); 836 napi_gro_receive(&priv->napi[q], 837 priv->rx_1st_skb); 838 stats->rx_packets++; 839 stats->rx_bytes += priv->rx_1st_skb->len; 840 break; 841 } 842 } 843 844 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 845 desc = &priv->gbeth_rx_ring[entry]; 846 } 847 848 /* Refill the RX ring buffers. */ 849 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 850 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 851 desc = &priv->gbeth_rx_ring[entry]; 852 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 853 854 if (!priv->rx_skb[q][entry]) { 855 skb = netdev_alloc_skb(ndev, info->max_rx_len); 856 if (!skb) 857 break; 858 ravb_set_buffer_align(skb); 859 dma_addr = dma_map_single(ndev->dev.parent, 860 skb->data, 861 GBETH_RX_BUFF_MAX, 862 DMA_FROM_DEVICE); 863 skb_checksum_none_assert(skb); 864 /* We just set the data size to 0 for a failed mapping 865 * which should prevent DMA from happening... 866 */ 867 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 868 desc->ds_cc = cpu_to_le16(0); 869 desc->dptr = cpu_to_le32(dma_addr); 870 priv->rx_skb[q][entry] = skb; 871 } 872 /* Descriptor type must be set after all the above writes */ 873 dma_wmb(); 874 desc->die_dt = DT_FEMPTY; 875 } 876 877 *quota -= limit - (++boguscnt); 878 879 return boguscnt <= 0; 880 } 881 882 /* Packet receive function for Ethernet AVB */ 883 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 884 { 885 struct ravb_private *priv = netdev_priv(ndev); 886 const struct ravb_hw_info *info = priv->info; 887 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 888 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 889 priv->cur_rx[q]; 890 struct net_device_stats *stats = &priv->stats[q]; 891 struct ravb_ex_rx_desc *desc; 892 struct sk_buff *skb; 893 dma_addr_t dma_addr; 894 struct timespec64 ts; 895 u8 desc_status; 896 u16 pkt_len; 897 int limit; 898 899 boguscnt = min(boguscnt, *quota); 900 limit = boguscnt; 901 desc = &priv->rx_ring[q][entry]; 902 while (desc->die_dt != DT_FEMPTY) { 903 /* Descriptor type must be checked before all other reads */ 904 dma_rmb(); 905 desc_status = desc->msc; 906 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 907 908 if (--boguscnt < 0) 909 break; 910 911 /* We use 0-byte descriptors to mark the DMA mapping errors */ 912 if (!pkt_len) 913 continue; 914 915 if (desc_status & MSC_MC) 916 stats->multicast++; 917 918 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 919 MSC_CEEF)) { 920 stats->rx_errors++; 921 if (desc_status & MSC_CRC) 922 stats->rx_crc_errors++; 923 if (desc_status & MSC_RFE) 924 stats->rx_frame_errors++; 925 if (desc_status & (MSC_RTLF | MSC_RTSF)) 926 stats->rx_length_errors++; 927 if (desc_status & MSC_CEEF) 928 stats->rx_missed_errors++; 929 } else { 930 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 931 932 skb = priv->rx_skb[q][entry]; 933 priv->rx_skb[q][entry] = NULL; 934 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 935 RX_BUF_SZ, 936 DMA_FROM_DEVICE); 937 get_ts &= (q == RAVB_NC) ? 938 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 939 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 940 if (get_ts) { 941 struct skb_shared_hwtstamps *shhwtstamps; 942 943 shhwtstamps = skb_hwtstamps(skb); 944 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 945 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 946 32) | le32_to_cpu(desc->ts_sl); 947 ts.tv_nsec = le32_to_cpu(desc->ts_n); 948 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 949 } 950 951 skb_put(skb, pkt_len); 952 skb->protocol = eth_type_trans(skb, ndev); 953 if (ndev->features & NETIF_F_RXCSUM) 954 ravb_rx_csum(skb); 955 napi_gro_receive(&priv->napi[q], skb); 956 stats->rx_packets++; 957 stats->rx_bytes += pkt_len; 958 } 959 960 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 961 desc = &priv->rx_ring[q][entry]; 962 } 963 964 /* Refill the RX ring buffers. */ 965 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 966 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 967 desc = &priv->rx_ring[q][entry]; 968 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 969 970 if (!priv->rx_skb[q][entry]) { 971 skb = netdev_alloc_skb(ndev, info->max_rx_len); 972 if (!skb) 973 break; /* Better luck next round. */ 974 ravb_set_buffer_align(skb); 975 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 976 le16_to_cpu(desc->ds_cc), 977 DMA_FROM_DEVICE); 978 skb_checksum_none_assert(skb); 979 /* We just set the data size to 0 for a failed mapping 980 * which should prevent DMA from happening... 981 */ 982 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 983 desc->ds_cc = cpu_to_le16(0); 984 desc->dptr = cpu_to_le32(dma_addr); 985 priv->rx_skb[q][entry] = skb; 986 } 987 /* Descriptor type must be set after all the above writes */ 988 dma_wmb(); 989 desc->die_dt = DT_FEMPTY; 990 } 991 992 *quota -= limit - (++boguscnt); 993 994 return boguscnt <= 0; 995 } 996 997 /* Packet receive function for Ethernet AVB */ 998 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 999 { 1000 struct ravb_private *priv = netdev_priv(ndev); 1001 const struct ravb_hw_info *info = priv->info; 1002 1003 return info->receive(ndev, quota, q); 1004 } 1005 1006 static void ravb_rcv_snd_disable(struct net_device *ndev) 1007 { 1008 /* Disable TX and RX */ 1009 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1010 } 1011 1012 static void ravb_rcv_snd_enable(struct net_device *ndev) 1013 { 1014 /* Enable TX and RX */ 1015 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1016 } 1017 1018 /* function for waiting dma process finished */ 1019 static int ravb_stop_dma(struct net_device *ndev) 1020 { 1021 struct ravb_private *priv = netdev_priv(ndev); 1022 const struct ravb_hw_info *info = priv->info; 1023 int error; 1024 1025 /* Wait for stopping the hardware TX process */ 1026 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1027 1028 if (error) 1029 return error; 1030 1031 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1032 0); 1033 if (error) 1034 return error; 1035 1036 /* Stop the E-MAC's RX/TX processes. */ 1037 ravb_rcv_snd_disable(ndev); 1038 1039 /* Wait for stopping the RX DMA process */ 1040 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1041 if (error) 1042 return error; 1043 1044 /* Stop AVB-DMAC process */ 1045 return ravb_config(ndev); 1046 } 1047 1048 /* E-MAC interrupt handler */ 1049 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1050 { 1051 struct ravb_private *priv = netdev_priv(ndev); 1052 u32 ecsr, psr; 1053 1054 ecsr = ravb_read(ndev, ECSR); 1055 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1056 1057 if (ecsr & ECSR_MPD) 1058 pm_wakeup_event(&priv->pdev->dev, 0); 1059 if (ecsr & ECSR_ICD) 1060 ndev->stats.tx_carrier_errors++; 1061 if (ecsr & ECSR_LCHNG) { 1062 /* Link changed */ 1063 if (priv->no_avb_link) 1064 return; 1065 psr = ravb_read(ndev, PSR); 1066 if (priv->avb_link_active_low) 1067 psr ^= PSR_LMON; 1068 if (!(psr & PSR_LMON)) { 1069 /* DIsable RX and TX */ 1070 ravb_rcv_snd_disable(ndev); 1071 } else { 1072 /* Enable RX and TX */ 1073 ravb_rcv_snd_enable(ndev); 1074 } 1075 } 1076 } 1077 1078 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1079 { 1080 struct net_device *ndev = dev_id; 1081 struct ravb_private *priv = netdev_priv(ndev); 1082 1083 spin_lock(&priv->lock); 1084 ravb_emac_interrupt_unlocked(ndev); 1085 spin_unlock(&priv->lock); 1086 return IRQ_HANDLED; 1087 } 1088 1089 /* Error interrupt handler */ 1090 static void ravb_error_interrupt(struct net_device *ndev) 1091 { 1092 struct ravb_private *priv = netdev_priv(ndev); 1093 u32 eis, ris2; 1094 1095 eis = ravb_read(ndev, EIS); 1096 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1097 if (eis & EIS_QFS) { 1098 ris2 = ravb_read(ndev, RIS2); 1099 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 1100 RIS2); 1101 1102 /* Receive Descriptor Empty int */ 1103 if (ris2 & RIS2_QFF0) 1104 priv->stats[RAVB_BE].rx_over_errors++; 1105 1106 /* Receive Descriptor Empty int */ 1107 if (ris2 & RIS2_QFF1) 1108 priv->stats[RAVB_NC].rx_over_errors++; 1109 1110 /* Receive FIFO Overflow int */ 1111 if (ris2 & RIS2_RFFF) 1112 priv->rx_fifo_errors++; 1113 } 1114 } 1115 1116 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1117 { 1118 struct ravb_private *priv = netdev_priv(ndev); 1119 const struct ravb_hw_info *info = priv->info; 1120 u32 ris0 = ravb_read(ndev, RIS0); 1121 u32 ric0 = ravb_read(ndev, RIC0); 1122 u32 tis = ravb_read(ndev, TIS); 1123 u32 tic = ravb_read(ndev, TIC); 1124 1125 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1126 if (napi_schedule_prep(&priv->napi[q])) { 1127 /* Mask RX and TX interrupts */ 1128 if (!info->multi_irqs) { 1129 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1130 ravb_write(ndev, tic & ~BIT(q), TIC); 1131 } else { 1132 ravb_write(ndev, BIT(q), RID0); 1133 ravb_write(ndev, BIT(q), TID); 1134 } 1135 __napi_schedule(&priv->napi[q]); 1136 } else { 1137 netdev_warn(ndev, 1138 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1139 ris0, ric0); 1140 netdev_warn(ndev, 1141 " tx status 0x%08x, tx mask 0x%08x.\n", 1142 tis, tic); 1143 } 1144 return true; 1145 } 1146 return false; 1147 } 1148 1149 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1150 { 1151 u32 tis = ravb_read(ndev, TIS); 1152 1153 if (tis & TIS_TFUF) { 1154 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1155 ravb_get_tx_tstamp(ndev); 1156 return true; 1157 } 1158 return false; 1159 } 1160 1161 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1162 { 1163 struct net_device *ndev = dev_id; 1164 struct ravb_private *priv = netdev_priv(ndev); 1165 const struct ravb_hw_info *info = priv->info; 1166 irqreturn_t result = IRQ_NONE; 1167 u32 iss; 1168 1169 spin_lock(&priv->lock); 1170 /* Get interrupt status */ 1171 iss = ravb_read(ndev, ISS); 1172 1173 /* Received and transmitted interrupts */ 1174 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1175 int q; 1176 1177 /* Timestamp updated */ 1178 if (ravb_timestamp_interrupt(ndev)) 1179 result = IRQ_HANDLED; 1180 1181 /* Network control and best effort queue RX/TX */ 1182 if (info->nc_queues) { 1183 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1184 if (ravb_queue_interrupt(ndev, q)) 1185 result = IRQ_HANDLED; 1186 } 1187 } else { 1188 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1189 result = IRQ_HANDLED; 1190 } 1191 } 1192 1193 /* E-MAC status summary */ 1194 if (iss & ISS_MS) { 1195 ravb_emac_interrupt_unlocked(ndev); 1196 result = IRQ_HANDLED; 1197 } 1198 1199 /* Error status summary */ 1200 if (iss & ISS_ES) { 1201 ravb_error_interrupt(ndev); 1202 result = IRQ_HANDLED; 1203 } 1204 1205 /* gPTP interrupt status summary */ 1206 if (iss & ISS_CGIS) { 1207 ravb_ptp_interrupt(ndev); 1208 result = IRQ_HANDLED; 1209 } 1210 1211 spin_unlock(&priv->lock); 1212 return result; 1213 } 1214 1215 /* Timestamp/Error/gPTP interrupt handler */ 1216 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1217 { 1218 struct net_device *ndev = dev_id; 1219 struct ravb_private *priv = netdev_priv(ndev); 1220 irqreturn_t result = IRQ_NONE; 1221 u32 iss; 1222 1223 spin_lock(&priv->lock); 1224 /* Get interrupt status */ 1225 iss = ravb_read(ndev, ISS); 1226 1227 /* Timestamp updated */ 1228 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1229 result = IRQ_HANDLED; 1230 1231 /* Error status summary */ 1232 if (iss & ISS_ES) { 1233 ravb_error_interrupt(ndev); 1234 result = IRQ_HANDLED; 1235 } 1236 1237 /* gPTP interrupt status summary */ 1238 if (iss & ISS_CGIS) { 1239 ravb_ptp_interrupt(ndev); 1240 result = IRQ_HANDLED; 1241 } 1242 1243 spin_unlock(&priv->lock); 1244 return result; 1245 } 1246 1247 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1248 { 1249 struct net_device *ndev = dev_id; 1250 struct ravb_private *priv = netdev_priv(ndev); 1251 irqreturn_t result = IRQ_NONE; 1252 1253 spin_lock(&priv->lock); 1254 1255 /* Network control/Best effort queue RX/TX */ 1256 if (ravb_queue_interrupt(ndev, q)) 1257 result = IRQ_HANDLED; 1258 1259 spin_unlock(&priv->lock); 1260 return result; 1261 } 1262 1263 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1264 { 1265 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1266 } 1267 1268 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1269 { 1270 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1271 } 1272 1273 static int ravb_poll(struct napi_struct *napi, int budget) 1274 { 1275 struct net_device *ndev = napi->dev; 1276 struct ravb_private *priv = netdev_priv(ndev); 1277 const struct ravb_hw_info *info = priv->info; 1278 bool gptp = info->gptp || info->ccc_gac; 1279 struct ravb_rx_desc *desc; 1280 unsigned long flags; 1281 int q = napi - priv->napi; 1282 int mask = BIT(q); 1283 int quota = budget; 1284 unsigned int entry; 1285 1286 if (!gptp) { 1287 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 1288 desc = &priv->gbeth_rx_ring[entry]; 1289 } 1290 /* Processing RX Descriptor Ring */ 1291 /* Clear RX interrupt */ 1292 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1293 if (gptp || desc->die_dt != DT_FEMPTY) { 1294 if (ravb_rx(ndev, "a, q)) 1295 goto out; 1296 } 1297 1298 /* Processing TX Descriptor Ring */ 1299 spin_lock_irqsave(&priv->lock, flags); 1300 /* Clear TX interrupt */ 1301 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1302 ravb_tx_free(ndev, q, true); 1303 netif_wake_subqueue(ndev, q); 1304 spin_unlock_irqrestore(&priv->lock, flags); 1305 1306 napi_complete(napi); 1307 1308 /* Re-enable RX/TX interrupts */ 1309 spin_lock_irqsave(&priv->lock, flags); 1310 if (!info->multi_irqs) { 1311 ravb_modify(ndev, RIC0, mask, mask); 1312 ravb_modify(ndev, TIC, mask, mask); 1313 } else { 1314 ravb_write(ndev, mask, RIE0); 1315 ravb_write(ndev, mask, TIE); 1316 } 1317 spin_unlock_irqrestore(&priv->lock, flags); 1318 1319 /* Receive error message handling */ 1320 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1321 if (info->nc_queues) 1322 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1323 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1324 ndev->stats.rx_over_errors = priv->rx_over_errors; 1325 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1326 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1327 out: 1328 return budget - quota; 1329 } 1330 1331 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1332 { 1333 struct ravb_private *priv = netdev_priv(ndev); 1334 1335 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1336 } 1337 1338 /* PHY state control function */ 1339 static void ravb_adjust_link(struct net_device *ndev) 1340 { 1341 struct ravb_private *priv = netdev_priv(ndev); 1342 const struct ravb_hw_info *info = priv->info; 1343 struct phy_device *phydev = ndev->phydev; 1344 bool new_state = false; 1345 unsigned long flags; 1346 1347 spin_lock_irqsave(&priv->lock, flags); 1348 1349 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1350 if (priv->no_avb_link) 1351 ravb_rcv_snd_disable(ndev); 1352 1353 if (phydev->link) { 1354 if (info->half_duplex && phydev->duplex != priv->duplex) { 1355 new_state = true; 1356 priv->duplex = phydev->duplex; 1357 ravb_set_duplex_gbeth(ndev); 1358 } 1359 1360 if (phydev->speed != priv->speed) { 1361 new_state = true; 1362 priv->speed = phydev->speed; 1363 info->set_rate(ndev); 1364 } 1365 if (!priv->link) { 1366 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1367 new_state = true; 1368 priv->link = phydev->link; 1369 } 1370 } else if (priv->link) { 1371 new_state = true; 1372 priv->link = 0; 1373 priv->speed = 0; 1374 if (info->half_duplex) 1375 priv->duplex = -1; 1376 } 1377 1378 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1379 if (priv->no_avb_link && phydev->link) 1380 ravb_rcv_snd_enable(ndev); 1381 1382 spin_unlock_irqrestore(&priv->lock, flags); 1383 1384 if (new_state && netif_msg_link(priv)) 1385 phy_print_status(phydev); 1386 } 1387 1388 static const struct soc_device_attribute r8a7795es10[] = { 1389 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1390 { /* sentinel */ } 1391 }; 1392 1393 /* PHY init function */ 1394 static int ravb_phy_init(struct net_device *ndev) 1395 { 1396 struct device_node *np = ndev->dev.parent->of_node; 1397 struct ravb_private *priv = netdev_priv(ndev); 1398 const struct ravb_hw_info *info = priv->info; 1399 struct phy_device *phydev; 1400 struct device_node *pn; 1401 phy_interface_t iface; 1402 int err; 1403 1404 priv->link = 0; 1405 priv->speed = 0; 1406 priv->duplex = -1; 1407 1408 /* Try connecting to PHY */ 1409 pn = of_parse_phandle(np, "phy-handle", 0); 1410 if (!pn) { 1411 /* In the case of a fixed PHY, the DT node associated 1412 * to the PHY is the Ethernet MAC DT node. 1413 */ 1414 if (of_phy_is_fixed_link(np)) { 1415 err = of_phy_register_fixed_link(np); 1416 if (err) 1417 return err; 1418 } 1419 pn = of_node_get(np); 1420 } 1421 1422 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1423 : priv->phy_interface; 1424 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1425 of_node_put(pn); 1426 if (!phydev) { 1427 netdev_err(ndev, "failed to connect PHY\n"); 1428 err = -ENOENT; 1429 goto err_deregister_fixed_link; 1430 } 1431 1432 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1433 * at this time. 1434 */ 1435 if (soc_device_match(r8a7795es10)) { 1436 err = phy_set_max_speed(phydev, SPEED_100); 1437 if (err) { 1438 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1439 goto err_phy_disconnect; 1440 } 1441 1442 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1443 } 1444 1445 if (!info->half_duplex) { 1446 /* 10BASE, Pause and Asym Pause is not supported */ 1447 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1448 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1449 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1450 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1451 1452 /* Half Duplex is not supported */ 1453 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1454 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1455 } 1456 1457 phy_attached_info(phydev); 1458 1459 return 0; 1460 1461 err_phy_disconnect: 1462 phy_disconnect(phydev); 1463 err_deregister_fixed_link: 1464 if (of_phy_is_fixed_link(np)) 1465 of_phy_deregister_fixed_link(np); 1466 1467 return err; 1468 } 1469 1470 /* PHY control start function */ 1471 static int ravb_phy_start(struct net_device *ndev) 1472 { 1473 int error; 1474 1475 error = ravb_phy_init(ndev); 1476 if (error) 1477 return error; 1478 1479 phy_start(ndev->phydev); 1480 1481 return 0; 1482 } 1483 1484 static u32 ravb_get_msglevel(struct net_device *ndev) 1485 { 1486 struct ravb_private *priv = netdev_priv(ndev); 1487 1488 return priv->msg_enable; 1489 } 1490 1491 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1492 { 1493 struct ravb_private *priv = netdev_priv(ndev); 1494 1495 priv->msg_enable = value; 1496 } 1497 1498 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1499 "rx_queue_0_current", 1500 "tx_queue_0_current", 1501 "rx_queue_0_dirty", 1502 "tx_queue_0_dirty", 1503 "rx_queue_0_packets", 1504 "tx_queue_0_packets", 1505 "rx_queue_0_bytes", 1506 "tx_queue_0_bytes", 1507 "rx_queue_0_mcast_packets", 1508 "rx_queue_0_errors", 1509 "rx_queue_0_crc_errors", 1510 "rx_queue_0_frame_errors", 1511 "rx_queue_0_length_errors", 1512 "rx_queue_0_csum_offload_errors", 1513 "rx_queue_0_over_errors", 1514 }; 1515 1516 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1517 "rx_queue_0_current", 1518 "tx_queue_0_current", 1519 "rx_queue_0_dirty", 1520 "tx_queue_0_dirty", 1521 "rx_queue_0_packets", 1522 "tx_queue_0_packets", 1523 "rx_queue_0_bytes", 1524 "tx_queue_0_bytes", 1525 "rx_queue_0_mcast_packets", 1526 "rx_queue_0_errors", 1527 "rx_queue_0_crc_errors", 1528 "rx_queue_0_frame_errors", 1529 "rx_queue_0_length_errors", 1530 "rx_queue_0_missed_errors", 1531 "rx_queue_0_over_errors", 1532 1533 "rx_queue_1_current", 1534 "tx_queue_1_current", 1535 "rx_queue_1_dirty", 1536 "tx_queue_1_dirty", 1537 "rx_queue_1_packets", 1538 "tx_queue_1_packets", 1539 "rx_queue_1_bytes", 1540 "tx_queue_1_bytes", 1541 "rx_queue_1_mcast_packets", 1542 "rx_queue_1_errors", 1543 "rx_queue_1_crc_errors", 1544 "rx_queue_1_frame_errors", 1545 "rx_queue_1_length_errors", 1546 "rx_queue_1_missed_errors", 1547 "rx_queue_1_over_errors", 1548 }; 1549 1550 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1551 { 1552 struct ravb_private *priv = netdev_priv(netdev); 1553 const struct ravb_hw_info *info = priv->info; 1554 1555 switch (sset) { 1556 case ETH_SS_STATS: 1557 return info->stats_len; 1558 default: 1559 return -EOPNOTSUPP; 1560 } 1561 } 1562 1563 static void ravb_get_ethtool_stats(struct net_device *ndev, 1564 struct ethtool_stats *estats, u64 *data) 1565 { 1566 struct ravb_private *priv = netdev_priv(ndev); 1567 const struct ravb_hw_info *info = priv->info; 1568 int num_rx_q; 1569 int i = 0; 1570 int q; 1571 1572 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1573 /* Device-specific stats */ 1574 for (q = RAVB_BE; q < num_rx_q; q++) { 1575 struct net_device_stats *stats = &priv->stats[q]; 1576 1577 data[i++] = priv->cur_rx[q]; 1578 data[i++] = priv->cur_tx[q]; 1579 data[i++] = priv->dirty_rx[q]; 1580 data[i++] = priv->dirty_tx[q]; 1581 data[i++] = stats->rx_packets; 1582 data[i++] = stats->tx_packets; 1583 data[i++] = stats->rx_bytes; 1584 data[i++] = stats->tx_bytes; 1585 data[i++] = stats->multicast; 1586 data[i++] = stats->rx_errors; 1587 data[i++] = stats->rx_crc_errors; 1588 data[i++] = stats->rx_frame_errors; 1589 data[i++] = stats->rx_length_errors; 1590 data[i++] = stats->rx_missed_errors; 1591 data[i++] = stats->rx_over_errors; 1592 } 1593 } 1594 1595 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1596 { 1597 struct ravb_private *priv = netdev_priv(ndev); 1598 const struct ravb_hw_info *info = priv->info; 1599 1600 switch (stringset) { 1601 case ETH_SS_STATS: 1602 memcpy(data, info->gstrings_stats, info->gstrings_size); 1603 break; 1604 } 1605 } 1606 1607 static void ravb_get_ringparam(struct net_device *ndev, 1608 struct ethtool_ringparam *ring) 1609 { 1610 struct ravb_private *priv = netdev_priv(ndev); 1611 1612 ring->rx_max_pending = BE_RX_RING_MAX; 1613 ring->tx_max_pending = BE_TX_RING_MAX; 1614 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1615 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1616 } 1617 1618 static int ravb_set_ringparam(struct net_device *ndev, 1619 struct ethtool_ringparam *ring) 1620 { 1621 struct ravb_private *priv = netdev_priv(ndev); 1622 const struct ravb_hw_info *info = priv->info; 1623 int error; 1624 1625 if (ring->tx_pending > BE_TX_RING_MAX || 1626 ring->rx_pending > BE_RX_RING_MAX || 1627 ring->tx_pending < BE_TX_RING_MIN || 1628 ring->rx_pending < BE_RX_RING_MIN) 1629 return -EINVAL; 1630 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1631 return -EINVAL; 1632 1633 if (netif_running(ndev)) { 1634 netif_device_detach(ndev); 1635 /* Stop PTP Clock driver */ 1636 if (info->gptp) 1637 ravb_ptp_stop(ndev); 1638 /* Wait for DMA stopping */ 1639 error = ravb_stop_dma(ndev); 1640 if (error) { 1641 netdev_err(ndev, 1642 "cannot set ringparam! Any AVB processes are still running?\n"); 1643 return error; 1644 } 1645 synchronize_irq(ndev->irq); 1646 1647 /* Free all the skb's in the RX queue and the DMA buffers. */ 1648 ravb_ring_free(ndev, RAVB_BE); 1649 if (info->nc_queues) 1650 ravb_ring_free(ndev, RAVB_NC); 1651 } 1652 1653 /* Set new parameters */ 1654 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1655 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1656 1657 if (netif_running(ndev)) { 1658 error = ravb_dmac_init(ndev); 1659 if (error) { 1660 netdev_err(ndev, 1661 "%s: ravb_dmac_init() failed, error %d\n", 1662 __func__, error); 1663 return error; 1664 } 1665 1666 ravb_emac_init(ndev); 1667 1668 /* Initialise PTP Clock driver */ 1669 if (info->gptp) 1670 ravb_ptp_init(ndev, priv->pdev); 1671 1672 netif_device_attach(ndev); 1673 } 1674 1675 return 0; 1676 } 1677 1678 static int ravb_get_ts_info(struct net_device *ndev, 1679 struct ethtool_ts_info *info) 1680 { 1681 struct ravb_private *priv = netdev_priv(ndev); 1682 const struct ravb_hw_info *hw_info = priv->info; 1683 1684 info->so_timestamping = 1685 SOF_TIMESTAMPING_TX_SOFTWARE | 1686 SOF_TIMESTAMPING_RX_SOFTWARE | 1687 SOF_TIMESTAMPING_SOFTWARE | 1688 SOF_TIMESTAMPING_TX_HARDWARE | 1689 SOF_TIMESTAMPING_RX_HARDWARE | 1690 SOF_TIMESTAMPING_RAW_HARDWARE; 1691 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1692 info->rx_filters = 1693 (1 << HWTSTAMP_FILTER_NONE) | 1694 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1695 (1 << HWTSTAMP_FILTER_ALL); 1696 if (hw_info->gptp || hw_info->ccc_gac) 1697 info->phc_index = ptp_clock_index(priv->ptp.clock); 1698 1699 return 0; 1700 } 1701 1702 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1703 { 1704 struct ravb_private *priv = netdev_priv(ndev); 1705 1706 wol->supported = WAKE_MAGIC; 1707 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1708 } 1709 1710 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1711 { 1712 struct ravb_private *priv = netdev_priv(ndev); 1713 const struct ravb_hw_info *info = priv->info; 1714 1715 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1716 return -EOPNOTSUPP; 1717 1718 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1719 1720 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1721 1722 return 0; 1723 } 1724 1725 static const struct ethtool_ops ravb_ethtool_ops = { 1726 .nway_reset = phy_ethtool_nway_reset, 1727 .get_msglevel = ravb_get_msglevel, 1728 .set_msglevel = ravb_set_msglevel, 1729 .get_link = ethtool_op_get_link, 1730 .get_strings = ravb_get_strings, 1731 .get_ethtool_stats = ravb_get_ethtool_stats, 1732 .get_sset_count = ravb_get_sset_count, 1733 .get_ringparam = ravb_get_ringparam, 1734 .set_ringparam = ravb_set_ringparam, 1735 .get_ts_info = ravb_get_ts_info, 1736 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1737 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1738 .get_wol = ravb_get_wol, 1739 .set_wol = ravb_set_wol, 1740 }; 1741 1742 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1743 struct net_device *ndev, struct device *dev, 1744 const char *ch) 1745 { 1746 char *name; 1747 int error; 1748 1749 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1750 if (!name) 1751 return -ENOMEM; 1752 error = request_irq(irq, handler, 0, name, ndev); 1753 if (error) 1754 netdev_err(ndev, "cannot request IRQ %s\n", name); 1755 1756 return error; 1757 } 1758 1759 /* Network device open function for Ethernet AVB */ 1760 static int ravb_open(struct net_device *ndev) 1761 { 1762 struct ravb_private *priv = netdev_priv(ndev); 1763 const struct ravb_hw_info *info = priv->info; 1764 struct platform_device *pdev = priv->pdev; 1765 struct device *dev = &pdev->dev; 1766 int error; 1767 1768 napi_enable(&priv->napi[RAVB_BE]); 1769 if (info->nc_queues) 1770 napi_enable(&priv->napi[RAVB_NC]); 1771 1772 if (!info->multi_irqs) { 1773 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1774 ndev->name, ndev); 1775 if (error) { 1776 netdev_err(ndev, "cannot request IRQ\n"); 1777 goto out_napi_off; 1778 } 1779 } else { 1780 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1781 dev, "ch22:multi"); 1782 if (error) 1783 goto out_napi_off; 1784 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1785 dev, "ch24:emac"); 1786 if (error) 1787 goto out_free_irq; 1788 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1789 ndev, dev, "ch0:rx_be"); 1790 if (error) 1791 goto out_free_irq_emac; 1792 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1793 ndev, dev, "ch18:tx_be"); 1794 if (error) 1795 goto out_free_irq_be_rx; 1796 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1797 ndev, dev, "ch1:rx_nc"); 1798 if (error) 1799 goto out_free_irq_be_tx; 1800 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1801 ndev, dev, "ch19:tx_nc"); 1802 if (error) 1803 goto out_free_irq_nc_rx; 1804 } 1805 1806 /* Device init */ 1807 error = ravb_dmac_init(ndev); 1808 if (error) 1809 goto out_free_irq_nc_tx; 1810 ravb_emac_init(ndev); 1811 1812 /* Initialise PTP Clock driver */ 1813 if (info->gptp) 1814 ravb_ptp_init(ndev, priv->pdev); 1815 1816 netif_tx_start_all_queues(ndev); 1817 1818 /* PHY control start */ 1819 error = ravb_phy_start(ndev); 1820 if (error) 1821 goto out_ptp_stop; 1822 1823 return 0; 1824 1825 out_ptp_stop: 1826 /* Stop PTP Clock driver */ 1827 if (info->gptp) 1828 ravb_ptp_stop(ndev); 1829 out_free_irq_nc_tx: 1830 if (!info->multi_irqs) 1831 goto out_free_irq; 1832 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1833 out_free_irq_nc_rx: 1834 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1835 out_free_irq_be_tx: 1836 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1837 out_free_irq_be_rx: 1838 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1839 out_free_irq_emac: 1840 free_irq(priv->emac_irq, ndev); 1841 out_free_irq: 1842 free_irq(ndev->irq, ndev); 1843 out_napi_off: 1844 if (info->nc_queues) 1845 napi_disable(&priv->napi[RAVB_NC]); 1846 napi_disable(&priv->napi[RAVB_BE]); 1847 return error; 1848 } 1849 1850 /* Timeout function for Ethernet AVB */ 1851 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1852 { 1853 struct ravb_private *priv = netdev_priv(ndev); 1854 1855 netif_err(priv, tx_err, ndev, 1856 "transmit timed out, status %08x, resetting...\n", 1857 ravb_read(ndev, ISS)); 1858 1859 /* tx_errors count up */ 1860 ndev->stats.tx_errors++; 1861 1862 schedule_work(&priv->work); 1863 } 1864 1865 static void ravb_tx_timeout_work(struct work_struct *work) 1866 { 1867 struct ravb_private *priv = container_of(work, struct ravb_private, 1868 work); 1869 const struct ravb_hw_info *info = priv->info; 1870 struct net_device *ndev = priv->ndev; 1871 int error; 1872 1873 netif_tx_stop_all_queues(ndev); 1874 1875 /* Stop PTP Clock driver */ 1876 if (info->gptp) 1877 ravb_ptp_stop(ndev); 1878 1879 /* Wait for DMA stopping */ 1880 if (ravb_stop_dma(ndev)) { 1881 /* If ravb_stop_dma() fails, the hardware is still operating 1882 * for TX and/or RX. So, this should not call the following 1883 * functions because ravb_dmac_init() is possible to fail too. 1884 * Also, this should not retry ravb_stop_dma() again and again 1885 * here because it's possible to wait forever. So, this just 1886 * re-enables the TX and RX and skip the following 1887 * re-initialization procedure. 1888 */ 1889 ravb_rcv_snd_enable(ndev); 1890 goto out; 1891 } 1892 1893 ravb_ring_free(ndev, RAVB_BE); 1894 if (info->nc_queues) 1895 ravb_ring_free(ndev, RAVB_NC); 1896 1897 /* Device init */ 1898 error = ravb_dmac_init(ndev); 1899 if (error) { 1900 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1901 * should return here to avoid re-enabling the TX and RX in 1902 * ravb_emac_init(). 1903 */ 1904 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1905 __func__, error); 1906 return; 1907 } 1908 ravb_emac_init(ndev); 1909 1910 out: 1911 /* Initialise PTP Clock driver */ 1912 if (info->gptp) 1913 ravb_ptp_init(ndev, priv->pdev); 1914 1915 netif_tx_start_all_queues(ndev); 1916 } 1917 1918 /* Packet transmit function for Ethernet AVB */ 1919 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1920 { 1921 struct ravb_private *priv = netdev_priv(ndev); 1922 const struct ravb_hw_info *info = priv->info; 1923 unsigned int num_tx_desc = priv->num_tx_desc; 1924 u16 q = skb_get_queue_mapping(skb); 1925 struct ravb_tstamp_skb *ts_skb; 1926 struct ravb_tx_desc *desc; 1927 unsigned long flags; 1928 u32 dma_addr; 1929 void *buffer; 1930 u32 entry; 1931 u32 len; 1932 1933 spin_lock_irqsave(&priv->lock, flags); 1934 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1935 num_tx_desc) { 1936 netif_err(priv, tx_queued, ndev, 1937 "still transmitting with the full ring!\n"); 1938 netif_stop_subqueue(ndev, q); 1939 spin_unlock_irqrestore(&priv->lock, flags); 1940 return NETDEV_TX_BUSY; 1941 } 1942 1943 if (skb_put_padto(skb, ETH_ZLEN)) 1944 goto exit; 1945 1946 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1947 priv->tx_skb[q][entry / num_tx_desc] = skb; 1948 1949 if (num_tx_desc > 1) { 1950 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1951 entry / num_tx_desc * DPTR_ALIGN; 1952 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1953 1954 /* Zero length DMA descriptors are problematic as they seem 1955 * to terminate DMA transfers. Avoid them by simply using a 1956 * length of DPTR_ALIGN (4) when skb data is aligned to 1957 * DPTR_ALIGN. 1958 * 1959 * As skb is guaranteed to have at least ETH_ZLEN (60) 1960 * bytes of data by the call to skb_put_padto() above this 1961 * is safe with respect to both the length of the first DMA 1962 * descriptor (len) overflowing the available data and the 1963 * length of the second DMA descriptor (skb->len - len) 1964 * being negative. 1965 */ 1966 if (len == 0) 1967 len = DPTR_ALIGN; 1968 1969 memcpy(buffer, skb->data, len); 1970 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1971 DMA_TO_DEVICE); 1972 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1973 goto drop; 1974 1975 desc = &priv->tx_ring[q][entry]; 1976 desc->ds_tagl = cpu_to_le16(len); 1977 desc->dptr = cpu_to_le32(dma_addr); 1978 1979 buffer = skb->data + len; 1980 len = skb->len - len; 1981 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1982 DMA_TO_DEVICE); 1983 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1984 goto unmap; 1985 1986 desc++; 1987 } else { 1988 desc = &priv->tx_ring[q][entry]; 1989 len = skb->len; 1990 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1991 DMA_TO_DEVICE); 1992 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1993 goto drop; 1994 } 1995 desc->ds_tagl = cpu_to_le16(len); 1996 desc->dptr = cpu_to_le32(dma_addr); 1997 1998 /* TX timestamp required */ 1999 if (info->gptp || info->ccc_gac) { 2000 if (q == RAVB_NC) { 2001 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2002 if (!ts_skb) { 2003 if (num_tx_desc > 1) { 2004 desc--; 2005 dma_unmap_single(ndev->dev.parent, dma_addr, 2006 len, DMA_TO_DEVICE); 2007 } 2008 goto unmap; 2009 } 2010 ts_skb->skb = skb_get(skb); 2011 ts_skb->tag = priv->ts_skb_tag++; 2012 priv->ts_skb_tag &= 0x3ff; 2013 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2014 2015 /* TAG and timestamp required flag */ 2016 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2017 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2018 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2019 } 2020 2021 skb_tx_timestamp(skb); 2022 } 2023 /* Descriptor type must be set after all the above writes */ 2024 dma_wmb(); 2025 if (num_tx_desc > 1) { 2026 desc->die_dt = DT_FEND; 2027 desc--; 2028 desc->die_dt = DT_FSTART; 2029 } else { 2030 desc->die_dt = DT_FSINGLE; 2031 } 2032 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2033 2034 priv->cur_tx[q] += num_tx_desc; 2035 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2036 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2037 !ravb_tx_free(ndev, q, true)) 2038 netif_stop_subqueue(ndev, q); 2039 2040 exit: 2041 spin_unlock_irqrestore(&priv->lock, flags); 2042 return NETDEV_TX_OK; 2043 2044 unmap: 2045 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2046 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2047 drop: 2048 dev_kfree_skb_any(skb); 2049 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2050 goto exit; 2051 } 2052 2053 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2054 struct net_device *sb_dev) 2055 { 2056 /* If skb needs TX timestamp, it is handled in network control queue */ 2057 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2058 RAVB_BE; 2059 2060 } 2061 2062 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2063 { 2064 struct ravb_private *priv = netdev_priv(ndev); 2065 const struct ravb_hw_info *info = priv->info; 2066 struct net_device_stats *nstats, *stats0, *stats1; 2067 2068 nstats = &ndev->stats; 2069 stats0 = &priv->stats[RAVB_BE]; 2070 2071 if (info->tx_counters) { 2072 nstats->tx_dropped += ravb_read(ndev, TROCR); 2073 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2074 } 2075 2076 if (info->carrier_counters) { 2077 nstats->collisions += ravb_read(ndev, CXR41); 2078 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2079 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2080 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2081 } 2082 2083 nstats->rx_packets = stats0->rx_packets; 2084 nstats->tx_packets = stats0->tx_packets; 2085 nstats->rx_bytes = stats0->rx_bytes; 2086 nstats->tx_bytes = stats0->tx_bytes; 2087 nstats->multicast = stats0->multicast; 2088 nstats->rx_errors = stats0->rx_errors; 2089 nstats->rx_crc_errors = stats0->rx_crc_errors; 2090 nstats->rx_frame_errors = stats0->rx_frame_errors; 2091 nstats->rx_length_errors = stats0->rx_length_errors; 2092 nstats->rx_missed_errors = stats0->rx_missed_errors; 2093 nstats->rx_over_errors = stats0->rx_over_errors; 2094 if (info->nc_queues) { 2095 stats1 = &priv->stats[RAVB_NC]; 2096 2097 nstats->rx_packets += stats1->rx_packets; 2098 nstats->tx_packets += stats1->tx_packets; 2099 nstats->rx_bytes += stats1->rx_bytes; 2100 nstats->tx_bytes += stats1->tx_bytes; 2101 nstats->multicast += stats1->multicast; 2102 nstats->rx_errors += stats1->rx_errors; 2103 nstats->rx_crc_errors += stats1->rx_crc_errors; 2104 nstats->rx_frame_errors += stats1->rx_frame_errors; 2105 nstats->rx_length_errors += stats1->rx_length_errors; 2106 nstats->rx_missed_errors += stats1->rx_missed_errors; 2107 nstats->rx_over_errors += stats1->rx_over_errors; 2108 } 2109 2110 return nstats; 2111 } 2112 2113 /* Update promiscuous bit */ 2114 static void ravb_set_rx_mode(struct net_device *ndev) 2115 { 2116 struct ravb_private *priv = netdev_priv(ndev); 2117 unsigned long flags; 2118 2119 spin_lock_irqsave(&priv->lock, flags); 2120 ravb_modify(ndev, ECMR, ECMR_PRM, 2121 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2122 spin_unlock_irqrestore(&priv->lock, flags); 2123 } 2124 2125 /* Device close function for Ethernet AVB */ 2126 static int ravb_close(struct net_device *ndev) 2127 { 2128 struct device_node *np = ndev->dev.parent->of_node; 2129 struct ravb_private *priv = netdev_priv(ndev); 2130 const struct ravb_hw_info *info = priv->info; 2131 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2132 2133 netif_tx_stop_all_queues(ndev); 2134 2135 /* Disable interrupts by clearing the interrupt masks. */ 2136 ravb_write(ndev, 0, RIC0); 2137 ravb_write(ndev, 0, RIC2); 2138 ravb_write(ndev, 0, TIC); 2139 2140 /* Stop PTP Clock driver */ 2141 if (info->gptp) 2142 ravb_ptp_stop(ndev); 2143 2144 /* Set the config mode to stop the AVB-DMAC's processes */ 2145 if (ravb_stop_dma(ndev) < 0) 2146 netdev_err(ndev, 2147 "device will be stopped after h/w processes are done.\n"); 2148 2149 /* Clear the timestamp list */ 2150 if (info->gptp || info->ccc_gac) { 2151 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2152 list_del(&ts_skb->list); 2153 kfree_skb(ts_skb->skb); 2154 kfree(ts_skb); 2155 } 2156 } 2157 2158 /* PHY disconnect */ 2159 if (ndev->phydev) { 2160 phy_stop(ndev->phydev); 2161 phy_disconnect(ndev->phydev); 2162 if (of_phy_is_fixed_link(np)) 2163 of_phy_deregister_fixed_link(np); 2164 } 2165 2166 if (info->multi_irqs) { 2167 free_irq(priv->tx_irqs[RAVB_NC], ndev); 2168 free_irq(priv->rx_irqs[RAVB_NC], ndev); 2169 free_irq(priv->tx_irqs[RAVB_BE], ndev); 2170 free_irq(priv->rx_irqs[RAVB_BE], ndev); 2171 free_irq(priv->emac_irq, ndev); 2172 } 2173 free_irq(ndev->irq, ndev); 2174 2175 if (info->nc_queues) 2176 napi_disable(&priv->napi[RAVB_NC]); 2177 napi_disable(&priv->napi[RAVB_BE]); 2178 2179 /* Free all the skb's in the RX queue and the DMA buffers. */ 2180 ravb_ring_free(ndev, RAVB_BE); 2181 if (info->nc_queues) 2182 ravb_ring_free(ndev, RAVB_NC); 2183 2184 return 0; 2185 } 2186 2187 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2188 { 2189 struct ravb_private *priv = netdev_priv(ndev); 2190 struct hwtstamp_config config; 2191 2192 config.flags = 0; 2193 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2194 HWTSTAMP_TX_OFF; 2195 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2196 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2197 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2198 break; 2199 case RAVB_RXTSTAMP_TYPE_ALL: 2200 config.rx_filter = HWTSTAMP_FILTER_ALL; 2201 break; 2202 default: 2203 config.rx_filter = HWTSTAMP_FILTER_NONE; 2204 } 2205 2206 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2207 -EFAULT : 0; 2208 } 2209 2210 /* Control hardware time stamping */ 2211 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2212 { 2213 struct ravb_private *priv = netdev_priv(ndev); 2214 struct hwtstamp_config config; 2215 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2216 u32 tstamp_tx_ctrl; 2217 2218 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2219 return -EFAULT; 2220 2221 /* Reserved for future extensions */ 2222 if (config.flags) 2223 return -EINVAL; 2224 2225 switch (config.tx_type) { 2226 case HWTSTAMP_TX_OFF: 2227 tstamp_tx_ctrl = 0; 2228 break; 2229 case HWTSTAMP_TX_ON: 2230 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2231 break; 2232 default: 2233 return -ERANGE; 2234 } 2235 2236 switch (config.rx_filter) { 2237 case HWTSTAMP_FILTER_NONE: 2238 tstamp_rx_ctrl = 0; 2239 break; 2240 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2241 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2242 break; 2243 default: 2244 config.rx_filter = HWTSTAMP_FILTER_ALL; 2245 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2246 } 2247 2248 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2249 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2250 2251 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2252 -EFAULT : 0; 2253 } 2254 2255 /* ioctl to device function */ 2256 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2257 { 2258 struct phy_device *phydev = ndev->phydev; 2259 2260 if (!netif_running(ndev)) 2261 return -EINVAL; 2262 2263 if (!phydev) 2264 return -ENODEV; 2265 2266 switch (cmd) { 2267 case SIOCGHWTSTAMP: 2268 return ravb_hwtstamp_get(ndev, req); 2269 case SIOCSHWTSTAMP: 2270 return ravb_hwtstamp_set(ndev, req); 2271 } 2272 2273 return phy_mii_ioctl(phydev, req, cmd); 2274 } 2275 2276 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2277 { 2278 struct ravb_private *priv = netdev_priv(ndev); 2279 2280 ndev->mtu = new_mtu; 2281 2282 if (netif_running(ndev)) { 2283 synchronize_irq(priv->emac_irq); 2284 ravb_emac_init(ndev); 2285 } 2286 2287 netdev_update_features(ndev); 2288 2289 return 0; 2290 } 2291 2292 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2293 { 2294 struct ravb_private *priv = netdev_priv(ndev); 2295 unsigned long flags; 2296 2297 spin_lock_irqsave(&priv->lock, flags); 2298 2299 /* Disable TX and RX */ 2300 ravb_rcv_snd_disable(ndev); 2301 2302 /* Modify RX Checksum setting */ 2303 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2304 2305 /* Enable TX and RX */ 2306 ravb_rcv_snd_enable(ndev); 2307 2308 spin_unlock_irqrestore(&priv->lock, flags); 2309 } 2310 2311 static int ravb_set_features_gbeth(struct net_device *ndev, 2312 netdev_features_t features) 2313 { 2314 /* Place holder */ 2315 return 0; 2316 } 2317 2318 static int ravb_set_features_rcar(struct net_device *ndev, 2319 netdev_features_t features) 2320 { 2321 netdev_features_t changed = ndev->features ^ features; 2322 2323 if (changed & NETIF_F_RXCSUM) 2324 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2325 2326 ndev->features = features; 2327 2328 return 0; 2329 } 2330 2331 static int ravb_set_features(struct net_device *ndev, 2332 netdev_features_t features) 2333 { 2334 struct ravb_private *priv = netdev_priv(ndev); 2335 const struct ravb_hw_info *info = priv->info; 2336 2337 return info->set_feature(ndev, features); 2338 } 2339 2340 static const struct net_device_ops ravb_netdev_ops = { 2341 .ndo_open = ravb_open, 2342 .ndo_stop = ravb_close, 2343 .ndo_start_xmit = ravb_start_xmit, 2344 .ndo_select_queue = ravb_select_queue, 2345 .ndo_get_stats = ravb_get_stats, 2346 .ndo_set_rx_mode = ravb_set_rx_mode, 2347 .ndo_tx_timeout = ravb_tx_timeout, 2348 .ndo_eth_ioctl = ravb_do_ioctl, 2349 .ndo_change_mtu = ravb_change_mtu, 2350 .ndo_validate_addr = eth_validate_addr, 2351 .ndo_set_mac_address = eth_mac_addr, 2352 .ndo_set_features = ravb_set_features, 2353 }; 2354 2355 /* MDIO bus init function */ 2356 static int ravb_mdio_init(struct ravb_private *priv) 2357 { 2358 struct platform_device *pdev = priv->pdev; 2359 struct device *dev = &pdev->dev; 2360 int error; 2361 2362 /* Bitbang init */ 2363 priv->mdiobb.ops = &bb_ops; 2364 2365 /* MII controller setting */ 2366 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2367 if (!priv->mii_bus) 2368 return -ENOMEM; 2369 2370 /* Hook up MII support for ethtool */ 2371 priv->mii_bus->name = "ravb_mii"; 2372 priv->mii_bus->parent = dev; 2373 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2374 pdev->name, pdev->id); 2375 2376 /* Register MDIO bus */ 2377 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2378 if (error) 2379 goto out_free_bus; 2380 2381 return 0; 2382 2383 out_free_bus: 2384 free_mdio_bitbang(priv->mii_bus); 2385 return error; 2386 } 2387 2388 /* MDIO bus release function */ 2389 static int ravb_mdio_release(struct ravb_private *priv) 2390 { 2391 /* Unregister mdio bus */ 2392 mdiobus_unregister(priv->mii_bus); 2393 2394 /* Free bitbang info */ 2395 free_mdio_bitbang(priv->mii_bus); 2396 2397 return 0; 2398 } 2399 2400 static const struct ravb_hw_info ravb_gen3_hw_info = { 2401 .rx_ring_free = ravb_rx_ring_free_rcar, 2402 .rx_ring_format = ravb_rx_ring_format_rcar, 2403 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2404 .receive = ravb_rx_rcar, 2405 .set_rate = ravb_set_rate_rcar, 2406 .set_feature = ravb_set_features_rcar, 2407 .dmac_init = ravb_dmac_init_rcar, 2408 .emac_init = ravb_emac_init_rcar, 2409 .gstrings_stats = ravb_gstrings_stats, 2410 .gstrings_size = sizeof(ravb_gstrings_stats), 2411 .net_hw_features = NETIF_F_RXCSUM, 2412 .net_features = NETIF_F_RXCSUM, 2413 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2414 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2415 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2416 .rx_max_buf_size = SZ_2K, 2417 .internal_delay = 1, 2418 .tx_counters = 1, 2419 .multi_irqs = 1, 2420 .ccc_gac = 1, 2421 .nc_queues = 1, 2422 .magic_pkt = 1, 2423 }; 2424 2425 static const struct ravb_hw_info ravb_gen2_hw_info = { 2426 .rx_ring_free = ravb_rx_ring_free_rcar, 2427 .rx_ring_format = ravb_rx_ring_format_rcar, 2428 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2429 .receive = ravb_rx_rcar, 2430 .set_rate = ravb_set_rate_rcar, 2431 .set_feature = ravb_set_features_rcar, 2432 .dmac_init = ravb_dmac_init_rcar, 2433 .emac_init = ravb_emac_init_rcar, 2434 .gstrings_stats = ravb_gstrings_stats, 2435 .gstrings_size = sizeof(ravb_gstrings_stats), 2436 .net_hw_features = NETIF_F_RXCSUM, 2437 .net_features = NETIF_F_RXCSUM, 2438 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2439 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2440 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2441 .rx_max_buf_size = SZ_2K, 2442 .aligned_tx = 1, 2443 .gptp = 1, 2444 .nc_queues = 1, 2445 .magic_pkt = 1, 2446 }; 2447 2448 static const struct ravb_hw_info gbeth_hw_info = { 2449 .rx_ring_free = ravb_rx_ring_free_gbeth, 2450 .rx_ring_format = ravb_rx_ring_format_gbeth, 2451 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2452 .receive = ravb_rx_gbeth, 2453 .set_rate = ravb_set_rate_gbeth, 2454 .set_feature = ravb_set_features_gbeth, 2455 .dmac_init = ravb_dmac_init_gbeth, 2456 .emac_init = ravb_emac_init_gbeth, 2457 .gstrings_stats = ravb_gstrings_stats_gbeth, 2458 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2459 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2460 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), 2461 .tccr_mask = TCCR_TSRQ0, 2462 .rx_max_buf_size = SZ_8K, 2463 .aligned_tx = 1, 2464 .tx_counters = 1, 2465 .carrier_counters = 1, 2466 .half_duplex = 1, 2467 }; 2468 2469 static const struct of_device_id ravb_match_table[] = { 2470 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2471 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2472 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2473 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2474 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2475 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2476 { } 2477 }; 2478 MODULE_DEVICE_TABLE(of, ravb_match_table); 2479 2480 static int ravb_set_gti(struct net_device *ndev) 2481 { 2482 struct ravb_private *priv = netdev_priv(ndev); 2483 struct device *dev = ndev->dev.parent; 2484 unsigned long rate; 2485 uint64_t inc; 2486 2487 rate = clk_get_rate(priv->clk); 2488 if (!rate) 2489 return -EINVAL; 2490 2491 inc = 1000000000ULL << 20; 2492 do_div(inc, rate); 2493 2494 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 2495 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 2496 inc, GTI_TIV_MIN, GTI_TIV_MAX); 2497 return -EINVAL; 2498 } 2499 2500 ravb_write(ndev, inc, GTI); 2501 2502 return 0; 2503 } 2504 2505 static void ravb_set_config_mode(struct net_device *ndev) 2506 { 2507 struct ravb_private *priv = netdev_priv(ndev); 2508 const struct ravb_hw_info *info = priv->info; 2509 2510 if (info->gptp) { 2511 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2512 /* Set CSEL value */ 2513 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 2514 } else if (info->ccc_gac) { 2515 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 2516 CCC_GAC | CCC_CSEL_HPB); 2517 } else { 2518 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2519 } 2520 } 2521 2522 /* Set tx and rx clock internal delay modes */ 2523 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2524 { 2525 struct ravb_private *priv = netdev_priv(ndev); 2526 bool explicit_delay = false; 2527 u32 delay; 2528 2529 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2530 /* Valid values are 0 and 1800, according to DT bindings */ 2531 priv->rxcidm = !!delay; 2532 explicit_delay = true; 2533 } 2534 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2535 /* Valid values are 0 and 2000, according to DT bindings */ 2536 priv->txcidm = !!delay; 2537 explicit_delay = true; 2538 } 2539 2540 if (explicit_delay) 2541 return; 2542 2543 /* Fall back to legacy rgmii-*id behavior */ 2544 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2545 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2546 priv->rxcidm = 1; 2547 priv->rgmii_override = 1; 2548 } 2549 2550 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2551 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2552 priv->txcidm = 1; 2553 priv->rgmii_override = 1; 2554 } 2555 } 2556 2557 static void ravb_set_delay_mode(struct net_device *ndev) 2558 { 2559 struct ravb_private *priv = netdev_priv(ndev); 2560 u32 set = 0; 2561 2562 if (priv->rxcidm) 2563 set |= APSR_RDM; 2564 if (priv->txcidm) 2565 set |= APSR_TDM; 2566 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2567 } 2568 2569 static int ravb_probe(struct platform_device *pdev) 2570 { 2571 struct device_node *np = pdev->dev.of_node; 2572 const struct ravb_hw_info *info; 2573 struct reset_control *rstc; 2574 struct ravb_private *priv; 2575 struct net_device *ndev; 2576 int error, irq, q; 2577 struct resource *res; 2578 int i; 2579 2580 if (!np) { 2581 dev_err(&pdev->dev, 2582 "this driver is required to be instantiated from device tree\n"); 2583 return -EINVAL; 2584 } 2585 2586 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2587 if (IS_ERR(rstc)) 2588 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2589 "failed to get cpg reset\n"); 2590 2591 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2592 NUM_TX_QUEUE, NUM_RX_QUEUE); 2593 if (!ndev) 2594 return -ENOMEM; 2595 2596 info = of_device_get_match_data(&pdev->dev); 2597 2598 ndev->features = info->net_features; 2599 ndev->hw_features = info->net_hw_features; 2600 2601 reset_control_deassert(rstc); 2602 pm_runtime_enable(&pdev->dev); 2603 pm_runtime_get_sync(&pdev->dev); 2604 2605 if (info->multi_irqs) 2606 irq = platform_get_irq_byname(pdev, "ch22"); 2607 else 2608 irq = platform_get_irq(pdev, 0); 2609 if (irq < 0) { 2610 error = irq; 2611 goto out_release; 2612 } 2613 ndev->irq = irq; 2614 2615 SET_NETDEV_DEV(ndev, &pdev->dev); 2616 2617 priv = netdev_priv(ndev); 2618 priv->info = info; 2619 priv->rstc = rstc; 2620 priv->ndev = ndev; 2621 priv->pdev = pdev; 2622 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2623 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2624 if (info->nc_queues) { 2625 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2626 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2627 } 2628 2629 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2630 if (IS_ERR(priv->addr)) { 2631 error = PTR_ERR(priv->addr); 2632 goto out_release; 2633 } 2634 2635 /* The Ether-specific entries in the device structure. */ 2636 ndev->base_addr = res->start; 2637 2638 spin_lock_init(&priv->lock); 2639 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2640 2641 error = of_get_phy_mode(np, &priv->phy_interface); 2642 if (error && error != -ENODEV) 2643 goto out_release; 2644 2645 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2646 priv->avb_link_active_low = 2647 of_property_read_bool(np, "renesas,ether-link-active-low"); 2648 2649 if (info->multi_irqs) { 2650 irq = platform_get_irq_byname(pdev, "ch24"); 2651 if (irq < 0) { 2652 error = irq; 2653 goto out_release; 2654 } 2655 priv->emac_irq = irq; 2656 for (i = 0; i < NUM_RX_QUEUE; i++) { 2657 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2658 if (irq < 0) { 2659 error = irq; 2660 goto out_release; 2661 } 2662 priv->rx_irqs[i] = irq; 2663 } 2664 for (i = 0; i < NUM_TX_QUEUE; i++) { 2665 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2666 if (irq < 0) { 2667 error = irq; 2668 goto out_release; 2669 } 2670 priv->tx_irqs[i] = irq; 2671 } 2672 } 2673 2674 priv->clk = devm_clk_get(&pdev->dev, NULL); 2675 if (IS_ERR(priv->clk)) { 2676 error = PTR_ERR(priv->clk); 2677 goto out_release; 2678 } 2679 2680 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2681 if (IS_ERR(priv->refclk)) { 2682 error = PTR_ERR(priv->refclk); 2683 goto out_release; 2684 } 2685 clk_prepare_enable(priv->refclk); 2686 2687 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2688 ndev->min_mtu = ETH_MIN_MTU; 2689 2690 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2691 * Use two descriptor to handle such situation. First descriptor to 2692 * handle aligned data buffer and second descriptor to handle the 2693 * overflow data because of alignment. 2694 */ 2695 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2696 2697 /* Set function */ 2698 ndev->netdev_ops = &ravb_netdev_ops; 2699 ndev->ethtool_ops = &ravb_ethtool_ops; 2700 2701 /* Set AVB config mode */ 2702 ravb_set_config_mode(ndev); 2703 2704 if (info->gptp || info->ccc_gac) { 2705 /* Set GTI value */ 2706 error = ravb_set_gti(ndev); 2707 if (error) 2708 goto out_disable_refclk; 2709 2710 /* Request GTI loading */ 2711 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2712 } 2713 2714 if (info->internal_delay) { 2715 ravb_parse_delay_mode(np, ndev); 2716 ravb_set_delay_mode(ndev); 2717 } 2718 2719 /* Allocate descriptor base address table */ 2720 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2721 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2722 &priv->desc_bat_dma, GFP_KERNEL); 2723 if (!priv->desc_bat) { 2724 dev_err(&pdev->dev, 2725 "Cannot allocate desc base address table (size %d bytes)\n", 2726 priv->desc_bat_size); 2727 error = -ENOMEM; 2728 goto out_disable_refclk; 2729 } 2730 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2731 priv->desc_bat[q].die_dt = DT_EOS; 2732 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2733 2734 /* Initialise HW timestamp list */ 2735 INIT_LIST_HEAD(&priv->ts_skb_list); 2736 2737 /* Initialise PTP Clock driver */ 2738 if (info->ccc_gac) 2739 ravb_ptp_init(ndev, pdev); 2740 2741 /* Debug message level */ 2742 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2743 2744 /* Read and set MAC address */ 2745 ravb_read_mac_address(np, ndev); 2746 if (!is_valid_ether_addr(ndev->dev_addr)) { 2747 dev_warn(&pdev->dev, 2748 "no valid MAC address supplied, using a random one\n"); 2749 eth_hw_addr_random(ndev); 2750 } 2751 2752 /* MDIO bus init */ 2753 error = ravb_mdio_init(priv); 2754 if (error) { 2755 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2756 goto out_dma_free; 2757 } 2758 2759 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2760 if (info->nc_queues) 2761 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2762 2763 /* Network device register */ 2764 error = register_netdev(ndev); 2765 if (error) 2766 goto out_napi_del; 2767 2768 device_set_wakeup_capable(&pdev->dev, 1); 2769 2770 /* Print device information */ 2771 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2772 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2773 2774 platform_set_drvdata(pdev, ndev); 2775 2776 return 0; 2777 2778 out_napi_del: 2779 if (info->nc_queues) 2780 netif_napi_del(&priv->napi[RAVB_NC]); 2781 2782 netif_napi_del(&priv->napi[RAVB_BE]); 2783 ravb_mdio_release(priv); 2784 out_dma_free: 2785 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2786 priv->desc_bat_dma); 2787 2788 /* Stop PTP Clock driver */ 2789 if (info->ccc_gac) 2790 ravb_ptp_stop(ndev); 2791 out_disable_refclk: 2792 clk_disable_unprepare(priv->refclk); 2793 out_release: 2794 free_netdev(ndev); 2795 2796 pm_runtime_put(&pdev->dev); 2797 pm_runtime_disable(&pdev->dev); 2798 reset_control_assert(rstc); 2799 return error; 2800 } 2801 2802 static int ravb_remove(struct platform_device *pdev) 2803 { 2804 struct net_device *ndev = platform_get_drvdata(pdev); 2805 struct ravb_private *priv = netdev_priv(ndev); 2806 const struct ravb_hw_info *info = priv->info; 2807 2808 /* Stop PTP Clock driver */ 2809 if (info->ccc_gac) 2810 ravb_ptp_stop(ndev); 2811 2812 clk_disable_unprepare(priv->refclk); 2813 2814 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2815 priv->desc_bat_dma); 2816 /* Set reset mode */ 2817 ravb_write(ndev, CCC_OPC_RESET, CCC); 2818 pm_runtime_put_sync(&pdev->dev); 2819 unregister_netdev(ndev); 2820 if (info->nc_queues) 2821 netif_napi_del(&priv->napi[RAVB_NC]); 2822 netif_napi_del(&priv->napi[RAVB_BE]); 2823 ravb_mdio_release(priv); 2824 pm_runtime_disable(&pdev->dev); 2825 reset_control_assert(priv->rstc); 2826 free_netdev(ndev); 2827 platform_set_drvdata(pdev, NULL); 2828 2829 return 0; 2830 } 2831 2832 static int ravb_wol_setup(struct net_device *ndev) 2833 { 2834 struct ravb_private *priv = netdev_priv(ndev); 2835 const struct ravb_hw_info *info = priv->info; 2836 2837 /* Disable interrupts by clearing the interrupt masks. */ 2838 ravb_write(ndev, 0, RIC0); 2839 ravb_write(ndev, 0, RIC2); 2840 ravb_write(ndev, 0, TIC); 2841 2842 /* Only allow ECI interrupts */ 2843 synchronize_irq(priv->emac_irq); 2844 if (info->nc_queues) 2845 napi_disable(&priv->napi[RAVB_NC]); 2846 napi_disable(&priv->napi[RAVB_BE]); 2847 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2848 2849 /* Enable MagicPacket */ 2850 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2851 2852 return enable_irq_wake(priv->emac_irq); 2853 } 2854 2855 static int ravb_wol_restore(struct net_device *ndev) 2856 { 2857 struct ravb_private *priv = netdev_priv(ndev); 2858 const struct ravb_hw_info *info = priv->info; 2859 int ret; 2860 2861 if (info->nc_queues) 2862 napi_enable(&priv->napi[RAVB_NC]); 2863 napi_enable(&priv->napi[RAVB_BE]); 2864 2865 /* Disable MagicPacket */ 2866 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2867 2868 ret = ravb_close(ndev); 2869 if (ret < 0) 2870 return ret; 2871 2872 return disable_irq_wake(priv->emac_irq); 2873 } 2874 2875 static int __maybe_unused ravb_suspend(struct device *dev) 2876 { 2877 struct net_device *ndev = dev_get_drvdata(dev); 2878 struct ravb_private *priv = netdev_priv(ndev); 2879 int ret; 2880 2881 if (!netif_running(ndev)) 2882 return 0; 2883 2884 netif_device_detach(ndev); 2885 2886 if (priv->wol_enabled) 2887 ret = ravb_wol_setup(ndev); 2888 else 2889 ret = ravb_close(ndev); 2890 2891 return ret; 2892 } 2893 2894 static int __maybe_unused ravb_resume(struct device *dev) 2895 { 2896 struct net_device *ndev = dev_get_drvdata(dev); 2897 struct ravb_private *priv = netdev_priv(ndev); 2898 const struct ravb_hw_info *info = priv->info; 2899 int ret = 0; 2900 2901 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2902 if (priv->wol_enabled) 2903 ravb_write(ndev, CCC_OPC_RESET, CCC); 2904 2905 /* All register have been reset to default values. 2906 * Restore all registers which where setup at probe time and 2907 * reopen device if it was running before system suspended. 2908 */ 2909 2910 /* Set AVB config mode */ 2911 ravb_set_config_mode(ndev); 2912 2913 if (info->gptp || info->ccc_gac) { 2914 /* Set GTI value */ 2915 ret = ravb_set_gti(ndev); 2916 if (ret) 2917 return ret; 2918 2919 /* Request GTI loading */ 2920 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2921 } 2922 2923 if (info->internal_delay) 2924 ravb_set_delay_mode(ndev); 2925 2926 /* Restore descriptor base address table */ 2927 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2928 2929 if (netif_running(ndev)) { 2930 if (priv->wol_enabled) { 2931 ret = ravb_wol_restore(ndev); 2932 if (ret) 2933 return ret; 2934 } 2935 ret = ravb_open(ndev); 2936 if (ret < 0) 2937 return ret; 2938 netif_device_attach(ndev); 2939 } 2940 2941 return ret; 2942 } 2943 2944 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2945 { 2946 /* Runtime PM callback shared between ->runtime_suspend() 2947 * and ->runtime_resume(). Simply returns success. 2948 * 2949 * This driver re-initializes all registers after 2950 * pm_runtime_get_sync() anyway so there is no need 2951 * to save and restore registers here. 2952 */ 2953 return 0; 2954 } 2955 2956 static const struct dev_pm_ops ravb_dev_pm_ops = { 2957 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2958 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2959 }; 2960 2961 static struct platform_driver ravb_driver = { 2962 .probe = ravb_probe, 2963 .remove = ravb_remove, 2964 .driver = { 2965 .name = "ravb", 2966 .pm = &ravb_dev_pm_ops, 2967 .of_match_table = ravb_match_table, 2968 }, 2969 }; 2970 2971 module_platform_driver(ravb_driver); 2972 2973 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2974 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2975 MODULE_LICENSE("GPL v2"); 2976