1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/reset.h> 32 #include <linux/math64.h> 33 34 #include "ravb.h" 35 36 #define RAVB_DEF_MSG_ENABLE \ 37 (NETIF_MSG_LINK | \ 38 NETIF_MSG_TIMER | \ 39 NETIF_MSG_RX_ERR | \ 40 NETIF_MSG_TX_ERR) 41 42 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 43 "ch0", /* RAVB_BE */ 44 "ch1", /* RAVB_NC */ 45 }; 46 47 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 48 "ch18", /* RAVB_BE */ 49 "ch19", /* RAVB_NC */ 50 }; 51 52 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 53 u32 set) 54 { 55 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 56 } 57 58 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 59 { 60 int i; 61 62 for (i = 0; i < 10000; i++) { 63 if ((ravb_read(ndev, reg) & mask) == value) 64 return 0; 65 udelay(10); 66 } 67 return -ETIMEDOUT; 68 } 69 70 static int ravb_config(struct net_device *ndev) 71 { 72 int error; 73 74 /* Set config mode */ 75 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 76 /* Check if the operating mode is changed to the config mode */ 77 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 78 if (error) 79 netdev_err(ndev, "failed to switch device to config mode\n"); 80 81 return error; 82 } 83 84 static void ravb_set_rate_gbeth(struct net_device *ndev) 85 { 86 struct ravb_private *priv = netdev_priv(ndev); 87 88 switch (priv->speed) { 89 case 10: /* 10BASE */ 90 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 91 break; 92 case 100: /* 100BASE */ 93 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 94 break; 95 case 1000: /* 1000BASE */ 96 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 97 break; 98 } 99 } 100 101 static void ravb_set_rate_rcar(struct net_device *ndev) 102 { 103 struct ravb_private *priv = netdev_priv(ndev); 104 105 switch (priv->speed) { 106 case 100: /* 100BASE */ 107 ravb_write(ndev, GECMR_SPEED_100, GECMR); 108 break; 109 case 1000: /* 1000BASE */ 110 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 111 break; 112 } 113 } 114 115 static void ravb_set_buffer_align(struct sk_buff *skb) 116 { 117 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 118 119 if (reserve) 120 skb_reserve(skb, RAVB_ALIGN - reserve); 121 } 122 123 /* Get MAC address from the MAC address registers 124 * 125 * Ethernet AVB device doesn't have ROM for MAC address. 126 * This function gets the MAC address that was used by a bootloader. 127 */ 128 static void ravb_read_mac_address(struct device_node *np, 129 struct net_device *ndev) 130 { 131 int ret; 132 133 ret = of_get_ethdev_address(np, ndev); 134 if (ret) { 135 u32 mahr = ravb_read(ndev, MAHR); 136 u32 malr = ravb_read(ndev, MALR); 137 u8 addr[ETH_ALEN]; 138 139 addr[0] = (mahr >> 24) & 0xFF; 140 addr[1] = (mahr >> 16) & 0xFF; 141 addr[2] = (mahr >> 8) & 0xFF; 142 addr[3] = (mahr >> 0) & 0xFF; 143 addr[4] = (malr >> 8) & 0xFF; 144 addr[5] = (malr >> 0) & 0xFF; 145 eth_hw_addr_set(ndev, addr); 146 } 147 } 148 149 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 150 { 151 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 152 mdiobb); 153 154 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 155 } 156 157 /* MDC pin control */ 158 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 161 } 162 163 /* Data I/O pin control */ 164 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 167 } 168 169 /* Set data bit */ 170 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 171 { 172 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 173 } 174 175 /* Get data bit */ 176 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 177 { 178 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 179 mdiobb); 180 181 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 182 } 183 184 /* MDIO bus control struct */ 185 static const struct mdiobb_ops bb_ops = { 186 .owner = THIS_MODULE, 187 .set_mdc = ravb_set_mdc, 188 .set_mdio_dir = ravb_set_mdio_dir, 189 .set_mdio_data = ravb_set_mdio_data, 190 .get_mdio_data = ravb_get_mdio_data, 191 }; 192 193 /* Free TX skb function for AVB-IP */ 194 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 195 { 196 struct ravb_private *priv = netdev_priv(ndev); 197 struct net_device_stats *stats = &priv->stats[q]; 198 unsigned int num_tx_desc = priv->num_tx_desc; 199 struct ravb_tx_desc *desc; 200 unsigned int entry; 201 int free_num = 0; 202 u32 size; 203 204 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 205 bool txed; 206 207 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 208 num_tx_desc); 209 desc = &priv->tx_ring[q][entry]; 210 txed = desc->die_dt == DT_FEMPTY; 211 if (free_txed_only && !txed) 212 break; 213 /* Descriptor type must be checked before all other reads */ 214 dma_rmb(); 215 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 216 /* Free the original skb. */ 217 if (priv->tx_skb[q][entry / num_tx_desc]) { 218 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 219 size, DMA_TO_DEVICE); 220 /* Last packet descriptor? */ 221 if (entry % num_tx_desc == num_tx_desc - 1) { 222 entry /= num_tx_desc; 223 dev_kfree_skb_any(priv->tx_skb[q][entry]); 224 priv->tx_skb[q][entry] = NULL; 225 if (txed) 226 stats->tx_packets++; 227 } 228 free_num++; 229 } 230 if (txed) 231 stats->tx_bytes += size; 232 desc->die_dt = DT_EEMPTY; 233 } 234 return free_num; 235 } 236 237 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 238 { 239 struct ravb_private *priv = netdev_priv(ndev); 240 unsigned int ring_size; 241 unsigned int i; 242 243 if (!priv->gbeth_rx_ring) 244 return; 245 246 for (i = 0; i < priv->num_rx_ring[q]; i++) { 247 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i]; 248 249 if (!dma_mapping_error(ndev->dev.parent, 250 le32_to_cpu(desc->dptr))) 251 dma_unmap_single(ndev->dev.parent, 252 le32_to_cpu(desc->dptr), 253 GBETH_RX_BUFF_MAX, 254 DMA_FROM_DEVICE); 255 } 256 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 257 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring, 258 priv->rx_desc_dma[q]); 259 priv->gbeth_rx_ring = NULL; 260 } 261 262 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q) 263 { 264 struct ravb_private *priv = netdev_priv(ndev); 265 unsigned int ring_size; 266 unsigned int i; 267 268 if (!priv->rx_ring[q]) 269 return; 270 271 for (i = 0; i < priv->num_rx_ring[q]; i++) { 272 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 273 274 if (!dma_mapping_error(ndev->dev.parent, 275 le32_to_cpu(desc->dptr))) 276 dma_unmap_single(ndev->dev.parent, 277 le32_to_cpu(desc->dptr), 278 RX_BUF_SZ, 279 DMA_FROM_DEVICE); 280 } 281 ring_size = sizeof(struct ravb_ex_rx_desc) * 282 (priv->num_rx_ring[q] + 1); 283 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 284 priv->rx_desc_dma[q]); 285 priv->rx_ring[q] = NULL; 286 } 287 288 /* Free skb's and DMA buffers for Ethernet AVB */ 289 static void ravb_ring_free(struct net_device *ndev, int q) 290 { 291 struct ravb_private *priv = netdev_priv(ndev); 292 const struct ravb_hw_info *info = priv->info; 293 unsigned int num_tx_desc = priv->num_tx_desc; 294 unsigned int ring_size; 295 unsigned int i; 296 297 info->rx_ring_free(ndev, q); 298 299 if (priv->tx_ring[q]) { 300 ravb_tx_free(ndev, q, false); 301 302 ring_size = sizeof(struct ravb_tx_desc) * 303 (priv->num_tx_ring[q] * num_tx_desc + 1); 304 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 305 priv->tx_desc_dma[q]); 306 priv->tx_ring[q] = NULL; 307 } 308 309 /* Free RX skb ringbuffer */ 310 if (priv->rx_skb[q]) { 311 for (i = 0; i < priv->num_rx_ring[q]; i++) 312 dev_kfree_skb(priv->rx_skb[q][i]); 313 } 314 kfree(priv->rx_skb[q]); 315 priv->rx_skb[q] = NULL; 316 317 /* Free aligned TX buffers */ 318 kfree(priv->tx_align[q]); 319 priv->tx_align[q] = NULL; 320 321 /* Free TX skb ringbuffer. 322 * SKBs are freed by ravb_tx_free() call above. 323 */ 324 kfree(priv->tx_skb[q]); 325 priv->tx_skb[q] = NULL; 326 } 327 328 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 329 { 330 struct ravb_private *priv = netdev_priv(ndev); 331 struct ravb_rx_desc *rx_desc; 332 unsigned int rx_ring_size; 333 dma_addr_t dma_addr; 334 unsigned int i; 335 336 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 337 memset(priv->gbeth_rx_ring, 0, rx_ring_size); 338 /* Build RX ring buffer */ 339 for (i = 0; i < priv->num_rx_ring[q]; i++) { 340 /* RX descriptor */ 341 rx_desc = &priv->gbeth_rx_ring[i]; 342 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 343 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 344 GBETH_RX_BUFF_MAX, 345 DMA_FROM_DEVICE); 346 /* We just set the data size to 0 for a failed mapping which 347 * should prevent DMA from happening... 348 */ 349 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 350 rx_desc->ds_cc = cpu_to_le16(0); 351 rx_desc->dptr = cpu_to_le32(dma_addr); 352 rx_desc->die_dt = DT_FEMPTY; 353 } 354 rx_desc = &priv->gbeth_rx_ring[i]; 355 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 356 rx_desc->die_dt = DT_LINKFIX; /* type */ 357 } 358 359 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q) 360 { 361 struct ravb_private *priv = netdev_priv(ndev); 362 struct ravb_ex_rx_desc *rx_desc; 363 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 364 dma_addr_t dma_addr; 365 unsigned int i; 366 367 memset(priv->rx_ring[q], 0, rx_ring_size); 368 /* Build RX ring buffer */ 369 for (i = 0; i < priv->num_rx_ring[q]; i++) { 370 /* RX descriptor */ 371 rx_desc = &priv->rx_ring[q][i]; 372 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 373 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 374 RX_BUF_SZ, 375 DMA_FROM_DEVICE); 376 /* We just set the data size to 0 for a failed mapping which 377 * should prevent DMA from happening... 378 */ 379 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 380 rx_desc->ds_cc = cpu_to_le16(0); 381 rx_desc->dptr = cpu_to_le32(dma_addr); 382 rx_desc->die_dt = DT_FEMPTY; 383 } 384 rx_desc = &priv->rx_ring[q][i]; 385 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 386 rx_desc->die_dt = DT_LINKFIX; /* type */ 387 } 388 389 /* Format skb and descriptor buffer for Ethernet AVB */ 390 static void ravb_ring_format(struct net_device *ndev, int q) 391 { 392 struct ravb_private *priv = netdev_priv(ndev); 393 const struct ravb_hw_info *info = priv->info; 394 unsigned int num_tx_desc = priv->num_tx_desc; 395 struct ravb_tx_desc *tx_desc; 396 struct ravb_desc *desc; 397 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 398 num_tx_desc; 399 unsigned int i; 400 401 priv->cur_rx[q] = 0; 402 priv->cur_tx[q] = 0; 403 priv->dirty_rx[q] = 0; 404 priv->dirty_tx[q] = 0; 405 406 info->rx_ring_format(ndev, q); 407 408 memset(priv->tx_ring[q], 0, tx_ring_size); 409 /* Build TX ring buffer */ 410 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 411 i++, tx_desc++) { 412 tx_desc->die_dt = DT_EEMPTY; 413 if (num_tx_desc > 1) { 414 tx_desc++; 415 tx_desc->die_dt = DT_EEMPTY; 416 } 417 } 418 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 419 tx_desc->die_dt = DT_LINKFIX; /* type */ 420 421 /* RX descriptor base address for best effort */ 422 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 423 desc->die_dt = DT_LINKFIX; /* type */ 424 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 425 426 /* TX descriptor base address for best effort */ 427 desc = &priv->desc_bat[q]; 428 desc->die_dt = DT_LINKFIX; /* type */ 429 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 430 } 431 432 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 433 { 434 struct ravb_private *priv = netdev_priv(ndev); 435 unsigned int ring_size; 436 437 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 438 439 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size, 440 &priv->rx_desc_dma[q], 441 GFP_KERNEL); 442 return priv->gbeth_rx_ring; 443 } 444 445 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q) 446 { 447 struct ravb_private *priv = netdev_priv(ndev); 448 unsigned int ring_size; 449 450 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 451 452 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 453 &priv->rx_desc_dma[q], 454 GFP_KERNEL); 455 return priv->rx_ring[q]; 456 } 457 458 /* Init skb and descriptor buffer for Ethernet AVB */ 459 static int ravb_ring_init(struct net_device *ndev, int q) 460 { 461 struct ravb_private *priv = netdev_priv(ndev); 462 const struct ravb_hw_info *info = priv->info; 463 unsigned int num_tx_desc = priv->num_tx_desc; 464 unsigned int ring_size; 465 struct sk_buff *skb; 466 unsigned int i; 467 468 /* Allocate RX and TX skb rings */ 469 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 470 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 471 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 472 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 473 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 474 goto error; 475 476 for (i = 0; i < priv->num_rx_ring[q]; i++) { 477 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL); 478 if (!skb) 479 goto error; 480 ravb_set_buffer_align(skb); 481 priv->rx_skb[q][i] = skb; 482 } 483 484 if (num_tx_desc > 1) { 485 /* Allocate rings for the aligned buffers */ 486 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 487 DPTR_ALIGN - 1, GFP_KERNEL); 488 if (!priv->tx_align[q]) 489 goto error; 490 } 491 492 /* Allocate all RX descriptors. */ 493 if (!info->alloc_rx_desc(ndev, q)) 494 goto error; 495 496 priv->dirty_rx[q] = 0; 497 498 /* Allocate all TX descriptors. */ 499 ring_size = sizeof(struct ravb_tx_desc) * 500 (priv->num_tx_ring[q] * num_tx_desc + 1); 501 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 502 &priv->tx_desc_dma[q], 503 GFP_KERNEL); 504 if (!priv->tx_ring[q]) 505 goto error; 506 507 return 0; 508 509 error: 510 ravb_ring_free(ndev, q); 511 512 return -ENOMEM; 513 } 514 515 static void ravb_emac_init_gbeth(struct net_device *ndev) 516 { 517 struct ravb_private *priv = netdev_priv(ndev); 518 519 /* Receive frame limit set register */ 520 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 521 522 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 523 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 524 ECMR_TE | ECMR_RE | ECMR_RCPT | 525 ECMR_TXF | ECMR_RXF, ECMR); 526 527 ravb_set_rate_gbeth(ndev); 528 529 /* Set MAC address */ 530 ravb_write(ndev, 531 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 532 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 533 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 534 535 /* E-MAC status register clear */ 536 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 537 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 538 539 /* E-MAC interrupt enable register */ 540 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 541 542 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 543 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 544 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 545 } else { 546 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 547 CXR31_SEL_LINK0); 548 } 549 } 550 551 static void ravb_emac_init_rcar(struct net_device *ndev) 552 { 553 /* Receive frame limit set register */ 554 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 555 556 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 557 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 558 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 559 ECMR_TE | ECMR_RE, ECMR); 560 561 ravb_set_rate_rcar(ndev); 562 563 /* Set MAC address */ 564 ravb_write(ndev, 565 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 566 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 567 ravb_write(ndev, 568 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 569 570 /* E-MAC status register clear */ 571 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 572 573 /* E-MAC interrupt enable register */ 574 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 575 } 576 577 /* E-MAC init function */ 578 static void ravb_emac_init(struct net_device *ndev) 579 { 580 struct ravb_private *priv = netdev_priv(ndev); 581 const struct ravb_hw_info *info = priv->info; 582 583 info->emac_init(ndev); 584 } 585 586 static int ravb_dmac_init_gbeth(struct net_device *ndev) 587 { 588 int error; 589 590 error = ravb_ring_init(ndev, RAVB_BE); 591 if (error) 592 return error; 593 594 /* Descriptor format */ 595 ravb_ring_format(ndev, RAVB_BE); 596 597 /* Set DMAC RX */ 598 ravb_write(ndev, 0x60000000, RCR); 599 600 /* Set Max Frame Length (RTC) */ 601 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 602 603 /* Set FIFO size */ 604 ravb_write(ndev, 0x00222200, TGC); 605 606 ravb_write(ndev, 0, TCCR); 607 608 /* Frame receive */ 609 ravb_write(ndev, RIC0_FRE0, RIC0); 610 /* Disable FIFO full warning */ 611 ravb_write(ndev, 0x0, RIC1); 612 /* Receive FIFO full error, descriptor empty */ 613 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 614 615 ravb_write(ndev, TIC_FTE0, TIC); 616 617 return 0; 618 } 619 620 static int ravb_dmac_init_rcar(struct net_device *ndev) 621 { 622 struct ravb_private *priv = netdev_priv(ndev); 623 const struct ravb_hw_info *info = priv->info; 624 int error; 625 626 error = ravb_ring_init(ndev, RAVB_BE); 627 if (error) 628 return error; 629 error = ravb_ring_init(ndev, RAVB_NC); 630 if (error) { 631 ravb_ring_free(ndev, RAVB_BE); 632 return error; 633 } 634 635 /* Descriptor format */ 636 ravb_ring_format(ndev, RAVB_BE); 637 ravb_ring_format(ndev, RAVB_NC); 638 639 /* Set AVB RX */ 640 ravb_write(ndev, 641 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 642 643 /* Set FIFO size */ 644 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 645 646 /* Timestamp enable */ 647 ravb_write(ndev, TCCR_TFEN, TCCR); 648 649 /* Interrupt init: */ 650 if (info->multi_irqs) { 651 /* Clear DIL.DPLx */ 652 ravb_write(ndev, 0, DIL); 653 /* Set queue specific interrupt */ 654 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 655 } 656 /* Frame receive */ 657 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 658 /* Disable FIFO full warning */ 659 ravb_write(ndev, 0, RIC1); 660 /* Receive FIFO full error, descriptor empty */ 661 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 662 /* Frame transmitted, timestamp FIFO updated */ 663 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 664 665 return 0; 666 } 667 668 /* Device init function for Ethernet AVB */ 669 static int ravb_dmac_init(struct net_device *ndev) 670 { 671 struct ravb_private *priv = netdev_priv(ndev); 672 const struct ravb_hw_info *info = priv->info; 673 int error; 674 675 /* Set CONFIG mode */ 676 error = ravb_config(ndev); 677 if (error) 678 return error; 679 680 error = info->dmac_init(ndev); 681 if (error) 682 return error; 683 684 /* Setting the control will start the AVB-DMAC process. */ 685 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 686 687 return 0; 688 } 689 690 static void ravb_get_tx_tstamp(struct net_device *ndev) 691 { 692 struct ravb_private *priv = netdev_priv(ndev); 693 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 694 struct skb_shared_hwtstamps shhwtstamps; 695 struct sk_buff *skb; 696 struct timespec64 ts; 697 u16 tag, tfa_tag; 698 int count; 699 u32 tfa2; 700 701 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 702 while (count--) { 703 tfa2 = ravb_read(ndev, TFA2); 704 tfa_tag = (tfa2 & TFA2_TST) >> 16; 705 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 706 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 707 ravb_read(ndev, TFA1); 708 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 709 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 710 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 711 list) { 712 skb = ts_skb->skb; 713 tag = ts_skb->tag; 714 list_del(&ts_skb->list); 715 kfree(ts_skb); 716 if (tag == tfa_tag) { 717 skb_tstamp_tx(skb, &shhwtstamps); 718 dev_consume_skb_any(skb); 719 break; 720 } else { 721 dev_kfree_skb_any(skb); 722 } 723 } 724 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 725 } 726 } 727 728 static void ravb_rx_csum(struct sk_buff *skb) 729 { 730 u8 *hw_csum; 731 732 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 733 * appended to packet data 734 */ 735 if (unlikely(skb->len < sizeof(__sum16))) 736 return; 737 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 738 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 739 skb->ip_summed = CHECKSUM_COMPLETE; 740 skb_trim(skb, skb->len - sizeof(__sum16)); 741 } 742 743 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 744 struct ravb_rx_desc *desc) 745 { 746 struct ravb_private *priv = netdev_priv(ndev); 747 struct sk_buff *skb; 748 749 skb = priv->rx_skb[RAVB_BE][entry]; 750 priv->rx_skb[RAVB_BE][entry] = NULL; 751 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 752 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE); 753 754 return skb; 755 } 756 757 /* Packet receive function for Gigabit Ethernet */ 758 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 759 { 760 struct ravb_private *priv = netdev_priv(ndev); 761 const struct ravb_hw_info *info = priv->info; 762 struct net_device_stats *stats; 763 struct ravb_rx_desc *desc; 764 struct sk_buff *skb; 765 dma_addr_t dma_addr; 766 u8 desc_status; 767 int boguscnt; 768 u16 pkt_len; 769 u8 die_dt; 770 int entry; 771 int limit; 772 773 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 774 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 775 stats = &priv->stats[q]; 776 777 boguscnt = min(boguscnt, *quota); 778 limit = boguscnt; 779 desc = &priv->gbeth_rx_ring[entry]; 780 while (desc->die_dt != DT_FEMPTY) { 781 /* Descriptor type must be checked before all other reads */ 782 dma_rmb(); 783 desc_status = desc->msc; 784 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 785 786 if (--boguscnt < 0) 787 break; 788 789 /* We use 0-byte descriptors to mark the DMA mapping errors */ 790 if (!pkt_len) 791 continue; 792 793 if (desc_status & MSC_MC) 794 stats->multicast++; 795 796 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 797 stats->rx_errors++; 798 if (desc_status & MSC_CRC) 799 stats->rx_crc_errors++; 800 if (desc_status & MSC_RFE) 801 stats->rx_frame_errors++; 802 if (desc_status & (MSC_RTLF | MSC_RTSF)) 803 stats->rx_length_errors++; 804 if (desc_status & MSC_CEEF) 805 stats->rx_missed_errors++; 806 } else { 807 die_dt = desc->die_dt & 0xF0; 808 switch (die_dt) { 809 case DT_FSINGLE: 810 skb = ravb_get_skb_gbeth(ndev, entry, desc); 811 skb_put(skb, pkt_len); 812 skb->protocol = eth_type_trans(skb, ndev); 813 napi_gro_receive(&priv->napi[q], skb); 814 stats->rx_packets++; 815 stats->rx_bytes += pkt_len; 816 break; 817 case DT_FSTART: 818 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 819 skb_put(priv->rx_1st_skb, pkt_len); 820 break; 821 case DT_FMID: 822 skb = ravb_get_skb_gbeth(ndev, entry, desc); 823 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 824 priv->rx_1st_skb->len, 825 skb->data, 826 pkt_len); 827 skb_put(priv->rx_1st_skb, pkt_len); 828 dev_kfree_skb(skb); 829 break; 830 case DT_FEND: 831 skb = ravb_get_skb_gbeth(ndev, entry, desc); 832 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 833 priv->rx_1st_skb->len, 834 skb->data, 835 pkt_len); 836 skb_put(priv->rx_1st_skb, pkt_len); 837 dev_kfree_skb(skb); 838 priv->rx_1st_skb->protocol = 839 eth_type_trans(priv->rx_1st_skb, ndev); 840 napi_gro_receive(&priv->napi[q], 841 priv->rx_1st_skb); 842 stats->rx_packets++; 843 stats->rx_bytes += pkt_len; 844 break; 845 } 846 } 847 848 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 849 desc = &priv->gbeth_rx_ring[entry]; 850 } 851 852 /* Refill the RX ring buffers. */ 853 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 854 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 855 desc = &priv->gbeth_rx_ring[entry]; 856 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 857 858 if (!priv->rx_skb[q][entry]) { 859 skb = netdev_alloc_skb(ndev, info->max_rx_len); 860 if (!skb) 861 break; 862 ravb_set_buffer_align(skb); 863 dma_addr = dma_map_single(ndev->dev.parent, 864 skb->data, 865 GBETH_RX_BUFF_MAX, 866 DMA_FROM_DEVICE); 867 skb_checksum_none_assert(skb); 868 /* We just set the data size to 0 for a failed mapping 869 * which should prevent DMA from happening... 870 */ 871 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 872 desc->ds_cc = cpu_to_le16(0); 873 desc->dptr = cpu_to_le32(dma_addr); 874 priv->rx_skb[q][entry] = skb; 875 } 876 /* Descriptor type must be set after all the above writes */ 877 dma_wmb(); 878 desc->die_dt = DT_FEMPTY; 879 } 880 881 *quota -= limit - (++boguscnt); 882 883 return boguscnt <= 0; 884 } 885 886 /* Packet receive function for Ethernet AVB */ 887 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 888 { 889 struct ravb_private *priv = netdev_priv(ndev); 890 const struct ravb_hw_info *info = priv->info; 891 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 892 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 893 priv->cur_rx[q]; 894 struct net_device_stats *stats = &priv->stats[q]; 895 struct ravb_ex_rx_desc *desc; 896 struct sk_buff *skb; 897 dma_addr_t dma_addr; 898 struct timespec64 ts; 899 u8 desc_status; 900 u16 pkt_len; 901 int limit; 902 903 boguscnt = min(boguscnt, *quota); 904 limit = boguscnt; 905 desc = &priv->rx_ring[q][entry]; 906 while (desc->die_dt != DT_FEMPTY) { 907 /* Descriptor type must be checked before all other reads */ 908 dma_rmb(); 909 desc_status = desc->msc; 910 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 911 912 if (--boguscnt < 0) 913 break; 914 915 /* We use 0-byte descriptors to mark the DMA mapping errors */ 916 if (!pkt_len) 917 continue; 918 919 if (desc_status & MSC_MC) 920 stats->multicast++; 921 922 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 923 MSC_CEEF)) { 924 stats->rx_errors++; 925 if (desc_status & MSC_CRC) 926 stats->rx_crc_errors++; 927 if (desc_status & MSC_RFE) 928 stats->rx_frame_errors++; 929 if (desc_status & (MSC_RTLF | MSC_RTSF)) 930 stats->rx_length_errors++; 931 if (desc_status & MSC_CEEF) 932 stats->rx_missed_errors++; 933 } else { 934 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 935 936 skb = priv->rx_skb[q][entry]; 937 priv->rx_skb[q][entry] = NULL; 938 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 939 RX_BUF_SZ, 940 DMA_FROM_DEVICE); 941 get_ts &= (q == RAVB_NC) ? 942 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 943 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 944 if (get_ts) { 945 struct skb_shared_hwtstamps *shhwtstamps; 946 947 shhwtstamps = skb_hwtstamps(skb); 948 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 949 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 950 32) | le32_to_cpu(desc->ts_sl); 951 ts.tv_nsec = le32_to_cpu(desc->ts_n); 952 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 953 } 954 955 skb_put(skb, pkt_len); 956 skb->protocol = eth_type_trans(skb, ndev); 957 if (ndev->features & NETIF_F_RXCSUM) 958 ravb_rx_csum(skb); 959 napi_gro_receive(&priv->napi[q], skb); 960 stats->rx_packets++; 961 stats->rx_bytes += pkt_len; 962 } 963 964 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 965 desc = &priv->rx_ring[q][entry]; 966 } 967 968 /* Refill the RX ring buffers. */ 969 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 970 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 971 desc = &priv->rx_ring[q][entry]; 972 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 973 974 if (!priv->rx_skb[q][entry]) { 975 skb = netdev_alloc_skb(ndev, info->max_rx_len); 976 if (!skb) 977 break; /* Better luck next round. */ 978 ravb_set_buffer_align(skb); 979 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 980 le16_to_cpu(desc->ds_cc), 981 DMA_FROM_DEVICE); 982 skb_checksum_none_assert(skb); 983 /* We just set the data size to 0 for a failed mapping 984 * which should prevent DMA from happening... 985 */ 986 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 987 desc->ds_cc = cpu_to_le16(0); 988 desc->dptr = cpu_to_le32(dma_addr); 989 priv->rx_skb[q][entry] = skb; 990 } 991 /* Descriptor type must be set after all the above writes */ 992 dma_wmb(); 993 desc->die_dt = DT_FEMPTY; 994 } 995 996 *quota -= limit - (++boguscnt); 997 998 return boguscnt <= 0; 999 } 1000 1001 /* Packet receive function for Ethernet AVB */ 1002 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 1003 { 1004 struct ravb_private *priv = netdev_priv(ndev); 1005 const struct ravb_hw_info *info = priv->info; 1006 1007 return info->receive(ndev, quota, q); 1008 } 1009 1010 static void ravb_rcv_snd_disable(struct net_device *ndev) 1011 { 1012 /* Disable TX and RX */ 1013 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1014 } 1015 1016 static void ravb_rcv_snd_enable(struct net_device *ndev) 1017 { 1018 /* Enable TX and RX */ 1019 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1020 } 1021 1022 /* function for waiting dma process finished */ 1023 static int ravb_stop_dma(struct net_device *ndev) 1024 { 1025 struct ravb_private *priv = netdev_priv(ndev); 1026 const struct ravb_hw_info *info = priv->info; 1027 int error; 1028 1029 /* Wait for stopping the hardware TX process */ 1030 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1031 1032 if (error) 1033 return error; 1034 1035 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1036 0); 1037 if (error) 1038 return error; 1039 1040 /* Stop the E-MAC's RX/TX processes. */ 1041 ravb_rcv_snd_disable(ndev); 1042 1043 /* Wait for stopping the RX DMA process */ 1044 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1045 if (error) 1046 return error; 1047 1048 /* Stop AVB-DMAC process */ 1049 return ravb_config(ndev); 1050 } 1051 1052 /* E-MAC interrupt handler */ 1053 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1054 { 1055 struct ravb_private *priv = netdev_priv(ndev); 1056 u32 ecsr, psr; 1057 1058 ecsr = ravb_read(ndev, ECSR); 1059 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1060 1061 if (ecsr & ECSR_MPD) 1062 pm_wakeup_event(&priv->pdev->dev, 0); 1063 if (ecsr & ECSR_ICD) 1064 ndev->stats.tx_carrier_errors++; 1065 if (ecsr & ECSR_LCHNG) { 1066 /* Link changed */ 1067 if (priv->no_avb_link) 1068 return; 1069 psr = ravb_read(ndev, PSR); 1070 if (priv->avb_link_active_low) 1071 psr ^= PSR_LMON; 1072 if (!(psr & PSR_LMON)) { 1073 /* DIsable RX and TX */ 1074 ravb_rcv_snd_disable(ndev); 1075 } else { 1076 /* Enable RX and TX */ 1077 ravb_rcv_snd_enable(ndev); 1078 } 1079 } 1080 } 1081 1082 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1083 { 1084 struct net_device *ndev = dev_id; 1085 struct ravb_private *priv = netdev_priv(ndev); 1086 1087 spin_lock(&priv->lock); 1088 ravb_emac_interrupt_unlocked(ndev); 1089 spin_unlock(&priv->lock); 1090 return IRQ_HANDLED; 1091 } 1092 1093 /* Error interrupt handler */ 1094 static void ravb_error_interrupt(struct net_device *ndev) 1095 { 1096 struct ravb_private *priv = netdev_priv(ndev); 1097 u32 eis, ris2; 1098 1099 eis = ravb_read(ndev, EIS); 1100 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1101 if (eis & EIS_QFS) { 1102 ris2 = ravb_read(ndev, RIS2); 1103 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1104 RIS2); 1105 1106 /* Receive Descriptor Empty int */ 1107 if (ris2 & RIS2_QFF0) 1108 priv->stats[RAVB_BE].rx_over_errors++; 1109 1110 /* Receive Descriptor Empty int */ 1111 if (ris2 & RIS2_QFF1) 1112 priv->stats[RAVB_NC].rx_over_errors++; 1113 1114 /* Receive FIFO Overflow int */ 1115 if (ris2 & RIS2_RFFF) 1116 priv->rx_fifo_errors++; 1117 } 1118 } 1119 1120 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1121 { 1122 struct ravb_private *priv = netdev_priv(ndev); 1123 const struct ravb_hw_info *info = priv->info; 1124 u32 ris0 = ravb_read(ndev, RIS0); 1125 u32 ric0 = ravb_read(ndev, RIC0); 1126 u32 tis = ravb_read(ndev, TIS); 1127 u32 tic = ravb_read(ndev, TIC); 1128 1129 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1130 if (napi_schedule_prep(&priv->napi[q])) { 1131 /* Mask RX and TX interrupts */ 1132 if (!info->irq_en_dis) { 1133 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1134 ravb_write(ndev, tic & ~BIT(q), TIC); 1135 } else { 1136 ravb_write(ndev, BIT(q), RID0); 1137 ravb_write(ndev, BIT(q), TID); 1138 } 1139 __napi_schedule(&priv->napi[q]); 1140 } else { 1141 netdev_warn(ndev, 1142 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1143 ris0, ric0); 1144 netdev_warn(ndev, 1145 " tx status 0x%08x, tx mask 0x%08x.\n", 1146 tis, tic); 1147 } 1148 return true; 1149 } 1150 return false; 1151 } 1152 1153 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1154 { 1155 u32 tis = ravb_read(ndev, TIS); 1156 1157 if (tis & TIS_TFUF) { 1158 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1159 ravb_get_tx_tstamp(ndev); 1160 return true; 1161 } 1162 return false; 1163 } 1164 1165 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1166 { 1167 struct net_device *ndev = dev_id; 1168 struct ravb_private *priv = netdev_priv(ndev); 1169 const struct ravb_hw_info *info = priv->info; 1170 irqreturn_t result = IRQ_NONE; 1171 u32 iss; 1172 1173 spin_lock(&priv->lock); 1174 /* Get interrupt status */ 1175 iss = ravb_read(ndev, ISS); 1176 1177 /* Received and transmitted interrupts */ 1178 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1179 int q; 1180 1181 /* Timestamp updated */ 1182 if (ravb_timestamp_interrupt(ndev)) 1183 result = IRQ_HANDLED; 1184 1185 /* Network control and best effort queue RX/TX */ 1186 if (info->nc_queues) { 1187 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1188 if (ravb_queue_interrupt(ndev, q)) 1189 result = IRQ_HANDLED; 1190 } 1191 } else { 1192 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1193 result = IRQ_HANDLED; 1194 } 1195 } 1196 1197 /* E-MAC status summary */ 1198 if (iss & ISS_MS) { 1199 ravb_emac_interrupt_unlocked(ndev); 1200 result = IRQ_HANDLED; 1201 } 1202 1203 /* Error status summary */ 1204 if (iss & ISS_ES) { 1205 ravb_error_interrupt(ndev); 1206 result = IRQ_HANDLED; 1207 } 1208 1209 /* gPTP interrupt status summary */ 1210 if (iss & ISS_CGIS) { 1211 ravb_ptp_interrupt(ndev); 1212 result = IRQ_HANDLED; 1213 } 1214 1215 spin_unlock(&priv->lock); 1216 return result; 1217 } 1218 1219 /* Timestamp/Error/gPTP interrupt handler */ 1220 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1221 { 1222 struct net_device *ndev = dev_id; 1223 struct ravb_private *priv = netdev_priv(ndev); 1224 irqreturn_t result = IRQ_NONE; 1225 u32 iss; 1226 1227 spin_lock(&priv->lock); 1228 /* Get interrupt status */ 1229 iss = ravb_read(ndev, ISS); 1230 1231 /* Timestamp updated */ 1232 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1233 result = IRQ_HANDLED; 1234 1235 /* Error status summary */ 1236 if (iss & ISS_ES) { 1237 ravb_error_interrupt(ndev); 1238 result = IRQ_HANDLED; 1239 } 1240 1241 /* gPTP interrupt status summary */ 1242 if (iss & ISS_CGIS) { 1243 ravb_ptp_interrupt(ndev); 1244 result = IRQ_HANDLED; 1245 } 1246 1247 spin_unlock(&priv->lock); 1248 return result; 1249 } 1250 1251 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1252 { 1253 struct net_device *ndev = dev_id; 1254 struct ravb_private *priv = netdev_priv(ndev); 1255 irqreturn_t result = IRQ_NONE; 1256 1257 spin_lock(&priv->lock); 1258 1259 /* Network control/Best effort queue RX/TX */ 1260 if (ravb_queue_interrupt(ndev, q)) 1261 result = IRQ_HANDLED; 1262 1263 spin_unlock(&priv->lock); 1264 return result; 1265 } 1266 1267 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1268 { 1269 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1270 } 1271 1272 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1273 { 1274 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1275 } 1276 1277 static int ravb_poll(struct napi_struct *napi, int budget) 1278 { 1279 struct net_device *ndev = napi->dev; 1280 struct ravb_private *priv = netdev_priv(ndev); 1281 const struct ravb_hw_info *info = priv->info; 1282 bool gptp = info->gptp || info->ccc_gac; 1283 struct ravb_rx_desc *desc; 1284 unsigned long flags; 1285 int q = napi - priv->napi; 1286 int mask = BIT(q); 1287 int quota = budget; 1288 unsigned int entry; 1289 1290 if (!gptp) { 1291 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 1292 desc = &priv->gbeth_rx_ring[entry]; 1293 } 1294 /* Processing RX Descriptor Ring */ 1295 /* Clear RX interrupt */ 1296 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1297 if (gptp || desc->die_dt != DT_FEMPTY) { 1298 if (ravb_rx(ndev, "a, q)) 1299 goto out; 1300 } 1301 1302 /* Processing TX Descriptor Ring */ 1303 spin_lock_irqsave(&priv->lock, flags); 1304 /* Clear TX interrupt */ 1305 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1306 ravb_tx_free(ndev, q, true); 1307 netif_wake_subqueue(ndev, q); 1308 spin_unlock_irqrestore(&priv->lock, flags); 1309 1310 napi_complete(napi); 1311 1312 /* Re-enable RX/TX interrupts */ 1313 spin_lock_irqsave(&priv->lock, flags); 1314 if (!info->irq_en_dis) { 1315 ravb_modify(ndev, RIC0, mask, mask); 1316 ravb_modify(ndev, TIC, mask, mask); 1317 } else { 1318 ravb_write(ndev, mask, RIE0); 1319 ravb_write(ndev, mask, TIE); 1320 } 1321 spin_unlock_irqrestore(&priv->lock, flags); 1322 1323 /* Receive error message handling */ 1324 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1325 if (info->nc_queues) 1326 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1327 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1328 ndev->stats.rx_over_errors = priv->rx_over_errors; 1329 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1330 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1331 out: 1332 return budget - quota; 1333 } 1334 1335 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1336 { 1337 struct ravb_private *priv = netdev_priv(ndev); 1338 1339 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1340 } 1341 1342 /* PHY state control function */ 1343 static void ravb_adjust_link(struct net_device *ndev) 1344 { 1345 struct ravb_private *priv = netdev_priv(ndev); 1346 const struct ravb_hw_info *info = priv->info; 1347 struct phy_device *phydev = ndev->phydev; 1348 bool new_state = false; 1349 unsigned long flags; 1350 1351 spin_lock_irqsave(&priv->lock, flags); 1352 1353 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1354 if (priv->no_avb_link) 1355 ravb_rcv_snd_disable(ndev); 1356 1357 if (phydev->link) { 1358 if (info->half_duplex && phydev->duplex != priv->duplex) { 1359 new_state = true; 1360 priv->duplex = phydev->duplex; 1361 ravb_set_duplex_gbeth(ndev); 1362 } 1363 1364 if (phydev->speed != priv->speed) { 1365 new_state = true; 1366 priv->speed = phydev->speed; 1367 info->set_rate(ndev); 1368 } 1369 if (!priv->link) { 1370 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1371 new_state = true; 1372 priv->link = phydev->link; 1373 } 1374 } else if (priv->link) { 1375 new_state = true; 1376 priv->link = 0; 1377 priv->speed = 0; 1378 if (info->half_duplex) 1379 priv->duplex = -1; 1380 } 1381 1382 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1383 if (priv->no_avb_link && phydev->link) 1384 ravb_rcv_snd_enable(ndev); 1385 1386 spin_unlock_irqrestore(&priv->lock, flags); 1387 1388 if (new_state && netif_msg_link(priv)) 1389 phy_print_status(phydev); 1390 } 1391 1392 /* PHY init function */ 1393 static int ravb_phy_init(struct net_device *ndev) 1394 { 1395 struct device_node *np = ndev->dev.parent->of_node; 1396 struct ravb_private *priv = netdev_priv(ndev); 1397 const struct ravb_hw_info *info = priv->info; 1398 struct phy_device *phydev; 1399 struct device_node *pn; 1400 phy_interface_t iface; 1401 int err; 1402 1403 priv->link = 0; 1404 priv->speed = 0; 1405 priv->duplex = -1; 1406 1407 /* Try connecting to PHY */ 1408 pn = of_parse_phandle(np, "phy-handle", 0); 1409 if (!pn) { 1410 /* In the case of a fixed PHY, the DT node associated 1411 * to the PHY is the Ethernet MAC DT node. 1412 */ 1413 if (of_phy_is_fixed_link(np)) { 1414 err = of_phy_register_fixed_link(np); 1415 if (err) 1416 return err; 1417 } 1418 pn = of_node_get(np); 1419 } 1420 1421 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1422 : priv->phy_interface; 1423 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1424 of_node_put(pn); 1425 if (!phydev) { 1426 netdev_err(ndev, "failed to connect PHY\n"); 1427 err = -ENOENT; 1428 goto err_deregister_fixed_link; 1429 } 1430 1431 if (!info->half_duplex) { 1432 /* 10BASE, Pause and Asym Pause is not supported */ 1433 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1434 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1435 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1436 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1437 1438 /* Half Duplex is not supported */ 1439 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1440 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1441 } 1442 1443 phy_attached_info(phydev); 1444 1445 return 0; 1446 1447 err_deregister_fixed_link: 1448 if (of_phy_is_fixed_link(np)) 1449 of_phy_deregister_fixed_link(np); 1450 1451 return err; 1452 } 1453 1454 /* PHY control start function */ 1455 static int ravb_phy_start(struct net_device *ndev) 1456 { 1457 int error; 1458 1459 error = ravb_phy_init(ndev); 1460 if (error) 1461 return error; 1462 1463 phy_start(ndev->phydev); 1464 1465 return 0; 1466 } 1467 1468 static u32 ravb_get_msglevel(struct net_device *ndev) 1469 { 1470 struct ravb_private *priv = netdev_priv(ndev); 1471 1472 return priv->msg_enable; 1473 } 1474 1475 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1476 { 1477 struct ravb_private *priv = netdev_priv(ndev); 1478 1479 priv->msg_enable = value; 1480 } 1481 1482 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1483 "rx_queue_0_current", 1484 "tx_queue_0_current", 1485 "rx_queue_0_dirty", 1486 "tx_queue_0_dirty", 1487 "rx_queue_0_packets", 1488 "tx_queue_0_packets", 1489 "rx_queue_0_bytes", 1490 "tx_queue_0_bytes", 1491 "rx_queue_0_mcast_packets", 1492 "rx_queue_0_errors", 1493 "rx_queue_0_crc_errors", 1494 "rx_queue_0_frame_errors", 1495 "rx_queue_0_length_errors", 1496 "rx_queue_0_csum_offload_errors", 1497 "rx_queue_0_over_errors", 1498 }; 1499 1500 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1501 "rx_queue_0_current", 1502 "tx_queue_0_current", 1503 "rx_queue_0_dirty", 1504 "tx_queue_0_dirty", 1505 "rx_queue_0_packets", 1506 "tx_queue_0_packets", 1507 "rx_queue_0_bytes", 1508 "tx_queue_0_bytes", 1509 "rx_queue_0_mcast_packets", 1510 "rx_queue_0_errors", 1511 "rx_queue_0_crc_errors", 1512 "rx_queue_0_frame_errors", 1513 "rx_queue_0_length_errors", 1514 "rx_queue_0_missed_errors", 1515 "rx_queue_0_over_errors", 1516 1517 "rx_queue_1_current", 1518 "tx_queue_1_current", 1519 "rx_queue_1_dirty", 1520 "tx_queue_1_dirty", 1521 "rx_queue_1_packets", 1522 "tx_queue_1_packets", 1523 "rx_queue_1_bytes", 1524 "tx_queue_1_bytes", 1525 "rx_queue_1_mcast_packets", 1526 "rx_queue_1_errors", 1527 "rx_queue_1_crc_errors", 1528 "rx_queue_1_frame_errors", 1529 "rx_queue_1_length_errors", 1530 "rx_queue_1_missed_errors", 1531 "rx_queue_1_over_errors", 1532 }; 1533 1534 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1535 { 1536 struct ravb_private *priv = netdev_priv(netdev); 1537 const struct ravb_hw_info *info = priv->info; 1538 1539 switch (sset) { 1540 case ETH_SS_STATS: 1541 return info->stats_len; 1542 default: 1543 return -EOPNOTSUPP; 1544 } 1545 } 1546 1547 static void ravb_get_ethtool_stats(struct net_device *ndev, 1548 struct ethtool_stats *estats, u64 *data) 1549 { 1550 struct ravb_private *priv = netdev_priv(ndev); 1551 const struct ravb_hw_info *info = priv->info; 1552 int num_rx_q; 1553 int i = 0; 1554 int q; 1555 1556 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1557 /* Device-specific stats */ 1558 for (q = RAVB_BE; q < num_rx_q; q++) { 1559 struct net_device_stats *stats = &priv->stats[q]; 1560 1561 data[i++] = priv->cur_rx[q]; 1562 data[i++] = priv->cur_tx[q]; 1563 data[i++] = priv->dirty_rx[q]; 1564 data[i++] = priv->dirty_tx[q]; 1565 data[i++] = stats->rx_packets; 1566 data[i++] = stats->tx_packets; 1567 data[i++] = stats->rx_bytes; 1568 data[i++] = stats->tx_bytes; 1569 data[i++] = stats->multicast; 1570 data[i++] = stats->rx_errors; 1571 data[i++] = stats->rx_crc_errors; 1572 data[i++] = stats->rx_frame_errors; 1573 data[i++] = stats->rx_length_errors; 1574 data[i++] = stats->rx_missed_errors; 1575 data[i++] = stats->rx_over_errors; 1576 } 1577 } 1578 1579 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1580 { 1581 struct ravb_private *priv = netdev_priv(ndev); 1582 const struct ravb_hw_info *info = priv->info; 1583 1584 switch (stringset) { 1585 case ETH_SS_STATS: 1586 memcpy(data, info->gstrings_stats, info->gstrings_size); 1587 break; 1588 } 1589 } 1590 1591 static void ravb_get_ringparam(struct net_device *ndev, 1592 struct ethtool_ringparam *ring, 1593 struct kernel_ethtool_ringparam *kernel_ring, 1594 struct netlink_ext_ack *extack) 1595 { 1596 struct ravb_private *priv = netdev_priv(ndev); 1597 1598 ring->rx_max_pending = BE_RX_RING_MAX; 1599 ring->tx_max_pending = BE_TX_RING_MAX; 1600 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1601 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1602 } 1603 1604 static int ravb_set_ringparam(struct net_device *ndev, 1605 struct ethtool_ringparam *ring, 1606 struct kernel_ethtool_ringparam *kernel_ring, 1607 struct netlink_ext_ack *extack) 1608 { 1609 struct ravb_private *priv = netdev_priv(ndev); 1610 const struct ravb_hw_info *info = priv->info; 1611 int error; 1612 1613 if (ring->tx_pending > BE_TX_RING_MAX || 1614 ring->rx_pending > BE_RX_RING_MAX || 1615 ring->tx_pending < BE_TX_RING_MIN || 1616 ring->rx_pending < BE_RX_RING_MIN) 1617 return -EINVAL; 1618 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1619 return -EINVAL; 1620 1621 if (netif_running(ndev)) { 1622 netif_device_detach(ndev); 1623 /* Stop PTP Clock driver */ 1624 if (info->gptp) 1625 ravb_ptp_stop(ndev); 1626 /* Wait for DMA stopping */ 1627 error = ravb_stop_dma(ndev); 1628 if (error) { 1629 netdev_err(ndev, 1630 "cannot set ringparam! Any AVB processes are still running?\n"); 1631 return error; 1632 } 1633 synchronize_irq(ndev->irq); 1634 1635 /* Free all the skb's in the RX queue and the DMA buffers. */ 1636 ravb_ring_free(ndev, RAVB_BE); 1637 if (info->nc_queues) 1638 ravb_ring_free(ndev, RAVB_NC); 1639 } 1640 1641 /* Set new parameters */ 1642 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1643 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1644 1645 if (netif_running(ndev)) { 1646 error = ravb_dmac_init(ndev); 1647 if (error) { 1648 netdev_err(ndev, 1649 "%s: ravb_dmac_init() failed, error %d\n", 1650 __func__, error); 1651 return error; 1652 } 1653 1654 ravb_emac_init(ndev); 1655 1656 /* Initialise PTP Clock driver */ 1657 if (info->gptp) 1658 ravb_ptp_init(ndev, priv->pdev); 1659 1660 netif_device_attach(ndev); 1661 } 1662 1663 return 0; 1664 } 1665 1666 static int ravb_get_ts_info(struct net_device *ndev, 1667 struct ethtool_ts_info *info) 1668 { 1669 struct ravb_private *priv = netdev_priv(ndev); 1670 const struct ravb_hw_info *hw_info = priv->info; 1671 1672 info->so_timestamping = 1673 SOF_TIMESTAMPING_TX_SOFTWARE | 1674 SOF_TIMESTAMPING_RX_SOFTWARE | 1675 SOF_TIMESTAMPING_SOFTWARE | 1676 SOF_TIMESTAMPING_TX_HARDWARE | 1677 SOF_TIMESTAMPING_RX_HARDWARE | 1678 SOF_TIMESTAMPING_RAW_HARDWARE; 1679 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1680 info->rx_filters = 1681 (1 << HWTSTAMP_FILTER_NONE) | 1682 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1683 (1 << HWTSTAMP_FILTER_ALL); 1684 if (hw_info->gptp || hw_info->ccc_gac) 1685 info->phc_index = ptp_clock_index(priv->ptp.clock); 1686 1687 return 0; 1688 } 1689 1690 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1691 { 1692 struct ravb_private *priv = netdev_priv(ndev); 1693 1694 wol->supported = WAKE_MAGIC; 1695 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1696 } 1697 1698 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1699 { 1700 struct ravb_private *priv = netdev_priv(ndev); 1701 const struct ravb_hw_info *info = priv->info; 1702 1703 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1704 return -EOPNOTSUPP; 1705 1706 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1707 1708 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1709 1710 return 0; 1711 } 1712 1713 static const struct ethtool_ops ravb_ethtool_ops = { 1714 .nway_reset = phy_ethtool_nway_reset, 1715 .get_msglevel = ravb_get_msglevel, 1716 .set_msglevel = ravb_set_msglevel, 1717 .get_link = ethtool_op_get_link, 1718 .get_strings = ravb_get_strings, 1719 .get_ethtool_stats = ravb_get_ethtool_stats, 1720 .get_sset_count = ravb_get_sset_count, 1721 .get_ringparam = ravb_get_ringparam, 1722 .set_ringparam = ravb_set_ringparam, 1723 .get_ts_info = ravb_get_ts_info, 1724 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1725 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1726 .get_wol = ravb_get_wol, 1727 .set_wol = ravb_set_wol, 1728 }; 1729 1730 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1731 struct net_device *ndev, struct device *dev, 1732 const char *ch) 1733 { 1734 char *name; 1735 int error; 1736 1737 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1738 if (!name) 1739 return -ENOMEM; 1740 error = request_irq(irq, handler, 0, name, ndev); 1741 if (error) 1742 netdev_err(ndev, "cannot request IRQ %s\n", name); 1743 1744 return error; 1745 } 1746 1747 /* Network device open function for Ethernet AVB */ 1748 static int ravb_open(struct net_device *ndev) 1749 { 1750 struct ravb_private *priv = netdev_priv(ndev); 1751 const struct ravb_hw_info *info = priv->info; 1752 struct platform_device *pdev = priv->pdev; 1753 struct device *dev = &pdev->dev; 1754 int error; 1755 1756 napi_enable(&priv->napi[RAVB_BE]); 1757 if (info->nc_queues) 1758 napi_enable(&priv->napi[RAVB_NC]); 1759 1760 if (!info->multi_irqs) { 1761 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1762 ndev->name, ndev); 1763 if (error) { 1764 netdev_err(ndev, "cannot request IRQ\n"); 1765 goto out_napi_off; 1766 } 1767 } else { 1768 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1769 dev, "ch22:multi"); 1770 if (error) 1771 goto out_napi_off; 1772 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1773 dev, "ch24:emac"); 1774 if (error) 1775 goto out_free_irq; 1776 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1777 ndev, dev, "ch0:rx_be"); 1778 if (error) 1779 goto out_free_irq_emac; 1780 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1781 ndev, dev, "ch18:tx_be"); 1782 if (error) 1783 goto out_free_irq_be_rx; 1784 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1785 ndev, dev, "ch1:rx_nc"); 1786 if (error) 1787 goto out_free_irq_be_tx; 1788 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1789 ndev, dev, "ch19:tx_nc"); 1790 if (error) 1791 goto out_free_irq_nc_rx; 1792 1793 if (info->err_mgmt_irqs) { 1794 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt, 1795 ndev, dev, "err_a"); 1796 if (error) 1797 goto out_free_irq_nc_tx; 1798 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt, 1799 ndev, dev, "mgmt_a"); 1800 if (error) 1801 goto out_free_irq_erra; 1802 } 1803 } 1804 1805 /* Device init */ 1806 error = ravb_dmac_init(ndev); 1807 if (error) 1808 goto out_free_irq_mgmta; 1809 ravb_emac_init(ndev); 1810 1811 /* Initialise PTP Clock driver */ 1812 if (info->gptp) 1813 ravb_ptp_init(ndev, priv->pdev); 1814 1815 netif_tx_start_all_queues(ndev); 1816 1817 /* PHY control start */ 1818 error = ravb_phy_start(ndev); 1819 if (error) 1820 goto out_ptp_stop; 1821 1822 return 0; 1823 1824 out_ptp_stop: 1825 /* Stop PTP Clock driver */ 1826 if (info->gptp) 1827 ravb_ptp_stop(ndev); 1828 out_free_irq_mgmta: 1829 if (!info->multi_irqs) 1830 goto out_free_irq; 1831 if (info->err_mgmt_irqs) 1832 free_irq(priv->mgmta_irq, ndev); 1833 out_free_irq_erra: 1834 if (info->err_mgmt_irqs) 1835 free_irq(priv->erra_irq, ndev); 1836 out_free_irq_nc_tx: 1837 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1838 out_free_irq_nc_rx: 1839 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1840 out_free_irq_be_tx: 1841 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1842 out_free_irq_be_rx: 1843 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1844 out_free_irq_emac: 1845 free_irq(priv->emac_irq, ndev); 1846 out_free_irq: 1847 free_irq(ndev->irq, ndev); 1848 out_napi_off: 1849 if (info->nc_queues) 1850 napi_disable(&priv->napi[RAVB_NC]); 1851 napi_disable(&priv->napi[RAVB_BE]); 1852 return error; 1853 } 1854 1855 /* Timeout function for Ethernet AVB */ 1856 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1857 { 1858 struct ravb_private *priv = netdev_priv(ndev); 1859 1860 netif_err(priv, tx_err, ndev, 1861 "transmit timed out, status %08x, resetting...\n", 1862 ravb_read(ndev, ISS)); 1863 1864 /* tx_errors count up */ 1865 ndev->stats.tx_errors++; 1866 1867 schedule_work(&priv->work); 1868 } 1869 1870 static void ravb_tx_timeout_work(struct work_struct *work) 1871 { 1872 struct ravb_private *priv = container_of(work, struct ravb_private, 1873 work); 1874 const struct ravb_hw_info *info = priv->info; 1875 struct net_device *ndev = priv->ndev; 1876 int error; 1877 1878 netif_tx_stop_all_queues(ndev); 1879 1880 /* Stop PTP Clock driver */ 1881 if (info->gptp) 1882 ravb_ptp_stop(ndev); 1883 1884 /* Wait for DMA stopping */ 1885 if (ravb_stop_dma(ndev)) { 1886 /* If ravb_stop_dma() fails, the hardware is still operating 1887 * for TX and/or RX. So, this should not call the following 1888 * functions because ravb_dmac_init() is possible to fail too. 1889 * Also, this should not retry ravb_stop_dma() again and again 1890 * here because it's possible to wait forever. So, this just 1891 * re-enables the TX and RX and skip the following 1892 * re-initialization procedure. 1893 */ 1894 ravb_rcv_snd_enable(ndev); 1895 goto out; 1896 } 1897 1898 ravb_ring_free(ndev, RAVB_BE); 1899 if (info->nc_queues) 1900 ravb_ring_free(ndev, RAVB_NC); 1901 1902 /* Device init */ 1903 error = ravb_dmac_init(ndev); 1904 if (error) { 1905 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1906 * should return here to avoid re-enabling the TX and RX in 1907 * ravb_emac_init(). 1908 */ 1909 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1910 __func__, error); 1911 return; 1912 } 1913 ravb_emac_init(ndev); 1914 1915 out: 1916 /* Initialise PTP Clock driver */ 1917 if (info->gptp) 1918 ravb_ptp_init(ndev, priv->pdev); 1919 1920 netif_tx_start_all_queues(ndev); 1921 } 1922 1923 /* Packet transmit function for Ethernet AVB */ 1924 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1925 { 1926 struct ravb_private *priv = netdev_priv(ndev); 1927 const struct ravb_hw_info *info = priv->info; 1928 unsigned int num_tx_desc = priv->num_tx_desc; 1929 u16 q = skb_get_queue_mapping(skb); 1930 struct ravb_tstamp_skb *ts_skb; 1931 struct ravb_tx_desc *desc; 1932 unsigned long flags; 1933 u32 dma_addr; 1934 void *buffer; 1935 u32 entry; 1936 u32 len; 1937 1938 spin_lock_irqsave(&priv->lock, flags); 1939 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1940 num_tx_desc) { 1941 netif_err(priv, tx_queued, ndev, 1942 "still transmitting with the full ring!\n"); 1943 netif_stop_subqueue(ndev, q); 1944 spin_unlock_irqrestore(&priv->lock, flags); 1945 return NETDEV_TX_BUSY; 1946 } 1947 1948 if (skb_put_padto(skb, ETH_ZLEN)) 1949 goto exit; 1950 1951 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1952 priv->tx_skb[q][entry / num_tx_desc] = skb; 1953 1954 if (num_tx_desc > 1) { 1955 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1956 entry / num_tx_desc * DPTR_ALIGN; 1957 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1958 1959 /* Zero length DMA descriptors are problematic as they seem 1960 * to terminate DMA transfers. Avoid them by simply using a 1961 * length of DPTR_ALIGN (4) when skb data is aligned to 1962 * DPTR_ALIGN. 1963 * 1964 * As skb is guaranteed to have at least ETH_ZLEN (60) 1965 * bytes of data by the call to skb_put_padto() above this 1966 * is safe with respect to both the length of the first DMA 1967 * descriptor (len) overflowing the available data and the 1968 * length of the second DMA descriptor (skb->len - len) 1969 * being negative. 1970 */ 1971 if (len == 0) 1972 len = DPTR_ALIGN; 1973 1974 memcpy(buffer, skb->data, len); 1975 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1976 DMA_TO_DEVICE); 1977 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1978 goto drop; 1979 1980 desc = &priv->tx_ring[q][entry]; 1981 desc->ds_tagl = cpu_to_le16(len); 1982 desc->dptr = cpu_to_le32(dma_addr); 1983 1984 buffer = skb->data + len; 1985 len = skb->len - len; 1986 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1987 DMA_TO_DEVICE); 1988 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1989 goto unmap; 1990 1991 desc++; 1992 } else { 1993 desc = &priv->tx_ring[q][entry]; 1994 len = skb->len; 1995 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1996 DMA_TO_DEVICE); 1997 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1998 goto drop; 1999 } 2000 desc->ds_tagl = cpu_to_le16(len); 2001 desc->dptr = cpu_to_le32(dma_addr); 2002 2003 /* TX timestamp required */ 2004 if (info->gptp || info->ccc_gac) { 2005 if (q == RAVB_NC) { 2006 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2007 if (!ts_skb) { 2008 if (num_tx_desc > 1) { 2009 desc--; 2010 dma_unmap_single(ndev->dev.parent, dma_addr, 2011 len, DMA_TO_DEVICE); 2012 } 2013 goto unmap; 2014 } 2015 ts_skb->skb = skb_get(skb); 2016 ts_skb->tag = priv->ts_skb_tag++; 2017 priv->ts_skb_tag &= 0x3ff; 2018 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2019 2020 /* TAG and timestamp required flag */ 2021 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2022 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2023 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2024 } 2025 2026 skb_tx_timestamp(skb); 2027 } 2028 /* Descriptor type must be set after all the above writes */ 2029 dma_wmb(); 2030 if (num_tx_desc > 1) { 2031 desc->die_dt = DT_FEND; 2032 desc--; 2033 desc->die_dt = DT_FSTART; 2034 } else { 2035 desc->die_dt = DT_FSINGLE; 2036 } 2037 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2038 2039 priv->cur_tx[q] += num_tx_desc; 2040 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2041 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2042 !ravb_tx_free(ndev, q, true)) 2043 netif_stop_subqueue(ndev, q); 2044 2045 exit: 2046 spin_unlock_irqrestore(&priv->lock, flags); 2047 return NETDEV_TX_OK; 2048 2049 unmap: 2050 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2051 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2052 drop: 2053 dev_kfree_skb_any(skb); 2054 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2055 goto exit; 2056 } 2057 2058 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2059 struct net_device *sb_dev) 2060 { 2061 /* If skb needs TX timestamp, it is handled in network control queue */ 2062 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2063 RAVB_BE; 2064 2065 } 2066 2067 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2068 { 2069 struct ravb_private *priv = netdev_priv(ndev); 2070 const struct ravb_hw_info *info = priv->info; 2071 struct net_device_stats *nstats, *stats0, *stats1; 2072 2073 nstats = &ndev->stats; 2074 stats0 = &priv->stats[RAVB_BE]; 2075 2076 if (info->tx_counters) { 2077 nstats->tx_dropped += ravb_read(ndev, TROCR); 2078 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2079 } 2080 2081 if (info->carrier_counters) { 2082 nstats->collisions += ravb_read(ndev, CXR41); 2083 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2084 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2085 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2086 } 2087 2088 nstats->rx_packets = stats0->rx_packets; 2089 nstats->tx_packets = stats0->tx_packets; 2090 nstats->rx_bytes = stats0->rx_bytes; 2091 nstats->tx_bytes = stats0->tx_bytes; 2092 nstats->multicast = stats0->multicast; 2093 nstats->rx_errors = stats0->rx_errors; 2094 nstats->rx_crc_errors = stats0->rx_crc_errors; 2095 nstats->rx_frame_errors = stats0->rx_frame_errors; 2096 nstats->rx_length_errors = stats0->rx_length_errors; 2097 nstats->rx_missed_errors = stats0->rx_missed_errors; 2098 nstats->rx_over_errors = stats0->rx_over_errors; 2099 if (info->nc_queues) { 2100 stats1 = &priv->stats[RAVB_NC]; 2101 2102 nstats->rx_packets += stats1->rx_packets; 2103 nstats->tx_packets += stats1->tx_packets; 2104 nstats->rx_bytes += stats1->rx_bytes; 2105 nstats->tx_bytes += stats1->tx_bytes; 2106 nstats->multicast += stats1->multicast; 2107 nstats->rx_errors += stats1->rx_errors; 2108 nstats->rx_crc_errors += stats1->rx_crc_errors; 2109 nstats->rx_frame_errors += stats1->rx_frame_errors; 2110 nstats->rx_length_errors += stats1->rx_length_errors; 2111 nstats->rx_missed_errors += stats1->rx_missed_errors; 2112 nstats->rx_over_errors += stats1->rx_over_errors; 2113 } 2114 2115 return nstats; 2116 } 2117 2118 /* Update promiscuous bit */ 2119 static void ravb_set_rx_mode(struct net_device *ndev) 2120 { 2121 struct ravb_private *priv = netdev_priv(ndev); 2122 unsigned long flags; 2123 2124 spin_lock_irqsave(&priv->lock, flags); 2125 ravb_modify(ndev, ECMR, ECMR_PRM, 2126 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2127 spin_unlock_irqrestore(&priv->lock, flags); 2128 } 2129 2130 /* Device close function for Ethernet AVB */ 2131 static int ravb_close(struct net_device *ndev) 2132 { 2133 struct device_node *np = ndev->dev.parent->of_node; 2134 struct ravb_private *priv = netdev_priv(ndev); 2135 const struct ravb_hw_info *info = priv->info; 2136 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2137 2138 netif_tx_stop_all_queues(ndev); 2139 2140 /* Disable interrupts by clearing the interrupt masks. */ 2141 ravb_write(ndev, 0, RIC0); 2142 ravb_write(ndev, 0, RIC2); 2143 ravb_write(ndev, 0, TIC); 2144 2145 /* Stop PTP Clock driver */ 2146 if (info->gptp) 2147 ravb_ptp_stop(ndev); 2148 2149 /* Set the config mode to stop the AVB-DMAC's processes */ 2150 if (ravb_stop_dma(ndev) < 0) 2151 netdev_err(ndev, 2152 "device will be stopped after h/w processes are done.\n"); 2153 2154 /* Clear the timestamp list */ 2155 if (info->gptp || info->ccc_gac) { 2156 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2157 list_del(&ts_skb->list); 2158 kfree_skb(ts_skb->skb); 2159 kfree(ts_skb); 2160 } 2161 } 2162 2163 /* PHY disconnect */ 2164 if (ndev->phydev) { 2165 phy_stop(ndev->phydev); 2166 phy_disconnect(ndev->phydev); 2167 if (of_phy_is_fixed_link(np)) 2168 of_phy_deregister_fixed_link(np); 2169 } 2170 2171 if (info->multi_irqs) { 2172 free_irq(priv->tx_irqs[RAVB_NC], ndev); 2173 free_irq(priv->rx_irqs[RAVB_NC], ndev); 2174 free_irq(priv->tx_irqs[RAVB_BE], ndev); 2175 free_irq(priv->rx_irqs[RAVB_BE], ndev); 2176 free_irq(priv->emac_irq, ndev); 2177 if (info->err_mgmt_irqs) { 2178 free_irq(priv->erra_irq, ndev); 2179 free_irq(priv->mgmta_irq, ndev); 2180 } 2181 } 2182 free_irq(ndev->irq, ndev); 2183 2184 if (info->nc_queues) 2185 napi_disable(&priv->napi[RAVB_NC]); 2186 napi_disable(&priv->napi[RAVB_BE]); 2187 2188 /* Free all the skb's in the RX queue and the DMA buffers. */ 2189 ravb_ring_free(ndev, RAVB_BE); 2190 if (info->nc_queues) 2191 ravb_ring_free(ndev, RAVB_NC); 2192 2193 return 0; 2194 } 2195 2196 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2197 { 2198 struct ravb_private *priv = netdev_priv(ndev); 2199 struct hwtstamp_config config; 2200 2201 config.flags = 0; 2202 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2203 HWTSTAMP_TX_OFF; 2204 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2205 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2206 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2207 break; 2208 case RAVB_RXTSTAMP_TYPE_ALL: 2209 config.rx_filter = HWTSTAMP_FILTER_ALL; 2210 break; 2211 default: 2212 config.rx_filter = HWTSTAMP_FILTER_NONE; 2213 } 2214 2215 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2216 -EFAULT : 0; 2217 } 2218 2219 /* Control hardware time stamping */ 2220 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2221 { 2222 struct ravb_private *priv = netdev_priv(ndev); 2223 struct hwtstamp_config config; 2224 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2225 u32 tstamp_tx_ctrl; 2226 2227 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2228 return -EFAULT; 2229 2230 switch (config.tx_type) { 2231 case HWTSTAMP_TX_OFF: 2232 tstamp_tx_ctrl = 0; 2233 break; 2234 case HWTSTAMP_TX_ON: 2235 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2236 break; 2237 default: 2238 return -ERANGE; 2239 } 2240 2241 switch (config.rx_filter) { 2242 case HWTSTAMP_FILTER_NONE: 2243 tstamp_rx_ctrl = 0; 2244 break; 2245 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2246 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2247 break; 2248 default: 2249 config.rx_filter = HWTSTAMP_FILTER_ALL; 2250 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2251 } 2252 2253 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2254 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2255 2256 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2257 -EFAULT : 0; 2258 } 2259 2260 /* ioctl to device function */ 2261 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2262 { 2263 struct phy_device *phydev = ndev->phydev; 2264 2265 if (!netif_running(ndev)) 2266 return -EINVAL; 2267 2268 if (!phydev) 2269 return -ENODEV; 2270 2271 switch (cmd) { 2272 case SIOCGHWTSTAMP: 2273 return ravb_hwtstamp_get(ndev, req); 2274 case SIOCSHWTSTAMP: 2275 return ravb_hwtstamp_set(ndev, req); 2276 } 2277 2278 return phy_mii_ioctl(phydev, req, cmd); 2279 } 2280 2281 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2282 { 2283 struct ravb_private *priv = netdev_priv(ndev); 2284 2285 ndev->mtu = new_mtu; 2286 2287 if (netif_running(ndev)) { 2288 synchronize_irq(priv->emac_irq); 2289 ravb_emac_init(ndev); 2290 } 2291 2292 netdev_update_features(ndev); 2293 2294 return 0; 2295 } 2296 2297 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2298 { 2299 struct ravb_private *priv = netdev_priv(ndev); 2300 unsigned long flags; 2301 2302 spin_lock_irqsave(&priv->lock, flags); 2303 2304 /* Disable TX and RX */ 2305 ravb_rcv_snd_disable(ndev); 2306 2307 /* Modify RX Checksum setting */ 2308 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2309 2310 /* Enable TX and RX */ 2311 ravb_rcv_snd_enable(ndev); 2312 2313 spin_unlock_irqrestore(&priv->lock, flags); 2314 } 2315 2316 static int ravb_set_features_gbeth(struct net_device *ndev, 2317 netdev_features_t features) 2318 { 2319 /* Place holder */ 2320 return 0; 2321 } 2322 2323 static int ravb_set_features_rcar(struct net_device *ndev, 2324 netdev_features_t features) 2325 { 2326 netdev_features_t changed = ndev->features ^ features; 2327 2328 if (changed & NETIF_F_RXCSUM) 2329 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2330 2331 ndev->features = features; 2332 2333 return 0; 2334 } 2335 2336 static int ravb_set_features(struct net_device *ndev, 2337 netdev_features_t features) 2338 { 2339 struct ravb_private *priv = netdev_priv(ndev); 2340 const struct ravb_hw_info *info = priv->info; 2341 2342 return info->set_feature(ndev, features); 2343 } 2344 2345 static const struct net_device_ops ravb_netdev_ops = { 2346 .ndo_open = ravb_open, 2347 .ndo_stop = ravb_close, 2348 .ndo_start_xmit = ravb_start_xmit, 2349 .ndo_select_queue = ravb_select_queue, 2350 .ndo_get_stats = ravb_get_stats, 2351 .ndo_set_rx_mode = ravb_set_rx_mode, 2352 .ndo_tx_timeout = ravb_tx_timeout, 2353 .ndo_eth_ioctl = ravb_do_ioctl, 2354 .ndo_change_mtu = ravb_change_mtu, 2355 .ndo_validate_addr = eth_validate_addr, 2356 .ndo_set_mac_address = eth_mac_addr, 2357 .ndo_set_features = ravb_set_features, 2358 }; 2359 2360 /* MDIO bus init function */ 2361 static int ravb_mdio_init(struct ravb_private *priv) 2362 { 2363 struct platform_device *pdev = priv->pdev; 2364 struct device *dev = &pdev->dev; 2365 struct phy_device *phydev; 2366 struct device_node *pn; 2367 int error; 2368 2369 /* Bitbang init */ 2370 priv->mdiobb.ops = &bb_ops; 2371 2372 /* MII controller setting */ 2373 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2374 if (!priv->mii_bus) 2375 return -ENOMEM; 2376 2377 /* Hook up MII support for ethtool */ 2378 priv->mii_bus->name = "ravb_mii"; 2379 priv->mii_bus->parent = dev; 2380 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2381 pdev->name, pdev->id); 2382 2383 /* Register MDIO bus */ 2384 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2385 if (error) 2386 goto out_free_bus; 2387 2388 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2389 phydev = of_phy_find_device(pn); 2390 if (phydev) { 2391 phydev->mac_managed_pm = true; 2392 put_device(&phydev->mdio.dev); 2393 } 2394 of_node_put(pn); 2395 2396 return 0; 2397 2398 out_free_bus: 2399 free_mdio_bitbang(priv->mii_bus); 2400 return error; 2401 } 2402 2403 /* MDIO bus release function */ 2404 static int ravb_mdio_release(struct ravb_private *priv) 2405 { 2406 /* Unregister mdio bus */ 2407 mdiobus_unregister(priv->mii_bus); 2408 2409 /* Free bitbang info */ 2410 free_mdio_bitbang(priv->mii_bus); 2411 2412 return 0; 2413 } 2414 2415 static const struct ravb_hw_info ravb_gen3_hw_info = { 2416 .rx_ring_free = ravb_rx_ring_free_rcar, 2417 .rx_ring_format = ravb_rx_ring_format_rcar, 2418 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2419 .receive = ravb_rx_rcar, 2420 .set_rate = ravb_set_rate_rcar, 2421 .set_feature = ravb_set_features_rcar, 2422 .dmac_init = ravb_dmac_init_rcar, 2423 .emac_init = ravb_emac_init_rcar, 2424 .gstrings_stats = ravb_gstrings_stats, 2425 .gstrings_size = sizeof(ravb_gstrings_stats), 2426 .net_hw_features = NETIF_F_RXCSUM, 2427 .net_features = NETIF_F_RXCSUM, 2428 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2429 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2430 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2431 .rx_max_buf_size = SZ_2K, 2432 .internal_delay = 1, 2433 .tx_counters = 1, 2434 .multi_irqs = 1, 2435 .irq_en_dis = 1, 2436 .ccc_gac = 1, 2437 .nc_queues = 1, 2438 .magic_pkt = 1, 2439 }; 2440 2441 static const struct ravb_hw_info ravb_gen2_hw_info = { 2442 .rx_ring_free = ravb_rx_ring_free_rcar, 2443 .rx_ring_format = ravb_rx_ring_format_rcar, 2444 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2445 .receive = ravb_rx_rcar, 2446 .set_rate = ravb_set_rate_rcar, 2447 .set_feature = ravb_set_features_rcar, 2448 .dmac_init = ravb_dmac_init_rcar, 2449 .emac_init = ravb_emac_init_rcar, 2450 .gstrings_stats = ravb_gstrings_stats, 2451 .gstrings_size = sizeof(ravb_gstrings_stats), 2452 .net_hw_features = NETIF_F_RXCSUM, 2453 .net_features = NETIF_F_RXCSUM, 2454 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2455 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2456 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2457 .rx_max_buf_size = SZ_2K, 2458 .aligned_tx = 1, 2459 .gptp = 1, 2460 .nc_queues = 1, 2461 .magic_pkt = 1, 2462 }; 2463 2464 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2465 .rx_ring_free = ravb_rx_ring_free_rcar, 2466 .rx_ring_format = ravb_rx_ring_format_rcar, 2467 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2468 .receive = ravb_rx_rcar, 2469 .set_rate = ravb_set_rate_rcar, 2470 .set_feature = ravb_set_features_rcar, 2471 .dmac_init = ravb_dmac_init_rcar, 2472 .emac_init = ravb_emac_init_rcar, 2473 .gstrings_stats = ravb_gstrings_stats, 2474 .gstrings_size = sizeof(ravb_gstrings_stats), 2475 .net_hw_features = NETIF_F_RXCSUM, 2476 .net_features = NETIF_F_RXCSUM, 2477 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2478 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2479 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2480 .rx_max_buf_size = SZ_2K, 2481 .multi_irqs = 1, 2482 .err_mgmt_irqs = 1, 2483 .gptp = 1, 2484 .gptp_ref_clk = 1, 2485 .nc_queues = 1, 2486 .magic_pkt = 1, 2487 }; 2488 2489 static const struct ravb_hw_info gbeth_hw_info = { 2490 .rx_ring_free = ravb_rx_ring_free_gbeth, 2491 .rx_ring_format = ravb_rx_ring_format_gbeth, 2492 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2493 .receive = ravb_rx_gbeth, 2494 .set_rate = ravb_set_rate_gbeth, 2495 .set_feature = ravb_set_features_gbeth, 2496 .dmac_init = ravb_dmac_init_gbeth, 2497 .emac_init = ravb_emac_init_gbeth, 2498 .gstrings_stats = ravb_gstrings_stats_gbeth, 2499 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2500 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2501 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), 2502 .tccr_mask = TCCR_TSRQ0, 2503 .rx_max_buf_size = SZ_8K, 2504 .aligned_tx = 1, 2505 .tx_counters = 1, 2506 .carrier_counters = 1, 2507 .half_duplex = 1, 2508 }; 2509 2510 static const struct of_device_id ravb_match_table[] = { 2511 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2512 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2513 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2514 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2515 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2516 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info }, 2517 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2518 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2519 { } 2520 }; 2521 MODULE_DEVICE_TABLE(of, ravb_match_table); 2522 2523 static int ravb_set_gti(struct net_device *ndev) 2524 { 2525 struct ravb_private *priv = netdev_priv(ndev); 2526 const struct ravb_hw_info *info = priv->info; 2527 struct device *dev = ndev->dev.parent; 2528 unsigned long rate; 2529 uint64_t inc; 2530 2531 if (info->gptp_ref_clk) 2532 rate = clk_get_rate(priv->gptp_clk); 2533 else 2534 rate = clk_get_rate(priv->clk); 2535 if (!rate) 2536 return -EINVAL; 2537 2538 inc = div64_ul(1000000000ULL << 20, rate); 2539 2540 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 2541 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 2542 inc, GTI_TIV_MIN, GTI_TIV_MAX); 2543 return -EINVAL; 2544 } 2545 2546 ravb_write(ndev, inc, GTI); 2547 2548 return 0; 2549 } 2550 2551 static void ravb_set_config_mode(struct net_device *ndev) 2552 { 2553 struct ravb_private *priv = netdev_priv(ndev); 2554 const struct ravb_hw_info *info = priv->info; 2555 2556 if (info->gptp) { 2557 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2558 /* Set CSEL value */ 2559 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 2560 } else if (info->ccc_gac) { 2561 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 2562 CCC_GAC | CCC_CSEL_HPB); 2563 } else { 2564 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2565 } 2566 } 2567 2568 /* Set tx and rx clock internal delay modes */ 2569 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2570 { 2571 struct ravb_private *priv = netdev_priv(ndev); 2572 bool explicit_delay = false; 2573 u32 delay; 2574 2575 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2576 /* Valid values are 0 and 1800, according to DT bindings */ 2577 priv->rxcidm = !!delay; 2578 explicit_delay = true; 2579 } 2580 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2581 /* Valid values are 0 and 2000, according to DT bindings */ 2582 priv->txcidm = !!delay; 2583 explicit_delay = true; 2584 } 2585 2586 if (explicit_delay) 2587 return; 2588 2589 /* Fall back to legacy rgmii-*id behavior */ 2590 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2591 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2592 priv->rxcidm = 1; 2593 priv->rgmii_override = 1; 2594 } 2595 2596 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2597 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2598 priv->txcidm = 1; 2599 priv->rgmii_override = 1; 2600 } 2601 } 2602 2603 static void ravb_set_delay_mode(struct net_device *ndev) 2604 { 2605 struct ravb_private *priv = netdev_priv(ndev); 2606 u32 set = 0; 2607 2608 if (priv->rxcidm) 2609 set |= APSR_RDM; 2610 if (priv->txcidm) 2611 set |= APSR_TDM; 2612 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2613 } 2614 2615 static int ravb_probe(struct platform_device *pdev) 2616 { 2617 struct device_node *np = pdev->dev.of_node; 2618 const struct ravb_hw_info *info; 2619 struct reset_control *rstc; 2620 struct ravb_private *priv; 2621 struct net_device *ndev; 2622 int error, irq, q; 2623 struct resource *res; 2624 int i; 2625 2626 if (!np) { 2627 dev_err(&pdev->dev, 2628 "this driver is required to be instantiated from device tree\n"); 2629 return -EINVAL; 2630 } 2631 2632 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2633 if (IS_ERR(rstc)) 2634 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2635 "failed to get cpg reset\n"); 2636 2637 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2638 NUM_TX_QUEUE, NUM_RX_QUEUE); 2639 if (!ndev) 2640 return -ENOMEM; 2641 2642 info = of_device_get_match_data(&pdev->dev); 2643 2644 ndev->features = info->net_features; 2645 ndev->hw_features = info->net_hw_features; 2646 2647 reset_control_deassert(rstc); 2648 pm_runtime_enable(&pdev->dev); 2649 pm_runtime_get_sync(&pdev->dev); 2650 2651 if (info->multi_irqs) { 2652 if (info->err_mgmt_irqs) 2653 irq = platform_get_irq_byname(pdev, "dia"); 2654 else 2655 irq = platform_get_irq_byname(pdev, "ch22"); 2656 } else { 2657 irq = platform_get_irq(pdev, 0); 2658 } 2659 if (irq < 0) { 2660 error = irq; 2661 goto out_release; 2662 } 2663 ndev->irq = irq; 2664 2665 SET_NETDEV_DEV(ndev, &pdev->dev); 2666 2667 priv = netdev_priv(ndev); 2668 priv->info = info; 2669 priv->rstc = rstc; 2670 priv->ndev = ndev; 2671 priv->pdev = pdev; 2672 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2673 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2674 if (info->nc_queues) { 2675 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2676 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2677 } 2678 2679 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2680 if (IS_ERR(priv->addr)) { 2681 error = PTR_ERR(priv->addr); 2682 goto out_release; 2683 } 2684 2685 /* The Ether-specific entries in the device structure. */ 2686 ndev->base_addr = res->start; 2687 2688 spin_lock_init(&priv->lock); 2689 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2690 2691 error = of_get_phy_mode(np, &priv->phy_interface); 2692 if (error && error != -ENODEV) 2693 goto out_release; 2694 2695 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2696 priv->avb_link_active_low = 2697 of_property_read_bool(np, "renesas,ether-link-active-low"); 2698 2699 if (info->multi_irqs) { 2700 if (info->err_mgmt_irqs) 2701 irq = platform_get_irq_byname(pdev, "line3"); 2702 else 2703 irq = platform_get_irq_byname(pdev, "ch24"); 2704 if (irq < 0) { 2705 error = irq; 2706 goto out_release; 2707 } 2708 priv->emac_irq = irq; 2709 for (i = 0; i < NUM_RX_QUEUE; i++) { 2710 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2711 if (irq < 0) { 2712 error = irq; 2713 goto out_release; 2714 } 2715 priv->rx_irqs[i] = irq; 2716 } 2717 for (i = 0; i < NUM_TX_QUEUE; i++) { 2718 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2719 if (irq < 0) { 2720 error = irq; 2721 goto out_release; 2722 } 2723 priv->tx_irqs[i] = irq; 2724 } 2725 2726 if (info->err_mgmt_irqs) { 2727 irq = platform_get_irq_byname(pdev, "err_a"); 2728 if (irq < 0) { 2729 error = irq; 2730 goto out_release; 2731 } 2732 priv->erra_irq = irq; 2733 2734 irq = platform_get_irq_byname(pdev, "mgmt_a"); 2735 if (irq < 0) { 2736 error = irq; 2737 goto out_release; 2738 } 2739 priv->mgmta_irq = irq; 2740 } 2741 } 2742 2743 priv->clk = devm_clk_get(&pdev->dev, NULL); 2744 if (IS_ERR(priv->clk)) { 2745 error = PTR_ERR(priv->clk); 2746 goto out_release; 2747 } 2748 2749 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2750 if (IS_ERR(priv->refclk)) { 2751 error = PTR_ERR(priv->refclk); 2752 goto out_release; 2753 } 2754 clk_prepare_enable(priv->refclk); 2755 2756 if (info->gptp_ref_clk) { 2757 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2758 if (IS_ERR(priv->gptp_clk)) { 2759 error = PTR_ERR(priv->gptp_clk); 2760 goto out_disable_refclk; 2761 } 2762 clk_prepare_enable(priv->gptp_clk); 2763 } 2764 2765 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2766 ndev->min_mtu = ETH_MIN_MTU; 2767 2768 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2769 * Use two descriptor to handle such situation. First descriptor to 2770 * handle aligned data buffer and second descriptor to handle the 2771 * overflow data because of alignment. 2772 */ 2773 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2774 2775 /* Set function */ 2776 ndev->netdev_ops = &ravb_netdev_ops; 2777 ndev->ethtool_ops = &ravb_ethtool_ops; 2778 2779 /* Set AVB config mode */ 2780 ravb_set_config_mode(ndev); 2781 2782 if (info->gptp || info->ccc_gac) { 2783 /* Set GTI value */ 2784 error = ravb_set_gti(ndev); 2785 if (error) 2786 goto out_disable_gptp_clk; 2787 2788 /* Request GTI loading */ 2789 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2790 } 2791 2792 if (info->internal_delay) { 2793 ravb_parse_delay_mode(np, ndev); 2794 ravb_set_delay_mode(ndev); 2795 } 2796 2797 /* Allocate descriptor base address table */ 2798 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2799 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2800 &priv->desc_bat_dma, GFP_KERNEL); 2801 if (!priv->desc_bat) { 2802 dev_err(&pdev->dev, 2803 "Cannot allocate desc base address table (size %d bytes)\n", 2804 priv->desc_bat_size); 2805 error = -ENOMEM; 2806 goto out_disable_gptp_clk; 2807 } 2808 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2809 priv->desc_bat[q].die_dt = DT_EOS; 2810 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2811 2812 /* Initialise HW timestamp list */ 2813 INIT_LIST_HEAD(&priv->ts_skb_list); 2814 2815 /* Initialise PTP Clock driver */ 2816 if (info->ccc_gac) 2817 ravb_ptp_init(ndev, pdev); 2818 2819 /* Debug message level */ 2820 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2821 2822 /* Read and set MAC address */ 2823 ravb_read_mac_address(np, ndev); 2824 if (!is_valid_ether_addr(ndev->dev_addr)) { 2825 dev_warn(&pdev->dev, 2826 "no valid MAC address supplied, using a random one\n"); 2827 eth_hw_addr_random(ndev); 2828 } 2829 2830 /* MDIO bus init */ 2831 error = ravb_mdio_init(priv); 2832 if (error) { 2833 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2834 goto out_dma_free; 2835 } 2836 2837 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 2838 if (info->nc_queues) 2839 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 2840 2841 /* Network device register */ 2842 error = register_netdev(ndev); 2843 if (error) 2844 goto out_napi_del; 2845 2846 device_set_wakeup_capable(&pdev->dev, 1); 2847 2848 /* Print device information */ 2849 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2850 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2851 2852 platform_set_drvdata(pdev, ndev); 2853 2854 return 0; 2855 2856 out_napi_del: 2857 if (info->nc_queues) 2858 netif_napi_del(&priv->napi[RAVB_NC]); 2859 2860 netif_napi_del(&priv->napi[RAVB_BE]); 2861 ravb_mdio_release(priv); 2862 out_dma_free: 2863 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2864 priv->desc_bat_dma); 2865 2866 /* Stop PTP Clock driver */ 2867 if (info->ccc_gac) 2868 ravb_ptp_stop(ndev); 2869 out_disable_gptp_clk: 2870 clk_disable_unprepare(priv->gptp_clk); 2871 out_disable_refclk: 2872 clk_disable_unprepare(priv->refclk); 2873 out_release: 2874 free_netdev(ndev); 2875 2876 pm_runtime_put(&pdev->dev); 2877 pm_runtime_disable(&pdev->dev); 2878 reset_control_assert(rstc); 2879 return error; 2880 } 2881 2882 static int ravb_remove(struct platform_device *pdev) 2883 { 2884 struct net_device *ndev = platform_get_drvdata(pdev); 2885 struct ravb_private *priv = netdev_priv(ndev); 2886 const struct ravb_hw_info *info = priv->info; 2887 2888 /* Stop PTP Clock driver */ 2889 if (info->ccc_gac) 2890 ravb_ptp_stop(ndev); 2891 2892 clk_disable_unprepare(priv->gptp_clk); 2893 clk_disable_unprepare(priv->refclk); 2894 2895 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2896 priv->desc_bat_dma); 2897 /* Set reset mode */ 2898 ravb_write(ndev, CCC_OPC_RESET, CCC); 2899 unregister_netdev(ndev); 2900 if (info->nc_queues) 2901 netif_napi_del(&priv->napi[RAVB_NC]); 2902 netif_napi_del(&priv->napi[RAVB_BE]); 2903 ravb_mdio_release(priv); 2904 pm_runtime_put_sync(&pdev->dev); 2905 pm_runtime_disable(&pdev->dev); 2906 reset_control_assert(priv->rstc); 2907 free_netdev(ndev); 2908 platform_set_drvdata(pdev, NULL); 2909 2910 return 0; 2911 } 2912 2913 static int ravb_wol_setup(struct net_device *ndev) 2914 { 2915 struct ravb_private *priv = netdev_priv(ndev); 2916 const struct ravb_hw_info *info = priv->info; 2917 2918 /* Disable interrupts by clearing the interrupt masks. */ 2919 ravb_write(ndev, 0, RIC0); 2920 ravb_write(ndev, 0, RIC2); 2921 ravb_write(ndev, 0, TIC); 2922 2923 /* Only allow ECI interrupts */ 2924 synchronize_irq(priv->emac_irq); 2925 if (info->nc_queues) 2926 napi_disable(&priv->napi[RAVB_NC]); 2927 napi_disable(&priv->napi[RAVB_BE]); 2928 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2929 2930 /* Enable MagicPacket */ 2931 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2932 2933 return enable_irq_wake(priv->emac_irq); 2934 } 2935 2936 static int ravb_wol_restore(struct net_device *ndev) 2937 { 2938 struct ravb_private *priv = netdev_priv(ndev); 2939 const struct ravb_hw_info *info = priv->info; 2940 2941 if (info->nc_queues) 2942 napi_enable(&priv->napi[RAVB_NC]); 2943 napi_enable(&priv->napi[RAVB_BE]); 2944 2945 /* Disable MagicPacket */ 2946 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2947 2948 ravb_close(ndev); 2949 2950 return disable_irq_wake(priv->emac_irq); 2951 } 2952 2953 static int __maybe_unused ravb_suspend(struct device *dev) 2954 { 2955 struct net_device *ndev = dev_get_drvdata(dev); 2956 struct ravb_private *priv = netdev_priv(ndev); 2957 int ret; 2958 2959 if (!netif_running(ndev)) 2960 return 0; 2961 2962 netif_device_detach(ndev); 2963 2964 if (priv->wol_enabled) 2965 ret = ravb_wol_setup(ndev); 2966 else 2967 ret = ravb_close(ndev); 2968 2969 if (priv->info->ccc_gac) 2970 ravb_ptp_stop(ndev); 2971 2972 return ret; 2973 } 2974 2975 static int __maybe_unused ravb_resume(struct device *dev) 2976 { 2977 struct net_device *ndev = dev_get_drvdata(dev); 2978 struct ravb_private *priv = netdev_priv(ndev); 2979 const struct ravb_hw_info *info = priv->info; 2980 int ret = 0; 2981 2982 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2983 if (priv->wol_enabled) 2984 ravb_write(ndev, CCC_OPC_RESET, CCC); 2985 2986 /* All register have been reset to default values. 2987 * Restore all registers which where setup at probe time and 2988 * reopen device if it was running before system suspended. 2989 */ 2990 2991 /* Set AVB config mode */ 2992 ravb_set_config_mode(ndev); 2993 2994 if (info->gptp || info->ccc_gac) { 2995 /* Set GTI value */ 2996 ret = ravb_set_gti(ndev); 2997 if (ret) 2998 return ret; 2999 3000 /* Request GTI loading */ 3001 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 3002 } 3003 3004 if (info->internal_delay) 3005 ravb_set_delay_mode(ndev); 3006 3007 /* Restore descriptor base address table */ 3008 ravb_write(ndev, priv->desc_bat_dma, DBAT); 3009 3010 if (priv->info->ccc_gac) 3011 ravb_ptp_init(ndev, priv->pdev); 3012 3013 if (netif_running(ndev)) { 3014 if (priv->wol_enabled) { 3015 ret = ravb_wol_restore(ndev); 3016 if (ret) 3017 return ret; 3018 } 3019 ret = ravb_open(ndev); 3020 if (ret < 0) 3021 return ret; 3022 ravb_set_rx_mode(ndev); 3023 netif_device_attach(ndev); 3024 } 3025 3026 return ret; 3027 } 3028 3029 static int __maybe_unused ravb_runtime_nop(struct device *dev) 3030 { 3031 /* Runtime PM callback shared between ->runtime_suspend() 3032 * and ->runtime_resume(). Simply returns success. 3033 * 3034 * This driver re-initializes all registers after 3035 * pm_runtime_get_sync() anyway so there is no need 3036 * to save and restore registers here. 3037 */ 3038 return 0; 3039 } 3040 3041 static const struct dev_pm_ops ravb_dev_pm_ops = { 3042 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3043 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 3044 }; 3045 3046 static struct platform_driver ravb_driver = { 3047 .probe = ravb_probe, 3048 .remove = ravb_remove, 3049 .driver = { 3050 .name = "ravb", 3051 .pm = &ravb_dev_pm_ops, 3052 .of_match_table = ravb_match_table, 3053 }, 3054 }; 3055 3056 module_platform_driver(ravb_driver); 3057 3058 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3059 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3060 MODULE_LICENSE("GPL v2"); 3061