1 /* Renesas Ethernet AVB device driver 2 * 3 * Copyright (C) 2014-2015 Renesas Electronics Corporation 4 * Copyright (C) 2015 Renesas Solutions Corp. 5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com> 6 * 7 * Based on the SuperH Ethernet driver 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License version 2, 11 * as published by the Free Software Foundation. 12 */ 13 14 #include <linux/cache.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/err.h> 19 #include <linux/etherdevice.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/kernel.h> 23 #include <linux/list.h> 24 #include <linux/module.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_mdio.h> 30 #include <linux/of_net.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 35 #include <asm/div64.h> 36 37 #include "ravb.h" 38 39 #define RAVB_DEF_MSG_ENABLE \ 40 (NETIF_MSG_LINK | \ 41 NETIF_MSG_TIMER | \ 42 NETIF_MSG_RX_ERR | \ 43 NETIF_MSG_TX_ERR) 44 45 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 46 { 47 int i; 48 49 for (i = 0; i < 10000; i++) { 50 if ((ravb_read(ndev, reg) & mask) == value) 51 return 0; 52 udelay(10); 53 } 54 return -ETIMEDOUT; 55 } 56 57 static int ravb_config(struct net_device *ndev) 58 { 59 int error; 60 61 /* Set config mode */ 62 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG, 63 CCC); 64 /* Check if the operating mode is changed to the config mode */ 65 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 66 if (error) 67 netdev_err(ndev, "failed to switch device to config mode\n"); 68 69 return error; 70 } 71 72 static void ravb_set_duplex(struct net_device *ndev) 73 { 74 struct ravb_private *priv = netdev_priv(ndev); 75 u32 ecmr = ravb_read(ndev, ECMR); 76 77 if (priv->duplex) /* Full */ 78 ecmr |= ECMR_DM; 79 else /* Half */ 80 ecmr &= ~ECMR_DM; 81 ravb_write(ndev, ecmr, ECMR); 82 } 83 84 static void ravb_set_rate(struct net_device *ndev) 85 { 86 struct ravb_private *priv = netdev_priv(ndev); 87 88 switch (priv->speed) { 89 case 100: /* 100BASE */ 90 ravb_write(ndev, GECMR_SPEED_100, GECMR); 91 break; 92 case 1000: /* 1000BASE */ 93 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 94 break; 95 default: 96 break; 97 } 98 } 99 100 static void ravb_set_buffer_align(struct sk_buff *skb) 101 { 102 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 103 104 if (reserve) 105 skb_reserve(skb, RAVB_ALIGN - reserve); 106 } 107 108 /* Get MAC address from the MAC address registers 109 * 110 * Ethernet AVB device doesn't have ROM for MAC address. 111 * This function gets the MAC address that was used by a bootloader. 112 */ 113 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 114 { 115 if (mac) { 116 ether_addr_copy(ndev->dev_addr, mac); 117 } else { 118 ndev->dev_addr[0] = (ravb_read(ndev, MAHR) >> 24); 119 ndev->dev_addr[1] = (ravb_read(ndev, MAHR) >> 16) & 0xFF; 120 ndev->dev_addr[2] = (ravb_read(ndev, MAHR) >> 8) & 0xFF; 121 ndev->dev_addr[3] = (ravb_read(ndev, MAHR) >> 0) & 0xFF; 122 ndev->dev_addr[4] = (ravb_read(ndev, MALR) >> 8) & 0xFF; 123 ndev->dev_addr[5] = (ravb_read(ndev, MALR) >> 0) & 0xFF; 124 } 125 } 126 127 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 128 { 129 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 130 mdiobb); 131 u32 pir = ravb_read(priv->ndev, PIR); 132 133 if (set) 134 pir |= mask; 135 else 136 pir &= ~mask; 137 ravb_write(priv->ndev, pir, PIR); 138 } 139 140 /* MDC pin control */ 141 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 142 { 143 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 144 } 145 146 /* Data I/O pin control */ 147 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 148 { 149 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 150 } 151 152 /* Set data bit */ 153 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 154 { 155 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 156 } 157 158 /* Get data bit */ 159 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 160 { 161 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 162 mdiobb); 163 164 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 165 } 166 167 /* MDIO bus control struct */ 168 static struct mdiobb_ops bb_ops = { 169 .owner = THIS_MODULE, 170 .set_mdc = ravb_set_mdc, 171 .set_mdio_dir = ravb_set_mdio_dir, 172 .set_mdio_data = ravb_set_mdio_data, 173 .get_mdio_data = ravb_get_mdio_data, 174 }; 175 176 /* Free skb's and DMA buffers for Ethernet AVB */ 177 static void ravb_ring_free(struct net_device *ndev, int q) 178 { 179 struct ravb_private *priv = netdev_priv(ndev); 180 int ring_size; 181 int i; 182 183 /* Free RX skb ringbuffer */ 184 if (priv->rx_skb[q]) { 185 for (i = 0; i < priv->num_rx_ring[q]; i++) 186 dev_kfree_skb(priv->rx_skb[q][i]); 187 } 188 kfree(priv->rx_skb[q]); 189 priv->rx_skb[q] = NULL; 190 191 /* Free TX skb ringbuffer */ 192 if (priv->tx_skb[q]) { 193 for (i = 0; i < priv->num_tx_ring[q]; i++) 194 dev_kfree_skb(priv->tx_skb[q][i]); 195 } 196 kfree(priv->tx_skb[q]); 197 priv->tx_skb[q] = NULL; 198 199 /* Free aligned TX buffers */ 200 kfree(priv->tx_align[q]); 201 priv->tx_align[q] = NULL; 202 203 if (priv->rx_ring[q]) { 204 ring_size = sizeof(struct ravb_ex_rx_desc) * 205 (priv->num_rx_ring[q] + 1); 206 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 207 priv->rx_desc_dma[q]); 208 priv->rx_ring[q] = NULL; 209 } 210 211 if (priv->tx_ring[q]) { 212 ring_size = sizeof(struct ravb_tx_desc) * 213 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 214 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 215 priv->tx_desc_dma[q]); 216 priv->tx_ring[q] = NULL; 217 } 218 } 219 220 /* Format skb and descriptor buffer for Ethernet AVB */ 221 static void ravb_ring_format(struct net_device *ndev, int q) 222 { 223 struct ravb_private *priv = netdev_priv(ndev); 224 struct ravb_ex_rx_desc *rx_desc; 225 struct ravb_tx_desc *tx_desc; 226 struct ravb_desc *desc; 227 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 228 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 229 NUM_TX_DESC; 230 dma_addr_t dma_addr; 231 int i; 232 233 priv->cur_rx[q] = 0; 234 priv->cur_tx[q] = 0; 235 priv->dirty_rx[q] = 0; 236 priv->dirty_tx[q] = 0; 237 238 memset(priv->rx_ring[q], 0, rx_ring_size); 239 /* Build RX ring buffer */ 240 for (i = 0; i < priv->num_rx_ring[q]; i++) { 241 /* RX descriptor */ 242 rx_desc = &priv->rx_ring[q][i]; 243 /* The size of the buffer should be on 16-byte boundary. */ 244 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); 245 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 246 ALIGN(PKT_BUF_SZ, 16), 247 DMA_FROM_DEVICE); 248 /* We just set the data size to 0 for a failed mapping which 249 * should prevent DMA from happening... 250 */ 251 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 252 rx_desc->ds_cc = cpu_to_le16(0); 253 rx_desc->dptr = cpu_to_le32(dma_addr); 254 rx_desc->die_dt = DT_FEMPTY; 255 } 256 rx_desc = &priv->rx_ring[q][i]; 257 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 258 rx_desc->die_dt = DT_LINKFIX; /* type */ 259 260 memset(priv->tx_ring[q], 0, tx_ring_size); 261 /* Build TX ring buffer */ 262 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 263 i++, tx_desc++) { 264 tx_desc->die_dt = DT_EEMPTY; 265 tx_desc++; 266 tx_desc->die_dt = DT_EEMPTY; 267 } 268 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 269 tx_desc->die_dt = DT_LINKFIX; /* type */ 270 271 /* RX descriptor base address for best effort */ 272 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 273 desc->die_dt = DT_LINKFIX; /* type */ 274 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 275 276 /* TX descriptor base address for best effort */ 277 desc = &priv->desc_bat[q]; 278 desc->die_dt = DT_LINKFIX; /* type */ 279 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 280 } 281 282 /* Init skb and descriptor buffer for Ethernet AVB */ 283 static int ravb_ring_init(struct net_device *ndev, int q) 284 { 285 struct ravb_private *priv = netdev_priv(ndev); 286 struct sk_buff *skb; 287 int ring_size; 288 int i; 289 290 /* Allocate RX and TX skb rings */ 291 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 292 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 293 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 294 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 295 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 296 goto error; 297 298 for (i = 0; i < priv->num_rx_ring[q]; i++) { 299 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); 300 if (!skb) 301 goto error; 302 ravb_set_buffer_align(skb); 303 priv->rx_skb[q][i] = skb; 304 } 305 306 /* Allocate rings for the aligned buffers */ 307 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 308 DPTR_ALIGN - 1, GFP_KERNEL); 309 if (!priv->tx_align[q]) 310 goto error; 311 312 /* Allocate all RX descriptors. */ 313 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 314 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 315 &priv->rx_desc_dma[q], 316 GFP_KERNEL); 317 if (!priv->rx_ring[q]) 318 goto error; 319 320 priv->dirty_rx[q] = 0; 321 322 /* Allocate all TX descriptors. */ 323 ring_size = sizeof(struct ravb_tx_desc) * 324 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 325 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 326 &priv->tx_desc_dma[q], 327 GFP_KERNEL); 328 if (!priv->tx_ring[q]) 329 goto error; 330 331 return 0; 332 333 error: 334 ravb_ring_free(ndev, q); 335 336 return -ENOMEM; 337 } 338 339 /* E-MAC init function */ 340 static void ravb_emac_init(struct net_device *ndev) 341 { 342 struct ravb_private *priv = netdev_priv(ndev); 343 u32 ecmr; 344 345 /* Receive frame limit set register */ 346 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 347 348 /* PAUSE prohibition */ 349 ecmr = ravb_read(ndev, ECMR); 350 ecmr &= ECMR_DM; 351 ecmr |= ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 352 ravb_write(ndev, ecmr, ECMR); 353 354 ravb_set_rate(ndev); 355 356 /* Set MAC address */ 357 ravb_write(ndev, 358 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 359 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 360 ravb_write(ndev, 361 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 362 363 ravb_write(ndev, 1, MPR); 364 365 /* E-MAC status register clear */ 366 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 367 368 /* E-MAC interrupt enable register */ 369 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 370 } 371 372 /* Device init function for Ethernet AVB */ 373 static int ravb_dmac_init(struct net_device *ndev) 374 { 375 int error; 376 377 /* Set CONFIG mode */ 378 error = ravb_config(ndev); 379 if (error) 380 return error; 381 382 error = ravb_ring_init(ndev, RAVB_BE); 383 if (error) 384 return error; 385 error = ravb_ring_init(ndev, RAVB_NC); 386 if (error) { 387 ravb_ring_free(ndev, RAVB_BE); 388 return error; 389 } 390 391 /* Descriptor format */ 392 ravb_ring_format(ndev, RAVB_BE); 393 ravb_ring_format(ndev, RAVB_NC); 394 395 #if defined(__LITTLE_ENDIAN) 396 ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC); 397 #else 398 ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC); 399 #endif 400 401 /* Set AVB RX */ 402 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR); 403 404 /* Set FIFO size */ 405 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 406 407 /* Timestamp enable */ 408 ravb_write(ndev, TCCR_TFEN, TCCR); 409 410 /* Interrupt enable: */ 411 /* Frame receive */ 412 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 413 /* Receive FIFO full error, descriptor empty */ 414 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 415 /* Frame transmitted, timestamp FIFO updated */ 416 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 417 418 /* Setting the control will start the AVB-DMAC process. */ 419 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION, 420 CCC); 421 422 return 0; 423 } 424 425 /* Free TX skb function for AVB-IP */ 426 static int ravb_tx_free(struct net_device *ndev, int q) 427 { 428 struct ravb_private *priv = netdev_priv(ndev); 429 struct net_device_stats *stats = &priv->stats[q]; 430 struct ravb_tx_desc *desc; 431 int free_num = 0; 432 int entry; 433 u32 size; 434 435 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 436 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 437 NUM_TX_DESC); 438 desc = &priv->tx_ring[q][entry]; 439 if (desc->die_dt != DT_FEMPTY) 440 break; 441 /* Descriptor type must be checked before all other reads */ 442 dma_rmb(); 443 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 444 /* Free the original skb. */ 445 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 446 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 447 size, DMA_TO_DEVICE); 448 /* Last packet descriptor? */ 449 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 450 entry /= NUM_TX_DESC; 451 dev_kfree_skb_any(priv->tx_skb[q][entry]); 452 priv->tx_skb[q][entry] = NULL; 453 stats->tx_packets++; 454 } 455 free_num++; 456 } 457 stats->tx_bytes += size; 458 desc->die_dt = DT_EEMPTY; 459 } 460 return free_num; 461 } 462 463 static void ravb_get_tx_tstamp(struct net_device *ndev) 464 { 465 struct ravb_private *priv = netdev_priv(ndev); 466 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 467 struct skb_shared_hwtstamps shhwtstamps; 468 struct sk_buff *skb; 469 struct timespec64 ts; 470 u16 tag, tfa_tag; 471 int count; 472 u32 tfa2; 473 474 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 475 while (count--) { 476 tfa2 = ravb_read(ndev, TFA2); 477 tfa_tag = (tfa2 & TFA2_TST) >> 16; 478 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 479 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 480 ravb_read(ndev, TFA1); 481 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 482 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 483 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 484 list) { 485 skb = ts_skb->skb; 486 tag = ts_skb->tag; 487 list_del(&ts_skb->list); 488 kfree(ts_skb); 489 if (tag == tfa_tag) { 490 skb_tstamp_tx(skb, &shhwtstamps); 491 break; 492 } 493 } 494 ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR); 495 } 496 } 497 498 /* Packet receive function for Ethernet AVB */ 499 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 500 { 501 struct ravb_private *priv = netdev_priv(ndev); 502 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 503 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 504 priv->cur_rx[q]; 505 struct net_device_stats *stats = &priv->stats[q]; 506 struct ravb_ex_rx_desc *desc; 507 struct sk_buff *skb; 508 dma_addr_t dma_addr; 509 struct timespec64 ts; 510 u8 desc_status; 511 u16 pkt_len; 512 int limit; 513 514 boguscnt = min(boguscnt, *quota); 515 limit = boguscnt; 516 desc = &priv->rx_ring[q][entry]; 517 while (desc->die_dt != DT_FEMPTY) { 518 /* Descriptor type must be checked before all other reads */ 519 dma_rmb(); 520 desc_status = desc->msc; 521 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 522 523 if (--boguscnt < 0) 524 break; 525 526 /* We use 0-byte descriptors to mark the DMA mapping errors */ 527 if (!pkt_len) 528 continue; 529 530 if (desc_status & MSC_MC) 531 stats->multicast++; 532 533 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 534 MSC_CEEF)) { 535 stats->rx_errors++; 536 if (desc_status & MSC_CRC) 537 stats->rx_crc_errors++; 538 if (desc_status & MSC_RFE) 539 stats->rx_frame_errors++; 540 if (desc_status & (MSC_RTLF | MSC_RTSF)) 541 stats->rx_length_errors++; 542 if (desc_status & MSC_CEEF) 543 stats->rx_missed_errors++; 544 } else { 545 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 546 547 skb = priv->rx_skb[q][entry]; 548 priv->rx_skb[q][entry] = NULL; 549 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 550 ALIGN(PKT_BUF_SZ, 16), 551 DMA_FROM_DEVICE); 552 get_ts &= (q == RAVB_NC) ? 553 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 554 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 555 if (get_ts) { 556 struct skb_shared_hwtstamps *shhwtstamps; 557 558 shhwtstamps = skb_hwtstamps(skb); 559 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 560 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 561 32) | le32_to_cpu(desc->ts_sl); 562 ts.tv_nsec = le32_to_cpu(desc->ts_n); 563 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 564 } 565 skb_put(skb, pkt_len); 566 skb->protocol = eth_type_trans(skb, ndev); 567 napi_gro_receive(&priv->napi[q], skb); 568 stats->rx_packets++; 569 stats->rx_bytes += pkt_len; 570 } 571 572 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 573 desc = &priv->rx_ring[q][entry]; 574 } 575 576 /* Refill the RX ring buffers. */ 577 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 578 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 579 desc = &priv->rx_ring[q][entry]; 580 /* The size of the buffer should be on 16-byte boundary. */ 581 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); 582 583 if (!priv->rx_skb[q][entry]) { 584 skb = netdev_alloc_skb(ndev, 585 PKT_BUF_SZ + RAVB_ALIGN - 1); 586 if (!skb) 587 break; /* Better luck next round. */ 588 ravb_set_buffer_align(skb); 589 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 590 le16_to_cpu(desc->ds_cc), 591 DMA_FROM_DEVICE); 592 skb_checksum_none_assert(skb); 593 /* We just set the data size to 0 for a failed mapping 594 * which should prevent DMA from happening... 595 */ 596 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 597 desc->ds_cc = cpu_to_le16(0); 598 desc->dptr = cpu_to_le32(dma_addr); 599 priv->rx_skb[q][entry] = skb; 600 } 601 /* Descriptor type must be set after all the above writes */ 602 dma_wmb(); 603 desc->die_dt = DT_FEMPTY; 604 } 605 606 *quota -= limit - (++boguscnt); 607 608 return boguscnt <= 0; 609 } 610 611 static void ravb_rcv_snd_disable(struct net_device *ndev) 612 { 613 /* Disable TX and RX */ 614 ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR); 615 } 616 617 static void ravb_rcv_snd_enable(struct net_device *ndev) 618 { 619 /* Enable TX and RX */ 620 ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR); 621 } 622 623 /* function for waiting dma process finished */ 624 static int ravb_stop_dma(struct net_device *ndev) 625 { 626 int error; 627 628 /* Wait for stopping the hardware TX process */ 629 error = ravb_wait(ndev, TCCR, 630 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 631 if (error) 632 return error; 633 634 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 635 0); 636 if (error) 637 return error; 638 639 /* Stop the E-MAC's RX/TX processes. */ 640 ravb_rcv_snd_disable(ndev); 641 642 /* Wait for stopping the RX DMA process */ 643 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 644 if (error) 645 return error; 646 647 /* Stop AVB-DMAC process */ 648 return ravb_config(ndev); 649 } 650 651 /* E-MAC interrupt handler */ 652 static void ravb_emac_interrupt(struct net_device *ndev) 653 { 654 struct ravb_private *priv = netdev_priv(ndev); 655 u32 ecsr, psr; 656 657 ecsr = ravb_read(ndev, ECSR); 658 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 659 if (ecsr & ECSR_ICD) 660 ndev->stats.tx_carrier_errors++; 661 if (ecsr & ECSR_LCHNG) { 662 /* Link changed */ 663 if (priv->no_avb_link) 664 return; 665 psr = ravb_read(ndev, PSR); 666 if (priv->avb_link_active_low) 667 psr ^= PSR_LMON; 668 if (!(psr & PSR_LMON)) { 669 /* DIsable RX and TX */ 670 ravb_rcv_snd_disable(ndev); 671 } else { 672 /* Enable RX and TX */ 673 ravb_rcv_snd_enable(ndev); 674 } 675 } 676 } 677 678 /* Error interrupt handler */ 679 static void ravb_error_interrupt(struct net_device *ndev) 680 { 681 struct ravb_private *priv = netdev_priv(ndev); 682 u32 eis, ris2; 683 684 eis = ravb_read(ndev, EIS); 685 ravb_write(ndev, ~EIS_QFS, EIS); 686 if (eis & EIS_QFS) { 687 ris2 = ravb_read(ndev, RIS2); 688 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); 689 690 /* Receive Descriptor Empty int */ 691 if (ris2 & RIS2_QFF0) 692 priv->stats[RAVB_BE].rx_over_errors++; 693 694 /* Receive Descriptor Empty int */ 695 if (ris2 & RIS2_QFF1) 696 priv->stats[RAVB_NC].rx_over_errors++; 697 698 /* Receive FIFO Overflow int */ 699 if (ris2 & RIS2_RFFF) 700 priv->rx_fifo_errors++; 701 } 702 } 703 704 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 705 { 706 struct net_device *ndev = dev_id; 707 struct ravb_private *priv = netdev_priv(ndev); 708 irqreturn_t result = IRQ_NONE; 709 u32 iss; 710 711 spin_lock(&priv->lock); 712 /* Get interrupt status */ 713 iss = ravb_read(ndev, ISS); 714 715 /* Received and transmitted interrupts */ 716 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 717 u32 ris0 = ravb_read(ndev, RIS0); 718 u32 ric0 = ravb_read(ndev, RIC0); 719 u32 tis = ravb_read(ndev, TIS); 720 u32 tic = ravb_read(ndev, TIC); 721 int q; 722 723 /* Timestamp updated */ 724 if (tis & TIS_TFUF) { 725 ravb_write(ndev, ~TIS_TFUF, TIS); 726 ravb_get_tx_tstamp(ndev); 727 result = IRQ_HANDLED; 728 } 729 730 /* Network control and best effort queue RX/TX */ 731 for (q = RAVB_NC; q >= RAVB_BE; q--) { 732 if (((ris0 & ric0) & BIT(q)) || 733 ((tis & tic) & BIT(q))) { 734 if (napi_schedule_prep(&priv->napi[q])) { 735 /* Mask RX and TX interrupts */ 736 ric0 &= ~BIT(q); 737 tic &= ~BIT(q); 738 ravb_write(ndev, ric0, RIC0); 739 ravb_write(ndev, tic, TIC); 740 __napi_schedule(&priv->napi[q]); 741 } else { 742 netdev_warn(ndev, 743 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 744 ris0, ric0); 745 netdev_warn(ndev, 746 " tx status 0x%08x, tx mask 0x%08x.\n", 747 tis, tic); 748 } 749 result = IRQ_HANDLED; 750 } 751 } 752 } 753 754 /* E-MAC status summary */ 755 if (iss & ISS_MS) { 756 ravb_emac_interrupt(ndev); 757 result = IRQ_HANDLED; 758 } 759 760 /* Error status summary */ 761 if (iss & ISS_ES) { 762 ravb_error_interrupt(ndev); 763 result = IRQ_HANDLED; 764 } 765 766 if (iss & ISS_CGIS) 767 result = ravb_ptp_interrupt(ndev); 768 769 mmiowb(); 770 spin_unlock(&priv->lock); 771 return result; 772 } 773 774 static int ravb_poll(struct napi_struct *napi, int budget) 775 { 776 struct net_device *ndev = napi->dev; 777 struct ravb_private *priv = netdev_priv(ndev); 778 unsigned long flags; 779 int q = napi - priv->napi; 780 int mask = BIT(q); 781 int quota = budget; 782 u32 ris0, tis; 783 784 for (;;) { 785 tis = ravb_read(ndev, TIS); 786 ris0 = ravb_read(ndev, RIS0); 787 if (!((ris0 & mask) || (tis & mask))) 788 break; 789 790 /* Processing RX Descriptor Ring */ 791 if (ris0 & mask) { 792 /* Clear RX interrupt */ 793 ravb_write(ndev, ~mask, RIS0); 794 if (ravb_rx(ndev, "a, q)) 795 goto out; 796 } 797 /* Processing TX Descriptor Ring */ 798 if (tis & mask) { 799 spin_lock_irqsave(&priv->lock, flags); 800 /* Clear TX interrupt */ 801 ravb_write(ndev, ~mask, TIS); 802 ravb_tx_free(ndev, q); 803 netif_wake_subqueue(ndev, q); 804 mmiowb(); 805 spin_unlock_irqrestore(&priv->lock, flags); 806 } 807 } 808 809 napi_complete(napi); 810 811 /* Re-enable RX/TX interrupts */ 812 spin_lock_irqsave(&priv->lock, flags); 813 ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0); 814 ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC); 815 mmiowb(); 816 spin_unlock_irqrestore(&priv->lock, flags); 817 818 /* Receive error message handling */ 819 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 820 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 821 if (priv->rx_over_errors != ndev->stats.rx_over_errors) { 822 ndev->stats.rx_over_errors = priv->rx_over_errors; 823 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n"); 824 } 825 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) { 826 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 827 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n"); 828 } 829 out: 830 return budget - quota; 831 } 832 833 /* PHY state control function */ 834 static void ravb_adjust_link(struct net_device *ndev) 835 { 836 struct ravb_private *priv = netdev_priv(ndev); 837 struct phy_device *phydev = priv->phydev; 838 bool new_state = false; 839 840 if (phydev->link) { 841 if (phydev->duplex != priv->duplex) { 842 new_state = true; 843 priv->duplex = phydev->duplex; 844 ravb_set_duplex(ndev); 845 } 846 847 if (phydev->speed != priv->speed) { 848 new_state = true; 849 priv->speed = phydev->speed; 850 ravb_set_rate(ndev); 851 } 852 if (!priv->link) { 853 ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF, 854 ECMR); 855 new_state = true; 856 priv->link = phydev->link; 857 if (priv->no_avb_link) 858 ravb_rcv_snd_enable(ndev); 859 } 860 } else if (priv->link) { 861 new_state = true; 862 priv->link = 0; 863 priv->speed = 0; 864 priv->duplex = -1; 865 if (priv->no_avb_link) 866 ravb_rcv_snd_disable(ndev); 867 } 868 869 if (new_state && netif_msg_link(priv)) 870 phy_print_status(phydev); 871 } 872 873 /* PHY init function */ 874 static int ravb_phy_init(struct net_device *ndev) 875 { 876 struct device_node *np = ndev->dev.parent->of_node; 877 struct ravb_private *priv = netdev_priv(ndev); 878 struct phy_device *phydev; 879 struct device_node *pn; 880 881 priv->link = 0; 882 priv->speed = 0; 883 priv->duplex = -1; 884 885 /* Try connecting to PHY */ 886 pn = of_parse_phandle(np, "phy-handle", 0); 887 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 888 priv->phy_interface); 889 if (!phydev) { 890 netdev_err(ndev, "failed to connect PHY\n"); 891 return -ENOENT; 892 } 893 894 /* This driver only support 10/100Mbit speeds on Gen3 895 * at this time. 896 */ 897 if (priv->chip_id == RCAR_GEN3) { 898 int err; 899 900 err = phy_set_max_speed(phydev, SPEED_100); 901 if (err) { 902 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 903 phy_disconnect(phydev); 904 return err; 905 } 906 907 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 908 } 909 910 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n", 911 phydev->addr, phydev->irq, phydev->drv->name); 912 913 priv->phydev = phydev; 914 915 return 0; 916 } 917 918 /* PHY control start function */ 919 static int ravb_phy_start(struct net_device *ndev) 920 { 921 struct ravb_private *priv = netdev_priv(ndev); 922 int error; 923 924 error = ravb_phy_init(ndev); 925 if (error) 926 return error; 927 928 phy_start(priv->phydev); 929 930 return 0; 931 } 932 933 static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 934 { 935 struct ravb_private *priv = netdev_priv(ndev); 936 int error = -ENODEV; 937 unsigned long flags; 938 939 if (priv->phydev) { 940 spin_lock_irqsave(&priv->lock, flags); 941 error = phy_ethtool_gset(priv->phydev, ecmd); 942 spin_unlock_irqrestore(&priv->lock, flags); 943 } 944 945 return error; 946 } 947 948 static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 949 { 950 struct ravb_private *priv = netdev_priv(ndev); 951 unsigned long flags; 952 int error; 953 954 if (!priv->phydev) 955 return -ENODEV; 956 957 spin_lock_irqsave(&priv->lock, flags); 958 959 /* Disable TX and RX */ 960 ravb_rcv_snd_disable(ndev); 961 962 error = phy_ethtool_sset(priv->phydev, ecmd); 963 if (error) 964 goto error_exit; 965 966 if (ecmd->duplex == DUPLEX_FULL) 967 priv->duplex = 1; 968 else 969 priv->duplex = 0; 970 971 ravb_set_duplex(ndev); 972 973 error_exit: 974 mdelay(1); 975 976 /* Enable TX and RX */ 977 ravb_rcv_snd_enable(ndev); 978 979 mmiowb(); 980 spin_unlock_irqrestore(&priv->lock, flags); 981 982 return error; 983 } 984 985 static int ravb_nway_reset(struct net_device *ndev) 986 { 987 struct ravb_private *priv = netdev_priv(ndev); 988 int error = -ENODEV; 989 unsigned long flags; 990 991 if (priv->phydev) { 992 spin_lock_irqsave(&priv->lock, flags); 993 error = phy_start_aneg(priv->phydev); 994 spin_unlock_irqrestore(&priv->lock, flags); 995 } 996 997 return error; 998 } 999 1000 static u32 ravb_get_msglevel(struct net_device *ndev) 1001 { 1002 struct ravb_private *priv = netdev_priv(ndev); 1003 1004 return priv->msg_enable; 1005 } 1006 1007 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1008 { 1009 struct ravb_private *priv = netdev_priv(ndev); 1010 1011 priv->msg_enable = value; 1012 } 1013 1014 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1015 "rx_queue_0_current", 1016 "tx_queue_0_current", 1017 "rx_queue_0_dirty", 1018 "tx_queue_0_dirty", 1019 "rx_queue_0_packets", 1020 "tx_queue_0_packets", 1021 "rx_queue_0_bytes", 1022 "tx_queue_0_bytes", 1023 "rx_queue_0_mcast_packets", 1024 "rx_queue_0_errors", 1025 "rx_queue_0_crc_errors", 1026 "rx_queue_0_frame_errors", 1027 "rx_queue_0_length_errors", 1028 "rx_queue_0_missed_errors", 1029 "rx_queue_0_over_errors", 1030 1031 "rx_queue_1_current", 1032 "tx_queue_1_current", 1033 "rx_queue_1_dirty", 1034 "tx_queue_1_dirty", 1035 "rx_queue_1_packets", 1036 "tx_queue_1_packets", 1037 "rx_queue_1_bytes", 1038 "tx_queue_1_bytes", 1039 "rx_queue_1_mcast_packets", 1040 "rx_queue_1_errors", 1041 "rx_queue_1_crc_errors", 1042 "rx_queue_1_frame_errors_", 1043 "rx_queue_1_length_errors", 1044 "rx_queue_1_missed_errors", 1045 "rx_queue_1_over_errors", 1046 }; 1047 1048 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1049 1050 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1051 { 1052 switch (sset) { 1053 case ETH_SS_STATS: 1054 return RAVB_STATS_LEN; 1055 default: 1056 return -EOPNOTSUPP; 1057 } 1058 } 1059 1060 static void ravb_get_ethtool_stats(struct net_device *ndev, 1061 struct ethtool_stats *stats, u64 *data) 1062 { 1063 struct ravb_private *priv = netdev_priv(ndev); 1064 int i = 0; 1065 int q; 1066 1067 /* Device-specific stats */ 1068 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1069 struct net_device_stats *stats = &priv->stats[q]; 1070 1071 data[i++] = priv->cur_rx[q]; 1072 data[i++] = priv->cur_tx[q]; 1073 data[i++] = priv->dirty_rx[q]; 1074 data[i++] = priv->dirty_tx[q]; 1075 data[i++] = stats->rx_packets; 1076 data[i++] = stats->tx_packets; 1077 data[i++] = stats->rx_bytes; 1078 data[i++] = stats->tx_bytes; 1079 data[i++] = stats->multicast; 1080 data[i++] = stats->rx_errors; 1081 data[i++] = stats->rx_crc_errors; 1082 data[i++] = stats->rx_frame_errors; 1083 data[i++] = stats->rx_length_errors; 1084 data[i++] = stats->rx_missed_errors; 1085 data[i++] = stats->rx_over_errors; 1086 } 1087 } 1088 1089 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1090 { 1091 switch (stringset) { 1092 case ETH_SS_STATS: 1093 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1094 break; 1095 } 1096 } 1097 1098 static void ravb_get_ringparam(struct net_device *ndev, 1099 struct ethtool_ringparam *ring) 1100 { 1101 struct ravb_private *priv = netdev_priv(ndev); 1102 1103 ring->rx_max_pending = BE_RX_RING_MAX; 1104 ring->tx_max_pending = BE_TX_RING_MAX; 1105 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1106 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1107 } 1108 1109 static int ravb_set_ringparam(struct net_device *ndev, 1110 struct ethtool_ringparam *ring) 1111 { 1112 struct ravb_private *priv = netdev_priv(ndev); 1113 int error; 1114 1115 if (ring->tx_pending > BE_TX_RING_MAX || 1116 ring->rx_pending > BE_RX_RING_MAX || 1117 ring->tx_pending < BE_TX_RING_MIN || 1118 ring->rx_pending < BE_RX_RING_MIN) 1119 return -EINVAL; 1120 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1121 return -EINVAL; 1122 1123 if (netif_running(ndev)) { 1124 netif_device_detach(ndev); 1125 /* Stop PTP Clock driver */ 1126 ravb_ptp_stop(ndev); 1127 /* Wait for DMA stopping */ 1128 error = ravb_stop_dma(ndev); 1129 if (error) { 1130 netdev_err(ndev, 1131 "cannot set ringparam! Any AVB processes are still running?\n"); 1132 return error; 1133 } 1134 synchronize_irq(ndev->irq); 1135 1136 /* Free all the skb's in the RX queue and the DMA buffers. */ 1137 ravb_ring_free(ndev, RAVB_BE); 1138 ravb_ring_free(ndev, RAVB_NC); 1139 } 1140 1141 /* Set new parameters */ 1142 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1143 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1144 1145 if (netif_running(ndev)) { 1146 error = ravb_dmac_init(ndev); 1147 if (error) { 1148 netdev_err(ndev, 1149 "%s: ravb_dmac_init() failed, error %d\n", 1150 __func__, error); 1151 return error; 1152 } 1153 1154 ravb_emac_init(ndev); 1155 1156 /* Initialise PTP Clock driver */ 1157 ravb_ptp_init(ndev, priv->pdev); 1158 1159 netif_device_attach(ndev); 1160 } 1161 1162 return 0; 1163 } 1164 1165 static int ravb_get_ts_info(struct net_device *ndev, 1166 struct ethtool_ts_info *info) 1167 { 1168 struct ravb_private *priv = netdev_priv(ndev); 1169 1170 info->so_timestamping = 1171 SOF_TIMESTAMPING_TX_SOFTWARE | 1172 SOF_TIMESTAMPING_RX_SOFTWARE | 1173 SOF_TIMESTAMPING_SOFTWARE | 1174 SOF_TIMESTAMPING_TX_HARDWARE | 1175 SOF_TIMESTAMPING_RX_HARDWARE | 1176 SOF_TIMESTAMPING_RAW_HARDWARE; 1177 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1178 info->rx_filters = 1179 (1 << HWTSTAMP_FILTER_NONE) | 1180 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1181 (1 << HWTSTAMP_FILTER_ALL); 1182 info->phc_index = ptp_clock_index(priv->ptp.clock); 1183 1184 return 0; 1185 } 1186 1187 static const struct ethtool_ops ravb_ethtool_ops = { 1188 .get_settings = ravb_get_settings, 1189 .set_settings = ravb_set_settings, 1190 .nway_reset = ravb_nway_reset, 1191 .get_msglevel = ravb_get_msglevel, 1192 .set_msglevel = ravb_set_msglevel, 1193 .get_link = ethtool_op_get_link, 1194 .get_strings = ravb_get_strings, 1195 .get_ethtool_stats = ravb_get_ethtool_stats, 1196 .get_sset_count = ravb_get_sset_count, 1197 .get_ringparam = ravb_get_ringparam, 1198 .set_ringparam = ravb_set_ringparam, 1199 .get_ts_info = ravb_get_ts_info, 1200 }; 1201 1202 /* Network device open function for Ethernet AVB */ 1203 static int ravb_open(struct net_device *ndev) 1204 { 1205 struct ravb_private *priv = netdev_priv(ndev); 1206 int error; 1207 1208 napi_enable(&priv->napi[RAVB_BE]); 1209 napi_enable(&priv->napi[RAVB_NC]); 1210 1211 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name, 1212 ndev); 1213 if (error) { 1214 netdev_err(ndev, "cannot request IRQ\n"); 1215 goto out_napi_off; 1216 } 1217 1218 if (priv->chip_id == RCAR_GEN3) { 1219 error = request_irq(priv->emac_irq, ravb_interrupt, 1220 IRQF_SHARED, ndev->name, ndev); 1221 if (error) { 1222 netdev_err(ndev, "cannot request IRQ\n"); 1223 goto out_free_irq; 1224 } 1225 } 1226 1227 /* Device init */ 1228 error = ravb_dmac_init(ndev); 1229 if (error) 1230 goto out_free_irq; 1231 ravb_emac_init(ndev); 1232 1233 /* Initialise PTP Clock driver */ 1234 ravb_ptp_init(ndev, priv->pdev); 1235 1236 netif_tx_start_all_queues(ndev); 1237 1238 /* PHY control start */ 1239 error = ravb_phy_start(ndev); 1240 if (error) 1241 goto out_ptp_stop; 1242 1243 return 0; 1244 1245 out_ptp_stop: 1246 /* Stop PTP Clock driver */ 1247 ravb_ptp_stop(ndev); 1248 out_free_irq: 1249 free_irq(ndev->irq, ndev); 1250 free_irq(priv->emac_irq, ndev); 1251 out_napi_off: 1252 napi_disable(&priv->napi[RAVB_NC]); 1253 napi_disable(&priv->napi[RAVB_BE]); 1254 return error; 1255 } 1256 1257 /* Timeout function for Ethernet AVB */ 1258 static void ravb_tx_timeout(struct net_device *ndev) 1259 { 1260 struct ravb_private *priv = netdev_priv(ndev); 1261 1262 netif_err(priv, tx_err, ndev, 1263 "transmit timed out, status %08x, resetting...\n", 1264 ravb_read(ndev, ISS)); 1265 1266 /* tx_errors count up */ 1267 ndev->stats.tx_errors++; 1268 1269 schedule_work(&priv->work); 1270 } 1271 1272 static void ravb_tx_timeout_work(struct work_struct *work) 1273 { 1274 struct ravb_private *priv = container_of(work, struct ravb_private, 1275 work); 1276 struct net_device *ndev = priv->ndev; 1277 1278 netif_tx_stop_all_queues(ndev); 1279 1280 /* Stop PTP Clock driver */ 1281 ravb_ptp_stop(ndev); 1282 1283 /* Wait for DMA stopping */ 1284 ravb_stop_dma(ndev); 1285 1286 ravb_ring_free(ndev, RAVB_BE); 1287 ravb_ring_free(ndev, RAVB_NC); 1288 1289 /* Device init */ 1290 ravb_dmac_init(ndev); 1291 ravb_emac_init(ndev); 1292 1293 /* Initialise PTP Clock driver */ 1294 ravb_ptp_init(ndev, priv->pdev); 1295 1296 netif_tx_start_all_queues(ndev); 1297 } 1298 1299 /* Packet transmit function for Ethernet AVB */ 1300 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1301 { 1302 struct ravb_private *priv = netdev_priv(ndev); 1303 u16 q = skb_get_queue_mapping(skb); 1304 struct ravb_tstamp_skb *ts_skb; 1305 struct ravb_tx_desc *desc; 1306 unsigned long flags; 1307 u32 dma_addr; 1308 void *buffer; 1309 u32 entry; 1310 u32 len; 1311 1312 spin_lock_irqsave(&priv->lock, flags); 1313 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1314 NUM_TX_DESC) { 1315 netif_err(priv, tx_queued, ndev, 1316 "still transmitting with the full ring!\n"); 1317 netif_stop_subqueue(ndev, q); 1318 spin_unlock_irqrestore(&priv->lock, flags); 1319 return NETDEV_TX_BUSY; 1320 } 1321 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1322 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1323 1324 if (skb_put_padto(skb, ETH_ZLEN)) 1325 goto drop; 1326 1327 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1328 entry / NUM_TX_DESC * DPTR_ALIGN; 1329 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1330 memcpy(buffer, skb->data, len); 1331 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1332 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1333 goto drop; 1334 1335 desc = &priv->tx_ring[q][entry]; 1336 desc->ds_tagl = cpu_to_le16(len); 1337 desc->dptr = cpu_to_le32(dma_addr); 1338 1339 buffer = skb->data + len; 1340 len = skb->len - len; 1341 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1342 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1343 goto unmap; 1344 1345 desc++; 1346 desc->ds_tagl = cpu_to_le16(len); 1347 desc->dptr = cpu_to_le32(dma_addr); 1348 1349 /* TX timestamp required */ 1350 if (q == RAVB_NC) { 1351 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1352 if (!ts_skb) { 1353 desc--; 1354 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1355 DMA_TO_DEVICE); 1356 goto unmap; 1357 } 1358 ts_skb->skb = skb; 1359 ts_skb->tag = priv->ts_skb_tag++; 1360 priv->ts_skb_tag &= 0x3ff; 1361 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1362 1363 /* TAG and timestamp required flag */ 1364 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1365 skb_tx_timestamp(skb); 1366 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1367 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); 1368 } 1369 1370 /* Descriptor type must be set after all the above writes */ 1371 dma_wmb(); 1372 desc->die_dt = DT_FEND; 1373 desc--; 1374 desc->die_dt = DT_FSTART; 1375 1376 ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR); 1377 1378 priv->cur_tx[q] += NUM_TX_DESC; 1379 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1380 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q)) 1381 netif_stop_subqueue(ndev, q); 1382 1383 exit: 1384 mmiowb(); 1385 spin_unlock_irqrestore(&priv->lock, flags); 1386 return NETDEV_TX_OK; 1387 1388 unmap: 1389 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1390 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1391 drop: 1392 dev_kfree_skb_any(skb); 1393 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1394 goto exit; 1395 } 1396 1397 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1398 void *accel_priv, select_queue_fallback_t fallback) 1399 { 1400 /* If skb needs TX timestamp, it is handled in network control queue */ 1401 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1402 RAVB_BE; 1403 1404 } 1405 1406 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1407 { 1408 struct ravb_private *priv = netdev_priv(ndev); 1409 struct net_device_stats *nstats, *stats0, *stats1; 1410 1411 nstats = &ndev->stats; 1412 stats0 = &priv->stats[RAVB_BE]; 1413 stats1 = &priv->stats[RAVB_NC]; 1414 1415 nstats->tx_dropped += ravb_read(ndev, TROCR); 1416 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1417 nstats->collisions += ravb_read(ndev, CDCR); 1418 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1419 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1420 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1421 1422 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1423 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1424 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1425 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1426 1427 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1428 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1429 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1430 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1431 nstats->multicast = stats0->multicast + stats1->multicast; 1432 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1433 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1434 nstats->rx_frame_errors = 1435 stats0->rx_frame_errors + stats1->rx_frame_errors; 1436 nstats->rx_length_errors = 1437 stats0->rx_length_errors + stats1->rx_length_errors; 1438 nstats->rx_missed_errors = 1439 stats0->rx_missed_errors + stats1->rx_missed_errors; 1440 nstats->rx_over_errors = 1441 stats0->rx_over_errors + stats1->rx_over_errors; 1442 1443 return nstats; 1444 } 1445 1446 /* Update promiscuous bit */ 1447 static void ravb_set_rx_mode(struct net_device *ndev) 1448 { 1449 struct ravb_private *priv = netdev_priv(ndev); 1450 unsigned long flags; 1451 u32 ecmr; 1452 1453 spin_lock_irqsave(&priv->lock, flags); 1454 ecmr = ravb_read(ndev, ECMR); 1455 if (ndev->flags & IFF_PROMISC) 1456 ecmr |= ECMR_PRM; 1457 else 1458 ecmr &= ~ECMR_PRM; 1459 ravb_write(ndev, ecmr, ECMR); 1460 mmiowb(); 1461 spin_unlock_irqrestore(&priv->lock, flags); 1462 } 1463 1464 /* Device close function for Ethernet AVB */ 1465 static int ravb_close(struct net_device *ndev) 1466 { 1467 struct ravb_private *priv = netdev_priv(ndev); 1468 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1469 1470 netif_tx_stop_all_queues(ndev); 1471 1472 /* Disable interrupts by clearing the interrupt masks. */ 1473 ravb_write(ndev, 0, RIC0); 1474 ravb_write(ndev, 0, RIC1); 1475 ravb_write(ndev, 0, RIC2); 1476 ravb_write(ndev, 0, TIC); 1477 1478 /* Stop PTP Clock driver */ 1479 ravb_ptp_stop(ndev); 1480 1481 /* Set the config mode to stop the AVB-DMAC's processes */ 1482 if (ravb_stop_dma(ndev) < 0) 1483 netdev_err(ndev, 1484 "device will be stopped after h/w processes are done.\n"); 1485 1486 /* Clear the timestamp list */ 1487 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1488 list_del(&ts_skb->list); 1489 kfree(ts_skb); 1490 } 1491 1492 /* PHY disconnect */ 1493 if (priv->phydev) { 1494 phy_stop(priv->phydev); 1495 phy_disconnect(priv->phydev); 1496 priv->phydev = NULL; 1497 } 1498 1499 free_irq(ndev->irq, ndev); 1500 1501 napi_disable(&priv->napi[RAVB_NC]); 1502 napi_disable(&priv->napi[RAVB_BE]); 1503 1504 /* Free all the skb's in the RX queue and the DMA buffers. */ 1505 ravb_ring_free(ndev, RAVB_BE); 1506 ravb_ring_free(ndev, RAVB_NC); 1507 1508 return 0; 1509 } 1510 1511 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1512 { 1513 struct ravb_private *priv = netdev_priv(ndev); 1514 struct hwtstamp_config config; 1515 1516 config.flags = 0; 1517 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1518 HWTSTAMP_TX_OFF; 1519 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1520 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1521 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1522 config.rx_filter = HWTSTAMP_FILTER_ALL; 1523 else 1524 config.rx_filter = HWTSTAMP_FILTER_NONE; 1525 1526 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1527 -EFAULT : 0; 1528 } 1529 1530 /* Control hardware time stamping */ 1531 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1532 { 1533 struct ravb_private *priv = netdev_priv(ndev); 1534 struct hwtstamp_config config; 1535 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1536 u32 tstamp_tx_ctrl; 1537 1538 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1539 return -EFAULT; 1540 1541 /* Reserved for future extensions */ 1542 if (config.flags) 1543 return -EINVAL; 1544 1545 switch (config.tx_type) { 1546 case HWTSTAMP_TX_OFF: 1547 tstamp_tx_ctrl = 0; 1548 break; 1549 case HWTSTAMP_TX_ON: 1550 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1551 break; 1552 default: 1553 return -ERANGE; 1554 } 1555 1556 switch (config.rx_filter) { 1557 case HWTSTAMP_FILTER_NONE: 1558 tstamp_rx_ctrl = 0; 1559 break; 1560 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1561 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1562 break; 1563 default: 1564 config.rx_filter = HWTSTAMP_FILTER_ALL; 1565 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1566 } 1567 1568 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1569 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1570 1571 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1572 -EFAULT : 0; 1573 } 1574 1575 /* ioctl to device function */ 1576 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1577 { 1578 struct ravb_private *priv = netdev_priv(ndev); 1579 struct phy_device *phydev = priv->phydev; 1580 1581 if (!netif_running(ndev)) 1582 return -EINVAL; 1583 1584 if (!phydev) 1585 return -ENODEV; 1586 1587 switch (cmd) { 1588 case SIOCGHWTSTAMP: 1589 return ravb_hwtstamp_get(ndev, req); 1590 case SIOCSHWTSTAMP: 1591 return ravb_hwtstamp_set(ndev, req); 1592 } 1593 1594 return phy_mii_ioctl(phydev, req, cmd); 1595 } 1596 1597 static const struct net_device_ops ravb_netdev_ops = { 1598 .ndo_open = ravb_open, 1599 .ndo_stop = ravb_close, 1600 .ndo_start_xmit = ravb_start_xmit, 1601 .ndo_select_queue = ravb_select_queue, 1602 .ndo_get_stats = ravb_get_stats, 1603 .ndo_set_rx_mode = ravb_set_rx_mode, 1604 .ndo_tx_timeout = ravb_tx_timeout, 1605 .ndo_do_ioctl = ravb_do_ioctl, 1606 .ndo_validate_addr = eth_validate_addr, 1607 .ndo_set_mac_address = eth_mac_addr, 1608 .ndo_change_mtu = eth_change_mtu, 1609 }; 1610 1611 /* MDIO bus init function */ 1612 static int ravb_mdio_init(struct ravb_private *priv) 1613 { 1614 struct platform_device *pdev = priv->pdev; 1615 struct device *dev = &pdev->dev; 1616 int error; 1617 1618 /* Bitbang init */ 1619 priv->mdiobb.ops = &bb_ops; 1620 1621 /* MII controller setting */ 1622 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1623 if (!priv->mii_bus) 1624 return -ENOMEM; 1625 1626 /* Hook up MII support for ethtool */ 1627 priv->mii_bus->name = "ravb_mii"; 1628 priv->mii_bus->parent = dev; 1629 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1630 pdev->name, pdev->id); 1631 1632 /* Register MDIO bus */ 1633 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1634 if (error) 1635 goto out_free_bus; 1636 1637 return 0; 1638 1639 out_free_bus: 1640 free_mdio_bitbang(priv->mii_bus); 1641 return error; 1642 } 1643 1644 /* MDIO bus release function */ 1645 static int ravb_mdio_release(struct ravb_private *priv) 1646 { 1647 /* Unregister mdio bus */ 1648 mdiobus_unregister(priv->mii_bus); 1649 1650 /* Free bitbang info */ 1651 free_mdio_bitbang(priv->mii_bus); 1652 1653 return 0; 1654 } 1655 1656 static const struct of_device_id ravb_match_table[] = { 1657 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1658 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1659 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1660 { } 1661 }; 1662 MODULE_DEVICE_TABLE(of, ravb_match_table); 1663 1664 static int ravb_set_gti(struct net_device *ndev) 1665 { 1666 1667 struct device *dev = ndev->dev.parent; 1668 struct device_node *np = dev->of_node; 1669 unsigned long rate; 1670 struct clk *clk; 1671 uint64_t inc; 1672 1673 clk = of_clk_get(np, 0); 1674 if (IS_ERR(clk)) { 1675 dev_err(dev, "could not get clock\n"); 1676 return PTR_ERR(clk); 1677 } 1678 1679 rate = clk_get_rate(clk); 1680 clk_put(clk); 1681 1682 inc = 1000000000ULL << 20; 1683 do_div(inc, rate); 1684 1685 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1686 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1687 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1688 return -EINVAL; 1689 } 1690 1691 ravb_write(ndev, inc, GTI); 1692 1693 return 0; 1694 } 1695 1696 static int ravb_probe(struct platform_device *pdev) 1697 { 1698 struct device_node *np = pdev->dev.of_node; 1699 const struct of_device_id *match; 1700 struct ravb_private *priv; 1701 enum ravb_chip_id chip_id; 1702 struct net_device *ndev; 1703 int error, irq, q; 1704 struct resource *res; 1705 1706 if (!np) { 1707 dev_err(&pdev->dev, 1708 "this driver is required to be instantiated from device tree\n"); 1709 return -EINVAL; 1710 } 1711 1712 /* Get base address */ 1713 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1714 if (!res) { 1715 dev_err(&pdev->dev, "invalid resource\n"); 1716 return -EINVAL; 1717 } 1718 1719 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 1720 NUM_TX_QUEUE, NUM_RX_QUEUE); 1721 if (!ndev) 1722 return -ENOMEM; 1723 1724 pm_runtime_enable(&pdev->dev); 1725 pm_runtime_get_sync(&pdev->dev); 1726 1727 /* The Ether-specific entries in the device structure. */ 1728 ndev->base_addr = res->start; 1729 ndev->dma = -1; 1730 1731 match = of_match_device(of_match_ptr(ravb_match_table), &pdev->dev); 1732 chip_id = (enum ravb_chip_id)match->data; 1733 1734 if (chip_id == RCAR_GEN3) 1735 irq = platform_get_irq_byname(pdev, "ch22"); 1736 else 1737 irq = platform_get_irq(pdev, 0); 1738 if (irq < 0) { 1739 error = irq; 1740 goto out_release; 1741 } 1742 ndev->irq = irq; 1743 1744 SET_NETDEV_DEV(ndev, &pdev->dev); 1745 1746 priv = netdev_priv(ndev); 1747 priv->ndev = ndev; 1748 priv->pdev = pdev; 1749 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 1750 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 1751 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 1752 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 1753 priv->addr = devm_ioremap_resource(&pdev->dev, res); 1754 if (IS_ERR(priv->addr)) { 1755 error = PTR_ERR(priv->addr); 1756 goto out_release; 1757 } 1758 1759 spin_lock_init(&priv->lock); 1760 INIT_WORK(&priv->work, ravb_tx_timeout_work); 1761 1762 priv->phy_interface = of_get_phy_mode(np); 1763 1764 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 1765 priv->avb_link_active_low = 1766 of_property_read_bool(np, "renesas,ether-link-active-low"); 1767 1768 if (chip_id == RCAR_GEN3) { 1769 irq = platform_get_irq_byname(pdev, "ch24"); 1770 if (irq < 0) { 1771 error = irq; 1772 goto out_release; 1773 } 1774 priv->emac_irq = irq; 1775 } 1776 1777 priv->chip_id = chip_id; 1778 1779 /* Set function */ 1780 ndev->netdev_ops = &ravb_netdev_ops; 1781 ndev->ethtool_ops = &ravb_ethtool_ops; 1782 1783 /* Set AVB config mode */ 1784 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG, 1785 CCC); 1786 1787 /* Set CSEL value */ 1788 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB, 1789 CCC); 1790 1791 /* Set GTI value */ 1792 error = ravb_set_gti(ndev); 1793 if (error) 1794 goto out_release; 1795 1796 /* Request GTI loading */ 1797 ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR); 1798 1799 /* Allocate descriptor base address table */ 1800 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 1801 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 1802 &priv->desc_bat_dma, GFP_KERNEL); 1803 if (!priv->desc_bat) { 1804 dev_err(&pdev->dev, 1805 "Cannot allocate desc base address table (size %d bytes)\n", 1806 priv->desc_bat_size); 1807 error = -ENOMEM; 1808 goto out_release; 1809 } 1810 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 1811 priv->desc_bat[q].die_dt = DT_EOS; 1812 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1813 1814 /* Initialise HW timestamp list */ 1815 INIT_LIST_HEAD(&priv->ts_skb_list); 1816 1817 /* Debug message level */ 1818 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 1819 1820 /* Read and set MAC address */ 1821 ravb_read_mac_address(ndev, of_get_mac_address(np)); 1822 if (!is_valid_ether_addr(ndev->dev_addr)) { 1823 dev_warn(&pdev->dev, 1824 "no valid MAC address supplied, using a random one\n"); 1825 eth_hw_addr_random(ndev); 1826 } 1827 1828 /* MDIO bus init */ 1829 error = ravb_mdio_init(priv); 1830 if (error) { 1831 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 1832 goto out_dma_free; 1833 } 1834 1835 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 1836 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 1837 1838 /* Network device register */ 1839 error = register_netdev(ndev); 1840 if (error) 1841 goto out_napi_del; 1842 1843 /* Print device information */ 1844 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 1845 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 1846 1847 platform_set_drvdata(pdev, ndev); 1848 1849 return 0; 1850 1851 out_napi_del: 1852 netif_napi_del(&priv->napi[RAVB_NC]); 1853 netif_napi_del(&priv->napi[RAVB_BE]); 1854 ravb_mdio_release(priv); 1855 out_dma_free: 1856 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 1857 priv->desc_bat_dma); 1858 out_release: 1859 if (ndev) 1860 free_netdev(ndev); 1861 1862 pm_runtime_put(&pdev->dev); 1863 pm_runtime_disable(&pdev->dev); 1864 return error; 1865 } 1866 1867 static int ravb_remove(struct platform_device *pdev) 1868 { 1869 struct net_device *ndev = platform_get_drvdata(pdev); 1870 struct ravb_private *priv = netdev_priv(ndev); 1871 1872 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 1873 priv->desc_bat_dma); 1874 /* Set reset mode */ 1875 ravb_write(ndev, CCC_OPC_RESET, CCC); 1876 pm_runtime_put_sync(&pdev->dev); 1877 unregister_netdev(ndev); 1878 netif_napi_del(&priv->napi[RAVB_NC]); 1879 netif_napi_del(&priv->napi[RAVB_BE]); 1880 ravb_mdio_release(priv); 1881 pm_runtime_disable(&pdev->dev); 1882 free_netdev(ndev); 1883 platform_set_drvdata(pdev, NULL); 1884 1885 return 0; 1886 } 1887 1888 #ifdef CONFIG_PM 1889 static int ravb_runtime_nop(struct device *dev) 1890 { 1891 /* Runtime PM callback shared between ->runtime_suspend() 1892 * and ->runtime_resume(). Simply returns success. 1893 * 1894 * This driver re-initializes all registers after 1895 * pm_runtime_get_sync() anyway so there is no need 1896 * to save and restore registers here. 1897 */ 1898 return 0; 1899 } 1900 1901 static const struct dev_pm_ops ravb_dev_pm_ops = { 1902 .runtime_suspend = ravb_runtime_nop, 1903 .runtime_resume = ravb_runtime_nop, 1904 }; 1905 1906 #define RAVB_PM_OPS (&ravb_dev_pm_ops) 1907 #else 1908 #define RAVB_PM_OPS NULL 1909 #endif 1910 1911 static struct platform_driver ravb_driver = { 1912 .probe = ravb_probe, 1913 .remove = ravb_remove, 1914 .driver = { 1915 .name = "ravb", 1916 .pm = RAVB_PM_OPS, 1917 .of_match_table = ravb_match_table, 1918 }, 1919 }; 1920 1921 module_platform_driver(ravb_driver); 1922 1923 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 1924 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 1925 MODULE_LICENSE("GPL v2"); 1926