1 /* Renesas Ethernet AVB device driver
2  *
3  * Copyright (C) 2014-2015 Renesas Electronics Corporation
4  * Copyright (C) 2015 Renesas Solutions Corp.
5  * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
6  *
7  * Based on the SuperH Ethernet driver
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms and conditions of the GNU General Public License version 2,
11  * as published by the Free Software Foundation.
12  */
13 
14 #ifndef __RAVB_H__
15 #define __RAVB_H__
16 
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/mdio-bitbang.h>
21 #include <linux/netdevice.h>
22 #include <linux/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/ptp_clock_kernel.h>
25 
26 #define BE_TX_RING_SIZE	64	/* TX ring size for Best Effort */
27 #define BE_RX_RING_SIZE	1024	/* RX ring size for Best Effort */
28 #define NC_TX_RING_SIZE	64	/* TX ring size for Network Control */
29 #define NC_RX_RING_SIZE	64	/* RX ring size for Network Control */
30 #define BE_TX_RING_MIN	64
31 #define BE_RX_RING_MIN	64
32 #define BE_TX_RING_MAX	1024
33 #define BE_RX_RING_MAX	2048
34 
35 #define PKT_BUF_SZ	1538
36 
37 /* Driver's parameters */
38 #define RAVB_ALIGN	128
39 
40 /* Hardware time stamp */
41 #define RAVB_TXTSTAMP_VALID	0x00000001	/* TX timestamp valid */
42 #define RAVB_TXTSTAMP_ENABLED	0x00000010	/* Enable TX timestamping */
43 
44 #define RAVB_RXTSTAMP_VALID	0x00000001	/* RX timestamp valid */
45 #define RAVB_RXTSTAMP_TYPE	0x00000006	/* RX type mask */
46 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
47 #define RAVB_RXTSTAMP_TYPE_ALL	0x00000006
48 #define RAVB_RXTSTAMP_ENABLED	0x00000010	/* Enable RX timestamping */
49 
50 enum ravb_reg {
51 	/* AVB-DMAC registers */
52 	CCC	= 0x0000,
53 	DBAT	= 0x0004,
54 	DLR	= 0x0008,
55 	CSR	= 0x000C,
56 	CDAR0	= 0x0010,
57 	CDAR1	= 0x0014,
58 	CDAR2	= 0x0018,
59 	CDAR3	= 0x001C,
60 	CDAR4	= 0x0020,
61 	CDAR5	= 0x0024,
62 	CDAR6	= 0x0028,
63 	CDAR7	= 0x002C,
64 	CDAR8	= 0x0030,
65 	CDAR9	= 0x0034,
66 	CDAR10	= 0x0038,
67 	CDAR11	= 0x003C,
68 	CDAR12	= 0x0040,
69 	CDAR13	= 0x0044,
70 	CDAR14	= 0x0048,
71 	CDAR15	= 0x004C,
72 	CDAR16	= 0x0050,
73 	CDAR17	= 0x0054,
74 	CDAR18	= 0x0058,
75 	CDAR19	= 0x005C,
76 	CDAR20	= 0x0060,
77 	CDAR21	= 0x0064,
78 	ESR	= 0x0088,
79 	APSR	= 0x008C,	/* R-Car Gen3 only */
80 	RCR	= 0x0090,
81 	RQC0	= 0x0094,
82 	RQC1	= 0x0098,
83 	RQC2	= 0x009C,
84 	RQC3	= 0x00A0,
85 	RQC4	= 0x00A4,
86 	RPC	= 0x00B0,
87 	UFCW	= 0x00BC,
88 	UFCS	= 0x00C0,
89 	UFCV0	= 0x00C4,
90 	UFCV1	= 0x00C8,
91 	UFCV2	= 0x00CC,
92 	UFCV3	= 0x00D0,
93 	UFCV4	= 0x00D4,
94 	UFCD0	= 0x00E0,
95 	UFCD1	= 0x00E4,
96 	UFCD2	= 0x00E8,
97 	UFCD3	= 0x00EC,
98 	UFCD4	= 0x00F0,
99 	SFO	= 0x00FC,
100 	SFP0	= 0x0100,
101 	SFP1	= 0x0104,
102 	SFP2	= 0x0108,
103 	SFP3	= 0x010C,
104 	SFP4	= 0x0110,
105 	SFP5	= 0x0114,
106 	SFP6	= 0x0118,
107 	SFP7	= 0x011C,
108 	SFP8	= 0x0120,
109 	SFP9	= 0x0124,
110 	SFP10	= 0x0128,
111 	SFP11	= 0x012C,
112 	SFP12	= 0x0130,
113 	SFP13	= 0x0134,
114 	SFP14	= 0x0138,
115 	SFP15	= 0x013C,
116 	SFP16	= 0x0140,
117 	SFP17	= 0x0144,
118 	SFP18	= 0x0148,
119 	SFP19	= 0x014C,
120 	SFP20	= 0x0150,
121 	SFP21	= 0x0154,
122 	SFP22	= 0x0158,
123 	SFP23	= 0x015C,
124 	SFP24	= 0x0160,
125 	SFP25	= 0x0164,
126 	SFP26	= 0x0168,
127 	SFP27	= 0x016C,
128 	SFP28	= 0x0170,
129 	SFP29	= 0x0174,
130 	SFP30	= 0x0178,
131 	SFP31	= 0x017C,
132 	SFM0	= 0x01C0,
133 	SFM1	= 0x01C4,
134 	TGC	= 0x0300,
135 	TCCR	= 0x0304,
136 	TSR	= 0x0308,
137 	TFA0	= 0x0310,
138 	TFA1	= 0x0314,
139 	TFA2	= 0x0318,
140 	CIVR0	= 0x0320,
141 	CIVR1	= 0x0324,
142 	CDVR0	= 0x0328,
143 	CDVR1	= 0x032C,
144 	CUL0	= 0x0330,
145 	CUL1	= 0x0334,
146 	CLL0	= 0x0338,
147 	CLL1	= 0x033C,
148 	DIC	= 0x0350,
149 	DIS	= 0x0354,
150 	EIC	= 0x0358,
151 	EIS	= 0x035C,
152 	RIC0	= 0x0360,
153 	RIS0	= 0x0364,
154 	RIC1	= 0x0368,
155 	RIS1	= 0x036C,
156 	RIC2	= 0x0370,
157 	RIS2	= 0x0374,
158 	TIC	= 0x0378,
159 	TIS	= 0x037C,
160 	ISS	= 0x0380,
161 	CIE	= 0x0384,	/* R-Car Gen3 only */
162 	GCCR	= 0x0390,
163 	GMTT	= 0x0394,
164 	GPTC	= 0x0398,
165 	GTI	= 0x039C,
166 	GTO0	= 0x03A0,
167 	GTO1	= 0x03A4,
168 	GTO2	= 0x03A8,
169 	GIC	= 0x03AC,
170 	GIS	= 0x03B0,
171 	GCPT	= 0x03B4,	/* Undocumented? */
172 	GCT0	= 0x03B8,
173 	GCT1	= 0x03BC,
174 	GCT2	= 0x03C0,
175 	GIE	= 0x03CC,	/* R-Car Gen3 only */
176 	GID	= 0x03D0,	/* R-Car Gen3 only */
177 	DIL	= 0x0440,	/* R-Car Gen3 only */
178 	RIE0	= 0x0460,	/* R-Car Gen3 only */
179 	RID0	= 0x0464,	/* R-Car Gen3 only */
180 	RIE2	= 0x0470,	/* R-Car Gen3 only */
181 	RID2	= 0x0474,	/* R-Car Gen3 only */
182 	TIE	= 0x0478,	/* R-Car Gen3 only */
183 	TID	= 0x047c,	/* R-Car Gen3 only */
184 
185 	/* E-MAC registers */
186 	ECMR	= 0x0500,
187 	RFLR	= 0x0508,
188 	ECSR	= 0x0510,
189 	ECSIPR	= 0x0518,
190 	PIR	= 0x0520,
191 	PSR	= 0x0528,
192 	PIPR	= 0x052c,
193 	MPR	= 0x0558,
194 	PFTCR	= 0x055c,
195 	PFRCR	= 0x0560,
196 	GECMR	= 0x05b0,
197 	MAHR	= 0x05c0,
198 	MALR	= 0x05c8,
199 	TROCR	= 0x0700,	/* Undocumented? */
200 	CDCR	= 0x0708,	/* Undocumented? */
201 	LCCR	= 0x0710,	/* Undocumented? */
202 	CEFCR	= 0x0740,
203 	FRECR	= 0x0748,
204 	TSFRCR	= 0x0750,
205 	TLFRCR	= 0x0758,
206 	RFCR	= 0x0760,
207 	CERCR	= 0x0768,	/* Undocumented? */
208 	CEECR	= 0x0770,	/* Undocumented? */
209 	MAFCR	= 0x0778,
210 };
211 
212 
213 /* Register bits of the Ethernet AVB */
214 /* CCC */
215 enum CCC_BIT {
216 	CCC_OPC		= 0x00000003,
217 	CCC_OPC_RESET	= 0x00000000,
218 	CCC_OPC_CONFIG	= 0x00000001,
219 	CCC_OPC_OPERATION = 0x00000002,
220 	CCC_GAC		= 0x00000080,
221 	CCC_DTSR	= 0x00000100,
222 	CCC_CSEL	= 0x00030000,
223 	CCC_CSEL_HPB	= 0x00010000,
224 	CCC_CSEL_ETH_TX	= 0x00020000,
225 	CCC_CSEL_GMII_REF = 0x00030000,
226 	CCC_BOC		= 0x00100000,	/* Undocumented? */
227 	CCC_LBME	= 0x01000000,
228 };
229 
230 /* CSR */
231 enum CSR_BIT {
232 	CSR_OPS		= 0x0000000F,
233 	CSR_OPS_RESET	= 0x00000001,
234 	CSR_OPS_CONFIG	= 0x00000002,
235 	CSR_OPS_OPERATION = 0x00000004,
236 	CSR_OPS_STANDBY	= 0x00000008,	/* Undocumented? */
237 	CSR_DTS		= 0x00000100,
238 	CSR_TPO0	= 0x00010000,
239 	CSR_TPO1	= 0x00020000,
240 	CSR_TPO2	= 0x00040000,
241 	CSR_TPO3	= 0x00080000,
242 	CSR_RPO		= 0x00100000,
243 };
244 
245 /* ESR */
246 enum ESR_BIT {
247 	ESR_EQN		= 0x0000001F,
248 	ESR_ET		= 0x00000F00,
249 	ESR_EIL		= 0x00001000,
250 };
251 
252 /* APSR */
253 enum APSR_BIT {
254 	APSR_MEMS		= 0x00000002,
255 	APSR_CMSW		= 0x00000010,
256 	APSR_DM			= 0x00006000,	/* Undocumented? */
257 	APSR_DM_RDM		= 0x00002000,
258 	APSR_DM_TDM		= 0x00004000,
259 };
260 
261 /* RCR */
262 enum RCR_BIT {
263 	RCR_EFFS	= 0x00000001,
264 	RCR_ENCF	= 0x00000002,
265 	RCR_ESF		= 0x0000000C,
266 	RCR_ETS0	= 0x00000010,
267 	RCR_ETS2	= 0x00000020,
268 	RCR_RFCL	= 0x1FFF0000,
269 };
270 
271 /* RQC0/1/2/3/4 */
272 enum RQC_BIT {
273 	RQC_RSM0	= 0x00000003,
274 	RQC_UFCC0	= 0x00000030,
275 	RQC_RSM1	= 0x00000300,
276 	RQC_UFCC1	= 0x00003000,
277 	RQC_RSM2	= 0x00030000,
278 	RQC_UFCC2	= 0x00300000,
279 	RQC_RSM3	= 0x03000000,
280 	RQC_UFCC3	= 0x30000000,
281 };
282 
283 /* RPC */
284 enum RPC_BIT {
285 	RPC_PCNT	= 0x00000700,
286 	RPC_DCNT	= 0x00FF0000,
287 };
288 
289 /* UFCW */
290 enum UFCW_BIT {
291 	UFCW_WL0	= 0x0000003F,
292 	UFCW_WL1	= 0x00003F00,
293 	UFCW_WL2	= 0x003F0000,
294 	UFCW_WL3	= 0x3F000000,
295 };
296 
297 /* UFCS */
298 enum UFCS_BIT {
299 	UFCS_SL0	= 0x0000003F,
300 	UFCS_SL1	= 0x00003F00,
301 	UFCS_SL2	= 0x003F0000,
302 	UFCS_SL3	= 0x3F000000,
303 };
304 
305 /* UFCV0/1/2/3/4 */
306 enum UFCV_BIT {
307 	UFCV_CV0	= 0x0000003F,
308 	UFCV_CV1	= 0x00003F00,
309 	UFCV_CV2	= 0x003F0000,
310 	UFCV_CV3	= 0x3F000000,
311 };
312 
313 /* UFCD0/1/2/3/4 */
314 enum UFCD_BIT {
315 	UFCD_DV0	= 0x0000003F,
316 	UFCD_DV1	= 0x00003F00,
317 	UFCD_DV2	= 0x003F0000,
318 	UFCD_DV3	= 0x3F000000,
319 };
320 
321 /* SFO */
322 enum SFO_BIT {
323 	SFO_FPB		= 0x0000003F,
324 };
325 
326 /* RTC */
327 enum RTC_BIT {
328 	RTC_MFL0	= 0x00000FFF,
329 	RTC_MFL1	= 0x0FFF0000,
330 };
331 
332 /* TGC */
333 enum TGC_BIT {
334 	TGC_TSM0	= 0x00000001,
335 	TGC_TSM1	= 0x00000002,
336 	TGC_TSM2	= 0x00000004,
337 	TGC_TSM3	= 0x00000008,
338 	TGC_TQP		= 0x00000030,
339 	TGC_TQP_NONAVB	= 0x00000000,
340 	TGC_TQP_AVBMODE1 = 0x00000010,
341 	TGC_TQP_AVBMODE2 = 0x00000030,
342 	TGC_TBD0	= 0x00000300,
343 	TGC_TBD1	= 0x00003000,
344 	TGC_TBD2	= 0x00030000,
345 	TGC_TBD3	= 0x00300000,
346 };
347 
348 /* TCCR */
349 enum TCCR_BIT {
350 	TCCR_TSRQ0	= 0x00000001,
351 	TCCR_TSRQ1	= 0x00000002,
352 	TCCR_TSRQ2	= 0x00000004,
353 	TCCR_TSRQ3	= 0x00000008,
354 	TCCR_TFEN	= 0x00000100,
355 	TCCR_TFR	= 0x00000200,
356 };
357 
358 /* TSR */
359 enum TSR_BIT {
360 	TSR_CCS0	= 0x00000003,
361 	TSR_CCS1	= 0x0000000C,
362 	TSR_TFFL	= 0x00000700,
363 };
364 
365 /* TFA2 */
366 enum TFA2_BIT {
367 	TFA2_TSV	= 0x0000FFFF,
368 	TFA2_TST	= 0x03FF0000,
369 };
370 
371 /* DIC */
372 enum DIC_BIT {
373 	DIC_DPE1	= 0x00000002,
374 	DIC_DPE2	= 0x00000004,
375 	DIC_DPE3	= 0x00000008,
376 	DIC_DPE4	= 0x00000010,
377 	DIC_DPE5	= 0x00000020,
378 	DIC_DPE6	= 0x00000040,
379 	DIC_DPE7	= 0x00000080,
380 	DIC_DPE8	= 0x00000100,
381 	DIC_DPE9	= 0x00000200,
382 	DIC_DPE10	= 0x00000400,
383 	DIC_DPE11	= 0x00000800,
384 	DIC_DPE12	= 0x00001000,
385 	DIC_DPE13	= 0x00002000,
386 	DIC_DPE14	= 0x00004000,
387 	DIC_DPE15	= 0x00008000,
388 };
389 
390 /* DIS */
391 enum DIS_BIT {
392 	DIS_DPF1	= 0x00000002,
393 	DIS_DPF2	= 0x00000004,
394 	DIS_DPF3	= 0x00000008,
395 	DIS_DPF4	= 0x00000010,
396 	DIS_DPF5	= 0x00000020,
397 	DIS_DPF6	= 0x00000040,
398 	DIS_DPF7	= 0x00000080,
399 	DIS_DPF8	= 0x00000100,
400 	DIS_DPF9	= 0x00000200,
401 	DIS_DPF10	= 0x00000400,
402 	DIS_DPF11	= 0x00000800,
403 	DIS_DPF12	= 0x00001000,
404 	DIS_DPF13	= 0x00002000,
405 	DIS_DPF14	= 0x00004000,
406 	DIS_DPF15	= 0x00008000,
407 };
408 
409 /* EIC */
410 enum EIC_BIT {
411 	EIC_MREE	= 0x00000001,
412 	EIC_MTEE	= 0x00000002,
413 	EIC_QEE		= 0x00000004,
414 	EIC_SEE		= 0x00000008,
415 	EIC_CLLE0	= 0x00000010,
416 	EIC_CLLE1	= 0x00000020,
417 	EIC_CULE0	= 0x00000040,
418 	EIC_CULE1	= 0x00000080,
419 	EIC_TFFE	= 0x00000100,
420 };
421 
422 /* EIS */
423 enum EIS_BIT {
424 	EIS_MREF	= 0x00000001,
425 	EIS_MTEF	= 0x00000002,
426 	EIS_QEF		= 0x00000004,
427 	EIS_SEF		= 0x00000008,
428 	EIS_CLLF0	= 0x00000010,
429 	EIS_CLLF1	= 0x00000020,
430 	EIS_CULF0	= 0x00000040,
431 	EIS_CULF1	= 0x00000080,
432 	EIS_TFFF	= 0x00000100,
433 	EIS_QFS		= 0x00010000,
434 };
435 
436 /* RIC0 */
437 enum RIC0_BIT {
438 	RIC0_FRE0	= 0x00000001,
439 	RIC0_FRE1	= 0x00000002,
440 	RIC0_FRE2	= 0x00000004,
441 	RIC0_FRE3	= 0x00000008,
442 	RIC0_FRE4	= 0x00000010,
443 	RIC0_FRE5	= 0x00000020,
444 	RIC0_FRE6	= 0x00000040,
445 	RIC0_FRE7	= 0x00000080,
446 	RIC0_FRE8	= 0x00000100,
447 	RIC0_FRE9	= 0x00000200,
448 	RIC0_FRE10	= 0x00000400,
449 	RIC0_FRE11	= 0x00000800,
450 	RIC0_FRE12	= 0x00001000,
451 	RIC0_FRE13	= 0x00002000,
452 	RIC0_FRE14	= 0x00004000,
453 	RIC0_FRE15	= 0x00008000,
454 	RIC0_FRE16	= 0x00010000,
455 	RIC0_FRE17	= 0x00020000,
456 };
457 
458 /* RIC0 */
459 enum RIS0_BIT {
460 	RIS0_FRF0	= 0x00000001,
461 	RIS0_FRF1	= 0x00000002,
462 	RIS0_FRF2	= 0x00000004,
463 	RIS0_FRF3	= 0x00000008,
464 	RIS0_FRF4	= 0x00000010,
465 	RIS0_FRF5	= 0x00000020,
466 	RIS0_FRF6	= 0x00000040,
467 	RIS0_FRF7	= 0x00000080,
468 	RIS0_FRF8	= 0x00000100,
469 	RIS0_FRF9	= 0x00000200,
470 	RIS0_FRF10	= 0x00000400,
471 	RIS0_FRF11	= 0x00000800,
472 	RIS0_FRF12	= 0x00001000,
473 	RIS0_FRF13	= 0x00002000,
474 	RIS0_FRF14	= 0x00004000,
475 	RIS0_FRF15	= 0x00008000,
476 	RIS0_FRF16	= 0x00010000,
477 	RIS0_FRF17	= 0x00020000,
478 };
479 
480 /* RIC1 */
481 enum RIC1_BIT {
482 	RIC1_RFWE	= 0x80000000,
483 };
484 
485 /* RIS1 */
486 enum RIS1_BIT {
487 	RIS1_RFWF	= 0x80000000,
488 };
489 
490 /* RIC2 */
491 enum RIC2_BIT {
492 	RIC2_QFE0	= 0x00000001,
493 	RIC2_QFE1	= 0x00000002,
494 	RIC2_QFE2	= 0x00000004,
495 	RIC2_QFE3	= 0x00000008,
496 	RIC2_QFE4	= 0x00000010,
497 	RIC2_QFE5	= 0x00000020,
498 	RIC2_QFE6	= 0x00000040,
499 	RIC2_QFE7	= 0x00000080,
500 	RIC2_QFE8	= 0x00000100,
501 	RIC2_QFE9	= 0x00000200,
502 	RIC2_QFE10	= 0x00000400,
503 	RIC2_QFE11	= 0x00000800,
504 	RIC2_QFE12	= 0x00001000,
505 	RIC2_QFE13	= 0x00002000,
506 	RIC2_QFE14	= 0x00004000,
507 	RIC2_QFE15	= 0x00008000,
508 	RIC2_QFE16	= 0x00010000,
509 	RIC2_QFE17	= 0x00020000,
510 	RIC2_RFFE	= 0x80000000,
511 };
512 
513 /* RIS2 */
514 enum RIS2_BIT {
515 	RIS2_QFF0	= 0x00000001,
516 	RIS2_QFF1	= 0x00000002,
517 	RIS2_QFF2	= 0x00000004,
518 	RIS2_QFF3	= 0x00000008,
519 	RIS2_QFF4	= 0x00000010,
520 	RIS2_QFF5	= 0x00000020,
521 	RIS2_QFF6	= 0x00000040,
522 	RIS2_QFF7	= 0x00000080,
523 	RIS2_QFF8	= 0x00000100,
524 	RIS2_QFF9	= 0x00000200,
525 	RIS2_QFF10	= 0x00000400,
526 	RIS2_QFF11	= 0x00000800,
527 	RIS2_QFF12	= 0x00001000,
528 	RIS2_QFF13	= 0x00002000,
529 	RIS2_QFF14	= 0x00004000,
530 	RIS2_QFF15	= 0x00008000,
531 	RIS2_QFF16	= 0x00010000,
532 	RIS2_QFF17	= 0x00020000,
533 	RIS2_RFFF	= 0x80000000,
534 };
535 
536 /* TIC */
537 enum TIC_BIT {
538 	TIC_FTE0	= 0x00000001,	/* Undocumented? */
539 	TIC_FTE1	= 0x00000002,	/* Undocumented? */
540 	TIC_TFUE	= 0x00000100,
541 	TIC_TFWE	= 0x00000200,
542 };
543 
544 /* TIS */
545 enum TIS_BIT {
546 	TIS_FTF0	= 0x00000001,	/* Undocumented? */
547 	TIS_FTF1	= 0x00000002,	/* Undocumented? */
548 	TIS_TFUF	= 0x00000100,
549 	TIS_TFWF	= 0x00000200,
550 };
551 
552 /* ISS */
553 enum ISS_BIT {
554 	ISS_FRS		= 0x00000001,	/* Undocumented? */
555 	ISS_FTS		= 0x00000004,	/* Undocumented? */
556 	ISS_ES		= 0x00000040,
557 	ISS_MS		= 0x00000080,
558 	ISS_TFUS	= 0x00000100,
559 	ISS_TFWS	= 0x00000200,
560 	ISS_RFWS	= 0x00001000,
561 	ISS_CGIS	= 0x00002000,
562 	ISS_DPS1	= 0x00020000,
563 	ISS_DPS2	= 0x00040000,
564 	ISS_DPS3	= 0x00080000,
565 	ISS_DPS4	= 0x00100000,
566 	ISS_DPS5	= 0x00200000,
567 	ISS_DPS6	= 0x00400000,
568 	ISS_DPS7	= 0x00800000,
569 	ISS_DPS8	= 0x01000000,
570 	ISS_DPS9	= 0x02000000,
571 	ISS_DPS10	= 0x04000000,
572 	ISS_DPS11	= 0x08000000,
573 	ISS_DPS12	= 0x10000000,
574 	ISS_DPS13	= 0x20000000,
575 	ISS_DPS14	= 0x40000000,
576 	ISS_DPS15	= 0x80000000,
577 };
578 
579 /* CIE (R-Car Gen3 only) */
580 enum CIE_BIT {
581 	CIE_CRIE	= 0x00000001,
582 	CIE_CTIE	= 0x00000100,
583 	CIE_RQFM	= 0x00010000,
584 	CIE_CL0M	= 0x00020000,
585 	CIE_RFWL	= 0x00040000,
586 	CIE_RFFL	= 0x00080000,
587 };
588 
589 /* GCCR */
590 enum GCCR_BIT {
591 	GCCR_TCR	= 0x00000003,
592 	GCCR_TCR_NOREQ	= 0x00000000, /* No request */
593 	GCCR_TCR_RESET	= 0x00000001, /* gPTP/AVTP presentation timer reset */
594 	GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */
595 	GCCR_LTO	= 0x00000004,
596 	GCCR_LTI	= 0x00000008,
597 	GCCR_LPTC	= 0x00000010,
598 	GCCR_LMTT	= 0x00000020,
599 	GCCR_TCSS	= 0x00000300,
600 	GCCR_TCSS_GPTP	= 0x00000000,	/* gPTP timer value */
601 	GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */
602 	GCCR_TCSS_AVTP	= 0x00000200,	/* AVTP presentation time value */
603 };
604 
605 /* GTI */
606 enum GTI_BIT {
607 	GTI_TIV		= 0x0FFFFFFF,
608 };
609 
610 #define GTI_TIV_MAX	GTI_TIV
611 #define GTI_TIV_MIN	0x20
612 
613 /* GIC */
614 enum GIC_BIT {
615 	GIC_PTCE	= 0x00000001,	/* Undocumented? */
616 	GIC_PTME	= 0x00000004,
617 };
618 
619 /* GIS */
620 enum GIS_BIT {
621 	GIS_PTCF	= 0x00000001,	/* Undocumented? */
622 	GIS_PTMF	= 0x00000004,
623 };
624 
625 /* GIE (R-Car Gen3 only) */
626 enum GIE_BIT {
627 	GIE_PTCS	= 0x00000001,
628 	GIE_PTOS	= 0x00000002,
629 	GIE_PTMS0	= 0x00000004,
630 	GIE_PTMS1	= 0x00000008,
631 	GIE_PTMS2	= 0x00000010,
632 	GIE_PTMS3	= 0x00000020,
633 	GIE_PTMS4	= 0x00000040,
634 	GIE_PTMS5	= 0x00000080,
635 	GIE_PTMS6	= 0x00000100,
636 	GIE_PTMS7	= 0x00000200,
637 	GIE_ATCS0	= 0x00010000,
638 	GIE_ATCS1	= 0x00020000,
639 	GIE_ATCS2	= 0x00040000,
640 	GIE_ATCS3	= 0x00080000,
641 	GIE_ATCS4	= 0x00100000,
642 	GIE_ATCS5	= 0x00200000,
643 	GIE_ATCS6	= 0x00400000,
644 	GIE_ATCS7	= 0x00800000,
645 	GIE_ATCS8	= 0x01000000,
646 	GIE_ATCS9	= 0x02000000,
647 	GIE_ATCS10	= 0x04000000,
648 	GIE_ATCS11	= 0x08000000,
649 	GIE_ATCS12	= 0x10000000,
650 	GIE_ATCS13	= 0x20000000,
651 	GIE_ATCS14	= 0x40000000,
652 	GIE_ATCS15	= 0x80000000,
653 };
654 
655 /* GID (R-Car Gen3 only) */
656 enum GID_BIT {
657 	GID_PTCD	= 0x00000001,
658 	GID_PTOD	= 0x00000002,
659 	GID_PTMD0	= 0x00000004,
660 	GID_PTMD1	= 0x00000008,
661 	GID_PTMD2	= 0x00000010,
662 	GID_PTMD3	= 0x00000020,
663 	GID_PTMD4	= 0x00000040,
664 	GID_PTMD5	= 0x00000080,
665 	GID_PTMD6	= 0x00000100,
666 	GID_PTMD7	= 0x00000200,
667 	GID_ATCD0	= 0x00010000,
668 	GID_ATCD1	= 0x00020000,
669 	GID_ATCD2	= 0x00040000,
670 	GID_ATCD3	= 0x00080000,
671 	GID_ATCD4	= 0x00100000,
672 	GID_ATCD5	= 0x00200000,
673 	GID_ATCD6	= 0x00400000,
674 	GID_ATCD7	= 0x00800000,
675 	GID_ATCD8	= 0x01000000,
676 	GID_ATCD9	= 0x02000000,
677 	GID_ATCD10	= 0x04000000,
678 	GID_ATCD11	= 0x08000000,
679 	GID_ATCD12	= 0x10000000,
680 	GID_ATCD13	= 0x20000000,
681 	GID_ATCD14	= 0x40000000,
682 	GID_ATCD15	= 0x80000000,
683 };
684 
685 /* RIE0 (R-Car Gen3 only) */
686 enum RIE0_BIT {
687 	RIE0_FRS0	= 0x00000001,
688 	RIE0_FRS1	= 0x00000002,
689 	RIE0_FRS2	= 0x00000004,
690 	RIE0_FRS3	= 0x00000008,
691 	RIE0_FRS4	= 0x00000010,
692 	RIE0_FRS5	= 0x00000020,
693 	RIE0_FRS6	= 0x00000040,
694 	RIE0_FRS7	= 0x00000080,
695 	RIE0_FRS8	= 0x00000100,
696 	RIE0_FRS9	= 0x00000200,
697 	RIE0_FRS10	= 0x00000400,
698 	RIE0_FRS11	= 0x00000800,
699 	RIE0_FRS12	= 0x00001000,
700 	RIE0_FRS13	= 0x00002000,
701 	RIE0_FRS14	= 0x00004000,
702 	RIE0_FRS15	= 0x00008000,
703 	RIE0_FRS16	= 0x00010000,
704 	RIE0_FRS17	= 0x00020000,
705 };
706 
707 /* RID0 (R-Car Gen3 only) */
708 enum RID0_BIT {
709 	RID0_FRD0	= 0x00000001,
710 	RID0_FRD1	= 0x00000002,
711 	RID0_FRD2	= 0x00000004,
712 	RID0_FRD3	= 0x00000008,
713 	RID0_FRD4	= 0x00000010,
714 	RID0_FRD5	= 0x00000020,
715 	RID0_FRD6	= 0x00000040,
716 	RID0_FRD7	= 0x00000080,
717 	RID0_FRD8	= 0x00000100,
718 	RID0_FRD9	= 0x00000200,
719 	RID0_FRD10	= 0x00000400,
720 	RID0_FRD11	= 0x00000800,
721 	RID0_FRD12	= 0x00001000,
722 	RID0_FRD13	= 0x00002000,
723 	RID0_FRD14	= 0x00004000,
724 	RID0_FRD15	= 0x00008000,
725 	RID0_FRD16	= 0x00010000,
726 	RID0_FRD17	= 0x00020000,
727 };
728 
729 /* RIE2 (R-Car Gen3 only) */
730 enum RIE2_BIT {
731 	RIE2_QFS0	= 0x00000001,
732 	RIE2_QFS1	= 0x00000002,
733 	RIE2_QFS2	= 0x00000004,
734 	RIE2_QFS3	= 0x00000008,
735 	RIE2_QFS4	= 0x00000010,
736 	RIE2_QFS5	= 0x00000020,
737 	RIE2_QFS6	= 0x00000040,
738 	RIE2_QFS7	= 0x00000080,
739 	RIE2_QFS8	= 0x00000100,
740 	RIE2_QFS9	= 0x00000200,
741 	RIE2_QFS10	= 0x00000400,
742 	RIE2_QFS11	= 0x00000800,
743 	RIE2_QFS12	= 0x00001000,
744 	RIE2_QFS13	= 0x00002000,
745 	RIE2_QFS14	= 0x00004000,
746 	RIE2_QFS15	= 0x00008000,
747 	RIE2_QFS16	= 0x00010000,
748 	RIE2_QFS17	= 0x00020000,
749 	RIE2_RFFS	= 0x80000000,
750 };
751 
752 /* RID2 (R-Car Gen3 only) */
753 enum RID2_BIT {
754 	RID2_QFD0	= 0x00000001,
755 	RID2_QFD1	= 0x00000002,
756 	RID2_QFD2	= 0x00000004,
757 	RID2_QFD3	= 0x00000008,
758 	RID2_QFD4	= 0x00000010,
759 	RID2_QFD5	= 0x00000020,
760 	RID2_QFD6	= 0x00000040,
761 	RID2_QFD7	= 0x00000080,
762 	RID2_QFD8	= 0x00000100,
763 	RID2_QFD9	= 0x00000200,
764 	RID2_QFD10	= 0x00000400,
765 	RID2_QFD11	= 0x00000800,
766 	RID2_QFD12	= 0x00001000,
767 	RID2_QFD13	= 0x00002000,
768 	RID2_QFD14	= 0x00004000,
769 	RID2_QFD15	= 0x00008000,
770 	RID2_QFD16	= 0x00010000,
771 	RID2_QFD17	= 0x00020000,
772 	RID2_RFFD	= 0x80000000,
773 };
774 
775 /* TIE (R-Car Gen3 only) */
776 enum TIE_BIT {
777 	TIE_FTS0	= 0x00000001,
778 	TIE_FTS1	= 0x00000002,
779 	TIE_FTS2	= 0x00000004,
780 	TIE_FTS3	= 0x00000008,
781 	TIE_TFUS	= 0x00000100,
782 	TIE_TFWS	= 0x00000200,
783 	TIE_MFUS	= 0x00000400,
784 	TIE_MFWS	= 0x00000800,
785 	TIE_TDPS0	= 0x00010000,
786 	TIE_TDPS1	= 0x00020000,
787 	TIE_TDPS2	= 0x00040000,
788 	TIE_TDPS3	= 0x00080000,
789 };
790 
791 /* TID (R-Car Gen3 only) */
792 enum TID_BIT {
793 	TID_FTD0	= 0x00000001,
794 	TID_FTD1	= 0x00000002,
795 	TID_FTD2	= 0x00000004,
796 	TID_FTD3	= 0x00000008,
797 	TID_TFUD	= 0x00000100,
798 	TID_TFWD	= 0x00000200,
799 	TID_MFUD	= 0x00000400,
800 	TID_MFWD	= 0x00000800,
801 	TID_TDPD0	= 0x00010000,
802 	TID_TDPD1	= 0x00020000,
803 	TID_TDPD2	= 0x00040000,
804 	TID_TDPD3	= 0x00080000,
805 };
806 
807 /* ECMR */
808 enum ECMR_BIT {
809 	ECMR_PRM	= 0x00000001,
810 	ECMR_DM		= 0x00000002,
811 	ECMR_TE		= 0x00000020,
812 	ECMR_RE		= 0x00000040,
813 	ECMR_MPDE	= 0x00000200,
814 	ECMR_TXF	= 0x00010000,	/* Undocumented? */
815 	ECMR_RXF	= 0x00020000,
816 	ECMR_PFR	= 0x00040000,
817 	ECMR_ZPF	= 0x00080000,	/* Undocumented? */
818 	ECMR_RZPF	= 0x00100000,
819 	ECMR_DPAD	= 0x00200000,
820 	ECMR_RCSC	= 0x00800000,
821 	ECMR_TRCCM	= 0x04000000,
822 };
823 
824 /* ECSR */
825 enum ECSR_BIT {
826 	ECSR_ICD	= 0x00000001,
827 	ECSR_MPD	= 0x00000002,
828 	ECSR_LCHNG	= 0x00000004,
829 	ECSR_PHYI	= 0x00000008,
830 };
831 
832 /* ECSIPR */
833 enum ECSIPR_BIT {
834 	ECSIPR_ICDIP	= 0x00000001,
835 	ECSIPR_MPDIP	= 0x00000002,
836 	ECSIPR_LCHNGIP	= 0x00000004,	/* Undocumented? */
837 };
838 
839 /* PIR */
840 enum PIR_BIT {
841 	PIR_MDC		= 0x00000001,
842 	PIR_MMD		= 0x00000002,
843 	PIR_MDO		= 0x00000004,
844 	PIR_MDI		= 0x00000008,
845 };
846 
847 /* PSR */
848 enum PSR_BIT {
849 	PSR_LMON	= 0x00000001,
850 };
851 
852 /* PIPR */
853 enum PIPR_BIT {
854 	PIPR_PHYIP	= 0x00000001,
855 };
856 
857 /* MPR */
858 enum MPR_BIT {
859 	MPR_MP		= 0x0000ffff,
860 };
861 
862 /* GECMR */
863 enum GECMR_BIT {
864 	GECMR_SPEED	= 0x00000001,
865 	GECMR_SPEED_100	= 0x00000000,
866 	GECMR_SPEED_1000 = 0x00000001,
867 };
868 
869 /* The Ethernet AVB descriptor definitions. */
870 struct ravb_desc {
871 	__le16 ds;		/* Descriptor size */
872 	u8 cc;		/* Content control MSBs (reserved) */
873 	u8 die_dt;	/* Descriptor interrupt enable and type */
874 	__le32 dptr;	/* Descriptor pointer */
875 };
876 
877 #define DPTR_ALIGN	4	/* Required descriptor pointer alignment */
878 
879 enum DIE_DT {
880 	/* Frame data */
881 	DT_FMID		= 0x40,
882 	DT_FSTART	= 0x50,
883 	DT_FEND		= 0x60,
884 	DT_FSINGLE	= 0x70,
885 	/* Chain control */
886 	DT_LINK		= 0x80,
887 	DT_LINKFIX	= 0x90,
888 	DT_EOS		= 0xa0,
889 	/* HW/SW arbitration */
890 	DT_FEMPTY	= 0xc0,
891 	DT_FEMPTY_IS	= 0xd0,
892 	DT_FEMPTY_IC	= 0xe0,
893 	DT_FEMPTY_ND	= 0xf0,
894 	DT_LEMPTY	= 0x20,
895 	DT_EEMPTY	= 0x30,
896 };
897 
898 struct ravb_rx_desc {
899 	__le16 ds_cc;	/* Descriptor size and content control LSBs */
900 	u8 msc;		/* MAC status code */
901 	u8 die_dt;	/* Descriptor interrupt enable and type */
902 	__le32 dptr;	/* Descpriptor pointer */
903 };
904 
905 struct ravb_ex_rx_desc {
906 	__le16 ds_cc;	/* Descriptor size and content control lower bits */
907 	u8 msc;		/* MAC status code */
908 	u8 die_dt;	/* Descriptor interrupt enable and type */
909 	__le32 dptr;	/* Descpriptor pointer */
910 	__le32 ts_n;	/* Timestampe nsec */
911 	__le32 ts_sl;	/* Timestamp low */
912 	__le16 ts_sh;	/* Timestamp high */
913 	__le16 res;	/* Reserved bits */
914 };
915 
916 enum RX_DS_CC_BIT {
917 	RX_DS		= 0x0fff, /* Data size */
918 	RX_TR		= 0x1000, /* Truncation indication */
919 	RX_EI		= 0x2000, /* Error indication */
920 	RX_PS		= 0xc000, /* Padding selection */
921 };
922 
923 /* E-MAC status code */
924 enum MSC_BIT {
925 	MSC_CRC		= 0x01, /* Frame CRC error */
926 	MSC_RFE		= 0x02, /* Frame reception error (flagged by PHY) */
927 	MSC_RTSF	= 0x04, /* Frame length error (frame too short) */
928 	MSC_RTLF	= 0x08, /* Frame length error (frame too long) */
929 	MSC_FRE		= 0x10, /* Fraction error (not a multiple of 8 bits) */
930 	MSC_CRL		= 0x20, /* Carrier lost */
931 	MSC_CEEF	= 0x40, /* Carrier extension error */
932 	MSC_MC		= 0x80, /* Multicast frame reception */
933 };
934 
935 struct ravb_tx_desc {
936 	__le16 ds_tagl;	/* Descriptor size and frame tag LSBs */
937 	u8 tagh_tsr;	/* Frame tag MSBs and timestamp storage request bit */
938 	u8 die_dt;	/* Descriptor interrupt enable and type */
939 	__le32 dptr;	/* Descpriptor pointer */
940 };
941 
942 enum TX_DS_TAGL_BIT {
943 	TX_DS		= 0x0fff, /* Data size */
944 	TX_TAGL		= 0xf000, /* Frame tag LSBs */
945 };
946 
947 enum TX_TAGH_TSR_BIT {
948 	TX_TAGH		= 0x3f, /* Frame tag MSBs */
949 	TX_TSR		= 0x40, /* Timestamp storage request */
950 };
951 enum RAVB_QUEUE {
952 	RAVB_BE = 0,	/* Best Effort Queue */
953 	RAVB_NC,	/* Network Control Queue */
954 };
955 
956 #define DBAT_ENTRY_NUM	22
957 #define RX_QUEUE_OFFSET	4
958 #define NUM_RX_QUEUE	2
959 #define NUM_TX_QUEUE	2
960 #define NUM_TX_DESC	2	/* TX descriptors per packet */
961 
962 struct ravb_tstamp_skb {
963 	struct list_head list;
964 	struct sk_buff *skb;
965 	u16 tag;
966 };
967 
968 struct ravb_ptp_perout {
969 	u32 target;
970 	u32 period;
971 };
972 
973 #define N_EXT_TS	1
974 #define N_PER_OUT	1
975 
976 struct ravb_ptp {
977 	struct ptp_clock *clock;
978 	struct ptp_clock_info info;
979 	u32 default_addend;
980 	u32 current_addend;
981 	int extts[N_EXT_TS];
982 	struct ravb_ptp_perout perout[N_PER_OUT];
983 };
984 
985 enum ravb_chip_id {
986 	RCAR_GEN2,
987 	RCAR_GEN3,
988 };
989 
990 struct ravb_private {
991 	struct net_device *ndev;
992 	struct platform_device *pdev;
993 	void __iomem *addr;
994 	struct clk *clk;
995 	struct mdiobb_ctrl mdiobb;
996 	u32 num_rx_ring[NUM_RX_QUEUE];
997 	u32 num_tx_ring[NUM_TX_QUEUE];
998 	u32 desc_bat_size;
999 	dma_addr_t desc_bat_dma;
1000 	struct ravb_desc *desc_bat;
1001 	dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
1002 	dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
1003 	struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE];
1004 	struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
1005 	void *tx_align[NUM_TX_QUEUE];
1006 	struct sk_buff **rx_skb[NUM_RX_QUEUE];
1007 	struct sk_buff **tx_skb[NUM_TX_QUEUE];
1008 	u32 rx_over_errors;
1009 	u32 rx_fifo_errors;
1010 	struct net_device_stats stats[NUM_RX_QUEUE];
1011 	u32 tstamp_tx_ctrl;
1012 	u32 tstamp_rx_ctrl;
1013 	struct list_head ts_skb_list;
1014 	u32 ts_skb_tag;
1015 	struct ravb_ptp ptp;
1016 	spinlock_t lock;		/* Register access lock */
1017 	u32 cur_rx[NUM_RX_QUEUE];	/* Consumer ring indices */
1018 	u32 dirty_rx[NUM_RX_QUEUE];	/* Producer ring indices */
1019 	u32 cur_tx[NUM_TX_QUEUE];
1020 	u32 dirty_tx[NUM_TX_QUEUE];
1021 	u32 rx_buf_sz;			/* Based on MTU+slack. */
1022 	struct napi_struct napi[NUM_RX_QUEUE];
1023 	struct work_struct work;
1024 	/* MII transceiver section. */
1025 	struct mii_bus *mii_bus;	/* MDIO bus control */
1026 	int link;
1027 	phy_interface_t phy_interface;
1028 	int msg_enable;
1029 	int speed;
1030 	int duplex;
1031 	int emac_irq;
1032 	enum ravb_chip_id chip_id;
1033 	int rx_irqs[NUM_RX_QUEUE];
1034 	int tx_irqs[NUM_TX_QUEUE];
1035 
1036 	unsigned no_avb_link:1;
1037 	unsigned avb_link_active_low:1;
1038 	unsigned wol_enabled:1;
1039 };
1040 
1041 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
1042 {
1043 	struct ravb_private *priv = netdev_priv(ndev);
1044 
1045 	return ioread32(priv->addr + reg);
1046 }
1047 
1048 static inline void ravb_write(struct net_device *ndev, u32 data,
1049 			      enum ravb_reg reg)
1050 {
1051 	struct ravb_private *priv = netdev_priv(ndev);
1052 
1053 	iowrite32(data, priv->addr + reg);
1054 }
1055 
1056 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
1057 		 u32 set);
1058 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
1059 
1060 void ravb_ptp_interrupt(struct net_device *ndev);
1061 void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev);
1062 void ravb_ptp_stop(struct net_device *ndev);
1063 
1064 #endif	/* #ifndef __RAVB_H__ */
1065