1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/phy.h> 14 15 #include "r8169.h" 16 17 typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp, 18 struct phy_device *phydev); 19 20 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage, 21 int reg, u16 mask, u16 val) 22 { 23 int oldpage = phy_select_page(phydev, 0x0007); 24 25 __phy_write(phydev, 0x1e, extpage); 26 __phy_modify(phydev, reg, mask, val); 27 28 phy_restore_page(phydev, oldpage, 0); 29 } 30 31 static void r8168d_phy_param(struct phy_device *phydev, u16 parm, 32 u16 mask, u16 val) 33 { 34 int oldpage = phy_select_page(phydev, 0x0005); 35 36 __phy_write(phydev, 0x05, parm); 37 __phy_modify(phydev, 0x06, mask, val); 38 39 phy_restore_page(phydev, oldpage, 0); 40 } 41 42 static void r8168g_phy_param(struct phy_device *phydev, u16 parm, 43 u16 mask, u16 val) 44 { 45 int oldpage = phy_select_page(phydev, 0x0a43); 46 47 __phy_write(phydev, 0x13, parm); 48 __phy_modify(phydev, 0x14, mask, val); 49 50 phy_restore_page(phydev, oldpage, 0); 51 } 52 53 struct phy_reg { 54 u16 reg; 55 u16 val; 56 }; 57 58 static void __rtl_writephy_batch(struct phy_device *phydev, 59 const struct phy_reg *regs, int len) 60 { 61 phy_lock_mdio_bus(phydev); 62 63 while (len-- > 0) { 64 __phy_write(phydev, regs->reg, regs->val); 65 regs++; 66 } 67 68 phy_unlock_mdio_bus(phydev); 69 } 70 71 #define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a)) 72 73 static void rtl8168f_config_eee_phy(struct phy_device *phydev) 74 { 75 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8)); 76 r8168d_phy_param(phydev, 0x8b85, 0, BIT(13)); 77 } 78 79 static void rtl8168g_config_eee_phy(struct phy_device *phydev) 80 { 81 phy_modify_paged(phydev, 0x0a43, 0x11, 0, BIT(4)); 82 } 83 84 static void rtl8168h_config_eee_phy(struct phy_device *phydev) 85 { 86 rtl8168g_config_eee_phy(phydev); 87 88 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 89 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 90 } 91 92 static void rtl8125a_config_eee_phy(struct phy_device *phydev) 93 { 94 rtl8168h_config_eee_phy(phydev); 95 96 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 97 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 98 } 99 100 static void rtl8125b_config_eee_phy(struct phy_device *phydev) 101 { 102 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 103 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 104 phy_modify_paged(phydev, 0xa42, 0x14, 0x0080, 0x0000); 105 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0200, 0x0000); 106 } 107 108 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp, 109 struct phy_device *phydev) 110 { 111 static const struct phy_reg phy_reg_init[] = { 112 { 0x1f, 0x0001 }, 113 { 0x06, 0x006e }, 114 { 0x08, 0x0708 }, 115 { 0x15, 0x4000 }, 116 { 0x18, 0x65c7 }, 117 118 { 0x1f, 0x0001 }, 119 { 0x03, 0x00a1 }, 120 { 0x02, 0x0008 }, 121 { 0x01, 0x0120 }, 122 { 0x00, 0x1000 }, 123 { 0x04, 0x0800 }, 124 { 0x04, 0x0000 }, 125 126 { 0x03, 0xff41 }, 127 { 0x02, 0xdf60 }, 128 { 0x01, 0x0140 }, 129 { 0x00, 0x0077 }, 130 { 0x04, 0x7800 }, 131 { 0x04, 0x7000 }, 132 133 { 0x03, 0x802f }, 134 { 0x02, 0x4f02 }, 135 { 0x01, 0x0409 }, 136 { 0x00, 0xf0f9 }, 137 { 0x04, 0x9800 }, 138 { 0x04, 0x9000 }, 139 140 { 0x03, 0xdf01 }, 141 { 0x02, 0xdf20 }, 142 { 0x01, 0xff95 }, 143 { 0x00, 0xba00 }, 144 { 0x04, 0xa800 }, 145 { 0x04, 0xa000 }, 146 147 { 0x03, 0xff41 }, 148 { 0x02, 0xdf20 }, 149 { 0x01, 0x0140 }, 150 { 0x00, 0x00bb }, 151 { 0x04, 0xb800 }, 152 { 0x04, 0xb000 }, 153 154 { 0x03, 0xdf41 }, 155 { 0x02, 0xdc60 }, 156 { 0x01, 0x6340 }, 157 { 0x00, 0x007d }, 158 { 0x04, 0xd800 }, 159 { 0x04, 0xd000 }, 160 161 { 0x03, 0xdf01 }, 162 { 0x02, 0xdf20 }, 163 { 0x01, 0x100a }, 164 { 0x00, 0xa0ff }, 165 { 0x04, 0xf800 }, 166 { 0x04, 0xf000 }, 167 168 { 0x1f, 0x0000 }, 169 { 0x0b, 0x0000 }, 170 { 0x00, 0x9200 } 171 }; 172 173 rtl_writephy_batch(phydev, phy_reg_init); 174 } 175 176 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp, 177 struct phy_device *phydev) 178 { 179 phy_write_paged(phydev, 0x0002, 0x01, 0x90d0); 180 } 181 182 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, 183 struct phy_device *phydev) 184 { 185 static const struct phy_reg phy_reg_init[] = { 186 { 0x1f, 0x0001 }, 187 { 0x04, 0x0000 }, 188 { 0x03, 0x00a1 }, 189 { 0x02, 0x0008 }, 190 { 0x01, 0x0120 }, 191 { 0x00, 0x1000 }, 192 { 0x04, 0x0800 }, 193 { 0x04, 0x9000 }, 194 { 0x03, 0x802f }, 195 { 0x02, 0x4f02 }, 196 { 0x01, 0x0409 }, 197 { 0x00, 0xf099 }, 198 { 0x04, 0x9800 }, 199 { 0x04, 0xa000 }, 200 { 0x03, 0xdf01 }, 201 { 0x02, 0xdf20 }, 202 { 0x01, 0xff95 }, 203 { 0x00, 0xba00 }, 204 { 0x04, 0xa800 }, 205 { 0x04, 0xf000 }, 206 { 0x03, 0xdf01 }, 207 { 0x02, 0xdf20 }, 208 { 0x01, 0x101a }, 209 { 0x00, 0xa0ff }, 210 { 0x04, 0xf800 }, 211 { 0x04, 0x0000 }, 212 { 0x1f, 0x0000 }, 213 214 { 0x1f, 0x0001 }, 215 { 0x10, 0xf41b }, 216 { 0x14, 0xfb54 }, 217 { 0x18, 0xf5c7 }, 218 { 0x1f, 0x0000 }, 219 220 { 0x1f, 0x0001 }, 221 { 0x17, 0x0cc0 }, 222 { 0x1f, 0x0000 } 223 }; 224 225 rtl_writephy_batch(phydev, phy_reg_init); 226 } 227 228 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp, 229 struct phy_device *phydev) 230 { 231 static const struct phy_reg phy_reg_init[] = { 232 { 0x1f, 0x0001 }, 233 { 0x04, 0x0000 }, 234 { 0x03, 0x00a1 }, 235 { 0x02, 0x0008 }, 236 { 0x01, 0x0120 }, 237 { 0x00, 0x1000 }, 238 { 0x04, 0x0800 }, 239 { 0x04, 0x9000 }, 240 { 0x03, 0x802f }, 241 { 0x02, 0x4f02 }, 242 { 0x01, 0x0409 }, 243 { 0x00, 0xf099 }, 244 { 0x04, 0x9800 }, 245 { 0x04, 0xa000 }, 246 { 0x03, 0xdf01 }, 247 { 0x02, 0xdf20 }, 248 { 0x01, 0xff95 }, 249 { 0x00, 0xba00 }, 250 { 0x04, 0xa800 }, 251 { 0x04, 0xf000 }, 252 { 0x03, 0xdf01 }, 253 { 0x02, 0xdf20 }, 254 { 0x01, 0x101a }, 255 { 0x00, 0xa0ff }, 256 { 0x04, 0xf800 }, 257 { 0x04, 0x0000 }, 258 { 0x1f, 0x0000 }, 259 260 { 0x1f, 0x0001 }, 261 { 0x0b, 0x8480 }, 262 { 0x1f, 0x0000 }, 263 264 { 0x1f, 0x0001 }, 265 { 0x18, 0x67c7 }, 266 { 0x04, 0x2000 }, 267 { 0x03, 0x002f }, 268 { 0x02, 0x4360 }, 269 { 0x01, 0x0109 }, 270 { 0x00, 0x3022 }, 271 { 0x04, 0x2800 }, 272 { 0x1f, 0x0000 }, 273 274 { 0x1f, 0x0001 }, 275 { 0x17, 0x0cc0 }, 276 { 0x1f, 0x0000 } 277 }; 278 279 rtl_writephy_batch(phydev, phy_reg_init); 280 } 281 282 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp, 283 struct phy_device *phydev) 284 { 285 phy_write(phydev, 0x1f, 0x0001); 286 phy_set_bits(phydev, 0x16, BIT(0)); 287 phy_write(phydev, 0x10, 0xf41b); 288 phy_write(phydev, 0x1f, 0x0000); 289 } 290 291 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp, 292 struct phy_device *phydev) 293 { 294 phy_write_paged(phydev, 0x0001, 0x10, 0xf41b); 295 } 296 297 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp, 298 struct phy_device *phydev) 299 { 300 phy_write(phydev, 0x1d, 0x0f00); 301 phy_write_paged(phydev, 0x0002, 0x0c, 0x1ec8); 302 } 303 304 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp, 305 struct phy_device *phydev) 306 { 307 phy_set_bits(phydev, 0x14, BIT(5)); 308 phy_set_bits(phydev, 0x0d, BIT(5)); 309 phy_write_paged(phydev, 0x0001, 0x1d, 0x3d98); 310 } 311 312 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp, 313 struct phy_device *phydev) 314 { 315 static const struct phy_reg phy_reg_init[] = { 316 { 0x1f, 0x0001 }, 317 { 0x12, 0x2300 }, 318 { 0x1f, 0x0002 }, 319 { 0x00, 0x88d4 }, 320 { 0x01, 0x82b1 }, 321 { 0x03, 0x7002 }, 322 { 0x08, 0x9e30 }, 323 { 0x09, 0x01f0 }, 324 { 0x0a, 0x5500 }, 325 { 0x0c, 0x00c8 }, 326 { 0x1f, 0x0003 }, 327 { 0x12, 0xc096 }, 328 { 0x16, 0x000a }, 329 { 0x1f, 0x0000 }, 330 { 0x1f, 0x0000 }, 331 { 0x09, 0x2000 }, 332 { 0x09, 0x0000 } 333 }; 334 335 rtl_writephy_batch(phydev, phy_reg_init); 336 337 phy_set_bits(phydev, 0x14, BIT(5)); 338 phy_set_bits(phydev, 0x0d, BIT(5)); 339 } 340 341 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp, 342 struct phy_device *phydev) 343 { 344 static const struct phy_reg phy_reg_init[] = { 345 { 0x1f, 0x0001 }, 346 { 0x12, 0x2300 }, 347 { 0x03, 0x802f }, 348 { 0x02, 0x4f02 }, 349 { 0x01, 0x0409 }, 350 { 0x00, 0xf099 }, 351 { 0x04, 0x9800 }, 352 { 0x04, 0x9000 }, 353 { 0x1d, 0x3d98 }, 354 { 0x1f, 0x0002 }, 355 { 0x0c, 0x7eb8 }, 356 { 0x06, 0x0761 }, 357 { 0x1f, 0x0003 }, 358 { 0x16, 0x0f0a }, 359 { 0x1f, 0x0000 } 360 }; 361 362 rtl_writephy_batch(phydev, phy_reg_init); 363 364 phy_set_bits(phydev, 0x16, BIT(0)); 365 phy_set_bits(phydev, 0x14, BIT(5)); 366 phy_set_bits(phydev, 0x0d, BIT(5)); 367 } 368 369 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp, 370 struct phy_device *phydev) 371 { 372 static const struct phy_reg phy_reg_init[] = { 373 { 0x1f, 0x0001 }, 374 { 0x12, 0x2300 }, 375 { 0x1d, 0x3d98 }, 376 { 0x1f, 0x0002 }, 377 { 0x0c, 0x7eb8 }, 378 { 0x06, 0x5461 }, 379 { 0x1f, 0x0003 }, 380 { 0x16, 0x0f0a }, 381 { 0x1f, 0x0000 } 382 }; 383 384 rtl_writephy_batch(phydev, phy_reg_init); 385 386 phy_set_bits(phydev, 0x16, BIT(0)); 387 phy_set_bits(phydev, 0x14, BIT(5)); 388 phy_set_bits(phydev, 0x0d, BIT(5)); 389 } 390 391 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 392 /* Channel Estimation */ 393 { 0x1f, 0x0001 }, 394 { 0x06, 0x4064 }, 395 { 0x07, 0x2863 }, 396 { 0x08, 0x059c }, 397 { 0x09, 0x26b4 }, 398 { 0x0a, 0x6a19 }, 399 { 0x0b, 0xdcc8 }, 400 { 0x10, 0xf06d }, 401 { 0x14, 0x7f68 }, 402 { 0x18, 0x7fd9 }, 403 { 0x1c, 0xf0ff }, 404 { 0x1d, 0x3d9c }, 405 { 0x1f, 0x0003 }, 406 { 0x12, 0xf49f }, 407 { 0x13, 0x070b }, 408 { 0x1a, 0x05ad }, 409 { 0x14, 0x94c0 }, 410 411 /* 412 * Tx Error Issue 413 * Enhance line driver power 414 */ 415 { 0x1f, 0x0002 }, 416 { 0x06, 0x5561 }, 417 { 0x1f, 0x0005 }, 418 { 0x05, 0x8332 }, 419 { 0x06, 0x5561 }, 420 421 /* 422 * Can not link to 1Gbps with bad cable 423 * Decrease SNR threshold form 21.07dB to 19.04dB 424 */ 425 { 0x1f, 0x0001 }, 426 { 0x17, 0x0cc0 }, 427 428 { 0x1f, 0x0000 }, 429 { 0x0d, 0xf880 } 430 }; 431 432 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 433 { 0x1f, 0x0002 }, 434 { 0x05, 0x669a }, 435 { 0x1f, 0x0005 }, 436 { 0x05, 0x8330 }, 437 { 0x06, 0x669a }, 438 { 0x1f, 0x0002 } 439 }; 440 441 static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp, 442 struct phy_device *phydev, 443 u16 val) 444 { 445 u16 reg_val; 446 447 phy_write(phydev, 0x1f, 0x0005); 448 phy_write(phydev, 0x05, 0x001b); 449 reg_val = phy_read(phydev, 0x06); 450 phy_write(phydev, 0x1f, 0x0000); 451 452 if (reg_val != val) 453 phydev_warn(phydev, "chipset not ready for firmware\n"); 454 else 455 r8169_apply_firmware(tp); 456 } 457 458 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp, 459 struct phy_device *phydev) 460 { 461 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 462 463 /* 464 * Rx Error Issue 465 * Fine Tune Switching regulator parameter 466 */ 467 phy_write(phydev, 0x1f, 0x0002); 468 phy_modify(phydev, 0x0b, 0x00ef, 0x0010); 469 phy_modify(phydev, 0x0c, 0x5d00, 0xa200); 470 471 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 472 int val; 473 474 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_1); 475 476 val = phy_read(phydev, 0x0d); 477 478 if ((val & 0x00ff) != 0x006c) { 479 static const u32 set[] = { 480 0x0065, 0x0066, 0x0067, 0x0068, 481 0x0069, 0x006a, 0x006b, 0x006c 482 }; 483 int i; 484 485 phy_write(phydev, 0x1f, 0x0002); 486 487 val &= 0xff00; 488 for (i = 0; i < ARRAY_SIZE(set); i++) 489 phy_write(phydev, 0x0d, val | set[i]); 490 } 491 } else { 492 phy_write_paged(phydev, 0x0002, 0x05, 0x6662); 493 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x6662); 494 } 495 496 /* RSET couple improve */ 497 phy_write(phydev, 0x1f, 0x0002); 498 phy_set_bits(phydev, 0x0d, 0x0300); 499 phy_set_bits(phydev, 0x0f, 0x0010); 500 501 /* Fine tune PLL performance */ 502 phy_write(phydev, 0x1f, 0x0002); 503 phy_modify(phydev, 0x02, 0x0600, 0x0100); 504 phy_clear_bits(phydev, 0x03, 0xe000); 505 phy_write(phydev, 0x1f, 0x0000); 506 507 rtl8168d_apply_firmware_cond(tp, phydev, 0xbf00); 508 } 509 510 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp, 511 struct phy_device *phydev) 512 { 513 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 514 515 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 516 int val; 517 518 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_1); 519 520 val = phy_read(phydev, 0x0d); 521 if ((val & 0x00ff) != 0x006c) { 522 static const u32 set[] = { 523 0x0065, 0x0066, 0x0067, 0x0068, 524 0x0069, 0x006a, 0x006b, 0x006c 525 }; 526 int i; 527 528 phy_write(phydev, 0x1f, 0x0002); 529 530 val &= 0xff00; 531 for (i = 0; i < ARRAY_SIZE(set); i++) 532 phy_write(phydev, 0x0d, val | set[i]); 533 } 534 } else { 535 phy_write_paged(phydev, 0x0002, 0x05, 0x2642); 536 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x2642); 537 } 538 539 /* Fine tune PLL performance */ 540 phy_write(phydev, 0x1f, 0x0002); 541 phy_modify(phydev, 0x02, 0x0600, 0x0100); 542 phy_clear_bits(phydev, 0x03, 0xe000); 543 phy_write(phydev, 0x1f, 0x0000); 544 545 /* Switching regulator Slew rate */ 546 phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0017); 547 548 rtl8168d_apply_firmware_cond(tp, phydev, 0xb300); 549 } 550 551 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp, 552 struct phy_device *phydev) 553 { 554 static const struct phy_reg phy_reg_init[] = { 555 { 0x1f, 0x0002 }, 556 { 0x10, 0x0008 }, 557 { 0x0d, 0x006c }, 558 559 { 0x1f, 0x0000 }, 560 { 0x0d, 0xf880 }, 561 562 { 0x1f, 0x0001 }, 563 { 0x17, 0x0cc0 }, 564 565 { 0x1f, 0x0001 }, 566 { 0x0b, 0xa4d8 }, 567 { 0x09, 0x281c }, 568 { 0x07, 0x2883 }, 569 { 0x0a, 0x6b35 }, 570 { 0x1d, 0x3da4 }, 571 { 0x1c, 0xeffd }, 572 { 0x14, 0x7f52 }, 573 { 0x18, 0x7fc6 }, 574 { 0x08, 0x0601 }, 575 { 0x06, 0x4063 }, 576 { 0x10, 0xf074 }, 577 { 0x1f, 0x0003 }, 578 { 0x13, 0x0789 }, 579 { 0x12, 0xf4bd }, 580 { 0x1a, 0x04fd }, 581 { 0x14, 0x84b0 }, 582 { 0x1f, 0x0000 }, 583 { 0x00, 0x9200 }, 584 585 { 0x1f, 0x0005 }, 586 { 0x01, 0x0340 }, 587 { 0x1f, 0x0001 }, 588 { 0x04, 0x4000 }, 589 { 0x03, 0x1d21 }, 590 { 0x02, 0x0c32 }, 591 { 0x01, 0x0200 }, 592 { 0x00, 0x5554 }, 593 { 0x04, 0x4800 }, 594 { 0x04, 0x4000 }, 595 { 0x04, 0xf000 }, 596 { 0x03, 0xdf01 }, 597 { 0x02, 0xdf20 }, 598 { 0x01, 0x101a }, 599 { 0x00, 0xa0ff }, 600 { 0x04, 0xf800 }, 601 { 0x04, 0xf000 }, 602 { 0x1f, 0x0000 }, 603 }; 604 605 rtl_writephy_batch(phydev, phy_reg_init); 606 r8168d_modify_extpage(phydev, 0x0023, 0x16, 0xffff, 0x0000); 607 } 608 609 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp, 610 struct phy_device *phydev) 611 { 612 phy_write_paged(phydev, 0x0001, 0x17, 0x0cc0); 613 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0xffff, 0x0040); 614 phy_set_bits(phydev, 0x0d, BIT(5)); 615 } 616 617 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp, 618 struct phy_device *phydev) 619 { 620 static const struct phy_reg phy_reg_init[] = { 621 /* Channel estimation fine tune */ 622 { 0x1f, 0x0001 }, 623 { 0x0b, 0x6c20 }, 624 { 0x07, 0x2872 }, 625 { 0x1c, 0xefff }, 626 { 0x1f, 0x0003 }, 627 { 0x14, 0x6420 }, 628 { 0x1f, 0x0000 }, 629 }; 630 631 r8169_apply_firmware(tp); 632 633 /* Enable Delay cap */ 634 r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896); 635 636 rtl_writephy_batch(phydev, phy_reg_init); 637 638 /* Update PFM & 10M TX idle timer */ 639 r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919); 640 641 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 642 643 /* DCO enable for 10M IDLE Power */ 644 r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006); 645 646 /* For impedance matching */ 647 phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000); 648 649 /* PHY auto speed down */ 650 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050); 651 phy_set_bits(phydev, 0x14, BIT(15)); 652 653 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 654 r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000); 655 656 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000); 657 phy_write_paged(phydev, 0x0006, 0x00, 0x5a00); 658 659 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); 660 } 661 662 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp, 663 struct phy_device *phydev) 664 { 665 r8169_apply_firmware(tp); 666 667 /* Enable Delay cap */ 668 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 669 670 /* Channel estimation fine tune */ 671 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 672 673 /* Green Setting */ 674 r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222); 675 r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000); 676 r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000); 677 678 /* For 4-corner performance improve */ 679 phy_write(phydev, 0x1f, 0x0005); 680 phy_write(phydev, 0x05, 0x8b80); 681 phy_set_bits(phydev, 0x17, 0x0006); 682 phy_write(phydev, 0x1f, 0x0000); 683 684 /* PHY auto speed down */ 685 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 686 phy_set_bits(phydev, 0x14, BIT(15)); 687 688 /* improve 10M EEE waveform */ 689 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 690 691 /* Improve 2-pair detection performance */ 692 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 693 694 rtl8168f_config_eee_phy(phydev); 695 696 /* Green feature */ 697 phy_write(phydev, 0x1f, 0x0003); 698 phy_set_bits(phydev, 0x19, BIT(0)); 699 phy_set_bits(phydev, 0x10, BIT(10)); 700 phy_write(phydev, 0x1f, 0x0000); 701 phy_modify_paged(phydev, 0x0005, 0x01, 0, BIT(8)); 702 } 703 704 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp, 705 struct phy_device *phydev) 706 { 707 /* For 4-corner performance improve */ 708 r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006); 709 710 /* PHY auto speed down */ 711 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 712 phy_set_bits(phydev, 0x14, BIT(15)); 713 714 /* Improve 10M EEE waveform */ 715 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 716 717 rtl8168f_config_eee_phy(phydev); 718 } 719 720 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp, 721 struct phy_device *phydev) 722 { 723 r8169_apply_firmware(tp); 724 725 /* Channel estimation fine tune */ 726 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 727 728 /* Modify green table for giga & fnet */ 729 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 730 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 731 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 732 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 733 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 734 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb); 735 736 /* Modify green table for 10M */ 737 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 738 739 /* Disable hiimpedance detection (RTCT) */ 740 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 741 742 rtl8168f_hw_phy_config(tp, phydev); 743 744 /* Improve 2-pair detection performance */ 745 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 746 } 747 748 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp, 749 struct phy_device *phydev) 750 { 751 r8169_apply_firmware(tp); 752 753 rtl8168f_hw_phy_config(tp, phydev); 754 } 755 756 static void rtl8411_hw_phy_config(struct rtl8169_private *tp, 757 struct phy_device *phydev) 758 { 759 r8169_apply_firmware(tp); 760 761 rtl8168f_hw_phy_config(tp, phydev); 762 763 /* Improve 2-pair detection performance */ 764 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 765 766 /* Channel estimation fine tune */ 767 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 768 769 /* Modify green table for giga & fnet */ 770 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 771 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 772 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 773 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 774 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 775 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa); 776 777 /* Modify green table for 10M */ 778 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 779 780 /* Disable hiimpedance detection (RTCT) */ 781 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 782 783 /* Modify green table for giga */ 784 r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000); 785 r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000); 786 r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000); 787 r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100); 788 r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000); 789 r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000); 790 r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000); 791 792 /* uc same-seed solution */ 793 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000); 794 795 /* Green feature */ 796 phy_write(phydev, 0x1f, 0x0003); 797 phy_clear_bits(phydev, 0x19, BIT(0)); 798 phy_clear_bits(phydev, 0x10, BIT(10)); 799 phy_write(phydev, 0x1f, 0x0000); 800 } 801 802 static void rtl8168g_disable_aldps(struct phy_device *phydev) 803 { 804 phy_modify_paged(phydev, 0x0a43, 0x10, BIT(2), 0); 805 } 806 807 static void rtl8168g_enable_gphy_10m(struct phy_device *phydev) 808 { 809 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 810 } 811 812 static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev) 813 { 814 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 815 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 816 r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000); 817 phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003); 818 } 819 820 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp, 821 struct phy_device *phydev) 822 { 823 int ret; 824 825 r8169_apply_firmware(tp); 826 827 ret = phy_read_paged(phydev, 0x0a46, 0x10); 828 if (ret & BIT(8)) 829 phy_modify_paged(phydev, 0x0bcc, 0x12, BIT(15), 0); 830 else 831 phy_modify_paged(phydev, 0x0bcc, 0x12, 0, BIT(15)); 832 833 ret = phy_read_paged(phydev, 0x0a46, 0x13); 834 if (ret & BIT(8)) 835 phy_modify_paged(phydev, 0x0c41, 0x15, 0, BIT(1)); 836 else 837 phy_modify_paged(phydev, 0x0c41, 0x15, BIT(1), 0); 838 839 /* Enable PHY auto speed down */ 840 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 841 842 rtl8168g_phy_adjust_10m_aldps(phydev); 843 844 /* EEE auto-fallback function */ 845 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 846 847 /* Enable UC LPF tune function */ 848 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 849 850 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 851 852 /* Improve SWR Efficiency */ 853 phy_write(phydev, 0x1f, 0x0bcd); 854 phy_write(phydev, 0x14, 0x5065); 855 phy_write(phydev, 0x14, 0xd065); 856 phy_write(phydev, 0x1f, 0x0bc8); 857 phy_write(phydev, 0x11, 0x5655); 858 phy_write(phydev, 0x1f, 0x0bcd); 859 phy_write(phydev, 0x14, 0x1065); 860 phy_write(phydev, 0x14, 0x9065); 861 phy_write(phydev, 0x14, 0x1065); 862 phy_write(phydev, 0x1f, 0x0000); 863 864 rtl8168g_disable_aldps(phydev); 865 rtl8168g_config_eee_phy(phydev); 866 } 867 868 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp, 869 struct phy_device *phydev) 870 { 871 r8169_apply_firmware(tp); 872 rtl8168g_config_eee_phy(phydev); 873 } 874 875 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp, 876 struct phy_device *phydev) 877 { 878 u16 dout_tapbin; 879 u32 data; 880 881 r8169_apply_firmware(tp); 882 883 /* CHN EST parameters adjust - giga master */ 884 r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000); 885 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000); 886 r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500); 887 r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00); 888 889 /* CHN EST parameters adjust - giga slave */ 890 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000); 891 r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000); 892 r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000); 893 894 /* CHN EST parameters adjust - fnet */ 895 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200); 896 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500); 897 r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00); 898 899 /* enable R-tune & PGA-retune function */ 900 dout_tapbin = 0; 901 data = phy_read_paged(phydev, 0x0a46, 0x13); 902 data &= 3; 903 data <<= 2; 904 dout_tapbin |= data; 905 data = phy_read_paged(phydev, 0x0a46, 0x12); 906 data &= 0xc000; 907 data >>= 14; 908 dout_tapbin |= data; 909 dout_tapbin = ~(dout_tapbin ^ 0x08); 910 dout_tapbin <<= 12; 911 dout_tapbin &= 0xf000; 912 913 r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin); 914 r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin); 915 r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin); 916 r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin); 917 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 918 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 919 920 rtl8168g_enable_gphy_10m(phydev); 921 922 /* SAR ADC performance */ 923 phy_modify_paged(phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 924 925 r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000); 926 r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000); 927 r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000); 928 r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000); 929 r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000); 930 r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000); 931 r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000); 932 933 /* disable phy pfm mode */ 934 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 935 936 rtl8168g_disable_aldps(phydev); 937 rtl8168h_config_eee_phy(phydev); 938 } 939 940 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp, 941 struct phy_device *phydev) 942 { 943 u16 ioffset, rlen; 944 u32 data; 945 946 r8169_apply_firmware(tp); 947 948 /* CHIN EST parameter update */ 949 r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a); 950 951 /* enable R-tune & PGA-retune function */ 952 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 953 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 954 955 rtl8168g_enable_gphy_10m(phydev); 956 957 ioffset = rtl8168h_2_get_adc_bias_ioffset(tp); 958 if (ioffset != 0xffff) 959 phy_write_paged(phydev, 0x0bcf, 0x16, ioffset); 960 961 /* Modify rlen (TX LPF corner frequency) level */ 962 data = phy_read_paged(phydev, 0x0bcd, 0x16); 963 data &= 0x000f; 964 rlen = 0; 965 if (data > 3) 966 rlen = data - 3; 967 data = rlen | (rlen << 4) | (rlen << 8) | (rlen << 12); 968 phy_write_paged(phydev, 0x0bcd, 0x17, data); 969 970 /* disable phy pfm mode */ 971 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 972 973 rtl8168g_disable_aldps(phydev); 974 rtl8168g_config_eee_phy(phydev); 975 } 976 977 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp, 978 struct phy_device *phydev) 979 { 980 /* Enable PHY auto speed down */ 981 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 982 983 rtl8168g_phy_adjust_10m_aldps(phydev); 984 985 /* Enable EEE auto-fallback function */ 986 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 987 988 /* Enable UC LPF tune function */ 989 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 990 991 /* set rg_sel_sdm_rate */ 992 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 993 994 rtl8168g_disable_aldps(phydev); 995 rtl8168g_config_eee_phy(phydev); 996 } 997 998 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp, 999 struct phy_device *phydev) 1000 { 1001 rtl8168g_phy_adjust_10m_aldps(phydev); 1002 1003 /* Enable UC LPF tune function */ 1004 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 1005 1006 /* Set rg_sel_sdm_rate */ 1007 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 1008 1009 /* Channel estimation parameters */ 1010 r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00); 1011 r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00); 1012 r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500); 1013 r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00); 1014 r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800); 1015 r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00); 1016 r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400); 1017 r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500); 1018 r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800); 1019 r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00); 1020 r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500); 1021 r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100); 1022 r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200); 1023 r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400); 1024 r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00); 1025 r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00); 1026 r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00); 1027 r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00); 1028 r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00); 1029 r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00); 1030 r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400); 1031 1032 /* Force PWM-mode */ 1033 phy_write(phydev, 0x1f, 0x0bcd); 1034 phy_write(phydev, 0x14, 0x5065); 1035 phy_write(phydev, 0x14, 0xd065); 1036 phy_write(phydev, 0x1f, 0x0bc8); 1037 phy_write(phydev, 0x12, 0x00ed); 1038 phy_write(phydev, 0x1f, 0x0bcd); 1039 phy_write(phydev, 0x14, 0x1065); 1040 phy_write(phydev, 0x14, 0x9065); 1041 phy_write(phydev, 0x14, 0x1065); 1042 phy_write(phydev, 0x1f, 0x0000); 1043 1044 rtl8168g_disable_aldps(phydev); 1045 rtl8168g_config_eee_phy(phydev); 1046 } 1047 1048 static void rtl8117_hw_phy_config(struct rtl8169_private *tp, 1049 struct phy_device *phydev) 1050 { 1051 /* CHN EST parameters adjust - fnet */ 1052 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800); 1053 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00); 1054 r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000); 1055 1056 r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000); 1057 r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00); 1058 r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600); 1059 r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000); 1060 r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800); 1061 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000); 1062 r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000); 1063 r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00); 1064 r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800); 1065 r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000); 1066 r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300); 1067 r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800); 1068 r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200); 1069 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800); 1070 r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800); 1071 r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00); 1072 r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300); 1073 r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300); 1074 1075 r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800); 1076 1077 rtl8168g_enable_gphy_10m(phydev); 1078 1079 r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400); 1080 1081 rtl8168g_disable_aldps(phydev); 1082 rtl8168h_config_eee_phy(phydev); 1083 } 1084 1085 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp, 1086 struct phy_device *phydev) 1087 { 1088 static const struct phy_reg phy_reg_init[] = { 1089 { 0x1f, 0x0003 }, 1090 { 0x08, 0x441d }, 1091 { 0x01, 0x9100 }, 1092 { 0x1f, 0x0000 } 1093 }; 1094 1095 phy_set_bits(phydev, 0x11, BIT(12)); 1096 phy_set_bits(phydev, 0x19, BIT(13)); 1097 phy_set_bits(phydev, 0x10, BIT(15)); 1098 1099 rtl_writephy_batch(phydev, phy_reg_init); 1100 } 1101 1102 static void rtl8401_hw_phy_config(struct rtl8169_private *tp, 1103 struct phy_device *phydev) 1104 { 1105 phy_set_bits(phydev, 0x11, BIT(12)); 1106 phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0003); 1107 } 1108 1109 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp, 1110 struct phy_device *phydev) 1111 { 1112 /* Disable ALDPS before ram code */ 1113 phy_write(phydev, 0x18, 0x0310); 1114 msleep(100); 1115 1116 r8169_apply_firmware(tp); 1117 1118 phy_write_paged(phydev, 0x0005, 0x1a, 0x0000); 1119 phy_write_paged(phydev, 0x0004, 0x1c, 0x0000); 1120 phy_write_paged(phydev, 0x0001, 0x15, 0x7701); 1121 } 1122 1123 static void rtl8402_hw_phy_config(struct rtl8169_private *tp, 1124 struct phy_device *phydev) 1125 { 1126 /* Disable ALDPS before setting firmware */ 1127 phy_write(phydev, 0x18, 0x0310); 1128 msleep(20); 1129 1130 r8169_apply_firmware(tp); 1131 1132 /* EEE setting */ 1133 phy_write(phydev, 0x1f, 0x0004); 1134 phy_write(phydev, 0x10, 0x401f); 1135 phy_write(phydev, 0x19, 0x7030); 1136 phy_write(phydev, 0x1f, 0x0000); 1137 } 1138 1139 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp, 1140 struct phy_device *phydev) 1141 { 1142 static const struct phy_reg phy_reg_init[] = { 1143 { 0x1f, 0x0004 }, 1144 { 0x10, 0xc07f }, 1145 { 0x19, 0x7030 }, 1146 { 0x1f, 0x0000 } 1147 }; 1148 1149 /* Disable ALDPS before ram code */ 1150 phy_write(phydev, 0x18, 0x0310); 1151 msleep(100); 1152 1153 r8169_apply_firmware(tp); 1154 1155 rtl_writephy_batch(phydev, phy_reg_init); 1156 } 1157 1158 static void rtl8125_legacy_force_mode(struct phy_device *phydev) 1159 { 1160 phy_modify_paged(phydev, 0xa5b, 0x12, BIT(15), 0); 1161 } 1162 1163 static void rtl8125a_1_hw_phy_config(struct rtl8169_private *tp, 1164 struct phy_device *phydev) 1165 { 1166 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084); 1167 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 1168 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006); 1169 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 1170 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100); 1171 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000); 1172 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400); 1173 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff); 1174 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff); 1175 1176 r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400); 1177 r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300); 1178 r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00); 1179 r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000); 1180 r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500); 1181 r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000); 1182 r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300); 1183 r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000); 1184 r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000); 1185 r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500); 1186 r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00); 1187 r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100); 1188 r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000); 1189 1190 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038); 1191 r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6); 1192 1193 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555); 1194 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00); 1195 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000); 1196 rtl8168g_enable_gphy_10m(phydev); 1197 1198 rtl8125a_config_eee_phy(phydev); 1199 } 1200 1201 static void rtl8125a_2_hw_phy_config(struct rtl8169_private *tp, 1202 struct phy_device *phydev) 1203 { 1204 int i; 1205 1206 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 1207 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 1208 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 1209 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 1210 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 1211 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 1212 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 1213 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 1214 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 1215 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 1216 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 1217 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 1218 1219 phy_write(phydev, 0x1f, 0x0b87); 1220 phy_write(phydev, 0x16, 0x80a2); 1221 phy_write(phydev, 0x17, 0x0153); 1222 phy_write(phydev, 0x16, 0x809c); 1223 phy_write(phydev, 0x17, 0x0153); 1224 phy_write(phydev, 0x1f, 0x0000); 1225 1226 phy_write(phydev, 0x1f, 0x0a43); 1227 phy_write(phydev, 0x13, 0x81B3); 1228 phy_write(phydev, 0x14, 0x0043); 1229 phy_write(phydev, 0x14, 0x00A7); 1230 phy_write(phydev, 0x14, 0x00D6); 1231 phy_write(phydev, 0x14, 0x00EC); 1232 phy_write(phydev, 0x14, 0x00F6); 1233 phy_write(phydev, 0x14, 0x00FB); 1234 phy_write(phydev, 0x14, 0x00FD); 1235 phy_write(phydev, 0x14, 0x00FF); 1236 phy_write(phydev, 0x14, 0x00BB); 1237 phy_write(phydev, 0x14, 0x0058); 1238 phy_write(phydev, 0x14, 0x0029); 1239 phy_write(phydev, 0x14, 0x0013); 1240 phy_write(phydev, 0x14, 0x0009); 1241 phy_write(phydev, 0x14, 0x0004); 1242 phy_write(phydev, 0x14, 0x0002); 1243 for (i = 0; i < 25; i++) 1244 phy_write(phydev, 0x14, 0x0000); 1245 phy_write(phydev, 0x1f, 0x0000); 1246 1247 r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F); 1248 r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843); 1249 1250 r8169_apply_firmware(tp); 1251 1252 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 1253 1254 r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100); 1255 1256 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 1257 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 1258 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 1259 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 1260 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 1261 rtl8168g_enable_gphy_10m(phydev); 1262 1263 rtl8125a_config_eee_phy(phydev); 1264 } 1265 1266 static void rtl8125b_hw_phy_config(struct rtl8169_private *tp, 1267 struct phy_device *phydev) 1268 { 1269 r8169_apply_firmware(tp); 1270 1271 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 1272 phy_modify_paged(phydev, 0xac4, 0x13, 0x00f0, 0x0090); 1273 phy_modify_paged(phydev, 0xad3, 0x10, 0x0003, 0x0001); 1274 1275 phy_write(phydev, 0x1f, 0x0b87); 1276 phy_write(phydev, 0x16, 0x80f5); 1277 phy_write(phydev, 0x17, 0x760e); 1278 phy_write(phydev, 0x16, 0x8107); 1279 phy_write(phydev, 0x17, 0x360e); 1280 phy_write(phydev, 0x16, 0x8551); 1281 phy_modify(phydev, 0x17, 0xff00, 0x0800); 1282 phy_write(phydev, 0x1f, 0x0000); 1283 1284 phy_modify_paged(phydev, 0xbf0, 0x10, 0xe000, 0xa000); 1285 phy_modify_paged(phydev, 0xbf4, 0x13, 0x0f00, 0x0300); 1286 1287 r8168g_phy_param(phydev, 0x8044, 0xffff, 0x2417); 1288 r8168g_phy_param(phydev, 0x804a, 0xffff, 0x2417); 1289 r8168g_phy_param(phydev, 0x8050, 0xffff, 0x2417); 1290 r8168g_phy_param(phydev, 0x8056, 0xffff, 0x2417); 1291 r8168g_phy_param(phydev, 0x805c, 0xffff, 0x2417); 1292 r8168g_phy_param(phydev, 0x8062, 0xffff, 0x2417); 1293 r8168g_phy_param(phydev, 0x8068, 0xffff, 0x2417); 1294 r8168g_phy_param(phydev, 0x806e, 0xffff, 0x2417); 1295 r8168g_phy_param(phydev, 0x8074, 0xffff, 0x2417); 1296 r8168g_phy_param(phydev, 0x807a, 0xffff, 0x2417); 1297 1298 phy_modify_paged(phydev, 0xa4c, 0x15, 0x0000, 0x0040); 1299 phy_modify_paged(phydev, 0xbf8, 0x12, 0xe000, 0xa000); 1300 1301 rtl8125_legacy_force_mode(phydev); 1302 rtl8125b_config_eee_phy(phydev); 1303 } 1304 1305 void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, 1306 enum mac_version ver) 1307 { 1308 static const rtl_phy_cfg_fct phy_configs[] = { 1309 /* PCI devices. */ 1310 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 1311 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 1312 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 1313 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 1314 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 1315 /* PCI-E devices. */ 1316 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 1317 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 1318 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 1319 [RTL_GIGA_MAC_VER_10] = NULL, 1320 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 1321 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 1322 [RTL_GIGA_MAC_VER_13] = NULL, 1323 [RTL_GIGA_MAC_VER_14] = rtl8401_hw_phy_config, 1324 [RTL_GIGA_MAC_VER_16] = NULL, 1325 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 1326 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 1327 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 1328 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 1329 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 1330 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config, 1331 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 1332 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 1333 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 1334 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 1335 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 1336 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 1337 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 1338 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 1339 [RTL_GIGA_MAC_VER_31] = NULL, 1340 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 1341 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 1342 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 1343 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 1344 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 1345 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 1346 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 1347 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 1348 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 1349 [RTL_GIGA_MAC_VER_41] = NULL, 1350 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 1351 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 1352 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 1353 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 1354 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 1355 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 1356 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 1357 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 1358 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 1359 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 1360 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, 1361 [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config, 1362 [RTL_GIGA_MAC_VER_60] = rtl8125a_1_hw_phy_config, 1363 [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config, 1364 [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config, 1365 }; 1366 1367 if (phy_configs[ver]) 1368 phy_configs[ver](tp, phydev); 1369 } 1370