1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 59 #define R8169_MSG_DEFAULT \ 60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 enum mac_version { 87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */ 88 RTL_GIGA_MAC_VER_02, 89 RTL_GIGA_MAC_VER_03, 90 RTL_GIGA_MAC_VER_04, 91 RTL_GIGA_MAC_VER_05, 92 RTL_GIGA_MAC_VER_06, 93 RTL_GIGA_MAC_VER_07, 94 RTL_GIGA_MAC_VER_08, 95 RTL_GIGA_MAC_VER_09, 96 RTL_GIGA_MAC_VER_10, 97 RTL_GIGA_MAC_VER_11, 98 RTL_GIGA_MAC_VER_12, 99 RTL_GIGA_MAC_VER_13, 100 RTL_GIGA_MAC_VER_14, 101 RTL_GIGA_MAC_VER_15, 102 RTL_GIGA_MAC_VER_16, 103 RTL_GIGA_MAC_VER_17, 104 RTL_GIGA_MAC_VER_18, 105 RTL_GIGA_MAC_VER_19, 106 RTL_GIGA_MAC_VER_20, 107 RTL_GIGA_MAC_VER_21, 108 RTL_GIGA_MAC_VER_22, 109 RTL_GIGA_MAC_VER_23, 110 RTL_GIGA_MAC_VER_24, 111 RTL_GIGA_MAC_VER_25, 112 RTL_GIGA_MAC_VER_26, 113 RTL_GIGA_MAC_VER_27, 114 RTL_GIGA_MAC_VER_28, 115 RTL_GIGA_MAC_VER_29, 116 RTL_GIGA_MAC_VER_30, 117 RTL_GIGA_MAC_VER_31, 118 RTL_GIGA_MAC_VER_32, 119 RTL_GIGA_MAC_VER_33, 120 RTL_GIGA_MAC_VER_34, 121 RTL_GIGA_MAC_VER_35, 122 RTL_GIGA_MAC_VER_36, 123 RTL_GIGA_MAC_VER_37, 124 RTL_GIGA_MAC_VER_38, 125 RTL_GIGA_MAC_VER_39, 126 RTL_GIGA_MAC_VER_40, 127 RTL_GIGA_MAC_VER_41, 128 RTL_GIGA_MAC_VER_42, 129 RTL_GIGA_MAC_VER_43, 130 RTL_GIGA_MAC_VER_44, 131 RTL_GIGA_MAC_VER_45, 132 RTL_GIGA_MAC_VER_46, 133 RTL_GIGA_MAC_VER_47, 134 RTL_GIGA_MAC_VER_48, 135 RTL_GIGA_MAC_VER_49, 136 RTL_GIGA_MAC_VER_50, 137 RTL_GIGA_MAC_VER_51, 138 RTL_GIGA_MAC_VER_60, 139 RTL_GIGA_MAC_VER_61, 140 RTL_GIGA_MAC_NONE 141 }; 142 143 #define JUMBO_1K ETH_DATA_LEN 144 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 145 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 146 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 147 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 148 149 static const struct { 150 const char *name; 151 const char *fw_name; 152 } rtl_chip_infos[] = { 153 /* PCI devices. */ 154 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 155 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 156 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 157 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 158 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 159 /* PCI-E devices. */ 160 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 161 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 162 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 163 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 164 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 165 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 166 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 167 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 168 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 169 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 170 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 171 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 172 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 173 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 174 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 175 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 176 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 177 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 178 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 179 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 180 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 181 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 182 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 183 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 184 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 185 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 186 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 187 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 188 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 189 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 190 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 191 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 192 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 193 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 194 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 195 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 196 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 197 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 198 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 199 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 200 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 201 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 202 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 203 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 204 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 205 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 206 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 207 }; 208 209 static const struct pci_device_id rtl8169_pci_tbl[] = { 210 { PCI_VDEVICE(REALTEK, 0x2502) }, 211 { PCI_VDEVICE(REALTEK, 0x2600) }, 212 { PCI_VDEVICE(REALTEK, 0x8129) }, 213 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 214 { PCI_VDEVICE(REALTEK, 0x8161) }, 215 { PCI_VDEVICE(REALTEK, 0x8167) }, 216 { PCI_VDEVICE(REALTEK, 0x8168) }, 217 { PCI_VDEVICE(NCUBE, 0x8168) }, 218 { PCI_VDEVICE(REALTEK, 0x8169) }, 219 { PCI_VENDOR_ID_DLINK, 0x4300, 220 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 221 { PCI_VDEVICE(DLINK, 0x4300) }, 222 { PCI_VDEVICE(DLINK, 0x4302) }, 223 { PCI_VDEVICE(AT, 0xc107) }, 224 { PCI_VDEVICE(USR, 0x0116) }, 225 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 226 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 227 { PCI_VDEVICE(REALTEK, 0x8125) }, 228 { PCI_VDEVICE(REALTEK, 0x3000) }, 229 {} 230 }; 231 232 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 233 234 static struct { 235 u32 msg_enable; 236 } debug = { -1 }; 237 238 enum rtl_registers { 239 MAC0 = 0, /* Ethernet hardware address. */ 240 MAC4 = 4, 241 MAR0 = 8, /* Multicast filter. */ 242 CounterAddrLow = 0x10, 243 CounterAddrHigh = 0x14, 244 TxDescStartAddrLow = 0x20, 245 TxDescStartAddrHigh = 0x24, 246 TxHDescStartAddrLow = 0x28, 247 TxHDescStartAddrHigh = 0x2c, 248 FLASH = 0x30, 249 ERSR = 0x36, 250 ChipCmd = 0x37, 251 TxPoll = 0x38, 252 IntrMask = 0x3c, 253 IntrStatus = 0x3e, 254 255 TxConfig = 0x40, 256 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 257 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 258 259 RxConfig = 0x44, 260 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 261 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 262 #define RXCFG_FIFO_SHIFT 13 263 /* No threshold before first PCI xfer */ 264 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 265 #define RX_EARLY_OFF (1 << 11) 266 #define RXCFG_DMA_SHIFT 8 267 /* Unlimited maximum PCI burst. */ 268 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 269 270 RxMissed = 0x4c, 271 Cfg9346 = 0x50, 272 Config0 = 0x51, 273 Config1 = 0x52, 274 Config2 = 0x53, 275 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 276 277 Config3 = 0x54, 278 Config4 = 0x55, 279 Config5 = 0x56, 280 PHYAR = 0x60, 281 PHYstatus = 0x6c, 282 RxMaxSize = 0xda, 283 CPlusCmd = 0xe0, 284 IntrMitigate = 0xe2, 285 286 #define RTL_COALESCE_MASK 0x0f 287 #define RTL_COALESCE_SHIFT 4 288 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 289 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 290 291 RxDescAddrLow = 0xe4, 292 RxDescAddrHigh = 0xe8, 293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 294 295 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 296 297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 298 299 #define TxPacketMax (8064 >> 7) 300 #define EarlySize 0x27 301 302 FuncEvent = 0xf0, 303 FuncEventMask = 0xf4, 304 FuncPresetState = 0xf8, 305 IBCR0 = 0xf8, 306 IBCR2 = 0xf9, 307 IBIMR0 = 0xfa, 308 IBISR0 = 0xfb, 309 FuncForceEvent = 0xfc, 310 }; 311 312 enum rtl8168_8101_registers { 313 CSIDR = 0x64, 314 CSIAR = 0x68, 315 #define CSIAR_FLAG 0x80000000 316 #define CSIAR_WRITE_CMD 0x80000000 317 #define CSIAR_BYTE_ENABLE 0x0000f000 318 #define CSIAR_ADDR_MASK 0x00000fff 319 PMCH = 0x6f, 320 EPHYAR = 0x80, 321 #define EPHYAR_FLAG 0x80000000 322 #define EPHYAR_WRITE_CMD 0x80000000 323 #define EPHYAR_REG_MASK 0x1f 324 #define EPHYAR_REG_SHIFT 16 325 #define EPHYAR_DATA_MASK 0xffff 326 DLLPR = 0xd0, 327 #define PFM_EN (1 << 6) 328 #define TX_10M_PS_EN (1 << 7) 329 DBG_REG = 0xd1, 330 #define FIX_NAK_1 (1 << 4) 331 #define FIX_NAK_2 (1 << 3) 332 TWSI = 0xd2, 333 MCU = 0xd3, 334 #define NOW_IS_OOB (1 << 7) 335 #define TX_EMPTY (1 << 5) 336 #define RX_EMPTY (1 << 4) 337 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 338 #define EN_NDP (1 << 3) 339 #define EN_OOB_RESET (1 << 2) 340 #define LINK_LIST_RDY (1 << 1) 341 EFUSEAR = 0xdc, 342 #define EFUSEAR_FLAG 0x80000000 343 #define EFUSEAR_WRITE_CMD 0x80000000 344 #define EFUSEAR_READ_CMD 0x00000000 345 #define EFUSEAR_REG_MASK 0x03ff 346 #define EFUSEAR_REG_SHIFT 8 347 #define EFUSEAR_DATA_MASK 0xff 348 MISC_1 = 0xf2, 349 #define PFM_D3COLD_EN (1 << 6) 350 }; 351 352 enum rtl8168_registers { 353 LED_FREQ = 0x1a, 354 EEE_LED = 0x1b, 355 ERIDR = 0x70, 356 ERIAR = 0x74, 357 #define ERIAR_FLAG 0x80000000 358 #define ERIAR_WRITE_CMD 0x80000000 359 #define ERIAR_READ_CMD 0x00000000 360 #define ERIAR_ADDR_BYTE_ALIGN 4 361 #define ERIAR_TYPE_SHIFT 16 362 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 363 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 364 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 365 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 366 #define ERIAR_MASK_SHIFT 12 367 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 368 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 369 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 370 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 371 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 372 EPHY_RXER_NUM = 0x7c, 373 OCPDR = 0xb0, /* OCP GPHY access */ 374 #define OCPDR_WRITE_CMD 0x80000000 375 #define OCPDR_READ_CMD 0x00000000 376 #define OCPDR_REG_MASK 0x7f 377 #define OCPDR_GPHY_REG_SHIFT 16 378 #define OCPDR_DATA_MASK 0xffff 379 OCPAR = 0xb4, 380 #define OCPAR_FLAG 0x80000000 381 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 382 #define OCPAR_GPHY_READ_CMD 0x0000f060 383 GPHY_OCP = 0xb8, 384 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 385 MISC = 0xf0, /* 8168e only. */ 386 #define TXPLA_RST (1 << 29) 387 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 388 #define PWM_EN (1 << 22) 389 #define RXDV_GATED_EN (1 << 19) 390 #define EARLY_TALLY_EN (1 << 16) 391 }; 392 393 enum rtl8125_registers { 394 IntrMask_8125 = 0x38, 395 IntrStatus_8125 = 0x3c, 396 TxPoll_8125 = 0x90, 397 MAC0_BKP = 0x19e0, 398 }; 399 400 #define RX_VLAN_INNER_8125 BIT(22) 401 #define RX_VLAN_OUTER_8125 BIT(23) 402 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 403 404 #define RX_FETCH_DFLT_8125 (8 << 27) 405 406 enum rtl_register_content { 407 /* InterruptStatusBits */ 408 SYSErr = 0x8000, 409 PCSTimeout = 0x4000, 410 SWInt = 0x0100, 411 TxDescUnavail = 0x0080, 412 RxFIFOOver = 0x0040, 413 LinkChg = 0x0020, 414 RxOverflow = 0x0010, 415 TxErr = 0x0008, 416 TxOK = 0x0004, 417 RxErr = 0x0002, 418 RxOK = 0x0001, 419 420 /* RxStatusDesc */ 421 RxRWT = (1 << 22), 422 RxRES = (1 << 21), 423 RxRUNT = (1 << 20), 424 RxCRC = (1 << 19), 425 426 /* ChipCmdBits */ 427 StopReq = 0x80, 428 CmdReset = 0x10, 429 CmdRxEnb = 0x08, 430 CmdTxEnb = 0x04, 431 RxBufEmpty = 0x01, 432 433 /* TXPoll register p.5 */ 434 HPQ = 0x80, /* Poll cmd on the high prio queue */ 435 NPQ = 0x40, /* Poll cmd on the low prio queue */ 436 FSWInt = 0x01, /* Forced software interrupt */ 437 438 /* Cfg9346Bits */ 439 Cfg9346_Lock = 0x00, 440 Cfg9346_Unlock = 0xc0, 441 442 /* rx_mode_bits */ 443 AcceptErr = 0x20, 444 AcceptRunt = 0x10, 445 AcceptBroadcast = 0x08, 446 AcceptMulticast = 0x04, 447 AcceptMyPhys = 0x02, 448 AcceptAllPhys = 0x01, 449 #define RX_CONFIG_ACCEPT_MASK 0x3f 450 451 /* TxConfigBits */ 452 TxInterFrameGapShift = 24, 453 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 454 455 /* Config1 register p.24 */ 456 LEDS1 = (1 << 7), 457 LEDS0 = (1 << 6), 458 Speed_down = (1 << 4), 459 MEMMAP = (1 << 3), 460 IOMAP = (1 << 2), 461 VPD = (1 << 1), 462 PMEnable = (1 << 0), /* Power Management Enable */ 463 464 /* Config2 register p. 25 */ 465 ClkReqEn = (1 << 7), /* Clock Request Enable */ 466 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 467 PCI_Clock_66MHz = 0x01, 468 PCI_Clock_33MHz = 0x00, 469 470 /* Config3 register p.25 */ 471 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 472 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 473 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 474 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 475 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 476 477 /* Config4 register */ 478 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 479 480 /* Config5 register p.27 */ 481 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 482 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 483 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 484 Spi_en = (1 << 3), 485 LanWake = (1 << 1), /* LanWake enable/disable */ 486 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 487 ASPM_en = (1 << 0), /* ASPM enable */ 488 489 /* CPlusCmd p.31 */ 490 EnableBist = (1 << 15), // 8168 8101 491 Mac_dbgo_oe = (1 << 14), // 8168 8101 492 Normal_mode = (1 << 13), // unused 493 Force_half_dup = (1 << 12), // 8168 8101 494 Force_rxflow_en = (1 << 11), // 8168 8101 495 Force_txflow_en = (1 << 10), // 8168 8101 496 Cxpl_dbg_sel = (1 << 9), // 8168 8101 497 ASF = (1 << 8), // 8168 8101 498 PktCntrDisable = (1 << 7), // 8168 8101 499 Mac_dbgo_sel = 0x001c, // 8168 500 RxVlan = (1 << 6), 501 RxChkSum = (1 << 5), 502 PCIDAC = (1 << 4), 503 PCIMulRW = (1 << 3), 504 #define INTT_MASK GENMASK(1, 0) 505 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 506 507 /* rtl8169_PHYstatus */ 508 TBI_Enable = 0x80, 509 TxFlowCtrl = 0x40, 510 RxFlowCtrl = 0x20, 511 _1000bpsF = 0x10, 512 _100bps = 0x08, 513 _10bps = 0x04, 514 LinkStatus = 0x02, 515 FullDup = 0x01, 516 517 /* ResetCounterCommand */ 518 CounterReset = 0x1, 519 520 /* DumpCounterCommand */ 521 CounterDump = 0x8, 522 523 /* magic enable v2 */ 524 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 525 }; 526 527 enum rtl_desc_bit { 528 /* First doubleword. */ 529 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 530 RingEnd = (1 << 30), /* End of descriptor ring */ 531 FirstFrag = (1 << 29), /* First segment of a packet */ 532 LastFrag = (1 << 28), /* Final segment of a packet */ 533 }; 534 535 /* Generic case. */ 536 enum rtl_tx_desc_bit { 537 /* First doubleword. */ 538 TD_LSO = (1 << 27), /* Large Send Offload */ 539 #define TD_MSS_MAX 0x07ffu /* MSS value */ 540 541 /* Second doubleword. */ 542 TxVlanTag = (1 << 17), /* Add VLAN tag */ 543 }; 544 545 /* 8169, 8168b and 810x except 8102e. */ 546 enum rtl_tx_desc_bit_0 { 547 /* First doubleword. */ 548 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 549 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 550 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 551 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 552 }; 553 554 /* 8102e, 8168c and beyond. */ 555 enum rtl_tx_desc_bit_1 { 556 /* First doubleword. */ 557 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 558 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 559 #define GTTCPHO_SHIFT 18 560 #define GTTCPHO_MAX 0x7f 561 562 /* Second doubleword. */ 563 #define TCPHO_SHIFT 18 564 #define TCPHO_MAX 0x3ff 565 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 566 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 567 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 568 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 569 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 570 }; 571 572 enum rtl_rx_desc_bit { 573 /* Rx private */ 574 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 575 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 576 577 #define RxProtoUDP (PID1) 578 #define RxProtoTCP (PID0) 579 #define RxProtoIP (PID1 | PID0) 580 #define RxProtoMask RxProtoIP 581 582 IPFail = (1 << 16), /* IP checksum failed */ 583 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 584 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 585 RxVlanTag = (1 << 16), /* VLAN tag available */ 586 }; 587 588 #define RsvdMask 0x3fffc000 589 590 #define RTL_GSO_MAX_SIZE_V1 32000 591 #define RTL_GSO_MAX_SEGS_V1 24 592 #define RTL_GSO_MAX_SIZE_V2 64000 593 #define RTL_GSO_MAX_SEGS_V2 64 594 595 struct TxDesc { 596 __le32 opts1; 597 __le32 opts2; 598 __le64 addr; 599 }; 600 601 struct RxDesc { 602 __le32 opts1; 603 __le32 opts2; 604 __le64 addr; 605 }; 606 607 struct ring_info { 608 struct sk_buff *skb; 609 u32 len; 610 }; 611 612 struct rtl8169_counters { 613 __le64 tx_packets; 614 __le64 rx_packets; 615 __le64 tx_errors; 616 __le32 rx_errors; 617 __le16 rx_missed; 618 __le16 align_errors; 619 __le32 tx_one_collision; 620 __le32 tx_multi_collision; 621 __le64 rx_unicast; 622 __le64 rx_broadcast; 623 __le32 rx_multicast; 624 __le16 tx_aborted; 625 __le16 tx_underun; 626 }; 627 628 struct rtl8169_tc_offsets { 629 bool inited; 630 __le64 tx_errors; 631 __le32 tx_multi_collision; 632 __le16 tx_aborted; 633 }; 634 635 enum rtl_flag { 636 RTL_FLAG_TASK_ENABLED = 0, 637 RTL_FLAG_TASK_RESET_PENDING, 638 RTL_FLAG_MAX 639 }; 640 641 struct rtl8169_stats { 642 u64 packets; 643 u64 bytes; 644 struct u64_stats_sync syncp; 645 }; 646 647 struct rtl8169_private { 648 void __iomem *mmio_addr; /* memory map physical address */ 649 struct pci_dev *pci_dev; 650 struct net_device *dev; 651 struct phy_device *phydev; 652 struct napi_struct napi; 653 u32 msg_enable; 654 enum mac_version mac_version; 655 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 656 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 657 u32 dirty_tx; 658 struct rtl8169_stats rx_stats; 659 struct rtl8169_stats tx_stats; 660 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 661 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 662 dma_addr_t TxPhyAddr; 663 dma_addr_t RxPhyAddr; 664 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 665 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 666 u16 cp_cmd; 667 u32 irq_mask; 668 struct clk *clk; 669 670 struct { 671 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 672 struct mutex mutex; 673 struct work_struct work; 674 } wk; 675 676 unsigned irq_enabled:1; 677 unsigned supports_gmii:1; 678 unsigned aspm_manageable:1; 679 dma_addr_t counters_phys_addr; 680 struct rtl8169_counters *counters; 681 struct rtl8169_tc_offsets tc_offset; 682 u32 saved_wolopts; 683 684 const char *fw_name; 685 struct rtl_fw *rtl_fw; 686 687 u32 ocp_base; 688 }; 689 690 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 691 692 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 693 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 694 module_param_named(debug, debug.msg_enable, int, 0); 695 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 696 MODULE_SOFTDEP("pre: realtek"); 697 MODULE_LICENSE("GPL"); 698 MODULE_FIRMWARE(FIRMWARE_8168D_1); 699 MODULE_FIRMWARE(FIRMWARE_8168D_2); 700 MODULE_FIRMWARE(FIRMWARE_8168E_1); 701 MODULE_FIRMWARE(FIRMWARE_8168E_2); 702 MODULE_FIRMWARE(FIRMWARE_8168E_3); 703 MODULE_FIRMWARE(FIRMWARE_8105E_1); 704 MODULE_FIRMWARE(FIRMWARE_8168F_1); 705 MODULE_FIRMWARE(FIRMWARE_8168F_2); 706 MODULE_FIRMWARE(FIRMWARE_8402_1); 707 MODULE_FIRMWARE(FIRMWARE_8411_1); 708 MODULE_FIRMWARE(FIRMWARE_8411_2); 709 MODULE_FIRMWARE(FIRMWARE_8106E_1); 710 MODULE_FIRMWARE(FIRMWARE_8106E_2); 711 MODULE_FIRMWARE(FIRMWARE_8168G_2); 712 MODULE_FIRMWARE(FIRMWARE_8168G_3); 713 MODULE_FIRMWARE(FIRMWARE_8168H_1); 714 MODULE_FIRMWARE(FIRMWARE_8168H_2); 715 MODULE_FIRMWARE(FIRMWARE_8107E_1); 716 MODULE_FIRMWARE(FIRMWARE_8107E_2); 717 MODULE_FIRMWARE(FIRMWARE_8125A_3); 718 719 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 720 { 721 return &tp->pci_dev->dev; 722 } 723 724 static void rtl_lock_work(struct rtl8169_private *tp) 725 { 726 mutex_lock(&tp->wk.mutex); 727 } 728 729 static void rtl_unlock_work(struct rtl8169_private *tp) 730 { 731 mutex_unlock(&tp->wk.mutex); 732 } 733 734 static void rtl_lock_config_regs(struct rtl8169_private *tp) 735 { 736 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 737 } 738 739 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 740 { 741 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 742 } 743 744 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force) 745 { 746 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL, 747 PCI_EXP_DEVCTL_READRQ, force); 748 } 749 750 static bool rtl_is_8125(struct rtl8169_private *tp) 751 { 752 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 753 } 754 755 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 756 { 757 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 758 tp->mac_version != RTL_GIGA_MAC_VER_39 && 759 tp->mac_version <= RTL_GIGA_MAC_VER_51; 760 } 761 762 static bool rtl_supports_eee(struct rtl8169_private *tp) 763 { 764 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 765 tp->mac_version != RTL_GIGA_MAC_VER_37 && 766 tp->mac_version != RTL_GIGA_MAC_VER_39; 767 } 768 769 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 770 { 771 int i; 772 773 for (i = 0; i < ETH_ALEN; i++) 774 mac[i] = RTL_R8(tp, reg + i); 775 } 776 777 struct rtl_cond { 778 bool (*check)(struct rtl8169_private *); 779 const char *msg; 780 }; 781 782 static void rtl_udelay(unsigned int d) 783 { 784 udelay(d); 785 } 786 787 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 788 void (*delay)(unsigned int), unsigned int d, int n, 789 bool high) 790 { 791 int i; 792 793 for (i = 0; i < n; i++) { 794 if (c->check(tp) == high) 795 return true; 796 delay(d); 797 } 798 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 799 c->msg, !high, n, d); 800 return false; 801 } 802 803 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 804 const struct rtl_cond *c, 805 unsigned int d, int n) 806 { 807 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 808 } 809 810 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 811 const struct rtl_cond *c, 812 unsigned int d, int n) 813 { 814 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 815 } 816 817 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 818 const struct rtl_cond *c, 819 unsigned int d, int n) 820 { 821 return rtl_loop_wait(tp, c, msleep, d, n, true); 822 } 823 824 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 825 const struct rtl_cond *c, 826 unsigned int d, int n) 827 { 828 return rtl_loop_wait(tp, c, msleep, d, n, false); 829 } 830 831 #define DECLARE_RTL_COND(name) \ 832 static bool name ## _check(struct rtl8169_private *); \ 833 \ 834 static const struct rtl_cond name = { \ 835 .check = name ## _check, \ 836 .msg = #name \ 837 }; \ 838 \ 839 static bool name ## _check(struct rtl8169_private *tp) 840 841 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 842 { 843 if (reg & 0xffff0001) { 844 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 845 return true; 846 } 847 return false; 848 } 849 850 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 851 { 852 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 853 } 854 855 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 856 { 857 if (rtl_ocp_reg_failure(tp, reg)) 858 return; 859 860 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 861 862 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 863 } 864 865 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 866 { 867 if (rtl_ocp_reg_failure(tp, reg)) 868 return 0; 869 870 RTL_W32(tp, GPHY_OCP, reg << 15); 871 872 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 873 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 874 } 875 876 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 877 { 878 if (rtl_ocp_reg_failure(tp, reg)) 879 return; 880 881 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 882 } 883 884 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 885 { 886 if (rtl_ocp_reg_failure(tp, reg)) 887 return 0; 888 889 RTL_W32(tp, OCPDR, reg << 15); 890 891 return RTL_R32(tp, OCPDR); 892 } 893 894 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 895 u16 set) 896 { 897 u16 data = r8168_mac_ocp_read(tp, reg); 898 899 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 900 } 901 902 #define OCP_STD_PHY_BASE 0xa400 903 904 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 905 { 906 if (reg == 0x1f) { 907 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 908 return; 909 } 910 911 if (tp->ocp_base != OCP_STD_PHY_BASE) 912 reg -= 0x10; 913 914 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 915 } 916 917 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 918 { 919 if (tp->ocp_base != OCP_STD_PHY_BASE) 920 reg -= 0x10; 921 922 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 923 } 924 925 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 926 { 927 if (reg == 0x1f) { 928 tp->ocp_base = value << 4; 929 return; 930 } 931 932 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 933 } 934 935 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 936 { 937 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 938 } 939 940 DECLARE_RTL_COND(rtl_phyar_cond) 941 { 942 return RTL_R32(tp, PHYAR) & 0x80000000; 943 } 944 945 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 946 { 947 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 948 949 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 950 /* 951 * According to hardware specs a 20us delay is required after write 952 * complete indication, but before sending next command. 953 */ 954 udelay(20); 955 } 956 957 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 958 { 959 int value; 960 961 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 962 963 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 964 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 965 966 /* 967 * According to hardware specs a 20us delay is required after read 968 * complete indication, but before sending next command. 969 */ 970 udelay(20); 971 972 return value; 973 } 974 975 DECLARE_RTL_COND(rtl_ocpar_cond) 976 { 977 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 978 } 979 980 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 981 { 982 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 983 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 984 RTL_W32(tp, EPHY_RXER_NUM, 0); 985 986 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 987 } 988 989 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 990 { 991 r8168dp_1_mdio_access(tp, reg, 992 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 993 } 994 995 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 996 { 997 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 998 999 mdelay(1); 1000 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1001 RTL_W32(tp, EPHY_RXER_NUM, 0); 1002 1003 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1004 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1005 } 1006 1007 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1008 1009 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1010 { 1011 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1012 } 1013 1014 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1015 { 1016 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1017 } 1018 1019 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1020 { 1021 r8168dp_2_mdio_start(tp); 1022 1023 r8169_mdio_write(tp, reg, value); 1024 1025 r8168dp_2_mdio_stop(tp); 1026 } 1027 1028 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1029 { 1030 int value; 1031 1032 /* Work around issue with chip reporting wrong PHY ID */ 1033 if (reg == MII_PHYSID2) 1034 return 0xc912; 1035 1036 r8168dp_2_mdio_start(tp); 1037 1038 value = r8169_mdio_read(tp, reg); 1039 1040 r8168dp_2_mdio_stop(tp); 1041 1042 return value; 1043 } 1044 1045 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1046 { 1047 switch (tp->mac_version) { 1048 case RTL_GIGA_MAC_VER_27: 1049 r8168dp_1_mdio_write(tp, location, val); 1050 break; 1051 case RTL_GIGA_MAC_VER_28: 1052 case RTL_GIGA_MAC_VER_31: 1053 r8168dp_2_mdio_write(tp, location, val); 1054 break; 1055 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1056 r8168g_mdio_write(tp, location, val); 1057 break; 1058 default: 1059 r8169_mdio_write(tp, location, val); 1060 break; 1061 } 1062 } 1063 1064 static int rtl_readphy(struct rtl8169_private *tp, int location) 1065 { 1066 switch (tp->mac_version) { 1067 case RTL_GIGA_MAC_VER_27: 1068 return r8168dp_1_mdio_read(tp, location); 1069 case RTL_GIGA_MAC_VER_28: 1070 case RTL_GIGA_MAC_VER_31: 1071 return r8168dp_2_mdio_read(tp, location); 1072 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1073 return r8168g_mdio_read(tp, location); 1074 default: 1075 return r8169_mdio_read(tp, location); 1076 } 1077 } 1078 1079 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) 1080 { 1081 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); 1082 } 1083 1084 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) 1085 { 1086 int val; 1087 1088 val = rtl_readphy(tp, reg_addr); 1089 rtl_writephy(tp, reg_addr, (val & ~m) | p); 1090 } 1091 1092 DECLARE_RTL_COND(rtl_ephyar_cond) 1093 { 1094 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1095 } 1096 1097 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1098 { 1099 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1100 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1101 1102 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1103 1104 udelay(10); 1105 } 1106 1107 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1108 { 1109 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1110 1111 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1112 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1113 } 1114 1115 DECLARE_RTL_COND(rtl_eriar_cond) 1116 { 1117 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1118 } 1119 1120 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1121 u32 val, int type) 1122 { 1123 BUG_ON((addr & 3) || (mask == 0)); 1124 RTL_W32(tp, ERIDR, val); 1125 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1126 1127 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1128 } 1129 1130 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1131 u32 val) 1132 { 1133 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1134 } 1135 1136 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1137 { 1138 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1139 1140 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1141 RTL_R32(tp, ERIDR) : ~0; 1142 } 1143 1144 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1145 { 1146 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1147 } 1148 1149 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1150 u32 m) 1151 { 1152 u32 val; 1153 1154 val = rtl_eri_read(tp, addr); 1155 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1156 } 1157 1158 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1159 u32 p) 1160 { 1161 rtl_w0w1_eri(tp, addr, mask, p, 0); 1162 } 1163 1164 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1165 u32 m) 1166 { 1167 rtl_w0w1_eri(tp, addr, mask, 0, m); 1168 } 1169 1170 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1171 { 1172 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1173 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1174 RTL_R32(tp, OCPDR) : ~0; 1175 } 1176 1177 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1178 { 1179 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1180 } 1181 1182 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1183 u32 data) 1184 { 1185 RTL_W32(tp, OCPDR, data); 1186 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1187 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1188 } 1189 1190 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1191 u32 data) 1192 { 1193 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1194 data, ERIAR_OOB); 1195 } 1196 1197 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1198 { 1199 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1200 1201 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1202 } 1203 1204 #define OOB_CMD_RESET 0x00 1205 #define OOB_CMD_DRIVER_START 0x05 1206 #define OOB_CMD_DRIVER_STOP 0x06 1207 1208 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1209 { 1210 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1211 } 1212 1213 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1214 { 1215 u16 reg; 1216 1217 reg = rtl8168_get_ocp_reg(tp); 1218 1219 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1220 } 1221 1222 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1223 { 1224 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1225 } 1226 1227 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1228 { 1229 return RTL_R8(tp, IBISR0) & 0x20; 1230 } 1231 1232 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1233 { 1234 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1235 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1236 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1237 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1238 } 1239 1240 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1241 { 1242 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1243 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1244 } 1245 1246 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1247 { 1248 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1249 r8168ep_ocp_write(tp, 0x01, 0x30, 1250 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1251 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1252 } 1253 1254 static void rtl8168_driver_start(struct rtl8169_private *tp) 1255 { 1256 switch (tp->mac_version) { 1257 case RTL_GIGA_MAC_VER_27: 1258 case RTL_GIGA_MAC_VER_28: 1259 case RTL_GIGA_MAC_VER_31: 1260 rtl8168dp_driver_start(tp); 1261 break; 1262 case RTL_GIGA_MAC_VER_49: 1263 case RTL_GIGA_MAC_VER_50: 1264 case RTL_GIGA_MAC_VER_51: 1265 rtl8168ep_driver_start(tp); 1266 break; 1267 default: 1268 BUG(); 1269 break; 1270 } 1271 } 1272 1273 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1274 { 1275 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1276 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1277 } 1278 1279 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1280 { 1281 rtl8168ep_stop_cmac(tp); 1282 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1283 r8168ep_ocp_write(tp, 0x01, 0x30, 1284 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1285 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1286 } 1287 1288 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1289 { 1290 switch (tp->mac_version) { 1291 case RTL_GIGA_MAC_VER_27: 1292 case RTL_GIGA_MAC_VER_28: 1293 case RTL_GIGA_MAC_VER_31: 1294 rtl8168dp_driver_stop(tp); 1295 break; 1296 case RTL_GIGA_MAC_VER_49: 1297 case RTL_GIGA_MAC_VER_50: 1298 case RTL_GIGA_MAC_VER_51: 1299 rtl8168ep_driver_stop(tp); 1300 break; 1301 default: 1302 BUG(); 1303 break; 1304 } 1305 } 1306 1307 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1308 { 1309 u16 reg = rtl8168_get_ocp_reg(tp); 1310 1311 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1312 } 1313 1314 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1315 { 1316 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1317 } 1318 1319 static bool r8168_check_dash(struct rtl8169_private *tp) 1320 { 1321 switch (tp->mac_version) { 1322 case RTL_GIGA_MAC_VER_27: 1323 case RTL_GIGA_MAC_VER_28: 1324 case RTL_GIGA_MAC_VER_31: 1325 return r8168dp_check_dash(tp); 1326 case RTL_GIGA_MAC_VER_49: 1327 case RTL_GIGA_MAC_VER_50: 1328 case RTL_GIGA_MAC_VER_51: 1329 return r8168ep_check_dash(tp); 1330 default: 1331 return false; 1332 } 1333 } 1334 1335 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1336 { 1337 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1338 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1339 } 1340 1341 DECLARE_RTL_COND(rtl_efusear_cond) 1342 { 1343 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1344 } 1345 1346 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1347 { 1348 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1349 1350 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1351 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1352 } 1353 1354 static u32 rtl_get_events(struct rtl8169_private *tp) 1355 { 1356 if (rtl_is_8125(tp)) 1357 return RTL_R32(tp, IntrStatus_8125); 1358 else 1359 return RTL_R16(tp, IntrStatus); 1360 } 1361 1362 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1363 { 1364 if (rtl_is_8125(tp)) 1365 RTL_W32(tp, IntrStatus_8125, bits); 1366 else 1367 RTL_W16(tp, IntrStatus, bits); 1368 } 1369 1370 static void rtl_irq_disable(struct rtl8169_private *tp) 1371 { 1372 if (rtl_is_8125(tp)) 1373 RTL_W32(tp, IntrMask_8125, 0); 1374 else 1375 RTL_W16(tp, IntrMask, 0); 1376 tp->irq_enabled = 0; 1377 } 1378 1379 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) 1380 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) 1381 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) 1382 1383 static void rtl_irq_enable(struct rtl8169_private *tp) 1384 { 1385 tp->irq_enabled = 1; 1386 if (rtl_is_8125(tp)) 1387 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1388 else 1389 RTL_W16(tp, IntrMask, tp->irq_mask); 1390 } 1391 1392 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1393 { 1394 rtl_irq_disable(tp); 1395 rtl_ack_events(tp, 0xffffffff); 1396 /* PCI commit */ 1397 RTL_R8(tp, ChipCmd); 1398 } 1399 1400 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1401 { 1402 struct net_device *dev = tp->dev; 1403 struct phy_device *phydev = tp->phydev; 1404 1405 if (!netif_running(dev)) 1406 return; 1407 1408 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1409 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1410 if (phydev->speed == SPEED_1000) { 1411 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1412 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1413 } else if (phydev->speed == SPEED_100) { 1414 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1415 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1416 } else { 1417 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1418 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1419 } 1420 rtl_reset_packet_filter(tp); 1421 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1422 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1423 if (phydev->speed == SPEED_1000) { 1424 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1425 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1426 } else { 1427 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1428 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1429 } 1430 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1431 if (phydev->speed == SPEED_10) { 1432 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1433 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1434 } else { 1435 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1436 } 1437 } 1438 } 1439 1440 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1441 1442 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1443 { 1444 struct rtl8169_private *tp = netdev_priv(dev); 1445 1446 rtl_lock_work(tp); 1447 wol->supported = WAKE_ANY; 1448 wol->wolopts = tp->saved_wolopts; 1449 rtl_unlock_work(tp); 1450 } 1451 1452 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1453 { 1454 static const struct { 1455 u32 opt; 1456 u16 reg; 1457 u8 mask; 1458 } cfg[] = { 1459 { WAKE_PHY, Config3, LinkUp }, 1460 { WAKE_UCAST, Config5, UWF }, 1461 { WAKE_BCAST, Config5, BWF }, 1462 { WAKE_MCAST, Config5, MWF }, 1463 { WAKE_ANY, Config5, LanWake }, 1464 { WAKE_MAGIC, Config3, MagicPacket } 1465 }; 1466 unsigned int i, tmp = ARRAY_SIZE(cfg); 1467 u8 options; 1468 1469 rtl_unlock_config_regs(tp); 1470 1471 if (rtl_is_8168evl_up(tp)) { 1472 tmp--; 1473 if (wolopts & WAKE_MAGIC) 1474 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1475 MagicPacket_v2); 1476 else 1477 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1478 MagicPacket_v2); 1479 } else if (rtl_is_8125(tp)) { 1480 tmp--; 1481 if (wolopts & WAKE_MAGIC) 1482 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1483 else 1484 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1485 } 1486 1487 for (i = 0; i < tmp; i++) { 1488 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1489 if (wolopts & cfg[i].opt) 1490 options |= cfg[i].mask; 1491 RTL_W8(tp, cfg[i].reg, options); 1492 } 1493 1494 switch (tp->mac_version) { 1495 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1496 options = RTL_R8(tp, Config1) & ~PMEnable; 1497 if (wolopts) 1498 options |= PMEnable; 1499 RTL_W8(tp, Config1, options); 1500 break; 1501 case RTL_GIGA_MAC_VER_34: 1502 case RTL_GIGA_MAC_VER_37: 1503 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51: 1504 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1505 if (wolopts) 1506 options |= PME_SIGNAL; 1507 RTL_W8(tp, Config2, options); 1508 break; 1509 default: 1510 break; 1511 } 1512 1513 rtl_lock_config_regs(tp); 1514 1515 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1516 } 1517 1518 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1519 { 1520 struct rtl8169_private *tp = netdev_priv(dev); 1521 struct device *d = tp_to_dev(tp); 1522 1523 if (wol->wolopts & ~WAKE_ANY) 1524 return -EINVAL; 1525 1526 pm_runtime_get_noresume(d); 1527 1528 rtl_lock_work(tp); 1529 1530 tp->saved_wolopts = wol->wolopts; 1531 1532 if (pm_runtime_active(d)) 1533 __rtl8169_set_wol(tp, tp->saved_wolopts); 1534 1535 rtl_unlock_work(tp); 1536 1537 pm_runtime_put_noidle(d); 1538 1539 return 0; 1540 } 1541 1542 static void rtl8169_get_drvinfo(struct net_device *dev, 1543 struct ethtool_drvinfo *info) 1544 { 1545 struct rtl8169_private *tp = netdev_priv(dev); 1546 struct rtl_fw *rtl_fw = tp->rtl_fw; 1547 1548 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1549 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1550 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1551 if (rtl_fw) 1552 strlcpy(info->fw_version, rtl_fw->version, 1553 sizeof(info->fw_version)); 1554 } 1555 1556 static int rtl8169_get_regs_len(struct net_device *dev) 1557 { 1558 return R8169_REGS_SIZE; 1559 } 1560 1561 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1562 netdev_features_t features) 1563 { 1564 struct rtl8169_private *tp = netdev_priv(dev); 1565 1566 if (dev->mtu > TD_MSS_MAX) 1567 features &= ~NETIF_F_ALL_TSO; 1568 1569 if (dev->mtu > JUMBO_1K && 1570 tp->mac_version > RTL_GIGA_MAC_VER_06) 1571 features &= ~NETIF_F_IP_CSUM; 1572 1573 return features; 1574 } 1575 1576 static int rtl8169_set_features(struct net_device *dev, 1577 netdev_features_t features) 1578 { 1579 struct rtl8169_private *tp = netdev_priv(dev); 1580 u32 rx_config; 1581 1582 rtl_lock_work(tp); 1583 1584 rx_config = RTL_R32(tp, RxConfig); 1585 if (features & NETIF_F_RXALL) 1586 rx_config |= (AcceptErr | AcceptRunt); 1587 else 1588 rx_config &= ~(AcceptErr | AcceptRunt); 1589 1590 if (rtl_is_8125(tp)) { 1591 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1592 rx_config |= RX_VLAN_8125; 1593 else 1594 rx_config &= ~RX_VLAN_8125; 1595 } 1596 1597 RTL_W32(tp, RxConfig, rx_config); 1598 1599 if (features & NETIF_F_RXCSUM) 1600 tp->cp_cmd |= RxChkSum; 1601 else 1602 tp->cp_cmd &= ~RxChkSum; 1603 1604 if (!rtl_is_8125(tp)) { 1605 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1606 tp->cp_cmd |= RxVlan; 1607 else 1608 tp->cp_cmd &= ~RxVlan; 1609 } 1610 1611 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1612 RTL_R16(tp, CPlusCmd); 1613 1614 rtl_unlock_work(tp); 1615 1616 return 0; 1617 } 1618 1619 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1620 { 1621 return (skb_vlan_tag_present(skb)) ? 1622 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1623 } 1624 1625 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1626 { 1627 u32 opts2 = le32_to_cpu(desc->opts2); 1628 1629 if (opts2 & RxVlanTag) 1630 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1631 } 1632 1633 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1634 void *p) 1635 { 1636 struct rtl8169_private *tp = netdev_priv(dev); 1637 u32 __iomem *data = tp->mmio_addr; 1638 u32 *dw = p; 1639 int i; 1640 1641 rtl_lock_work(tp); 1642 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1643 memcpy_fromio(dw++, data++, 4); 1644 rtl_unlock_work(tp); 1645 } 1646 1647 static u32 rtl8169_get_msglevel(struct net_device *dev) 1648 { 1649 struct rtl8169_private *tp = netdev_priv(dev); 1650 1651 return tp->msg_enable; 1652 } 1653 1654 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1655 { 1656 struct rtl8169_private *tp = netdev_priv(dev); 1657 1658 tp->msg_enable = value; 1659 } 1660 1661 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1662 "tx_packets", 1663 "rx_packets", 1664 "tx_errors", 1665 "rx_errors", 1666 "rx_missed", 1667 "align_errors", 1668 "tx_single_collisions", 1669 "tx_multi_collisions", 1670 "unicast", 1671 "broadcast", 1672 "multicast", 1673 "tx_aborted", 1674 "tx_underrun", 1675 }; 1676 1677 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1678 { 1679 switch (sset) { 1680 case ETH_SS_STATS: 1681 return ARRAY_SIZE(rtl8169_gstrings); 1682 default: 1683 return -EOPNOTSUPP; 1684 } 1685 } 1686 1687 DECLARE_RTL_COND(rtl_counters_cond) 1688 { 1689 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1690 } 1691 1692 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1693 { 1694 dma_addr_t paddr = tp->counters_phys_addr; 1695 u32 cmd; 1696 1697 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1698 RTL_R32(tp, CounterAddrHigh); 1699 cmd = (u64)paddr & DMA_BIT_MASK(32); 1700 RTL_W32(tp, CounterAddrLow, cmd); 1701 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1702 1703 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1704 } 1705 1706 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1707 { 1708 /* 1709 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1710 * tally counters. 1711 */ 1712 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1713 return true; 1714 1715 return rtl8169_do_counters(tp, CounterReset); 1716 } 1717 1718 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1719 { 1720 u8 val = RTL_R8(tp, ChipCmd); 1721 1722 /* 1723 * Some chips are unable to dump tally counters when the receiver 1724 * is disabled. If 0xff chip may be in a PCI power-save state. 1725 */ 1726 if (!(val & CmdRxEnb) || val == 0xff) 1727 return true; 1728 1729 return rtl8169_do_counters(tp, CounterDump); 1730 } 1731 1732 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1733 { 1734 struct rtl8169_counters *counters = tp->counters; 1735 bool ret = false; 1736 1737 /* 1738 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1739 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1740 * reset by a power cycle, while the counter values collected by the 1741 * driver are reset at every driver unload/load cycle. 1742 * 1743 * To make sure the HW values returned by @get_stats64 match the SW 1744 * values, we collect the initial values at first open(*) and use them 1745 * as offsets to normalize the values returned by @get_stats64. 1746 * 1747 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1748 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1749 * set at open time by rtl_hw_start. 1750 */ 1751 1752 if (tp->tc_offset.inited) 1753 return true; 1754 1755 /* If both, reset and update fail, propagate to caller. */ 1756 if (rtl8169_reset_counters(tp)) 1757 ret = true; 1758 1759 if (rtl8169_update_counters(tp)) 1760 ret = true; 1761 1762 tp->tc_offset.tx_errors = counters->tx_errors; 1763 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1764 tp->tc_offset.tx_aborted = counters->tx_aborted; 1765 tp->tc_offset.inited = true; 1766 1767 return ret; 1768 } 1769 1770 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1771 struct ethtool_stats *stats, u64 *data) 1772 { 1773 struct rtl8169_private *tp = netdev_priv(dev); 1774 struct device *d = tp_to_dev(tp); 1775 struct rtl8169_counters *counters = tp->counters; 1776 1777 ASSERT_RTNL(); 1778 1779 pm_runtime_get_noresume(d); 1780 1781 if (pm_runtime_active(d)) 1782 rtl8169_update_counters(tp); 1783 1784 pm_runtime_put_noidle(d); 1785 1786 data[0] = le64_to_cpu(counters->tx_packets); 1787 data[1] = le64_to_cpu(counters->rx_packets); 1788 data[2] = le64_to_cpu(counters->tx_errors); 1789 data[3] = le32_to_cpu(counters->rx_errors); 1790 data[4] = le16_to_cpu(counters->rx_missed); 1791 data[5] = le16_to_cpu(counters->align_errors); 1792 data[6] = le32_to_cpu(counters->tx_one_collision); 1793 data[7] = le32_to_cpu(counters->tx_multi_collision); 1794 data[8] = le64_to_cpu(counters->rx_unicast); 1795 data[9] = le64_to_cpu(counters->rx_broadcast); 1796 data[10] = le32_to_cpu(counters->rx_multicast); 1797 data[11] = le16_to_cpu(counters->tx_aborted); 1798 data[12] = le16_to_cpu(counters->tx_underun); 1799 } 1800 1801 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1802 { 1803 switch(stringset) { 1804 case ETH_SS_STATS: 1805 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1806 break; 1807 } 1808 } 1809 1810 /* 1811 * Interrupt coalescing 1812 * 1813 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1814 * > 8169, 8168 and 810x line of chipsets 1815 * 1816 * 8169, 8168, and 8136(810x) serial chipsets support it. 1817 * 1818 * > 2 - the Tx timer unit at gigabit speed 1819 * 1820 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1821 * (0xe0) bit 1 and bit 0. 1822 * 1823 * For 8169 1824 * bit[1:0] \ speed 1000M 100M 10M 1825 * 0 0 320ns 2.56us 40.96us 1826 * 0 1 2.56us 20.48us 327.7us 1827 * 1 0 5.12us 40.96us 655.4us 1828 * 1 1 10.24us 81.92us 1.31ms 1829 * 1830 * For the other 1831 * bit[1:0] \ speed 1000M 100M 10M 1832 * 0 0 5us 2.56us 40.96us 1833 * 0 1 40us 20.48us 327.7us 1834 * 1 0 80us 40.96us 655.4us 1835 * 1 1 160us 81.92us 1.31ms 1836 */ 1837 1838 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1839 struct rtl_coalesce_scale { 1840 /* Rx / Tx */ 1841 u32 nsecs[2]; 1842 }; 1843 1844 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1845 struct rtl_coalesce_info { 1846 u32 speed; 1847 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1848 }; 1849 1850 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1851 #define rxtx_x1822(r, t) { \ 1852 {{(r), (t)}}, \ 1853 {{(r)*8, (t)*8}}, \ 1854 {{(r)*8*2, (t)*8*2}}, \ 1855 {{(r)*8*2*2, (t)*8*2*2}}, \ 1856 } 1857 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1858 /* speed delays: rx00 tx00 */ 1859 { SPEED_10, rxtx_x1822(40960, 40960) }, 1860 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1861 { SPEED_1000, rxtx_x1822( 320, 320) }, 1862 { 0 }, 1863 }; 1864 1865 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1866 /* speed delays: rx00 tx00 */ 1867 { SPEED_10, rxtx_x1822(40960, 40960) }, 1868 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1869 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1870 { 0 }, 1871 }; 1872 #undef rxtx_x1822 1873 1874 /* get rx/tx scale vector corresponding to current speed */ 1875 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1876 { 1877 struct rtl8169_private *tp = netdev_priv(dev); 1878 const struct rtl_coalesce_info *ci; 1879 1880 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1881 ci = rtl_coalesce_info_8169; 1882 else 1883 ci = rtl_coalesce_info_8168_8136; 1884 1885 for (; ci->speed; ci++) { 1886 if (tp->phydev->speed == ci->speed) 1887 return ci; 1888 } 1889 1890 return ERR_PTR(-ELNRNG); 1891 } 1892 1893 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1894 { 1895 struct rtl8169_private *tp = netdev_priv(dev); 1896 const struct rtl_coalesce_info *ci; 1897 const struct rtl_coalesce_scale *scale; 1898 struct { 1899 u32 *max_frames; 1900 u32 *usecs; 1901 } coal_settings [] = { 1902 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1903 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1904 }, *p = coal_settings; 1905 int i; 1906 u16 w; 1907 1908 if (rtl_is_8125(tp)) 1909 return -EOPNOTSUPP; 1910 1911 memset(ec, 0, sizeof(*ec)); 1912 1913 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1914 ci = rtl_coalesce_info(dev); 1915 if (IS_ERR(ci)) 1916 return PTR_ERR(ci); 1917 1918 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1919 1920 /* read IntrMitigate and adjust according to scale */ 1921 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1922 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1923 w >>= RTL_COALESCE_SHIFT; 1924 *p->usecs = w & RTL_COALESCE_MASK; 1925 } 1926 1927 for (i = 0; i < 2; i++) { 1928 p = coal_settings + i; 1929 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1930 1931 /* 1932 * ethtool_coalesce says it is illegal to set both usecs and 1933 * max_frames to 0. 1934 */ 1935 if (!*p->usecs && !*p->max_frames) 1936 *p->max_frames = 1; 1937 } 1938 1939 return 0; 1940 } 1941 1942 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1943 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1944 struct net_device *dev, u32 nsec, u16 *cp01) 1945 { 1946 const struct rtl_coalesce_info *ci; 1947 u16 i; 1948 1949 ci = rtl_coalesce_info(dev); 1950 if (IS_ERR(ci)) 1951 return ERR_CAST(ci); 1952 1953 for (i = 0; i < 4; i++) { 1954 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1955 ci->scalev[i].nsecs[1]); 1956 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1957 *cp01 = i; 1958 return &ci->scalev[i]; 1959 } 1960 } 1961 1962 return ERR_PTR(-EINVAL); 1963 } 1964 1965 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1966 { 1967 struct rtl8169_private *tp = netdev_priv(dev); 1968 const struct rtl_coalesce_scale *scale; 1969 struct { 1970 u32 frames; 1971 u32 usecs; 1972 } coal_settings [] = { 1973 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 1974 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 1975 }, *p = coal_settings; 1976 u16 w = 0, cp01; 1977 int i; 1978 1979 if (rtl_is_8125(tp)) 1980 return -EOPNOTSUPP; 1981 1982 scale = rtl_coalesce_choose_scale(dev, 1983 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 1984 if (IS_ERR(scale)) 1985 return PTR_ERR(scale); 1986 1987 for (i = 0; i < 2; i++, p++) { 1988 u32 units; 1989 1990 /* 1991 * accept max_frames=1 we returned in rtl_get_coalesce. 1992 * accept it not only when usecs=0 because of e.g. the following scenario: 1993 * 1994 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1995 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1996 * - then user does `ethtool -C eth0 rx-usecs 100` 1997 * 1998 * since ethtool sends to kernel whole ethtool_coalesce 1999 * settings, if we do not handle rx_usecs=!0, rx_frames=1 2000 * we'll reject it below in `frames % 4 != 0`. 2001 */ 2002 if (p->frames == 1) { 2003 p->frames = 0; 2004 } 2005 2006 units = p->usecs * 1000 / scale->nsecs[i]; 2007 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 2008 return -EINVAL; 2009 2010 w <<= RTL_COALESCE_SHIFT; 2011 w |= units; 2012 w <<= RTL_COALESCE_SHIFT; 2013 w |= p->frames >> 2; 2014 } 2015 2016 rtl_lock_work(tp); 2017 2018 RTL_W16(tp, IntrMitigate, swab16(w)); 2019 2020 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2021 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2022 RTL_R16(tp, CPlusCmd); 2023 2024 rtl_unlock_work(tp); 2025 2026 return 0; 2027 } 2028 2029 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 2030 { 2031 struct rtl8169_private *tp = netdev_priv(dev); 2032 struct device *d = tp_to_dev(tp); 2033 int ret; 2034 2035 if (!rtl_supports_eee(tp)) 2036 return -EOPNOTSUPP; 2037 2038 pm_runtime_get_noresume(d); 2039 2040 if (!pm_runtime_active(d)) { 2041 ret = -EOPNOTSUPP; 2042 } else { 2043 ret = phy_ethtool_get_eee(tp->phydev, data); 2044 } 2045 2046 pm_runtime_put_noidle(d); 2047 2048 return ret; 2049 } 2050 2051 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 2052 { 2053 struct rtl8169_private *tp = netdev_priv(dev); 2054 struct device *d = tp_to_dev(tp); 2055 int ret; 2056 2057 if (!rtl_supports_eee(tp)) 2058 return -EOPNOTSUPP; 2059 2060 pm_runtime_get_noresume(d); 2061 2062 if (!pm_runtime_active(d)) { 2063 ret = -EOPNOTSUPP; 2064 goto out; 2065 } 2066 2067 if (dev->phydev->autoneg == AUTONEG_DISABLE || 2068 dev->phydev->duplex != DUPLEX_FULL) { 2069 ret = -EPROTONOSUPPORT; 2070 goto out; 2071 } 2072 2073 ret = phy_ethtool_set_eee(tp->phydev, data); 2074 out: 2075 pm_runtime_put_noidle(d); 2076 return ret; 2077 } 2078 2079 static const struct ethtool_ops rtl8169_ethtool_ops = { 2080 .get_drvinfo = rtl8169_get_drvinfo, 2081 .get_regs_len = rtl8169_get_regs_len, 2082 .get_link = ethtool_op_get_link, 2083 .get_coalesce = rtl_get_coalesce, 2084 .set_coalesce = rtl_set_coalesce, 2085 .get_msglevel = rtl8169_get_msglevel, 2086 .set_msglevel = rtl8169_set_msglevel, 2087 .get_regs = rtl8169_get_regs, 2088 .get_wol = rtl8169_get_wol, 2089 .set_wol = rtl8169_set_wol, 2090 .get_strings = rtl8169_get_strings, 2091 .get_sset_count = rtl8169_get_sset_count, 2092 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2093 .get_ts_info = ethtool_op_get_ts_info, 2094 .nway_reset = phy_ethtool_nway_reset, 2095 .get_eee = rtl8169_get_eee, 2096 .set_eee = rtl8169_set_eee, 2097 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2098 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2099 }; 2100 2101 static void rtl_enable_eee(struct rtl8169_private *tp) 2102 { 2103 struct phy_device *phydev = tp->phydev; 2104 int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2105 2106 if (supported > 0) 2107 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported); 2108 } 2109 2110 static void rtl8169_get_mac_version(struct rtl8169_private *tp) 2111 { 2112 /* 2113 * The driver currently handles the 8168Bf and the 8168Be identically 2114 * but they can be identified more specifically through the test below 2115 * if needed: 2116 * 2117 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2118 * 2119 * Same thing for the 8101Eb and the 8101Ec: 2120 * 2121 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2122 */ 2123 static const struct rtl_mac_info { 2124 u16 mask; 2125 u16 val; 2126 u16 mac_version; 2127 } mac_info[] = { 2128 /* 8125 family. */ 2129 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2130 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2131 2132 /* 8168EP family. */ 2133 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2134 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2135 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2136 2137 /* 8168H family. */ 2138 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2139 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2140 2141 /* 8168G family. */ 2142 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2143 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2144 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2145 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2146 2147 /* 8168F family. */ 2148 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2149 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2150 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2151 2152 /* 8168E family. */ 2153 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2154 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2155 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2156 2157 /* 8168D family. */ 2158 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2159 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2160 2161 /* 8168DP family. */ 2162 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2163 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2164 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2165 2166 /* 8168C family. */ 2167 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2168 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2169 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2170 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2171 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2172 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2173 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2174 2175 /* 8168B family. */ 2176 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2177 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2178 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2179 2180 /* 8101 family. */ 2181 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2182 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2183 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2184 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2185 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2186 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2187 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2188 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2189 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2190 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2191 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2192 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2193 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2194 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2195 /* FIXME: where did these entries come from ? -- FR */ 2196 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2197 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2198 2199 /* 8110 family. */ 2200 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2201 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2202 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2203 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2204 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2205 2206 /* Catch-all */ 2207 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2208 }; 2209 const struct rtl_mac_info *p = mac_info; 2210 u16 reg = RTL_R32(tp, TxConfig) >> 20; 2211 2212 while ((reg & p->mask) != p->val) 2213 p++; 2214 tp->mac_version = p->mac_version; 2215 2216 if (tp->mac_version == RTL_GIGA_MAC_NONE) { 2217 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf); 2218 } else if (!tp->supports_gmii) { 2219 if (tp->mac_version == RTL_GIGA_MAC_VER_42) 2220 tp->mac_version = RTL_GIGA_MAC_VER_43; 2221 else if (tp->mac_version == RTL_GIGA_MAC_VER_45) 2222 tp->mac_version = RTL_GIGA_MAC_VER_47; 2223 else if (tp->mac_version == RTL_GIGA_MAC_VER_46) 2224 tp->mac_version = RTL_GIGA_MAC_VER_48; 2225 } 2226 } 2227 2228 struct phy_reg { 2229 u16 reg; 2230 u16 val; 2231 }; 2232 2233 static void __rtl_writephy_batch(struct rtl8169_private *tp, 2234 const struct phy_reg *regs, int len) 2235 { 2236 while (len-- > 0) { 2237 rtl_writephy(tp, regs->reg, regs->val); 2238 regs++; 2239 } 2240 } 2241 2242 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a)) 2243 2244 static void rtl_release_firmware(struct rtl8169_private *tp) 2245 { 2246 if (tp->rtl_fw) { 2247 rtl_fw_release_firmware(tp->rtl_fw); 2248 kfree(tp->rtl_fw); 2249 tp->rtl_fw = NULL; 2250 } 2251 } 2252 2253 static void rtl_apply_firmware(struct rtl8169_private *tp) 2254 { 2255 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2256 if (tp->rtl_fw) 2257 rtl_fw_write_firmware(tp, tp->rtl_fw); 2258 } 2259 2260 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) 2261 { 2262 if (rtl_readphy(tp, reg) != val) 2263 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); 2264 else 2265 rtl_apply_firmware(tp); 2266 } 2267 2268 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2269 { 2270 /* Adjust EEE LED frequency */ 2271 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2272 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2273 2274 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2275 } 2276 2277 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2278 { 2279 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2280 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2281 } 2282 2283 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp) 2284 { 2285 struct phy_device *phydev = tp->phydev; 2286 2287 phy_write(phydev, 0x1f, 0x0007); 2288 phy_write(phydev, 0x1e, 0x0020); 2289 phy_set_bits(phydev, 0x15, BIT(8)); 2290 2291 phy_write(phydev, 0x1f, 0x0005); 2292 phy_write(phydev, 0x05, 0x8b85); 2293 phy_set_bits(phydev, 0x06, BIT(13)); 2294 2295 phy_write(phydev, 0x1f, 0x0000); 2296 } 2297 2298 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp) 2299 { 2300 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4)); 2301 } 2302 2303 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp) 2304 { 2305 struct phy_device *phydev = tp->phydev; 2306 2307 rtl8168g_config_eee_phy(tp); 2308 2309 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 2310 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 2311 } 2312 2313 static void rtl8125_config_eee_phy(struct rtl8169_private *tp) 2314 { 2315 struct phy_device *phydev = tp->phydev; 2316 2317 rtl8168h_config_eee_phy(tp); 2318 2319 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 2320 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 2321 } 2322 2323 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) 2324 { 2325 static const struct phy_reg phy_reg_init[] = { 2326 { 0x1f, 0x0001 }, 2327 { 0x06, 0x006e }, 2328 { 0x08, 0x0708 }, 2329 { 0x15, 0x4000 }, 2330 { 0x18, 0x65c7 }, 2331 2332 { 0x1f, 0x0001 }, 2333 { 0x03, 0x00a1 }, 2334 { 0x02, 0x0008 }, 2335 { 0x01, 0x0120 }, 2336 { 0x00, 0x1000 }, 2337 { 0x04, 0x0800 }, 2338 { 0x04, 0x0000 }, 2339 2340 { 0x03, 0xff41 }, 2341 { 0x02, 0xdf60 }, 2342 { 0x01, 0x0140 }, 2343 { 0x00, 0x0077 }, 2344 { 0x04, 0x7800 }, 2345 { 0x04, 0x7000 }, 2346 2347 { 0x03, 0x802f }, 2348 { 0x02, 0x4f02 }, 2349 { 0x01, 0x0409 }, 2350 { 0x00, 0xf0f9 }, 2351 { 0x04, 0x9800 }, 2352 { 0x04, 0x9000 }, 2353 2354 { 0x03, 0xdf01 }, 2355 { 0x02, 0xdf20 }, 2356 { 0x01, 0xff95 }, 2357 { 0x00, 0xba00 }, 2358 { 0x04, 0xa800 }, 2359 { 0x04, 0xa000 }, 2360 2361 { 0x03, 0xff41 }, 2362 { 0x02, 0xdf20 }, 2363 { 0x01, 0x0140 }, 2364 { 0x00, 0x00bb }, 2365 { 0x04, 0xb800 }, 2366 { 0x04, 0xb000 }, 2367 2368 { 0x03, 0xdf41 }, 2369 { 0x02, 0xdc60 }, 2370 { 0x01, 0x6340 }, 2371 { 0x00, 0x007d }, 2372 { 0x04, 0xd800 }, 2373 { 0x04, 0xd000 }, 2374 2375 { 0x03, 0xdf01 }, 2376 { 0x02, 0xdf20 }, 2377 { 0x01, 0x100a }, 2378 { 0x00, 0xa0ff }, 2379 { 0x04, 0xf800 }, 2380 { 0x04, 0xf000 }, 2381 2382 { 0x1f, 0x0000 }, 2383 { 0x0b, 0x0000 }, 2384 { 0x00, 0x9200 } 2385 }; 2386 2387 rtl_writephy_batch(tp, phy_reg_init); 2388 } 2389 2390 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) 2391 { 2392 static const struct phy_reg phy_reg_init[] = { 2393 { 0x1f, 0x0002 }, 2394 { 0x01, 0x90d0 }, 2395 { 0x1f, 0x0000 } 2396 }; 2397 2398 rtl_writephy_batch(tp, phy_reg_init); 2399 } 2400 2401 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) 2402 { 2403 struct pci_dev *pdev = tp->pci_dev; 2404 2405 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || 2406 (pdev->subsystem_device != 0xe000)) 2407 return; 2408 2409 rtl_writephy(tp, 0x1f, 0x0001); 2410 rtl_writephy(tp, 0x10, 0xf01b); 2411 rtl_writephy(tp, 0x1f, 0x0000); 2412 } 2413 2414 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) 2415 { 2416 static const struct phy_reg phy_reg_init[] = { 2417 { 0x1f, 0x0001 }, 2418 { 0x04, 0x0000 }, 2419 { 0x03, 0x00a1 }, 2420 { 0x02, 0x0008 }, 2421 { 0x01, 0x0120 }, 2422 { 0x00, 0x1000 }, 2423 { 0x04, 0x0800 }, 2424 { 0x04, 0x9000 }, 2425 { 0x03, 0x802f }, 2426 { 0x02, 0x4f02 }, 2427 { 0x01, 0x0409 }, 2428 { 0x00, 0xf099 }, 2429 { 0x04, 0x9800 }, 2430 { 0x04, 0xa000 }, 2431 { 0x03, 0xdf01 }, 2432 { 0x02, 0xdf20 }, 2433 { 0x01, 0xff95 }, 2434 { 0x00, 0xba00 }, 2435 { 0x04, 0xa800 }, 2436 { 0x04, 0xf000 }, 2437 { 0x03, 0xdf01 }, 2438 { 0x02, 0xdf20 }, 2439 { 0x01, 0x101a }, 2440 { 0x00, 0xa0ff }, 2441 { 0x04, 0xf800 }, 2442 { 0x04, 0x0000 }, 2443 { 0x1f, 0x0000 }, 2444 2445 { 0x1f, 0x0001 }, 2446 { 0x10, 0xf41b }, 2447 { 0x14, 0xfb54 }, 2448 { 0x18, 0xf5c7 }, 2449 { 0x1f, 0x0000 }, 2450 2451 { 0x1f, 0x0001 }, 2452 { 0x17, 0x0cc0 }, 2453 { 0x1f, 0x0000 } 2454 }; 2455 2456 rtl_writephy_batch(tp, phy_reg_init); 2457 2458 rtl8169scd_hw_phy_config_quirk(tp); 2459 } 2460 2461 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) 2462 { 2463 static const struct phy_reg phy_reg_init[] = { 2464 { 0x1f, 0x0001 }, 2465 { 0x04, 0x0000 }, 2466 { 0x03, 0x00a1 }, 2467 { 0x02, 0x0008 }, 2468 { 0x01, 0x0120 }, 2469 { 0x00, 0x1000 }, 2470 { 0x04, 0x0800 }, 2471 { 0x04, 0x9000 }, 2472 { 0x03, 0x802f }, 2473 { 0x02, 0x4f02 }, 2474 { 0x01, 0x0409 }, 2475 { 0x00, 0xf099 }, 2476 { 0x04, 0x9800 }, 2477 { 0x04, 0xa000 }, 2478 { 0x03, 0xdf01 }, 2479 { 0x02, 0xdf20 }, 2480 { 0x01, 0xff95 }, 2481 { 0x00, 0xba00 }, 2482 { 0x04, 0xa800 }, 2483 { 0x04, 0xf000 }, 2484 { 0x03, 0xdf01 }, 2485 { 0x02, 0xdf20 }, 2486 { 0x01, 0x101a }, 2487 { 0x00, 0xa0ff }, 2488 { 0x04, 0xf800 }, 2489 { 0x04, 0x0000 }, 2490 { 0x1f, 0x0000 }, 2491 2492 { 0x1f, 0x0001 }, 2493 { 0x0b, 0x8480 }, 2494 { 0x1f, 0x0000 }, 2495 2496 { 0x1f, 0x0001 }, 2497 { 0x18, 0x67c7 }, 2498 { 0x04, 0x2000 }, 2499 { 0x03, 0x002f }, 2500 { 0x02, 0x4360 }, 2501 { 0x01, 0x0109 }, 2502 { 0x00, 0x3022 }, 2503 { 0x04, 0x2800 }, 2504 { 0x1f, 0x0000 }, 2505 2506 { 0x1f, 0x0001 }, 2507 { 0x17, 0x0cc0 }, 2508 { 0x1f, 0x0000 } 2509 }; 2510 2511 rtl_writephy_batch(tp, phy_reg_init); 2512 } 2513 2514 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) 2515 { 2516 static const struct phy_reg phy_reg_init[] = { 2517 { 0x10, 0xf41b }, 2518 { 0x1f, 0x0000 } 2519 }; 2520 2521 rtl_writephy(tp, 0x1f, 0x0001); 2522 rtl_patchphy(tp, 0x16, 1 << 0); 2523 2524 rtl_writephy_batch(tp, phy_reg_init); 2525 } 2526 2527 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) 2528 { 2529 static const struct phy_reg phy_reg_init[] = { 2530 { 0x1f, 0x0001 }, 2531 { 0x10, 0xf41b }, 2532 { 0x1f, 0x0000 } 2533 }; 2534 2535 rtl_writephy_batch(tp, phy_reg_init); 2536 } 2537 2538 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) 2539 { 2540 static const struct phy_reg phy_reg_init[] = { 2541 { 0x1f, 0x0000 }, 2542 { 0x1d, 0x0f00 }, 2543 { 0x1f, 0x0002 }, 2544 { 0x0c, 0x1ec8 }, 2545 { 0x1f, 0x0000 } 2546 }; 2547 2548 rtl_writephy_batch(tp, phy_reg_init); 2549 } 2550 2551 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) 2552 { 2553 static const struct phy_reg phy_reg_init[] = { 2554 { 0x1f, 0x0001 }, 2555 { 0x1d, 0x3d98 }, 2556 { 0x1f, 0x0000 } 2557 }; 2558 2559 rtl_writephy(tp, 0x1f, 0x0000); 2560 rtl_patchphy(tp, 0x14, 1 << 5); 2561 rtl_patchphy(tp, 0x0d, 1 << 5); 2562 2563 rtl_writephy_batch(tp, phy_reg_init); 2564 } 2565 2566 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) 2567 { 2568 static const struct phy_reg phy_reg_init[] = { 2569 { 0x1f, 0x0001 }, 2570 { 0x12, 0x2300 }, 2571 { 0x1f, 0x0002 }, 2572 { 0x00, 0x88d4 }, 2573 { 0x01, 0x82b1 }, 2574 { 0x03, 0x7002 }, 2575 { 0x08, 0x9e30 }, 2576 { 0x09, 0x01f0 }, 2577 { 0x0a, 0x5500 }, 2578 { 0x0c, 0x00c8 }, 2579 { 0x1f, 0x0003 }, 2580 { 0x12, 0xc096 }, 2581 { 0x16, 0x000a }, 2582 { 0x1f, 0x0000 }, 2583 { 0x1f, 0x0000 }, 2584 { 0x09, 0x2000 }, 2585 { 0x09, 0x0000 } 2586 }; 2587 2588 rtl_writephy_batch(tp, phy_reg_init); 2589 2590 rtl_patchphy(tp, 0x14, 1 << 5); 2591 rtl_patchphy(tp, 0x0d, 1 << 5); 2592 rtl_writephy(tp, 0x1f, 0x0000); 2593 } 2594 2595 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) 2596 { 2597 static const struct phy_reg phy_reg_init[] = { 2598 { 0x1f, 0x0001 }, 2599 { 0x12, 0x2300 }, 2600 { 0x03, 0x802f }, 2601 { 0x02, 0x4f02 }, 2602 { 0x01, 0x0409 }, 2603 { 0x00, 0xf099 }, 2604 { 0x04, 0x9800 }, 2605 { 0x04, 0x9000 }, 2606 { 0x1d, 0x3d98 }, 2607 { 0x1f, 0x0002 }, 2608 { 0x0c, 0x7eb8 }, 2609 { 0x06, 0x0761 }, 2610 { 0x1f, 0x0003 }, 2611 { 0x16, 0x0f0a }, 2612 { 0x1f, 0x0000 } 2613 }; 2614 2615 rtl_writephy_batch(tp, phy_reg_init); 2616 2617 rtl_patchphy(tp, 0x16, 1 << 0); 2618 rtl_patchphy(tp, 0x14, 1 << 5); 2619 rtl_patchphy(tp, 0x0d, 1 << 5); 2620 rtl_writephy(tp, 0x1f, 0x0000); 2621 } 2622 2623 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) 2624 { 2625 static const struct phy_reg phy_reg_init[] = { 2626 { 0x1f, 0x0001 }, 2627 { 0x12, 0x2300 }, 2628 { 0x1d, 0x3d98 }, 2629 { 0x1f, 0x0002 }, 2630 { 0x0c, 0x7eb8 }, 2631 { 0x06, 0x5461 }, 2632 { 0x1f, 0x0003 }, 2633 { 0x16, 0x0f0a }, 2634 { 0x1f, 0x0000 } 2635 }; 2636 2637 rtl_writephy_batch(tp, phy_reg_init); 2638 2639 rtl_patchphy(tp, 0x16, 1 << 0); 2640 rtl_patchphy(tp, 0x14, 1 << 5); 2641 rtl_patchphy(tp, 0x0d, 1 << 5); 2642 rtl_writephy(tp, 0x1f, 0x0000); 2643 } 2644 2645 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) 2646 { 2647 rtl8168c_3_hw_phy_config(tp); 2648 } 2649 2650 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 2651 /* Channel Estimation */ 2652 { 0x1f, 0x0001 }, 2653 { 0x06, 0x4064 }, 2654 { 0x07, 0x2863 }, 2655 { 0x08, 0x059c }, 2656 { 0x09, 0x26b4 }, 2657 { 0x0a, 0x6a19 }, 2658 { 0x0b, 0xdcc8 }, 2659 { 0x10, 0xf06d }, 2660 { 0x14, 0x7f68 }, 2661 { 0x18, 0x7fd9 }, 2662 { 0x1c, 0xf0ff }, 2663 { 0x1d, 0x3d9c }, 2664 { 0x1f, 0x0003 }, 2665 { 0x12, 0xf49f }, 2666 { 0x13, 0x070b }, 2667 { 0x1a, 0x05ad }, 2668 { 0x14, 0x94c0 }, 2669 2670 /* 2671 * Tx Error Issue 2672 * Enhance line driver power 2673 */ 2674 { 0x1f, 0x0002 }, 2675 { 0x06, 0x5561 }, 2676 { 0x1f, 0x0005 }, 2677 { 0x05, 0x8332 }, 2678 { 0x06, 0x5561 }, 2679 2680 /* 2681 * Can not link to 1Gbps with bad cable 2682 * Decrease SNR threshold form 21.07dB to 19.04dB 2683 */ 2684 { 0x1f, 0x0001 }, 2685 { 0x17, 0x0cc0 }, 2686 2687 { 0x1f, 0x0000 }, 2688 { 0x0d, 0xf880 } 2689 }; 2690 2691 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 2692 { 0x1f, 0x0002 }, 2693 { 0x05, 0x669a }, 2694 { 0x1f, 0x0005 }, 2695 { 0x05, 0x8330 }, 2696 { 0x06, 0x669a }, 2697 { 0x1f, 0x0002 } 2698 }; 2699 2700 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) 2701 { 2702 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2703 2704 /* 2705 * Rx Error Issue 2706 * Fine Tune Switching regulator parameter 2707 */ 2708 rtl_writephy(tp, 0x1f, 0x0002); 2709 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); 2710 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); 2711 2712 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2713 int val; 2714 2715 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2716 2717 val = rtl_readphy(tp, 0x0d); 2718 2719 if ((val & 0x00ff) != 0x006c) { 2720 static const u32 set[] = { 2721 0x0065, 0x0066, 0x0067, 0x0068, 2722 0x0069, 0x006a, 0x006b, 0x006c 2723 }; 2724 int i; 2725 2726 rtl_writephy(tp, 0x1f, 0x0002); 2727 2728 val &= 0xff00; 2729 for (i = 0; i < ARRAY_SIZE(set); i++) 2730 rtl_writephy(tp, 0x0d, val | set[i]); 2731 } 2732 } else { 2733 static const struct phy_reg phy_reg_init[] = { 2734 { 0x1f, 0x0002 }, 2735 { 0x05, 0x6662 }, 2736 { 0x1f, 0x0005 }, 2737 { 0x05, 0x8330 }, 2738 { 0x06, 0x6662 } 2739 }; 2740 2741 rtl_writephy_batch(tp, phy_reg_init); 2742 } 2743 2744 /* RSET couple improve */ 2745 rtl_writephy(tp, 0x1f, 0x0002); 2746 rtl_patchphy(tp, 0x0d, 0x0300); 2747 rtl_patchphy(tp, 0x0f, 0x0010); 2748 2749 /* Fine tune PLL performance */ 2750 rtl_writephy(tp, 0x1f, 0x0002); 2751 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2752 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2753 2754 rtl_writephy(tp, 0x1f, 0x0005); 2755 rtl_writephy(tp, 0x05, 0x001b); 2756 2757 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); 2758 2759 rtl_writephy(tp, 0x1f, 0x0000); 2760 } 2761 2762 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) 2763 { 2764 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2765 2766 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2767 int val; 2768 2769 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2770 2771 val = rtl_readphy(tp, 0x0d); 2772 if ((val & 0x00ff) != 0x006c) { 2773 static const u32 set[] = { 2774 0x0065, 0x0066, 0x0067, 0x0068, 2775 0x0069, 0x006a, 0x006b, 0x006c 2776 }; 2777 int i; 2778 2779 rtl_writephy(tp, 0x1f, 0x0002); 2780 2781 val &= 0xff00; 2782 for (i = 0; i < ARRAY_SIZE(set); i++) 2783 rtl_writephy(tp, 0x0d, val | set[i]); 2784 } 2785 } else { 2786 static const struct phy_reg phy_reg_init[] = { 2787 { 0x1f, 0x0002 }, 2788 { 0x05, 0x2642 }, 2789 { 0x1f, 0x0005 }, 2790 { 0x05, 0x8330 }, 2791 { 0x06, 0x2642 } 2792 }; 2793 2794 rtl_writephy_batch(tp, phy_reg_init); 2795 } 2796 2797 /* Fine tune PLL performance */ 2798 rtl_writephy(tp, 0x1f, 0x0002); 2799 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2800 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2801 2802 /* Switching regulator Slew rate */ 2803 rtl_writephy(tp, 0x1f, 0x0002); 2804 rtl_patchphy(tp, 0x0f, 0x0017); 2805 2806 rtl_writephy(tp, 0x1f, 0x0005); 2807 rtl_writephy(tp, 0x05, 0x001b); 2808 2809 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); 2810 2811 rtl_writephy(tp, 0x1f, 0x0000); 2812 } 2813 2814 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) 2815 { 2816 static const struct phy_reg phy_reg_init[] = { 2817 { 0x1f, 0x0002 }, 2818 { 0x10, 0x0008 }, 2819 { 0x0d, 0x006c }, 2820 2821 { 0x1f, 0x0000 }, 2822 { 0x0d, 0xf880 }, 2823 2824 { 0x1f, 0x0001 }, 2825 { 0x17, 0x0cc0 }, 2826 2827 { 0x1f, 0x0001 }, 2828 { 0x0b, 0xa4d8 }, 2829 { 0x09, 0x281c }, 2830 { 0x07, 0x2883 }, 2831 { 0x0a, 0x6b35 }, 2832 { 0x1d, 0x3da4 }, 2833 { 0x1c, 0xeffd }, 2834 { 0x14, 0x7f52 }, 2835 { 0x18, 0x7fc6 }, 2836 { 0x08, 0x0601 }, 2837 { 0x06, 0x4063 }, 2838 { 0x10, 0xf074 }, 2839 { 0x1f, 0x0003 }, 2840 { 0x13, 0x0789 }, 2841 { 0x12, 0xf4bd }, 2842 { 0x1a, 0x04fd }, 2843 { 0x14, 0x84b0 }, 2844 { 0x1f, 0x0000 }, 2845 { 0x00, 0x9200 }, 2846 2847 { 0x1f, 0x0005 }, 2848 { 0x01, 0x0340 }, 2849 { 0x1f, 0x0001 }, 2850 { 0x04, 0x4000 }, 2851 { 0x03, 0x1d21 }, 2852 { 0x02, 0x0c32 }, 2853 { 0x01, 0x0200 }, 2854 { 0x00, 0x5554 }, 2855 { 0x04, 0x4800 }, 2856 { 0x04, 0x4000 }, 2857 { 0x04, 0xf000 }, 2858 { 0x03, 0xdf01 }, 2859 { 0x02, 0xdf20 }, 2860 { 0x01, 0x101a }, 2861 { 0x00, 0xa0ff }, 2862 { 0x04, 0xf800 }, 2863 { 0x04, 0xf000 }, 2864 { 0x1f, 0x0000 }, 2865 2866 { 0x1f, 0x0007 }, 2867 { 0x1e, 0x0023 }, 2868 { 0x16, 0x0000 }, 2869 { 0x1f, 0x0000 } 2870 }; 2871 2872 rtl_writephy_batch(tp, phy_reg_init); 2873 } 2874 2875 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) 2876 { 2877 static const struct phy_reg phy_reg_init[] = { 2878 { 0x1f, 0x0001 }, 2879 { 0x17, 0x0cc0 }, 2880 2881 { 0x1f, 0x0007 }, 2882 { 0x1e, 0x002d }, 2883 { 0x18, 0x0040 }, 2884 { 0x1f, 0x0000 } 2885 }; 2886 2887 rtl_writephy_batch(tp, phy_reg_init); 2888 rtl_patchphy(tp, 0x0d, 1 << 5); 2889 } 2890 2891 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) 2892 { 2893 static const struct phy_reg phy_reg_init[] = { 2894 /* Enable Delay cap */ 2895 { 0x1f, 0x0005 }, 2896 { 0x05, 0x8b80 }, 2897 { 0x06, 0xc896 }, 2898 { 0x1f, 0x0000 }, 2899 2900 /* Channel estimation fine tune */ 2901 { 0x1f, 0x0001 }, 2902 { 0x0b, 0x6c20 }, 2903 { 0x07, 0x2872 }, 2904 { 0x1c, 0xefff }, 2905 { 0x1f, 0x0003 }, 2906 { 0x14, 0x6420 }, 2907 { 0x1f, 0x0000 }, 2908 2909 /* Update PFM & 10M TX idle timer */ 2910 { 0x1f, 0x0007 }, 2911 { 0x1e, 0x002f }, 2912 { 0x15, 0x1919 }, 2913 { 0x1f, 0x0000 }, 2914 2915 { 0x1f, 0x0007 }, 2916 { 0x1e, 0x00ac }, 2917 { 0x18, 0x0006 }, 2918 { 0x1f, 0x0000 } 2919 }; 2920 2921 rtl_apply_firmware(tp); 2922 2923 rtl_writephy_batch(tp, phy_reg_init); 2924 2925 /* DCO enable for 10M IDLE Power */ 2926 rtl_writephy(tp, 0x1f, 0x0007); 2927 rtl_writephy(tp, 0x1e, 0x0023); 2928 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 2929 rtl_writephy(tp, 0x1f, 0x0000); 2930 2931 /* For impedance matching */ 2932 rtl_writephy(tp, 0x1f, 0x0002); 2933 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00); 2934 rtl_writephy(tp, 0x1f, 0x0000); 2935 2936 /* PHY auto speed down */ 2937 rtl_writephy(tp, 0x1f, 0x0007); 2938 rtl_writephy(tp, 0x1e, 0x002d); 2939 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000); 2940 rtl_writephy(tp, 0x1f, 0x0000); 2941 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 2942 2943 rtl_writephy(tp, 0x1f, 0x0005); 2944 rtl_writephy(tp, 0x05, 0x8b86); 2945 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 2946 rtl_writephy(tp, 0x1f, 0x0000); 2947 2948 rtl_writephy(tp, 0x1f, 0x0005); 2949 rtl_writephy(tp, 0x05, 0x8b85); 2950 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); 2951 rtl_writephy(tp, 0x1f, 0x0007); 2952 rtl_writephy(tp, 0x1e, 0x0020); 2953 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100); 2954 rtl_writephy(tp, 0x1f, 0x0006); 2955 rtl_writephy(tp, 0x00, 0x5a00); 2956 rtl_writephy(tp, 0x1f, 0x0000); 2957 rtl_writephy(tp, 0x0d, 0x0007); 2958 rtl_writephy(tp, 0x0e, 0x003c); 2959 rtl_writephy(tp, 0x0d, 0x4007); 2960 rtl_writephy(tp, 0x0e, 0x0000); 2961 rtl_writephy(tp, 0x0d, 0x0000); 2962 } 2963 2964 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2965 { 2966 const u16 w[] = { 2967 addr[0] | (addr[1] << 8), 2968 addr[2] | (addr[3] << 8), 2969 addr[4] | (addr[5] << 8) 2970 }; 2971 2972 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2973 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2974 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2975 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2976 } 2977 2978 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) 2979 { 2980 static const struct phy_reg phy_reg_init[] = { 2981 /* Enable Delay cap */ 2982 { 0x1f, 0x0004 }, 2983 { 0x1f, 0x0007 }, 2984 { 0x1e, 0x00ac }, 2985 { 0x18, 0x0006 }, 2986 { 0x1f, 0x0002 }, 2987 { 0x1f, 0x0000 }, 2988 { 0x1f, 0x0000 }, 2989 2990 /* Channel estimation fine tune */ 2991 { 0x1f, 0x0003 }, 2992 { 0x09, 0xa20f }, 2993 { 0x1f, 0x0000 }, 2994 { 0x1f, 0x0000 }, 2995 2996 /* Green Setting */ 2997 { 0x1f, 0x0005 }, 2998 { 0x05, 0x8b5b }, 2999 { 0x06, 0x9222 }, 3000 { 0x05, 0x8b6d }, 3001 { 0x06, 0x8000 }, 3002 { 0x05, 0x8b76 }, 3003 { 0x06, 0x8000 }, 3004 { 0x1f, 0x0000 } 3005 }; 3006 3007 rtl_apply_firmware(tp); 3008 3009 rtl_writephy_batch(tp, phy_reg_init); 3010 3011 /* For 4-corner performance improve */ 3012 rtl_writephy(tp, 0x1f, 0x0005); 3013 rtl_writephy(tp, 0x05, 0x8b80); 3014 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 3015 rtl_writephy(tp, 0x1f, 0x0000); 3016 3017 /* PHY auto speed down */ 3018 rtl_writephy(tp, 0x1f, 0x0004); 3019 rtl_writephy(tp, 0x1f, 0x0007); 3020 rtl_writephy(tp, 0x1e, 0x002d); 3021 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3022 rtl_writephy(tp, 0x1f, 0x0002); 3023 rtl_writephy(tp, 0x1f, 0x0000); 3024 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3025 3026 /* improve 10M EEE waveform */ 3027 rtl_writephy(tp, 0x1f, 0x0005); 3028 rtl_writephy(tp, 0x05, 0x8b86); 3029 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3030 rtl_writephy(tp, 0x1f, 0x0000); 3031 3032 /* Improve 2-pair detection performance */ 3033 rtl_writephy(tp, 0x1f, 0x0005); 3034 rtl_writephy(tp, 0x05, 0x8b85); 3035 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3036 rtl_writephy(tp, 0x1f, 0x0000); 3037 3038 rtl8168f_config_eee_phy(tp); 3039 rtl_enable_eee(tp); 3040 3041 /* Green feature */ 3042 rtl_writephy(tp, 0x1f, 0x0003); 3043 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000); 3044 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000); 3045 rtl_writephy(tp, 0x1f, 0x0000); 3046 rtl_writephy(tp, 0x1f, 0x0005); 3047 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000); 3048 rtl_writephy(tp, 0x1f, 0x0000); 3049 3050 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ 3051 rtl_rar_exgmac_set(tp, tp->dev->dev_addr); 3052 } 3053 3054 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) 3055 { 3056 /* For 4-corner performance improve */ 3057 rtl_writephy(tp, 0x1f, 0x0005); 3058 rtl_writephy(tp, 0x05, 0x8b80); 3059 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000); 3060 rtl_writephy(tp, 0x1f, 0x0000); 3061 3062 /* PHY auto speed down */ 3063 rtl_writephy(tp, 0x1f, 0x0007); 3064 rtl_writephy(tp, 0x1e, 0x002d); 3065 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3066 rtl_writephy(tp, 0x1f, 0x0000); 3067 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3068 3069 /* Improve 10M EEE waveform */ 3070 rtl_writephy(tp, 0x1f, 0x0005); 3071 rtl_writephy(tp, 0x05, 0x8b86); 3072 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3073 rtl_writephy(tp, 0x1f, 0x0000); 3074 3075 rtl8168f_config_eee_phy(tp); 3076 rtl_enable_eee(tp); 3077 } 3078 3079 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) 3080 { 3081 static const struct phy_reg phy_reg_init[] = { 3082 /* Channel estimation fine tune */ 3083 { 0x1f, 0x0003 }, 3084 { 0x09, 0xa20f }, 3085 { 0x1f, 0x0000 }, 3086 3087 /* Modify green table for giga & fnet */ 3088 { 0x1f, 0x0005 }, 3089 { 0x05, 0x8b55 }, 3090 { 0x06, 0x0000 }, 3091 { 0x05, 0x8b5e }, 3092 { 0x06, 0x0000 }, 3093 { 0x05, 0x8b67 }, 3094 { 0x06, 0x0000 }, 3095 { 0x05, 0x8b70 }, 3096 { 0x06, 0x0000 }, 3097 { 0x1f, 0x0000 }, 3098 { 0x1f, 0x0007 }, 3099 { 0x1e, 0x0078 }, 3100 { 0x17, 0x0000 }, 3101 { 0x19, 0x00fb }, 3102 { 0x1f, 0x0000 }, 3103 3104 /* Modify green table for 10M */ 3105 { 0x1f, 0x0005 }, 3106 { 0x05, 0x8b79 }, 3107 { 0x06, 0xaa00 }, 3108 { 0x1f, 0x0000 }, 3109 3110 /* Disable hiimpedance detection (RTCT) */ 3111 { 0x1f, 0x0003 }, 3112 { 0x01, 0x328a }, 3113 { 0x1f, 0x0000 } 3114 }; 3115 3116 rtl_apply_firmware(tp); 3117 3118 rtl_writephy_batch(tp, phy_reg_init); 3119 3120 rtl8168f_hw_phy_config(tp); 3121 3122 /* Improve 2-pair detection performance */ 3123 rtl_writephy(tp, 0x1f, 0x0005); 3124 rtl_writephy(tp, 0x05, 0x8b85); 3125 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3126 rtl_writephy(tp, 0x1f, 0x0000); 3127 } 3128 3129 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) 3130 { 3131 rtl_apply_firmware(tp); 3132 3133 rtl8168f_hw_phy_config(tp); 3134 } 3135 3136 static void rtl8411_hw_phy_config(struct rtl8169_private *tp) 3137 { 3138 static const struct phy_reg phy_reg_init[] = { 3139 /* Channel estimation fine tune */ 3140 { 0x1f, 0x0003 }, 3141 { 0x09, 0xa20f }, 3142 { 0x1f, 0x0000 }, 3143 3144 /* Modify green table for giga & fnet */ 3145 { 0x1f, 0x0005 }, 3146 { 0x05, 0x8b55 }, 3147 { 0x06, 0x0000 }, 3148 { 0x05, 0x8b5e }, 3149 { 0x06, 0x0000 }, 3150 { 0x05, 0x8b67 }, 3151 { 0x06, 0x0000 }, 3152 { 0x05, 0x8b70 }, 3153 { 0x06, 0x0000 }, 3154 { 0x1f, 0x0000 }, 3155 { 0x1f, 0x0007 }, 3156 { 0x1e, 0x0078 }, 3157 { 0x17, 0x0000 }, 3158 { 0x19, 0x00aa }, 3159 { 0x1f, 0x0000 }, 3160 3161 /* Modify green table for 10M */ 3162 { 0x1f, 0x0005 }, 3163 { 0x05, 0x8b79 }, 3164 { 0x06, 0xaa00 }, 3165 { 0x1f, 0x0000 }, 3166 3167 /* Disable hiimpedance detection (RTCT) */ 3168 { 0x1f, 0x0003 }, 3169 { 0x01, 0x328a }, 3170 { 0x1f, 0x0000 } 3171 }; 3172 3173 3174 rtl_apply_firmware(tp); 3175 3176 rtl8168f_hw_phy_config(tp); 3177 3178 /* Improve 2-pair detection performance */ 3179 rtl_writephy(tp, 0x1f, 0x0005); 3180 rtl_writephy(tp, 0x05, 0x8b85); 3181 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3182 rtl_writephy(tp, 0x1f, 0x0000); 3183 3184 rtl_writephy_batch(tp, phy_reg_init); 3185 3186 /* Modify green table for giga */ 3187 rtl_writephy(tp, 0x1f, 0x0005); 3188 rtl_writephy(tp, 0x05, 0x8b54); 3189 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3190 rtl_writephy(tp, 0x05, 0x8b5d); 3191 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3192 rtl_writephy(tp, 0x05, 0x8a7c); 3193 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3194 rtl_writephy(tp, 0x05, 0x8a7f); 3195 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000); 3196 rtl_writephy(tp, 0x05, 0x8a82); 3197 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3198 rtl_writephy(tp, 0x05, 0x8a85); 3199 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3200 rtl_writephy(tp, 0x05, 0x8a88); 3201 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3202 rtl_writephy(tp, 0x1f, 0x0000); 3203 3204 /* uc same-seed solution */ 3205 rtl_writephy(tp, 0x1f, 0x0005); 3206 rtl_writephy(tp, 0x05, 0x8b85); 3207 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000); 3208 rtl_writephy(tp, 0x1f, 0x0000); 3209 3210 /* Green feature */ 3211 rtl_writephy(tp, 0x1f, 0x0003); 3212 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); 3213 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); 3214 rtl_writephy(tp, 0x1f, 0x0000); 3215 } 3216 3217 static void rtl8168g_disable_aldps(struct rtl8169_private *tp) 3218 { 3219 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0); 3220 } 3221 3222 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp) 3223 { 3224 struct phy_device *phydev = tp->phydev; 3225 3226 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 3227 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 3228 phy_write(phydev, 0x1f, 0x0a43); 3229 phy_write(phydev, 0x13, 0x8084); 3230 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13)); 3231 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0)); 3232 3233 phy_write(phydev, 0x1f, 0x0000); 3234 } 3235 3236 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) 3237 { 3238 int ret; 3239 3240 rtl_apply_firmware(tp); 3241 3242 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10); 3243 if (ret & BIT(8)) 3244 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0); 3245 else 3246 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15)); 3247 3248 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13); 3249 if (ret & BIT(8)) 3250 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1)); 3251 else 3252 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0); 3253 3254 /* Enable PHY auto speed down */ 3255 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3256 3257 rtl8168g_phy_adjust_10m_aldps(tp); 3258 3259 /* EEE auto-fallback function */ 3260 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3261 3262 /* Enable UC LPF tune function */ 3263 rtl_writephy(tp, 0x1f, 0x0a43); 3264 rtl_writephy(tp, 0x13, 0x8012); 3265 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3266 3267 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3268 3269 /* Improve SWR Efficiency */ 3270 rtl_writephy(tp, 0x1f, 0x0bcd); 3271 rtl_writephy(tp, 0x14, 0x5065); 3272 rtl_writephy(tp, 0x14, 0xd065); 3273 rtl_writephy(tp, 0x1f, 0x0bc8); 3274 rtl_writephy(tp, 0x11, 0x5655); 3275 rtl_writephy(tp, 0x1f, 0x0bcd); 3276 rtl_writephy(tp, 0x14, 0x1065); 3277 rtl_writephy(tp, 0x14, 0x9065); 3278 rtl_writephy(tp, 0x14, 0x1065); 3279 rtl_writephy(tp, 0x1f, 0x0000); 3280 3281 rtl8168g_disable_aldps(tp); 3282 rtl8168g_config_eee_phy(tp); 3283 rtl_enable_eee(tp); 3284 } 3285 3286 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) 3287 { 3288 rtl_apply_firmware(tp); 3289 rtl8168g_config_eee_phy(tp); 3290 rtl_enable_eee(tp); 3291 } 3292 3293 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) 3294 { 3295 u16 dout_tapbin; 3296 u32 data; 3297 3298 rtl_apply_firmware(tp); 3299 3300 /* CHN EST parameters adjust - giga master */ 3301 rtl_writephy(tp, 0x1f, 0x0a43); 3302 rtl_writephy(tp, 0x13, 0x809b); 3303 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800); 3304 rtl_writephy(tp, 0x13, 0x80a2); 3305 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00); 3306 rtl_writephy(tp, 0x13, 0x80a4); 3307 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00); 3308 rtl_writephy(tp, 0x13, 0x809c); 3309 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00); 3310 rtl_writephy(tp, 0x1f, 0x0000); 3311 3312 /* CHN EST parameters adjust - giga slave */ 3313 rtl_writephy(tp, 0x1f, 0x0a43); 3314 rtl_writephy(tp, 0x13, 0x80ad); 3315 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800); 3316 rtl_writephy(tp, 0x13, 0x80b4); 3317 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00); 3318 rtl_writephy(tp, 0x13, 0x80ac); 3319 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00); 3320 rtl_writephy(tp, 0x1f, 0x0000); 3321 3322 /* CHN EST parameters adjust - fnet */ 3323 rtl_writephy(tp, 0x1f, 0x0a43); 3324 rtl_writephy(tp, 0x13, 0x808e); 3325 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00); 3326 rtl_writephy(tp, 0x13, 0x8090); 3327 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00); 3328 rtl_writephy(tp, 0x13, 0x8092); 3329 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00); 3330 rtl_writephy(tp, 0x1f, 0x0000); 3331 3332 /* enable R-tune & PGA-retune function */ 3333 dout_tapbin = 0; 3334 rtl_writephy(tp, 0x1f, 0x0a46); 3335 data = rtl_readphy(tp, 0x13); 3336 data &= 3; 3337 data <<= 2; 3338 dout_tapbin |= data; 3339 data = rtl_readphy(tp, 0x12); 3340 data &= 0xc000; 3341 data >>= 14; 3342 dout_tapbin |= data; 3343 dout_tapbin = ~(dout_tapbin^0x08); 3344 dout_tapbin <<= 12; 3345 dout_tapbin &= 0xf000; 3346 rtl_writephy(tp, 0x1f, 0x0a43); 3347 rtl_writephy(tp, 0x13, 0x827a); 3348 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3349 rtl_writephy(tp, 0x13, 0x827b); 3350 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3351 rtl_writephy(tp, 0x13, 0x827c); 3352 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3353 rtl_writephy(tp, 0x13, 0x827d); 3354 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3355 3356 rtl_writephy(tp, 0x1f, 0x0a43); 3357 rtl_writephy(tp, 0x13, 0x0811); 3358 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3359 rtl_writephy(tp, 0x1f, 0x0a42); 3360 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3361 rtl_writephy(tp, 0x1f, 0x0000); 3362 3363 /* enable GPHY 10M */ 3364 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3365 3366 /* SAR ADC performance */ 3367 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 3368 3369 rtl_writephy(tp, 0x1f, 0x0a43); 3370 rtl_writephy(tp, 0x13, 0x803f); 3371 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3372 rtl_writephy(tp, 0x13, 0x8047); 3373 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3374 rtl_writephy(tp, 0x13, 0x804f); 3375 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3376 rtl_writephy(tp, 0x13, 0x8057); 3377 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3378 rtl_writephy(tp, 0x13, 0x805f); 3379 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3380 rtl_writephy(tp, 0x13, 0x8067); 3381 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3382 rtl_writephy(tp, 0x13, 0x806f); 3383 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3384 rtl_writephy(tp, 0x1f, 0x0000); 3385 3386 /* disable phy pfm mode */ 3387 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3388 3389 rtl8168g_disable_aldps(tp); 3390 rtl8168h_config_eee_phy(tp); 3391 rtl_enable_eee(tp); 3392 } 3393 3394 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) 3395 { 3396 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; 3397 u16 rlen; 3398 u32 data; 3399 3400 rtl_apply_firmware(tp); 3401 3402 /* CHIN EST parameter update */ 3403 rtl_writephy(tp, 0x1f, 0x0a43); 3404 rtl_writephy(tp, 0x13, 0x808a); 3405 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f); 3406 rtl_writephy(tp, 0x1f, 0x0000); 3407 3408 /* enable R-tune & PGA-retune function */ 3409 rtl_writephy(tp, 0x1f, 0x0a43); 3410 rtl_writephy(tp, 0x13, 0x0811); 3411 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3412 rtl_writephy(tp, 0x1f, 0x0a42); 3413 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3414 rtl_writephy(tp, 0x1f, 0x0000); 3415 3416 /* enable GPHY 10M */ 3417 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3418 3419 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 3420 data = r8168_mac_ocp_read(tp, 0xdd02); 3421 ioffset_p3 = ((data & 0x80)>>7); 3422 ioffset_p3 <<= 3; 3423 3424 data = r8168_mac_ocp_read(tp, 0xdd00); 3425 ioffset_p3 |= ((data & (0xe000))>>13); 3426 ioffset_p2 = ((data & (0x1e00))>>9); 3427 ioffset_p1 = ((data & (0x01e0))>>5); 3428 ioffset_p0 = ((data & 0x0010)>>4); 3429 ioffset_p0 <<= 3; 3430 ioffset_p0 |= (data & (0x07)); 3431 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); 3432 3433 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || 3434 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) { 3435 rtl_writephy(tp, 0x1f, 0x0bcf); 3436 rtl_writephy(tp, 0x16, data); 3437 rtl_writephy(tp, 0x1f, 0x0000); 3438 } 3439 3440 /* Modify rlen (TX LPF corner frequency) level */ 3441 rtl_writephy(tp, 0x1f, 0x0bcd); 3442 data = rtl_readphy(tp, 0x16); 3443 data &= 0x000f; 3444 rlen = 0; 3445 if (data > 3) 3446 rlen = data - 3; 3447 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); 3448 rtl_writephy(tp, 0x17, data); 3449 rtl_writephy(tp, 0x1f, 0x0bcd); 3450 rtl_writephy(tp, 0x1f, 0x0000); 3451 3452 /* disable phy pfm mode */ 3453 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3454 3455 rtl8168g_disable_aldps(tp); 3456 rtl8168g_config_eee_phy(tp); 3457 rtl_enable_eee(tp); 3458 } 3459 3460 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) 3461 { 3462 /* Enable PHY auto speed down */ 3463 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3464 3465 rtl8168g_phy_adjust_10m_aldps(tp); 3466 3467 /* Enable EEE auto-fallback function */ 3468 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3469 3470 /* Enable UC LPF tune function */ 3471 rtl_writephy(tp, 0x1f, 0x0a43); 3472 rtl_writephy(tp, 0x13, 0x8012); 3473 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3474 rtl_writephy(tp, 0x1f, 0x0000); 3475 3476 /* set rg_sel_sdm_rate */ 3477 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3478 3479 rtl8168g_disable_aldps(tp); 3480 rtl8168g_config_eee_phy(tp); 3481 rtl_enable_eee(tp); 3482 } 3483 3484 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) 3485 { 3486 rtl8168g_phy_adjust_10m_aldps(tp); 3487 3488 /* Enable UC LPF tune function */ 3489 rtl_writephy(tp, 0x1f, 0x0a43); 3490 rtl_writephy(tp, 0x13, 0x8012); 3491 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3492 rtl_writephy(tp, 0x1f, 0x0000); 3493 3494 /* Set rg_sel_sdm_rate */ 3495 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3496 3497 /* Channel estimation parameters */ 3498 rtl_writephy(tp, 0x1f, 0x0a43); 3499 rtl_writephy(tp, 0x13, 0x80f3); 3500 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff); 3501 rtl_writephy(tp, 0x13, 0x80f0); 3502 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff); 3503 rtl_writephy(tp, 0x13, 0x80ef); 3504 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff); 3505 rtl_writephy(tp, 0x13, 0x80f6); 3506 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff); 3507 rtl_writephy(tp, 0x13, 0x80ec); 3508 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff); 3509 rtl_writephy(tp, 0x13, 0x80ed); 3510 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3511 rtl_writephy(tp, 0x13, 0x80f2); 3512 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff); 3513 rtl_writephy(tp, 0x13, 0x80f4); 3514 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff); 3515 rtl_writephy(tp, 0x1f, 0x0a43); 3516 rtl_writephy(tp, 0x13, 0x8110); 3517 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff); 3518 rtl_writephy(tp, 0x13, 0x810f); 3519 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff); 3520 rtl_writephy(tp, 0x13, 0x8111); 3521 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff); 3522 rtl_writephy(tp, 0x13, 0x8113); 3523 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff); 3524 rtl_writephy(tp, 0x13, 0x8115); 3525 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff); 3526 rtl_writephy(tp, 0x13, 0x810e); 3527 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff); 3528 rtl_writephy(tp, 0x13, 0x810c); 3529 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3530 rtl_writephy(tp, 0x13, 0x810b); 3531 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff); 3532 rtl_writephy(tp, 0x1f, 0x0a43); 3533 rtl_writephy(tp, 0x13, 0x80d1); 3534 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff); 3535 rtl_writephy(tp, 0x13, 0x80cd); 3536 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff); 3537 rtl_writephy(tp, 0x13, 0x80d3); 3538 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff); 3539 rtl_writephy(tp, 0x13, 0x80d5); 3540 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff); 3541 rtl_writephy(tp, 0x13, 0x80d7); 3542 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff); 3543 3544 /* Force PWM-mode */ 3545 rtl_writephy(tp, 0x1f, 0x0bcd); 3546 rtl_writephy(tp, 0x14, 0x5065); 3547 rtl_writephy(tp, 0x14, 0xd065); 3548 rtl_writephy(tp, 0x1f, 0x0bc8); 3549 rtl_writephy(tp, 0x12, 0x00ed); 3550 rtl_writephy(tp, 0x1f, 0x0bcd); 3551 rtl_writephy(tp, 0x14, 0x1065); 3552 rtl_writephy(tp, 0x14, 0x9065); 3553 rtl_writephy(tp, 0x14, 0x1065); 3554 rtl_writephy(tp, 0x1f, 0x0000); 3555 3556 rtl8168g_disable_aldps(tp); 3557 rtl8168g_config_eee_phy(tp); 3558 rtl_enable_eee(tp); 3559 } 3560 3561 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) 3562 { 3563 static const struct phy_reg phy_reg_init[] = { 3564 { 0x1f, 0x0003 }, 3565 { 0x08, 0x441d }, 3566 { 0x01, 0x9100 }, 3567 { 0x1f, 0x0000 } 3568 }; 3569 3570 rtl_writephy(tp, 0x1f, 0x0000); 3571 rtl_patchphy(tp, 0x11, 1 << 12); 3572 rtl_patchphy(tp, 0x19, 1 << 13); 3573 rtl_patchphy(tp, 0x10, 1 << 15); 3574 3575 rtl_writephy_batch(tp, phy_reg_init); 3576 } 3577 3578 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) 3579 { 3580 static const struct phy_reg phy_reg_init[] = { 3581 { 0x1f, 0x0005 }, 3582 { 0x1a, 0x0000 }, 3583 { 0x1f, 0x0000 }, 3584 3585 { 0x1f, 0x0004 }, 3586 { 0x1c, 0x0000 }, 3587 { 0x1f, 0x0000 }, 3588 3589 { 0x1f, 0x0001 }, 3590 { 0x15, 0x7701 }, 3591 { 0x1f, 0x0000 } 3592 }; 3593 3594 /* Disable ALDPS before ram code */ 3595 rtl_writephy(tp, 0x1f, 0x0000); 3596 rtl_writephy(tp, 0x18, 0x0310); 3597 msleep(100); 3598 3599 rtl_apply_firmware(tp); 3600 3601 rtl_writephy_batch(tp, phy_reg_init); 3602 } 3603 3604 static void rtl8402_hw_phy_config(struct rtl8169_private *tp) 3605 { 3606 /* Disable ALDPS before setting firmware */ 3607 rtl_writephy(tp, 0x1f, 0x0000); 3608 rtl_writephy(tp, 0x18, 0x0310); 3609 msleep(20); 3610 3611 rtl_apply_firmware(tp); 3612 3613 /* EEE setting */ 3614 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3615 rtl_writephy(tp, 0x1f, 0x0004); 3616 rtl_writephy(tp, 0x10, 0x401f); 3617 rtl_writephy(tp, 0x19, 0x7030); 3618 rtl_writephy(tp, 0x1f, 0x0000); 3619 } 3620 3621 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) 3622 { 3623 static const struct phy_reg phy_reg_init[] = { 3624 { 0x1f, 0x0004 }, 3625 { 0x10, 0xc07f }, 3626 { 0x19, 0x7030 }, 3627 { 0x1f, 0x0000 } 3628 }; 3629 3630 /* Disable ALDPS before ram code */ 3631 rtl_writephy(tp, 0x1f, 0x0000); 3632 rtl_writephy(tp, 0x18, 0x0310); 3633 msleep(100); 3634 3635 rtl_apply_firmware(tp); 3636 3637 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3638 rtl_writephy_batch(tp, phy_reg_init); 3639 3640 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3641 } 3642 3643 static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp) 3644 { 3645 struct phy_device *phydev = tp->phydev; 3646 3647 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084); 3648 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3649 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006); 3650 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3651 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100); 3652 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000); 3653 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400); 3654 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff); 3655 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff); 3656 3657 phy_write(phydev, 0x1f, 0x0a43); 3658 phy_write(phydev, 0x13, 0x80ea); 3659 phy_modify(phydev, 0x14, 0xff00, 0xc400); 3660 phy_write(phydev, 0x13, 0x80eb); 3661 phy_modify(phydev, 0x14, 0x0700, 0x0300); 3662 phy_write(phydev, 0x13, 0x80f8); 3663 phy_modify(phydev, 0x14, 0xff00, 0x1c00); 3664 phy_write(phydev, 0x13, 0x80f1); 3665 phy_modify(phydev, 0x14, 0xff00, 0x3000); 3666 phy_write(phydev, 0x13, 0x80fe); 3667 phy_modify(phydev, 0x14, 0xff00, 0xa500); 3668 phy_write(phydev, 0x13, 0x8102); 3669 phy_modify(phydev, 0x14, 0xff00, 0x5000); 3670 phy_write(phydev, 0x13, 0x8105); 3671 phy_modify(phydev, 0x14, 0xff00, 0x3300); 3672 phy_write(phydev, 0x13, 0x8100); 3673 phy_modify(phydev, 0x14, 0xff00, 0x7000); 3674 phy_write(phydev, 0x13, 0x8104); 3675 phy_modify(phydev, 0x14, 0xff00, 0xf000); 3676 phy_write(phydev, 0x13, 0x8106); 3677 phy_modify(phydev, 0x14, 0xff00, 0x6500); 3678 phy_write(phydev, 0x13, 0x80dc); 3679 phy_modify(phydev, 0x14, 0xff00, 0xed00); 3680 phy_write(phydev, 0x13, 0x80df); 3681 phy_set_bits(phydev, 0x14, BIT(8)); 3682 phy_write(phydev, 0x13, 0x80e1); 3683 phy_clear_bits(phydev, 0x14, BIT(8)); 3684 phy_write(phydev, 0x1f, 0x0000); 3685 3686 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038); 3687 phy_write_paged(phydev, 0xa43, 0x13, 0x819f); 3688 phy_write_paged(phydev, 0xa43, 0x14, 0xd0b6); 3689 3690 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555); 3691 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00); 3692 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000); 3693 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3694 3695 rtl8125_config_eee_phy(tp); 3696 rtl_enable_eee(tp); 3697 } 3698 3699 static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp) 3700 { 3701 struct phy_device *phydev = tp->phydev; 3702 int i; 3703 3704 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3705 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 3706 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3707 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 3708 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 3709 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 3710 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 3711 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 3712 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 3713 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 3714 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 3715 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 3716 3717 phy_write(phydev, 0x1f, 0x0b87); 3718 phy_write(phydev, 0x16, 0x80a2); 3719 phy_write(phydev, 0x17, 0x0153); 3720 phy_write(phydev, 0x16, 0x809c); 3721 phy_write(phydev, 0x17, 0x0153); 3722 phy_write(phydev, 0x1f, 0x0000); 3723 3724 phy_write(phydev, 0x1f, 0x0a43); 3725 phy_write(phydev, 0x13, 0x81B3); 3726 phy_write(phydev, 0x14, 0x0043); 3727 phy_write(phydev, 0x14, 0x00A7); 3728 phy_write(phydev, 0x14, 0x00D6); 3729 phy_write(phydev, 0x14, 0x00EC); 3730 phy_write(phydev, 0x14, 0x00F6); 3731 phy_write(phydev, 0x14, 0x00FB); 3732 phy_write(phydev, 0x14, 0x00FD); 3733 phy_write(phydev, 0x14, 0x00FF); 3734 phy_write(phydev, 0x14, 0x00BB); 3735 phy_write(phydev, 0x14, 0x0058); 3736 phy_write(phydev, 0x14, 0x0029); 3737 phy_write(phydev, 0x14, 0x0013); 3738 phy_write(phydev, 0x14, 0x0009); 3739 phy_write(phydev, 0x14, 0x0004); 3740 phy_write(phydev, 0x14, 0x0002); 3741 for (i = 0; i < 25; i++) 3742 phy_write(phydev, 0x14, 0x0000); 3743 3744 phy_write(phydev, 0x13, 0x8257); 3745 phy_write(phydev, 0x14, 0x020F); 3746 3747 phy_write(phydev, 0x13, 0x80EA); 3748 phy_write(phydev, 0x14, 0x7843); 3749 phy_write(phydev, 0x1f, 0x0000); 3750 3751 rtl_apply_firmware(tp); 3752 3753 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 3754 3755 phy_write(phydev, 0x1f, 0x0a43); 3756 phy_write(phydev, 0x13, 0x81a2); 3757 phy_set_bits(phydev, 0x14, BIT(8)); 3758 phy_write(phydev, 0x1f, 0x0000); 3759 3760 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 3761 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 3762 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 3763 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 3764 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 3765 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3766 3767 rtl8125_config_eee_phy(tp); 3768 rtl_enable_eee(tp); 3769 } 3770 3771 static void rtl_hw_phy_config(struct net_device *dev) 3772 { 3773 static const rtl_generic_fct phy_configs[] = { 3774 /* PCI devices. */ 3775 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 3776 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 3777 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 3778 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 3779 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 3780 /* PCI-E devices. */ 3781 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 3782 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 3783 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 3784 [RTL_GIGA_MAC_VER_10] = NULL, 3785 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 3786 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 3787 [RTL_GIGA_MAC_VER_13] = NULL, 3788 [RTL_GIGA_MAC_VER_14] = NULL, 3789 [RTL_GIGA_MAC_VER_15] = NULL, 3790 [RTL_GIGA_MAC_VER_16] = NULL, 3791 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 3792 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 3793 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 3794 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 3795 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 3796 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config, 3797 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 3798 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 3799 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 3800 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 3801 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 3802 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 3803 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 3804 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 3805 [RTL_GIGA_MAC_VER_31] = NULL, 3806 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 3807 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 3808 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 3809 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 3810 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 3811 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 3812 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 3813 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 3814 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 3815 [RTL_GIGA_MAC_VER_41] = NULL, 3816 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 3817 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 3818 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 3819 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 3820 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 3821 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 3822 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 3823 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 3824 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 3825 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 3826 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config, 3827 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config, 3828 }; 3829 struct rtl8169_private *tp = netdev_priv(dev); 3830 3831 if (phy_configs[tp->mac_version]) 3832 phy_configs[tp->mac_version](tp); 3833 } 3834 3835 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 3836 { 3837 if (!test_and_set_bit(flag, tp->wk.flags)) 3838 schedule_work(&tp->wk.work); 3839 } 3840 3841 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 3842 { 3843 rtl_hw_phy_config(dev); 3844 3845 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 3846 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 3847 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 3848 netif_dbg(tp, drv, dev, 3849 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 3850 RTL_W8(tp, 0x82, 0x01); 3851 } 3852 3853 /* We may have called phy_speed_down before */ 3854 phy_speed_up(tp->phydev); 3855 3856 genphy_soft_reset(tp->phydev); 3857 } 3858 3859 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 3860 { 3861 rtl_lock_work(tp); 3862 3863 rtl_unlock_config_regs(tp); 3864 3865 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 3866 RTL_R32(tp, MAC4); 3867 3868 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3869 RTL_R32(tp, MAC0); 3870 3871 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 3872 rtl_rar_exgmac_set(tp, addr); 3873 3874 rtl_lock_config_regs(tp); 3875 3876 rtl_unlock_work(tp); 3877 } 3878 3879 static int rtl_set_mac_address(struct net_device *dev, void *p) 3880 { 3881 struct rtl8169_private *tp = netdev_priv(dev); 3882 struct device *d = tp_to_dev(tp); 3883 int ret; 3884 3885 ret = eth_mac_addr(dev, p); 3886 if (ret) 3887 return ret; 3888 3889 pm_runtime_get_noresume(d); 3890 3891 if (pm_runtime_active(d)) 3892 rtl_rar_set(tp, dev->dev_addr); 3893 3894 pm_runtime_put_noidle(d); 3895 3896 return 0; 3897 } 3898 3899 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3900 { 3901 struct rtl8169_private *tp = netdev_priv(dev); 3902 3903 if (!netif_running(dev)) 3904 return -ENODEV; 3905 3906 return phy_mii_ioctl(tp->phydev, ifr, cmd); 3907 } 3908 3909 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 3910 { 3911 switch (tp->mac_version) { 3912 case RTL_GIGA_MAC_VER_25: 3913 case RTL_GIGA_MAC_VER_26: 3914 case RTL_GIGA_MAC_VER_29: 3915 case RTL_GIGA_MAC_VER_30: 3916 case RTL_GIGA_MAC_VER_32: 3917 case RTL_GIGA_MAC_VER_33: 3918 case RTL_GIGA_MAC_VER_34: 3919 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51: 3920 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 3921 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 3922 break; 3923 default: 3924 break; 3925 } 3926 } 3927 3928 static void rtl_pll_power_down(struct rtl8169_private *tp) 3929 { 3930 if (r8168_check_dash(tp)) 3931 return; 3932 3933 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 3934 tp->mac_version == RTL_GIGA_MAC_VER_33) 3935 rtl_ephy_write(tp, 0x19, 0xff64); 3936 3937 if (device_may_wakeup(tp_to_dev(tp))) { 3938 phy_speed_down(tp->phydev, false); 3939 rtl_wol_suspend_quirk(tp); 3940 return; 3941 } 3942 3943 switch (tp->mac_version) { 3944 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3945 case RTL_GIGA_MAC_VER_37: 3946 case RTL_GIGA_MAC_VER_39: 3947 case RTL_GIGA_MAC_VER_43: 3948 case RTL_GIGA_MAC_VER_44: 3949 case RTL_GIGA_MAC_VER_45: 3950 case RTL_GIGA_MAC_VER_46: 3951 case RTL_GIGA_MAC_VER_47: 3952 case RTL_GIGA_MAC_VER_48: 3953 case RTL_GIGA_MAC_VER_50: 3954 case RTL_GIGA_MAC_VER_51: 3955 case RTL_GIGA_MAC_VER_60: 3956 case RTL_GIGA_MAC_VER_61: 3957 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3958 break; 3959 case RTL_GIGA_MAC_VER_40: 3960 case RTL_GIGA_MAC_VER_41: 3961 case RTL_GIGA_MAC_VER_49: 3962 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3963 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3964 break; 3965 default: 3966 break; 3967 } 3968 } 3969 3970 static void rtl_pll_power_up(struct rtl8169_private *tp) 3971 { 3972 switch (tp->mac_version) { 3973 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3974 case RTL_GIGA_MAC_VER_37: 3975 case RTL_GIGA_MAC_VER_39: 3976 case RTL_GIGA_MAC_VER_43: 3977 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 3978 break; 3979 case RTL_GIGA_MAC_VER_44: 3980 case RTL_GIGA_MAC_VER_45: 3981 case RTL_GIGA_MAC_VER_46: 3982 case RTL_GIGA_MAC_VER_47: 3983 case RTL_GIGA_MAC_VER_48: 3984 case RTL_GIGA_MAC_VER_50: 3985 case RTL_GIGA_MAC_VER_51: 3986 case RTL_GIGA_MAC_VER_60: 3987 case RTL_GIGA_MAC_VER_61: 3988 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3989 break; 3990 case RTL_GIGA_MAC_VER_40: 3991 case RTL_GIGA_MAC_VER_41: 3992 case RTL_GIGA_MAC_VER_49: 3993 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3994 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3995 break; 3996 default: 3997 break; 3998 } 3999 4000 phy_resume(tp->phydev); 4001 /* give MAC/PHY some time to resume */ 4002 msleep(20); 4003 } 4004 4005 static void rtl_init_rxcfg(struct rtl8169_private *tp) 4006 { 4007 switch (tp->mac_version) { 4008 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4009 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4010 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 4011 break; 4012 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 4013 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 4014 case RTL_GIGA_MAC_VER_38: 4015 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 4016 break; 4017 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 4018 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 4019 break; 4020 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 4021 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 | 4022 RX_DMA_BURST); 4023 break; 4024 default: 4025 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 4026 break; 4027 } 4028 } 4029 4030 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 4031 { 4032 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 4033 } 4034 4035 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 4036 { 4037 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4038 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 4039 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); 4040 } 4041 4042 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 4043 { 4044 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4045 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 4046 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4047 } 4048 4049 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 4050 { 4051 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4052 } 4053 4054 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 4055 { 4056 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4057 } 4058 4059 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 4060 { 4061 RTL_W8(tp, MaxTxPacketSize, 0x3f); 4062 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4063 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 4064 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); 4065 } 4066 4067 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 4068 { 4069 RTL_W8(tp, MaxTxPacketSize, 0x0c); 4070 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4071 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 4072 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4073 } 4074 4075 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) 4076 { 4077 rtl_tx_performance_tweak(tp, 4078 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN); 4079 } 4080 4081 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) 4082 { 4083 rtl_tx_performance_tweak(tp, 4084 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN); 4085 } 4086 4087 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 4088 { 4089 r8168b_0_hw_jumbo_enable(tp); 4090 4091 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 4092 } 4093 4094 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 4095 { 4096 r8168b_0_hw_jumbo_disable(tp); 4097 4098 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 4099 } 4100 4101 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) 4102 { 4103 rtl_unlock_config_regs(tp); 4104 switch (tp->mac_version) { 4105 case RTL_GIGA_MAC_VER_11: 4106 r8168b_0_hw_jumbo_enable(tp); 4107 break; 4108 case RTL_GIGA_MAC_VER_12: 4109 case RTL_GIGA_MAC_VER_17: 4110 r8168b_1_hw_jumbo_enable(tp); 4111 break; 4112 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 4113 r8168c_hw_jumbo_enable(tp); 4114 break; 4115 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 4116 r8168dp_hw_jumbo_enable(tp); 4117 break; 4118 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4119 r8168e_hw_jumbo_enable(tp); 4120 break; 4121 default: 4122 break; 4123 } 4124 rtl_lock_config_regs(tp); 4125 } 4126 4127 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) 4128 { 4129 rtl_unlock_config_regs(tp); 4130 switch (tp->mac_version) { 4131 case RTL_GIGA_MAC_VER_11: 4132 r8168b_0_hw_jumbo_disable(tp); 4133 break; 4134 case RTL_GIGA_MAC_VER_12: 4135 case RTL_GIGA_MAC_VER_17: 4136 r8168b_1_hw_jumbo_disable(tp); 4137 break; 4138 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 4139 r8168c_hw_jumbo_disable(tp); 4140 break; 4141 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 4142 r8168dp_hw_jumbo_disable(tp); 4143 break; 4144 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4145 r8168e_hw_jumbo_disable(tp); 4146 break; 4147 default: 4148 break; 4149 } 4150 rtl_lock_config_regs(tp); 4151 } 4152 4153 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu) 4154 { 4155 if (mtu > ETH_DATA_LEN) 4156 rtl_hw_jumbo_enable(tp); 4157 else 4158 rtl_hw_jumbo_disable(tp); 4159 } 4160 4161 DECLARE_RTL_COND(rtl_chipcmd_cond) 4162 { 4163 return RTL_R8(tp, ChipCmd) & CmdReset; 4164 } 4165 4166 static void rtl_hw_reset(struct rtl8169_private *tp) 4167 { 4168 RTL_W8(tp, ChipCmd, CmdReset); 4169 4170 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 4171 } 4172 4173 static void rtl_request_firmware(struct rtl8169_private *tp) 4174 { 4175 struct rtl_fw *rtl_fw; 4176 4177 /* firmware loaded already or no firmware available */ 4178 if (tp->rtl_fw || !tp->fw_name) 4179 return; 4180 4181 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 4182 if (!rtl_fw) { 4183 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 4184 return; 4185 } 4186 4187 rtl_fw->phy_write = rtl_writephy; 4188 rtl_fw->phy_read = rtl_readphy; 4189 rtl_fw->mac_mcu_write = mac_mcu_write; 4190 rtl_fw->mac_mcu_read = mac_mcu_read; 4191 rtl_fw->fw_name = tp->fw_name; 4192 rtl_fw->dev = tp_to_dev(tp); 4193 4194 if (rtl_fw_request_firmware(rtl_fw)) 4195 kfree(rtl_fw); 4196 else 4197 tp->rtl_fw = rtl_fw; 4198 } 4199 4200 static void rtl_rx_close(struct rtl8169_private *tp) 4201 { 4202 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 4203 } 4204 4205 DECLARE_RTL_COND(rtl_npq_cond) 4206 { 4207 return RTL_R8(tp, TxPoll) & NPQ; 4208 } 4209 4210 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 4211 { 4212 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 4213 } 4214 4215 static void rtl8169_hw_reset(struct rtl8169_private *tp) 4216 { 4217 /* Disable interrupts */ 4218 rtl8169_irq_mask_and_ack(tp); 4219 4220 rtl_rx_close(tp); 4221 4222 switch (tp->mac_version) { 4223 case RTL_GIGA_MAC_VER_27: 4224 case RTL_GIGA_MAC_VER_28: 4225 case RTL_GIGA_MAC_VER_31: 4226 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 4227 break; 4228 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4229 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 4230 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4231 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4232 break; 4233 default: 4234 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4235 udelay(100); 4236 break; 4237 } 4238 4239 rtl_hw_reset(tp); 4240 } 4241 4242 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 4243 { 4244 u32 val = TX_DMA_BURST << TxDMAShift | 4245 InterFrameGap << TxInterFrameGapShift; 4246 4247 if (rtl_is_8168evl_up(tp)) 4248 val |= TXCFG_AUTO_FIFO; 4249 4250 RTL_W32(tp, TxConfig, val); 4251 } 4252 4253 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 4254 { 4255 /* Low hurts. Let's disable the filtering. */ 4256 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 4257 } 4258 4259 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 4260 { 4261 /* 4262 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 4263 * register to be written before TxDescAddrLow to work. 4264 * Switching from MMIO to I/O access fixes the issue as well. 4265 */ 4266 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 4267 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 4268 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 4269 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 4270 } 4271 4272 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 4273 { 4274 u32 val; 4275 4276 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 4277 val = 0x000fff00; 4278 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 4279 val = 0x00ffff00; 4280 else 4281 return; 4282 4283 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 4284 val |= 0xff; 4285 4286 RTL_W32(tp, 0x7c, val); 4287 } 4288 4289 static void rtl_set_rx_mode(struct net_device *dev) 4290 { 4291 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 4292 /* Multicast hash filter */ 4293 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 4294 struct rtl8169_private *tp = netdev_priv(dev); 4295 u32 tmp; 4296 4297 if (dev->flags & IFF_PROMISC) { 4298 /* Unconditionally log net taps. */ 4299 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 4300 rx_mode |= AcceptAllPhys; 4301 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 4302 dev->flags & IFF_ALLMULTI || 4303 tp->mac_version == RTL_GIGA_MAC_VER_35) { 4304 /* accept all multicasts */ 4305 } else if (netdev_mc_empty(dev)) { 4306 rx_mode &= ~AcceptMulticast; 4307 } else { 4308 struct netdev_hw_addr *ha; 4309 4310 mc_filter[1] = mc_filter[0] = 0; 4311 netdev_for_each_mc_addr(ha, dev) { 4312 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 4313 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 4314 } 4315 4316 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 4317 tmp = mc_filter[0]; 4318 mc_filter[0] = swab32(mc_filter[1]); 4319 mc_filter[1] = swab32(tmp); 4320 } 4321 } 4322 4323 if (dev->features & NETIF_F_RXALL) 4324 rx_mode |= (AcceptErr | AcceptRunt); 4325 4326 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 4327 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 4328 4329 tmp = RTL_R32(tp, RxConfig); 4330 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); 4331 } 4332 4333 DECLARE_RTL_COND(rtl_csiar_cond) 4334 { 4335 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 4336 } 4337 4338 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 4339 { 4340 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4341 4342 RTL_W32(tp, CSIDR, value); 4343 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 4344 CSIAR_BYTE_ENABLE | func << 16); 4345 4346 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 4347 } 4348 4349 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 4350 { 4351 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4352 4353 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 4354 CSIAR_BYTE_ENABLE); 4355 4356 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 4357 RTL_R32(tp, CSIDR) : ~0; 4358 } 4359 4360 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 4361 { 4362 struct pci_dev *pdev = tp->pci_dev; 4363 u32 csi; 4364 4365 /* According to Realtek the value at config space address 0x070f 4366 * controls the L0s/L1 entrance latency. We try standard ECAM access 4367 * first and if it fails fall back to CSI. 4368 */ 4369 if (pdev->cfg_size > 0x070f && 4370 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 4371 return; 4372 4373 netdev_notice_once(tp->dev, 4374 "No native access to PCI extended config space, falling back to CSI\n"); 4375 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 4376 rtl_csi_write(tp, 0x070c, csi | val << 24); 4377 } 4378 4379 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 4380 { 4381 rtl_csi_access_enable(tp, 0x27); 4382 } 4383 4384 struct ephy_info { 4385 unsigned int offset; 4386 u16 mask; 4387 u16 bits; 4388 }; 4389 4390 static void __rtl_ephy_init(struct rtl8169_private *tp, 4391 const struct ephy_info *e, int len) 4392 { 4393 u16 w; 4394 4395 while (len-- > 0) { 4396 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 4397 rtl_ephy_write(tp, e->offset, w); 4398 e++; 4399 } 4400 } 4401 4402 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 4403 4404 static void rtl_disable_clock_request(struct rtl8169_private *tp) 4405 { 4406 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 4407 PCI_EXP_LNKCTL_CLKREQ_EN); 4408 } 4409 4410 static void rtl_enable_clock_request(struct rtl8169_private *tp) 4411 { 4412 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 4413 PCI_EXP_LNKCTL_CLKREQ_EN); 4414 } 4415 4416 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 4417 { 4418 /* work around an issue when PCI reset occurs during L2/L3 state */ 4419 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 4420 } 4421 4422 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 4423 { 4424 /* Don't enable ASPM in the chip if OS can't control ASPM */ 4425 if (enable && tp->aspm_manageable) { 4426 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 4427 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 4428 } else { 4429 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4430 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4431 } 4432 4433 udelay(10); 4434 } 4435 4436 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 4437 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 4438 { 4439 /* Usage of dynamic vs. static FIFO is controlled by bit 4440 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 4441 */ 4442 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 4443 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 4444 } 4445 4446 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 4447 u8 low, u8 high) 4448 { 4449 /* FIFO thresholds for pause flow control */ 4450 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 4451 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 4452 } 4453 4454 static void rtl_hw_start_8168bb(struct rtl8169_private *tp) 4455 { 4456 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4457 } 4458 4459 static void rtl_hw_start_8168bef(struct rtl8169_private *tp) 4460 { 4461 rtl_hw_start_8168bb(tp); 4462 4463 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 4464 } 4465 4466 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 4467 { 4468 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 4469 4470 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4471 4472 rtl_disable_clock_request(tp); 4473 } 4474 4475 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 4476 { 4477 static const struct ephy_info e_info_8168cp[] = { 4478 { 0x01, 0, 0x0001 }, 4479 { 0x02, 0x0800, 0x1000 }, 4480 { 0x03, 0, 0x0042 }, 4481 { 0x06, 0x0080, 0x0000 }, 4482 { 0x07, 0, 0x2000 } 4483 }; 4484 4485 rtl_set_def_aspm_entry_latency(tp); 4486 4487 rtl_ephy_init(tp, e_info_8168cp); 4488 4489 __rtl_hw_start_8168cp(tp); 4490 } 4491 4492 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 4493 { 4494 rtl_set_def_aspm_entry_latency(tp); 4495 4496 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4497 } 4498 4499 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 4500 { 4501 rtl_set_def_aspm_entry_latency(tp); 4502 4503 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4504 4505 /* Magic. */ 4506 RTL_W8(tp, DBG_REG, 0x20); 4507 } 4508 4509 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 4510 { 4511 static const struct ephy_info e_info_8168c_1[] = { 4512 { 0x02, 0x0800, 0x1000 }, 4513 { 0x03, 0, 0x0002 }, 4514 { 0x06, 0x0080, 0x0000 } 4515 }; 4516 4517 rtl_set_def_aspm_entry_latency(tp); 4518 4519 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 4520 4521 rtl_ephy_init(tp, e_info_8168c_1); 4522 4523 __rtl_hw_start_8168cp(tp); 4524 } 4525 4526 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 4527 { 4528 static const struct ephy_info e_info_8168c_2[] = { 4529 { 0x01, 0, 0x0001 }, 4530 { 0x03, 0x0400, 0x0020 } 4531 }; 4532 4533 rtl_set_def_aspm_entry_latency(tp); 4534 4535 rtl_ephy_init(tp, e_info_8168c_2); 4536 4537 __rtl_hw_start_8168cp(tp); 4538 } 4539 4540 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 4541 { 4542 rtl_hw_start_8168c_2(tp); 4543 } 4544 4545 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 4546 { 4547 rtl_set_def_aspm_entry_latency(tp); 4548 4549 __rtl_hw_start_8168cp(tp); 4550 } 4551 4552 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 4553 { 4554 rtl_set_def_aspm_entry_latency(tp); 4555 4556 rtl_disable_clock_request(tp); 4557 4558 if (tp->dev->mtu <= ETH_DATA_LEN) 4559 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4560 } 4561 4562 static void rtl_hw_start_8168dp(struct rtl8169_private *tp) 4563 { 4564 rtl_set_def_aspm_entry_latency(tp); 4565 4566 if (tp->dev->mtu <= ETH_DATA_LEN) 4567 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4568 4569 rtl_disable_clock_request(tp); 4570 } 4571 4572 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 4573 { 4574 static const struct ephy_info e_info_8168d_4[] = { 4575 { 0x0b, 0x0000, 0x0048 }, 4576 { 0x19, 0x0020, 0x0050 }, 4577 { 0x0c, 0x0100, 0x0020 }, 4578 { 0x10, 0x0004, 0x0000 }, 4579 }; 4580 4581 rtl_set_def_aspm_entry_latency(tp); 4582 4583 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4584 4585 rtl_ephy_init(tp, e_info_8168d_4); 4586 4587 rtl_enable_clock_request(tp); 4588 } 4589 4590 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 4591 { 4592 static const struct ephy_info e_info_8168e_1[] = { 4593 { 0x00, 0x0200, 0x0100 }, 4594 { 0x00, 0x0000, 0x0004 }, 4595 { 0x06, 0x0002, 0x0001 }, 4596 { 0x06, 0x0000, 0x0030 }, 4597 { 0x07, 0x0000, 0x2000 }, 4598 { 0x00, 0x0000, 0x0020 }, 4599 { 0x03, 0x5800, 0x2000 }, 4600 { 0x03, 0x0000, 0x0001 }, 4601 { 0x01, 0x0800, 0x1000 }, 4602 { 0x07, 0x0000, 0x4000 }, 4603 { 0x1e, 0x0000, 0x2000 }, 4604 { 0x19, 0xffff, 0xfe6c }, 4605 { 0x0a, 0x0000, 0x0040 } 4606 }; 4607 4608 rtl_set_def_aspm_entry_latency(tp); 4609 4610 rtl_ephy_init(tp, e_info_8168e_1); 4611 4612 rtl_disable_clock_request(tp); 4613 4614 /* Reset tx FIFO pointer */ 4615 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 4616 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 4617 4618 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4619 } 4620 4621 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 4622 { 4623 static const struct ephy_info e_info_8168e_2[] = { 4624 { 0x09, 0x0000, 0x0080 }, 4625 { 0x19, 0x0000, 0x0224 }, 4626 { 0x00, 0x0000, 0x0004 }, 4627 { 0x0c, 0x3df0, 0x0200 }, 4628 }; 4629 4630 rtl_set_def_aspm_entry_latency(tp); 4631 4632 rtl_ephy_init(tp, e_info_8168e_2); 4633 4634 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4635 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4636 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4637 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4638 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 4639 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4640 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4641 4642 rtl_disable_clock_request(tp); 4643 4644 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4645 4646 rtl8168_config_eee_mac(tp); 4647 4648 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4649 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4650 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4651 4652 rtl_hw_aspm_clkreq_enable(tp, true); 4653 } 4654 4655 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 4656 { 4657 rtl_set_def_aspm_entry_latency(tp); 4658 4659 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4660 4661 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4662 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4663 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4664 rtl_reset_packet_filter(tp); 4665 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4666 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 4667 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4668 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 4669 4670 rtl_disable_clock_request(tp); 4671 4672 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4673 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4674 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4675 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4676 4677 rtl8168_config_eee_mac(tp); 4678 } 4679 4680 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 4681 { 4682 static const struct ephy_info e_info_8168f_1[] = { 4683 { 0x06, 0x00c0, 0x0020 }, 4684 { 0x08, 0x0001, 0x0002 }, 4685 { 0x09, 0x0000, 0x0080 }, 4686 { 0x19, 0x0000, 0x0224 }, 4687 { 0x00, 0x0000, 0x0004 }, 4688 { 0x0c, 0x3df0, 0x0200 }, 4689 }; 4690 4691 rtl_hw_start_8168f(tp); 4692 4693 rtl_ephy_init(tp, e_info_8168f_1); 4694 4695 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4696 } 4697 4698 static void rtl_hw_start_8411(struct rtl8169_private *tp) 4699 { 4700 static const struct ephy_info e_info_8168f_1[] = { 4701 { 0x06, 0x00c0, 0x0020 }, 4702 { 0x0f, 0xffff, 0x5200 }, 4703 { 0x19, 0x0000, 0x0224 }, 4704 { 0x00, 0x0000, 0x0004 }, 4705 { 0x0c, 0x3df0, 0x0200 }, 4706 }; 4707 4708 rtl_hw_start_8168f(tp); 4709 rtl_pcie_state_l2l3_disable(tp); 4710 4711 rtl_ephy_init(tp, e_info_8168f_1); 4712 4713 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 4714 } 4715 4716 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 4717 { 4718 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4719 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4720 4721 rtl_set_def_aspm_entry_latency(tp); 4722 4723 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4724 4725 rtl_reset_packet_filter(tp); 4726 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 4727 4728 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4729 4730 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4731 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4732 4733 rtl8168_config_eee_mac(tp); 4734 4735 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4736 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4737 4738 rtl_pcie_state_l2l3_disable(tp); 4739 } 4740 4741 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 4742 { 4743 static const struct ephy_info e_info_8168g_1[] = { 4744 { 0x00, 0x0008, 0x0000 }, 4745 { 0x0c, 0x3ff0, 0x0820 }, 4746 { 0x1e, 0x0000, 0x0001 }, 4747 { 0x19, 0x8000, 0x0000 } 4748 }; 4749 4750 rtl_hw_start_8168g(tp); 4751 4752 /* disable aspm and clock request before access ephy */ 4753 rtl_hw_aspm_clkreq_enable(tp, false); 4754 rtl_ephy_init(tp, e_info_8168g_1); 4755 rtl_hw_aspm_clkreq_enable(tp, true); 4756 } 4757 4758 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 4759 { 4760 static const struct ephy_info e_info_8168g_2[] = { 4761 { 0x00, 0x0008, 0x0000 }, 4762 { 0x0c, 0x3ff0, 0x0820 }, 4763 { 0x19, 0xffff, 0x7c00 }, 4764 { 0x1e, 0xffff, 0x20eb }, 4765 { 0x0d, 0xffff, 0x1666 }, 4766 { 0x00, 0xffff, 0x10a3 }, 4767 { 0x06, 0xffff, 0xf050 }, 4768 { 0x04, 0x0000, 0x0010 }, 4769 { 0x1d, 0x4000, 0x0000 }, 4770 }; 4771 4772 rtl_hw_start_8168g(tp); 4773 4774 /* disable aspm and clock request before access ephy */ 4775 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4776 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4777 rtl_ephy_init(tp, e_info_8168g_2); 4778 } 4779 4780 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 4781 { 4782 static const struct ephy_info e_info_8411_2[] = { 4783 { 0x00, 0x0008, 0x0000 }, 4784 { 0x0c, 0x37d0, 0x0820 }, 4785 { 0x1e, 0x0000, 0x0001 }, 4786 { 0x19, 0x8021, 0x0000 }, 4787 { 0x1e, 0x0000, 0x2000 }, 4788 { 0x0d, 0x0100, 0x0200 }, 4789 { 0x00, 0x0000, 0x0080 }, 4790 { 0x06, 0x0000, 0x0010 }, 4791 { 0x04, 0x0000, 0x0010 }, 4792 { 0x1d, 0x0000, 0x4000 }, 4793 }; 4794 4795 rtl_hw_start_8168g(tp); 4796 4797 /* disable aspm and clock request before access ephy */ 4798 rtl_hw_aspm_clkreq_enable(tp, false); 4799 rtl_ephy_init(tp, e_info_8411_2); 4800 4801 /* The following Realtek-provided magic fixes an issue with the RX unit 4802 * getting confused after the PHY having been powered-down. 4803 */ 4804 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 4805 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 4806 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 4807 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 4808 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 4809 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 4810 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 4811 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 4812 mdelay(3); 4813 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 4814 4815 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 4816 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 4817 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 4818 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 4819 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 4820 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 4821 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 4822 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 4823 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 4824 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 4825 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 4826 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 4827 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 4828 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 4829 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 4830 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 4831 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 4832 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 4833 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 4834 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 4835 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 4836 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 4837 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 4838 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 4839 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 4840 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 4841 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 4842 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 4843 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 4844 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 4845 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 4846 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 4847 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 4848 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 4849 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 4850 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 4851 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 4852 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 4853 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 4854 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 4855 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 4856 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 4857 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 4858 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 4859 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 4860 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 4861 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 4862 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 4863 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 4864 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 4865 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 4866 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 4867 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 4868 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 4869 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 4870 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 4871 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 4872 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 4873 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 4874 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 4875 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 4876 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 4877 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 4878 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 4879 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 4880 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 4881 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 4882 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 4883 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 4884 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 4885 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 4886 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 4887 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 4888 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 4889 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 4890 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 4891 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 4892 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 4893 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 4894 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 4895 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 4896 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 4897 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 4898 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 4899 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 4900 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 4901 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 4902 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 4903 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 4904 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 4905 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 4906 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 4907 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 4908 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 4909 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 4910 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 4911 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 4912 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 4913 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 4914 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 4915 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 4916 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 4917 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 4918 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 4919 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 4920 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 4921 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 4922 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 4923 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 4924 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 4925 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 4926 4927 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 4928 4929 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 4930 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 4931 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 4932 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 4933 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 4934 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 4935 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 4936 4937 rtl_hw_aspm_clkreq_enable(tp, true); 4938 } 4939 4940 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 4941 { 4942 static const struct ephy_info e_info_8168h_1[] = { 4943 { 0x1e, 0x0800, 0x0001 }, 4944 { 0x1d, 0x0000, 0x0800 }, 4945 { 0x05, 0xffff, 0x2089 }, 4946 { 0x06, 0xffff, 0x5881 }, 4947 { 0x04, 0xffff, 0x854a }, 4948 { 0x01, 0xffff, 0x068b } 4949 }; 4950 int rg_saw_cnt; 4951 4952 /* disable aspm and clock request before access ephy */ 4953 rtl_hw_aspm_clkreq_enable(tp, false); 4954 rtl_ephy_init(tp, e_info_8168h_1); 4955 4956 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4957 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4958 4959 rtl_set_def_aspm_entry_latency(tp); 4960 4961 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4962 4963 rtl_reset_packet_filter(tp); 4964 4965 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 4966 4967 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 4968 4969 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4970 4971 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4972 4973 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4974 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4975 4976 rtl8168_config_eee_mac(tp); 4977 4978 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4979 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4980 4981 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4982 4983 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4984 4985 rtl_pcie_state_l2l3_disable(tp); 4986 4987 rtl_writephy(tp, 0x1f, 0x0c42); 4988 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff); 4989 rtl_writephy(tp, 0x1f, 0x0000); 4990 if (rg_saw_cnt > 0) { 4991 u16 sw_cnt_1ms_ini; 4992 4993 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 4994 sw_cnt_1ms_ini &= 0x0fff; 4995 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 4996 } 4997 4998 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 4999 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 5000 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 5001 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 5002 5003 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 5004 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 5005 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 5006 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 5007 5008 rtl_hw_aspm_clkreq_enable(tp, true); 5009 } 5010 5011 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 5012 { 5013 rtl8168ep_stop_cmac(tp); 5014 5015 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 5016 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 5017 5018 rtl_set_def_aspm_entry_latency(tp); 5019 5020 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5021 5022 rtl_reset_packet_filter(tp); 5023 5024 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 5025 5026 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 5027 5028 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 5029 5030 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 5031 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 5032 5033 rtl8168_config_eee_mac(tp); 5034 5035 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 5036 5037 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 5038 5039 rtl_pcie_state_l2l3_disable(tp); 5040 } 5041 5042 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 5043 { 5044 static const struct ephy_info e_info_8168ep_1[] = { 5045 { 0x00, 0xffff, 0x10ab }, 5046 { 0x06, 0xffff, 0xf030 }, 5047 { 0x08, 0xffff, 0x2006 }, 5048 { 0x0d, 0xffff, 0x1666 }, 5049 { 0x0c, 0x3ff0, 0x0000 } 5050 }; 5051 5052 /* disable aspm and clock request before access ephy */ 5053 rtl_hw_aspm_clkreq_enable(tp, false); 5054 rtl_ephy_init(tp, e_info_8168ep_1); 5055 5056 rtl_hw_start_8168ep(tp); 5057 5058 rtl_hw_aspm_clkreq_enable(tp, true); 5059 } 5060 5061 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 5062 { 5063 static const struct ephy_info e_info_8168ep_2[] = { 5064 { 0x00, 0xffff, 0x10a3 }, 5065 { 0x19, 0xffff, 0xfc00 }, 5066 { 0x1e, 0xffff, 0x20ea } 5067 }; 5068 5069 /* disable aspm and clock request before access ephy */ 5070 rtl_hw_aspm_clkreq_enable(tp, false); 5071 rtl_ephy_init(tp, e_info_8168ep_2); 5072 5073 rtl_hw_start_8168ep(tp); 5074 5075 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5076 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 5077 5078 rtl_hw_aspm_clkreq_enable(tp, true); 5079 } 5080 5081 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 5082 { 5083 static const struct ephy_info e_info_8168ep_3[] = { 5084 { 0x00, 0x0000, 0x0080 }, 5085 { 0x0d, 0x0100, 0x0200 }, 5086 { 0x19, 0x8021, 0x0000 }, 5087 { 0x1e, 0x0000, 0x2000 }, 5088 }; 5089 5090 /* disable aspm and clock request before access ephy */ 5091 rtl_hw_aspm_clkreq_enable(tp, false); 5092 rtl_ephy_init(tp, e_info_8168ep_3); 5093 5094 rtl_hw_start_8168ep(tp); 5095 5096 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5097 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 5098 5099 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 5100 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5101 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5102 5103 rtl_hw_aspm_clkreq_enable(tp, true); 5104 } 5105 5106 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 5107 { 5108 static const struct ephy_info e_info_8102e_1[] = { 5109 { 0x01, 0, 0x6e65 }, 5110 { 0x02, 0, 0x091f }, 5111 { 0x03, 0, 0xc2f9 }, 5112 { 0x06, 0, 0xafb5 }, 5113 { 0x07, 0, 0x0e00 }, 5114 { 0x19, 0, 0xec80 }, 5115 { 0x01, 0, 0x2e65 }, 5116 { 0x01, 0, 0x6e65 } 5117 }; 5118 u8 cfg1; 5119 5120 rtl_set_def_aspm_entry_latency(tp); 5121 5122 RTL_W8(tp, DBG_REG, FIX_NAK_1); 5123 5124 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5125 5126 RTL_W8(tp, Config1, 5127 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 5128 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5129 5130 cfg1 = RTL_R8(tp, Config1); 5131 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 5132 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 5133 5134 rtl_ephy_init(tp, e_info_8102e_1); 5135 } 5136 5137 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 5138 { 5139 rtl_set_def_aspm_entry_latency(tp); 5140 5141 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5142 5143 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 5144 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5145 } 5146 5147 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 5148 { 5149 rtl_hw_start_8102e_2(tp); 5150 5151 rtl_ephy_write(tp, 0x03, 0xc2f9); 5152 } 5153 5154 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 5155 { 5156 static const struct ephy_info e_info_8105e_1[] = { 5157 { 0x07, 0, 0x4000 }, 5158 { 0x19, 0, 0x0200 }, 5159 { 0x19, 0, 0x0020 }, 5160 { 0x1e, 0, 0x2000 }, 5161 { 0x03, 0, 0x0001 }, 5162 { 0x19, 0, 0x0100 }, 5163 { 0x19, 0, 0x0004 }, 5164 { 0x0a, 0, 0x0020 } 5165 }; 5166 5167 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5168 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5169 5170 /* Disable Early Tally Counter */ 5171 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 5172 5173 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5174 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 5175 5176 rtl_ephy_init(tp, e_info_8105e_1); 5177 5178 rtl_pcie_state_l2l3_disable(tp); 5179 } 5180 5181 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 5182 { 5183 rtl_hw_start_8105e_1(tp); 5184 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 5185 } 5186 5187 static void rtl_hw_start_8402(struct rtl8169_private *tp) 5188 { 5189 static const struct ephy_info e_info_8402[] = { 5190 { 0x19, 0xffff, 0xff64 }, 5191 { 0x1e, 0, 0x4000 } 5192 }; 5193 5194 rtl_set_def_aspm_entry_latency(tp); 5195 5196 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5197 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5198 5199 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5200 5201 rtl_ephy_init(tp, e_info_8402); 5202 5203 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5204 5205 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 5206 rtl_reset_packet_filter(tp); 5207 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 5208 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 5209 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 5210 5211 rtl_pcie_state_l2l3_disable(tp); 5212 } 5213 5214 static void rtl_hw_start_8106(struct rtl8169_private *tp) 5215 { 5216 rtl_hw_aspm_clkreq_enable(tp, false); 5217 5218 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5219 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5220 5221 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 5222 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5223 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5224 5225 rtl_pcie_state_l2l3_disable(tp); 5226 rtl_hw_aspm_clkreq_enable(tp, true); 5227 } 5228 5229 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 5230 { 5231 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 5232 } 5233 5234 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 5235 { 5236 rtl_pcie_state_l2l3_disable(tp); 5237 5238 RTL_W16(tp, 0x382, 0x221b); 5239 RTL_W8(tp, 0x4500, 0); 5240 RTL_W16(tp, 0x4800, 0); 5241 5242 /* disable UPS */ 5243 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 5244 5245 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 5246 5247 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 5248 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 5249 5250 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 5251 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5252 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5253 5254 /* disable new tx descriptor format */ 5255 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 5256 5257 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 5258 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 5259 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 5260 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 5261 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 5262 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 5263 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 5264 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 5265 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 5266 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 5267 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 5268 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 5269 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 5270 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 5271 udelay(1); 5272 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 5273 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 5274 5275 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 5276 5277 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 5278 5279 rtl8125_config_eee_mac(tp); 5280 5281 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 5282 udelay(10); 5283 } 5284 5285 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 5286 { 5287 static const struct ephy_info e_info_8125_1[] = { 5288 { 0x01, 0xffff, 0xa812 }, 5289 { 0x09, 0xffff, 0x520c }, 5290 { 0x04, 0xffff, 0xd000 }, 5291 { 0x0d, 0xffff, 0xf702 }, 5292 { 0x0a, 0xffff, 0x8653 }, 5293 { 0x06, 0xffff, 0x001e }, 5294 { 0x08, 0xffff, 0x3595 }, 5295 { 0x20, 0xffff, 0x9455 }, 5296 { 0x21, 0xffff, 0x99ff }, 5297 { 0x02, 0xffff, 0x6046 }, 5298 { 0x29, 0xffff, 0xfe00 }, 5299 { 0x23, 0xffff, 0xab62 }, 5300 5301 { 0x41, 0xffff, 0xa80c }, 5302 { 0x49, 0xffff, 0x520c }, 5303 { 0x44, 0xffff, 0xd000 }, 5304 { 0x4d, 0xffff, 0xf702 }, 5305 { 0x4a, 0xffff, 0x8653 }, 5306 { 0x46, 0xffff, 0x001e }, 5307 { 0x48, 0xffff, 0x3595 }, 5308 { 0x60, 0xffff, 0x9455 }, 5309 { 0x61, 0xffff, 0x99ff }, 5310 { 0x42, 0xffff, 0x6046 }, 5311 { 0x69, 0xffff, 0xfe00 }, 5312 { 0x63, 0xffff, 0xab62 }, 5313 }; 5314 5315 rtl_set_def_aspm_entry_latency(tp); 5316 5317 /* disable aspm and clock request before access ephy */ 5318 rtl_hw_aspm_clkreq_enable(tp, false); 5319 rtl_ephy_init(tp, e_info_8125_1); 5320 5321 rtl_hw_start_8125_common(tp); 5322 } 5323 5324 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 5325 { 5326 static const struct ephy_info e_info_8125_2[] = { 5327 { 0x04, 0xffff, 0xd000 }, 5328 { 0x0a, 0xffff, 0x8653 }, 5329 { 0x23, 0xffff, 0xab66 }, 5330 { 0x20, 0xffff, 0x9455 }, 5331 { 0x21, 0xffff, 0x99ff }, 5332 { 0x29, 0xffff, 0xfe04 }, 5333 5334 { 0x44, 0xffff, 0xd000 }, 5335 { 0x4a, 0xffff, 0x8653 }, 5336 { 0x63, 0xffff, 0xab66 }, 5337 { 0x60, 0xffff, 0x9455 }, 5338 { 0x61, 0xffff, 0x99ff }, 5339 { 0x69, 0xffff, 0xfe04 }, 5340 }; 5341 5342 rtl_set_def_aspm_entry_latency(tp); 5343 5344 /* disable aspm and clock request before access ephy */ 5345 rtl_hw_aspm_clkreq_enable(tp, false); 5346 rtl_ephy_init(tp, e_info_8125_2); 5347 5348 rtl_hw_start_8125_common(tp); 5349 } 5350 5351 static void rtl_hw_config(struct rtl8169_private *tp) 5352 { 5353 static const rtl_generic_fct hw_configs[] = { 5354 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 5355 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 5356 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 5357 [RTL_GIGA_MAC_VER_10] = NULL, 5358 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb, 5359 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef, 5360 [RTL_GIGA_MAC_VER_13] = NULL, 5361 [RTL_GIGA_MAC_VER_14] = NULL, 5362 [RTL_GIGA_MAC_VER_15] = NULL, 5363 [RTL_GIGA_MAC_VER_16] = NULL, 5364 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef, 5365 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 5366 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 5367 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 5368 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 5369 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 5370 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 5371 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 5372 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 5373 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 5374 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 5375 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 5376 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 5377 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 5378 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp, 5379 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 5380 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 5381 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 5382 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 5383 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 5384 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 5385 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 5386 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 5387 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 5388 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 5389 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 5390 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 5391 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 5392 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 5393 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 5394 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 5395 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 5396 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 5397 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 5398 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 5399 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 5400 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 5401 }; 5402 5403 if (hw_configs[tp->mac_version]) 5404 hw_configs[tp->mac_version](tp); 5405 } 5406 5407 static void rtl_hw_start_8125(struct rtl8169_private *tp) 5408 { 5409 int i; 5410 5411 /* disable interrupt coalescing */ 5412 for (i = 0xa00; i < 0xb00; i += 4) 5413 RTL_W32(tp, i, 0); 5414 5415 rtl_hw_config(tp); 5416 } 5417 5418 static void rtl_hw_start_8168(struct rtl8169_private *tp) 5419 { 5420 if (tp->mac_version == RTL_GIGA_MAC_VER_13 || 5421 tp->mac_version == RTL_GIGA_MAC_VER_16) 5422 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, 5423 PCI_EXP_DEVCTL_NOSNOOP_EN); 5424 5425 if (rtl_is_8168evl_up(tp)) 5426 RTL_W8(tp, MaxTxPacketSize, EarlySize); 5427 else 5428 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5429 5430 rtl_hw_config(tp); 5431 5432 /* disable interrupt coalescing */ 5433 RTL_W16(tp, IntrMitigate, 0x0000); 5434 } 5435 5436 static void rtl_hw_start_8169(struct rtl8169_private *tp) 5437 { 5438 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5439 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 5440 5441 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 5442 5443 tp->cp_cmd |= PCIMulRW; 5444 5445 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 5446 tp->mac_version == RTL_GIGA_MAC_VER_03) { 5447 netif_dbg(tp, drv, tp->dev, 5448 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n"); 5449 tp->cp_cmd |= (1 << 14); 5450 } 5451 5452 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5453 5454 rtl8169_set_magic_reg(tp, tp->mac_version); 5455 5456 RTL_W32(tp, RxMissed, 0); 5457 5458 /* disable interrupt coalescing */ 5459 RTL_W16(tp, IntrMitigate, 0x0000); 5460 } 5461 5462 static void rtl_hw_start(struct rtl8169_private *tp) 5463 { 5464 rtl_unlock_config_regs(tp); 5465 5466 tp->cp_cmd &= CPCMD_MASK; 5467 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5468 5469 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5470 rtl_hw_start_8169(tp); 5471 else if (rtl_is_8125(tp)) 5472 rtl_hw_start_8125(tp); 5473 else 5474 rtl_hw_start_8168(tp); 5475 5476 rtl_set_rx_max_size(tp); 5477 rtl_set_rx_tx_desc_registers(tp); 5478 rtl_lock_config_regs(tp); 5479 5480 rtl_jumbo_config(tp, tp->dev->mtu); 5481 5482 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 5483 RTL_R16(tp, CPlusCmd); 5484 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 5485 rtl_init_rxcfg(tp); 5486 rtl_set_tx_config_registers(tp); 5487 rtl_set_rx_mode(tp->dev); 5488 rtl_irq_enable(tp); 5489 } 5490 5491 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 5492 { 5493 struct rtl8169_private *tp = netdev_priv(dev); 5494 5495 rtl_jumbo_config(tp, new_mtu); 5496 5497 dev->mtu = new_mtu; 5498 netdev_update_features(dev); 5499 5500 return 0; 5501 } 5502 5503 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 5504 { 5505 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); 5506 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 5507 } 5508 5509 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 5510 { 5511 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 5512 5513 /* Force memory writes to complete before releasing descriptor */ 5514 dma_wmb(); 5515 5516 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 5517 } 5518 5519 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 5520 struct RxDesc *desc) 5521 { 5522 struct device *d = tp_to_dev(tp); 5523 int node = dev_to_node(d); 5524 dma_addr_t mapping; 5525 struct page *data; 5526 5527 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 5528 if (!data) 5529 return NULL; 5530 5531 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5532 if (unlikely(dma_mapping_error(d, mapping))) { 5533 if (net_ratelimit()) 5534 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 5535 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 5536 return NULL; 5537 } 5538 5539 desc->addr = cpu_to_le64(mapping); 5540 rtl8169_mark_to_asic(desc); 5541 5542 return data; 5543 } 5544 5545 static void rtl8169_rx_clear(struct rtl8169_private *tp) 5546 { 5547 unsigned int i; 5548 5549 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 5550 dma_unmap_page(tp_to_dev(tp), 5551 le64_to_cpu(tp->RxDescArray[i].addr), 5552 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5553 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 5554 tp->Rx_databuff[i] = NULL; 5555 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5556 } 5557 } 5558 5559 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 5560 { 5561 desc->opts1 |= cpu_to_le32(RingEnd); 5562 } 5563 5564 static int rtl8169_rx_fill(struct rtl8169_private *tp) 5565 { 5566 unsigned int i; 5567 5568 for (i = 0; i < NUM_RX_DESC; i++) { 5569 struct page *data; 5570 5571 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 5572 if (!data) { 5573 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5574 goto err_out; 5575 } 5576 tp->Rx_databuff[i] = data; 5577 } 5578 5579 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 5580 return 0; 5581 5582 err_out: 5583 rtl8169_rx_clear(tp); 5584 return -ENOMEM; 5585 } 5586 5587 static int rtl8169_init_ring(struct rtl8169_private *tp) 5588 { 5589 rtl8169_init_ring_indexes(tp); 5590 5591 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 5592 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 5593 5594 return rtl8169_rx_fill(tp); 5595 } 5596 5597 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, 5598 struct TxDesc *desc) 5599 { 5600 unsigned int len = tx_skb->len; 5601 5602 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); 5603 5604 desc->opts1 = 0x00; 5605 desc->opts2 = 0x00; 5606 desc->addr = 0x00; 5607 tx_skb->len = 0; 5608 } 5609 5610 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 5611 unsigned int n) 5612 { 5613 unsigned int i; 5614 5615 for (i = 0; i < n; i++) { 5616 unsigned int entry = (start + i) % NUM_TX_DESC; 5617 struct ring_info *tx_skb = tp->tx_skb + entry; 5618 unsigned int len = tx_skb->len; 5619 5620 if (len) { 5621 struct sk_buff *skb = tx_skb->skb; 5622 5623 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5624 tp->TxDescArray + entry); 5625 if (skb) { 5626 dev_consume_skb_any(skb); 5627 tx_skb->skb = NULL; 5628 } 5629 } 5630 } 5631 } 5632 5633 static void rtl8169_tx_clear(struct rtl8169_private *tp) 5634 { 5635 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 5636 tp->cur_tx = tp->dirty_tx = 0; 5637 netdev_reset_queue(tp->dev); 5638 } 5639 5640 static void rtl_reset_work(struct rtl8169_private *tp) 5641 { 5642 struct net_device *dev = tp->dev; 5643 int i; 5644 5645 napi_disable(&tp->napi); 5646 netif_stop_queue(dev); 5647 synchronize_rcu(); 5648 5649 rtl8169_hw_reset(tp); 5650 5651 for (i = 0; i < NUM_RX_DESC; i++) 5652 rtl8169_mark_to_asic(tp->RxDescArray + i); 5653 5654 rtl8169_tx_clear(tp); 5655 rtl8169_init_ring_indexes(tp); 5656 5657 napi_enable(&tp->napi); 5658 rtl_hw_start(tp); 5659 netif_wake_queue(dev); 5660 } 5661 5662 static void rtl8169_tx_timeout(struct net_device *dev) 5663 { 5664 struct rtl8169_private *tp = netdev_priv(dev); 5665 5666 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5667 } 5668 5669 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry) 5670 { 5671 u32 status = opts0 | len; 5672 5673 if (entry == NUM_TX_DESC - 1) 5674 status |= RingEnd; 5675 5676 return cpu_to_le32(status); 5677 } 5678 5679 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 5680 u32 *opts) 5681 { 5682 struct skb_shared_info *info = skb_shinfo(skb); 5683 unsigned int cur_frag, entry; 5684 struct TxDesc *uninitialized_var(txd); 5685 struct device *d = tp_to_dev(tp); 5686 5687 entry = tp->cur_tx; 5688 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 5689 const skb_frag_t *frag = info->frags + cur_frag; 5690 dma_addr_t mapping; 5691 u32 len; 5692 void *addr; 5693 5694 entry = (entry + 1) % NUM_TX_DESC; 5695 5696 txd = tp->TxDescArray + entry; 5697 len = skb_frag_size(frag); 5698 addr = skb_frag_address(frag); 5699 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 5700 if (unlikely(dma_mapping_error(d, mapping))) { 5701 if (net_ratelimit()) 5702 netif_err(tp, drv, tp->dev, 5703 "Failed to map TX fragments DMA!\n"); 5704 goto err_out; 5705 } 5706 5707 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5708 txd->opts2 = cpu_to_le32(opts[1]); 5709 txd->addr = cpu_to_le64(mapping); 5710 5711 tp->tx_skb[entry].len = len; 5712 } 5713 5714 if (cur_frag) { 5715 tp->tx_skb[entry].skb = skb; 5716 txd->opts1 |= cpu_to_le32(LastFrag); 5717 } 5718 5719 return cur_frag; 5720 5721 err_out: 5722 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 5723 return -EIO; 5724 } 5725 5726 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 5727 { 5728 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 5729 } 5730 5731 /* msdn_giant_send_check() 5732 * According to the document of microsoft, the TCP Pseudo Header excludes the 5733 * packet length for IPv6 TCP large packets. 5734 */ 5735 static int msdn_giant_send_check(struct sk_buff *skb) 5736 { 5737 const struct ipv6hdr *ipv6h; 5738 struct tcphdr *th; 5739 int ret; 5740 5741 ret = skb_cow_head(skb, 0); 5742 if (ret) 5743 return ret; 5744 5745 ipv6h = ipv6_hdr(skb); 5746 th = tcp_hdr(skb); 5747 5748 th->check = 0; 5749 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 5750 5751 return ret; 5752 } 5753 5754 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 5755 { 5756 u32 mss = skb_shinfo(skb)->gso_size; 5757 5758 if (mss) { 5759 opts[0] |= TD_LSO; 5760 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; 5761 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5762 const struct iphdr *ip = ip_hdr(skb); 5763 5764 if (ip->protocol == IPPROTO_TCP) 5765 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 5766 else if (ip->protocol == IPPROTO_UDP) 5767 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 5768 else 5769 WARN_ON_ONCE(1); 5770 } 5771 } 5772 5773 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 5774 struct sk_buff *skb, u32 *opts) 5775 { 5776 u32 transport_offset = (u32)skb_transport_offset(skb); 5777 u32 mss = skb_shinfo(skb)->gso_size; 5778 5779 if (mss) { 5780 switch (vlan_get_protocol(skb)) { 5781 case htons(ETH_P_IP): 5782 opts[0] |= TD1_GTSENV4; 5783 break; 5784 5785 case htons(ETH_P_IPV6): 5786 if (msdn_giant_send_check(skb)) 5787 return false; 5788 5789 opts[0] |= TD1_GTSENV6; 5790 break; 5791 5792 default: 5793 WARN_ON_ONCE(1); 5794 break; 5795 } 5796 5797 opts[0] |= transport_offset << GTTCPHO_SHIFT; 5798 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; 5799 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5800 u8 ip_protocol; 5801 5802 switch (vlan_get_protocol(skb)) { 5803 case htons(ETH_P_IP): 5804 opts[1] |= TD1_IPv4_CS; 5805 ip_protocol = ip_hdr(skb)->protocol; 5806 break; 5807 5808 case htons(ETH_P_IPV6): 5809 opts[1] |= TD1_IPv6_CS; 5810 ip_protocol = ipv6_hdr(skb)->nexthdr; 5811 break; 5812 5813 default: 5814 ip_protocol = IPPROTO_RAW; 5815 break; 5816 } 5817 5818 if (ip_protocol == IPPROTO_TCP) 5819 opts[1] |= TD1_TCP_CS; 5820 else if (ip_protocol == IPPROTO_UDP) 5821 opts[1] |= TD1_UDP_CS; 5822 else 5823 WARN_ON_ONCE(1); 5824 5825 opts[1] |= transport_offset << TCPHO_SHIFT; 5826 } else { 5827 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 5828 return !eth_skb_pad(skb); 5829 } 5830 5831 return true; 5832 } 5833 5834 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 5835 unsigned int nr_frags) 5836 { 5837 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 5838 5839 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 5840 return slots_avail > nr_frags; 5841 } 5842 5843 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 5844 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 5845 { 5846 switch (tp->mac_version) { 5847 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5848 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 5849 return false; 5850 default: 5851 return true; 5852 } 5853 } 5854 5855 static void rtl8169_doorbell(struct rtl8169_private *tp) 5856 { 5857 if (rtl_is_8125(tp)) 5858 RTL_W16(tp, TxPoll_8125, BIT(0)); 5859 else 5860 RTL_W8(tp, TxPoll, NPQ); 5861 } 5862 5863 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 5864 struct net_device *dev) 5865 { 5866 struct rtl8169_private *tp = netdev_priv(dev); 5867 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 5868 struct TxDesc *txd = tp->TxDescArray + entry; 5869 struct device *d = tp_to_dev(tp); 5870 dma_addr_t mapping; 5871 u32 opts[2], len; 5872 bool stop_queue; 5873 bool door_bell; 5874 int frags; 5875 5876 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) { 5877 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 5878 goto err_stop_0; 5879 } 5880 5881 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 5882 goto err_stop_0; 5883 5884 opts[1] = rtl8169_tx_vlan_tag(skb); 5885 opts[0] = DescOwn; 5886 5887 if (rtl_chip_supports_csum_v2(tp)) { 5888 if (!rtl8169_tso_csum_v2(tp, skb, opts)) 5889 goto err_dma_0; 5890 } else { 5891 rtl8169_tso_csum_v1(skb, opts); 5892 } 5893 5894 len = skb_headlen(skb); 5895 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); 5896 if (unlikely(dma_mapping_error(d, mapping))) { 5897 if (net_ratelimit()) 5898 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); 5899 goto err_dma_0; 5900 } 5901 5902 tp->tx_skb[entry].len = len; 5903 txd->addr = cpu_to_le64(mapping); 5904 5905 frags = rtl8169_xmit_frags(tp, skb, opts); 5906 if (frags < 0) 5907 goto err_dma_1; 5908 else if (frags) 5909 opts[0] |= FirstFrag; 5910 else { 5911 opts[0] |= FirstFrag | LastFrag; 5912 tp->tx_skb[entry].skb = skb; 5913 } 5914 5915 txd->opts2 = cpu_to_le32(opts[1]); 5916 5917 skb_tx_timestamp(skb); 5918 5919 /* Force memory writes to complete before releasing descriptor */ 5920 dma_wmb(); 5921 5922 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 5923 5924 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5925 5926 /* Force all memory writes to complete before notifying device */ 5927 wmb(); 5928 5929 tp->cur_tx += frags + 1; 5930 5931 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 5932 if (unlikely(stop_queue)) { 5933 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 5934 * not miss a ring update when it notices a stopped queue. 5935 */ 5936 smp_wmb(); 5937 netif_stop_queue(dev); 5938 door_bell = true; 5939 } 5940 5941 if (door_bell) 5942 rtl8169_doorbell(tp); 5943 5944 if (unlikely(stop_queue)) { 5945 /* Sync with rtl_tx: 5946 * - publish queue status and cur_tx ring index (write barrier) 5947 * - refresh dirty_tx ring index (read barrier). 5948 * May the current thread have a pessimistic view of the ring 5949 * status and forget to wake up queue, a racing rtl_tx thread 5950 * can't. 5951 */ 5952 smp_mb(); 5953 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 5954 netif_start_queue(dev); 5955 } 5956 5957 return NETDEV_TX_OK; 5958 5959 err_dma_1: 5960 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); 5961 err_dma_0: 5962 dev_kfree_skb_any(skb); 5963 dev->stats.tx_dropped++; 5964 return NETDEV_TX_OK; 5965 5966 err_stop_0: 5967 netif_stop_queue(dev); 5968 dev->stats.tx_dropped++; 5969 return NETDEV_TX_BUSY; 5970 } 5971 5972 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 5973 struct net_device *dev, 5974 netdev_features_t features) 5975 { 5976 int transport_offset = skb_transport_offset(skb); 5977 struct rtl8169_private *tp = netdev_priv(dev); 5978 5979 if (skb_is_gso(skb)) { 5980 if (transport_offset > GTTCPHO_MAX && 5981 rtl_chip_supports_csum_v2(tp)) 5982 features &= ~NETIF_F_ALL_TSO; 5983 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5984 if (skb->len < ETH_ZLEN) { 5985 switch (tp->mac_version) { 5986 case RTL_GIGA_MAC_VER_11: 5987 case RTL_GIGA_MAC_VER_12: 5988 case RTL_GIGA_MAC_VER_17: 5989 case RTL_GIGA_MAC_VER_34: 5990 features &= ~NETIF_F_CSUM_MASK; 5991 break; 5992 default: 5993 break; 5994 } 5995 } 5996 5997 if (transport_offset > TCPHO_MAX && 5998 rtl_chip_supports_csum_v2(tp)) 5999 features &= ~NETIF_F_CSUM_MASK; 6000 } 6001 6002 return vlan_features_check(skb, features); 6003 } 6004 6005 static void rtl8169_pcierr_interrupt(struct net_device *dev) 6006 { 6007 struct rtl8169_private *tp = netdev_priv(dev); 6008 struct pci_dev *pdev = tp->pci_dev; 6009 u16 pci_status, pci_cmd; 6010 6011 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 6012 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 6013 6014 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", 6015 pci_cmd, pci_status); 6016 6017 /* 6018 * The recovery sequence below admits a very elaborated explanation: 6019 * - it seems to work; 6020 * - I did not see what else could be done; 6021 * - it makes iop3xx happy. 6022 * 6023 * Feel free to adjust to your needs. 6024 */ 6025 if (pdev->broken_parity_status) 6026 pci_cmd &= ~PCI_COMMAND_PARITY; 6027 else 6028 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 6029 6030 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 6031 6032 pci_write_config_word(pdev, PCI_STATUS, 6033 pci_status & (PCI_STATUS_DETECTED_PARITY | 6034 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | 6035 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); 6036 6037 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 6038 } 6039 6040 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 6041 int budget) 6042 { 6043 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 6044 6045 dirty_tx = tp->dirty_tx; 6046 smp_rmb(); 6047 tx_left = tp->cur_tx - dirty_tx; 6048 6049 while (tx_left > 0) { 6050 unsigned int entry = dirty_tx % NUM_TX_DESC; 6051 struct ring_info *tx_skb = tp->tx_skb + entry; 6052 u32 status; 6053 6054 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 6055 if (status & DescOwn) 6056 break; 6057 6058 /* This barrier is needed to keep us from reading 6059 * any other fields out of the Tx descriptor until 6060 * we know the status of DescOwn 6061 */ 6062 dma_rmb(); 6063 6064 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 6065 tp->TxDescArray + entry); 6066 if (tx_skb->skb) { 6067 pkts_compl++; 6068 bytes_compl += tx_skb->skb->len; 6069 napi_consume_skb(tx_skb->skb, budget); 6070 tx_skb->skb = NULL; 6071 } 6072 dirty_tx++; 6073 tx_left--; 6074 } 6075 6076 if (tp->dirty_tx != dirty_tx) { 6077 netdev_completed_queue(dev, pkts_compl, bytes_compl); 6078 6079 u64_stats_update_begin(&tp->tx_stats.syncp); 6080 tp->tx_stats.packets += pkts_compl; 6081 tp->tx_stats.bytes += bytes_compl; 6082 u64_stats_update_end(&tp->tx_stats.syncp); 6083 6084 tp->dirty_tx = dirty_tx; 6085 /* Sync with rtl8169_start_xmit: 6086 * - publish dirty_tx ring index (write barrier) 6087 * - refresh cur_tx ring index and queue status (read barrier) 6088 * May the current thread miss the stopped queue condition, 6089 * a racing xmit thread can only have a right view of the 6090 * ring status. 6091 */ 6092 smp_mb(); 6093 if (netif_queue_stopped(dev) && 6094 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 6095 netif_wake_queue(dev); 6096 } 6097 /* 6098 * 8168 hack: TxPoll requests are lost when the Tx packets are 6099 * too close. Let's kick an extra TxPoll request when a burst 6100 * of start_xmit activity is detected (if it is not detected, 6101 * it is slow enough). -- FR 6102 */ 6103 if (tp->cur_tx != dirty_tx) 6104 rtl8169_doorbell(tp); 6105 } 6106 } 6107 6108 static inline int rtl8169_fragmented_frame(u32 status) 6109 { 6110 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 6111 } 6112 6113 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 6114 { 6115 u32 status = opts1 & RxProtoMask; 6116 6117 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 6118 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 6119 skb->ip_summed = CHECKSUM_UNNECESSARY; 6120 else 6121 skb_checksum_none_assert(skb); 6122 } 6123 6124 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 6125 { 6126 unsigned int cur_rx, rx_left; 6127 unsigned int count; 6128 6129 cur_rx = tp->cur_rx; 6130 6131 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 6132 unsigned int entry = cur_rx % NUM_RX_DESC; 6133 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 6134 struct RxDesc *desc = tp->RxDescArray + entry; 6135 u32 status; 6136 6137 status = le32_to_cpu(desc->opts1); 6138 if (status & DescOwn) 6139 break; 6140 6141 /* This barrier is needed to keep us from reading 6142 * any other fields out of the Rx descriptor until 6143 * we know the status of DescOwn 6144 */ 6145 dma_rmb(); 6146 6147 if (unlikely(status & RxRES)) { 6148 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 6149 status); 6150 dev->stats.rx_errors++; 6151 if (status & (RxRWT | RxRUNT)) 6152 dev->stats.rx_length_errors++; 6153 if (status & RxCRC) 6154 dev->stats.rx_crc_errors++; 6155 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 6156 dev->features & NETIF_F_RXALL) { 6157 goto process_pkt; 6158 } 6159 } else { 6160 unsigned int pkt_size; 6161 struct sk_buff *skb; 6162 6163 process_pkt: 6164 pkt_size = status & GENMASK(13, 0); 6165 if (likely(!(dev->features & NETIF_F_RXFCS))) 6166 pkt_size -= ETH_FCS_LEN; 6167 /* 6168 * The driver does not support incoming fragmented 6169 * frames. They are seen as a symptom of over-mtu 6170 * sized frames. 6171 */ 6172 if (unlikely(rtl8169_fragmented_frame(status))) { 6173 dev->stats.rx_dropped++; 6174 dev->stats.rx_length_errors++; 6175 goto release_descriptor; 6176 } 6177 6178 skb = napi_alloc_skb(&tp->napi, pkt_size); 6179 if (unlikely(!skb)) { 6180 dev->stats.rx_dropped++; 6181 goto release_descriptor; 6182 } 6183 6184 dma_sync_single_for_cpu(tp_to_dev(tp), 6185 le64_to_cpu(desc->addr), 6186 pkt_size, DMA_FROM_DEVICE); 6187 prefetch(rx_buf); 6188 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 6189 skb->tail += pkt_size; 6190 skb->len = pkt_size; 6191 6192 dma_sync_single_for_device(tp_to_dev(tp), 6193 le64_to_cpu(desc->addr), 6194 pkt_size, DMA_FROM_DEVICE); 6195 6196 rtl8169_rx_csum(skb, status); 6197 skb->protocol = eth_type_trans(skb, dev); 6198 6199 rtl8169_rx_vlan_tag(desc, skb); 6200 6201 if (skb->pkt_type == PACKET_MULTICAST) 6202 dev->stats.multicast++; 6203 6204 napi_gro_receive(&tp->napi, skb); 6205 6206 u64_stats_update_begin(&tp->rx_stats.syncp); 6207 tp->rx_stats.packets++; 6208 tp->rx_stats.bytes += pkt_size; 6209 u64_stats_update_end(&tp->rx_stats.syncp); 6210 } 6211 release_descriptor: 6212 desc->opts2 = 0; 6213 rtl8169_mark_to_asic(desc); 6214 } 6215 6216 count = cur_rx - tp->cur_rx; 6217 tp->cur_rx = cur_rx; 6218 6219 return count; 6220 } 6221 6222 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 6223 { 6224 struct rtl8169_private *tp = dev_instance; 6225 u32 status = rtl_get_events(tp); 6226 6227 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 6228 !(status & tp->irq_mask)) 6229 return IRQ_NONE; 6230 6231 if (unlikely(status & SYSErr)) { 6232 rtl8169_pcierr_interrupt(tp->dev); 6233 goto out; 6234 } 6235 6236 if (status & LinkChg) 6237 phy_mac_interrupt(tp->phydev); 6238 6239 if (unlikely(status & RxFIFOOver && 6240 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 6241 netif_stop_queue(tp->dev); 6242 /* XXX - Hack alert. See rtl_task(). */ 6243 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); 6244 } 6245 6246 rtl_irq_disable(tp); 6247 napi_schedule_irqoff(&tp->napi); 6248 out: 6249 rtl_ack_events(tp, status); 6250 6251 return IRQ_HANDLED; 6252 } 6253 6254 static void rtl_task(struct work_struct *work) 6255 { 6256 static const struct { 6257 int bitnr; 6258 void (*action)(struct rtl8169_private *); 6259 } rtl_work[] = { 6260 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, 6261 }; 6262 struct rtl8169_private *tp = 6263 container_of(work, struct rtl8169_private, wk.work); 6264 struct net_device *dev = tp->dev; 6265 int i; 6266 6267 rtl_lock_work(tp); 6268 6269 if (!netif_running(dev) || 6270 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 6271 goto out_unlock; 6272 6273 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { 6274 bool pending; 6275 6276 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); 6277 if (pending) 6278 rtl_work[i].action(tp); 6279 } 6280 6281 out_unlock: 6282 rtl_unlock_work(tp); 6283 } 6284 6285 static int rtl8169_poll(struct napi_struct *napi, int budget) 6286 { 6287 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 6288 struct net_device *dev = tp->dev; 6289 int work_done; 6290 6291 work_done = rtl_rx(dev, tp, (u32) budget); 6292 6293 rtl_tx(dev, tp, budget); 6294 6295 if (work_done < budget) { 6296 napi_complete_done(napi, work_done); 6297 rtl_irq_enable(tp); 6298 } 6299 6300 return work_done; 6301 } 6302 6303 static void rtl8169_rx_missed(struct net_device *dev) 6304 { 6305 struct rtl8169_private *tp = netdev_priv(dev); 6306 6307 if (tp->mac_version > RTL_GIGA_MAC_VER_06) 6308 return; 6309 6310 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff; 6311 RTL_W32(tp, RxMissed, 0); 6312 } 6313 6314 static void r8169_phylink_handler(struct net_device *ndev) 6315 { 6316 struct rtl8169_private *tp = netdev_priv(ndev); 6317 6318 if (netif_carrier_ok(ndev)) { 6319 rtl_link_chg_patch(tp); 6320 pm_request_resume(&tp->pci_dev->dev); 6321 } else { 6322 pm_runtime_idle(&tp->pci_dev->dev); 6323 } 6324 6325 if (net_ratelimit()) 6326 phy_print_status(tp->phydev); 6327 } 6328 6329 static int r8169_phy_connect(struct rtl8169_private *tp) 6330 { 6331 struct phy_device *phydev = tp->phydev; 6332 phy_interface_t phy_mode; 6333 int ret; 6334 6335 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 6336 PHY_INTERFACE_MODE_MII; 6337 6338 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 6339 phy_mode); 6340 if (ret) 6341 return ret; 6342 6343 if (!tp->supports_gmii) 6344 phy_set_max_speed(phydev, SPEED_100); 6345 6346 phy_support_asym_pause(phydev); 6347 6348 phy_attached_info(phydev); 6349 6350 return 0; 6351 } 6352 6353 static void rtl8169_down(struct net_device *dev) 6354 { 6355 struct rtl8169_private *tp = netdev_priv(dev); 6356 6357 phy_stop(tp->phydev); 6358 6359 napi_disable(&tp->napi); 6360 netif_stop_queue(dev); 6361 6362 rtl8169_hw_reset(tp); 6363 /* 6364 * At this point device interrupts can not be enabled in any function, 6365 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) 6366 * and napi is disabled (rtl8169_poll). 6367 */ 6368 rtl8169_rx_missed(dev); 6369 6370 /* Give a racing hard_start_xmit a few cycles to complete. */ 6371 synchronize_rcu(); 6372 6373 rtl8169_tx_clear(tp); 6374 6375 rtl8169_rx_clear(tp); 6376 6377 rtl_pll_power_down(tp); 6378 } 6379 6380 static int rtl8169_close(struct net_device *dev) 6381 { 6382 struct rtl8169_private *tp = netdev_priv(dev); 6383 struct pci_dev *pdev = tp->pci_dev; 6384 6385 pm_runtime_get_sync(&pdev->dev); 6386 6387 /* Update counters before going down */ 6388 rtl8169_update_counters(tp); 6389 6390 rtl_lock_work(tp); 6391 /* Clear all task flags */ 6392 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6393 6394 rtl8169_down(dev); 6395 rtl_unlock_work(tp); 6396 6397 cancel_work_sync(&tp->wk.work); 6398 6399 phy_disconnect(tp->phydev); 6400 6401 pci_free_irq(pdev, 0, tp); 6402 6403 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6404 tp->RxPhyAddr); 6405 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6406 tp->TxPhyAddr); 6407 tp->TxDescArray = NULL; 6408 tp->RxDescArray = NULL; 6409 6410 pm_runtime_put_sync(&pdev->dev); 6411 6412 return 0; 6413 } 6414 6415 #ifdef CONFIG_NET_POLL_CONTROLLER 6416 static void rtl8169_netpoll(struct net_device *dev) 6417 { 6418 struct rtl8169_private *tp = netdev_priv(dev); 6419 6420 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 6421 } 6422 #endif 6423 6424 static int rtl_open(struct net_device *dev) 6425 { 6426 struct rtl8169_private *tp = netdev_priv(dev); 6427 struct pci_dev *pdev = tp->pci_dev; 6428 int retval = -ENOMEM; 6429 6430 pm_runtime_get_sync(&pdev->dev); 6431 6432 /* 6433 * Rx and Tx descriptors needs 256 bytes alignment. 6434 * dma_alloc_coherent provides more. 6435 */ 6436 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 6437 &tp->TxPhyAddr, GFP_KERNEL); 6438 if (!tp->TxDescArray) 6439 goto err_pm_runtime_put; 6440 6441 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 6442 &tp->RxPhyAddr, GFP_KERNEL); 6443 if (!tp->RxDescArray) 6444 goto err_free_tx_0; 6445 6446 retval = rtl8169_init_ring(tp); 6447 if (retval < 0) 6448 goto err_free_rx_1; 6449 6450 rtl_request_firmware(tp); 6451 6452 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 6453 dev->name); 6454 if (retval < 0) 6455 goto err_release_fw_2; 6456 6457 retval = r8169_phy_connect(tp); 6458 if (retval) 6459 goto err_free_irq; 6460 6461 rtl_lock_work(tp); 6462 6463 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6464 6465 napi_enable(&tp->napi); 6466 6467 rtl8169_init_phy(dev, tp); 6468 6469 rtl_pll_power_up(tp); 6470 6471 rtl_hw_start(tp); 6472 6473 if (!rtl8169_init_counter_offsets(tp)) 6474 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 6475 6476 phy_start(tp->phydev); 6477 netif_start_queue(dev); 6478 6479 rtl_unlock_work(tp); 6480 6481 pm_runtime_put_sync(&pdev->dev); 6482 out: 6483 return retval; 6484 6485 err_free_irq: 6486 pci_free_irq(pdev, 0, tp); 6487 err_release_fw_2: 6488 rtl_release_firmware(tp); 6489 rtl8169_rx_clear(tp); 6490 err_free_rx_1: 6491 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6492 tp->RxPhyAddr); 6493 tp->RxDescArray = NULL; 6494 err_free_tx_0: 6495 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6496 tp->TxPhyAddr); 6497 tp->TxDescArray = NULL; 6498 err_pm_runtime_put: 6499 pm_runtime_put_noidle(&pdev->dev); 6500 goto out; 6501 } 6502 6503 static void 6504 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6505 { 6506 struct rtl8169_private *tp = netdev_priv(dev); 6507 struct pci_dev *pdev = tp->pci_dev; 6508 struct rtl8169_counters *counters = tp->counters; 6509 unsigned int start; 6510 6511 pm_runtime_get_noresume(&pdev->dev); 6512 6513 if (netif_running(dev) && pm_runtime_active(&pdev->dev)) 6514 rtl8169_rx_missed(dev); 6515 6516 do { 6517 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 6518 stats->rx_packets = tp->rx_stats.packets; 6519 stats->rx_bytes = tp->rx_stats.bytes; 6520 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 6521 6522 do { 6523 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 6524 stats->tx_packets = tp->tx_stats.packets; 6525 stats->tx_bytes = tp->tx_stats.bytes; 6526 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 6527 6528 stats->rx_dropped = dev->stats.rx_dropped; 6529 stats->tx_dropped = dev->stats.tx_dropped; 6530 stats->rx_length_errors = dev->stats.rx_length_errors; 6531 stats->rx_errors = dev->stats.rx_errors; 6532 stats->rx_crc_errors = dev->stats.rx_crc_errors; 6533 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 6534 stats->rx_missed_errors = dev->stats.rx_missed_errors; 6535 stats->multicast = dev->stats.multicast; 6536 6537 /* 6538 * Fetch additional counter values missing in stats collected by driver 6539 * from tally counters. 6540 */ 6541 if (pm_runtime_active(&pdev->dev)) 6542 rtl8169_update_counters(tp); 6543 6544 /* 6545 * Subtract values fetched during initalization. 6546 * See rtl8169_init_counter_offsets for a description why we do that. 6547 */ 6548 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 6549 le64_to_cpu(tp->tc_offset.tx_errors); 6550 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 6551 le32_to_cpu(tp->tc_offset.tx_multi_collision); 6552 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 6553 le16_to_cpu(tp->tc_offset.tx_aborted); 6554 6555 pm_runtime_put_noidle(&pdev->dev); 6556 } 6557 6558 static void rtl8169_net_suspend(struct net_device *dev) 6559 { 6560 struct rtl8169_private *tp = netdev_priv(dev); 6561 6562 if (!netif_running(dev)) 6563 return; 6564 6565 phy_stop(tp->phydev); 6566 netif_device_detach(dev); 6567 6568 rtl_lock_work(tp); 6569 napi_disable(&tp->napi); 6570 /* Clear all task flags */ 6571 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6572 6573 rtl_unlock_work(tp); 6574 6575 rtl_pll_power_down(tp); 6576 } 6577 6578 #ifdef CONFIG_PM 6579 6580 static int rtl8169_suspend(struct device *device) 6581 { 6582 struct net_device *dev = dev_get_drvdata(device); 6583 struct rtl8169_private *tp = netdev_priv(dev); 6584 6585 rtl8169_net_suspend(dev); 6586 clk_disable_unprepare(tp->clk); 6587 6588 return 0; 6589 } 6590 6591 static void __rtl8169_resume(struct net_device *dev) 6592 { 6593 struct rtl8169_private *tp = netdev_priv(dev); 6594 6595 netif_device_attach(dev); 6596 6597 rtl_pll_power_up(tp); 6598 rtl8169_init_phy(dev, tp); 6599 6600 phy_start(tp->phydev); 6601 6602 rtl_lock_work(tp); 6603 napi_enable(&tp->napi); 6604 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6605 rtl_reset_work(tp); 6606 rtl_unlock_work(tp); 6607 } 6608 6609 static int rtl8169_resume(struct device *device) 6610 { 6611 struct net_device *dev = dev_get_drvdata(device); 6612 struct rtl8169_private *tp = netdev_priv(dev); 6613 6614 rtl_rar_set(tp, dev->dev_addr); 6615 6616 clk_prepare_enable(tp->clk); 6617 6618 if (netif_running(dev)) 6619 __rtl8169_resume(dev); 6620 6621 return 0; 6622 } 6623 6624 static int rtl8169_runtime_suspend(struct device *device) 6625 { 6626 struct net_device *dev = dev_get_drvdata(device); 6627 struct rtl8169_private *tp = netdev_priv(dev); 6628 6629 if (!tp->TxDescArray) 6630 return 0; 6631 6632 rtl_lock_work(tp); 6633 __rtl8169_set_wol(tp, WAKE_ANY); 6634 rtl_unlock_work(tp); 6635 6636 rtl8169_net_suspend(dev); 6637 6638 /* Update counters before going runtime suspend */ 6639 rtl8169_rx_missed(dev); 6640 rtl8169_update_counters(tp); 6641 6642 return 0; 6643 } 6644 6645 static int rtl8169_runtime_resume(struct device *device) 6646 { 6647 struct net_device *dev = dev_get_drvdata(device); 6648 struct rtl8169_private *tp = netdev_priv(dev); 6649 6650 rtl_rar_set(tp, dev->dev_addr); 6651 6652 if (!tp->TxDescArray) 6653 return 0; 6654 6655 rtl_lock_work(tp); 6656 __rtl8169_set_wol(tp, tp->saved_wolopts); 6657 rtl_unlock_work(tp); 6658 6659 __rtl8169_resume(dev); 6660 6661 return 0; 6662 } 6663 6664 static int rtl8169_runtime_idle(struct device *device) 6665 { 6666 struct net_device *dev = dev_get_drvdata(device); 6667 6668 if (!netif_running(dev) || !netif_carrier_ok(dev)) 6669 pm_schedule_suspend(device, 10000); 6670 6671 return -EBUSY; 6672 } 6673 6674 static const struct dev_pm_ops rtl8169_pm_ops = { 6675 .suspend = rtl8169_suspend, 6676 .resume = rtl8169_resume, 6677 .freeze = rtl8169_suspend, 6678 .thaw = rtl8169_resume, 6679 .poweroff = rtl8169_suspend, 6680 .restore = rtl8169_resume, 6681 .runtime_suspend = rtl8169_runtime_suspend, 6682 .runtime_resume = rtl8169_runtime_resume, 6683 .runtime_idle = rtl8169_runtime_idle, 6684 }; 6685 6686 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 6687 6688 #else /* !CONFIG_PM */ 6689 6690 #define RTL8169_PM_OPS NULL 6691 6692 #endif /* !CONFIG_PM */ 6693 6694 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 6695 { 6696 /* WoL fails with 8168b when the receiver is disabled. */ 6697 switch (tp->mac_version) { 6698 case RTL_GIGA_MAC_VER_11: 6699 case RTL_GIGA_MAC_VER_12: 6700 case RTL_GIGA_MAC_VER_17: 6701 pci_clear_master(tp->pci_dev); 6702 6703 RTL_W8(tp, ChipCmd, CmdRxEnb); 6704 /* PCI commit */ 6705 RTL_R8(tp, ChipCmd); 6706 break; 6707 default: 6708 break; 6709 } 6710 } 6711 6712 static void rtl_shutdown(struct pci_dev *pdev) 6713 { 6714 struct net_device *dev = pci_get_drvdata(pdev); 6715 struct rtl8169_private *tp = netdev_priv(dev); 6716 6717 rtl8169_net_suspend(dev); 6718 6719 /* Restore original MAC address */ 6720 rtl_rar_set(tp, dev->perm_addr); 6721 6722 rtl8169_hw_reset(tp); 6723 6724 if (system_state == SYSTEM_POWER_OFF) { 6725 if (tp->saved_wolopts) { 6726 rtl_wol_suspend_quirk(tp); 6727 rtl_wol_shutdown_quirk(tp); 6728 } 6729 6730 pci_wake_from_d3(pdev, true); 6731 pci_set_power_state(pdev, PCI_D3hot); 6732 } 6733 } 6734 6735 static void rtl_remove_one(struct pci_dev *pdev) 6736 { 6737 struct net_device *dev = pci_get_drvdata(pdev); 6738 struct rtl8169_private *tp = netdev_priv(dev); 6739 6740 if (r8168_check_dash(tp)) 6741 rtl8168_driver_stop(tp); 6742 6743 netif_napi_del(&tp->napi); 6744 6745 unregister_netdev(dev); 6746 mdiobus_unregister(tp->phydev->mdio.bus); 6747 6748 rtl_release_firmware(tp); 6749 6750 if (pci_dev_run_wake(pdev)) 6751 pm_runtime_get_noresume(&pdev->dev); 6752 6753 /* restore original MAC address */ 6754 rtl_rar_set(tp, dev->perm_addr); 6755 } 6756 6757 static const struct net_device_ops rtl_netdev_ops = { 6758 .ndo_open = rtl_open, 6759 .ndo_stop = rtl8169_close, 6760 .ndo_get_stats64 = rtl8169_get_stats64, 6761 .ndo_start_xmit = rtl8169_start_xmit, 6762 .ndo_features_check = rtl8169_features_check, 6763 .ndo_tx_timeout = rtl8169_tx_timeout, 6764 .ndo_validate_addr = eth_validate_addr, 6765 .ndo_change_mtu = rtl8169_change_mtu, 6766 .ndo_fix_features = rtl8169_fix_features, 6767 .ndo_set_features = rtl8169_set_features, 6768 .ndo_set_mac_address = rtl_set_mac_address, 6769 .ndo_do_ioctl = rtl8169_ioctl, 6770 .ndo_set_rx_mode = rtl_set_rx_mode, 6771 #ifdef CONFIG_NET_POLL_CONTROLLER 6772 .ndo_poll_controller = rtl8169_netpoll, 6773 #endif 6774 6775 }; 6776 6777 static void rtl_set_irq_mask(struct rtl8169_private *tp) 6778 { 6779 tp->irq_mask = RTL_EVENT_NAPI | LinkChg; 6780 6781 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 6782 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 6783 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 6784 /* special workaround needed */ 6785 tp->irq_mask |= RxFIFOOver; 6786 else 6787 tp->irq_mask |= RxOverflow; 6788 } 6789 6790 static int rtl_alloc_irq(struct rtl8169_private *tp) 6791 { 6792 unsigned int flags; 6793 6794 switch (tp->mac_version) { 6795 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6796 rtl_unlock_config_regs(tp); 6797 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 6798 rtl_lock_config_regs(tp); 6799 /* fall through */ 6800 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24: 6801 flags = PCI_IRQ_LEGACY; 6802 break; 6803 default: 6804 flags = PCI_IRQ_ALL_TYPES; 6805 break; 6806 } 6807 6808 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 6809 } 6810 6811 static void rtl_read_mac_address(struct rtl8169_private *tp, 6812 u8 mac_addr[ETH_ALEN]) 6813 { 6814 /* Get MAC address */ 6815 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 6816 u32 value = rtl_eri_read(tp, 0xe0); 6817 6818 mac_addr[0] = (value >> 0) & 0xff; 6819 mac_addr[1] = (value >> 8) & 0xff; 6820 mac_addr[2] = (value >> 16) & 0xff; 6821 mac_addr[3] = (value >> 24) & 0xff; 6822 6823 value = rtl_eri_read(tp, 0xe4); 6824 mac_addr[4] = (value >> 0) & 0xff; 6825 mac_addr[5] = (value >> 8) & 0xff; 6826 } else if (rtl_is_8125(tp)) { 6827 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 6828 } 6829 } 6830 6831 DECLARE_RTL_COND(rtl_link_list_ready_cond) 6832 { 6833 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 6834 } 6835 6836 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 6837 { 6838 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 6839 } 6840 6841 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 6842 { 6843 struct rtl8169_private *tp = mii_bus->priv; 6844 6845 if (phyaddr > 0) 6846 return -ENODEV; 6847 6848 return rtl_readphy(tp, phyreg); 6849 } 6850 6851 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 6852 int phyreg, u16 val) 6853 { 6854 struct rtl8169_private *tp = mii_bus->priv; 6855 6856 if (phyaddr > 0) 6857 return -ENODEV; 6858 6859 rtl_writephy(tp, phyreg, val); 6860 6861 return 0; 6862 } 6863 6864 static int r8169_mdio_register(struct rtl8169_private *tp) 6865 { 6866 struct pci_dev *pdev = tp->pci_dev; 6867 struct mii_bus *new_bus; 6868 int ret; 6869 6870 new_bus = devm_mdiobus_alloc(&pdev->dev); 6871 if (!new_bus) 6872 return -ENOMEM; 6873 6874 new_bus->name = "r8169"; 6875 new_bus->priv = tp; 6876 new_bus->parent = &pdev->dev; 6877 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 6878 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 6879 6880 new_bus->read = r8169_mdio_read_reg; 6881 new_bus->write = r8169_mdio_write_reg; 6882 6883 ret = mdiobus_register(new_bus); 6884 if (ret) 6885 return ret; 6886 6887 tp->phydev = mdiobus_get_phy(new_bus, 0); 6888 if (!tp->phydev) { 6889 mdiobus_unregister(new_bus); 6890 return -ENODEV; 6891 } 6892 6893 /* PHY will be woken up in rtl_open() */ 6894 phy_suspend(tp->phydev); 6895 6896 return 0; 6897 } 6898 6899 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 6900 { 6901 tp->ocp_base = OCP_STD_PHY_BASE; 6902 6903 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6904 6905 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 6906 return; 6907 6908 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6909 return; 6910 6911 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6912 msleep(1); 6913 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6914 6915 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6916 6917 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6918 return; 6919 6920 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 6921 6922 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6923 } 6924 6925 static void rtl_hw_init_8125(struct rtl8169_private *tp) 6926 { 6927 tp->ocp_base = OCP_STD_PHY_BASE; 6928 6929 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6930 6931 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6932 return; 6933 6934 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6935 msleep(1); 6936 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6937 6938 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6939 6940 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6941 return; 6942 6943 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 6944 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 6945 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 6946 6947 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6948 } 6949 6950 static void rtl_hw_initialize(struct rtl8169_private *tp) 6951 { 6952 switch (tp->mac_version) { 6953 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51: 6954 rtl8168ep_stop_cmac(tp); 6955 /* fall through */ 6956 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 6957 rtl_hw_init_8168g(tp); 6958 break; 6959 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 6960 rtl_hw_init_8125(tp); 6961 break; 6962 default: 6963 break; 6964 } 6965 } 6966 6967 static int rtl_jumbo_max(struct rtl8169_private *tp) 6968 { 6969 /* Non-GBit versions don't support jumbo frames */ 6970 if (!tp->supports_gmii) 6971 return JUMBO_1K; 6972 6973 switch (tp->mac_version) { 6974 /* RTL8169 */ 6975 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6976 return JUMBO_7K; 6977 /* RTL8168b */ 6978 case RTL_GIGA_MAC_VER_11: 6979 case RTL_GIGA_MAC_VER_12: 6980 case RTL_GIGA_MAC_VER_17: 6981 return JUMBO_4K; 6982 /* RTL8168c */ 6983 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 6984 return JUMBO_6K; 6985 default: 6986 return JUMBO_9K; 6987 } 6988 } 6989 6990 static void rtl_disable_clk(void *data) 6991 { 6992 clk_disable_unprepare(data); 6993 } 6994 6995 static int rtl_get_ether_clk(struct rtl8169_private *tp) 6996 { 6997 struct device *d = tp_to_dev(tp); 6998 struct clk *clk; 6999 int rc; 7000 7001 clk = devm_clk_get(d, "ether_clk"); 7002 if (IS_ERR(clk)) { 7003 rc = PTR_ERR(clk); 7004 if (rc == -ENOENT) 7005 /* clk-core allows NULL (for suspend / resume) */ 7006 rc = 0; 7007 else if (rc != -EPROBE_DEFER) 7008 dev_err(d, "failed to get clk: %d\n", rc); 7009 } else { 7010 tp->clk = clk; 7011 rc = clk_prepare_enable(clk); 7012 if (rc) 7013 dev_err(d, "failed to enable clk: %d\n", rc); 7014 else 7015 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 7016 } 7017 7018 return rc; 7019 } 7020 7021 static void rtl_init_mac_address(struct rtl8169_private *tp) 7022 { 7023 struct net_device *dev = tp->dev; 7024 u8 *mac_addr = dev->dev_addr; 7025 int rc; 7026 7027 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 7028 if (!rc) 7029 goto done; 7030 7031 rtl_read_mac_address(tp, mac_addr); 7032 if (is_valid_ether_addr(mac_addr)) 7033 goto done; 7034 7035 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 7036 if (is_valid_ether_addr(mac_addr)) 7037 goto done; 7038 7039 eth_hw_addr_random(dev); 7040 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 7041 done: 7042 rtl_rar_set(tp, mac_addr); 7043 } 7044 7045 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 7046 { 7047 struct rtl8169_private *tp; 7048 struct net_device *dev; 7049 int chipset, region; 7050 int jumbo_max, rc; 7051 7052 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 7053 if (!dev) 7054 return -ENOMEM; 7055 7056 SET_NETDEV_DEV(dev, &pdev->dev); 7057 dev->netdev_ops = &rtl_netdev_ops; 7058 tp = netdev_priv(dev); 7059 tp->dev = dev; 7060 tp->pci_dev = pdev; 7061 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 7062 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 7063 7064 /* Get the *optional* external "ether_clk" used on some boards */ 7065 rc = rtl_get_ether_clk(tp); 7066 if (rc) 7067 return rc; 7068 7069 /* Disable ASPM completely as that cause random device stop working 7070 * problems as well as full system hangs for some PCIe devices users. 7071 */ 7072 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 7073 PCIE_LINK_STATE_L1); 7074 tp->aspm_manageable = !rc; 7075 7076 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 7077 rc = pcim_enable_device(pdev); 7078 if (rc < 0) { 7079 dev_err(&pdev->dev, "enable failure\n"); 7080 return rc; 7081 } 7082 7083 if (pcim_set_mwi(pdev) < 0) 7084 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 7085 7086 /* use first MMIO region */ 7087 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 7088 if (region < 0) { 7089 dev_err(&pdev->dev, "no MMIO resource found\n"); 7090 return -ENODEV; 7091 } 7092 7093 /* check for weird/broken PCI region reporting */ 7094 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 7095 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 7096 return -ENODEV; 7097 } 7098 7099 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 7100 if (rc < 0) { 7101 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 7102 return rc; 7103 } 7104 7105 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 7106 7107 /* Identify chip attached to board */ 7108 rtl8169_get_mac_version(tp); 7109 if (tp->mac_version == RTL_GIGA_MAC_NONE) 7110 return -ENODEV; 7111 7112 tp->cp_cmd = RTL_R16(tp, CPlusCmd); 7113 7114 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 7115 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 7116 dev->features |= NETIF_F_HIGHDMA; 7117 7118 rtl_init_rxcfg(tp); 7119 7120 rtl8169_irq_mask_and_ack(tp); 7121 7122 rtl_hw_initialize(tp); 7123 7124 rtl_hw_reset(tp); 7125 7126 pci_set_master(pdev); 7127 7128 chipset = tp->mac_version; 7129 7130 rc = rtl_alloc_irq(tp); 7131 if (rc < 0) { 7132 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 7133 return rc; 7134 } 7135 7136 mutex_init(&tp->wk.mutex); 7137 INIT_WORK(&tp->wk.work, rtl_task); 7138 u64_stats_init(&tp->rx_stats.syncp); 7139 u64_stats_init(&tp->tx_stats.syncp); 7140 7141 rtl_init_mac_address(tp); 7142 7143 dev->ethtool_ops = &rtl8169_ethtool_ops; 7144 7145 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 7146 7147 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7148 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 7149 NETIF_F_HW_VLAN_CTAG_RX; 7150 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7151 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 7152 NETIF_F_HW_VLAN_CTAG_RX; 7153 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7154 NETIF_F_HIGHDMA; 7155 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 7156 7157 tp->cp_cmd |= RxChkSum; 7158 /* RTL8125 uses register RxConfig for VLAN offloading config */ 7159 if (!rtl_is_8125(tp)) 7160 tp->cp_cmd |= RxVlan; 7161 /* 7162 * Pretend we are using VLANs; This bypasses a nasty bug where 7163 * Interrupts stop flowing on high load on 8110SCd controllers. 7164 */ 7165 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 7166 /* Disallow toggling */ 7167 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 7168 7169 if (rtl_chip_supports_csum_v2(tp)) { 7170 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 7171 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 7172 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 7173 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 7174 } else { 7175 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 7176 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 7177 } 7178 7179 /* RTL8168e-vl has a HW issue with TSO */ 7180 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { 7181 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7182 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7183 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7184 } 7185 7186 dev->hw_features |= NETIF_F_RXALL; 7187 dev->hw_features |= NETIF_F_RXFCS; 7188 7189 /* MTU range: 60 - hw-specific max */ 7190 dev->min_mtu = ETH_ZLEN; 7191 jumbo_max = rtl_jumbo_max(tp); 7192 dev->max_mtu = jumbo_max; 7193 7194 rtl_set_irq_mask(tp); 7195 7196 tp->fw_name = rtl_chip_infos[chipset].fw_name; 7197 7198 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 7199 &tp->counters_phys_addr, 7200 GFP_KERNEL); 7201 if (!tp->counters) 7202 return -ENOMEM; 7203 7204 pci_set_drvdata(pdev, dev); 7205 7206 rc = r8169_mdio_register(tp); 7207 if (rc) 7208 return rc; 7209 7210 /* chip gets powered up in rtl_open() */ 7211 rtl_pll_power_down(tp); 7212 7213 rc = register_netdev(dev); 7214 if (rc) 7215 goto err_mdio_unregister; 7216 7217 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 7218 rtl_chip_infos[chipset].name, dev->dev_addr, 7219 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf, 7220 pci_irq_vector(pdev, 0)); 7221 7222 if (jumbo_max > JUMBO_1K) 7223 netif_info(tp, probe, dev, 7224 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 7225 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 7226 "ok" : "ko"); 7227 7228 if (r8168_check_dash(tp)) 7229 rtl8168_driver_start(tp); 7230 7231 if (pci_dev_run_wake(pdev)) 7232 pm_runtime_put_sync(&pdev->dev); 7233 7234 return 0; 7235 7236 err_mdio_unregister: 7237 mdiobus_unregister(tp->phydev->mdio.bus); 7238 return rc; 7239 } 7240 7241 static struct pci_driver rtl8169_pci_driver = { 7242 .name = MODULENAME, 7243 .id_table = rtl8169_pci_tbl, 7244 .probe = rtl_init_one, 7245 .remove = rtl_remove_one, 7246 .shutdown = rtl_shutdown, 7247 .driver.pm = RTL8169_PM_OPS, 7248 }; 7249 7250 module_pci_driver(rtl8169_pci_driver); 7251