1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 52 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 62 #define MC_FILTER_LIMIT 32 63 64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 66 67 #define R8169_REGS_SIZE 256 68 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 69 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 70 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 73 74 #define OCP_STD_PHY_BASE 0xa400 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 91 static const struct { 92 const char *name; 93 const char *fw_name; 94 } rtl_chip_infos[] = { 95 /* PCI devices. */ 96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 101 /* PCI-E devices. */ 102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 109 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 110 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 111 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 112 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 118 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 119 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 120 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 121 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 122 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 123 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 124 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 125 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 126 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 127 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 128 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 129 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 130 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 131 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 132 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 133 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 134 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 135 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 136 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 137 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 138 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 139 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 140 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 141 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 142 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 143 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 144 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 145 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 146 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 147 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 148 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 149 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 150 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 151 }; 152 153 static const struct pci_device_id rtl8169_pci_tbl[] = { 154 { PCI_VDEVICE(REALTEK, 0x2502) }, 155 { PCI_VDEVICE(REALTEK, 0x2600) }, 156 { PCI_VDEVICE(REALTEK, 0x8129) }, 157 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 158 { PCI_VDEVICE(REALTEK, 0x8161) }, 159 { PCI_VDEVICE(REALTEK, 0x8167) }, 160 { PCI_VDEVICE(REALTEK, 0x8168) }, 161 { PCI_VDEVICE(NCUBE, 0x8168) }, 162 { PCI_VDEVICE(REALTEK, 0x8169) }, 163 { PCI_VENDOR_ID_DLINK, 0x4300, 164 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 165 { PCI_VDEVICE(DLINK, 0x4300) }, 166 { PCI_VDEVICE(DLINK, 0x4302) }, 167 { PCI_VDEVICE(AT, 0xc107) }, 168 { PCI_VDEVICE(USR, 0x0116) }, 169 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 170 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 171 { PCI_VDEVICE(REALTEK, 0x8125) }, 172 { PCI_VDEVICE(REALTEK, 0x3000) }, 173 {} 174 }; 175 176 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 177 178 enum rtl_registers { 179 MAC0 = 0, /* Ethernet hardware address. */ 180 MAC4 = 4, 181 MAR0 = 8, /* Multicast filter. */ 182 CounterAddrLow = 0x10, 183 CounterAddrHigh = 0x14, 184 TxDescStartAddrLow = 0x20, 185 TxDescStartAddrHigh = 0x24, 186 TxHDescStartAddrLow = 0x28, 187 TxHDescStartAddrHigh = 0x2c, 188 FLASH = 0x30, 189 ERSR = 0x36, 190 ChipCmd = 0x37, 191 TxPoll = 0x38, 192 IntrMask = 0x3c, 193 IntrStatus = 0x3e, 194 195 TxConfig = 0x40, 196 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 197 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 198 199 RxConfig = 0x44, 200 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 201 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 202 #define RXCFG_FIFO_SHIFT 13 203 /* No threshold before first PCI xfer */ 204 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 205 #define RX_EARLY_OFF (1 << 11) 206 #define RXCFG_DMA_SHIFT 8 207 /* Unlimited maximum PCI burst. */ 208 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 209 210 Cfg9346 = 0x50, 211 Config0 = 0x51, 212 Config1 = 0x52, 213 Config2 = 0x53, 214 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 215 216 Config3 = 0x54, 217 Config4 = 0x55, 218 Config5 = 0x56, 219 PHYAR = 0x60, 220 PHYstatus = 0x6c, 221 RxMaxSize = 0xda, 222 CPlusCmd = 0xe0, 223 IntrMitigate = 0xe2, 224 225 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 226 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 227 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 228 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 229 230 #define RTL_COALESCE_T_MAX 0x0fU 231 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 232 233 RxDescAddrLow = 0xe4, 234 RxDescAddrHigh = 0xe8, 235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 236 237 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 238 239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 240 241 #define TxPacketMax (8064 >> 7) 242 #define EarlySize 0x27 243 244 FuncEvent = 0xf0, 245 FuncEventMask = 0xf4, 246 FuncPresetState = 0xf8, 247 IBCR0 = 0xf8, 248 IBCR2 = 0xf9, 249 IBIMR0 = 0xfa, 250 IBISR0 = 0xfb, 251 FuncForceEvent = 0xfc, 252 }; 253 254 enum rtl8168_8101_registers { 255 CSIDR = 0x64, 256 CSIAR = 0x68, 257 #define CSIAR_FLAG 0x80000000 258 #define CSIAR_WRITE_CMD 0x80000000 259 #define CSIAR_BYTE_ENABLE 0x0000f000 260 #define CSIAR_ADDR_MASK 0x00000fff 261 PMCH = 0x6f, 262 #define D3COLD_NO_PLL_DOWN BIT(7) 263 #define D3HOT_NO_PLL_DOWN BIT(6) 264 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 265 EPHYAR = 0x80, 266 #define EPHYAR_FLAG 0x80000000 267 #define EPHYAR_WRITE_CMD 0x80000000 268 #define EPHYAR_REG_MASK 0x1f 269 #define EPHYAR_REG_SHIFT 16 270 #define EPHYAR_DATA_MASK 0xffff 271 DLLPR = 0xd0, 272 #define PFM_EN (1 << 6) 273 #define TX_10M_PS_EN (1 << 7) 274 DBG_REG = 0xd1, 275 #define FIX_NAK_1 (1 << 4) 276 #define FIX_NAK_2 (1 << 3) 277 TWSI = 0xd2, 278 MCU = 0xd3, 279 #define NOW_IS_OOB (1 << 7) 280 #define TX_EMPTY (1 << 5) 281 #define RX_EMPTY (1 << 4) 282 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 283 #define EN_NDP (1 << 3) 284 #define EN_OOB_RESET (1 << 2) 285 #define LINK_LIST_RDY (1 << 1) 286 EFUSEAR = 0xdc, 287 #define EFUSEAR_FLAG 0x80000000 288 #define EFUSEAR_WRITE_CMD 0x80000000 289 #define EFUSEAR_READ_CMD 0x00000000 290 #define EFUSEAR_REG_MASK 0x03ff 291 #define EFUSEAR_REG_SHIFT 8 292 #define EFUSEAR_DATA_MASK 0xff 293 MISC_1 = 0xf2, 294 #define PFM_D3COLD_EN (1 << 6) 295 }; 296 297 enum rtl8168_registers { 298 LED_FREQ = 0x1a, 299 EEE_LED = 0x1b, 300 ERIDR = 0x70, 301 ERIAR = 0x74, 302 #define ERIAR_FLAG 0x80000000 303 #define ERIAR_WRITE_CMD 0x80000000 304 #define ERIAR_READ_CMD 0x00000000 305 #define ERIAR_ADDR_BYTE_ALIGN 4 306 #define ERIAR_TYPE_SHIFT 16 307 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 310 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_MASK_SHIFT 12 312 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 315 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 317 EPHY_RXER_NUM = 0x7c, 318 OCPDR = 0xb0, /* OCP GPHY access */ 319 #define OCPDR_WRITE_CMD 0x80000000 320 #define OCPDR_READ_CMD 0x00000000 321 #define OCPDR_REG_MASK 0x7f 322 #define OCPDR_GPHY_REG_SHIFT 16 323 #define OCPDR_DATA_MASK 0xffff 324 OCPAR = 0xb4, 325 #define OCPAR_FLAG 0x80000000 326 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 327 #define OCPAR_GPHY_READ_CMD 0x0000f060 328 GPHY_OCP = 0xb8, 329 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 330 MISC = 0xf0, /* 8168e only. */ 331 #define TXPLA_RST (1 << 29) 332 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 333 #define PWM_EN (1 << 22) 334 #define RXDV_GATED_EN (1 << 19) 335 #define EARLY_TALLY_EN (1 << 16) 336 }; 337 338 enum rtl8125_registers { 339 IntrMask_8125 = 0x38, 340 IntrStatus_8125 = 0x3c, 341 TxPoll_8125 = 0x90, 342 MAC0_BKP = 0x19e0, 343 EEE_TXIDLE_TIMER_8125 = 0x6048, 344 }; 345 346 #define RX_VLAN_INNER_8125 BIT(22) 347 #define RX_VLAN_OUTER_8125 BIT(23) 348 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 349 350 #define RX_FETCH_DFLT_8125 (8 << 27) 351 352 enum rtl_register_content { 353 /* InterruptStatusBits */ 354 SYSErr = 0x8000, 355 PCSTimeout = 0x4000, 356 SWInt = 0x0100, 357 TxDescUnavail = 0x0080, 358 RxFIFOOver = 0x0040, 359 LinkChg = 0x0020, 360 RxOverflow = 0x0010, 361 TxErr = 0x0008, 362 TxOK = 0x0004, 363 RxErr = 0x0002, 364 RxOK = 0x0001, 365 366 /* RxStatusDesc */ 367 RxRWT = (1 << 22), 368 RxRES = (1 << 21), 369 RxRUNT = (1 << 20), 370 RxCRC = (1 << 19), 371 372 /* ChipCmdBits */ 373 StopReq = 0x80, 374 CmdReset = 0x10, 375 CmdRxEnb = 0x08, 376 CmdTxEnb = 0x04, 377 RxBufEmpty = 0x01, 378 379 /* TXPoll register p.5 */ 380 HPQ = 0x80, /* Poll cmd on the high prio queue */ 381 NPQ = 0x40, /* Poll cmd on the low prio queue */ 382 FSWInt = 0x01, /* Forced software interrupt */ 383 384 /* Cfg9346Bits */ 385 Cfg9346_Lock = 0x00, 386 Cfg9346_Unlock = 0xc0, 387 388 /* rx_mode_bits */ 389 AcceptErr = 0x20, 390 AcceptRunt = 0x10, 391 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 392 AcceptBroadcast = 0x08, 393 AcceptMulticast = 0x04, 394 AcceptMyPhys = 0x02, 395 AcceptAllPhys = 0x01, 396 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 397 #define RX_CONFIG_ACCEPT_MASK 0x3f 398 399 /* TxConfigBits */ 400 TxInterFrameGapShift = 24, 401 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 402 403 /* Config1 register p.24 */ 404 LEDS1 = (1 << 7), 405 LEDS0 = (1 << 6), 406 Speed_down = (1 << 4), 407 MEMMAP = (1 << 3), 408 IOMAP = (1 << 2), 409 VPD = (1 << 1), 410 PMEnable = (1 << 0), /* Power Management Enable */ 411 412 /* Config2 register p. 25 */ 413 ClkReqEn = (1 << 7), /* Clock Request Enable */ 414 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 415 PCI_Clock_66MHz = 0x01, 416 PCI_Clock_33MHz = 0x00, 417 418 /* Config3 register p.25 */ 419 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 420 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 421 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 422 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 423 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 424 425 /* Config4 register */ 426 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 427 428 /* Config5 register p.27 */ 429 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 430 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 431 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 432 Spi_en = (1 << 3), 433 LanWake = (1 << 1), /* LanWake enable/disable */ 434 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 435 ASPM_en = (1 << 0), /* ASPM enable */ 436 437 /* CPlusCmd p.31 */ 438 EnableBist = (1 << 15), // 8168 8101 439 Mac_dbgo_oe = (1 << 14), // 8168 8101 440 EnAnaPLL = (1 << 14), // 8169 441 Normal_mode = (1 << 13), // unused 442 Force_half_dup = (1 << 12), // 8168 8101 443 Force_rxflow_en = (1 << 11), // 8168 8101 444 Force_txflow_en = (1 << 10), // 8168 8101 445 Cxpl_dbg_sel = (1 << 9), // 8168 8101 446 ASF = (1 << 8), // 8168 8101 447 PktCntrDisable = (1 << 7), // 8168 8101 448 Mac_dbgo_sel = 0x001c, // 8168 449 RxVlan = (1 << 6), 450 RxChkSum = (1 << 5), 451 PCIDAC = (1 << 4), 452 PCIMulRW = (1 << 3), 453 #define INTT_MASK GENMASK(1, 0) 454 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 455 456 /* rtl8169_PHYstatus */ 457 TBI_Enable = 0x80, 458 TxFlowCtrl = 0x40, 459 RxFlowCtrl = 0x20, 460 _1000bpsF = 0x10, 461 _100bps = 0x08, 462 _10bps = 0x04, 463 LinkStatus = 0x02, 464 FullDup = 0x01, 465 466 /* ResetCounterCommand */ 467 CounterReset = 0x1, 468 469 /* DumpCounterCommand */ 470 CounterDump = 0x8, 471 472 /* magic enable v2 */ 473 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 474 }; 475 476 enum rtl_desc_bit { 477 /* First doubleword. */ 478 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 479 RingEnd = (1 << 30), /* End of descriptor ring */ 480 FirstFrag = (1 << 29), /* First segment of a packet */ 481 LastFrag = (1 << 28), /* Final segment of a packet */ 482 }; 483 484 /* Generic case. */ 485 enum rtl_tx_desc_bit { 486 /* First doubleword. */ 487 TD_LSO = (1 << 27), /* Large Send Offload */ 488 #define TD_MSS_MAX 0x07ffu /* MSS value */ 489 490 /* Second doubleword. */ 491 TxVlanTag = (1 << 17), /* Add VLAN tag */ 492 }; 493 494 /* 8169, 8168b and 810x except 8102e. */ 495 enum rtl_tx_desc_bit_0 { 496 /* First doubleword. */ 497 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 498 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 499 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 500 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 501 }; 502 503 /* 8102e, 8168c and beyond. */ 504 enum rtl_tx_desc_bit_1 { 505 /* First doubleword. */ 506 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 507 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 508 #define GTTCPHO_SHIFT 18 509 #define GTTCPHO_MAX 0x7f 510 511 /* Second doubleword. */ 512 #define TCPHO_SHIFT 18 513 #define TCPHO_MAX 0x3ff 514 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 515 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 516 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 517 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 518 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 519 }; 520 521 enum rtl_rx_desc_bit { 522 /* Rx private */ 523 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 524 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 525 526 #define RxProtoUDP (PID1) 527 #define RxProtoTCP (PID0) 528 #define RxProtoIP (PID1 | PID0) 529 #define RxProtoMask RxProtoIP 530 531 IPFail = (1 << 16), /* IP checksum failed */ 532 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 533 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 534 535 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 536 537 RxVlanTag = (1 << 16), /* VLAN tag available */ 538 }; 539 540 #define RTL_GSO_MAX_SIZE_V1 32000 541 #define RTL_GSO_MAX_SEGS_V1 24 542 #define RTL_GSO_MAX_SIZE_V2 64000 543 #define RTL_GSO_MAX_SEGS_V2 64 544 545 struct TxDesc { 546 __le32 opts1; 547 __le32 opts2; 548 __le64 addr; 549 }; 550 551 struct RxDesc { 552 __le32 opts1; 553 __le32 opts2; 554 __le64 addr; 555 }; 556 557 struct ring_info { 558 struct sk_buff *skb; 559 u32 len; 560 }; 561 562 struct rtl8169_counters { 563 __le64 tx_packets; 564 __le64 rx_packets; 565 __le64 tx_errors; 566 __le32 rx_errors; 567 __le16 rx_missed; 568 __le16 align_errors; 569 __le32 tx_one_collision; 570 __le32 tx_multi_collision; 571 __le64 rx_unicast; 572 __le64 rx_broadcast; 573 __le32 rx_multicast; 574 __le16 tx_aborted; 575 __le16 tx_underun; 576 }; 577 578 struct rtl8169_tc_offsets { 579 bool inited; 580 __le64 tx_errors; 581 __le32 tx_multi_collision; 582 __le16 tx_aborted; 583 __le16 rx_missed; 584 }; 585 586 enum rtl_flag { 587 RTL_FLAG_TASK_ENABLED = 0, 588 RTL_FLAG_TASK_RESET_PENDING, 589 RTL_FLAG_MAX 590 }; 591 592 enum rtl_dash_type { 593 RTL_DASH_NONE, 594 RTL_DASH_DP, 595 RTL_DASH_EP, 596 }; 597 598 struct rtl8169_private { 599 void __iomem *mmio_addr; /* memory map physical address */ 600 struct pci_dev *pci_dev; 601 struct net_device *dev; 602 struct phy_device *phydev; 603 struct napi_struct napi; 604 enum mac_version mac_version; 605 enum rtl_dash_type dash_type; 606 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 607 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 608 u32 dirty_tx; 609 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 610 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 611 dma_addr_t TxPhyAddr; 612 dma_addr_t RxPhyAddr; 613 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 614 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 615 u16 cp_cmd; 616 u32 irq_mask; 617 struct clk *clk; 618 619 struct { 620 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 621 struct work_struct work; 622 } wk; 623 624 unsigned supports_gmii:1; 625 unsigned aspm_manageable:1; 626 dma_addr_t counters_phys_addr; 627 struct rtl8169_counters *counters; 628 struct rtl8169_tc_offsets tc_offset; 629 u32 saved_wolopts; 630 int eee_adv; 631 632 const char *fw_name; 633 struct rtl_fw *rtl_fw; 634 635 u32 ocp_base; 636 }; 637 638 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 639 640 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 641 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 642 MODULE_SOFTDEP("pre: realtek"); 643 MODULE_LICENSE("GPL"); 644 MODULE_FIRMWARE(FIRMWARE_8168D_1); 645 MODULE_FIRMWARE(FIRMWARE_8168D_2); 646 MODULE_FIRMWARE(FIRMWARE_8168E_1); 647 MODULE_FIRMWARE(FIRMWARE_8168E_2); 648 MODULE_FIRMWARE(FIRMWARE_8168E_3); 649 MODULE_FIRMWARE(FIRMWARE_8105E_1); 650 MODULE_FIRMWARE(FIRMWARE_8168F_1); 651 MODULE_FIRMWARE(FIRMWARE_8168F_2); 652 MODULE_FIRMWARE(FIRMWARE_8402_1); 653 MODULE_FIRMWARE(FIRMWARE_8411_1); 654 MODULE_FIRMWARE(FIRMWARE_8411_2); 655 MODULE_FIRMWARE(FIRMWARE_8106E_1); 656 MODULE_FIRMWARE(FIRMWARE_8106E_2); 657 MODULE_FIRMWARE(FIRMWARE_8168G_2); 658 MODULE_FIRMWARE(FIRMWARE_8168G_3); 659 MODULE_FIRMWARE(FIRMWARE_8168H_1); 660 MODULE_FIRMWARE(FIRMWARE_8168H_2); 661 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 662 MODULE_FIRMWARE(FIRMWARE_8107E_1); 663 MODULE_FIRMWARE(FIRMWARE_8107E_2); 664 MODULE_FIRMWARE(FIRMWARE_8125A_3); 665 MODULE_FIRMWARE(FIRMWARE_8125B_2); 666 667 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 668 { 669 return &tp->pci_dev->dev; 670 } 671 672 static void rtl_lock_config_regs(struct rtl8169_private *tp) 673 { 674 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 675 } 676 677 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 678 { 679 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 680 } 681 682 static void rtl_pci_commit(struct rtl8169_private *tp) 683 { 684 /* Read an arbitrary register to commit a preceding PCI write */ 685 RTL_R8(tp, ChipCmd); 686 } 687 688 static bool rtl_is_8125(struct rtl8169_private *tp) 689 { 690 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 691 } 692 693 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 694 { 695 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 696 tp->mac_version != RTL_GIGA_MAC_VER_39 && 697 tp->mac_version <= RTL_GIGA_MAC_VER_53; 698 } 699 700 static bool rtl_supports_eee(struct rtl8169_private *tp) 701 { 702 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 703 tp->mac_version != RTL_GIGA_MAC_VER_37 && 704 tp->mac_version != RTL_GIGA_MAC_VER_39; 705 } 706 707 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 708 { 709 int i; 710 711 for (i = 0; i < ETH_ALEN; i++) 712 mac[i] = RTL_R8(tp, reg + i); 713 } 714 715 struct rtl_cond { 716 bool (*check)(struct rtl8169_private *); 717 const char *msg; 718 }; 719 720 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 721 unsigned long usecs, int n, bool high) 722 { 723 int i; 724 725 for (i = 0; i < n; i++) { 726 if (c->check(tp) == high) 727 return true; 728 fsleep(usecs); 729 } 730 731 if (net_ratelimit()) 732 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 733 c->msg, !high, n, usecs); 734 return false; 735 } 736 737 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 738 const struct rtl_cond *c, 739 unsigned long d, int n) 740 { 741 return rtl_loop_wait(tp, c, d, n, true); 742 } 743 744 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 745 const struct rtl_cond *c, 746 unsigned long d, int n) 747 { 748 return rtl_loop_wait(tp, c, d, n, false); 749 } 750 751 #define DECLARE_RTL_COND(name) \ 752 static bool name ## _check(struct rtl8169_private *); \ 753 \ 754 static const struct rtl_cond name = { \ 755 .check = name ## _check, \ 756 .msg = #name \ 757 }; \ 758 \ 759 static bool name ## _check(struct rtl8169_private *tp) 760 761 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 762 { 763 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 764 if (type == ERIAR_OOB && 765 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 766 tp->mac_version == RTL_GIGA_MAC_VER_53)) 767 *cmd |= 0xf70 << 18; 768 } 769 770 DECLARE_RTL_COND(rtl_eriar_cond) 771 { 772 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 773 } 774 775 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 776 u32 val, int type) 777 { 778 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 779 780 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 781 return; 782 783 RTL_W32(tp, ERIDR, val); 784 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 785 RTL_W32(tp, ERIAR, cmd); 786 787 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 788 } 789 790 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 791 u32 val) 792 { 793 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 794 } 795 796 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 797 { 798 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 799 800 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 801 RTL_W32(tp, ERIAR, cmd); 802 803 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 804 RTL_R32(tp, ERIDR) : ~0; 805 } 806 807 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 808 { 809 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 810 } 811 812 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 813 { 814 u32 val = rtl_eri_read(tp, addr); 815 816 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 817 } 818 819 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 820 { 821 rtl_w0w1_eri(tp, addr, p, 0); 822 } 823 824 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 825 { 826 rtl_w0w1_eri(tp, addr, 0, m); 827 } 828 829 static bool rtl_ocp_reg_failure(u32 reg) 830 { 831 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 832 } 833 834 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 835 { 836 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 837 } 838 839 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 840 { 841 if (rtl_ocp_reg_failure(reg)) 842 return; 843 844 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 845 846 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 847 } 848 849 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 850 { 851 if (rtl_ocp_reg_failure(reg)) 852 return 0; 853 854 RTL_W32(tp, GPHY_OCP, reg << 15); 855 856 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 857 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 858 } 859 860 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 861 { 862 if (rtl_ocp_reg_failure(reg)) 863 return; 864 865 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 866 } 867 868 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 869 { 870 if (rtl_ocp_reg_failure(reg)) 871 return 0; 872 873 RTL_W32(tp, OCPDR, reg << 15); 874 875 return RTL_R32(tp, OCPDR); 876 } 877 878 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 879 u16 set) 880 { 881 u16 data = r8168_mac_ocp_read(tp, reg); 882 883 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 884 } 885 886 /* Work around a hw issue with RTL8168g PHY, the quirk disables 887 * PHY MCU interrupts before PHY power-down. 888 */ 889 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 890 { 891 switch (tp->mac_version) { 892 case RTL_GIGA_MAC_VER_40: 893 case RTL_GIGA_MAC_VER_41: 894 case RTL_GIGA_MAC_VER_49: 895 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 896 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 897 else 898 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 899 break; 900 default: 901 break; 902 } 903 }; 904 905 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 906 { 907 if (reg == 0x1f) { 908 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 909 return; 910 } 911 912 if (tp->ocp_base != OCP_STD_PHY_BASE) 913 reg -= 0x10; 914 915 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 916 rtl8168g_phy_suspend_quirk(tp, value); 917 918 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 919 } 920 921 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 922 { 923 if (reg == 0x1f) 924 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 925 926 if (tp->ocp_base != OCP_STD_PHY_BASE) 927 reg -= 0x10; 928 929 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 930 } 931 932 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 933 { 934 if (reg == 0x1f) { 935 tp->ocp_base = value << 4; 936 return; 937 } 938 939 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 940 } 941 942 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 943 { 944 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 945 } 946 947 DECLARE_RTL_COND(rtl_phyar_cond) 948 { 949 return RTL_R32(tp, PHYAR) & 0x80000000; 950 } 951 952 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 953 { 954 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 955 956 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 957 /* 958 * According to hardware specs a 20us delay is required after write 959 * complete indication, but before sending next command. 960 */ 961 udelay(20); 962 } 963 964 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 965 { 966 int value; 967 968 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 969 970 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 971 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 972 973 /* 974 * According to hardware specs a 20us delay is required after read 975 * complete indication, but before sending next command. 976 */ 977 udelay(20); 978 979 return value; 980 } 981 982 DECLARE_RTL_COND(rtl_ocpar_cond) 983 { 984 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 985 } 986 987 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 988 989 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 990 { 991 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 992 } 993 994 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 995 { 996 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 997 } 998 999 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1000 { 1001 r8168dp_2_mdio_start(tp); 1002 1003 r8169_mdio_write(tp, reg, value); 1004 1005 r8168dp_2_mdio_stop(tp); 1006 } 1007 1008 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1009 { 1010 int value; 1011 1012 /* Work around issue with chip reporting wrong PHY ID */ 1013 if (reg == MII_PHYSID2) 1014 return 0xc912; 1015 1016 r8168dp_2_mdio_start(tp); 1017 1018 value = r8169_mdio_read(tp, reg); 1019 1020 r8168dp_2_mdio_stop(tp); 1021 1022 return value; 1023 } 1024 1025 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1026 { 1027 switch (tp->mac_version) { 1028 case RTL_GIGA_MAC_VER_28: 1029 case RTL_GIGA_MAC_VER_31: 1030 r8168dp_2_mdio_write(tp, location, val); 1031 break; 1032 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1033 r8168g_mdio_write(tp, location, val); 1034 break; 1035 default: 1036 r8169_mdio_write(tp, location, val); 1037 break; 1038 } 1039 } 1040 1041 static int rtl_readphy(struct rtl8169_private *tp, int location) 1042 { 1043 switch (tp->mac_version) { 1044 case RTL_GIGA_MAC_VER_28: 1045 case RTL_GIGA_MAC_VER_31: 1046 return r8168dp_2_mdio_read(tp, location); 1047 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1048 return r8168g_mdio_read(tp, location); 1049 default: 1050 return r8169_mdio_read(tp, location); 1051 } 1052 } 1053 1054 DECLARE_RTL_COND(rtl_ephyar_cond) 1055 { 1056 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1057 } 1058 1059 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1060 { 1061 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1062 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1063 1064 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1065 1066 udelay(10); 1067 } 1068 1069 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1070 { 1071 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1072 1073 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1074 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1075 } 1076 1077 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1078 { 1079 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1080 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1081 RTL_R32(tp, OCPDR) : ~0; 1082 } 1083 1084 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1085 { 1086 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1087 } 1088 1089 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1090 u32 data) 1091 { 1092 RTL_W32(tp, OCPDR, data); 1093 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1094 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1095 } 1096 1097 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1098 u32 data) 1099 { 1100 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1101 data, ERIAR_OOB); 1102 } 1103 1104 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1105 { 1106 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1107 1108 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1109 } 1110 1111 #define OOB_CMD_RESET 0x00 1112 #define OOB_CMD_DRIVER_START 0x05 1113 #define OOB_CMD_DRIVER_STOP 0x06 1114 1115 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1116 { 1117 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1118 } 1119 1120 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1121 { 1122 u16 reg; 1123 1124 reg = rtl8168_get_ocp_reg(tp); 1125 1126 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1127 } 1128 1129 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1130 { 1131 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1132 } 1133 1134 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1135 { 1136 return RTL_R8(tp, IBISR0) & 0x20; 1137 } 1138 1139 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1140 { 1141 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1142 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1143 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1144 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1145 } 1146 1147 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1148 { 1149 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1150 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1151 } 1152 1153 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1154 { 1155 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1156 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1157 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1158 } 1159 1160 static void rtl8168_driver_start(struct rtl8169_private *tp) 1161 { 1162 if (tp->dash_type == RTL_DASH_DP) 1163 rtl8168dp_driver_start(tp); 1164 else 1165 rtl8168ep_driver_start(tp); 1166 } 1167 1168 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1169 { 1170 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1171 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1172 } 1173 1174 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1175 { 1176 rtl8168ep_stop_cmac(tp); 1177 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1178 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1179 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1180 } 1181 1182 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1183 { 1184 if (tp->dash_type == RTL_DASH_DP) 1185 rtl8168dp_driver_stop(tp); 1186 else 1187 rtl8168ep_driver_stop(tp); 1188 } 1189 1190 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1191 { 1192 u16 reg = rtl8168_get_ocp_reg(tp); 1193 1194 return r8168dp_ocp_read(tp, reg) & BIT(15); 1195 } 1196 1197 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1198 { 1199 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1200 } 1201 1202 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1203 { 1204 switch (tp->mac_version) { 1205 case RTL_GIGA_MAC_VER_28: 1206 case RTL_GIGA_MAC_VER_31: 1207 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1208 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 1209 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1210 default: 1211 return RTL_DASH_NONE; 1212 } 1213 } 1214 1215 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1216 { 1217 switch (tp->mac_version) { 1218 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1219 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1220 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1221 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1222 if (enable) 1223 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1224 else 1225 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1226 break; 1227 default: 1228 break; 1229 } 1230 } 1231 1232 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1233 { 1234 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1235 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1236 } 1237 1238 DECLARE_RTL_COND(rtl_efusear_cond) 1239 { 1240 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1241 } 1242 1243 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1244 { 1245 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1246 1247 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1248 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1249 } 1250 1251 static u32 rtl_get_events(struct rtl8169_private *tp) 1252 { 1253 if (rtl_is_8125(tp)) 1254 return RTL_R32(tp, IntrStatus_8125); 1255 else 1256 return RTL_R16(tp, IntrStatus); 1257 } 1258 1259 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1260 { 1261 if (rtl_is_8125(tp)) 1262 RTL_W32(tp, IntrStatus_8125, bits); 1263 else 1264 RTL_W16(tp, IntrStatus, bits); 1265 } 1266 1267 static void rtl_irq_disable(struct rtl8169_private *tp) 1268 { 1269 if (rtl_is_8125(tp)) 1270 RTL_W32(tp, IntrMask_8125, 0); 1271 else 1272 RTL_W16(tp, IntrMask, 0); 1273 } 1274 1275 static void rtl_irq_enable(struct rtl8169_private *tp) 1276 { 1277 if (rtl_is_8125(tp)) 1278 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1279 else 1280 RTL_W16(tp, IntrMask, tp->irq_mask); 1281 } 1282 1283 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1284 { 1285 rtl_irq_disable(tp); 1286 rtl_ack_events(tp, 0xffffffff); 1287 rtl_pci_commit(tp); 1288 } 1289 1290 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1291 { 1292 struct phy_device *phydev = tp->phydev; 1293 1294 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1295 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1296 if (phydev->speed == SPEED_1000) { 1297 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1298 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1299 } else if (phydev->speed == SPEED_100) { 1300 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1301 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1302 } else { 1303 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1304 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1305 } 1306 rtl_reset_packet_filter(tp); 1307 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1308 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1309 if (phydev->speed == SPEED_1000) { 1310 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1311 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1312 } else { 1313 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1314 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1315 } 1316 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1317 if (phydev->speed == SPEED_10) { 1318 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1319 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1320 } else { 1321 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1322 } 1323 } 1324 } 1325 1326 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1327 1328 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1329 { 1330 struct rtl8169_private *tp = netdev_priv(dev); 1331 1332 wol->supported = WAKE_ANY; 1333 wol->wolopts = tp->saved_wolopts; 1334 } 1335 1336 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1337 { 1338 static const struct { 1339 u32 opt; 1340 u16 reg; 1341 u8 mask; 1342 } cfg[] = { 1343 { WAKE_PHY, Config3, LinkUp }, 1344 { WAKE_UCAST, Config5, UWF }, 1345 { WAKE_BCAST, Config5, BWF }, 1346 { WAKE_MCAST, Config5, MWF }, 1347 { WAKE_ANY, Config5, LanWake }, 1348 { WAKE_MAGIC, Config3, MagicPacket } 1349 }; 1350 unsigned int i, tmp = ARRAY_SIZE(cfg); 1351 u8 options; 1352 1353 rtl_unlock_config_regs(tp); 1354 1355 if (rtl_is_8168evl_up(tp)) { 1356 tmp--; 1357 if (wolopts & WAKE_MAGIC) 1358 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1359 else 1360 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1361 } else if (rtl_is_8125(tp)) { 1362 tmp--; 1363 if (wolopts & WAKE_MAGIC) 1364 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1365 else 1366 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1367 } 1368 1369 for (i = 0; i < tmp; i++) { 1370 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1371 if (wolopts & cfg[i].opt) 1372 options |= cfg[i].mask; 1373 RTL_W8(tp, cfg[i].reg, options); 1374 } 1375 1376 switch (tp->mac_version) { 1377 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1378 options = RTL_R8(tp, Config1) & ~PMEnable; 1379 if (wolopts) 1380 options |= PMEnable; 1381 RTL_W8(tp, Config1, options); 1382 break; 1383 case RTL_GIGA_MAC_VER_34: 1384 case RTL_GIGA_MAC_VER_37: 1385 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1386 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1387 if (wolopts) 1388 options |= PME_SIGNAL; 1389 RTL_W8(tp, Config2, options); 1390 break; 1391 default: 1392 break; 1393 } 1394 1395 rtl_lock_config_regs(tp); 1396 1397 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1398 rtl_set_d3_pll_down(tp, !wolopts); 1399 tp->dev->wol_enabled = wolopts ? 1 : 0; 1400 } 1401 1402 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1403 { 1404 struct rtl8169_private *tp = netdev_priv(dev); 1405 1406 if (wol->wolopts & ~WAKE_ANY) 1407 return -EINVAL; 1408 1409 tp->saved_wolopts = wol->wolopts; 1410 __rtl8169_set_wol(tp, tp->saved_wolopts); 1411 1412 return 0; 1413 } 1414 1415 static void rtl8169_get_drvinfo(struct net_device *dev, 1416 struct ethtool_drvinfo *info) 1417 { 1418 struct rtl8169_private *tp = netdev_priv(dev); 1419 struct rtl_fw *rtl_fw = tp->rtl_fw; 1420 1421 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1422 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1423 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1424 if (rtl_fw) 1425 strlcpy(info->fw_version, rtl_fw->version, 1426 sizeof(info->fw_version)); 1427 } 1428 1429 static int rtl8169_get_regs_len(struct net_device *dev) 1430 { 1431 return R8169_REGS_SIZE; 1432 } 1433 1434 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1435 netdev_features_t features) 1436 { 1437 struct rtl8169_private *tp = netdev_priv(dev); 1438 1439 if (dev->mtu > TD_MSS_MAX) 1440 features &= ~NETIF_F_ALL_TSO; 1441 1442 if (dev->mtu > ETH_DATA_LEN && 1443 tp->mac_version > RTL_GIGA_MAC_VER_06) 1444 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1445 1446 return features; 1447 } 1448 1449 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1450 netdev_features_t features) 1451 { 1452 u32 rx_config = RTL_R32(tp, RxConfig); 1453 1454 if (features & NETIF_F_RXALL) 1455 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1456 else 1457 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1458 1459 if (rtl_is_8125(tp)) { 1460 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1461 rx_config |= RX_VLAN_8125; 1462 else 1463 rx_config &= ~RX_VLAN_8125; 1464 } 1465 1466 RTL_W32(tp, RxConfig, rx_config); 1467 } 1468 1469 static int rtl8169_set_features(struct net_device *dev, 1470 netdev_features_t features) 1471 { 1472 struct rtl8169_private *tp = netdev_priv(dev); 1473 1474 rtl_set_rx_config_features(tp, features); 1475 1476 if (features & NETIF_F_RXCSUM) 1477 tp->cp_cmd |= RxChkSum; 1478 else 1479 tp->cp_cmd &= ~RxChkSum; 1480 1481 if (!rtl_is_8125(tp)) { 1482 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1483 tp->cp_cmd |= RxVlan; 1484 else 1485 tp->cp_cmd &= ~RxVlan; 1486 } 1487 1488 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1489 rtl_pci_commit(tp); 1490 1491 return 0; 1492 } 1493 1494 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1495 { 1496 return (skb_vlan_tag_present(skb)) ? 1497 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1498 } 1499 1500 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1501 { 1502 u32 opts2 = le32_to_cpu(desc->opts2); 1503 1504 if (opts2 & RxVlanTag) 1505 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1506 } 1507 1508 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1509 void *p) 1510 { 1511 struct rtl8169_private *tp = netdev_priv(dev); 1512 u32 __iomem *data = tp->mmio_addr; 1513 u32 *dw = p; 1514 int i; 1515 1516 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1517 memcpy_fromio(dw++, data++, 4); 1518 } 1519 1520 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1521 "tx_packets", 1522 "rx_packets", 1523 "tx_errors", 1524 "rx_errors", 1525 "rx_missed", 1526 "align_errors", 1527 "tx_single_collisions", 1528 "tx_multi_collisions", 1529 "unicast", 1530 "broadcast", 1531 "multicast", 1532 "tx_aborted", 1533 "tx_underrun", 1534 }; 1535 1536 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1537 { 1538 switch (sset) { 1539 case ETH_SS_STATS: 1540 return ARRAY_SIZE(rtl8169_gstrings); 1541 default: 1542 return -EOPNOTSUPP; 1543 } 1544 } 1545 1546 DECLARE_RTL_COND(rtl_counters_cond) 1547 { 1548 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1549 } 1550 1551 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1552 { 1553 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1554 1555 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1556 rtl_pci_commit(tp); 1557 RTL_W32(tp, CounterAddrLow, cmd); 1558 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1559 1560 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1561 } 1562 1563 static void rtl8169_update_counters(struct rtl8169_private *tp) 1564 { 1565 u8 val = RTL_R8(tp, ChipCmd); 1566 1567 /* 1568 * Some chips are unable to dump tally counters when the receiver 1569 * is disabled. If 0xff chip may be in a PCI power-save state. 1570 */ 1571 if (val & CmdRxEnb && val != 0xff) 1572 rtl8169_do_counters(tp, CounterDump); 1573 } 1574 1575 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1576 { 1577 struct rtl8169_counters *counters = tp->counters; 1578 1579 /* 1580 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1581 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1582 * reset by a power cycle, while the counter values collected by the 1583 * driver are reset at every driver unload/load cycle. 1584 * 1585 * To make sure the HW values returned by @get_stats64 match the SW 1586 * values, we collect the initial values at first open(*) and use them 1587 * as offsets to normalize the values returned by @get_stats64. 1588 * 1589 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1590 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1591 * set at open time by rtl_hw_start. 1592 */ 1593 1594 if (tp->tc_offset.inited) 1595 return; 1596 1597 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1598 rtl8169_do_counters(tp, CounterReset); 1599 } else { 1600 rtl8169_update_counters(tp); 1601 tp->tc_offset.tx_errors = counters->tx_errors; 1602 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1603 tp->tc_offset.tx_aborted = counters->tx_aborted; 1604 tp->tc_offset.rx_missed = counters->rx_missed; 1605 } 1606 1607 tp->tc_offset.inited = true; 1608 } 1609 1610 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1611 struct ethtool_stats *stats, u64 *data) 1612 { 1613 struct rtl8169_private *tp = netdev_priv(dev); 1614 struct rtl8169_counters *counters; 1615 1616 counters = tp->counters; 1617 rtl8169_update_counters(tp); 1618 1619 data[0] = le64_to_cpu(counters->tx_packets); 1620 data[1] = le64_to_cpu(counters->rx_packets); 1621 data[2] = le64_to_cpu(counters->tx_errors); 1622 data[3] = le32_to_cpu(counters->rx_errors); 1623 data[4] = le16_to_cpu(counters->rx_missed); 1624 data[5] = le16_to_cpu(counters->align_errors); 1625 data[6] = le32_to_cpu(counters->tx_one_collision); 1626 data[7] = le32_to_cpu(counters->tx_multi_collision); 1627 data[8] = le64_to_cpu(counters->rx_unicast); 1628 data[9] = le64_to_cpu(counters->rx_broadcast); 1629 data[10] = le32_to_cpu(counters->rx_multicast); 1630 data[11] = le16_to_cpu(counters->tx_aborted); 1631 data[12] = le16_to_cpu(counters->tx_underun); 1632 } 1633 1634 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1635 { 1636 switch(stringset) { 1637 case ETH_SS_STATS: 1638 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1639 break; 1640 } 1641 } 1642 1643 /* 1644 * Interrupt coalescing 1645 * 1646 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1647 * > 8169, 8168 and 810x line of chipsets 1648 * 1649 * 8169, 8168, and 8136(810x) serial chipsets support it. 1650 * 1651 * > 2 - the Tx timer unit at gigabit speed 1652 * 1653 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1654 * (0xe0) bit 1 and bit 0. 1655 * 1656 * For 8169 1657 * bit[1:0] \ speed 1000M 100M 10M 1658 * 0 0 320ns 2.56us 40.96us 1659 * 0 1 2.56us 20.48us 327.7us 1660 * 1 0 5.12us 40.96us 655.4us 1661 * 1 1 10.24us 81.92us 1.31ms 1662 * 1663 * For the other 1664 * bit[1:0] \ speed 1000M 100M 10M 1665 * 0 0 5us 2.56us 40.96us 1666 * 0 1 40us 20.48us 327.7us 1667 * 1 0 80us 40.96us 655.4us 1668 * 1 1 160us 81.92us 1.31ms 1669 */ 1670 1671 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1672 struct rtl_coalesce_info { 1673 u32 speed; 1674 u32 scale_nsecs[4]; 1675 }; 1676 1677 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1678 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1679 1680 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1681 { SPEED_1000, COALESCE_DELAY(320) }, 1682 { SPEED_100, COALESCE_DELAY(2560) }, 1683 { SPEED_10, COALESCE_DELAY(40960) }, 1684 { 0 }, 1685 }; 1686 1687 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1688 { SPEED_1000, COALESCE_DELAY(5000) }, 1689 { SPEED_100, COALESCE_DELAY(2560) }, 1690 { SPEED_10, COALESCE_DELAY(40960) }, 1691 { 0 }, 1692 }; 1693 #undef COALESCE_DELAY 1694 1695 /* get rx/tx scale vector corresponding to current speed */ 1696 static const struct rtl_coalesce_info * 1697 rtl_coalesce_info(struct rtl8169_private *tp) 1698 { 1699 const struct rtl_coalesce_info *ci; 1700 1701 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1702 ci = rtl_coalesce_info_8169; 1703 else 1704 ci = rtl_coalesce_info_8168_8136; 1705 1706 /* if speed is unknown assume highest one */ 1707 if (tp->phydev->speed == SPEED_UNKNOWN) 1708 return ci; 1709 1710 for (; ci->speed; ci++) { 1711 if (tp->phydev->speed == ci->speed) 1712 return ci; 1713 } 1714 1715 return ERR_PTR(-ELNRNG); 1716 } 1717 1718 static int rtl_get_coalesce(struct net_device *dev, 1719 struct ethtool_coalesce *ec, 1720 struct kernel_ethtool_coalesce *kernel_coal, 1721 struct netlink_ext_ack *extack) 1722 { 1723 struct rtl8169_private *tp = netdev_priv(dev); 1724 const struct rtl_coalesce_info *ci; 1725 u32 scale, c_us, c_fr; 1726 u16 intrmit; 1727 1728 if (rtl_is_8125(tp)) 1729 return -EOPNOTSUPP; 1730 1731 memset(ec, 0, sizeof(*ec)); 1732 1733 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1734 ci = rtl_coalesce_info(tp); 1735 if (IS_ERR(ci)) 1736 return PTR_ERR(ci); 1737 1738 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1739 1740 intrmit = RTL_R16(tp, IntrMitigate); 1741 1742 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1743 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1744 1745 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1746 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1747 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1748 1749 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1750 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1751 1752 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1753 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1754 1755 return 0; 1756 } 1757 1758 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1759 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1760 u16 *cp01) 1761 { 1762 const struct rtl_coalesce_info *ci; 1763 u16 i; 1764 1765 ci = rtl_coalesce_info(tp); 1766 if (IS_ERR(ci)) 1767 return PTR_ERR(ci); 1768 1769 for (i = 0; i < 4; i++) { 1770 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1771 *cp01 = i; 1772 return ci->scale_nsecs[i]; 1773 } 1774 } 1775 1776 return -ERANGE; 1777 } 1778 1779 static int rtl_set_coalesce(struct net_device *dev, 1780 struct ethtool_coalesce *ec, 1781 struct kernel_ethtool_coalesce *kernel_coal, 1782 struct netlink_ext_ack *extack) 1783 { 1784 struct rtl8169_private *tp = netdev_priv(dev); 1785 u32 tx_fr = ec->tx_max_coalesced_frames; 1786 u32 rx_fr = ec->rx_max_coalesced_frames; 1787 u32 coal_usec_max, units; 1788 u16 w = 0, cp01 = 0; 1789 int scale; 1790 1791 if (rtl_is_8125(tp)) 1792 return -EOPNOTSUPP; 1793 1794 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1795 return -ERANGE; 1796 1797 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1798 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1799 if (scale < 0) 1800 return scale; 1801 1802 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1803 * not only when usecs=0 because of e.g. the following scenario: 1804 * 1805 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1806 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1807 * - then user does `ethtool -C eth0 rx-usecs 100` 1808 * 1809 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1810 * if we want to ignore rx_frames then it has to be set to 0. 1811 */ 1812 if (rx_fr == 1) 1813 rx_fr = 0; 1814 if (tx_fr == 1) 1815 tx_fr = 0; 1816 1817 /* HW requires time limit to be set if frame limit is set */ 1818 if ((tx_fr && !ec->tx_coalesce_usecs) || 1819 (rx_fr && !ec->rx_coalesce_usecs)) 1820 return -EINVAL; 1821 1822 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1823 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1824 1825 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1826 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1827 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1828 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1829 1830 RTL_W16(tp, IntrMitigate, w); 1831 1832 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1833 if (rtl_is_8168evl_up(tp)) { 1834 if (!rx_fr && !tx_fr) 1835 /* disable packet counter */ 1836 tp->cp_cmd |= PktCntrDisable; 1837 else 1838 tp->cp_cmd &= ~PktCntrDisable; 1839 } 1840 1841 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1842 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1843 rtl_pci_commit(tp); 1844 1845 return 0; 1846 } 1847 1848 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1849 { 1850 struct rtl8169_private *tp = netdev_priv(dev); 1851 1852 if (!rtl_supports_eee(tp)) 1853 return -EOPNOTSUPP; 1854 1855 return phy_ethtool_get_eee(tp->phydev, data); 1856 } 1857 1858 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1859 { 1860 struct rtl8169_private *tp = netdev_priv(dev); 1861 int ret; 1862 1863 if (!rtl_supports_eee(tp)) 1864 return -EOPNOTSUPP; 1865 1866 ret = phy_ethtool_set_eee(tp->phydev, data); 1867 1868 if (!ret) 1869 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1870 MDIO_AN_EEE_ADV); 1871 return ret; 1872 } 1873 1874 static void rtl8169_get_ringparam(struct net_device *dev, 1875 struct ethtool_ringparam *data) 1876 { 1877 data->rx_max_pending = NUM_RX_DESC; 1878 data->rx_pending = NUM_RX_DESC; 1879 data->tx_max_pending = NUM_TX_DESC; 1880 data->tx_pending = NUM_TX_DESC; 1881 } 1882 1883 static void rtl8169_get_pauseparam(struct net_device *dev, 1884 struct ethtool_pauseparam *data) 1885 { 1886 struct rtl8169_private *tp = netdev_priv(dev); 1887 bool tx_pause, rx_pause; 1888 1889 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1890 1891 data->autoneg = tp->phydev->autoneg; 1892 data->tx_pause = tx_pause ? 1 : 0; 1893 data->rx_pause = rx_pause ? 1 : 0; 1894 } 1895 1896 static int rtl8169_set_pauseparam(struct net_device *dev, 1897 struct ethtool_pauseparam *data) 1898 { 1899 struct rtl8169_private *tp = netdev_priv(dev); 1900 1901 if (dev->mtu > ETH_DATA_LEN) 1902 return -EOPNOTSUPP; 1903 1904 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1905 1906 return 0; 1907 } 1908 1909 static const struct ethtool_ops rtl8169_ethtool_ops = { 1910 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1911 ETHTOOL_COALESCE_MAX_FRAMES, 1912 .get_drvinfo = rtl8169_get_drvinfo, 1913 .get_regs_len = rtl8169_get_regs_len, 1914 .get_link = ethtool_op_get_link, 1915 .get_coalesce = rtl_get_coalesce, 1916 .set_coalesce = rtl_set_coalesce, 1917 .get_regs = rtl8169_get_regs, 1918 .get_wol = rtl8169_get_wol, 1919 .set_wol = rtl8169_set_wol, 1920 .get_strings = rtl8169_get_strings, 1921 .get_sset_count = rtl8169_get_sset_count, 1922 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1923 .get_ts_info = ethtool_op_get_ts_info, 1924 .nway_reset = phy_ethtool_nway_reset, 1925 .get_eee = rtl8169_get_eee, 1926 .set_eee = rtl8169_set_eee, 1927 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1928 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1929 .get_ringparam = rtl8169_get_ringparam, 1930 .get_pauseparam = rtl8169_get_pauseparam, 1931 .set_pauseparam = rtl8169_set_pauseparam, 1932 }; 1933 1934 static void rtl_enable_eee(struct rtl8169_private *tp) 1935 { 1936 struct phy_device *phydev = tp->phydev; 1937 int adv; 1938 1939 /* respect EEE advertisement the user may have set */ 1940 if (tp->eee_adv >= 0) 1941 adv = tp->eee_adv; 1942 else 1943 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1944 1945 if (adv >= 0) 1946 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1947 } 1948 1949 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1950 { 1951 /* 1952 * The driver currently handles the 8168Bf and the 8168Be identically 1953 * but they can be identified more specifically through the test below 1954 * if needed: 1955 * 1956 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1957 * 1958 * Same thing for the 8101Eb and the 8101Ec: 1959 * 1960 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1961 */ 1962 static const struct rtl_mac_info { 1963 u16 mask; 1964 u16 val; 1965 enum mac_version ver; 1966 } mac_info[] = { 1967 /* 8125B family. */ 1968 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1969 1970 /* 8125A family. */ 1971 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1972 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1973 1974 /* RTL8117 */ 1975 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 1976 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1977 1978 /* 8168EP family. */ 1979 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1980 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1981 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1982 1983 /* 8168H family. */ 1984 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1985 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1986 1987 /* 8168G family. */ 1988 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1989 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1990 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1991 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1992 1993 /* 8168F family. */ 1994 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 1995 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 1996 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 1997 1998 /* 8168E family. */ 1999 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2000 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2001 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2002 2003 /* 8168D family. */ 2004 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2005 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2006 2007 /* 8168DP family. */ 2008 /* It seems this early RTL8168dp version never made it to 2009 * the wild. Support has been removed. 2010 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2011 */ 2012 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2013 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2014 2015 /* 8168C family. */ 2016 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2017 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2018 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2019 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2020 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2021 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2022 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2023 2024 /* 8168B family. */ 2025 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2026 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2027 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2028 2029 /* 8101 family. */ 2030 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2031 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2032 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2033 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2034 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2035 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2036 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2037 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2038 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2039 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2040 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2041 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2042 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2043 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2044 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2045 /* FIXME: where did these entries come from ? -- FR 2046 * Not even r8101 vendor driver knows these id's, 2047 * so let's disable detection for now. -- HK 2048 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2049 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2050 */ 2051 2052 /* 8110 family. */ 2053 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2054 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2055 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2056 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2057 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2058 2059 /* Catch-all */ 2060 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2061 }; 2062 const struct rtl_mac_info *p = mac_info; 2063 enum mac_version ver; 2064 2065 while ((xid & p->mask) != p->val) 2066 p++; 2067 ver = p->ver; 2068 2069 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2070 if (ver == RTL_GIGA_MAC_VER_42) 2071 ver = RTL_GIGA_MAC_VER_43; 2072 else if (ver == RTL_GIGA_MAC_VER_45) 2073 ver = RTL_GIGA_MAC_VER_47; 2074 else if (ver == RTL_GIGA_MAC_VER_46) 2075 ver = RTL_GIGA_MAC_VER_48; 2076 } 2077 2078 return ver; 2079 } 2080 2081 static void rtl_release_firmware(struct rtl8169_private *tp) 2082 { 2083 if (tp->rtl_fw) { 2084 rtl_fw_release_firmware(tp->rtl_fw); 2085 kfree(tp->rtl_fw); 2086 tp->rtl_fw = NULL; 2087 } 2088 } 2089 2090 void r8169_apply_firmware(struct rtl8169_private *tp) 2091 { 2092 int val; 2093 2094 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2095 if (tp->rtl_fw) { 2096 rtl_fw_write_firmware(tp, tp->rtl_fw); 2097 /* At least one firmware doesn't reset tp->ocp_base. */ 2098 tp->ocp_base = OCP_STD_PHY_BASE; 2099 2100 /* PHY soft reset may still be in progress */ 2101 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2102 !(val & BMCR_RESET), 2103 50000, 600000, true); 2104 } 2105 } 2106 2107 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2108 { 2109 /* Adjust EEE LED frequency */ 2110 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2111 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2112 2113 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2114 } 2115 2116 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2117 { 2118 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2119 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2120 } 2121 2122 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2123 { 2124 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2125 } 2126 2127 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2128 { 2129 rtl8125_set_eee_txidle_timer(tp); 2130 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2131 } 2132 2133 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2134 { 2135 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2136 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2137 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2138 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2139 } 2140 2141 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2142 { 2143 u16 data1, data2, ioffset; 2144 2145 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2146 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2147 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2148 2149 ioffset = (data2 >> 1) & 0x7ff8; 2150 ioffset |= data2 & 0x0007; 2151 if (data1 & BIT(7)) 2152 ioffset |= BIT(15); 2153 2154 return ioffset; 2155 } 2156 2157 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2158 { 2159 set_bit(flag, tp->wk.flags); 2160 schedule_work(&tp->wk.work); 2161 } 2162 2163 static void rtl8169_init_phy(struct rtl8169_private *tp) 2164 { 2165 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2166 2167 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2168 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2169 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2170 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2171 RTL_W8(tp, 0x82, 0x01); 2172 } 2173 2174 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2175 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2176 tp->pci_dev->subsystem_device == 0xe000) 2177 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2178 2179 /* We may have called phy_speed_down before */ 2180 phy_speed_up(tp->phydev); 2181 2182 if (rtl_supports_eee(tp)) 2183 rtl_enable_eee(tp); 2184 2185 genphy_soft_reset(tp->phydev); 2186 } 2187 2188 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2189 { 2190 rtl_unlock_config_regs(tp); 2191 2192 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2193 rtl_pci_commit(tp); 2194 2195 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2196 rtl_pci_commit(tp); 2197 2198 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2199 rtl_rar_exgmac_set(tp, addr); 2200 2201 rtl_lock_config_regs(tp); 2202 } 2203 2204 static int rtl_set_mac_address(struct net_device *dev, void *p) 2205 { 2206 struct rtl8169_private *tp = netdev_priv(dev); 2207 int ret; 2208 2209 ret = eth_mac_addr(dev, p); 2210 if (ret) 2211 return ret; 2212 2213 rtl_rar_set(tp, dev->dev_addr); 2214 2215 return 0; 2216 } 2217 2218 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2219 { 2220 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2221 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2222 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2223 } 2224 2225 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2226 { 2227 if (tp->dash_type != RTL_DASH_NONE) 2228 return; 2229 2230 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2231 tp->mac_version == RTL_GIGA_MAC_VER_33) 2232 rtl_ephy_write(tp, 0x19, 0xff64); 2233 2234 if (device_may_wakeup(tp_to_dev(tp))) { 2235 phy_speed_down(tp->phydev, false); 2236 rtl_wol_enable_rx(tp); 2237 } 2238 } 2239 2240 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2241 { 2242 switch (tp->mac_version) { 2243 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2244 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2245 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2246 break; 2247 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2248 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2249 case RTL_GIGA_MAC_VER_38: 2250 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2251 break; 2252 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2253 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2254 break; 2255 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2256 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2257 break; 2258 default: 2259 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2260 break; 2261 } 2262 } 2263 2264 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2265 { 2266 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2267 } 2268 2269 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2270 { 2271 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2272 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2273 } 2274 2275 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2276 { 2277 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2278 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2279 } 2280 2281 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2282 { 2283 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2284 } 2285 2286 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2287 { 2288 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2289 } 2290 2291 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2292 { 2293 RTL_W8(tp, MaxTxPacketSize, 0x24); 2294 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2295 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2296 } 2297 2298 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2299 { 2300 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2301 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2302 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2303 } 2304 2305 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2306 { 2307 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2308 } 2309 2310 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2311 { 2312 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2313 } 2314 2315 static void rtl_jumbo_config(struct rtl8169_private *tp) 2316 { 2317 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2318 int readrq = 4096; 2319 2320 rtl_unlock_config_regs(tp); 2321 switch (tp->mac_version) { 2322 case RTL_GIGA_MAC_VER_12: 2323 case RTL_GIGA_MAC_VER_17: 2324 if (jumbo) { 2325 readrq = 512; 2326 r8168b_1_hw_jumbo_enable(tp); 2327 } else { 2328 r8168b_1_hw_jumbo_disable(tp); 2329 } 2330 break; 2331 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2332 if (jumbo) { 2333 readrq = 512; 2334 r8168c_hw_jumbo_enable(tp); 2335 } else { 2336 r8168c_hw_jumbo_disable(tp); 2337 } 2338 break; 2339 case RTL_GIGA_MAC_VER_28: 2340 if (jumbo) 2341 r8168dp_hw_jumbo_enable(tp); 2342 else 2343 r8168dp_hw_jumbo_disable(tp); 2344 break; 2345 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2346 if (jumbo) 2347 r8168e_hw_jumbo_enable(tp); 2348 else 2349 r8168e_hw_jumbo_disable(tp); 2350 break; 2351 default: 2352 break; 2353 } 2354 rtl_lock_config_regs(tp); 2355 2356 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2357 pcie_set_readrq(tp->pci_dev, readrq); 2358 2359 /* Chip doesn't support pause in jumbo mode */ 2360 if (jumbo) { 2361 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2362 tp->phydev->advertising); 2363 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2364 tp->phydev->advertising); 2365 phy_start_aneg(tp->phydev); 2366 } 2367 } 2368 2369 DECLARE_RTL_COND(rtl_chipcmd_cond) 2370 { 2371 return RTL_R8(tp, ChipCmd) & CmdReset; 2372 } 2373 2374 static void rtl_hw_reset(struct rtl8169_private *tp) 2375 { 2376 RTL_W8(tp, ChipCmd, CmdReset); 2377 2378 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2379 } 2380 2381 static void rtl_request_firmware(struct rtl8169_private *tp) 2382 { 2383 struct rtl_fw *rtl_fw; 2384 2385 /* firmware loaded already or no firmware available */ 2386 if (tp->rtl_fw || !tp->fw_name) 2387 return; 2388 2389 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2390 if (!rtl_fw) 2391 return; 2392 2393 rtl_fw->phy_write = rtl_writephy; 2394 rtl_fw->phy_read = rtl_readphy; 2395 rtl_fw->mac_mcu_write = mac_mcu_write; 2396 rtl_fw->mac_mcu_read = mac_mcu_read; 2397 rtl_fw->fw_name = tp->fw_name; 2398 rtl_fw->dev = tp_to_dev(tp); 2399 2400 if (rtl_fw_request_firmware(rtl_fw)) 2401 kfree(rtl_fw); 2402 else 2403 tp->rtl_fw = rtl_fw; 2404 } 2405 2406 static void rtl_rx_close(struct rtl8169_private *tp) 2407 { 2408 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2409 } 2410 2411 DECLARE_RTL_COND(rtl_npq_cond) 2412 { 2413 return RTL_R8(tp, TxPoll) & NPQ; 2414 } 2415 2416 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2417 { 2418 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2419 } 2420 2421 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2422 { 2423 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2424 } 2425 2426 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2427 { 2428 /* IntrMitigate has new functionality on RTL8125 */ 2429 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2430 } 2431 2432 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2433 { 2434 switch (tp->mac_version) { 2435 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2436 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2437 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2438 break; 2439 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2440 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2441 break; 2442 case RTL_GIGA_MAC_VER_63: 2443 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2444 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2445 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2446 break; 2447 default: 2448 break; 2449 } 2450 } 2451 2452 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2453 { 2454 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2455 fsleep(2000); 2456 rtl_wait_txrx_fifo_empty(tp); 2457 } 2458 2459 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2460 { 2461 u32 val = TX_DMA_BURST << TxDMAShift | 2462 InterFrameGap << TxInterFrameGapShift; 2463 2464 if (rtl_is_8168evl_up(tp)) 2465 val |= TXCFG_AUTO_FIFO; 2466 2467 RTL_W32(tp, TxConfig, val); 2468 } 2469 2470 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2471 { 2472 /* Low hurts. Let's disable the filtering. */ 2473 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2474 } 2475 2476 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2477 { 2478 /* 2479 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2480 * register to be written before TxDescAddrLow to work. 2481 * Switching from MMIO to I/O access fixes the issue as well. 2482 */ 2483 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2484 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2485 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2486 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2487 } 2488 2489 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2490 { 2491 u32 val; 2492 2493 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2494 val = 0x000fff00; 2495 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2496 val = 0x00ffff00; 2497 else 2498 return; 2499 2500 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2501 val |= 0xff; 2502 2503 RTL_W32(tp, 0x7c, val); 2504 } 2505 2506 static void rtl_set_rx_mode(struct net_device *dev) 2507 { 2508 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2509 /* Multicast hash filter */ 2510 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2511 struct rtl8169_private *tp = netdev_priv(dev); 2512 u32 tmp; 2513 2514 if (dev->flags & IFF_PROMISC) { 2515 rx_mode |= AcceptAllPhys; 2516 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2517 dev->flags & IFF_ALLMULTI || 2518 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2519 /* accept all multicasts */ 2520 } else if (netdev_mc_empty(dev)) { 2521 rx_mode &= ~AcceptMulticast; 2522 } else { 2523 struct netdev_hw_addr *ha; 2524 2525 mc_filter[1] = mc_filter[0] = 0; 2526 netdev_for_each_mc_addr(ha, dev) { 2527 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2528 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2529 } 2530 2531 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2532 tmp = mc_filter[0]; 2533 mc_filter[0] = swab32(mc_filter[1]); 2534 mc_filter[1] = swab32(tmp); 2535 } 2536 } 2537 2538 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2539 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2540 2541 tmp = RTL_R32(tp, RxConfig); 2542 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2543 } 2544 2545 DECLARE_RTL_COND(rtl_csiar_cond) 2546 { 2547 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2548 } 2549 2550 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2551 { 2552 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2553 2554 RTL_W32(tp, CSIDR, value); 2555 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2556 CSIAR_BYTE_ENABLE | func << 16); 2557 2558 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2559 } 2560 2561 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2562 { 2563 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2564 2565 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2566 CSIAR_BYTE_ENABLE); 2567 2568 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2569 RTL_R32(tp, CSIDR) : ~0; 2570 } 2571 2572 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2573 { 2574 struct pci_dev *pdev = tp->pci_dev; 2575 u32 csi; 2576 2577 /* According to Realtek the value at config space address 0x070f 2578 * controls the L0s/L1 entrance latency. We try standard ECAM access 2579 * first and if it fails fall back to CSI. 2580 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2581 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2582 */ 2583 if (pdev->cfg_size > 0x070f && 2584 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2585 return; 2586 2587 netdev_notice_once(tp->dev, 2588 "No native access to PCI extended config space, falling back to CSI\n"); 2589 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2590 rtl_csi_write(tp, 0x070c, csi | val << 24); 2591 } 2592 2593 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2594 { 2595 /* L0 7us, L1 16us */ 2596 rtl_set_aspm_entry_latency(tp, 0x27); 2597 } 2598 2599 struct ephy_info { 2600 unsigned int offset; 2601 u16 mask; 2602 u16 bits; 2603 }; 2604 2605 static void __rtl_ephy_init(struct rtl8169_private *tp, 2606 const struct ephy_info *e, int len) 2607 { 2608 u16 w; 2609 2610 while (len-- > 0) { 2611 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2612 rtl_ephy_write(tp, e->offset, w); 2613 e++; 2614 } 2615 } 2616 2617 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2618 2619 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2620 { 2621 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2622 PCI_EXP_LNKCTL_CLKREQ_EN); 2623 } 2624 2625 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2626 { 2627 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2628 PCI_EXP_LNKCTL_CLKREQ_EN); 2629 } 2630 2631 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2632 { 2633 /* work around an issue when PCI reset occurs during L2/L3 state */ 2634 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2635 } 2636 2637 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2638 { 2639 /* Bits control which events trigger ASPM L1 exit: 2640 * Bit 12: rxdv 2641 * Bit 11: ltr_msg 2642 * Bit 10: txdma_poll 2643 * Bit 9: xadm 2644 * Bit 8: pktavi 2645 * Bit 7: txpla 2646 */ 2647 switch (tp->mac_version) { 2648 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2649 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2650 break; 2651 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2652 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2653 break; 2654 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2655 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 2656 break; 2657 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2658 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2659 break; 2660 default: 2661 break; 2662 } 2663 } 2664 2665 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2666 { 2667 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2668 if (enable && tp->aspm_manageable) { 2669 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2670 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2671 } else { 2672 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2673 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2674 } 2675 2676 udelay(10); 2677 } 2678 2679 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2680 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2681 { 2682 /* Usage of dynamic vs. static FIFO is controlled by bit 2683 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2684 */ 2685 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2686 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2687 } 2688 2689 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2690 u8 low, u8 high) 2691 { 2692 /* FIFO thresholds for pause flow control */ 2693 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2694 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2695 } 2696 2697 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2698 { 2699 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2700 } 2701 2702 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2703 { 2704 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2705 2706 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2707 2708 rtl_disable_clock_request(tp); 2709 } 2710 2711 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2712 { 2713 static const struct ephy_info e_info_8168cp[] = { 2714 { 0x01, 0, 0x0001 }, 2715 { 0x02, 0x0800, 0x1000 }, 2716 { 0x03, 0, 0x0042 }, 2717 { 0x06, 0x0080, 0x0000 }, 2718 { 0x07, 0, 0x2000 } 2719 }; 2720 2721 rtl_set_def_aspm_entry_latency(tp); 2722 2723 rtl_ephy_init(tp, e_info_8168cp); 2724 2725 __rtl_hw_start_8168cp(tp); 2726 } 2727 2728 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2729 { 2730 rtl_set_def_aspm_entry_latency(tp); 2731 2732 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2733 } 2734 2735 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2736 { 2737 rtl_set_def_aspm_entry_latency(tp); 2738 2739 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2740 2741 /* Magic. */ 2742 RTL_W8(tp, DBG_REG, 0x20); 2743 } 2744 2745 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2746 { 2747 static const struct ephy_info e_info_8168c_1[] = { 2748 { 0x02, 0x0800, 0x1000 }, 2749 { 0x03, 0, 0x0002 }, 2750 { 0x06, 0x0080, 0x0000 } 2751 }; 2752 2753 rtl_set_def_aspm_entry_latency(tp); 2754 2755 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2756 2757 rtl_ephy_init(tp, e_info_8168c_1); 2758 2759 __rtl_hw_start_8168cp(tp); 2760 } 2761 2762 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2763 { 2764 static const struct ephy_info e_info_8168c_2[] = { 2765 { 0x01, 0, 0x0001 }, 2766 { 0x03, 0x0400, 0x0020 } 2767 }; 2768 2769 rtl_set_def_aspm_entry_latency(tp); 2770 2771 rtl_ephy_init(tp, e_info_8168c_2); 2772 2773 __rtl_hw_start_8168cp(tp); 2774 } 2775 2776 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2777 { 2778 rtl_set_def_aspm_entry_latency(tp); 2779 2780 __rtl_hw_start_8168cp(tp); 2781 } 2782 2783 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2784 { 2785 rtl_set_def_aspm_entry_latency(tp); 2786 2787 rtl_disable_clock_request(tp); 2788 } 2789 2790 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2791 { 2792 static const struct ephy_info e_info_8168d_4[] = { 2793 { 0x0b, 0x0000, 0x0048 }, 2794 { 0x19, 0x0020, 0x0050 }, 2795 { 0x0c, 0x0100, 0x0020 }, 2796 { 0x10, 0x0004, 0x0000 }, 2797 }; 2798 2799 rtl_set_def_aspm_entry_latency(tp); 2800 2801 rtl_ephy_init(tp, e_info_8168d_4); 2802 2803 rtl_enable_clock_request(tp); 2804 } 2805 2806 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2807 { 2808 static const struct ephy_info e_info_8168e_1[] = { 2809 { 0x00, 0x0200, 0x0100 }, 2810 { 0x00, 0x0000, 0x0004 }, 2811 { 0x06, 0x0002, 0x0001 }, 2812 { 0x06, 0x0000, 0x0030 }, 2813 { 0x07, 0x0000, 0x2000 }, 2814 { 0x00, 0x0000, 0x0020 }, 2815 { 0x03, 0x5800, 0x2000 }, 2816 { 0x03, 0x0000, 0x0001 }, 2817 { 0x01, 0x0800, 0x1000 }, 2818 { 0x07, 0x0000, 0x4000 }, 2819 { 0x1e, 0x0000, 0x2000 }, 2820 { 0x19, 0xffff, 0xfe6c }, 2821 { 0x0a, 0x0000, 0x0040 } 2822 }; 2823 2824 rtl_set_def_aspm_entry_latency(tp); 2825 2826 rtl_ephy_init(tp, e_info_8168e_1); 2827 2828 rtl_disable_clock_request(tp); 2829 2830 /* Reset tx FIFO pointer */ 2831 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2832 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2833 2834 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2835 } 2836 2837 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2838 { 2839 static const struct ephy_info e_info_8168e_2[] = { 2840 { 0x09, 0x0000, 0x0080 }, 2841 { 0x19, 0x0000, 0x0224 }, 2842 { 0x00, 0x0000, 0x0004 }, 2843 { 0x0c, 0x3df0, 0x0200 }, 2844 }; 2845 2846 rtl_set_def_aspm_entry_latency(tp); 2847 2848 rtl_ephy_init(tp, e_info_8168e_2); 2849 2850 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2851 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2852 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2853 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2854 rtl_reset_packet_filter(tp); 2855 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2856 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2857 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2858 2859 rtl_disable_clock_request(tp); 2860 2861 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2862 2863 rtl8168_config_eee_mac(tp); 2864 2865 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2866 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2867 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2868 2869 rtl_hw_aspm_clkreq_enable(tp, true); 2870 } 2871 2872 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2873 { 2874 rtl_set_def_aspm_entry_latency(tp); 2875 2876 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2877 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2878 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2879 rtl_reset_packet_filter(tp); 2880 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2881 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2882 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2883 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2884 2885 rtl_disable_clock_request(tp); 2886 2887 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2888 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2889 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2890 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2891 2892 rtl8168_config_eee_mac(tp); 2893 } 2894 2895 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2896 { 2897 static const struct ephy_info e_info_8168f_1[] = { 2898 { 0x06, 0x00c0, 0x0020 }, 2899 { 0x08, 0x0001, 0x0002 }, 2900 { 0x09, 0x0000, 0x0080 }, 2901 { 0x19, 0x0000, 0x0224 }, 2902 { 0x00, 0x0000, 0x0008 }, 2903 { 0x0c, 0x3df0, 0x0200 }, 2904 }; 2905 2906 rtl_hw_start_8168f(tp); 2907 2908 rtl_ephy_init(tp, e_info_8168f_1); 2909 } 2910 2911 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2912 { 2913 static const struct ephy_info e_info_8168f_1[] = { 2914 { 0x06, 0x00c0, 0x0020 }, 2915 { 0x0f, 0xffff, 0x5200 }, 2916 { 0x19, 0x0000, 0x0224 }, 2917 { 0x00, 0x0000, 0x0008 }, 2918 { 0x0c, 0x3df0, 0x0200 }, 2919 }; 2920 2921 rtl_hw_start_8168f(tp); 2922 rtl_pcie_state_l2l3_disable(tp); 2923 2924 rtl_ephy_init(tp, e_info_8168f_1); 2925 } 2926 2927 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2928 { 2929 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2930 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2931 2932 rtl_set_def_aspm_entry_latency(tp); 2933 2934 rtl_reset_packet_filter(tp); 2935 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2936 2937 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2938 2939 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2940 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2941 2942 rtl8168_config_eee_mac(tp); 2943 2944 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2945 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2946 2947 rtl_pcie_state_l2l3_disable(tp); 2948 } 2949 2950 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2951 { 2952 static const struct ephy_info e_info_8168g_1[] = { 2953 { 0x00, 0x0008, 0x0000 }, 2954 { 0x0c, 0x3ff0, 0x0820 }, 2955 { 0x1e, 0x0000, 0x0001 }, 2956 { 0x19, 0x8000, 0x0000 } 2957 }; 2958 2959 rtl_hw_start_8168g(tp); 2960 2961 /* disable aspm and clock request before access ephy */ 2962 rtl_hw_aspm_clkreq_enable(tp, false); 2963 rtl_ephy_init(tp, e_info_8168g_1); 2964 rtl_hw_aspm_clkreq_enable(tp, true); 2965 } 2966 2967 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 2968 { 2969 static const struct ephy_info e_info_8168g_2[] = { 2970 { 0x00, 0x0008, 0x0000 }, 2971 { 0x0c, 0x3ff0, 0x0820 }, 2972 { 0x19, 0xffff, 0x7c00 }, 2973 { 0x1e, 0xffff, 0x20eb }, 2974 { 0x0d, 0xffff, 0x1666 }, 2975 { 0x00, 0xffff, 0x10a3 }, 2976 { 0x06, 0xffff, 0xf050 }, 2977 { 0x04, 0x0000, 0x0010 }, 2978 { 0x1d, 0x4000, 0x0000 }, 2979 }; 2980 2981 rtl_hw_start_8168g(tp); 2982 2983 /* disable aspm and clock request before access ephy */ 2984 rtl_hw_aspm_clkreq_enable(tp, false); 2985 rtl_ephy_init(tp, e_info_8168g_2); 2986 } 2987 2988 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 2989 { 2990 static const struct ephy_info e_info_8411_2[] = { 2991 { 0x00, 0x0008, 0x0000 }, 2992 { 0x0c, 0x37d0, 0x0820 }, 2993 { 0x1e, 0x0000, 0x0001 }, 2994 { 0x19, 0x8021, 0x0000 }, 2995 { 0x1e, 0x0000, 0x2000 }, 2996 { 0x0d, 0x0100, 0x0200 }, 2997 { 0x00, 0x0000, 0x0080 }, 2998 { 0x06, 0x0000, 0x0010 }, 2999 { 0x04, 0x0000, 0x0010 }, 3000 { 0x1d, 0x0000, 0x4000 }, 3001 }; 3002 3003 rtl_hw_start_8168g(tp); 3004 3005 /* disable aspm and clock request before access ephy */ 3006 rtl_hw_aspm_clkreq_enable(tp, false); 3007 rtl_ephy_init(tp, e_info_8411_2); 3008 3009 /* The following Realtek-provided magic fixes an issue with the RX unit 3010 * getting confused after the PHY having been powered-down. 3011 */ 3012 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3013 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3014 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3015 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3016 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3017 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3018 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3019 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3020 mdelay(3); 3021 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3022 3023 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3024 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3025 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3026 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3027 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3028 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3029 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3030 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3031 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3032 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3033 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3034 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3035 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3036 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3037 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3038 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3039 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3040 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3041 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3042 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3043 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3044 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3045 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3046 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3047 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3048 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3049 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3050 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3051 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3052 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3053 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3054 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3055 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3056 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3057 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3058 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3059 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3060 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3061 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3062 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3063 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3064 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3065 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3066 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3067 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3068 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3069 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3070 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3071 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3072 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3073 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3074 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3075 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3076 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3077 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3078 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3079 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3080 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3081 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3082 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3083 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3084 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3085 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3086 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3087 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3088 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3089 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3090 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3091 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3092 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3093 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3094 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3095 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3096 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3097 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3098 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3099 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3100 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3101 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3102 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3103 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3104 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3105 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3106 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3107 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3108 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3109 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3110 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3111 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3112 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3113 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3114 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3115 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3116 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3117 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3118 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3119 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3120 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3121 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3122 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3123 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3124 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3125 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3126 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3127 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3128 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3129 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3130 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3131 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3132 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3133 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3134 3135 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3136 3137 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3138 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3139 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3140 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3141 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3142 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3143 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3144 3145 rtl_hw_aspm_clkreq_enable(tp, true); 3146 } 3147 3148 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3149 { 3150 static const struct ephy_info e_info_8168h_1[] = { 3151 { 0x1e, 0x0800, 0x0001 }, 3152 { 0x1d, 0x0000, 0x0800 }, 3153 { 0x05, 0xffff, 0x2089 }, 3154 { 0x06, 0xffff, 0x5881 }, 3155 { 0x04, 0xffff, 0x854a }, 3156 { 0x01, 0xffff, 0x068b } 3157 }; 3158 int rg_saw_cnt; 3159 3160 /* disable aspm and clock request before access ephy */ 3161 rtl_hw_aspm_clkreq_enable(tp, false); 3162 rtl_ephy_init(tp, e_info_8168h_1); 3163 3164 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3165 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3166 3167 rtl_set_def_aspm_entry_latency(tp); 3168 3169 rtl_reset_packet_filter(tp); 3170 3171 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3172 3173 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3174 3175 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3176 3177 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3178 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3179 3180 rtl8168_config_eee_mac(tp); 3181 3182 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3183 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3184 3185 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3186 3187 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3188 3189 rtl_pcie_state_l2l3_disable(tp); 3190 3191 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3192 if (rg_saw_cnt > 0) { 3193 u16 sw_cnt_1ms_ini; 3194 3195 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3196 sw_cnt_1ms_ini &= 0x0fff; 3197 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3198 } 3199 3200 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3201 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3202 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3203 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3204 3205 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3206 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3207 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3208 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3209 3210 rtl_hw_aspm_clkreq_enable(tp, true); 3211 } 3212 3213 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3214 { 3215 rtl8168ep_stop_cmac(tp); 3216 3217 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3218 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3219 3220 rtl_set_def_aspm_entry_latency(tp); 3221 3222 rtl_reset_packet_filter(tp); 3223 3224 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3225 3226 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3227 3228 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3229 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3230 3231 rtl8168_config_eee_mac(tp); 3232 3233 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3234 3235 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3236 3237 rtl_pcie_state_l2l3_disable(tp); 3238 } 3239 3240 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3241 { 3242 static const struct ephy_info e_info_8168ep_1[] = { 3243 { 0x00, 0xffff, 0x10ab }, 3244 { 0x06, 0xffff, 0xf030 }, 3245 { 0x08, 0xffff, 0x2006 }, 3246 { 0x0d, 0xffff, 0x1666 }, 3247 { 0x0c, 0x3ff0, 0x0000 } 3248 }; 3249 3250 /* disable aspm and clock request before access ephy */ 3251 rtl_hw_aspm_clkreq_enable(tp, false); 3252 rtl_ephy_init(tp, e_info_8168ep_1); 3253 3254 rtl_hw_start_8168ep(tp); 3255 3256 rtl_hw_aspm_clkreq_enable(tp, true); 3257 } 3258 3259 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3260 { 3261 static const struct ephy_info e_info_8168ep_2[] = { 3262 { 0x00, 0xffff, 0x10a3 }, 3263 { 0x19, 0xffff, 0xfc00 }, 3264 { 0x1e, 0xffff, 0x20ea } 3265 }; 3266 3267 /* disable aspm and clock request before access ephy */ 3268 rtl_hw_aspm_clkreq_enable(tp, false); 3269 rtl_ephy_init(tp, e_info_8168ep_2); 3270 3271 rtl_hw_start_8168ep(tp); 3272 3273 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3274 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3275 3276 rtl_hw_aspm_clkreq_enable(tp, true); 3277 } 3278 3279 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3280 { 3281 static const struct ephy_info e_info_8168ep_3[] = { 3282 { 0x00, 0x0000, 0x0080 }, 3283 { 0x0d, 0x0100, 0x0200 }, 3284 { 0x19, 0x8021, 0x0000 }, 3285 { 0x1e, 0x0000, 0x2000 }, 3286 }; 3287 3288 /* disable aspm and clock request before access ephy */ 3289 rtl_hw_aspm_clkreq_enable(tp, false); 3290 rtl_ephy_init(tp, e_info_8168ep_3); 3291 3292 rtl_hw_start_8168ep(tp); 3293 3294 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3295 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3296 3297 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3298 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3299 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3300 3301 rtl_hw_aspm_clkreq_enable(tp, true); 3302 } 3303 3304 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3305 { 3306 static const struct ephy_info e_info_8117[] = { 3307 { 0x19, 0x0040, 0x1100 }, 3308 { 0x59, 0x0040, 0x1100 }, 3309 }; 3310 int rg_saw_cnt; 3311 3312 rtl8168ep_stop_cmac(tp); 3313 3314 /* disable aspm and clock request before access ephy */ 3315 rtl_hw_aspm_clkreq_enable(tp, false); 3316 rtl_ephy_init(tp, e_info_8117); 3317 3318 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3319 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3320 3321 rtl_set_def_aspm_entry_latency(tp); 3322 3323 rtl_reset_packet_filter(tp); 3324 3325 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3326 3327 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3328 3329 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3330 3331 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3332 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3333 3334 rtl8168_config_eee_mac(tp); 3335 3336 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3337 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3338 3339 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3340 3341 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3342 3343 rtl_pcie_state_l2l3_disable(tp); 3344 3345 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3346 if (rg_saw_cnt > 0) { 3347 u16 sw_cnt_1ms_ini; 3348 3349 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3350 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3351 } 3352 3353 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3354 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3355 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3356 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3357 3358 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3359 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3360 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3361 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3362 3363 /* firmware is for MAC only */ 3364 r8169_apply_firmware(tp); 3365 3366 rtl_hw_aspm_clkreq_enable(tp, true); 3367 } 3368 3369 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3370 { 3371 static const struct ephy_info e_info_8102e_1[] = { 3372 { 0x01, 0, 0x6e65 }, 3373 { 0x02, 0, 0x091f }, 3374 { 0x03, 0, 0xc2f9 }, 3375 { 0x06, 0, 0xafb5 }, 3376 { 0x07, 0, 0x0e00 }, 3377 { 0x19, 0, 0xec80 }, 3378 { 0x01, 0, 0x2e65 }, 3379 { 0x01, 0, 0x6e65 } 3380 }; 3381 u8 cfg1; 3382 3383 rtl_set_def_aspm_entry_latency(tp); 3384 3385 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3386 3387 RTL_W8(tp, Config1, 3388 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3389 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3390 3391 cfg1 = RTL_R8(tp, Config1); 3392 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3393 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3394 3395 rtl_ephy_init(tp, e_info_8102e_1); 3396 } 3397 3398 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3399 { 3400 rtl_set_def_aspm_entry_latency(tp); 3401 3402 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3403 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3404 } 3405 3406 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3407 { 3408 rtl_hw_start_8102e_2(tp); 3409 3410 rtl_ephy_write(tp, 0x03, 0xc2f9); 3411 } 3412 3413 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3414 { 3415 static const struct ephy_info e_info_8401[] = { 3416 { 0x01, 0xffff, 0x6fe5 }, 3417 { 0x03, 0xffff, 0x0599 }, 3418 { 0x06, 0xffff, 0xaf25 }, 3419 { 0x07, 0xffff, 0x8e68 }, 3420 }; 3421 3422 rtl_ephy_init(tp, e_info_8401); 3423 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3424 } 3425 3426 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3427 { 3428 static const struct ephy_info e_info_8105e_1[] = { 3429 { 0x07, 0, 0x4000 }, 3430 { 0x19, 0, 0x0200 }, 3431 { 0x19, 0, 0x0020 }, 3432 { 0x1e, 0, 0x2000 }, 3433 { 0x03, 0, 0x0001 }, 3434 { 0x19, 0, 0x0100 }, 3435 { 0x19, 0, 0x0004 }, 3436 { 0x0a, 0, 0x0020 } 3437 }; 3438 3439 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3440 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3441 3442 /* Disable Early Tally Counter */ 3443 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3444 3445 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3446 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3447 3448 rtl_ephy_init(tp, e_info_8105e_1); 3449 3450 rtl_pcie_state_l2l3_disable(tp); 3451 } 3452 3453 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3454 { 3455 rtl_hw_start_8105e_1(tp); 3456 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3457 } 3458 3459 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3460 { 3461 static const struct ephy_info e_info_8402[] = { 3462 { 0x19, 0xffff, 0xff64 }, 3463 { 0x1e, 0, 0x4000 } 3464 }; 3465 3466 rtl_set_def_aspm_entry_latency(tp); 3467 3468 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3469 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3470 3471 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3472 3473 rtl_ephy_init(tp, e_info_8402); 3474 3475 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3476 rtl_reset_packet_filter(tp); 3477 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3478 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3479 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3480 3481 /* disable EEE */ 3482 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3483 3484 rtl_pcie_state_l2l3_disable(tp); 3485 } 3486 3487 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3488 { 3489 rtl_hw_aspm_clkreq_enable(tp, false); 3490 3491 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3492 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3493 3494 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3495 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3496 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3497 3498 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3499 rtl_set_aspm_entry_latency(tp, 0x2f); 3500 3501 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3502 3503 /* disable EEE */ 3504 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3505 3506 rtl_pcie_state_l2l3_disable(tp); 3507 rtl_hw_aspm_clkreq_enable(tp, true); 3508 } 3509 3510 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3511 { 3512 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3513 } 3514 3515 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3516 { 3517 rtl_pcie_state_l2l3_disable(tp); 3518 3519 RTL_W16(tp, 0x382, 0x221b); 3520 RTL_W8(tp, 0x4500, 0); 3521 RTL_W16(tp, 0x4800, 0); 3522 3523 /* disable UPS */ 3524 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3525 3526 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3527 3528 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3529 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3530 3531 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3532 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3533 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3534 3535 /* disable new tx descriptor format */ 3536 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3537 3538 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3539 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3540 else 3541 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3542 3543 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3544 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3545 else 3546 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3547 3548 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3549 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3550 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3551 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3552 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3553 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3554 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3555 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3556 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3557 3558 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3559 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3560 udelay(1); 3561 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3562 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3563 3564 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3565 3566 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3567 3568 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3569 rtl8125b_config_eee_mac(tp); 3570 else 3571 rtl8125a_config_eee_mac(tp); 3572 3573 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3574 udelay(10); 3575 } 3576 3577 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3578 { 3579 static const struct ephy_info e_info_8125a_1[] = { 3580 { 0x01, 0xffff, 0xa812 }, 3581 { 0x09, 0xffff, 0x520c }, 3582 { 0x04, 0xffff, 0xd000 }, 3583 { 0x0d, 0xffff, 0xf702 }, 3584 { 0x0a, 0xffff, 0x8653 }, 3585 { 0x06, 0xffff, 0x001e }, 3586 { 0x08, 0xffff, 0x3595 }, 3587 { 0x20, 0xffff, 0x9455 }, 3588 { 0x21, 0xffff, 0x99ff }, 3589 { 0x02, 0xffff, 0x6046 }, 3590 { 0x29, 0xffff, 0xfe00 }, 3591 { 0x23, 0xffff, 0xab62 }, 3592 3593 { 0x41, 0xffff, 0xa80c }, 3594 { 0x49, 0xffff, 0x520c }, 3595 { 0x44, 0xffff, 0xd000 }, 3596 { 0x4d, 0xffff, 0xf702 }, 3597 { 0x4a, 0xffff, 0x8653 }, 3598 { 0x46, 0xffff, 0x001e }, 3599 { 0x48, 0xffff, 0x3595 }, 3600 { 0x60, 0xffff, 0x9455 }, 3601 { 0x61, 0xffff, 0x99ff }, 3602 { 0x42, 0xffff, 0x6046 }, 3603 { 0x69, 0xffff, 0xfe00 }, 3604 { 0x63, 0xffff, 0xab62 }, 3605 }; 3606 3607 rtl_set_def_aspm_entry_latency(tp); 3608 3609 /* disable aspm and clock request before access ephy */ 3610 rtl_hw_aspm_clkreq_enable(tp, false); 3611 rtl_ephy_init(tp, e_info_8125a_1); 3612 3613 rtl_hw_start_8125_common(tp); 3614 rtl_hw_aspm_clkreq_enable(tp, true); 3615 } 3616 3617 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3618 { 3619 static const struct ephy_info e_info_8125a_2[] = { 3620 { 0x04, 0xffff, 0xd000 }, 3621 { 0x0a, 0xffff, 0x8653 }, 3622 { 0x23, 0xffff, 0xab66 }, 3623 { 0x20, 0xffff, 0x9455 }, 3624 { 0x21, 0xffff, 0x99ff }, 3625 { 0x29, 0xffff, 0xfe04 }, 3626 3627 { 0x44, 0xffff, 0xd000 }, 3628 { 0x4a, 0xffff, 0x8653 }, 3629 { 0x63, 0xffff, 0xab66 }, 3630 { 0x60, 0xffff, 0x9455 }, 3631 { 0x61, 0xffff, 0x99ff }, 3632 { 0x69, 0xffff, 0xfe04 }, 3633 }; 3634 3635 rtl_set_def_aspm_entry_latency(tp); 3636 3637 /* disable aspm and clock request before access ephy */ 3638 rtl_hw_aspm_clkreq_enable(tp, false); 3639 rtl_ephy_init(tp, e_info_8125a_2); 3640 3641 rtl_hw_start_8125_common(tp); 3642 rtl_hw_aspm_clkreq_enable(tp, true); 3643 } 3644 3645 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3646 { 3647 static const struct ephy_info e_info_8125b[] = { 3648 { 0x0b, 0xffff, 0xa908 }, 3649 { 0x1e, 0xffff, 0x20eb }, 3650 { 0x4b, 0xffff, 0xa908 }, 3651 { 0x5e, 0xffff, 0x20eb }, 3652 { 0x22, 0x0030, 0x0020 }, 3653 { 0x62, 0x0030, 0x0020 }, 3654 }; 3655 3656 rtl_set_def_aspm_entry_latency(tp); 3657 rtl_hw_aspm_clkreq_enable(tp, false); 3658 3659 rtl_ephy_init(tp, e_info_8125b); 3660 rtl_hw_start_8125_common(tp); 3661 3662 rtl_hw_aspm_clkreq_enable(tp, true); 3663 } 3664 3665 static void rtl_hw_config(struct rtl8169_private *tp) 3666 { 3667 static const rtl_generic_fct hw_configs[] = { 3668 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3669 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3670 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3671 [RTL_GIGA_MAC_VER_10] = NULL, 3672 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3673 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3674 [RTL_GIGA_MAC_VER_13] = NULL, 3675 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3676 [RTL_GIGA_MAC_VER_16] = NULL, 3677 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3678 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3679 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3680 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3681 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3682 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3683 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3684 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3685 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3686 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3687 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3688 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3689 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3690 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3691 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3692 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3693 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3694 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3695 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3696 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3697 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3698 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3699 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3700 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3701 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3702 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3703 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3704 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3705 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3706 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3707 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3708 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3709 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3710 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3711 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3712 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3713 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3714 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3715 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3716 }; 3717 3718 if (hw_configs[tp->mac_version]) 3719 hw_configs[tp->mac_version](tp); 3720 } 3721 3722 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3723 { 3724 int i; 3725 3726 /* disable interrupt coalescing */ 3727 for (i = 0xa00; i < 0xb00; i += 4) 3728 RTL_W32(tp, i, 0); 3729 3730 rtl_hw_config(tp); 3731 } 3732 3733 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3734 { 3735 if (rtl_is_8168evl_up(tp)) 3736 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3737 else 3738 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3739 3740 rtl_hw_config(tp); 3741 3742 /* disable interrupt coalescing */ 3743 RTL_W16(tp, IntrMitigate, 0x0000); 3744 } 3745 3746 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3747 { 3748 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3749 3750 tp->cp_cmd |= PCIMulRW; 3751 3752 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3753 tp->mac_version == RTL_GIGA_MAC_VER_03) 3754 tp->cp_cmd |= EnAnaPLL; 3755 3756 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3757 3758 rtl8169_set_magic_reg(tp); 3759 3760 /* disable interrupt coalescing */ 3761 RTL_W16(tp, IntrMitigate, 0x0000); 3762 } 3763 3764 static void rtl_hw_start(struct rtl8169_private *tp) 3765 { 3766 rtl_unlock_config_regs(tp); 3767 3768 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3769 3770 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3771 rtl_hw_start_8169(tp); 3772 else if (rtl_is_8125(tp)) 3773 rtl_hw_start_8125(tp); 3774 else 3775 rtl_hw_start_8168(tp); 3776 3777 rtl_enable_exit_l1(tp); 3778 rtl_set_rx_max_size(tp); 3779 rtl_set_rx_tx_desc_registers(tp); 3780 rtl_lock_config_regs(tp); 3781 3782 rtl_jumbo_config(tp); 3783 3784 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3785 rtl_pci_commit(tp); 3786 3787 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3788 rtl_init_rxcfg(tp); 3789 rtl_set_tx_config_registers(tp); 3790 rtl_set_rx_config_features(tp, tp->dev->features); 3791 rtl_set_rx_mode(tp->dev); 3792 rtl_irq_enable(tp); 3793 } 3794 3795 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3796 { 3797 struct rtl8169_private *tp = netdev_priv(dev); 3798 3799 dev->mtu = new_mtu; 3800 netdev_update_features(dev); 3801 rtl_jumbo_config(tp); 3802 3803 switch (tp->mac_version) { 3804 case RTL_GIGA_MAC_VER_61: 3805 case RTL_GIGA_MAC_VER_63: 3806 rtl8125_set_eee_txidle_timer(tp); 3807 break; 3808 default: 3809 break; 3810 } 3811 3812 return 0; 3813 } 3814 3815 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3816 { 3817 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3818 3819 desc->opts2 = 0; 3820 /* Force memory writes to complete before releasing descriptor */ 3821 dma_wmb(); 3822 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3823 } 3824 3825 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3826 struct RxDesc *desc) 3827 { 3828 struct device *d = tp_to_dev(tp); 3829 int node = dev_to_node(d); 3830 dma_addr_t mapping; 3831 struct page *data; 3832 3833 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3834 if (!data) 3835 return NULL; 3836 3837 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3838 if (unlikely(dma_mapping_error(d, mapping))) { 3839 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3840 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3841 return NULL; 3842 } 3843 3844 desc->addr = cpu_to_le64(mapping); 3845 rtl8169_mark_to_asic(desc); 3846 3847 return data; 3848 } 3849 3850 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3851 { 3852 int i; 3853 3854 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3855 dma_unmap_page(tp_to_dev(tp), 3856 le64_to_cpu(tp->RxDescArray[i].addr), 3857 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3858 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3859 tp->Rx_databuff[i] = NULL; 3860 tp->RxDescArray[i].addr = 0; 3861 tp->RxDescArray[i].opts1 = 0; 3862 } 3863 } 3864 3865 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3866 { 3867 int i; 3868 3869 for (i = 0; i < NUM_RX_DESC; i++) { 3870 struct page *data; 3871 3872 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3873 if (!data) { 3874 rtl8169_rx_clear(tp); 3875 return -ENOMEM; 3876 } 3877 tp->Rx_databuff[i] = data; 3878 } 3879 3880 /* mark as last descriptor in the ring */ 3881 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3882 3883 return 0; 3884 } 3885 3886 static int rtl8169_init_ring(struct rtl8169_private *tp) 3887 { 3888 rtl8169_init_ring_indexes(tp); 3889 3890 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3891 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3892 3893 return rtl8169_rx_fill(tp); 3894 } 3895 3896 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3897 { 3898 struct ring_info *tx_skb = tp->tx_skb + entry; 3899 struct TxDesc *desc = tp->TxDescArray + entry; 3900 3901 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3902 DMA_TO_DEVICE); 3903 memset(desc, 0, sizeof(*desc)); 3904 memset(tx_skb, 0, sizeof(*tx_skb)); 3905 } 3906 3907 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3908 unsigned int n) 3909 { 3910 unsigned int i; 3911 3912 for (i = 0; i < n; i++) { 3913 unsigned int entry = (start + i) % NUM_TX_DESC; 3914 struct ring_info *tx_skb = tp->tx_skb + entry; 3915 unsigned int len = tx_skb->len; 3916 3917 if (len) { 3918 struct sk_buff *skb = tx_skb->skb; 3919 3920 rtl8169_unmap_tx_skb(tp, entry); 3921 if (skb) 3922 dev_consume_skb_any(skb); 3923 } 3924 } 3925 } 3926 3927 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3928 { 3929 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3930 netdev_reset_queue(tp->dev); 3931 } 3932 3933 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3934 { 3935 napi_disable(&tp->napi); 3936 3937 /* Give a racing hard_start_xmit a few cycles to complete. */ 3938 synchronize_net(); 3939 3940 /* Disable interrupts */ 3941 rtl8169_irq_mask_and_ack(tp); 3942 3943 rtl_rx_close(tp); 3944 3945 if (going_down && tp->dev->wol_enabled) 3946 goto no_reset; 3947 3948 switch (tp->mac_version) { 3949 case RTL_GIGA_MAC_VER_28: 3950 case RTL_GIGA_MAC_VER_31: 3951 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3952 break; 3953 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3954 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3955 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3956 break; 3957 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3958 rtl_enable_rxdvgate(tp); 3959 fsleep(2000); 3960 break; 3961 default: 3962 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3963 fsleep(100); 3964 break; 3965 } 3966 3967 rtl_hw_reset(tp); 3968 no_reset: 3969 rtl8169_tx_clear(tp); 3970 rtl8169_init_ring_indexes(tp); 3971 } 3972 3973 static void rtl_reset_work(struct rtl8169_private *tp) 3974 { 3975 int i; 3976 3977 netif_stop_queue(tp->dev); 3978 3979 rtl8169_cleanup(tp, false); 3980 3981 for (i = 0; i < NUM_RX_DESC; i++) 3982 rtl8169_mark_to_asic(tp->RxDescArray + i); 3983 3984 napi_enable(&tp->napi); 3985 rtl_hw_start(tp); 3986 } 3987 3988 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3989 { 3990 struct rtl8169_private *tp = netdev_priv(dev); 3991 3992 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3993 } 3994 3995 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3996 void *addr, unsigned int entry, bool desc_own) 3997 { 3998 struct TxDesc *txd = tp->TxDescArray + entry; 3999 struct device *d = tp_to_dev(tp); 4000 dma_addr_t mapping; 4001 u32 opts1; 4002 int ret; 4003 4004 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4005 ret = dma_mapping_error(d, mapping); 4006 if (unlikely(ret)) { 4007 if (net_ratelimit()) 4008 netdev_err(tp->dev, "Failed to map TX data!\n"); 4009 return ret; 4010 } 4011 4012 txd->addr = cpu_to_le64(mapping); 4013 txd->opts2 = cpu_to_le32(opts[1]); 4014 4015 opts1 = opts[0] | len; 4016 if (entry == NUM_TX_DESC - 1) 4017 opts1 |= RingEnd; 4018 if (desc_own) 4019 opts1 |= DescOwn; 4020 txd->opts1 = cpu_to_le32(opts1); 4021 4022 tp->tx_skb[entry].len = len; 4023 4024 return 0; 4025 } 4026 4027 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4028 const u32 *opts, unsigned int entry) 4029 { 4030 struct skb_shared_info *info = skb_shinfo(skb); 4031 unsigned int cur_frag; 4032 4033 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4034 const skb_frag_t *frag = info->frags + cur_frag; 4035 void *addr = skb_frag_address(frag); 4036 u32 len = skb_frag_size(frag); 4037 4038 entry = (entry + 1) % NUM_TX_DESC; 4039 4040 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4041 goto err_out; 4042 } 4043 4044 return 0; 4045 4046 err_out: 4047 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4048 return -EIO; 4049 } 4050 4051 static bool rtl_skb_is_udp(struct sk_buff *skb) 4052 { 4053 int no = skb_network_offset(skb); 4054 struct ipv6hdr *i6h, _i6h; 4055 struct iphdr *ih, _ih; 4056 4057 switch (vlan_get_protocol(skb)) { 4058 case htons(ETH_P_IP): 4059 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4060 return ih && ih->protocol == IPPROTO_UDP; 4061 case htons(ETH_P_IPV6): 4062 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4063 return i6h && i6h->nexthdr == IPPROTO_UDP; 4064 default: 4065 return false; 4066 } 4067 } 4068 4069 #define RTL_MIN_PATCH_LEN 47 4070 4071 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4072 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4073 struct sk_buff *skb) 4074 { 4075 unsigned int padto = 0, len = skb->len; 4076 4077 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4078 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4079 unsigned int trans_data_len = skb_tail_pointer(skb) - 4080 skb_transport_header(skb); 4081 4082 if (trans_data_len >= offsetof(struct udphdr, len) && 4083 trans_data_len < RTL_MIN_PATCH_LEN) { 4084 u16 dest = ntohs(udp_hdr(skb)->dest); 4085 4086 /* dest is a standard PTP port */ 4087 if (dest == 319 || dest == 320) 4088 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4089 } 4090 4091 if (trans_data_len < sizeof(struct udphdr)) 4092 padto = max_t(unsigned int, padto, 4093 len + sizeof(struct udphdr) - trans_data_len); 4094 } 4095 4096 return padto; 4097 } 4098 4099 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4100 struct sk_buff *skb) 4101 { 4102 unsigned int padto; 4103 4104 padto = rtl8125_quirk_udp_padto(tp, skb); 4105 4106 switch (tp->mac_version) { 4107 case RTL_GIGA_MAC_VER_34: 4108 case RTL_GIGA_MAC_VER_60: 4109 case RTL_GIGA_MAC_VER_61: 4110 case RTL_GIGA_MAC_VER_63: 4111 padto = max_t(unsigned int, padto, ETH_ZLEN); 4112 break; 4113 default: 4114 break; 4115 } 4116 4117 return padto; 4118 } 4119 4120 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4121 { 4122 u32 mss = skb_shinfo(skb)->gso_size; 4123 4124 if (mss) { 4125 opts[0] |= TD_LSO; 4126 opts[0] |= mss << TD0_MSS_SHIFT; 4127 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4128 const struct iphdr *ip = ip_hdr(skb); 4129 4130 if (ip->protocol == IPPROTO_TCP) 4131 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4132 else if (ip->protocol == IPPROTO_UDP) 4133 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4134 else 4135 WARN_ON_ONCE(1); 4136 } 4137 } 4138 4139 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4140 struct sk_buff *skb, u32 *opts) 4141 { 4142 u32 transport_offset = (u32)skb_transport_offset(skb); 4143 struct skb_shared_info *shinfo = skb_shinfo(skb); 4144 u32 mss = shinfo->gso_size; 4145 4146 if (mss) { 4147 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4148 opts[0] |= TD1_GTSENV4; 4149 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4150 if (skb_cow_head(skb, 0)) 4151 return false; 4152 4153 tcp_v6_gso_csum_prep(skb); 4154 opts[0] |= TD1_GTSENV6; 4155 } else { 4156 WARN_ON_ONCE(1); 4157 } 4158 4159 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4160 opts[1] |= mss << TD1_MSS_SHIFT; 4161 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4162 u8 ip_protocol; 4163 4164 switch (vlan_get_protocol(skb)) { 4165 case htons(ETH_P_IP): 4166 opts[1] |= TD1_IPv4_CS; 4167 ip_protocol = ip_hdr(skb)->protocol; 4168 break; 4169 4170 case htons(ETH_P_IPV6): 4171 opts[1] |= TD1_IPv6_CS; 4172 ip_protocol = ipv6_hdr(skb)->nexthdr; 4173 break; 4174 4175 default: 4176 ip_protocol = IPPROTO_RAW; 4177 break; 4178 } 4179 4180 if (ip_protocol == IPPROTO_TCP) 4181 opts[1] |= TD1_TCP_CS; 4182 else if (ip_protocol == IPPROTO_UDP) 4183 opts[1] |= TD1_UDP_CS; 4184 else 4185 WARN_ON_ONCE(1); 4186 4187 opts[1] |= transport_offset << TCPHO_SHIFT; 4188 } else { 4189 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4190 4191 /* skb_padto would free the skb on error */ 4192 return !__skb_put_padto(skb, padto, false); 4193 } 4194 4195 return true; 4196 } 4197 4198 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4199 { 4200 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4201 - READ_ONCE(tp->cur_tx); 4202 4203 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4204 return slots_avail > MAX_SKB_FRAGS; 4205 } 4206 4207 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4208 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4209 { 4210 switch (tp->mac_version) { 4211 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4212 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4213 return false; 4214 default: 4215 return true; 4216 } 4217 } 4218 4219 static void rtl8169_doorbell(struct rtl8169_private *tp) 4220 { 4221 if (rtl_is_8125(tp)) 4222 RTL_W16(tp, TxPoll_8125, BIT(0)); 4223 else 4224 RTL_W8(tp, TxPoll, NPQ); 4225 } 4226 4227 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4228 struct net_device *dev) 4229 { 4230 unsigned int frags = skb_shinfo(skb)->nr_frags; 4231 struct rtl8169_private *tp = netdev_priv(dev); 4232 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4233 struct TxDesc *txd_first, *txd_last; 4234 bool stop_queue, door_bell; 4235 u32 opts[2]; 4236 4237 if (unlikely(!rtl_tx_slots_avail(tp))) { 4238 if (net_ratelimit()) 4239 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4240 goto err_stop_0; 4241 } 4242 4243 opts[1] = rtl8169_tx_vlan_tag(skb); 4244 opts[0] = 0; 4245 4246 if (!rtl_chip_supports_csum_v2(tp)) 4247 rtl8169_tso_csum_v1(skb, opts); 4248 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4249 goto err_dma_0; 4250 4251 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4252 entry, false))) 4253 goto err_dma_0; 4254 4255 txd_first = tp->TxDescArray + entry; 4256 4257 if (frags) { 4258 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4259 goto err_dma_1; 4260 entry = (entry + frags) % NUM_TX_DESC; 4261 } 4262 4263 txd_last = tp->TxDescArray + entry; 4264 txd_last->opts1 |= cpu_to_le32(LastFrag); 4265 tp->tx_skb[entry].skb = skb; 4266 4267 skb_tx_timestamp(skb); 4268 4269 /* Force memory writes to complete before releasing descriptor */ 4270 dma_wmb(); 4271 4272 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4273 4274 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4275 4276 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4277 smp_wmb(); 4278 4279 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4280 4281 stop_queue = !rtl_tx_slots_avail(tp); 4282 if (unlikely(stop_queue)) { 4283 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4284 * not miss a ring update when it notices a stopped queue. 4285 */ 4286 smp_wmb(); 4287 netif_stop_queue(dev); 4288 /* Sync with rtl_tx: 4289 * - publish queue status and cur_tx ring index (write barrier) 4290 * - refresh dirty_tx ring index (read barrier). 4291 * May the current thread have a pessimistic view of the ring 4292 * status and forget to wake up queue, a racing rtl_tx thread 4293 * can't. 4294 */ 4295 smp_mb__after_atomic(); 4296 if (rtl_tx_slots_avail(tp)) 4297 netif_start_queue(dev); 4298 door_bell = true; 4299 } 4300 4301 if (door_bell) 4302 rtl8169_doorbell(tp); 4303 4304 return NETDEV_TX_OK; 4305 4306 err_dma_1: 4307 rtl8169_unmap_tx_skb(tp, entry); 4308 err_dma_0: 4309 dev_kfree_skb_any(skb); 4310 dev->stats.tx_dropped++; 4311 return NETDEV_TX_OK; 4312 4313 err_stop_0: 4314 netif_stop_queue(dev); 4315 dev->stats.tx_dropped++; 4316 return NETDEV_TX_BUSY; 4317 } 4318 4319 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4320 { 4321 struct skb_shared_info *info = skb_shinfo(skb); 4322 unsigned int nr_frags = info->nr_frags; 4323 4324 if (!nr_frags) 4325 return UINT_MAX; 4326 4327 return skb_frag_size(info->frags + nr_frags - 1); 4328 } 4329 4330 /* Workaround for hw issues with TSO on RTL8168evl */ 4331 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4332 netdev_features_t features) 4333 { 4334 /* IPv4 header has options field */ 4335 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4336 ip_hdrlen(skb) > sizeof(struct iphdr)) 4337 features &= ~NETIF_F_ALL_TSO; 4338 4339 /* IPv4 TCP header has options field */ 4340 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4341 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4342 features &= ~NETIF_F_ALL_TSO; 4343 4344 else if (rtl_last_frag_len(skb) <= 6) 4345 features &= ~NETIF_F_ALL_TSO; 4346 4347 return features; 4348 } 4349 4350 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4351 struct net_device *dev, 4352 netdev_features_t features) 4353 { 4354 int transport_offset = skb_transport_offset(skb); 4355 struct rtl8169_private *tp = netdev_priv(dev); 4356 4357 if (skb_is_gso(skb)) { 4358 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4359 features = rtl8168evl_fix_tso(skb, features); 4360 4361 if (transport_offset > GTTCPHO_MAX && 4362 rtl_chip_supports_csum_v2(tp)) 4363 features &= ~NETIF_F_ALL_TSO; 4364 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4365 /* work around hw bug on some chip versions */ 4366 if (skb->len < ETH_ZLEN) 4367 features &= ~NETIF_F_CSUM_MASK; 4368 4369 if (rtl_quirk_packet_padto(tp, skb)) 4370 features &= ~NETIF_F_CSUM_MASK; 4371 4372 if (transport_offset > TCPHO_MAX && 4373 rtl_chip_supports_csum_v2(tp)) 4374 features &= ~NETIF_F_CSUM_MASK; 4375 } 4376 4377 return vlan_features_check(skb, features); 4378 } 4379 4380 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4381 { 4382 struct rtl8169_private *tp = netdev_priv(dev); 4383 struct pci_dev *pdev = tp->pci_dev; 4384 int pci_status_errs; 4385 u16 pci_cmd; 4386 4387 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4388 4389 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4390 4391 if (net_ratelimit()) 4392 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4393 pci_cmd, pci_status_errs); 4394 4395 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4396 } 4397 4398 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4399 int budget) 4400 { 4401 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4402 struct sk_buff *skb; 4403 4404 dirty_tx = tp->dirty_tx; 4405 4406 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4407 unsigned int entry = dirty_tx % NUM_TX_DESC; 4408 u32 status; 4409 4410 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4411 if (status & DescOwn) 4412 break; 4413 4414 skb = tp->tx_skb[entry].skb; 4415 rtl8169_unmap_tx_skb(tp, entry); 4416 4417 if (skb) { 4418 pkts_compl++; 4419 bytes_compl += skb->len; 4420 napi_consume_skb(skb, budget); 4421 } 4422 dirty_tx++; 4423 } 4424 4425 if (tp->dirty_tx != dirty_tx) { 4426 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4427 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4428 4429 /* Sync with rtl8169_start_xmit: 4430 * - publish dirty_tx ring index (write barrier) 4431 * - refresh cur_tx ring index and queue status (read barrier) 4432 * May the current thread miss the stopped queue condition, 4433 * a racing xmit thread can only have a right view of the 4434 * ring status. 4435 */ 4436 smp_store_mb(tp->dirty_tx, dirty_tx); 4437 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4438 netif_wake_queue(dev); 4439 /* 4440 * 8168 hack: TxPoll requests are lost when the Tx packets are 4441 * too close. Let's kick an extra TxPoll request when a burst 4442 * of start_xmit activity is detected (if it is not detected, 4443 * it is slow enough). -- FR 4444 * If skb is NULL then we come here again once a tx irq is 4445 * triggered after the last fragment is marked transmitted. 4446 */ 4447 if (tp->cur_tx != dirty_tx && skb) 4448 rtl8169_doorbell(tp); 4449 } 4450 } 4451 4452 static inline int rtl8169_fragmented_frame(u32 status) 4453 { 4454 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4455 } 4456 4457 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4458 { 4459 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4460 4461 if (status == RxProtoTCP || status == RxProtoUDP) 4462 skb->ip_summed = CHECKSUM_UNNECESSARY; 4463 else 4464 skb_checksum_none_assert(skb); 4465 } 4466 4467 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4468 { 4469 struct device *d = tp_to_dev(tp); 4470 int count; 4471 4472 for (count = 0; count < budget; count++, tp->cur_rx++) { 4473 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4474 struct RxDesc *desc = tp->RxDescArray + entry; 4475 struct sk_buff *skb; 4476 const void *rx_buf; 4477 dma_addr_t addr; 4478 u32 status; 4479 4480 status = le32_to_cpu(desc->opts1); 4481 if (status & DescOwn) 4482 break; 4483 4484 /* This barrier is needed to keep us from reading 4485 * any other fields out of the Rx descriptor until 4486 * we know the status of DescOwn 4487 */ 4488 dma_rmb(); 4489 4490 if (unlikely(status & RxRES)) { 4491 if (net_ratelimit()) 4492 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4493 status); 4494 dev->stats.rx_errors++; 4495 if (status & (RxRWT | RxRUNT)) 4496 dev->stats.rx_length_errors++; 4497 if (status & RxCRC) 4498 dev->stats.rx_crc_errors++; 4499 4500 if (!(dev->features & NETIF_F_RXALL)) 4501 goto release_descriptor; 4502 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4503 goto release_descriptor; 4504 } 4505 4506 pkt_size = status & GENMASK(13, 0); 4507 if (likely(!(dev->features & NETIF_F_RXFCS))) 4508 pkt_size -= ETH_FCS_LEN; 4509 4510 /* The driver does not support incoming fragmented frames. 4511 * They are seen as a symptom of over-mtu sized frames. 4512 */ 4513 if (unlikely(rtl8169_fragmented_frame(status))) { 4514 dev->stats.rx_dropped++; 4515 dev->stats.rx_length_errors++; 4516 goto release_descriptor; 4517 } 4518 4519 skb = napi_alloc_skb(&tp->napi, pkt_size); 4520 if (unlikely(!skb)) { 4521 dev->stats.rx_dropped++; 4522 goto release_descriptor; 4523 } 4524 4525 addr = le64_to_cpu(desc->addr); 4526 rx_buf = page_address(tp->Rx_databuff[entry]); 4527 4528 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4529 prefetch(rx_buf); 4530 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4531 skb->tail += pkt_size; 4532 skb->len = pkt_size; 4533 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4534 4535 rtl8169_rx_csum(skb, status); 4536 skb->protocol = eth_type_trans(skb, dev); 4537 4538 rtl8169_rx_vlan_tag(desc, skb); 4539 4540 if (skb->pkt_type == PACKET_MULTICAST) 4541 dev->stats.multicast++; 4542 4543 napi_gro_receive(&tp->napi, skb); 4544 4545 dev_sw_netstats_rx_add(dev, pkt_size); 4546 release_descriptor: 4547 rtl8169_mark_to_asic(desc); 4548 } 4549 4550 return count; 4551 } 4552 4553 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4554 { 4555 struct rtl8169_private *tp = dev_instance; 4556 u32 status = rtl_get_events(tp); 4557 4558 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4559 return IRQ_NONE; 4560 4561 if (unlikely(status & SYSErr)) { 4562 rtl8169_pcierr_interrupt(tp->dev); 4563 goto out; 4564 } 4565 4566 if (status & LinkChg) 4567 phy_mac_interrupt(tp->phydev); 4568 4569 if (unlikely(status & RxFIFOOver && 4570 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4571 netif_stop_queue(tp->dev); 4572 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4573 } 4574 4575 if (napi_schedule_prep(&tp->napi)) { 4576 rtl_irq_disable(tp); 4577 __napi_schedule(&tp->napi); 4578 } 4579 out: 4580 rtl_ack_events(tp, status); 4581 4582 return IRQ_HANDLED; 4583 } 4584 4585 static void rtl_task(struct work_struct *work) 4586 { 4587 struct rtl8169_private *tp = 4588 container_of(work, struct rtl8169_private, wk.work); 4589 4590 rtnl_lock(); 4591 4592 if (!netif_running(tp->dev) || 4593 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4594 goto out_unlock; 4595 4596 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4597 rtl_reset_work(tp); 4598 netif_wake_queue(tp->dev); 4599 } 4600 out_unlock: 4601 rtnl_unlock(); 4602 } 4603 4604 static int rtl8169_poll(struct napi_struct *napi, int budget) 4605 { 4606 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4607 struct net_device *dev = tp->dev; 4608 int work_done; 4609 4610 rtl_tx(dev, tp, budget); 4611 4612 work_done = rtl_rx(dev, tp, budget); 4613 4614 if (work_done < budget && napi_complete_done(napi, work_done)) 4615 rtl_irq_enable(tp); 4616 4617 return work_done; 4618 } 4619 4620 static void r8169_phylink_handler(struct net_device *ndev) 4621 { 4622 struct rtl8169_private *tp = netdev_priv(ndev); 4623 4624 if (netif_carrier_ok(ndev)) { 4625 rtl_link_chg_patch(tp); 4626 pm_request_resume(&tp->pci_dev->dev); 4627 } else { 4628 pm_runtime_idle(&tp->pci_dev->dev); 4629 } 4630 4631 if (net_ratelimit()) 4632 phy_print_status(tp->phydev); 4633 } 4634 4635 static int r8169_phy_connect(struct rtl8169_private *tp) 4636 { 4637 struct phy_device *phydev = tp->phydev; 4638 phy_interface_t phy_mode; 4639 int ret; 4640 4641 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4642 PHY_INTERFACE_MODE_MII; 4643 4644 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4645 phy_mode); 4646 if (ret) 4647 return ret; 4648 4649 if (!tp->supports_gmii) 4650 phy_set_max_speed(phydev, SPEED_100); 4651 4652 phy_attached_info(phydev); 4653 4654 return 0; 4655 } 4656 4657 static void rtl8169_down(struct rtl8169_private *tp) 4658 { 4659 /* Clear all task flags */ 4660 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4661 4662 phy_stop(tp->phydev); 4663 4664 rtl8169_update_counters(tp); 4665 4666 pci_clear_master(tp->pci_dev); 4667 rtl_pci_commit(tp); 4668 4669 rtl8169_cleanup(tp, true); 4670 4671 rtl_prepare_power_down(tp); 4672 } 4673 4674 static void rtl8169_up(struct rtl8169_private *tp) 4675 { 4676 pci_set_master(tp->pci_dev); 4677 phy_init_hw(tp->phydev); 4678 phy_resume(tp->phydev); 4679 rtl8169_init_phy(tp); 4680 napi_enable(&tp->napi); 4681 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4682 rtl_reset_work(tp); 4683 4684 phy_start(tp->phydev); 4685 } 4686 4687 static int rtl8169_close(struct net_device *dev) 4688 { 4689 struct rtl8169_private *tp = netdev_priv(dev); 4690 struct pci_dev *pdev = tp->pci_dev; 4691 4692 pm_runtime_get_sync(&pdev->dev); 4693 4694 netif_stop_queue(dev); 4695 rtl8169_down(tp); 4696 rtl8169_rx_clear(tp); 4697 4698 cancel_work_sync(&tp->wk.work); 4699 4700 free_irq(pci_irq_vector(pdev, 0), tp); 4701 4702 phy_disconnect(tp->phydev); 4703 4704 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4705 tp->RxPhyAddr); 4706 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4707 tp->TxPhyAddr); 4708 tp->TxDescArray = NULL; 4709 tp->RxDescArray = NULL; 4710 4711 pm_runtime_put_sync(&pdev->dev); 4712 4713 return 0; 4714 } 4715 4716 #ifdef CONFIG_NET_POLL_CONTROLLER 4717 static void rtl8169_netpoll(struct net_device *dev) 4718 { 4719 struct rtl8169_private *tp = netdev_priv(dev); 4720 4721 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4722 } 4723 #endif 4724 4725 static int rtl_open(struct net_device *dev) 4726 { 4727 struct rtl8169_private *tp = netdev_priv(dev); 4728 struct pci_dev *pdev = tp->pci_dev; 4729 unsigned long irqflags; 4730 int retval = -ENOMEM; 4731 4732 pm_runtime_get_sync(&pdev->dev); 4733 4734 /* 4735 * Rx and Tx descriptors needs 256 bytes alignment. 4736 * dma_alloc_coherent provides more. 4737 */ 4738 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4739 &tp->TxPhyAddr, GFP_KERNEL); 4740 if (!tp->TxDescArray) 4741 goto out; 4742 4743 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4744 &tp->RxPhyAddr, GFP_KERNEL); 4745 if (!tp->RxDescArray) 4746 goto err_free_tx_0; 4747 4748 retval = rtl8169_init_ring(tp); 4749 if (retval < 0) 4750 goto err_free_rx_1; 4751 4752 rtl_request_firmware(tp); 4753 4754 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4755 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt, 4756 irqflags, dev->name, tp); 4757 if (retval < 0) 4758 goto err_release_fw_2; 4759 4760 retval = r8169_phy_connect(tp); 4761 if (retval) 4762 goto err_free_irq; 4763 4764 rtl8169_up(tp); 4765 rtl8169_init_counter_offsets(tp); 4766 netif_start_queue(dev); 4767 out: 4768 pm_runtime_put_sync(&pdev->dev); 4769 4770 return retval; 4771 4772 err_free_irq: 4773 free_irq(pci_irq_vector(pdev, 0), tp); 4774 err_release_fw_2: 4775 rtl_release_firmware(tp); 4776 rtl8169_rx_clear(tp); 4777 err_free_rx_1: 4778 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4779 tp->RxPhyAddr); 4780 tp->RxDescArray = NULL; 4781 err_free_tx_0: 4782 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4783 tp->TxPhyAddr); 4784 tp->TxDescArray = NULL; 4785 goto out; 4786 } 4787 4788 static void 4789 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4790 { 4791 struct rtl8169_private *tp = netdev_priv(dev); 4792 struct pci_dev *pdev = tp->pci_dev; 4793 struct rtl8169_counters *counters = tp->counters; 4794 4795 pm_runtime_get_noresume(&pdev->dev); 4796 4797 netdev_stats_to_stats64(stats, &dev->stats); 4798 dev_fetch_sw_netstats(stats, dev->tstats); 4799 4800 /* 4801 * Fetch additional counter values missing in stats collected by driver 4802 * from tally counters. 4803 */ 4804 if (pm_runtime_active(&pdev->dev)) 4805 rtl8169_update_counters(tp); 4806 4807 /* 4808 * Subtract values fetched during initalization. 4809 * See rtl8169_init_counter_offsets for a description why we do that. 4810 */ 4811 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4812 le64_to_cpu(tp->tc_offset.tx_errors); 4813 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4814 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4815 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4816 le16_to_cpu(tp->tc_offset.tx_aborted); 4817 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4818 le16_to_cpu(tp->tc_offset.rx_missed); 4819 4820 pm_runtime_put_noidle(&pdev->dev); 4821 } 4822 4823 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4824 { 4825 netif_device_detach(tp->dev); 4826 4827 if (netif_running(tp->dev)) 4828 rtl8169_down(tp); 4829 } 4830 4831 #ifdef CONFIG_PM 4832 4833 static int rtl8169_runtime_resume(struct device *dev) 4834 { 4835 struct rtl8169_private *tp = dev_get_drvdata(dev); 4836 4837 rtl_rar_set(tp, tp->dev->dev_addr); 4838 __rtl8169_set_wol(tp, tp->saved_wolopts); 4839 4840 if (tp->TxDescArray) 4841 rtl8169_up(tp); 4842 4843 netif_device_attach(tp->dev); 4844 4845 return 0; 4846 } 4847 4848 static int __maybe_unused rtl8169_suspend(struct device *device) 4849 { 4850 struct rtl8169_private *tp = dev_get_drvdata(device); 4851 4852 rtnl_lock(); 4853 rtl8169_net_suspend(tp); 4854 if (!device_may_wakeup(tp_to_dev(tp))) 4855 clk_disable_unprepare(tp->clk); 4856 rtnl_unlock(); 4857 4858 return 0; 4859 } 4860 4861 static int __maybe_unused rtl8169_resume(struct device *device) 4862 { 4863 struct rtl8169_private *tp = dev_get_drvdata(device); 4864 4865 if (!device_may_wakeup(tp_to_dev(tp))) 4866 clk_prepare_enable(tp->clk); 4867 4868 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4869 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4870 rtl_init_rxcfg(tp); 4871 4872 return rtl8169_runtime_resume(device); 4873 } 4874 4875 static int rtl8169_runtime_suspend(struct device *device) 4876 { 4877 struct rtl8169_private *tp = dev_get_drvdata(device); 4878 4879 if (!tp->TxDescArray) { 4880 netif_device_detach(tp->dev); 4881 return 0; 4882 } 4883 4884 rtnl_lock(); 4885 __rtl8169_set_wol(tp, WAKE_PHY); 4886 rtl8169_net_suspend(tp); 4887 rtnl_unlock(); 4888 4889 return 0; 4890 } 4891 4892 static int rtl8169_runtime_idle(struct device *device) 4893 { 4894 struct rtl8169_private *tp = dev_get_drvdata(device); 4895 4896 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4897 pm_schedule_suspend(device, 10000); 4898 4899 return -EBUSY; 4900 } 4901 4902 static const struct dev_pm_ops rtl8169_pm_ops = { 4903 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4904 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4905 rtl8169_runtime_idle) 4906 }; 4907 4908 #endif /* CONFIG_PM */ 4909 4910 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4911 { 4912 /* WoL fails with 8168b when the receiver is disabled. */ 4913 switch (tp->mac_version) { 4914 case RTL_GIGA_MAC_VER_11: 4915 case RTL_GIGA_MAC_VER_12: 4916 case RTL_GIGA_MAC_VER_17: 4917 pci_clear_master(tp->pci_dev); 4918 4919 RTL_W8(tp, ChipCmd, CmdRxEnb); 4920 rtl_pci_commit(tp); 4921 break; 4922 default: 4923 break; 4924 } 4925 } 4926 4927 static void rtl_shutdown(struct pci_dev *pdev) 4928 { 4929 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4930 4931 rtnl_lock(); 4932 rtl8169_net_suspend(tp); 4933 rtnl_unlock(); 4934 4935 /* Restore original MAC address */ 4936 rtl_rar_set(tp, tp->dev->perm_addr); 4937 4938 if (system_state == SYSTEM_POWER_OFF) { 4939 if (tp->saved_wolopts) 4940 rtl_wol_shutdown_quirk(tp); 4941 4942 pci_wake_from_d3(pdev, tp->saved_wolopts); 4943 pci_set_power_state(pdev, PCI_D3hot); 4944 } 4945 } 4946 4947 static void rtl_remove_one(struct pci_dev *pdev) 4948 { 4949 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4950 4951 if (pci_dev_run_wake(pdev)) 4952 pm_runtime_get_noresume(&pdev->dev); 4953 4954 unregister_netdev(tp->dev); 4955 4956 if (tp->dash_type != RTL_DASH_NONE) 4957 rtl8168_driver_stop(tp); 4958 4959 rtl_release_firmware(tp); 4960 4961 /* restore original MAC address */ 4962 rtl_rar_set(tp, tp->dev->perm_addr); 4963 } 4964 4965 static const struct net_device_ops rtl_netdev_ops = { 4966 .ndo_open = rtl_open, 4967 .ndo_stop = rtl8169_close, 4968 .ndo_get_stats64 = rtl8169_get_stats64, 4969 .ndo_start_xmit = rtl8169_start_xmit, 4970 .ndo_features_check = rtl8169_features_check, 4971 .ndo_tx_timeout = rtl8169_tx_timeout, 4972 .ndo_validate_addr = eth_validate_addr, 4973 .ndo_change_mtu = rtl8169_change_mtu, 4974 .ndo_fix_features = rtl8169_fix_features, 4975 .ndo_set_features = rtl8169_set_features, 4976 .ndo_set_mac_address = rtl_set_mac_address, 4977 .ndo_eth_ioctl = phy_do_ioctl_running, 4978 .ndo_set_rx_mode = rtl_set_rx_mode, 4979 #ifdef CONFIG_NET_POLL_CONTROLLER 4980 .ndo_poll_controller = rtl8169_netpoll, 4981 #endif 4982 4983 }; 4984 4985 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4986 { 4987 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4988 4989 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4990 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4991 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4992 /* special workaround needed */ 4993 tp->irq_mask |= RxFIFOOver; 4994 else 4995 tp->irq_mask |= RxOverflow; 4996 } 4997 4998 static int rtl_alloc_irq(struct rtl8169_private *tp) 4999 { 5000 unsigned int flags; 5001 5002 switch (tp->mac_version) { 5003 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5004 rtl_unlock_config_regs(tp); 5005 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5006 rtl_lock_config_regs(tp); 5007 fallthrough; 5008 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5009 flags = PCI_IRQ_LEGACY; 5010 break; 5011 default: 5012 flags = PCI_IRQ_ALL_TYPES; 5013 break; 5014 } 5015 5016 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5017 } 5018 5019 static void rtl_read_mac_address(struct rtl8169_private *tp, 5020 u8 mac_addr[ETH_ALEN]) 5021 { 5022 /* Get MAC address */ 5023 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5024 u32 value; 5025 5026 value = rtl_eri_read(tp, 0xe0); 5027 put_unaligned_le32(value, mac_addr); 5028 value = rtl_eri_read(tp, 0xe4); 5029 put_unaligned_le16(value, mac_addr + 4); 5030 } else if (rtl_is_8125(tp)) { 5031 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5032 } 5033 } 5034 5035 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5036 { 5037 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5038 } 5039 5040 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5041 { 5042 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5043 } 5044 5045 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5046 { 5047 struct rtl8169_private *tp = mii_bus->priv; 5048 5049 if (phyaddr > 0) 5050 return -ENODEV; 5051 5052 return rtl_readphy(tp, phyreg); 5053 } 5054 5055 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5056 int phyreg, u16 val) 5057 { 5058 struct rtl8169_private *tp = mii_bus->priv; 5059 5060 if (phyaddr > 0) 5061 return -ENODEV; 5062 5063 rtl_writephy(tp, phyreg, val); 5064 5065 return 0; 5066 } 5067 5068 static int r8169_mdio_register(struct rtl8169_private *tp) 5069 { 5070 struct pci_dev *pdev = tp->pci_dev; 5071 struct mii_bus *new_bus; 5072 int ret; 5073 5074 new_bus = devm_mdiobus_alloc(&pdev->dev); 5075 if (!new_bus) 5076 return -ENOMEM; 5077 5078 new_bus->name = "r8169"; 5079 new_bus->priv = tp; 5080 new_bus->parent = &pdev->dev; 5081 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5082 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5083 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5084 5085 new_bus->read = r8169_mdio_read_reg; 5086 new_bus->write = r8169_mdio_write_reg; 5087 5088 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5089 if (ret) 5090 return ret; 5091 5092 tp->phydev = mdiobus_get_phy(new_bus, 0); 5093 if (!tp->phydev) { 5094 return -ENODEV; 5095 } else if (!tp->phydev->drv) { 5096 /* Most chip versions fail with the genphy driver. 5097 * Therefore ensure that the dedicated PHY driver is loaded. 5098 */ 5099 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5100 tp->phydev->phy_id); 5101 return -EUNATCH; 5102 } 5103 5104 tp->phydev->mac_managed_pm = 1; 5105 5106 phy_support_asym_pause(tp->phydev); 5107 5108 /* PHY will be woken up in rtl_open() */ 5109 phy_suspend(tp->phydev); 5110 5111 return 0; 5112 } 5113 5114 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5115 { 5116 rtl_enable_rxdvgate(tp); 5117 5118 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5119 msleep(1); 5120 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5121 5122 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5123 r8168g_wait_ll_share_fifo_ready(tp); 5124 5125 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5126 r8168g_wait_ll_share_fifo_ready(tp); 5127 } 5128 5129 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5130 { 5131 rtl_enable_rxdvgate(tp); 5132 5133 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5134 msleep(1); 5135 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5136 5137 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5138 r8168g_wait_ll_share_fifo_ready(tp); 5139 5140 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5141 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5142 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5143 r8168g_wait_ll_share_fifo_ready(tp); 5144 } 5145 5146 static void rtl_hw_initialize(struct rtl8169_private *tp) 5147 { 5148 switch (tp->mac_version) { 5149 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 5150 rtl8168ep_stop_cmac(tp); 5151 fallthrough; 5152 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5153 rtl_hw_init_8168g(tp); 5154 break; 5155 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5156 rtl_hw_init_8125(tp); 5157 break; 5158 default: 5159 break; 5160 } 5161 } 5162 5163 static int rtl_jumbo_max(struct rtl8169_private *tp) 5164 { 5165 /* Non-GBit versions don't support jumbo frames */ 5166 if (!tp->supports_gmii) 5167 return 0; 5168 5169 switch (tp->mac_version) { 5170 /* RTL8169 */ 5171 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5172 return JUMBO_7K; 5173 /* RTL8168b */ 5174 case RTL_GIGA_MAC_VER_11: 5175 case RTL_GIGA_MAC_VER_12: 5176 case RTL_GIGA_MAC_VER_17: 5177 return JUMBO_4K; 5178 /* RTL8168c */ 5179 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5180 return JUMBO_6K; 5181 default: 5182 return JUMBO_9K; 5183 } 5184 } 5185 5186 static void rtl_disable_clk(void *data) 5187 { 5188 clk_disable_unprepare(data); 5189 } 5190 5191 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5192 { 5193 struct device *d = tp_to_dev(tp); 5194 struct clk *clk; 5195 int rc; 5196 5197 clk = devm_clk_get(d, "ether_clk"); 5198 if (IS_ERR(clk)) { 5199 rc = PTR_ERR(clk); 5200 if (rc == -ENOENT) 5201 /* clk-core allows NULL (for suspend / resume) */ 5202 rc = 0; 5203 else 5204 dev_err_probe(d, rc, "failed to get clk\n"); 5205 } else { 5206 tp->clk = clk; 5207 rc = clk_prepare_enable(clk); 5208 if (rc) 5209 dev_err(d, "failed to enable clk: %d\n", rc); 5210 else 5211 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5212 } 5213 5214 return rc; 5215 } 5216 5217 static void rtl_init_mac_address(struct rtl8169_private *tp) 5218 { 5219 struct net_device *dev = tp->dev; 5220 u8 *mac_addr = dev->dev_addr; 5221 int rc; 5222 5223 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5224 if (!rc) 5225 goto done; 5226 5227 rtl_read_mac_address(tp, mac_addr); 5228 if (is_valid_ether_addr(mac_addr)) 5229 goto done; 5230 5231 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5232 if (is_valid_ether_addr(mac_addr)) 5233 goto done; 5234 5235 eth_hw_addr_random(dev); 5236 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5237 done: 5238 rtl_rar_set(tp, mac_addr); 5239 } 5240 5241 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5242 { 5243 struct rtl8169_private *tp; 5244 int jumbo_max, region, rc; 5245 enum mac_version chipset; 5246 struct net_device *dev; 5247 u16 xid; 5248 5249 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5250 if (!dev) 5251 return -ENOMEM; 5252 5253 SET_NETDEV_DEV(dev, &pdev->dev); 5254 dev->netdev_ops = &rtl_netdev_ops; 5255 tp = netdev_priv(dev); 5256 tp->dev = dev; 5257 tp->pci_dev = pdev; 5258 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5259 tp->eee_adv = -1; 5260 tp->ocp_base = OCP_STD_PHY_BASE; 5261 5262 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5263 struct pcpu_sw_netstats); 5264 if (!dev->tstats) 5265 return -ENOMEM; 5266 5267 /* Get the *optional* external "ether_clk" used on some boards */ 5268 rc = rtl_get_ether_clk(tp); 5269 if (rc) 5270 return rc; 5271 5272 /* Disable ASPM L1 as that cause random device stop working 5273 * problems as well as full system hangs for some PCIe devices users. 5274 */ 5275 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5276 tp->aspm_manageable = !rc; 5277 5278 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5279 rc = pcim_enable_device(pdev); 5280 if (rc < 0) { 5281 dev_err(&pdev->dev, "enable failure\n"); 5282 return rc; 5283 } 5284 5285 if (pcim_set_mwi(pdev) < 0) 5286 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5287 5288 /* use first MMIO region */ 5289 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5290 if (region < 0) { 5291 dev_err(&pdev->dev, "no MMIO resource found\n"); 5292 return -ENODEV; 5293 } 5294 5295 /* check for weird/broken PCI region reporting */ 5296 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5297 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5298 return -ENODEV; 5299 } 5300 5301 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5302 if (rc < 0) { 5303 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5304 return rc; 5305 } 5306 5307 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5308 5309 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5310 5311 /* Identify chip attached to board */ 5312 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5313 if (chipset == RTL_GIGA_MAC_NONE) { 5314 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5315 return -ENODEV; 5316 } 5317 5318 tp->mac_version = chipset; 5319 5320 tp->dash_type = rtl_check_dash(tp); 5321 5322 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5323 5324 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5325 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5326 dev->features |= NETIF_F_HIGHDMA; 5327 5328 rtl_init_rxcfg(tp); 5329 5330 rtl8169_irq_mask_and_ack(tp); 5331 5332 rtl_hw_initialize(tp); 5333 5334 rtl_hw_reset(tp); 5335 5336 rc = rtl_alloc_irq(tp); 5337 if (rc < 0) { 5338 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5339 return rc; 5340 } 5341 5342 INIT_WORK(&tp->wk.work, rtl_task); 5343 5344 rtl_init_mac_address(tp); 5345 5346 dev->ethtool_ops = &rtl8169_ethtool_ops; 5347 5348 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5349 5350 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5351 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5352 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5353 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5354 5355 /* 5356 * Pretend we are using VLANs; This bypasses a nasty bug where 5357 * Interrupts stop flowing on high load on 8110SCd controllers. 5358 */ 5359 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5360 /* Disallow toggling */ 5361 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5362 5363 if (rtl_chip_supports_csum_v2(tp)) 5364 dev->hw_features |= NETIF_F_IPV6_CSUM; 5365 5366 dev->features |= dev->hw_features; 5367 5368 /* There has been a number of reports that using SG/TSO results in 5369 * tx timeouts. However for a lot of people SG/TSO works fine. 5370 * Therefore disable both features by default, but allow users to 5371 * enable them. Use at own risk! 5372 */ 5373 if (rtl_chip_supports_csum_v2(tp)) { 5374 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5375 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5376 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5377 } else { 5378 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5379 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5380 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5381 } 5382 5383 dev->hw_features |= NETIF_F_RXALL; 5384 dev->hw_features |= NETIF_F_RXFCS; 5385 5386 /* configure chip for default features */ 5387 rtl8169_set_features(dev, dev->features); 5388 5389 rtl_set_d3_pll_down(tp, true); 5390 5391 jumbo_max = rtl_jumbo_max(tp); 5392 if (jumbo_max) 5393 dev->max_mtu = jumbo_max; 5394 5395 rtl_set_irq_mask(tp); 5396 5397 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5398 5399 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5400 &tp->counters_phys_addr, 5401 GFP_KERNEL); 5402 if (!tp->counters) 5403 return -ENOMEM; 5404 5405 pci_set_drvdata(pdev, tp); 5406 5407 rc = r8169_mdio_register(tp); 5408 if (rc) 5409 return rc; 5410 5411 rc = register_netdev(dev); 5412 if (rc) 5413 return rc; 5414 5415 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5416 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5417 pci_irq_vector(pdev, 0)); 5418 5419 if (jumbo_max) 5420 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5421 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5422 "ok" : "ko"); 5423 5424 if (tp->dash_type != RTL_DASH_NONE) { 5425 netdev_info(dev, "DASH enabled\n"); 5426 rtl8168_driver_start(tp); 5427 } 5428 5429 if (pci_dev_run_wake(pdev)) 5430 pm_runtime_put_sync(&pdev->dev); 5431 5432 return 0; 5433 } 5434 5435 static struct pci_driver rtl8169_pci_driver = { 5436 .name = KBUILD_MODNAME, 5437 .id_table = rtl8169_pci_tbl, 5438 .probe = rtl_init_one, 5439 .remove = rtl_remove_one, 5440 .shutdown = rtl_shutdown, 5441 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5442 }; 5443 5444 module_pci_driver(rtl8169_pci_driver); 5445