1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define MODULENAME "r8169" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 56 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 59 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 60 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define OCP_STD_PHY_BASE 0xa400 77 78 #define RTL_CFG_NO_GBIT 1 79 80 /* write/read MMIO register */ 81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 87 88 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 92 93 static const struct { 94 const char *name; 95 const char *fw_name; 96 } rtl_chip_infos[] = { 97 /* PCI devices. */ 98 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 99 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 100 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 101 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 102 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 103 /* PCI-E devices. */ 104 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 106 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 107 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 108 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 111 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 112 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 113 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 114 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 115 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 119 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 121 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 122 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 123 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 125 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 127 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 128 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 129 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 130 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 131 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 132 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 133 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 134 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 135 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 136 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 137 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 138 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 139 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 140 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 141 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 142 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 143 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 144 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 145 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 148 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 149 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 150 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 151 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 152 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 153 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 154 }; 155 156 static const struct pci_device_id rtl8169_pci_tbl[] = { 157 { PCI_VDEVICE(REALTEK, 0x2502) }, 158 { PCI_VDEVICE(REALTEK, 0x2600) }, 159 { PCI_VDEVICE(REALTEK, 0x8129) }, 160 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 161 { PCI_VDEVICE(REALTEK, 0x8161) }, 162 { PCI_VDEVICE(REALTEK, 0x8167) }, 163 { PCI_VDEVICE(REALTEK, 0x8168) }, 164 { PCI_VDEVICE(NCUBE, 0x8168) }, 165 { PCI_VDEVICE(REALTEK, 0x8169) }, 166 { PCI_VENDOR_ID_DLINK, 0x4300, 167 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 168 { PCI_VDEVICE(DLINK, 0x4300) }, 169 { PCI_VDEVICE(DLINK, 0x4302) }, 170 { PCI_VDEVICE(AT, 0xc107) }, 171 { PCI_VDEVICE(USR, 0x0116) }, 172 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 173 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 174 { PCI_VDEVICE(REALTEK, 0x8125) }, 175 { PCI_VDEVICE(REALTEK, 0x3000) }, 176 {} 177 }; 178 179 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 180 181 enum rtl_registers { 182 MAC0 = 0, /* Ethernet hardware address. */ 183 MAC4 = 4, 184 MAR0 = 8, /* Multicast filter. */ 185 CounterAddrLow = 0x10, 186 CounterAddrHigh = 0x14, 187 TxDescStartAddrLow = 0x20, 188 TxDescStartAddrHigh = 0x24, 189 TxHDescStartAddrLow = 0x28, 190 TxHDescStartAddrHigh = 0x2c, 191 FLASH = 0x30, 192 ERSR = 0x36, 193 ChipCmd = 0x37, 194 TxPoll = 0x38, 195 IntrMask = 0x3c, 196 IntrStatus = 0x3e, 197 198 TxConfig = 0x40, 199 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 200 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 201 202 RxConfig = 0x44, 203 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 204 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 205 #define RXCFG_FIFO_SHIFT 13 206 /* No threshold before first PCI xfer */ 207 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 208 #define RX_EARLY_OFF (1 << 11) 209 #define RXCFG_DMA_SHIFT 8 210 /* Unlimited maximum PCI burst. */ 211 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 212 213 Cfg9346 = 0x50, 214 Config0 = 0x51, 215 Config1 = 0x52, 216 Config2 = 0x53, 217 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 218 219 Config3 = 0x54, 220 Config4 = 0x55, 221 Config5 = 0x56, 222 PHYAR = 0x60, 223 PHYstatus = 0x6c, 224 RxMaxSize = 0xda, 225 CPlusCmd = 0xe0, 226 IntrMitigate = 0xe2, 227 228 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 229 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 230 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 231 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 232 233 #define RTL_COALESCE_T_MAX 0x0fU 234 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 235 236 RxDescAddrLow = 0xe4, 237 RxDescAddrHigh = 0xe8, 238 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 239 240 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 241 242 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 243 244 #define TxPacketMax (8064 >> 7) 245 #define EarlySize 0x27 246 247 FuncEvent = 0xf0, 248 FuncEventMask = 0xf4, 249 FuncPresetState = 0xf8, 250 IBCR0 = 0xf8, 251 IBCR2 = 0xf9, 252 IBIMR0 = 0xfa, 253 IBISR0 = 0xfb, 254 FuncForceEvent = 0xfc, 255 }; 256 257 enum rtl8168_8101_registers { 258 CSIDR = 0x64, 259 CSIAR = 0x68, 260 #define CSIAR_FLAG 0x80000000 261 #define CSIAR_WRITE_CMD 0x80000000 262 #define CSIAR_BYTE_ENABLE 0x0000f000 263 #define CSIAR_ADDR_MASK 0x00000fff 264 PMCH = 0x6f, 265 #define D3COLD_NO_PLL_DOWN BIT(7) 266 #define D3HOT_NO_PLL_DOWN BIT(6) 267 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 268 EPHYAR = 0x80, 269 #define EPHYAR_FLAG 0x80000000 270 #define EPHYAR_WRITE_CMD 0x80000000 271 #define EPHYAR_REG_MASK 0x1f 272 #define EPHYAR_REG_SHIFT 16 273 #define EPHYAR_DATA_MASK 0xffff 274 DLLPR = 0xd0, 275 #define PFM_EN (1 << 6) 276 #define TX_10M_PS_EN (1 << 7) 277 DBG_REG = 0xd1, 278 #define FIX_NAK_1 (1 << 4) 279 #define FIX_NAK_2 (1 << 3) 280 TWSI = 0xd2, 281 MCU = 0xd3, 282 #define NOW_IS_OOB (1 << 7) 283 #define TX_EMPTY (1 << 5) 284 #define RX_EMPTY (1 << 4) 285 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 286 #define EN_NDP (1 << 3) 287 #define EN_OOB_RESET (1 << 2) 288 #define LINK_LIST_RDY (1 << 1) 289 EFUSEAR = 0xdc, 290 #define EFUSEAR_FLAG 0x80000000 291 #define EFUSEAR_WRITE_CMD 0x80000000 292 #define EFUSEAR_READ_CMD 0x00000000 293 #define EFUSEAR_REG_MASK 0x03ff 294 #define EFUSEAR_REG_SHIFT 8 295 #define EFUSEAR_DATA_MASK 0xff 296 MISC_1 = 0xf2, 297 #define PFM_D3COLD_EN (1 << 6) 298 }; 299 300 enum rtl8168_registers { 301 LED_FREQ = 0x1a, 302 EEE_LED = 0x1b, 303 ERIDR = 0x70, 304 ERIAR = 0x74, 305 #define ERIAR_FLAG 0x80000000 306 #define ERIAR_WRITE_CMD 0x80000000 307 #define ERIAR_READ_CMD 0x00000000 308 #define ERIAR_ADDR_BYTE_ALIGN 4 309 #define ERIAR_TYPE_SHIFT 16 310 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 312 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 313 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 314 #define ERIAR_MASK_SHIFT 12 315 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 317 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 318 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 319 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 320 EPHY_RXER_NUM = 0x7c, 321 OCPDR = 0xb0, /* OCP GPHY access */ 322 #define OCPDR_WRITE_CMD 0x80000000 323 #define OCPDR_READ_CMD 0x00000000 324 #define OCPDR_REG_MASK 0x7f 325 #define OCPDR_GPHY_REG_SHIFT 16 326 #define OCPDR_DATA_MASK 0xffff 327 OCPAR = 0xb4, 328 #define OCPAR_FLAG 0x80000000 329 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 330 #define OCPAR_GPHY_READ_CMD 0x0000f060 331 GPHY_OCP = 0xb8, 332 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 333 MISC = 0xf0, /* 8168e only. */ 334 #define TXPLA_RST (1 << 29) 335 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 336 #define PWM_EN (1 << 22) 337 #define RXDV_GATED_EN (1 << 19) 338 #define EARLY_TALLY_EN (1 << 16) 339 }; 340 341 enum rtl8125_registers { 342 IntrMask_8125 = 0x38, 343 IntrStatus_8125 = 0x3c, 344 TxPoll_8125 = 0x90, 345 MAC0_BKP = 0x19e0, 346 EEE_TXIDLE_TIMER_8125 = 0x6048, 347 }; 348 349 #define RX_VLAN_INNER_8125 BIT(22) 350 #define RX_VLAN_OUTER_8125 BIT(23) 351 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 352 353 #define RX_FETCH_DFLT_8125 (8 << 27) 354 355 enum rtl_register_content { 356 /* InterruptStatusBits */ 357 SYSErr = 0x8000, 358 PCSTimeout = 0x4000, 359 SWInt = 0x0100, 360 TxDescUnavail = 0x0080, 361 RxFIFOOver = 0x0040, 362 LinkChg = 0x0020, 363 RxOverflow = 0x0010, 364 TxErr = 0x0008, 365 TxOK = 0x0004, 366 RxErr = 0x0002, 367 RxOK = 0x0001, 368 369 /* RxStatusDesc */ 370 RxRWT = (1 << 22), 371 RxRES = (1 << 21), 372 RxRUNT = (1 << 20), 373 RxCRC = (1 << 19), 374 375 /* ChipCmdBits */ 376 StopReq = 0x80, 377 CmdReset = 0x10, 378 CmdRxEnb = 0x08, 379 CmdTxEnb = 0x04, 380 RxBufEmpty = 0x01, 381 382 /* TXPoll register p.5 */ 383 HPQ = 0x80, /* Poll cmd on the high prio queue */ 384 NPQ = 0x40, /* Poll cmd on the low prio queue */ 385 FSWInt = 0x01, /* Forced software interrupt */ 386 387 /* Cfg9346Bits */ 388 Cfg9346_Lock = 0x00, 389 Cfg9346_Unlock = 0xc0, 390 391 /* rx_mode_bits */ 392 AcceptErr = 0x20, 393 AcceptRunt = 0x10, 394 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 395 AcceptBroadcast = 0x08, 396 AcceptMulticast = 0x04, 397 AcceptMyPhys = 0x02, 398 AcceptAllPhys = 0x01, 399 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 400 #define RX_CONFIG_ACCEPT_MASK 0x3f 401 402 /* TxConfigBits */ 403 TxInterFrameGapShift = 24, 404 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 405 406 /* Config1 register p.24 */ 407 LEDS1 = (1 << 7), 408 LEDS0 = (1 << 6), 409 Speed_down = (1 << 4), 410 MEMMAP = (1 << 3), 411 IOMAP = (1 << 2), 412 VPD = (1 << 1), 413 PMEnable = (1 << 0), /* Power Management Enable */ 414 415 /* Config2 register p. 25 */ 416 ClkReqEn = (1 << 7), /* Clock Request Enable */ 417 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 418 PCI_Clock_66MHz = 0x01, 419 PCI_Clock_33MHz = 0x00, 420 421 /* Config3 register p.25 */ 422 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 423 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 424 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 425 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 426 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 427 428 /* Config4 register */ 429 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 430 431 /* Config5 register p.27 */ 432 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 433 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 434 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 435 Spi_en = (1 << 3), 436 LanWake = (1 << 1), /* LanWake enable/disable */ 437 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 438 ASPM_en = (1 << 0), /* ASPM enable */ 439 440 /* CPlusCmd p.31 */ 441 EnableBist = (1 << 15), // 8168 8101 442 Mac_dbgo_oe = (1 << 14), // 8168 8101 443 EnAnaPLL = (1 << 14), // 8169 444 Normal_mode = (1 << 13), // unused 445 Force_half_dup = (1 << 12), // 8168 8101 446 Force_rxflow_en = (1 << 11), // 8168 8101 447 Force_txflow_en = (1 << 10), // 8168 8101 448 Cxpl_dbg_sel = (1 << 9), // 8168 8101 449 ASF = (1 << 8), // 8168 8101 450 PktCntrDisable = (1 << 7), // 8168 8101 451 Mac_dbgo_sel = 0x001c, // 8168 452 RxVlan = (1 << 6), 453 RxChkSum = (1 << 5), 454 PCIDAC = (1 << 4), 455 PCIMulRW = (1 << 3), 456 #define INTT_MASK GENMASK(1, 0) 457 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 458 459 /* rtl8169_PHYstatus */ 460 TBI_Enable = 0x80, 461 TxFlowCtrl = 0x40, 462 RxFlowCtrl = 0x20, 463 _1000bpsF = 0x10, 464 _100bps = 0x08, 465 _10bps = 0x04, 466 LinkStatus = 0x02, 467 FullDup = 0x01, 468 469 /* ResetCounterCommand */ 470 CounterReset = 0x1, 471 472 /* DumpCounterCommand */ 473 CounterDump = 0x8, 474 475 /* magic enable v2 */ 476 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 477 }; 478 479 enum rtl_desc_bit { 480 /* First doubleword. */ 481 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 482 RingEnd = (1 << 30), /* End of descriptor ring */ 483 FirstFrag = (1 << 29), /* First segment of a packet */ 484 LastFrag = (1 << 28), /* Final segment of a packet */ 485 }; 486 487 /* Generic case. */ 488 enum rtl_tx_desc_bit { 489 /* First doubleword. */ 490 TD_LSO = (1 << 27), /* Large Send Offload */ 491 #define TD_MSS_MAX 0x07ffu /* MSS value */ 492 493 /* Second doubleword. */ 494 TxVlanTag = (1 << 17), /* Add VLAN tag */ 495 }; 496 497 /* 8169, 8168b and 810x except 8102e. */ 498 enum rtl_tx_desc_bit_0 { 499 /* First doubleword. */ 500 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 501 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 502 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 503 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 504 }; 505 506 /* 8102e, 8168c and beyond. */ 507 enum rtl_tx_desc_bit_1 { 508 /* First doubleword. */ 509 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 510 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 511 #define GTTCPHO_SHIFT 18 512 #define GTTCPHO_MAX 0x7f 513 514 /* Second doubleword. */ 515 #define TCPHO_SHIFT 18 516 #define TCPHO_MAX 0x3ff 517 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 518 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 519 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 520 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 521 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 522 }; 523 524 enum rtl_rx_desc_bit { 525 /* Rx private */ 526 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 527 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 528 529 #define RxProtoUDP (PID1) 530 #define RxProtoTCP (PID0) 531 #define RxProtoIP (PID1 | PID0) 532 #define RxProtoMask RxProtoIP 533 534 IPFail = (1 << 16), /* IP checksum failed */ 535 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 536 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 537 538 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 539 540 RxVlanTag = (1 << 16), /* VLAN tag available */ 541 }; 542 543 #define RTL_GSO_MAX_SIZE_V1 32000 544 #define RTL_GSO_MAX_SEGS_V1 24 545 #define RTL_GSO_MAX_SIZE_V2 64000 546 #define RTL_GSO_MAX_SEGS_V2 64 547 548 struct TxDesc { 549 __le32 opts1; 550 __le32 opts2; 551 __le64 addr; 552 }; 553 554 struct RxDesc { 555 __le32 opts1; 556 __le32 opts2; 557 __le64 addr; 558 }; 559 560 struct ring_info { 561 struct sk_buff *skb; 562 u32 len; 563 }; 564 565 struct rtl8169_counters { 566 __le64 tx_packets; 567 __le64 rx_packets; 568 __le64 tx_errors; 569 __le32 rx_errors; 570 __le16 rx_missed; 571 __le16 align_errors; 572 __le32 tx_one_collision; 573 __le32 tx_multi_collision; 574 __le64 rx_unicast; 575 __le64 rx_broadcast; 576 __le32 rx_multicast; 577 __le16 tx_aborted; 578 __le16 tx_underun; 579 }; 580 581 struct rtl8169_tc_offsets { 582 bool inited; 583 __le64 tx_errors; 584 __le32 tx_multi_collision; 585 __le16 tx_aborted; 586 __le16 rx_missed; 587 }; 588 589 enum rtl_flag { 590 RTL_FLAG_TASK_ENABLED = 0, 591 RTL_FLAG_TASK_RESET_PENDING, 592 RTL_FLAG_MAX 593 }; 594 595 enum rtl_dash_type { 596 RTL_DASH_NONE, 597 RTL_DASH_DP, 598 RTL_DASH_EP, 599 }; 600 601 struct rtl8169_private { 602 void __iomem *mmio_addr; /* memory map physical address */ 603 struct pci_dev *pci_dev; 604 struct net_device *dev; 605 struct phy_device *phydev; 606 struct napi_struct napi; 607 enum mac_version mac_version; 608 enum rtl_dash_type dash_type; 609 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 610 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 611 u32 dirty_tx; 612 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 613 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 614 dma_addr_t TxPhyAddr; 615 dma_addr_t RxPhyAddr; 616 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 617 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 618 u16 cp_cmd; 619 u32 irq_mask; 620 struct clk *clk; 621 622 struct { 623 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 624 struct work_struct work; 625 } wk; 626 627 unsigned supports_gmii:1; 628 unsigned aspm_manageable:1; 629 dma_addr_t counters_phys_addr; 630 struct rtl8169_counters *counters; 631 struct rtl8169_tc_offsets tc_offset; 632 u32 saved_wolopts; 633 int eee_adv; 634 635 const char *fw_name; 636 struct rtl_fw *rtl_fw; 637 638 u32 ocp_base; 639 }; 640 641 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 642 643 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 644 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 645 MODULE_SOFTDEP("pre: realtek"); 646 MODULE_LICENSE("GPL"); 647 MODULE_FIRMWARE(FIRMWARE_8168D_1); 648 MODULE_FIRMWARE(FIRMWARE_8168D_2); 649 MODULE_FIRMWARE(FIRMWARE_8168E_1); 650 MODULE_FIRMWARE(FIRMWARE_8168E_2); 651 MODULE_FIRMWARE(FIRMWARE_8168E_3); 652 MODULE_FIRMWARE(FIRMWARE_8105E_1); 653 MODULE_FIRMWARE(FIRMWARE_8168F_1); 654 MODULE_FIRMWARE(FIRMWARE_8168F_2); 655 MODULE_FIRMWARE(FIRMWARE_8402_1); 656 MODULE_FIRMWARE(FIRMWARE_8411_1); 657 MODULE_FIRMWARE(FIRMWARE_8411_2); 658 MODULE_FIRMWARE(FIRMWARE_8106E_1); 659 MODULE_FIRMWARE(FIRMWARE_8106E_2); 660 MODULE_FIRMWARE(FIRMWARE_8168G_2); 661 MODULE_FIRMWARE(FIRMWARE_8168G_3); 662 MODULE_FIRMWARE(FIRMWARE_8168H_1); 663 MODULE_FIRMWARE(FIRMWARE_8168H_2); 664 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 665 MODULE_FIRMWARE(FIRMWARE_8107E_1); 666 MODULE_FIRMWARE(FIRMWARE_8107E_2); 667 MODULE_FIRMWARE(FIRMWARE_8125A_3); 668 MODULE_FIRMWARE(FIRMWARE_8125B_2); 669 670 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 671 { 672 return &tp->pci_dev->dev; 673 } 674 675 static void rtl_lock_config_regs(struct rtl8169_private *tp) 676 { 677 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 678 } 679 680 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 681 { 682 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 683 } 684 685 static void rtl_pci_commit(struct rtl8169_private *tp) 686 { 687 /* Read an arbitrary register to commit a preceding PCI write */ 688 RTL_R8(tp, ChipCmd); 689 } 690 691 static bool rtl_is_8125(struct rtl8169_private *tp) 692 { 693 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 694 } 695 696 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 697 { 698 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 699 tp->mac_version != RTL_GIGA_MAC_VER_39 && 700 tp->mac_version <= RTL_GIGA_MAC_VER_53; 701 } 702 703 static bool rtl_supports_eee(struct rtl8169_private *tp) 704 { 705 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 706 tp->mac_version != RTL_GIGA_MAC_VER_37 && 707 tp->mac_version != RTL_GIGA_MAC_VER_39; 708 } 709 710 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 711 { 712 int i; 713 714 for (i = 0; i < ETH_ALEN; i++) 715 mac[i] = RTL_R8(tp, reg + i); 716 } 717 718 struct rtl_cond { 719 bool (*check)(struct rtl8169_private *); 720 const char *msg; 721 }; 722 723 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 724 unsigned long usecs, int n, bool high) 725 { 726 int i; 727 728 for (i = 0; i < n; i++) { 729 if (c->check(tp) == high) 730 return true; 731 fsleep(usecs); 732 } 733 734 if (net_ratelimit()) 735 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 736 c->msg, !high, n, usecs); 737 return false; 738 } 739 740 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 741 const struct rtl_cond *c, 742 unsigned long d, int n) 743 { 744 return rtl_loop_wait(tp, c, d, n, true); 745 } 746 747 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 748 const struct rtl_cond *c, 749 unsigned long d, int n) 750 { 751 return rtl_loop_wait(tp, c, d, n, false); 752 } 753 754 #define DECLARE_RTL_COND(name) \ 755 static bool name ## _check(struct rtl8169_private *); \ 756 \ 757 static const struct rtl_cond name = { \ 758 .check = name ## _check, \ 759 .msg = #name \ 760 }; \ 761 \ 762 static bool name ## _check(struct rtl8169_private *tp) 763 764 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 765 { 766 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 767 if (type == ERIAR_OOB && 768 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 769 tp->mac_version == RTL_GIGA_MAC_VER_53)) 770 *cmd |= 0x7f0 << 18; 771 } 772 773 DECLARE_RTL_COND(rtl_eriar_cond) 774 { 775 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 776 } 777 778 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 779 u32 val, int type) 780 { 781 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 782 783 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 784 return; 785 786 RTL_W32(tp, ERIDR, val); 787 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 788 RTL_W32(tp, ERIAR, cmd); 789 790 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 791 } 792 793 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 794 u32 val) 795 { 796 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 797 } 798 799 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 800 { 801 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 802 803 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 804 RTL_W32(tp, ERIAR, cmd); 805 806 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 807 RTL_R32(tp, ERIDR) : ~0; 808 } 809 810 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 811 { 812 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 813 } 814 815 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 816 { 817 u32 val = rtl_eri_read(tp, addr); 818 819 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 820 } 821 822 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 823 { 824 rtl_w0w1_eri(tp, addr, p, 0); 825 } 826 827 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 828 { 829 rtl_w0w1_eri(tp, addr, 0, m); 830 } 831 832 static bool rtl_ocp_reg_failure(u32 reg) 833 { 834 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 835 } 836 837 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 838 { 839 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 840 } 841 842 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 843 { 844 if (rtl_ocp_reg_failure(reg)) 845 return; 846 847 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 848 849 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 850 } 851 852 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 853 { 854 if (rtl_ocp_reg_failure(reg)) 855 return 0; 856 857 RTL_W32(tp, GPHY_OCP, reg << 15); 858 859 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 860 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 861 } 862 863 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 864 { 865 if (rtl_ocp_reg_failure(reg)) 866 return; 867 868 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 869 } 870 871 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 872 { 873 if (rtl_ocp_reg_failure(reg)) 874 return 0; 875 876 RTL_W32(tp, OCPDR, reg << 15); 877 878 return RTL_R32(tp, OCPDR); 879 } 880 881 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 882 u16 set) 883 { 884 u16 data = r8168_mac_ocp_read(tp, reg); 885 886 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 887 } 888 889 /* Work around a hw issue with RTL8168g PHY, the quirk disables 890 * PHY MCU interrupts before PHY power-down. 891 */ 892 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 893 { 894 switch (tp->mac_version) { 895 case RTL_GIGA_MAC_VER_40: 896 case RTL_GIGA_MAC_VER_41: 897 case RTL_GIGA_MAC_VER_49: 898 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 899 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 900 else 901 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 902 break; 903 default: 904 break; 905 } 906 }; 907 908 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 909 { 910 if (reg == 0x1f) { 911 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 912 return; 913 } 914 915 if (tp->ocp_base != OCP_STD_PHY_BASE) 916 reg -= 0x10; 917 918 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 919 rtl8168g_phy_suspend_quirk(tp, value); 920 921 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 922 } 923 924 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 925 { 926 if (reg == 0x1f) 927 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 928 929 if (tp->ocp_base != OCP_STD_PHY_BASE) 930 reg -= 0x10; 931 932 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 933 } 934 935 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 936 { 937 if (reg == 0x1f) { 938 tp->ocp_base = value << 4; 939 return; 940 } 941 942 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 943 } 944 945 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 946 { 947 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 948 } 949 950 DECLARE_RTL_COND(rtl_phyar_cond) 951 { 952 return RTL_R32(tp, PHYAR) & 0x80000000; 953 } 954 955 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 956 { 957 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 958 959 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 960 /* 961 * According to hardware specs a 20us delay is required after write 962 * complete indication, but before sending next command. 963 */ 964 udelay(20); 965 } 966 967 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 968 { 969 int value; 970 971 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 972 973 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 974 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 975 976 /* 977 * According to hardware specs a 20us delay is required after read 978 * complete indication, but before sending next command. 979 */ 980 udelay(20); 981 982 return value; 983 } 984 985 DECLARE_RTL_COND(rtl_ocpar_cond) 986 { 987 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 988 } 989 990 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 991 { 992 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 993 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 994 RTL_W32(tp, EPHY_RXER_NUM, 0); 995 996 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 997 } 998 999 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 1000 { 1001 r8168dp_1_mdio_access(tp, reg, 1002 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 1003 } 1004 1005 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 1006 { 1007 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 1008 1009 mdelay(1); 1010 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1011 RTL_W32(tp, EPHY_RXER_NUM, 0); 1012 1013 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1014 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1015 } 1016 1017 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1018 1019 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1020 { 1021 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1022 } 1023 1024 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1025 { 1026 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1027 } 1028 1029 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1030 { 1031 r8168dp_2_mdio_start(tp); 1032 1033 r8169_mdio_write(tp, reg, value); 1034 1035 r8168dp_2_mdio_stop(tp); 1036 } 1037 1038 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1039 { 1040 int value; 1041 1042 /* Work around issue with chip reporting wrong PHY ID */ 1043 if (reg == MII_PHYSID2) 1044 return 0xc912; 1045 1046 r8168dp_2_mdio_start(tp); 1047 1048 value = r8169_mdio_read(tp, reg); 1049 1050 r8168dp_2_mdio_stop(tp); 1051 1052 return value; 1053 } 1054 1055 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1056 { 1057 switch (tp->mac_version) { 1058 case RTL_GIGA_MAC_VER_27: 1059 r8168dp_1_mdio_write(tp, location, val); 1060 break; 1061 case RTL_GIGA_MAC_VER_28: 1062 case RTL_GIGA_MAC_VER_31: 1063 r8168dp_2_mdio_write(tp, location, val); 1064 break; 1065 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1066 r8168g_mdio_write(tp, location, val); 1067 break; 1068 default: 1069 r8169_mdio_write(tp, location, val); 1070 break; 1071 } 1072 } 1073 1074 static int rtl_readphy(struct rtl8169_private *tp, int location) 1075 { 1076 switch (tp->mac_version) { 1077 case RTL_GIGA_MAC_VER_27: 1078 return r8168dp_1_mdio_read(tp, location); 1079 case RTL_GIGA_MAC_VER_28: 1080 case RTL_GIGA_MAC_VER_31: 1081 return r8168dp_2_mdio_read(tp, location); 1082 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1083 return r8168g_mdio_read(tp, location); 1084 default: 1085 return r8169_mdio_read(tp, location); 1086 } 1087 } 1088 1089 DECLARE_RTL_COND(rtl_ephyar_cond) 1090 { 1091 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1092 } 1093 1094 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1095 { 1096 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1097 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1098 1099 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1100 1101 udelay(10); 1102 } 1103 1104 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1105 { 1106 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1107 1108 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1109 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1110 } 1111 1112 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1113 { 1114 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1115 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1116 RTL_R32(tp, OCPDR) : ~0; 1117 } 1118 1119 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1120 { 1121 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1122 } 1123 1124 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1125 u32 data) 1126 { 1127 RTL_W32(tp, OCPDR, data); 1128 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1129 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1130 } 1131 1132 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1133 u32 data) 1134 { 1135 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1136 data, ERIAR_OOB); 1137 } 1138 1139 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1140 { 1141 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1142 1143 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1144 } 1145 1146 #define OOB_CMD_RESET 0x00 1147 #define OOB_CMD_DRIVER_START 0x05 1148 #define OOB_CMD_DRIVER_STOP 0x06 1149 1150 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1151 { 1152 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1153 } 1154 1155 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1156 { 1157 u16 reg; 1158 1159 reg = rtl8168_get_ocp_reg(tp); 1160 1161 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1162 } 1163 1164 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1165 { 1166 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1167 } 1168 1169 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1170 { 1171 return RTL_R8(tp, IBISR0) & 0x20; 1172 } 1173 1174 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1175 { 1176 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1177 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1178 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1179 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1180 } 1181 1182 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1183 { 1184 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1185 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1186 } 1187 1188 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1189 { 1190 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1191 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1192 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1193 } 1194 1195 static void rtl8168_driver_start(struct rtl8169_private *tp) 1196 { 1197 if (tp->dash_type == RTL_DASH_DP) 1198 rtl8168dp_driver_start(tp); 1199 else 1200 rtl8168ep_driver_start(tp); 1201 } 1202 1203 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1204 { 1205 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1206 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1207 } 1208 1209 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1210 { 1211 rtl8168ep_stop_cmac(tp); 1212 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1213 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1214 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1215 } 1216 1217 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1218 { 1219 if (tp->dash_type == RTL_DASH_DP) 1220 rtl8168dp_driver_stop(tp); 1221 else 1222 rtl8168ep_driver_stop(tp); 1223 } 1224 1225 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1226 { 1227 u16 reg = rtl8168_get_ocp_reg(tp); 1228 1229 return r8168dp_ocp_read(tp, reg) & BIT(15); 1230 } 1231 1232 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1233 { 1234 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1235 } 1236 1237 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1238 { 1239 switch (tp->mac_version) { 1240 case RTL_GIGA_MAC_VER_27: 1241 case RTL_GIGA_MAC_VER_28: 1242 case RTL_GIGA_MAC_VER_31: 1243 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1244 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 1245 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1246 default: 1247 return RTL_DASH_NONE; 1248 } 1249 } 1250 1251 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1252 { 1253 switch (tp->mac_version) { 1254 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1255 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1256 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1257 if (enable) 1258 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1259 else 1260 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1261 break; 1262 default: 1263 break; 1264 } 1265 } 1266 1267 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1268 { 1269 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1270 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1271 } 1272 1273 DECLARE_RTL_COND(rtl_efusear_cond) 1274 { 1275 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1276 } 1277 1278 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1279 { 1280 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1281 1282 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1283 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1284 } 1285 1286 static u32 rtl_get_events(struct rtl8169_private *tp) 1287 { 1288 if (rtl_is_8125(tp)) 1289 return RTL_R32(tp, IntrStatus_8125); 1290 else 1291 return RTL_R16(tp, IntrStatus); 1292 } 1293 1294 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1295 { 1296 if (rtl_is_8125(tp)) 1297 RTL_W32(tp, IntrStatus_8125, bits); 1298 else 1299 RTL_W16(tp, IntrStatus, bits); 1300 } 1301 1302 static void rtl_irq_disable(struct rtl8169_private *tp) 1303 { 1304 if (rtl_is_8125(tp)) 1305 RTL_W32(tp, IntrMask_8125, 0); 1306 else 1307 RTL_W16(tp, IntrMask, 0); 1308 } 1309 1310 static void rtl_irq_enable(struct rtl8169_private *tp) 1311 { 1312 if (rtl_is_8125(tp)) 1313 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1314 else 1315 RTL_W16(tp, IntrMask, tp->irq_mask); 1316 } 1317 1318 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1319 { 1320 rtl_irq_disable(tp); 1321 rtl_ack_events(tp, 0xffffffff); 1322 rtl_pci_commit(tp); 1323 } 1324 1325 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1326 { 1327 struct phy_device *phydev = tp->phydev; 1328 1329 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1330 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1331 if (phydev->speed == SPEED_1000) { 1332 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1333 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1334 } else if (phydev->speed == SPEED_100) { 1335 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1336 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1337 } else { 1338 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1339 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1340 } 1341 rtl_reset_packet_filter(tp); 1342 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1343 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1344 if (phydev->speed == SPEED_1000) { 1345 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1346 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1347 } else { 1348 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1349 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1350 } 1351 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1352 if (phydev->speed == SPEED_10) { 1353 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1354 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1355 } else { 1356 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1357 } 1358 } 1359 } 1360 1361 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1362 1363 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1364 { 1365 struct rtl8169_private *tp = netdev_priv(dev); 1366 1367 wol->supported = WAKE_ANY; 1368 wol->wolopts = tp->saved_wolopts; 1369 } 1370 1371 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1372 { 1373 static const struct { 1374 u32 opt; 1375 u16 reg; 1376 u8 mask; 1377 } cfg[] = { 1378 { WAKE_PHY, Config3, LinkUp }, 1379 { WAKE_UCAST, Config5, UWF }, 1380 { WAKE_BCAST, Config5, BWF }, 1381 { WAKE_MCAST, Config5, MWF }, 1382 { WAKE_ANY, Config5, LanWake }, 1383 { WAKE_MAGIC, Config3, MagicPacket } 1384 }; 1385 unsigned int i, tmp = ARRAY_SIZE(cfg); 1386 u8 options; 1387 1388 rtl_unlock_config_regs(tp); 1389 1390 if (rtl_is_8168evl_up(tp)) { 1391 tmp--; 1392 if (wolopts & WAKE_MAGIC) 1393 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1394 else 1395 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1396 } else if (rtl_is_8125(tp)) { 1397 tmp--; 1398 if (wolopts & WAKE_MAGIC) 1399 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1400 else 1401 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1402 } 1403 1404 for (i = 0; i < tmp; i++) { 1405 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1406 if (wolopts & cfg[i].opt) 1407 options |= cfg[i].mask; 1408 RTL_W8(tp, cfg[i].reg, options); 1409 } 1410 1411 switch (tp->mac_version) { 1412 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1413 options = RTL_R8(tp, Config1) & ~PMEnable; 1414 if (wolopts) 1415 options |= PMEnable; 1416 RTL_W8(tp, Config1, options); 1417 break; 1418 case RTL_GIGA_MAC_VER_34: 1419 case RTL_GIGA_MAC_VER_37: 1420 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1421 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1422 if (wolopts) 1423 options |= PME_SIGNAL; 1424 RTL_W8(tp, Config2, options); 1425 break; 1426 default: 1427 break; 1428 } 1429 1430 rtl_lock_config_regs(tp); 1431 1432 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1433 rtl_set_d3_pll_down(tp, !wolopts); 1434 tp->dev->wol_enabled = wolopts ? 1 : 0; 1435 } 1436 1437 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1438 { 1439 struct rtl8169_private *tp = netdev_priv(dev); 1440 1441 if (wol->wolopts & ~WAKE_ANY) 1442 return -EINVAL; 1443 1444 tp->saved_wolopts = wol->wolopts; 1445 __rtl8169_set_wol(tp, tp->saved_wolopts); 1446 1447 return 0; 1448 } 1449 1450 static void rtl8169_get_drvinfo(struct net_device *dev, 1451 struct ethtool_drvinfo *info) 1452 { 1453 struct rtl8169_private *tp = netdev_priv(dev); 1454 struct rtl_fw *rtl_fw = tp->rtl_fw; 1455 1456 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1457 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1458 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1459 if (rtl_fw) 1460 strlcpy(info->fw_version, rtl_fw->version, 1461 sizeof(info->fw_version)); 1462 } 1463 1464 static int rtl8169_get_regs_len(struct net_device *dev) 1465 { 1466 return R8169_REGS_SIZE; 1467 } 1468 1469 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1470 netdev_features_t features) 1471 { 1472 struct rtl8169_private *tp = netdev_priv(dev); 1473 1474 if (dev->mtu > TD_MSS_MAX) 1475 features &= ~NETIF_F_ALL_TSO; 1476 1477 if (dev->mtu > ETH_DATA_LEN && 1478 tp->mac_version > RTL_GIGA_MAC_VER_06) 1479 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1480 1481 return features; 1482 } 1483 1484 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1485 netdev_features_t features) 1486 { 1487 u32 rx_config = RTL_R32(tp, RxConfig); 1488 1489 if (features & NETIF_F_RXALL) 1490 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1491 else 1492 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1493 1494 if (rtl_is_8125(tp)) { 1495 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1496 rx_config |= RX_VLAN_8125; 1497 else 1498 rx_config &= ~RX_VLAN_8125; 1499 } 1500 1501 RTL_W32(tp, RxConfig, rx_config); 1502 } 1503 1504 static int rtl8169_set_features(struct net_device *dev, 1505 netdev_features_t features) 1506 { 1507 struct rtl8169_private *tp = netdev_priv(dev); 1508 1509 rtl_set_rx_config_features(tp, features); 1510 1511 if (features & NETIF_F_RXCSUM) 1512 tp->cp_cmd |= RxChkSum; 1513 else 1514 tp->cp_cmd &= ~RxChkSum; 1515 1516 if (!rtl_is_8125(tp)) { 1517 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1518 tp->cp_cmd |= RxVlan; 1519 else 1520 tp->cp_cmd &= ~RxVlan; 1521 } 1522 1523 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1524 rtl_pci_commit(tp); 1525 1526 return 0; 1527 } 1528 1529 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1530 { 1531 return (skb_vlan_tag_present(skb)) ? 1532 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1533 } 1534 1535 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1536 { 1537 u32 opts2 = le32_to_cpu(desc->opts2); 1538 1539 if (opts2 & RxVlanTag) 1540 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1541 } 1542 1543 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1544 void *p) 1545 { 1546 struct rtl8169_private *tp = netdev_priv(dev); 1547 u32 __iomem *data = tp->mmio_addr; 1548 u32 *dw = p; 1549 int i; 1550 1551 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1552 memcpy_fromio(dw++, data++, 4); 1553 } 1554 1555 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1556 "tx_packets", 1557 "rx_packets", 1558 "tx_errors", 1559 "rx_errors", 1560 "rx_missed", 1561 "align_errors", 1562 "tx_single_collisions", 1563 "tx_multi_collisions", 1564 "unicast", 1565 "broadcast", 1566 "multicast", 1567 "tx_aborted", 1568 "tx_underrun", 1569 }; 1570 1571 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1572 { 1573 switch (sset) { 1574 case ETH_SS_STATS: 1575 return ARRAY_SIZE(rtl8169_gstrings); 1576 default: 1577 return -EOPNOTSUPP; 1578 } 1579 } 1580 1581 DECLARE_RTL_COND(rtl_counters_cond) 1582 { 1583 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1584 } 1585 1586 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1587 { 1588 dma_addr_t paddr = tp->counters_phys_addr; 1589 u32 cmd; 1590 1591 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1592 rtl_pci_commit(tp); 1593 cmd = (u64)paddr & DMA_BIT_MASK(32); 1594 RTL_W32(tp, CounterAddrLow, cmd); 1595 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1596 1597 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1598 } 1599 1600 static void rtl8169_update_counters(struct rtl8169_private *tp) 1601 { 1602 u8 val = RTL_R8(tp, ChipCmd); 1603 1604 /* 1605 * Some chips are unable to dump tally counters when the receiver 1606 * is disabled. If 0xff chip may be in a PCI power-save state. 1607 */ 1608 if (val & CmdRxEnb && val != 0xff) 1609 rtl8169_do_counters(tp, CounterDump); 1610 } 1611 1612 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1613 { 1614 struct rtl8169_counters *counters = tp->counters; 1615 1616 /* 1617 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1618 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1619 * reset by a power cycle, while the counter values collected by the 1620 * driver are reset at every driver unload/load cycle. 1621 * 1622 * To make sure the HW values returned by @get_stats64 match the SW 1623 * values, we collect the initial values at first open(*) and use them 1624 * as offsets to normalize the values returned by @get_stats64. 1625 * 1626 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1627 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1628 * set at open time by rtl_hw_start. 1629 */ 1630 1631 if (tp->tc_offset.inited) 1632 return; 1633 1634 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1635 rtl8169_do_counters(tp, CounterReset); 1636 } else { 1637 rtl8169_update_counters(tp); 1638 tp->tc_offset.tx_errors = counters->tx_errors; 1639 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1640 tp->tc_offset.tx_aborted = counters->tx_aborted; 1641 tp->tc_offset.rx_missed = counters->rx_missed; 1642 } 1643 1644 tp->tc_offset.inited = true; 1645 } 1646 1647 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1648 struct ethtool_stats *stats, u64 *data) 1649 { 1650 struct rtl8169_private *tp = netdev_priv(dev); 1651 struct rtl8169_counters *counters; 1652 1653 counters = tp->counters; 1654 rtl8169_update_counters(tp); 1655 1656 data[0] = le64_to_cpu(counters->tx_packets); 1657 data[1] = le64_to_cpu(counters->rx_packets); 1658 data[2] = le64_to_cpu(counters->tx_errors); 1659 data[3] = le32_to_cpu(counters->rx_errors); 1660 data[4] = le16_to_cpu(counters->rx_missed); 1661 data[5] = le16_to_cpu(counters->align_errors); 1662 data[6] = le32_to_cpu(counters->tx_one_collision); 1663 data[7] = le32_to_cpu(counters->tx_multi_collision); 1664 data[8] = le64_to_cpu(counters->rx_unicast); 1665 data[9] = le64_to_cpu(counters->rx_broadcast); 1666 data[10] = le32_to_cpu(counters->rx_multicast); 1667 data[11] = le16_to_cpu(counters->tx_aborted); 1668 data[12] = le16_to_cpu(counters->tx_underun); 1669 } 1670 1671 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1672 { 1673 switch(stringset) { 1674 case ETH_SS_STATS: 1675 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1676 break; 1677 } 1678 } 1679 1680 /* 1681 * Interrupt coalescing 1682 * 1683 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1684 * > 8169, 8168 and 810x line of chipsets 1685 * 1686 * 8169, 8168, and 8136(810x) serial chipsets support it. 1687 * 1688 * > 2 - the Tx timer unit at gigabit speed 1689 * 1690 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1691 * (0xe0) bit 1 and bit 0. 1692 * 1693 * For 8169 1694 * bit[1:0] \ speed 1000M 100M 10M 1695 * 0 0 320ns 2.56us 40.96us 1696 * 0 1 2.56us 20.48us 327.7us 1697 * 1 0 5.12us 40.96us 655.4us 1698 * 1 1 10.24us 81.92us 1.31ms 1699 * 1700 * For the other 1701 * bit[1:0] \ speed 1000M 100M 10M 1702 * 0 0 5us 2.56us 40.96us 1703 * 0 1 40us 20.48us 327.7us 1704 * 1 0 80us 40.96us 655.4us 1705 * 1 1 160us 81.92us 1.31ms 1706 */ 1707 1708 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1709 struct rtl_coalesce_info { 1710 u32 speed; 1711 u32 scale_nsecs[4]; 1712 }; 1713 1714 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1715 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1716 1717 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1718 { SPEED_1000, COALESCE_DELAY(320) }, 1719 { SPEED_100, COALESCE_DELAY(2560) }, 1720 { SPEED_10, COALESCE_DELAY(40960) }, 1721 { 0 }, 1722 }; 1723 1724 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1725 { SPEED_1000, COALESCE_DELAY(5000) }, 1726 { SPEED_100, COALESCE_DELAY(2560) }, 1727 { SPEED_10, COALESCE_DELAY(40960) }, 1728 { 0 }, 1729 }; 1730 #undef COALESCE_DELAY 1731 1732 /* get rx/tx scale vector corresponding to current speed */ 1733 static const struct rtl_coalesce_info * 1734 rtl_coalesce_info(struct rtl8169_private *tp) 1735 { 1736 const struct rtl_coalesce_info *ci; 1737 1738 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1739 ci = rtl_coalesce_info_8169; 1740 else 1741 ci = rtl_coalesce_info_8168_8136; 1742 1743 /* if speed is unknown assume highest one */ 1744 if (tp->phydev->speed == SPEED_UNKNOWN) 1745 return ci; 1746 1747 for (; ci->speed; ci++) { 1748 if (tp->phydev->speed == ci->speed) 1749 return ci; 1750 } 1751 1752 return ERR_PTR(-ELNRNG); 1753 } 1754 1755 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1756 { 1757 struct rtl8169_private *tp = netdev_priv(dev); 1758 const struct rtl_coalesce_info *ci; 1759 u32 scale, c_us, c_fr; 1760 u16 intrmit; 1761 1762 if (rtl_is_8125(tp)) 1763 return -EOPNOTSUPP; 1764 1765 memset(ec, 0, sizeof(*ec)); 1766 1767 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1768 ci = rtl_coalesce_info(tp); 1769 if (IS_ERR(ci)) 1770 return PTR_ERR(ci); 1771 1772 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1773 1774 intrmit = RTL_R16(tp, IntrMitigate); 1775 1776 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1777 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1778 1779 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1780 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1781 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1782 1783 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1784 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1785 1786 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1787 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1788 1789 return 0; 1790 } 1791 1792 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1793 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1794 u16 *cp01) 1795 { 1796 const struct rtl_coalesce_info *ci; 1797 u16 i; 1798 1799 ci = rtl_coalesce_info(tp); 1800 if (IS_ERR(ci)) 1801 return PTR_ERR(ci); 1802 1803 for (i = 0; i < 4; i++) { 1804 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1805 *cp01 = i; 1806 return ci->scale_nsecs[i]; 1807 } 1808 } 1809 1810 return -ERANGE; 1811 } 1812 1813 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1814 { 1815 struct rtl8169_private *tp = netdev_priv(dev); 1816 u32 tx_fr = ec->tx_max_coalesced_frames; 1817 u32 rx_fr = ec->rx_max_coalesced_frames; 1818 u32 coal_usec_max, units; 1819 u16 w = 0, cp01 = 0; 1820 int scale; 1821 1822 if (rtl_is_8125(tp)) 1823 return -EOPNOTSUPP; 1824 1825 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1826 return -ERANGE; 1827 1828 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1829 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1830 if (scale < 0) 1831 return scale; 1832 1833 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1834 * not only when usecs=0 because of e.g. the following scenario: 1835 * 1836 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1837 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1838 * - then user does `ethtool -C eth0 rx-usecs 100` 1839 * 1840 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1841 * if we want to ignore rx_frames then it has to be set to 0. 1842 */ 1843 if (rx_fr == 1) 1844 rx_fr = 0; 1845 if (tx_fr == 1) 1846 tx_fr = 0; 1847 1848 /* HW requires time limit to be set if frame limit is set */ 1849 if ((tx_fr && !ec->tx_coalesce_usecs) || 1850 (rx_fr && !ec->rx_coalesce_usecs)) 1851 return -EINVAL; 1852 1853 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1854 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1855 1856 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1857 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1858 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1859 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1860 1861 RTL_W16(tp, IntrMitigate, w); 1862 1863 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1864 if (rtl_is_8168evl_up(tp)) { 1865 if (!rx_fr && !tx_fr) 1866 /* disable packet counter */ 1867 tp->cp_cmd |= PktCntrDisable; 1868 else 1869 tp->cp_cmd &= ~PktCntrDisable; 1870 } 1871 1872 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1873 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1874 rtl_pci_commit(tp); 1875 1876 return 0; 1877 } 1878 1879 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1880 { 1881 struct rtl8169_private *tp = netdev_priv(dev); 1882 1883 if (!rtl_supports_eee(tp)) 1884 return -EOPNOTSUPP; 1885 1886 return phy_ethtool_get_eee(tp->phydev, data); 1887 } 1888 1889 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1890 { 1891 struct rtl8169_private *tp = netdev_priv(dev); 1892 int ret; 1893 1894 if (!rtl_supports_eee(tp)) 1895 return -EOPNOTSUPP; 1896 1897 ret = phy_ethtool_set_eee(tp->phydev, data); 1898 1899 if (!ret) 1900 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1901 MDIO_AN_EEE_ADV); 1902 return ret; 1903 } 1904 1905 static const struct ethtool_ops rtl8169_ethtool_ops = { 1906 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1907 ETHTOOL_COALESCE_MAX_FRAMES, 1908 .get_drvinfo = rtl8169_get_drvinfo, 1909 .get_regs_len = rtl8169_get_regs_len, 1910 .get_link = ethtool_op_get_link, 1911 .get_coalesce = rtl_get_coalesce, 1912 .set_coalesce = rtl_set_coalesce, 1913 .get_regs = rtl8169_get_regs, 1914 .get_wol = rtl8169_get_wol, 1915 .set_wol = rtl8169_set_wol, 1916 .get_strings = rtl8169_get_strings, 1917 .get_sset_count = rtl8169_get_sset_count, 1918 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1919 .get_ts_info = ethtool_op_get_ts_info, 1920 .nway_reset = phy_ethtool_nway_reset, 1921 .get_eee = rtl8169_get_eee, 1922 .set_eee = rtl8169_set_eee, 1923 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1924 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1925 }; 1926 1927 static void rtl_enable_eee(struct rtl8169_private *tp) 1928 { 1929 struct phy_device *phydev = tp->phydev; 1930 int adv; 1931 1932 /* respect EEE advertisement the user may have set */ 1933 if (tp->eee_adv >= 0) 1934 adv = tp->eee_adv; 1935 else 1936 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1937 1938 if (adv >= 0) 1939 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1940 } 1941 1942 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1943 { 1944 /* 1945 * The driver currently handles the 8168Bf and the 8168Be identically 1946 * but they can be identified more specifically through the test below 1947 * if needed: 1948 * 1949 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1950 * 1951 * Same thing for the 8101Eb and the 8101Ec: 1952 * 1953 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1954 */ 1955 static const struct rtl_mac_info { 1956 u16 mask; 1957 u16 val; 1958 enum mac_version ver; 1959 } mac_info[] = { 1960 /* 8125B family. */ 1961 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1962 1963 /* 8125A family. */ 1964 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1965 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1966 1967 /* RTL8117 */ 1968 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 1969 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1970 1971 /* 8168EP family. */ 1972 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1973 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1974 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1975 1976 /* 8168H family. */ 1977 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1978 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1979 1980 /* 8168G family. */ 1981 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1982 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1983 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1984 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1985 1986 /* 8168F family. */ 1987 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 1988 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 1989 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 1990 1991 /* 8168E family. */ 1992 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 1993 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 1994 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 1995 1996 /* 8168D family. */ 1997 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 1998 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 1999 2000 /* 8168DP family. */ 2001 /* It seems this early RTL8168dp version never made it to 2002 * the wild. Let's see whether somebody complains, if not 2003 * we'll remove support for this chip version completely. 2004 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2005 */ 2006 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2007 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2008 2009 /* 8168C family. */ 2010 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2011 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2012 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2013 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2014 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2015 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2016 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2017 2018 /* 8168B family. */ 2019 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2020 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2021 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2022 2023 /* 8101 family. */ 2024 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2025 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2026 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2027 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2028 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2029 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2030 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2031 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2032 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2033 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2034 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2035 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2036 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2037 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2038 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2039 /* FIXME: where did these entries come from ? -- FR 2040 * Not even r8101 vendor driver knows these id's, 2041 * so let's disable detection for now. -- HK 2042 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2043 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2044 */ 2045 2046 /* 8110 family. */ 2047 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2048 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2049 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2050 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2051 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2052 2053 /* Catch-all */ 2054 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2055 }; 2056 const struct rtl_mac_info *p = mac_info; 2057 enum mac_version ver; 2058 2059 while ((xid & p->mask) != p->val) 2060 p++; 2061 ver = p->ver; 2062 2063 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2064 if (ver == RTL_GIGA_MAC_VER_42) 2065 ver = RTL_GIGA_MAC_VER_43; 2066 else if (ver == RTL_GIGA_MAC_VER_45) 2067 ver = RTL_GIGA_MAC_VER_47; 2068 else if (ver == RTL_GIGA_MAC_VER_46) 2069 ver = RTL_GIGA_MAC_VER_48; 2070 } 2071 2072 return ver; 2073 } 2074 2075 static void rtl_release_firmware(struct rtl8169_private *tp) 2076 { 2077 if (tp->rtl_fw) { 2078 rtl_fw_release_firmware(tp->rtl_fw); 2079 kfree(tp->rtl_fw); 2080 tp->rtl_fw = NULL; 2081 } 2082 } 2083 2084 void r8169_apply_firmware(struct rtl8169_private *tp) 2085 { 2086 int val; 2087 2088 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2089 if (tp->rtl_fw) { 2090 rtl_fw_write_firmware(tp, tp->rtl_fw); 2091 /* At least one firmware doesn't reset tp->ocp_base. */ 2092 tp->ocp_base = OCP_STD_PHY_BASE; 2093 2094 /* PHY soft reset may still be in progress */ 2095 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2096 !(val & BMCR_RESET), 2097 50000, 600000, true); 2098 } 2099 } 2100 2101 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2102 { 2103 /* Adjust EEE LED frequency */ 2104 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2105 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2106 2107 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2108 } 2109 2110 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2111 { 2112 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2113 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2114 } 2115 2116 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2117 { 2118 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2119 } 2120 2121 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2122 { 2123 rtl8125_set_eee_txidle_timer(tp); 2124 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2125 } 2126 2127 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2128 { 2129 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2130 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2131 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2132 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2133 } 2134 2135 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2136 { 2137 u16 data1, data2, ioffset; 2138 2139 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2140 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2141 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2142 2143 ioffset = (data2 >> 1) & 0x7ff8; 2144 ioffset |= data2 & 0x0007; 2145 if (data1 & BIT(7)) 2146 ioffset |= BIT(15); 2147 2148 return ioffset; 2149 } 2150 2151 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2152 { 2153 set_bit(flag, tp->wk.flags); 2154 schedule_work(&tp->wk.work); 2155 } 2156 2157 static void rtl8169_init_phy(struct rtl8169_private *tp) 2158 { 2159 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2160 2161 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2162 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2163 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2164 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2165 RTL_W8(tp, 0x82, 0x01); 2166 } 2167 2168 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2169 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2170 tp->pci_dev->subsystem_device == 0xe000) 2171 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2172 2173 /* We may have called phy_speed_down before */ 2174 phy_speed_up(tp->phydev); 2175 2176 if (rtl_supports_eee(tp)) 2177 rtl_enable_eee(tp); 2178 2179 genphy_soft_reset(tp->phydev); 2180 } 2181 2182 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2183 { 2184 rtl_unlock_config_regs(tp); 2185 2186 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2187 rtl_pci_commit(tp); 2188 2189 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2190 rtl_pci_commit(tp); 2191 2192 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2193 rtl_rar_exgmac_set(tp, addr); 2194 2195 rtl_lock_config_regs(tp); 2196 } 2197 2198 static int rtl_set_mac_address(struct net_device *dev, void *p) 2199 { 2200 struct rtl8169_private *tp = netdev_priv(dev); 2201 int ret; 2202 2203 ret = eth_mac_addr(dev, p); 2204 if (ret) 2205 return ret; 2206 2207 rtl_rar_set(tp, dev->dev_addr); 2208 2209 return 0; 2210 } 2211 2212 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2213 { 2214 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2215 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2216 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2217 } 2218 2219 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2220 { 2221 if (tp->dash_type != RTL_DASH_NONE) 2222 return; 2223 2224 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2225 tp->mac_version == RTL_GIGA_MAC_VER_33) 2226 rtl_ephy_write(tp, 0x19, 0xff64); 2227 2228 if (device_may_wakeup(tp_to_dev(tp))) { 2229 phy_speed_down(tp->phydev, false); 2230 rtl_wol_enable_rx(tp); 2231 } 2232 } 2233 2234 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2235 { 2236 switch (tp->mac_version) { 2237 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2238 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2239 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2240 break; 2241 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2242 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2243 case RTL_GIGA_MAC_VER_38: 2244 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2245 break; 2246 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2247 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2248 break; 2249 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2250 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2251 break; 2252 default: 2253 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2254 break; 2255 } 2256 } 2257 2258 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2259 { 2260 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2261 } 2262 2263 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2264 { 2265 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2266 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2267 } 2268 2269 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2270 { 2271 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2272 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2273 } 2274 2275 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2276 { 2277 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2278 } 2279 2280 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2281 { 2282 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2283 } 2284 2285 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2286 { 2287 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2288 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2289 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2290 } 2291 2292 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2293 { 2294 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2295 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2296 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2297 } 2298 2299 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2300 { 2301 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2302 } 2303 2304 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2305 { 2306 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2307 } 2308 2309 static void rtl_jumbo_config(struct rtl8169_private *tp) 2310 { 2311 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2312 int readrq = 4096; 2313 2314 rtl_unlock_config_regs(tp); 2315 switch (tp->mac_version) { 2316 case RTL_GIGA_MAC_VER_12: 2317 case RTL_GIGA_MAC_VER_17: 2318 if (jumbo) { 2319 readrq = 512; 2320 r8168b_1_hw_jumbo_enable(tp); 2321 } else { 2322 r8168b_1_hw_jumbo_disable(tp); 2323 } 2324 break; 2325 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2326 if (jumbo) { 2327 readrq = 512; 2328 r8168c_hw_jumbo_enable(tp); 2329 } else { 2330 r8168c_hw_jumbo_disable(tp); 2331 } 2332 break; 2333 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2334 if (jumbo) 2335 r8168dp_hw_jumbo_enable(tp); 2336 else 2337 r8168dp_hw_jumbo_disable(tp); 2338 break; 2339 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2340 if (jumbo) 2341 r8168e_hw_jumbo_enable(tp); 2342 else 2343 r8168e_hw_jumbo_disable(tp); 2344 break; 2345 default: 2346 break; 2347 } 2348 rtl_lock_config_regs(tp); 2349 2350 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2351 pcie_set_readrq(tp->pci_dev, readrq); 2352 } 2353 2354 DECLARE_RTL_COND(rtl_chipcmd_cond) 2355 { 2356 return RTL_R8(tp, ChipCmd) & CmdReset; 2357 } 2358 2359 static void rtl_hw_reset(struct rtl8169_private *tp) 2360 { 2361 RTL_W8(tp, ChipCmd, CmdReset); 2362 2363 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2364 } 2365 2366 static void rtl_request_firmware(struct rtl8169_private *tp) 2367 { 2368 struct rtl_fw *rtl_fw; 2369 2370 /* firmware loaded already or no firmware available */ 2371 if (tp->rtl_fw || !tp->fw_name) 2372 return; 2373 2374 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2375 if (!rtl_fw) 2376 return; 2377 2378 rtl_fw->phy_write = rtl_writephy; 2379 rtl_fw->phy_read = rtl_readphy; 2380 rtl_fw->mac_mcu_write = mac_mcu_write; 2381 rtl_fw->mac_mcu_read = mac_mcu_read; 2382 rtl_fw->fw_name = tp->fw_name; 2383 rtl_fw->dev = tp_to_dev(tp); 2384 2385 if (rtl_fw_request_firmware(rtl_fw)) 2386 kfree(rtl_fw); 2387 else 2388 tp->rtl_fw = rtl_fw; 2389 } 2390 2391 static void rtl_rx_close(struct rtl8169_private *tp) 2392 { 2393 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2394 } 2395 2396 DECLARE_RTL_COND(rtl_npq_cond) 2397 { 2398 return RTL_R8(tp, TxPoll) & NPQ; 2399 } 2400 2401 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2402 { 2403 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2404 } 2405 2406 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2407 { 2408 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2409 } 2410 2411 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2412 { 2413 /* IntrMitigate has new functionality on RTL8125 */ 2414 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2415 } 2416 2417 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2418 { 2419 switch (tp->mac_version) { 2420 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2421 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2422 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2423 break; 2424 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2425 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2426 break; 2427 case RTL_GIGA_MAC_VER_63: 2428 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2429 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2430 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2431 break; 2432 default: 2433 break; 2434 } 2435 } 2436 2437 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2438 { 2439 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2440 fsleep(2000); 2441 rtl_wait_txrx_fifo_empty(tp); 2442 } 2443 2444 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2445 { 2446 u32 val = TX_DMA_BURST << TxDMAShift | 2447 InterFrameGap << TxInterFrameGapShift; 2448 2449 if (rtl_is_8168evl_up(tp)) 2450 val |= TXCFG_AUTO_FIFO; 2451 2452 RTL_W32(tp, TxConfig, val); 2453 } 2454 2455 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2456 { 2457 /* Low hurts. Let's disable the filtering. */ 2458 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2459 } 2460 2461 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2462 { 2463 /* 2464 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2465 * register to be written before TxDescAddrLow to work. 2466 * Switching from MMIO to I/O access fixes the issue as well. 2467 */ 2468 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2469 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2470 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2471 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2472 } 2473 2474 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2475 { 2476 u32 val; 2477 2478 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2479 val = 0x000fff00; 2480 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2481 val = 0x00ffff00; 2482 else 2483 return; 2484 2485 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2486 val |= 0xff; 2487 2488 RTL_W32(tp, 0x7c, val); 2489 } 2490 2491 static void rtl_set_rx_mode(struct net_device *dev) 2492 { 2493 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2494 /* Multicast hash filter */ 2495 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2496 struct rtl8169_private *tp = netdev_priv(dev); 2497 u32 tmp; 2498 2499 if (dev->flags & IFF_PROMISC) { 2500 rx_mode |= AcceptAllPhys; 2501 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2502 dev->flags & IFF_ALLMULTI || 2503 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2504 /* accept all multicasts */ 2505 } else if (netdev_mc_empty(dev)) { 2506 rx_mode &= ~AcceptMulticast; 2507 } else { 2508 struct netdev_hw_addr *ha; 2509 2510 mc_filter[1] = mc_filter[0] = 0; 2511 netdev_for_each_mc_addr(ha, dev) { 2512 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2513 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2514 } 2515 2516 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2517 tmp = mc_filter[0]; 2518 mc_filter[0] = swab32(mc_filter[1]); 2519 mc_filter[1] = swab32(tmp); 2520 } 2521 } 2522 2523 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2524 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2525 2526 tmp = RTL_R32(tp, RxConfig); 2527 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2528 } 2529 2530 DECLARE_RTL_COND(rtl_csiar_cond) 2531 { 2532 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2533 } 2534 2535 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2536 { 2537 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2538 2539 RTL_W32(tp, CSIDR, value); 2540 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2541 CSIAR_BYTE_ENABLE | func << 16); 2542 2543 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2544 } 2545 2546 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2547 { 2548 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2549 2550 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2551 CSIAR_BYTE_ENABLE); 2552 2553 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2554 RTL_R32(tp, CSIDR) : ~0; 2555 } 2556 2557 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2558 { 2559 struct pci_dev *pdev = tp->pci_dev; 2560 u32 csi; 2561 2562 /* According to Realtek the value at config space address 0x070f 2563 * controls the L0s/L1 entrance latency. We try standard ECAM access 2564 * first and if it fails fall back to CSI. 2565 */ 2566 if (pdev->cfg_size > 0x070f && 2567 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2568 return; 2569 2570 netdev_notice_once(tp->dev, 2571 "No native access to PCI extended config space, falling back to CSI\n"); 2572 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2573 rtl_csi_write(tp, 0x070c, csi | val << 24); 2574 } 2575 2576 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2577 { 2578 rtl_csi_access_enable(tp, 0x27); 2579 } 2580 2581 struct ephy_info { 2582 unsigned int offset; 2583 u16 mask; 2584 u16 bits; 2585 }; 2586 2587 static void __rtl_ephy_init(struct rtl8169_private *tp, 2588 const struct ephy_info *e, int len) 2589 { 2590 u16 w; 2591 2592 while (len-- > 0) { 2593 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2594 rtl_ephy_write(tp, e->offset, w); 2595 e++; 2596 } 2597 } 2598 2599 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2600 2601 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2602 { 2603 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2604 PCI_EXP_LNKCTL_CLKREQ_EN); 2605 } 2606 2607 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2608 { 2609 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2610 PCI_EXP_LNKCTL_CLKREQ_EN); 2611 } 2612 2613 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2614 { 2615 /* work around an issue when PCI reset occurs during L2/L3 state */ 2616 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2617 } 2618 2619 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2620 { 2621 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2622 if (enable && tp->aspm_manageable) { 2623 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2624 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2625 } else { 2626 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2627 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2628 } 2629 2630 udelay(10); 2631 } 2632 2633 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2634 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2635 { 2636 /* Usage of dynamic vs. static FIFO is controlled by bit 2637 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2638 */ 2639 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2640 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2641 } 2642 2643 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2644 u8 low, u8 high) 2645 { 2646 /* FIFO thresholds for pause flow control */ 2647 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2648 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2649 } 2650 2651 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2652 { 2653 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2654 } 2655 2656 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2657 { 2658 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2659 2660 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2661 2662 rtl_disable_clock_request(tp); 2663 } 2664 2665 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2666 { 2667 static const struct ephy_info e_info_8168cp[] = { 2668 { 0x01, 0, 0x0001 }, 2669 { 0x02, 0x0800, 0x1000 }, 2670 { 0x03, 0, 0x0042 }, 2671 { 0x06, 0x0080, 0x0000 }, 2672 { 0x07, 0, 0x2000 } 2673 }; 2674 2675 rtl_set_def_aspm_entry_latency(tp); 2676 2677 rtl_ephy_init(tp, e_info_8168cp); 2678 2679 __rtl_hw_start_8168cp(tp); 2680 } 2681 2682 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2683 { 2684 rtl_set_def_aspm_entry_latency(tp); 2685 2686 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2687 } 2688 2689 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2690 { 2691 rtl_set_def_aspm_entry_latency(tp); 2692 2693 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2694 2695 /* Magic. */ 2696 RTL_W8(tp, DBG_REG, 0x20); 2697 } 2698 2699 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2700 { 2701 static const struct ephy_info e_info_8168c_1[] = { 2702 { 0x02, 0x0800, 0x1000 }, 2703 { 0x03, 0, 0x0002 }, 2704 { 0x06, 0x0080, 0x0000 } 2705 }; 2706 2707 rtl_set_def_aspm_entry_latency(tp); 2708 2709 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2710 2711 rtl_ephy_init(tp, e_info_8168c_1); 2712 2713 __rtl_hw_start_8168cp(tp); 2714 } 2715 2716 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2717 { 2718 static const struct ephy_info e_info_8168c_2[] = { 2719 { 0x01, 0, 0x0001 }, 2720 { 0x03, 0x0400, 0x0020 } 2721 }; 2722 2723 rtl_set_def_aspm_entry_latency(tp); 2724 2725 rtl_ephy_init(tp, e_info_8168c_2); 2726 2727 __rtl_hw_start_8168cp(tp); 2728 } 2729 2730 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2731 { 2732 rtl_hw_start_8168c_2(tp); 2733 } 2734 2735 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2736 { 2737 rtl_set_def_aspm_entry_latency(tp); 2738 2739 __rtl_hw_start_8168cp(tp); 2740 } 2741 2742 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2743 { 2744 rtl_set_def_aspm_entry_latency(tp); 2745 2746 rtl_disable_clock_request(tp); 2747 } 2748 2749 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2750 { 2751 static const struct ephy_info e_info_8168d_4[] = { 2752 { 0x0b, 0x0000, 0x0048 }, 2753 { 0x19, 0x0020, 0x0050 }, 2754 { 0x0c, 0x0100, 0x0020 }, 2755 { 0x10, 0x0004, 0x0000 }, 2756 }; 2757 2758 rtl_set_def_aspm_entry_latency(tp); 2759 2760 rtl_ephy_init(tp, e_info_8168d_4); 2761 2762 rtl_enable_clock_request(tp); 2763 } 2764 2765 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2766 { 2767 static const struct ephy_info e_info_8168e_1[] = { 2768 { 0x00, 0x0200, 0x0100 }, 2769 { 0x00, 0x0000, 0x0004 }, 2770 { 0x06, 0x0002, 0x0001 }, 2771 { 0x06, 0x0000, 0x0030 }, 2772 { 0x07, 0x0000, 0x2000 }, 2773 { 0x00, 0x0000, 0x0020 }, 2774 { 0x03, 0x5800, 0x2000 }, 2775 { 0x03, 0x0000, 0x0001 }, 2776 { 0x01, 0x0800, 0x1000 }, 2777 { 0x07, 0x0000, 0x4000 }, 2778 { 0x1e, 0x0000, 0x2000 }, 2779 { 0x19, 0xffff, 0xfe6c }, 2780 { 0x0a, 0x0000, 0x0040 } 2781 }; 2782 2783 rtl_set_def_aspm_entry_latency(tp); 2784 2785 rtl_ephy_init(tp, e_info_8168e_1); 2786 2787 rtl_disable_clock_request(tp); 2788 2789 /* Reset tx FIFO pointer */ 2790 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2791 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2792 2793 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2794 } 2795 2796 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2797 { 2798 static const struct ephy_info e_info_8168e_2[] = { 2799 { 0x09, 0x0000, 0x0080 }, 2800 { 0x19, 0x0000, 0x0224 }, 2801 { 0x00, 0x0000, 0x0004 }, 2802 { 0x0c, 0x3df0, 0x0200 }, 2803 }; 2804 2805 rtl_set_def_aspm_entry_latency(tp); 2806 2807 rtl_ephy_init(tp, e_info_8168e_2); 2808 2809 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2810 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2811 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2812 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2813 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2814 rtl_reset_packet_filter(tp); 2815 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2816 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2817 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2818 2819 rtl_disable_clock_request(tp); 2820 2821 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2822 2823 rtl8168_config_eee_mac(tp); 2824 2825 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2826 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2827 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2828 2829 rtl_hw_aspm_clkreq_enable(tp, true); 2830 } 2831 2832 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2833 { 2834 rtl_set_def_aspm_entry_latency(tp); 2835 2836 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2837 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2838 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2839 rtl_reset_packet_filter(tp); 2840 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2841 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2842 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2843 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2844 2845 rtl_disable_clock_request(tp); 2846 2847 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2848 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2849 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2850 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2851 2852 rtl8168_config_eee_mac(tp); 2853 } 2854 2855 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2856 { 2857 static const struct ephy_info e_info_8168f_1[] = { 2858 { 0x06, 0x00c0, 0x0020 }, 2859 { 0x08, 0x0001, 0x0002 }, 2860 { 0x09, 0x0000, 0x0080 }, 2861 { 0x19, 0x0000, 0x0224 }, 2862 { 0x00, 0x0000, 0x0008 }, 2863 { 0x0c, 0x3df0, 0x0200 }, 2864 }; 2865 2866 rtl_hw_start_8168f(tp); 2867 2868 rtl_ephy_init(tp, e_info_8168f_1); 2869 2870 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2871 } 2872 2873 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2874 { 2875 static const struct ephy_info e_info_8168f_1[] = { 2876 { 0x06, 0x00c0, 0x0020 }, 2877 { 0x0f, 0xffff, 0x5200 }, 2878 { 0x19, 0x0000, 0x0224 }, 2879 { 0x00, 0x0000, 0x0008 }, 2880 { 0x0c, 0x3df0, 0x0200 }, 2881 }; 2882 2883 rtl_hw_start_8168f(tp); 2884 rtl_pcie_state_l2l3_disable(tp); 2885 2886 rtl_ephy_init(tp, e_info_8168f_1); 2887 2888 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2889 } 2890 2891 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2892 { 2893 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2894 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2895 2896 rtl_set_def_aspm_entry_latency(tp); 2897 2898 rtl_reset_packet_filter(tp); 2899 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2900 2901 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2902 2903 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2904 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2905 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2906 2907 rtl8168_config_eee_mac(tp); 2908 2909 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2910 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2911 2912 rtl_pcie_state_l2l3_disable(tp); 2913 } 2914 2915 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2916 { 2917 static const struct ephy_info e_info_8168g_1[] = { 2918 { 0x00, 0x0008, 0x0000 }, 2919 { 0x0c, 0x3ff0, 0x0820 }, 2920 { 0x1e, 0x0000, 0x0001 }, 2921 { 0x19, 0x8000, 0x0000 } 2922 }; 2923 2924 rtl_hw_start_8168g(tp); 2925 2926 /* disable aspm and clock request before access ephy */ 2927 rtl_hw_aspm_clkreq_enable(tp, false); 2928 rtl_ephy_init(tp, e_info_8168g_1); 2929 rtl_hw_aspm_clkreq_enable(tp, true); 2930 } 2931 2932 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 2933 { 2934 static const struct ephy_info e_info_8168g_2[] = { 2935 { 0x00, 0x0008, 0x0000 }, 2936 { 0x0c, 0x3ff0, 0x0820 }, 2937 { 0x19, 0xffff, 0x7c00 }, 2938 { 0x1e, 0xffff, 0x20eb }, 2939 { 0x0d, 0xffff, 0x1666 }, 2940 { 0x00, 0xffff, 0x10a3 }, 2941 { 0x06, 0xffff, 0xf050 }, 2942 { 0x04, 0x0000, 0x0010 }, 2943 { 0x1d, 0x4000, 0x0000 }, 2944 }; 2945 2946 rtl_hw_start_8168g(tp); 2947 2948 /* disable aspm and clock request before access ephy */ 2949 rtl_hw_aspm_clkreq_enable(tp, false); 2950 rtl_ephy_init(tp, e_info_8168g_2); 2951 } 2952 2953 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 2954 { 2955 static const struct ephy_info e_info_8411_2[] = { 2956 { 0x00, 0x0008, 0x0000 }, 2957 { 0x0c, 0x37d0, 0x0820 }, 2958 { 0x1e, 0x0000, 0x0001 }, 2959 { 0x19, 0x8021, 0x0000 }, 2960 { 0x1e, 0x0000, 0x2000 }, 2961 { 0x0d, 0x0100, 0x0200 }, 2962 { 0x00, 0x0000, 0x0080 }, 2963 { 0x06, 0x0000, 0x0010 }, 2964 { 0x04, 0x0000, 0x0010 }, 2965 { 0x1d, 0x0000, 0x4000 }, 2966 }; 2967 2968 rtl_hw_start_8168g(tp); 2969 2970 /* disable aspm and clock request before access ephy */ 2971 rtl_hw_aspm_clkreq_enable(tp, false); 2972 rtl_ephy_init(tp, e_info_8411_2); 2973 2974 /* The following Realtek-provided magic fixes an issue with the RX unit 2975 * getting confused after the PHY having been powered-down. 2976 */ 2977 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 2978 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 2979 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 2980 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 2981 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 2982 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 2983 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 2984 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 2985 mdelay(3); 2986 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 2987 2988 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 2989 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 2990 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 2991 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 2992 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 2993 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 2994 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 2995 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 2996 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 2997 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 2998 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 2999 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3000 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3001 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3002 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3003 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3004 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3005 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3006 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3007 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3008 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3009 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3010 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3011 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3012 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3013 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3014 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3015 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3016 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3017 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3018 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3019 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3020 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3021 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3022 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3023 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3024 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3025 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3026 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3027 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3028 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3029 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3030 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3031 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3032 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3033 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3034 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3035 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3036 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3037 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3038 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3039 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3040 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3041 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3042 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3043 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3044 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3045 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3046 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3047 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3048 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3049 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3050 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3051 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3052 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3053 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3054 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3055 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3056 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3057 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3058 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3059 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3060 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3061 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3062 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3063 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3064 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3065 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3066 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3067 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3068 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3069 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3070 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3071 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3072 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3073 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3074 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3075 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3076 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3077 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3078 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3079 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3080 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3081 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3082 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3083 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3084 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3085 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3086 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3087 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3088 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3089 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3090 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3091 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3092 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3093 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3094 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3095 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3096 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3097 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3098 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3099 3100 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3101 3102 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3103 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3104 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3105 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3106 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3107 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3108 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3109 3110 rtl_hw_aspm_clkreq_enable(tp, true); 3111 } 3112 3113 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3114 { 3115 static const struct ephy_info e_info_8168h_1[] = { 3116 { 0x1e, 0x0800, 0x0001 }, 3117 { 0x1d, 0x0000, 0x0800 }, 3118 { 0x05, 0xffff, 0x2089 }, 3119 { 0x06, 0xffff, 0x5881 }, 3120 { 0x04, 0xffff, 0x854a }, 3121 { 0x01, 0xffff, 0x068b } 3122 }; 3123 int rg_saw_cnt; 3124 3125 /* disable aspm and clock request before access ephy */ 3126 rtl_hw_aspm_clkreq_enable(tp, false); 3127 rtl_ephy_init(tp, e_info_8168h_1); 3128 3129 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3130 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3131 3132 rtl_set_def_aspm_entry_latency(tp); 3133 3134 rtl_reset_packet_filter(tp); 3135 3136 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3137 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3138 3139 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3140 3141 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3142 3143 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3144 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3145 3146 rtl8168_config_eee_mac(tp); 3147 3148 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3149 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3150 3151 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3152 3153 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3154 3155 rtl_pcie_state_l2l3_disable(tp); 3156 3157 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3158 if (rg_saw_cnt > 0) { 3159 u16 sw_cnt_1ms_ini; 3160 3161 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3162 sw_cnt_1ms_ini &= 0x0fff; 3163 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3164 } 3165 3166 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3167 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3168 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3169 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3170 3171 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3172 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3173 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3174 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3175 3176 rtl_hw_aspm_clkreq_enable(tp, true); 3177 } 3178 3179 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3180 { 3181 rtl8168ep_stop_cmac(tp); 3182 3183 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3184 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3185 3186 rtl_set_def_aspm_entry_latency(tp); 3187 3188 rtl_reset_packet_filter(tp); 3189 3190 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3191 3192 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3193 3194 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3195 3196 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3197 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3198 3199 rtl8168_config_eee_mac(tp); 3200 3201 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3202 3203 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3204 3205 rtl_pcie_state_l2l3_disable(tp); 3206 } 3207 3208 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3209 { 3210 static const struct ephy_info e_info_8168ep_1[] = { 3211 { 0x00, 0xffff, 0x10ab }, 3212 { 0x06, 0xffff, 0xf030 }, 3213 { 0x08, 0xffff, 0x2006 }, 3214 { 0x0d, 0xffff, 0x1666 }, 3215 { 0x0c, 0x3ff0, 0x0000 } 3216 }; 3217 3218 /* disable aspm and clock request before access ephy */ 3219 rtl_hw_aspm_clkreq_enable(tp, false); 3220 rtl_ephy_init(tp, e_info_8168ep_1); 3221 3222 rtl_hw_start_8168ep(tp); 3223 3224 rtl_hw_aspm_clkreq_enable(tp, true); 3225 } 3226 3227 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3228 { 3229 static const struct ephy_info e_info_8168ep_2[] = { 3230 { 0x00, 0xffff, 0x10a3 }, 3231 { 0x19, 0xffff, 0xfc00 }, 3232 { 0x1e, 0xffff, 0x20ea } 3233 }; 3234 3235 /* disable aspm and clock request before access ephy */ 3236 rtl_hw_aspm_clkreq_enable(tp, false); 3237 rtl_ephy_init(tp, e_info_8168ep_2); 3238 3239 rtl_hw_start_8168ep(tp); 3240 3241 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3242 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3243 3244 rtl_hw_aspm_clkreq_enable(tp, true); 3245 } 3246 3247 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3248 { 3249 static const struct ephy_info e_info_8168ep_3[] = { 3250 { 0x00, 0x0000, 0x0080 }, 3251 { 0x0d, 0x0100, 0x0200 }, 3252 { 0x19, 0x8021, 0x0000 }, 3253 { 0x1e, 0x0000, 0x2000 }, 3254 }; 3255 3256 /* disable aspm and clock request before access ephy */ 3257 rtl_hw_aspm_clkreq_enable(tp, false); 3258 rtl_ephy_init(tp, e_info_8168ep_3); 3259 3260 rtl_hw_start_8168ep(tp); 3261 3262 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3263 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3264 3265 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3266 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3267 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3268 3269 rtl_hw_aspm_clkreq_enable(tp, true); 3270 } 3271 3272 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3273 { 3274 static const struct ephy_info e_info_8117[] = { 3275 { 0x19, 0x0040, 0x1100 }, 3276 { 0x59, 0x0040, 0x1100 }, 3277 }; 3278 int rg_saw_cnt; 3279 3280 rtl8168ep_stop_cmac(tp); 3281 3282 /* disable aspm and clock request before access ephy */ 3283 rtl_hw_aspm_clkreq_enable(tp, false); 3284 rtl_ephy_init(tp, e_info_8117); 3285 3286 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3287 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3288 3289 rtl_set_def_aspm_entry_latency(tp); 3290 3291 rtl_reset_packet_filter(tp); 3292 3293 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3294 3295 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3296 3297 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3298 3299 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3300 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3301 3302 rtl8168_config_eee_mac(tp); 3303 3304 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3305 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3306 3307 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3308 3309 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3310 3311 rtl_pcie_state_l2l3_disable(tp); 3312 3313 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3314 if (rg_saw_cnt > 0) { 3315 u16 sw_cnt_1ms_ini; 3316 3317 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3318 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3319 } 3320 3321 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3322 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3323 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3324 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3325 3326 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3327 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3328 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3329 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3330 3331 /* firmware is for MAC only */ 3332 r8169_apply_firmware(tp); 3333 3334 rtl_hw_aspm_clkreq_enable(tp, true); 3335 } 3336 3337 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3338 { 3339 static const struct ephy_info e_info_8102e_1[] = { 3340 { 0x01, 0, 0x6e65 }, 3341 { 0x02, 0, 0x091f }, 3342 { 0x03, 0, 0xc2f9 }, 3343 { 0x06, 0, 0xafb5 }, 3344 { 0x07, 0, 0x0e00 }, 3345 { 0x19, 0, 0xec80 }, 3346 { 0x01, 0, 0x2e65 }, 3347 { 0x01, 0, 0x6e65 } 3348 }; 3349 u8 cfg1; 3350 3351 rtl_set_def_aspm_entry_latency(tp); 3352 3353 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3354 3355 RTL_W8(tp, Config1, 3356 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3357 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3358 3359 cfg1 = RTL_R8(tp, Config1); 3360 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3361 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3362 3363 rtl_ephy_init(tp, e_info_8102e_1); 3364 } 3365 3366 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3367 { 3368 rtl_set_def_aspm_entry_latency(tp); 3369 3370 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3371 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3372 } 3373 3374 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3375 { 3376 rtl_hw_start_8102e_2(tp); 3377 3378 rtl_ephy_write(tp, 0x03, 0xc2f9); 3379 } 3380 3381 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3382 { 3383 static const struct ephy_info e_info_8401[] = { 3384 { 0x01, 0xffff, 0x6fe5 }, 3385 { 0x03, 0xffff, 0x0599 }, 3386 { 0x06, 0xffff, 0xaf25 }, 3387 { 0x07, 0xffff, 0x8e68 }, 3388 }; 3389 3390 rtl_ephy_init(tp, e_info_8401); 3391 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3392 } 3393 3394 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3395 { 3396 static const struct ephy_info e_info_8105e_1[] = { 3397 { 0x07, 0, 0x4000 }, 3398 { 0x19, 0, 0x0200 }, 3399 { 0x19, 0, 0x0020 }, 3400 { 0x1e, 0, 0x2000 }, 3401 { 0x03, 0, 0x0001 }, 3402 { 0x19, 0, 0x0100 }, 3403 { 0x19, 0, 0x0004 }, 3404 { 0x0a, 0, 0x0020 } 3405 }; 3406 3407 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3408 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3409 3410 /* Disable Early Tally Counter */ 3411 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3412 3413 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3414 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3415 3416 rtl_ephy_init(tp, e_info_8105e_1); 3417 3418 rtl_pcie_state_l2l3_disable(tp); 3419 } 3420 3421 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3422 { 3423 rtl_hw_start_8105e_1(tp); 3424 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3425 } 3426 3427 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3428 { 3429 static const struct ephy_info e_info_8402[] = { 3430 { 0x19, 0xffff, 0xff64 }, 3431 { 0x1e, 0, 0x4000 } 3432 }; 3433 3434 rtl_set_def_aspm_entry_latency(tp); 3435 3436 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3437 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3438 3439 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3440 3441 rtl_ephy_init(tp, e_info_8402); 3442 3443 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3444 rtl_reset_packet_filter(tp); 3445 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3446 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3447 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3448 3449 /* disable EEE */ 3450 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3451 3452 rtl_pcie_state_l2l3_disable(tp); 3453 } 3454 3455 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3456 { 3457 rtl_hw_aspm_clkreq_enable(tp, false); 3458 3459 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3460 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3461 3462 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3463 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3464 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3465 3466 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3467 3468 /* disable EEE */ 3469 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3470 3471 rtl_pcie_state_l2l3_disable(tp); 3472 rtl_hw_aspm_clkreq_enable(tp, true); 3473 } 3474 3475 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3476 { 3477 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3478 } 3479 3480 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3481 { 3482 rtl_pcie_state_l2l3_disable(tp); 3483 3484 RTL_W16(tp, 0x382, 0x221b); 3485 RTL_W8(tp, 0x4500, 0); 3486 RTL_W16(tp, 0x4800, 0); 3487 3488 /* disable UPS */ 3489 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3490 3491 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3492 3493 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3494 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3495 3496 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3497 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3498 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3499 3500 /* disable new tx descriptor format */ 3501 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3502 3503 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3504 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3505 else 3506 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3507 3508 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3509 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3510 else 3511 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3512 3513 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3514 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3515 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3516 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3517 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3518 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3519 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3520 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3521 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3522 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3523 3524 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3525 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3526 udelay(1); 3527 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3528 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3529 3530 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3531 3532 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3533 3534 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3535 rtl8125b_config_eee_mac(tp); 3536 else 3537 rtl8125a_config_eee_mac(tp); 3538 3539 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3540 udelay(10); 3541 } 3542 3543 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3544 { 3545 static const struct ephy_info e_info_8125a_1[] = { 3546 { 0x01, 0xffff, 0xa812 }, 3547 { 0x09, 0xffff, 0x520c }, 3548 { 0x04, 0xffff, 0xd000 }, 3549 { 0x0d, 0xffff, 0xf702 }, 3550 { 0x0a, 0xffff, 0x8653 }, 3551 { 0x06, 0xffff, 0x001e }, 3552 { 0x08, 0xffff, 0x3595 }, 3553 { 0x20, 0xffff, 0x9455 }, 3554 { 0x21, 0xffff, 0x99ff }, 3555 { 0x02, 0xffff, 0x6046 }, 3556 { 0x29, 0xffff, 0xfe00 }, 3557 { 0x23, 0xffff, 0xab62 }, 3558 3559 { 0x41, 0xffff, 0xa80c }, 3560 { 0x49, 0xffff, 0x520c }, 3561 { 0x44, 0xffff, 0xd000 }, 3562 { 0x4d, 0xffff, 0xf702 }, 3563 { 0x4a, 0xffff, 0x8653 }, 3564 { 0x46, 0xffff, 0x001e }, 3565 { 0x48, 0xffff, 0x3595 }, 3566 { 0x60, 0xffff, 0x9455 }, 3567 { 0x61, 0xffff, 0x99ff }, 3568 { 0x42, 0xffff, 0x6046 }, 3569 { 0x69, 0xffff, 0xfe00 }, 3570 { 0x63, 0xffff, 0xab62 }, 3571 }; 3572 3573 rtl_set_def_aspm_entry_latency(tp); 3574 3575 /* disable aspm and clock request before access ephy */ 3576 rtl_hw_aspm_clkreq_enable(tp, false); 3577 rtl_ephy_init(tp, e_info_8125a_1); 3578 3579 rtl_hw_start_8125_common(tp); 3580 rtl_hw_aspm_clkreq_enable(tp, true); 3581 } 3582 3583 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3584 { 3585 static const struct ephy_info e_info_8125a_2[] = { 3586 { 0x04, 0xffff, 0xd000 }, 3587 { 0x0a, 0xffff, 0x8653 }, 3588 { 0x23, 0xffff, 0xab66 }, 3589 { 0x20, 0xffff, 0x9455 }, 3590 { 0x21, 0xffff, 0x99ff }, 3591 { 0x29, 0xffff, 0xfe04 }, 3592 3593 { 0x44, 0xffff, 0xd000 }, 3594 { 0x4a, 0xffff, 0x8653 }, 3595 { 0x63, 0xffff, 0xab66 }, 3596 { 0x60, 0xffff, 0x9455 }, 3597 { 0x61, 0xffff, 0x99ff }, 3598 { 0x69, 0xffff, 0xfe04 }, 3599 }; 3600 3601 rtl_set_def_aspm_entry_latency(tp); 3602 3603 /* disable aspm and clock request before access ephy */ 3604 rtl_hw_aspm_clkreq_enable(tp, false); 3605 rtl_ephy_init(tp, e_info_8125a_2); 3606 3607 rtl_hw_start_8125_common(tp); 3608 rtl_hw_aspm_clkreq_enable(tp, true); 3609 } 3610 3611 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3612 { 3613 static const struct ephy_info e_info_8125b[] = { 3614 { 0x0b, 0xffff, 0xa908 }, 3615 { 0x1e, 0xffff, 0x20eb }, 3616 { 0x4b, 0xffff, 0xa908 }, 3617 { 0x5e, 0xffff, 0x20eb }, 3618 { 0x22, 0x0030, 0x0020 }, 3619 { 0x62, 0x0030, 0x0020 }, 3620 }; 3621 3622 rtl_set_def_aspm_entry_latency(tp); 3623 rtl_hw_aspm_clkreq_enable(tp, false); 3624 3625 rtl_ephy_init(tp, e_info_8125b); 3626 rtl_hw_start_8125_common(tp); 3627 3628 rtl_hw_aspm_clkreq_enable(tp, true); 3629 } 3630 3631 static void rtl_hw_config(struct rtl8169_private *tp) 3632 { 3633 static const rtl_generic_fct hw_configs[] = { 3634 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3635 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3636 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3637 [RTL_GIGA_MAC_VER_10] = NULL, 3638 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3639 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3640 [RTL_GIGA_MAC_VER_13] = NULL, 3641 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3642 [RTL_GIGA_MAC_VER_16] = NULL, 3643 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3644 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3645 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3646 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3647 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3648 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3649 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3650 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3651 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3652 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3653 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3654 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3655 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3656 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3657 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3658 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3659 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3660 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3661 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3662 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3663 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3664 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3665 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3666 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3667 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3668 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3669 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3670 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3671 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3672 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3673 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3674 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3675 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3676 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3677 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3678 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3679 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3680 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3681 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3682 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3683 }; 3684 3685 if (hw_configs[tp->mac_version]) 3686 hw_configs[tp->mac_version](tp); 3687 } 3688 3689 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3690 { 3691 int i; 3692 3693 /* disable interrupt coalescing */ 3694 for (i = 0xa00; i < 0xb00; i += 4) 3695 RTL_W32(tp, i, 0); 3696 3697 rtl_hw_config(tp); 3698 } 3699 3700 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3701 { 3702 if (rtl_is_8168evl_up(tp)) 3703 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3704 else 3705 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3706 3707 rtl_hw_config(tp); 3708 3709 /* disable interrupt coalescing */ 3710 RTL_W16(tp, IntrMitigate, 0x0000); 3711 } 3712 3713 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3714 { 3715 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3716 3717 tp->cp_cmd |= PCIMulRW; 3718 3719 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3720 tp->mac_version == RTL_GIGA_MAC_VER_03) 3721 tp->cp_cmd |= EnAnaPLL; 3722 3723 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3724 3725 rtl8169_set_magic_reg(tp); 3726 3727 /* disable interrupt coalescing */ 3728 RTL_W16(tp, IntrMitigate, 0x0000); 3729 } 3730 3731 static void rtl_hw_start(struct rtl8169_private *tp) 3732 { 3733 rtl_unlock_config_regs(tp); 3734 3735 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3736 3737 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3738 rtl_hw_start_8169(tp); 3739 else if (rtl_is_8125(tp)) 3740 rtl_hw_start_8125(tp); 3741 else 3742 rtl_hw_start_8168(tp); 3743 3744 rtl_set_rx_max_size(tp); 3745 rtl_set_rx_tx_desc_registers(tp); 3746 rtl_lock_config_regs(tp); 3747 3748 rtl_jumbo_config(tp); 3749 3750 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3751 rtl_pci_commit(tp); 3752 3753 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3754 rtl_init_rxcfg(tp); 3755 rtl_set_tx_config_registers(tp); 3756 rtl_set_rx_config_features(tp, tp->dev->features); 3757 rtl_set_rx_mode(tp->dev); 3758 rtl_irq_enable(tp); 3759 } 3760 3761 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3762 { 3763 struct rtl8169_private *tp = netdev_priv(dev); 3764 3765 dev->mtu = new_mtu; 3766 netdev_update_features(dev); 3767 rtl_jumbo_config(tp); 3768 3769 switch (tp->mac_version) { 3770 case RTL_GIGA_MAC_VER_61: 3771 case RTL_GIGA_MAC_VER_63: 3772 rtl8125_set_eee_txidle_timer(tp); 3773 break; 3774 default: 3775 break; 3776 } 3777 3778 return 0; 3779 } 3780 3781 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3782 { 3783 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3784 3785 desc->opts2 = 0; 3786 /* Force memory writes to complete before releasing descriptor */ 3787 dma_wmb(); 3788 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3789 } 3790 3791 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3792 struct RxDesc *desc) 3793 { 3794 struct device *d = tp_to_dev(tp); 3795 int node = dev_to_node(d); 3796 dma_addr_t mapping; 3797 struct page *data; 3798 3799 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3800 if (!data) 3801 return NULL; 3802 3803 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3804 if (unlikely(dma_mapping_error(d, mapping))) { 3805 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3806 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3807 return NULL; 3808 } 3809 3810 desc->addr = cpu_to_le64(mapping); 3811 rtl8169_mark_to_asic(desc); 3812 3813 return data; 3814 } 3815 3816 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3817 { 3818 int i; 3819 3820 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3821 dma_unmap_page(tp_to_dev(tp), 3822 le64_to_cpu(tp->RxDescArray[i].addr), 3823 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3824 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3825 tp->Rx_databuff[i] = NULL; 3826 tp->RxDescArray[i].addr = 0; 3827 tp->RxDescArray[i].opts1 = 0; 3828 } 3829 } 3830 3831 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3832 { 3833 int i; 3834 3835 for (i = 0; i < NUM_RX_DESC; i++) { 3836 struct page *data; 3837 3838 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3839 if (!data) { 3840 rtl8169_rx_clear(tp); 3841 return -ENOMEM; 3842 } 3843 tp->Rx_databuff[i] = data; 3844 } 3845 3846 /* mark as last descriptor in the ring */ 3847 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3848 3849 return 0; 3850 } 3851 3852 static int rtl8169_init_ring(struct rtl8169_private *tp) 3853 { 3854 rtl8169_init_ring_indexes(tp); 3855 3856 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3857 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3858 3859 return rtl8169_rx_fill(tp); 3860 } 3861 3862 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3863 { 3864 struct ring_info *tx_skb = tp->tx_skb + entry; 3865 struct TxDesc *desc = tp->TxDescArray + entry; 3866 3867 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3868 DMA_TO_DEVICE); 3869 memset(desc, 0, sizeof(*desc)); 3870 memset(tx_skb, 0, sizeof(*tx_skb)); 3871 } 3872 3873 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3874 unsigned int n) 3875 { 3876 unsigned int i; 3877 3878 for (i = 0; i < n; i++) { 3879 unsigned int entry = (start + i) % NUM_TX_DESC; 3880 struct ring_info *tx_skb = tp->tx_skb + entry; 3881 unsigned int len = tx_skb->len; 3882 3883 if (len) { 3884 struct sk_buff *skb = tx_skb->skb; 3885 3886 rtl8169_unmap_tx_skb(tp, entry); 3887 if (skb) 3888 dev_consume_skb_any(skb); 3889 } 3890 } 3891 } 3892 3893 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3894 { 3895 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3896 netdev_reset_queue(tp->dev); 3897 } 3898 3899 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3900 { 3901 napi_disable(&tp->napi); 3902 3903 /* Give a racing hard_start_xmit a few cycles to complete. */ 3904 synchronize_net(); 3905 3906 /* Disable interrupts */ 3907 rtl8169_irq_mask_and_ack(tp); 3908 3909 rtl_rx_close(tp); 3910 3911 if (going_down && tp->dev->wol_enabled) 3912 goto no_reset; 3913 3914 switch (tp->mac_version) { 3915 case RTL_GIGA_MAC_VER_27: 3916 case RTL_GIGA_MAC_VER_28: 3917 case RTL_GIGA_MAC_VER_31: 3918 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3919 break; 3920 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3921 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3922 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3923 break; 3924 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3925 rtl_enable_rxdvgate(tp); 3926 fsleep(2000); 3927 break; 3928 default: 3929 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3930 fsleep(100); 3931 break; 3932 } 3933 3934 rtl_hw_reset(tp); 3935 no_reset: 3936 rtl8169_tx_clear(tp); 3937 rtl8169_init_ring_indexes(tp); 3938 } 3939 3940 static void rtl_reset_work(struct rtl8169_private *tp) 3941 { 3942 int i; 3943 3944 netif_stop_queue(tp->dev); 3945 3946 rtl8169_cleanup(tp, false); 3947 3948 for (i = 0; i < NUM_RX_DESC; i++) 3949 rtl8169_mark_to_asic(tp->RxDescArray + i); 3950 3951 napi_enable(&tp->napi); 3952 rtl_hw_start(tp); 3953 } 3954 3955 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3956 { 3957 struct rtl8169_private *tp = netdev_priv(dev); 3958 3959 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3960 } 3961 3962 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3963 void *addr, unsigned int entry, bool desc_own) 3964 { 3965 struct TxDesc *txd = tp->TxDescArray + entry; 3966 struct device *d = tp_to_dev(tp); 3967 dma_addr_t mapping; 3968 u32 opts1; 3969 int ret; 3970 3971 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3972 ret = dma_mapping_error(d, mapping); 3973 if (unlikely(ret)) { 3974 if (net_ratelimit()) 3975 netdev_err(tp->dev, "Failed to map TX data!\n"); 3976 return ret; 3977 } 3978 3979 txd->addr = cpu_to_le64(mapping); 3980 txd->opts2 = cpu_to_le32(opts[1]); 3981 3982 opts1 = opts[0] | len; 3983 if (entry == NUM_TX_DESC - 1) 3984 opts1 |= RingEnd; 3985 if (desc_own) 3986 opts1 |= DescOwn; 3987 txd->opts1 = cpu_to_le32(opts1); 3988 3989 tp->tx_skb[entry].len = len; 3990 3991 return 0; 3992 } 3993 3994 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3995 const u32 *opts, unsigned int entry) 3996 { 3997 struct skb_shared_info *info = skb_shinfo(skb); 3998 unsigned int cur_frag; 3999 4000 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4001 const skb_frag_t *frag = info->frags + cur_frag; 4002 void *addr = skb_frag_address(frag); 4003 u32 len = skb_frag_size(frag); 4004 4005 entry = (entry + 1) % NUM_TX_DESC; 4006 4007 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4008 goto err_out; 4009 } 4010 4011 return 0; 4012 4013 err_out: 4014 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4015 return -EIO; 4016 } 4017 4018 static bool rtl_skb_is_udp(struct sk_buff *skb) 4019 { 4020 int no = skb_network_offset(skb); 4021 struct ipv6hdr *i6h, _i6h; 4022 struct iphdr *ih, _ih; 4023 4024 switch (vlan_get_protocol(skb)) { 4025 case htons(ETH_P_IP): 4026 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4027 return ih && ih->protocol == IPPROTO_UDP; 4028 case htons(ETH_P_IPV6): 4029 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4030 return i6h && i6h->nexthdr == IPPROTO_UDP; 4031 default: 4032 return false; 4033 } 4034 } 4035 4036 #define RTL_MIN_PATCH_LEN 47 4037 4038 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4039 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4040 struct sk_buff *skb) 4041 { 4042 unsigned int padto = 0, len = skb->len; 4043 4044 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4045 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4046 unsigned int trans_data_len = skb_tail_pointer(skb) - 4047 skb_transport_header(skb); 4048 4049 if (trans_data_len >= offsetof(struct udphdr, len) && 4050 trans_data_len < RTL_MIN_PATCH_LEN) { 4051 u16 dest = ntohs(udp_hdr(skb)->dest); 4052 4053 /* dest is a standard PTP port */ 4054 if (dest == 319 || dest == 320) 4055 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4056 } 4057 4058 if (trans_data_len < sizeof(struct udphdr)) 4059 padto = max_t(unsigned int, padto, 4060 len + sizeof(struct udphdr) - trans_data_len); 4061 } 4062 4063 return padto; 4064 } 4065 4066 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4067 struct sk_buff *skb) 4068 { 4069 unsigned int padto; 4070 4071 padto = rtl8125_quirk_udp_padto(tp, skb); 4072 4073 switch (tp->mac_version) { 4074 case RTL_GIGA_MAC_VER_34: 4075 case RTL_GIGA_MAC_VER_60: 4076 case RTL_GIGA_MAC_VER_61: 4077 case RTL_GIGA_MAC_VER_63: 4078 padto = max_t(unsigned int, padto, ETH_ZLEN); 4079 default: 4080 break; 4081 } 4082 4083 return padto; 4084 } 4085 4086 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4087 { 4088 u32 mss = skb_shinfo(skb)->gso_size; 4089 4090 if (mss) { 4091 opts[0] |= TD_LSO; 4092 opts[0] |= mss << TD0_MSS_SHIFT; 4093 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4094 const struct iphdr *ip = ip_hdr(skb); 4095 4096 if (ip->protocol == IPPROTO_TCP) 4097 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4098 else if (ip->protocol == IPPROTO_UDP) 4099 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4100 else 4101 WARN_ON_ONCE(1); 4102 } 4103 } 4104 4105 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4106 struct sk_buff *skb, u32 *opts) 4107 { 4108 u32 transport_offset = (u32)skb_transport_offset(skb); 4109 struct skb_shared_info *shinfo = skb_shinfo(skb); 4110 u32 mss = shinfo->gso_size; 4111 4112 if (mss) { 4113 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4114 opts[0] |= TD1_GTSENV4; 4115 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4116 if (skb_cow_head(skb, 0)) 4117 return false; 4118 4119 tcp_v6_gso_csum_prep(skb); 4120 opts[0] |= TD1_GTSENV6; 4121 } else { 4122 WARN_ON_ONCE(1); 4123 } 4124 4125 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4126 opts[1] |= mss << TD1_MSS_SHIFT; 4127 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4128 u8 ip_protocol; 4129 4130 switch (vlan_get_protocol(skb)) { 4131 case htons(ETH_P_IP): 4132 opts[1] |= TD1_IPv4_CS; 4133 ip_protocol = ip_hdr(skb)->protocol; 4134 break; 4135 4136 case htons(ETH_P_IPV6): 4137 opts[1] |= TD1_IPv6_CS; 4138 ip_protocol = ipv6_hdr(skb)->nexthdr; 4139 break; 4140 4141 default: 4142 ip_protocol = IPPROTO_RAW; 4143 break; 4144 } 4145 4146 if (ip_protocol == IPPROTO_TCP) 4147 opts[1] |= TD1_TCP_CS; 4148 else if (ip_protocol == IPPROTO_UDP) 4149 opts[1] |= TD1_UDP_CS; 4150 else 4151 WARN_ON_ONCE(1); 4152 4153 opts[1] |= transport_offset << TCPHO_SHIFT; 4154 } else { 4155 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4156 4157 /* skb_padto would free the skb on error */ 4158 return !__skb_put_padto(skb, padto, false); 4159 } 4160 4161 return true; 4162 } 4163 4164 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4165 { 4166 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4167 - READ_ONCE(tp->cur_tx); 4168 4169 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4170 return slots_avail > MAX_SKB_FRAGS; 4171 } 4172 4173 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4174 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4175 { 4176 switch (tp->mac_version) { 4177 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4178 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4179 return false; 4180 default: 4181 return true; 4182 } 4183 } 4184 4185 static void rtl8169_doorbell(struct rtl8169_private *tp) 4186 { 4187 if (rtl_is_8125(tp)) 4188 RTL_W16(tp, TxPoll_8125, BIT(0)); 4189 else 4190 RTL_W8(tp, TxPoll, NPQ); 4191 } 4192 4193 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4194 struct net_device *dev) 4195 { 4196 unsigned int frags = skb_shinfo(skb)->nr_frags; 4197 struct rtl8169_private *tp = netdev_priv(dev); 4198 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4199 struct TxDesc *txd_first, *txd_last; 4200 bool stop_queue, door_bell; 4201 u32 opts[2]; 4202 4203 if (unlikely(!rtl_tx_slots_avail(tp))) { 4204 if (net_ratelimit()) 4205 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4206 goto err_stop_0; 4207 } 4208 4209 opts[1] = rtl8169_tx_vlan_tag(skb); 4210 opts[0] = 0; 4211 4212 if (!rtl_chip_supports_csum_v2(tp)) 4213 rtl8169_tso_csum_v1(skb, opts); 4214 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4215 goto err_dma_0; 4216 4217 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4218 entry, false))) 4219 goto err_dma_0; 4220 4221 txd_first = tp->TxDescArray + entry; 4222 4223 if (frags) { 4224 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4225 goto err_dma_1; 4226 entry = (entry + frags) % NUM_TX_DESC; 4227 } 4228 4229 txd_last = tp->TxDescArray + entry; 4230 txd_last->opts1 |= cpu_to_le32(LastFrag); 4231 tp->tx_skb[entry].skb = skb; 4232 4233 skb_tx_timestamp(skb); 4234 4235 /* Force memory writes to complete before releasing descriptor */ 4236 dma_wmb(); 4237 4238 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4239 4240 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4241 4242 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4243 smp_wmb(); 4244 4245 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4246 4247 stop_queue = !rtl_tx_slots_avail(tp); 4248 if (unlikely(stop_queue)) { 4249 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4250 * not miss a ring update when it notices a stopped queue. 4251 */ 4252 smp_wmb(); 4253 netif_stop_queue(dev); 4254 /* Sync with rtl_tx: 4255 * - publish queue status and cur_tx ring index (write barrier) 4256 * - refresh dirty_tx ring index (read barrier). 4257 * May the current thread have a pessimistic view of the ring 4258 * status and forget to wake up queue, a racing rtl_tx thread 4259 * can't. 4260 */ 4261 smp_mb__after_atomic(); 4262 if (rtl_tx_slots_avail(tp)) 4263 netif_start_queue(dev); 4264 door_bell = true; 4265 } 4266 4267 if (door_bell) 4268 rtl8169_doorbell(tp); 4269 4270 return NETDEV_TX_OK; 4271 4272 err_dma_1: 4273 rtl8169_unmap_tx_skb(tp, entry); 4274 err_dma_0: 4275 dev_kfree_skb_any(skb); 4276 dev->stats.tx_dropped++; 4277 return NETDEV_TX_OK; 4278 4279 err_stop_0: 4280 netif_stop_queue(dev); 4281 dev->stats.tx_dropped++; 4282 return NETDEV_TX_BUSY; 4283 } 4284 4285 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4286 { 4287 struct skb_shared_info *info = skb_shinfo(skb); 4288 unsigned int nr_frags = info->nr_frags; 4289 4290 if (!nr_frags) 4291 return UINT_MAX; 4292 4293 return skb_frag_size(info->frags + nr_frags - 1); 4294 } 4295 4296 /* Workaround for hw issues with TSO on RTL8168evl */ 4297 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4298 netdev_features_t features) 4299 { 4300 /* IPv4 header has options field */ 4301 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4302 ip_hdrlen(skb) > sizeof(struct iphdr)) 4303 features &= ~NETIF_F_ALL_TSO; 4304 4305 /* IPv4 TCP header has options field */ 4306 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4307 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4308 features &= ~NETIF_F_ALL_TSO; 4309 4310 else if (rtl_last_frag_len(skb) <= 6) 4311 features &= ~NETIF_F_ALL_TSO; 4312 4313 return features; 4314 } 4315 4316 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4317 struct net_device *dev, 4318 netdev_features_t features) 4319 { 4320 int transport_offset = skb_transport_offset(skb); 4321 struct rtl8169_private *tp = netdev_priv(dev); 4322 4323 if (skb_is_gso(skb)) { 4324 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4325 features = rtl8168evl_fix_tso(skb, features); 4326 4327 if (transport_offset > GTTCPHO_MAX && 4328 rtl_chip_supports_csum_v2(tp)) 4329 features &= ~NETIF_F_ALL_TSO; 4330 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4331 /* work around hw bug on some chip versions */ 4332 if (skb->len < ETH_ZLEN) 4333 features &= ~NETIF_F_CSUM_MASK; 4334 4335 if (rtl_quirk_packet_padto(tp, skb)) 4336 features &= ~NETIF_F_CSUM_MASK; 4337 4338 if (transport_offset > TCPHO_MAX && 4339 rtl_chip_supports_csum_v2(tp)) 4340 features &= ~NETIF_F_CSUM_MASK; 4341 } 4342 4343 return vlan_features_check(skb, features); 4344 } 4345 4346 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4347 { 4348 struct rtl8169_private *tp = netdev_priv(dev); 4349 struct pci_dev *pdev = tp->pci_dev; 4350 int pci_status_errs; 4351 u16 pci_cmd; 4352 4353 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4354 4355 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4356 4357 if (net_ratelimit()) 4358 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4359 pci_cmd, pci_status_errs); 4360 /* 4361 * The recovery sequence below admits a very elaborated explanation: 4362 * - it seems to work; 4363 * - I did not see what else could be done; 4364 * - it makes iop3xx happy. 4365 * 4366 * Feel free to adjust to your needs. 4367 */ 4368 if (pdev->broken_parity_status) 4369 pci_cmd &= ~PCI_COMMAND_PARITY; 4370 else 4371 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4372 4373 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4374 4375 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4376 } 4377 4378 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4379 int budget) 4380 { 4381 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4382 struct sk_buff *skb; 4383 4384 dirty_tx = tp->dirty_tx; 4385 4386 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4387 unsigned int entry = dirty_tx % NUM_TX_DESC; 4388 u32 status; 4389 4390 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4391 if (status & DescOwn) 4392 break; 4393 4394 skb = tp->tx_skb[entry].skb; 4395 rtl8169_unmap_tx_skb(tp, entry); 4396 4397 if (skb) { 4398 pkts_compl++; 4399 bytes_compl += skb->len; 4400 napi_consume_skb(skb, budget); 4401 } 4402 dirty_tx++; 4403 } 4404 4405 if (tp->dirty_tx != dirty_tx) { 4406 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4407 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4408 4409 /* Sync with rtl8169_start_xmit: 4410 * - publish dirty_tx ring index (write barrier) 4411 * - refresh cur_tx ring index and queue status (read barrier) 4412 * May the current thread miss the stopped queue condition, 4413 * a racing xmit thread can only have a right view of the 4414 * ring status. 4415 */ 4416 smp_store_mb(tp->dirty_tx, dirty_tx); 4417 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4418 netif_wake_queue(dev); 4419 /* 4420 * 8168 hack: TxPoll requests are lost when the Tx packets are 4421 * too close. Let's kick an extra TxPoll request when a burst 4422 * of start_xmit activity is detected (if it is not detected, 4423 * it is slow enough). -- FR 4424 * If skb is NULL then we come here again once a tx irq is 4425 * triggered after the last fragment is marked transmitted. 4426 */ 4427 if (tp->cur_tx != dirty_tx && skb) 4428 rtl8169_doorbell(tp); 4429 } 4430 } 4431 4432 static inline int rtl8169_fragmented_frame(u32 status) 4433 { 4434 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4435 } 4436 4437 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4438 { 4439 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4440 4441 if (status == RxProtoTCP || status == RxProtoUDP) 4442 skb->ip_summed = CHECKSUM_UNNECESSARY; 4443 else 4444 skb_checksum_none_assert(skb); 4445 } 4446 4447 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4448 { 4449 struct device *d = tp_to_dev(tp); 4450 int count; 4451 4452 for (count = 0; count < budget; count++, tp->cur_rx++) { 4453 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4454 struct RxDesc *desc = tp->RxDescArray + entry; 4455 struct sk_buff *skb; 4456 const void *rx_buf; 4457 dma_addr_t addr; 4458 u32 status; 4459 4460 status = le32_to_cpu(desc->opts1); 4461 if (status & DescOwn) 4462 break; 4463 4464 /* This barrier is needed to keep us from reading 4465 * any other fields out of the Rx descriptor until 4466 * we know the status of DescOwn 4467 */ 4468 dma_rmb(); 4469 4470 if (unlikely(status & RxRES)) { 4471 if (net_ratelimit()) 4472 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4473 status); 4474 dev->stats.rx_errors++; 4475 if (status & (RxRWT | RxRUNT)) 4476 dev->stats.rx_length_errors++; 4477 if (status & RxCRC) 4478 dev->stats.rx_crc_errors++; 4479 4480 if (!(dev->features & NETIF_F_RXALL)) 4481 goto release_descriptor; 4482 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4483 goto release_descriptor; 4484 } 4485 4486 pkt_size = status & GENMASK(13, 0); 4487 if (likely(!(dev->features & NETIF_F_RXFCS))) 4488 pkt_size -= ETH_FCS_LEN; 4489 4490 /* The driver does not support incoming fragmented frames. 4491 * They are seen as a symptom of over-mtu sized frames. 4492 */ 4493 if (unlikely(rtl8169_fragmented_frame(status))) { 4494 dev->stats.rx_dropped++; 4495 dev->stats.rx_length_errors++; 4496 goto release_descriptor; 4497 } 4498 4499 skb = napi_alloc_skb(&tp->napi, pkt_size); 4500 if (unlikely(!skb)) { 4501 dev->stats.rx_dropped++; 4502 goto release_descriptor; 4503 } 4504 4505 addr = le64_to_cpu(desc->addr); 4506 rx_buf = page_address(tp->Rx_databuff[entry]); 4507 4508 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4509 prefetch(rx_buf); 4510 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4511 skb->tail += pkt_size; 4512 skb->len = pkt_size; 4513 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4514 4515 rtl8169_rx_csum(skb, status); 4516 skb->protocol = eth_type_trans(skb, dev); 4517 4518 rtl8169_rx_vlan_tag(desc, skb); 4519 4520 if (skb->pkt_type == PACKET_MULTICAST) 4521 dev->stats.multicast++; 4522 4523 napi_gro_receive(&tp->napi, skb); 4524 4525 dev_sw_netstats_rx_add(dev, pkt_size); 4526 release_descriptor: 4527 rtl8169_mark_to_asic(desc); 4528 } 4529 4530 return count; 4531 } 4532 4533 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4534 { 4535 struct rtl8169_private *tp = dev_instance; 4536 u32 status = rtl_get_events(tp); 4537 4538 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4539 return IRQ_NONE; 4540 4541 if (unlikely(status & SYSErr)) { 4542 rtl8169_pcierr_interrupt(tp->dev); 4543 goto out; 4544 } 4545 4546 if (status & LinkChg) 4547 phy_mac_interrupt(tp->phydev); 4548 4549 if (unlikely(status & RxFIFOOver && 4550 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4551 netif_stop_queue(tp->dev); 4552 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4553 } 4554 4555 if (napi_schedule_prep(&tp->napi)) { 4556 rtl_irq_disable(tp); 4557 __napi_schedule(&tp->napi); 4558 } 4559 out: 4560 rtl_ack_events(tp, status); 4561 4562 return IRQ_HANDLED; 4563 } 4564 4565 static void rtl_task(struct work_struct *work) 4566 { 4567 struct rtl8169_private *tp = 4568 container_of(work, struct rtl8169_private, wk.work); 4569 4570 rtnl_lock(); 4571 4572 if (!netif_running(tp->dev) || 4573 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4574 goto out_unlock; 4575 4576 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4577 rtl_reset_work(tp); 4578 netif_wake_queue(tp->dev); 4579 } 4580 out_unlock: 4581 rtnl_unlock(); 4582 } 4583 4584 static int rtl8169_poll(struct napi_struct *napi, int budget) 4585 { 4586 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4587 struct net_device *dev = tp->dev; 4588 int work_done; 4589 4590 work_done = rtl_rx(dev, tp, budget); 4591 4592 rtl_tx(dev, tp, budget); 4593 4594 if (work_done < budget && napi_complete_done(napi, work_done)) 4595 rtl_irq_enable(tp); 4596 4597 return work_done; 4598 } 4599 4600 static void r8169_phylink_handler(struct net_device *ndev) 4601 { 4602 struct rtl8169_private *tp = netdev_priv(ndev); 4603 4604 if (netif_carrier_ok(ndev)) { 4605 rtl_link_chg_patch(tp); 4606 pm_request_resume(&tp->pci_dev->dev); 4607 } else { 4608 pm_runtime_idle(&tp->pci_dev->dev); 4609 } 4610 4611 if (net_ratelimit()) 4612 phy_print_status(tp->phydev); 4613 } 4614 4615 static int r8169_phy_connect(struct rtl8169_private *tp) 4616 { 4617 struct phy_device *phydev = tp->phydev; 4618 phy_interface_t phy_mode; 4619 int ret; 4620 4621 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4622 PHY_INTERFACE_MODE_MII; 4623 4624 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4625 phy_mode); 4626 if (ret) 4627 return ret; 4628 4629 if (!tp->supports_gmii) 4630 phy_set_max_speed(phydev, SPEED_100); 4631 4632 phy_support_asym_pause(phydev); 4633 4634 phy_attached_info(phydev); 4635 4636 return 0; 4637 } 4638 4639 static void rtl8169_down(struct rtl8169_private *tp) 4640 { 4641 /* Clear all task flags */ 4642 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4643 4644 phy_stop(tp->phydev); 4645 4646 rtl8169_update_counters(tp); 4647 4648 rtl8169_cleanup(tp, true); 4649 4650 rtl_prepare_power_down(tp); 4651 } 4652 4653 static void rtl8169_up(struct rtl8169_private *tp) 4654 { 4655 phy_resume(tp->phydev); 4656 rtl8169_init_phy(tp); 4657 napi_enable(&tp->napi); 4658 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4659 rtl_reset_work(tp); 4660 4661 phy_start(tp->phydev); 4662 } 4663 4664 static int rtl8169_close(struct net_device *dev) 4665 { 4666 struct rtl8169_private *tp = netdev_priv(dev); 4667 struct pci_dev *pdev = tp->pci_dev; 4668 4669 pm_runtime_get_sync(&pdev->dev); 4670 4671 netif_stop_queue(dev); 4672 rtl8169_down(tp); 4673 rtl8169_rx_clear(tp); 4674 4675 cancel_work_sync(&tp->wk.work); 4676 4677 free_irq(pci_irq_vector(pdev, 0), tp); 4678 4679 phy_disconnect(tp->phydev); 4680 4681 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4682 tp->RxPhyAddr); 4683 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4684 tp->TxPhyAddr); 4685 tp->TxDescArray = NULL; 4686 tp->RxDescArray = NULL; 4687 4688 pm_runtime_put_sync(&pdev->dev); 4689 4690 return 0; 4691 } 4692 4693 #ifdef CONFIG_NET_POLL_CONTROLLER 4694 static void rtl8169_netpoll(struct net_device *dev) 4695 { 4696 struct rtl8169_private *tp = netdev_priv(dev); 4697 4698 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4699 } 4700 #endif 4701 4702 static int rtl_open(struct net_device *dev) 4703 { 4704 struct rtl8169_private *tp = netdev_priv(dev); 4705 struct pci_dev *pdev = tp->pci_dev; 4706 unsigned long irqflags; 4707 int retval = -ENOMEM; 4708 4709 pm_runtime_get_sync(&pdev->dev); 4710 4711 /* 4712 * Rx and Tx descriptors needs 256 bytes alignment. 4713 * dma_alloc_coherent provides more. 4714 */ 4715 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4716 &tp->TxPhyAddr, GFP_KERNEL); 4717 if (!tp->TxDescArray) 4718 goto out; 4719 4720 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4721 &tp->RxPhyAddr, GFP_KERNEL); 4722 if (!tp->RxDescArray) 4723 goto err_free_tx_0; 4724 4725 retval = rtl8169_init_ring(tp); 4726 if (retval < 0) 4727 goto err_free_rx_1; 4728 4729 rtl_request_firmware(tp); 4730 4731 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4732 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt, 4733 irqflags, dev->name, tp); 4734 if (retval < 0) 4735 goto err_release_fw_2; 4736 4737 retval = r8169_phy_connect(tp); 4738 if (retval) 4739 goto err_free_irq; 4740 4741 rtl8169_up(tp); 4742 rtl8169_init_counter_offsets(tp); 4743 netif_start_queue(dev); 4744 out: 4745 pm_runtime_put_sync(&pdev->dev); 4746 4747 return retval; 4748 4749 err_free_irq: 4750 free_irq(pci_irq_vector(pdev, 0), tp); 4751 err_release_fw_2: 4752 rtl_release_firmware(tp); 4753 rtl8169_rx_clear(tp); 4754 err_free_rx_1: 4755 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4756 tp->RxPhyAddr); 4757 tp->RxDescArray = NULL; 4758 err_free_tx_0: 4759 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4760 tp->TxPhyAddr); 4761 tp->TxDescArray = NULL; 4762 goto out; 4763 } 4764 4765 static void 4766 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4767 { 4768 struct rtl8169_private *tp = netdev_priv(dev); 4769 struct pci_dev *pdev = tp->pci_dev; 4770 struct rtl8169_counters *counters = tp->counters; 4771 4772 pm_runtime_get_noresume(&pdev->dev); 4773 4774 netdev_stats_to_stats64(stats, &dev->stats); 4775 dev_fetch_sw_netstats(stats, dev->tstats); 4776 4777 /* 4778 * Fetch additional counter values missing in stats collected by driver 4779 * from tally counters. 4780 */ 4781 if (pm_runtime_active(&pdev->dev)) 4782 rtl8169_update_counters(tp); 4783 4784 /* 4785 * Subtract values fetched during initalization. 4786 * See rtl8169_init_counter_offsets for a description why we do that. 4787 */ 4788 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4789 le64_to_cpu(tp->tc_offset.tx_errors); 4790 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4791 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4792 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4793 le16_to_cpu(tp->tc_offset.tx_aborted); 4794 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4795 le16_to_cpu(tp->tc_offset.rx_missed); 4796 4797 pm_runtime_put_noidle(&pdev->dev); 4798 } 4799 4800 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4801 { 4802 netif_device_detach(tp->dev); 4803 4804 if (netif_running(tp->dev)) 4805 rtl8169_down(tp); 4806 } 4807 4808 #ifdef CONFIG_PM 4809 4810 static int rtl8169_runtime_resume(struct device *dev) 4811 { 4812 struct rtl8169_private *tp = dev_get_drvdata(dev); 4813 4814 rtl_rar_set(tp, tp->dev->dev_addr); 4815 __rtl8169_set_wol(tp, tp->saved_wolopts); 4816 4817 if (tp->TxDescArray) 4818 rtl8169_up(tp); 4819 4820 netif_device_attach(tp->dev); 4821 4822 return 0; 4823 } 4824 4825 static int __maybe_unused rtl8169_suspend(struct device *device) 4826 { 4827 struct rtl8169_private *tp = dev_get_drvdata(device); 4828 4829 rtnl_lock(); 4830 rtl8169_net_suspend(tp); 4831 if (!device_may_wakeup(tp_to_dev(tp))) 4832 clk_disable_unprepare(tp->clk); 4833 rtnl_unlock(); 4834 4835 return 0; 4836 } 4837 4838 static int __maybe_unused rtl8169_resume(struct device *device) 4839 { 4840 struct rtl8169_private *tp = dev_get_drvdata(device); 4841 4842 if (!device_may_wakeup(tp_to_dev(tp))) 4843 clk_prepare_enable(tp->clk); 4844 4845 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4846 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4847 rtl_init_rxcfg(tp); 4848 4849 return rtl8169_runtime_resume(device); 4850 } 4851 4852 static int rtl8169_runtime_suspend(struct device *device) 4853 { 4854 struct rtl8169_private *tp = dev_get_drvdata(device); 4855 4856 if (!tp->TxDescArray) { 4857 netif_device_detach(tp->dev); 4858 return 0; 4859 } 4860 4861 rtnl_lock(); 4862 __rtl8169_set_wol(tp, WAKE_PHY); 4863 rtl8169_net_suspend(tp); 4864 rtnl_unlock(); 4865 4866 return 0; 4867 } 4868 4869 static int rtl8169_runtime_idle(struct device *device) 4870 { 4871 struct rtl8169_private *tp = dev_get_drvdata(device); 4872 4873 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4874 pm_schedule_suspend(device, 10000); 4875 4876 return -EBUSY; 4877 } 4878 4879 static const struct dev_pm_ops rtl8169_pm_ops = { 4880 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4881 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4882 rtl8169_runtime_idle) 4883 }; 4884 4885 #endif /* CONFIG_PM */ 4886 4887 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4888 { 4889 /* WoL fails with 8168b when the receiver is disabled. */ 4890 switch (tp->mac_version) { 4891 case RTL_GIGA_MAC_VER_11: 4892 case RTL_GIGA_MAC_VER_12: 4893 case RTL_GIGA_MAC_VER_17: 4894 pci_clear_master(tp->pci_dev); 4895 4896 RTL_W8(tp, ChipCmd, CmdRxEnb); 4897 rtl_pci_commit(tp); 4898 break; 4899 default: 4900 break; 4901 } 4902 } 4903 4904 static void rtl_shutdown(struct pci_dev *pdev) 4905 { 4906 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4907 4908 rtnl_lock(); 4909 rtl8169_net_suspend(tp); 4910 rtnl_unlock(); 4911 4912 /* Restore original MAC address */ 4913 rtl_rar_set(tp, tp->dev->perm_addr); 4914 4915 if (system_state == SYSTEM_POWER_OFF) { 4916 if (tp->saved_wolopts) 4917 rtl_wol_shutdown_quirk(tp); 4918 4919 pci_wake_from_d3(pdev, tp->saved_wolopts); 4920 pci_set_power_state(pdev, PCI_D3hot); 4921 } 4922 } 4923 4924 static void rtl_remove_one(struct pci_dev *pdev) 4925 { 4926 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4927 4928 if (pci_dev_run_wake(pdev)) 4929 pm_runtime_get_noresume(&pdev->dev); 4930 4931 unregister_netdev(tp->dev); 4932 4933 if (tp->dash_type != RTL_DASH_NONE) 4934 rtl8168_driver_stop(tp); 4935 4936 rtl_release_firmware(tp); 4937 4938 /* restore original MAC address */ 4939 rtl_rar_set(tp, tp->dev->perm_addr); 4940 } 4941 4942 static const struct net_device_ops rtl_netdev_ops = { 4943 .ndo_open = rtl_open, 4944 .ndo_stop = rtl8169_close, 4945 .ndo_get_stats64 = rtl8169_get_stats64, 4946 .ndo_start_xmit = rtl8169_start_xmit, 4947 .ndo_features_check = rtl8169_features_check, 4948 .ndo_tx_timeout = rtl8169_tx_timeout, 4949 .ndo_validate_addr = eth_validate_addr, 4950 .ndo_change_mtu = rtl8169_change_mtu, 4951 .ndo_fix_features = rtl8169_fix_features, 4952 .ndo_set_features = rtl8169_set_features, 4953 .ndo_set_mac_address = rtl_set_mac_address, 4954 .ndo_do_ioctl = phy_do_ioctl_running, 4955 .ndo_set_rx_mode = rtl_set_rx_mode, 4956 #ifdef CONFIG_NET_POLL_CONTROLLER 4957 .ndo_poll_controller = rtl8169_netpoll, 4958 #endif 4959 4960 }; 4961 4962 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4963 { 4964 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4965 4966 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4967 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4968 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4969 /* special workaround needed */ 4970 tp->irq_mask |= RxFIFOOver; 4971 else 4972 tp->irq_mask |= RxOverflow; 4973 } 4974 4975 static int rtl_alloc_irq(struct rtl8169_private *tp) 4976 { 4977 unsigned int flags; 4978 4979 switch (tp->mac_version) { 4980 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4981 rtl_unlock_config_regs(tp); 4982 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4983 rtl_lock_config_regs(tp); 4984 fallthrough; 4985 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4986 flags = PCI_IRQ_LEGACY; 4987 break; 4988 default: 4989 flags = PCI_IRQ_ALL_TYPES; 4990 break; 4991 } 4992 4993 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4994 } 4995 4996 static void rtl_read_mac_address(struct rtl8169_private *tp, 4997 u8 mac_addr[ETH_ALEN]) 4998 { 4999 /* Get MAC address */ 5000 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5001 u32 value; 5002 5003 value = rtl_eri_read(tp, 0xe0); 5004 put_unaligned_le32(value, mac_addr); 5005 value = rtl_eri_read(tp, 0xe4); 5006 put_unaligned_le16(value, mac_addr + 4); 5007 } else if (rtl_is_8125(tp)) { 5008 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5009 } 5010 } 5011 5012 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5013 { 5014 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5015 } 5016 5017 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5018 { 5019 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5020 } 5021 5022 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5023 { 5024 struct rtl8169_private *tp = mii_bus->priv; 5025 5026 if (phyaddr > 0) 5027 return -ENODEV; 5028 5029 return rtl_readphy(tp, phyreg); 5030 } 5031 5032 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5033 int phyreg, u16 val) 5034 { 5035 struct rtl8169_private *tp = mii_bus->priv; 5036 5037 if (phyaddr > 0) 5038 return -ENODEV; 5039 5040 rtl_writephy(tp, phyreg, val); 5041 5042 return 0; 5043 } 5044 5045 static int r8169_mdio_register(struct rtl8169_private *tp) 5046 { 5047 struct pci_dev *pdev = tp->pci_dev; 5048 struct mii_bus *new_bus; 5049 int ret; 5050 5051 new_bus = devm_mdiobus_alloc(&pdev->dev); 5052 if (!new_bus) 5053 return -ENOMEM; 5054 5055 new_bus->name = "r8169"; 5056 new_bus->priv = tp; 5057 new_bus->parent = &pdev->dev; 5058 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5059 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5060 5061 new_bus->read = r8169_mdio_read_reg; 5062 new_bus->write = r8169_mdio_write_reg; 5063 5064 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5065 if (ret) 5066 return ret; 5067 5068 tp->phydev = mdiobus_get_phy(new_bus, 0); 5069 if (!tp->phydev) { 5070 return -ENODEV; 5071 } else if (!tp->phydev->drv) { 5072 /* Most chip versions fail with the genphy driver. 5073 * Therefore ensure that the dedicated PHY driver is loaded. 5074 */ 5075 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5076 tp->phydev->phy_id); 5077 return -EUNATCH; 5078 } 5079 5080 /* PHY will be woken up in rtl_open() */ 5081 phy_suspend(tp->phydev); 5082 5083 return 0; 5084 } 5085 5086 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5087 { 5088 rtl_enable_rxdvgate(tp); 5089 5090 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5091 msleep(1); 5092 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5093 5094 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5095 r8168g_wait_ll_share_fifo_ready(tp); 5096 5097 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5098 r8168g_wait_ll_share_fifo_ready(tp); 5099 } 5100 5101 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5102 { 5103 rtl_enable_rxdvgate(tp); 5104 5105 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5106 msleep(1); 5107 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5108 5109 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5110 r8168g_wait_ll_share_fifo_ready(tp); 5111 5112 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5113 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5114 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5115 r8168g_wait_ll_share_fifo_ready(tp); 5116 } 5117 5118 static void rtl_hw_initialize(struct rtl8169_private *tp) 5119 { 5120 switch (tp->mac_version) { 5121 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 5122 rtl8168ep_stop_cmac(tp); 5123 fallthrough; 5124 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5125 rtl_hw_init_8168g(tp); 5126 break; 5127 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5128 rtl_hw_init_8125(tp); 5129 break; 5130 default: 5131 break; 5132 } 5133 } 5134 5135 static int rtl_jumbo_max(struct rtl8169_private *tp) 5136 { 5137 /* Non-GBit versions don't support jumbo frames */ 5138 if (!tp->supports_gmii) 5139 return 0; 5140 5141 switch (tp->mac_version) { 5142 /* RTL8169 */ 5143 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5144 return JUMBO_7K; 5145 /* RTL8168b */ 5146 case RTL_GIGA_MAC_VER_11: 5147 case RTL_GIGA_MAC_VER_12: 5148 case RTL_GIGA_MAC_VER_17: 5149 return JUMBO_4K; 5150 /* RTL8168c */ 5151 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5152 return JUMBO_6K; 5153 default: 5154 return JUMBO_9K; 5155 } 5156 } 5157 5158 static void rtl_disable_clk(void *data) 5159 { 5160 clk_disable_unprepare(data); 5161 } 5162 5163 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5164 { 5165 struct device *d = tp_to_dev(tp); 5166 struct clk *clk; 5167 int rc; 5168 5169 clk = devm_clk_get(d, "ether_clk"); 5170 if (IS_ERR(clk)) { 5171 rc = PTR_ERR(clk); 5172 if (rc == -ENOENT) 5173 /* clk-core allows NULL (for suspend / resume) */ 5174 rc = 0; 5175 else 5176 dev_err_probe(d, rc, "failed to get clk\n"); 5177 } else { 5178 tp->clk = clk; 5179 rc = clk_prepare_enable(clk); 5180 if (rc) 5181 dev_err(d, "failed to enable clk: %d\n", rc); 5182 else 5183 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5184 } 5185 5186 return rc; 5187 } 5188 5189 static void rtl_init_mac_address(struct rtl8169_private *tp) 5190 { 5191 struct net_device *dev = tp->dev; 5192 u8 *mac_addr = dev->dev_addr; 5193 int rc; 5194 5195 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5196 if (!rc) 5197 goto done; 5198 5199 rtl_read_mac_address(tp, mac_addr); 5200 if (is_valid_ether_addr(mac_addr)) 5201 goto done; 5202 5203 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5204 if (is_valid_ether_addr(mac_addr)) 5205 goto done; 5206 5207 eth_hw_addr_random(dev); 5208 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5209 done: 5210 rtl_rar_set(tp, mac_addr); 5211 } 5212 5213 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5214 { 5215 struct rtl8169_private *tp; 5216 int jumbo_max, region, rc; 5217 enum mac_version chipset; 5218 struct net_device *dev; 5219 u16 xid; 5220 5221 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5222 if (!dev) 5223 return -ENOMEM; 5224 5225 SET_NETDEV_DEV(dev, &pdev->dev); 5226 dev->netdev_ops = &rtl_netdev_ops; 5227 tp = netdev_priv(dev); 5228 tp->dev = dev; 5229 tp->pci_dev = pdev; 5230 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5231 tp->eee_adv = -1; 5232 tp->ocp_base = OCP_STD_PHY_BASE; 5233 5234 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5235 struct pcpu_sw_netstats); 5236 if (!dev->tstats) 5237 return -ENOMEM; 5238 5239 /* Get the *optional* external "ether_clk" used on some boards */ 5240 rc = rtl_get_ether_clk(tp); 5241 if (rc) 5242 return rc; 5243 5244 /* Disable ASPM completely as that cause random device stop working 5245 * problems as well as full system hangs for some PCIe devices users. 5246 */ 5247 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5248 PCIE_LINK_STATE_L1); 5249 tp->aspm_manageable = !rc; 5250 5251 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5252 rc = pcim_enable_device(pdev); 5253 if (rc < 0) { 5254 dev_err(&pdev->dev, "enable failure\n"); 5255 return rc; 5256 } 5257 5258 if (pcim_set_mwi(pdev) < 0) 5259 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5260 5261 /* use first MMIO region */ 5262 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5263 if (region < 0) { 5264 dev_err(&pdev->dev, "no MMIO resource found\n"); 5265 return -ENODEV; 5266 } 5267 5268 /* check for weird/broken PCI region reporting */ 5269 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5270 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5271 return -ENODEV; 5272 } 5273 5274 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5275 if (rc < 0) { 5276 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5277 return rc; 5278 } 5279 5280 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5281 5282 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5283 5284 /* Identify chip attached to board */ 5285 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5286 if (chipset == RTL_GIGA_MAC_NONE) { 5287 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5288 return -ENODEV; 5289 } 5290 5291 tp->mac_version = chipset; 5292 5293 tp->dash_type = rtl_check_dash(tp); 5294 5295 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5296 5297 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5298 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5299 dev->features |= NETIF_F_HIGHDMA; 5300 5301 rtl_init_rxcfg(tp); 5302 5303 rtl8169_irq_mask_and_ack(tp); 5304 5305 rtl_hw_initialize(tp); 5306 5307 rtl_hw_reset(tp); 5308 5309 pci_set_master(pdev); 5310 5311 rc = rtl_alloc_irq(tp); 5312 if (rc < 0) { 5313 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5314 return rc; 5315 } 5316 5317 INIT_WORK(&tp->wk.work, rtl_task); 5318 5319 rtl_init_mac_address(tp); 5320 5321 dev->ethtool_ops = &rtl8169_ethtool_ops; 5322 5323 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5324 5325 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5326 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5327 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5328 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5329 5330 /* 5331 * Pretend we are using VLANs; This bypasses a nasty bug where 5332 * Interrupts stop flowing on high load on 8110SCd controllers. 5333 */ 5334 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5335 /* Disallow toggling */ 5336 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5337 5338 if (rtl_chip_supports_csum_v2(tp)) 5339 dev->hw_features |= NETIF_F_IPV6_CSUM; 5340 5341 dev->features |= dev->hw_features; 5342 5343 /* There has been a number of reports that using SG/TSO results in 5344 * tx timeouts. However for a lot of people SG/TSO works fine. 5345 * Therefore disable both features by default, but allow users to 5346 * enable them. Use at own risk! 5347 */ 5348 if (rtl_chip_supports_csum_v2(tp)) { 5349 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5350 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5351 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5352 } else { 5353 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5354 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5355 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5356 } 5357 5358 dev->hw_features |= NETIF_F_RXALL; 5359 dev->hw_features |= NETIF_F_RXFCS; 5360 5361 /* configure chip for default features */ 5362 rtl8169_set_features(dev, dev->features); 5363 5364 rtl_set_d3_pll_down(tp, true); 5365 5366 jumbo_max = rtl_jumbo_max(tp); 5367 if (jumbo_max) 5368 dev->max_mtu = jumbo_max; 5369 5370 rtl_set_irq_mask(tp); 5371 5372 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5373 5374 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5375 &tp->counters_phys_addr, 5376 GFP_KERNEL); 5377 if (!tp->counters) 5378 return -ENOMEM; 5379 5380 pci_set_drvdata(pdev, tp); 5381 5382 rc = r8169_mdio_register(tp); 5383 if (rc) 5384 return rc; 5385 5386 rc = register_netdev(dev); 5387 if (rc) 5388 return rc; 5389 5390 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5391 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5392 pci_irq_vector(pdev, 0)); 5393 5394 if (jumbo_max) 5395 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5396 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5397 "ok" : "ko"); 5398 5399 if (tp->dash_type != RTL_DASH_NONE) { 5400 netdev_info(dev, "DASH enabled\n"); 5401 rtl8168_driver_start(tp); 5402 } 5403 5404 if (pci_dev_run_wake(pdev)) 5405 pm_runtime_put_sync(&pdev->dev); 5406 5407 return 0; 5408 } 5409 5410 static struct pci_driver rtl8169_pci_driver = { 5411 .name = MODULENAME, 5412 .id_table = rtl8169_pci_tbl, 5413 .probe = rtl_init_one, 5414 .remove = rtl_remove_one, 5415 .shutdown = rtl_shutdown, 5416 #ifdef CONFIG_PM 5417 .driver.pm = &rtl8169_pm_ops, 5418 #endif 5419 }; 5420 5421 module_pci_driver(rtl8169_pci_driver); 5422