1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <net/ip6_checksum.h> 32 33 #include "r8169.h" 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 58 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 59 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 60 61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 63 #define MC_FILTER_LIMIT 32 64 65 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 66 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 67 68 #define R8169_REGS_SIZE 256 69 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 70 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 71 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 72 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 73 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 74 75 #define OCP_STD_PHY_BASE 0xa400 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92 static const struct { 93 const char *name; 94 const char *fw_name; 95 } rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 110 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 111 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 112 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 113 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 119 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 121 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 122 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 125 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 127 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 128 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 129 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 130 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 131 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 132 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 133 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 134 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 135 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 136 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 137 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 138 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 139 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 140 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 141 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 142 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 143 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 144 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 145 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 148 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 149 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 150 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 151 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 152 }; 153 154 static const struct pci_device_id rtl8169_pci_tbl[] = { 155 { PCI_VDEVICE(REALTEK, 0x2502) }, 156 { PCI_VDEVICE(REALTEK, 0x2600) }, 157 { PCI_VDEVICE(REALTEK, 0x8129) }, 158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 159 { PCI_VDEVICE(REALTEK, 0x8161) }, 160 { PCI_VDEVICE(REALTEK, 0x8167) }, 161 { PCI_VDEVICE(REALTEK, 0x8168) }, 162 { PCI_VDEVICE(NCUBE, 0x8168) }, 163 { PCI_VDEVICE(REALTEK, 0x8169) }, 164 { PCI_VENDOR_ID_DLINK, 0x4300, 165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 166 { PCI_VDEVICE(DLINK, 0x4300) }, 167 { PCI_VDEVICE(DLINK, 0x4302) }, 168 { PCI_VDEVICE(AT, 0xc107) }, 169 { PCI_VDEVICE(USR, 0x0116) }, 170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 172 { PCI_VDEVICE(REALTEK, 0x8125) }, 173 { PCI_VDEVICE(REALTEK, 0x3000) }, 174 {} 175 }; 176 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 178 179 enum rtl_registers { 180 MAC0 = 0, /* Ethernet hardware address. */ 181 MAC4 = 4, 182 MAR0 = 8, /* Multicast filter. */ 183 CounterAddrLow = 0x10, 184 CounterAddrHigh = 0x14, 185 TxDescStartAddrLow = 0x20, 186 TxDescStartAddrHigh = 0x24, 187 TxHDescStartAddrLow = 0x28, 188 TxHDescStartAddrHigh = 0x2c, 189 FLASH = 0x30, 190 ERSR = 0x36, 191 ChipCmd = 0x37, 192 TxPoll = 0x38, 193 IntrMask = 0x3c, 194 IntrStatus = 0x3e, 195 196 TxConfig = 0x40, 197 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 198 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 199 200 RxConfig = 0x44, 201 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 202 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 203 #define RXCFG_FIFO_SHIFT 13 204 /* No threshold before first PCI xfer */ 205 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 206 #define RX_EARLY_OFF (1 << 11) 207 #define RXCFG_DMA_SHIFT 8 208 /* Unlimited maximum PCI burst. */ 209 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 210 211 Cfg9346 = 0x50, 212 Config0 = 0x51, 213 Config1 = 0x52, 214 Config2 = 0x53, 215 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 216 217 Config3 = 0x54, 218 Config4 = 0x55, 219 Config5 = 0x56, 220 PHYAR = 0x60, 221 PHYstatus = 0x6c, 222 RxMaxSize = 0xda, 223 CPlusCmd = 0xe0, 224 IntrMitigate = 0xe2, 225 226 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 227 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 228 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 229 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 230 231 #define RTL_COALESCE_T_MAX 0x0fU 232 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 233 234 RxDescAddrLow = 0xe4, 235 RxDescAddrHigh = 0xe8, 236 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 237 238 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 239 240 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 241 242 #define TxPacketMax (8064 >> 7) 243 #define EarlySize 0x27 244 245 FuncEvent = 0xf0, 246 FuncEventMask = 0xf4, 247 FuncPresetState = 0xf8, 248 IBCR0 = 0xf8, 249 IBCR2 = 0xf9, 250 IBIMR0 = 0xfa, 251 IBISR0 = 0xfb, 252 FuncForceEvent = 0xfc, 253 }; 254 255 enum rtl8168_8101_registers { 256 CSIDR = 0x64, 257 CSIAR = 0x68, 258 #define CSIAR_FLAG 0x80000000 259 #define CSIAR_WRITE_CMD 0x80000000 260 #define CSIAR_BYTE_ENABLE 0x0000f000 261 #define CSIAR_ADDR_MASK 0x00000fff 262 PMCH = 0x6f, 263 EPHYAR = 0x80, 264 #define EPHYAR_FLAG 0x80000000 265 #define EPHYAR_WRITE_CMD 0x80000000 266 #define EPHYAR_REG_MASK 0x1f 267 #define EPHYAR_REG_SHIFT 16 268 #define EPHYAR_DATA_MASK 0xffff 269 DLLPR = 0xd0, 270 #define PFM_EN (1 << 6) 271 #define TX_10M_PS_EN (1 << 7) 272 DBG_REG = 0xd1, 273 #define FIX_NAK_1 (1 << 4) 274 #define FIX_NAK_2 (1 << 3) 275 TWSI = 0xd2, 276 MCU = 0xd3, 277 #define NOW_IS_OOB (1 << 7) 278 #define TX_EMPTY (1 << 5) 279 #define RX_EMPTY (1 << 4) 280 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 281 #define EN_NDP (1 << 3) 282 #define EN_OOB_RESET (1 << 2) 283 #define LINK_LIST_RDY (1 << 1) 284 EFUSEAR = 0xdc, 285 #define EFUSEAR_FLAG 0x80000000 286 #define EFUSEAR_WRITE_CMD 0x80000000 287 #define EFUSEAR_READ_CMD 0x00000000 288 #define EFUSEAR_REG_MASK 0x03ff 289 #define EFUSEAR_REG_SHIFT 8 290 #define EFUSEAR_DATA_MASK 0xff 291 MISC_1 = 0xf2, 292 #define PFM_D3COLD_EN (1 << 6) 293 }; 294 295 enum rtl8168_registers { 296 LED_FREQ = 0x1a, 297 EEE_LED = 0x1b, 298 ERIDR = 0x70, 299 ERIAR = 0x74, 300 #define ERIAR_FLAG 0x80000000 301 #define ERIAR_WRITE_CMD 0x80000000 302 #define ERIAR_READ_CMD 0x00000000 303 #define ERIAR_ADDR_BYTE_ALIGN 4 304 #define ERIAR_TYPE_SHIFT 16 305 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_MASK_SHIFT 12 310 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 315 EPHY_RXER_NUM = 0x7c, 316 OCPDR = 0xb0, /* OCP GPHY access */ 317 #define OCPDR_WRITE_CMD 0x80000000 318 #define OCPDR_READ_CMD 0x00000000 319 #define OCPDR_REG_MASK 0x7f 320 #define OCPDR_GPHY_REG_SHIFT 16 321 #define OCPDR_DATA_MASK 0xffff 322 OCPAR = 0xb4, 323 #define OCPAR_FLAG 0x80000000 324 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 325 #define OCPAR_GPHY_READ_CMD 0x0000f060 326 GPHY_OCP = 0xb8, 327 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 328 MISC = 0xf0, /* 8168e only. */ 329 #define TXPLA_RST (1 << 29) 330 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 331 #define PWM_EN (1 << 22) 332 #define RXDV_GATED_EN (1 << 19) 333 #define EARLY_TALLY_EN (1 << 16) 334 }; 335 336 enum rtl8125_registers { 337 IntrMask_8125 = 0x38, 338 IntrStatus_8125 = 0x3c, 339 TxPoll_8125 = 0x90, 340 MAC0_BKP = 0x19e0, 341 EEE_TXIDLE_TIMER_8125 = 0x6048, 342 }; 343 344 #define RX_VLAN_INNER_8125 BIT(22) 345 #define RX_VLAN_OUTER_8125 BIT(23) 346 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 347 348 #define RX_FETCH_DFLT_8125 (8 << 27) 349 350 enum rtl_register_content { 351 /* InterruptStatusBits */ 352 SYSErr = 0x8000, 353 PCSTimeout = 0x4000, 354 SWInt = 0x0100, 355 TxDescUnavail = 0x0080, 356 RxFIFOOver = 0x0040, 357 LinkChg = 0x0020, 358 RxOverflow = 0x0010, 359 TxErr = 0x0008, 360 TxOK = 0x0004, 361 RxErr = 0x0002, 362 RxOK = 0x0001, 363 364 /* RxStatusDesc */ 365 RxRWT = (1 << 22), 366 RxRES = (1 << 21), 367 RxRUNT = (1 << 20), 368 RxCRC = (1 << 19), 369 370 /* ChipCmdBits */ 371 StopReq = 0x80, 372 CmdReset = 0x10, 373 CmdRxEnb = 0x08, 374 CmdTxEnb = 0x04, 375 RxBufEmpty = 0x01, 376 377 /* TXPoll register p.5 */ 378 HPQ = 0x80, /* Poll cmd on the high prio queue */ 379 NPQ = 0x40, /* Poll cmd on the low prio queue */ 380 FSWInt = 0x01, /* Forced software interrupt */ 381 382 /* Cfg9346Bits */ 383 Cfg9346_Lock = 0x00, 384 Cfg9346_Unlock = 0xc0, 385 386 /* rx_mode_bits */ 387 AcceptErr = 0x20, 388 AcceptRunt = 0x10, 389 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 390 AcceptBroadcast = 0x08, 391 AcceptMulticast = 0x04, 392 AcceptMyPhys = 0x02, 393 AcceptAllPhys = 0x01, 394 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 395 #define RX_CONFIG_ACCEPT_MASK 0x3f 396 397 /* TxConfigBits */ 398 TxInterFrameGapShift = 24, 399 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 400 401 /* Config1 register p.24 */ 402 LEDS1 = (1 << 7), 403 LEDS0 = (1 << 6), 404 Speed_down = (1 << 4), 405 MEMMAP = (1 << 3), 406 IOMAP = (1 << 2), 407 VPD = (1 << 1), 408 PMEnable = (1 << 0), /* Power Management Enable */ 409 410 /* Config2 register p. 25 */ 411 ClkReqEn = (1 << 7), /* Clock Request Enable */ 412 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 413 PCI_Clock_66MHz = 0x01, 414 PCI_Clock_33MHz = 0x00, 415 416 /* Config3 register p.25 */ 417 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 418 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 419 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 420 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 421 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 422 423 /* Config4 register */ 424 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 425 426 /* Config5 register p.27 */ 427 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 428 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 429 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 430 Spi_en = (1 << 3), 431 LanWake = (1 << 1), /* LanWake enable/disable */ 432 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 433 ASPM_en = (1 << 0), /* ASPM enable */ 434 435 /* CPlusCmd p.31 */ 436 EnableBist = (1 << 15), // 8168 8101 437 Mac_dbgo_oe = (1 << 14), // 8168 8101 438 EnAnaPLL = (1 << 14), // 8169 439 Normal_mode = (1 << 13), // unused 440 Force_half_dup = (1 << 12), // 8168 8101 441 Force_rxflow_en = (1 << 11), // 8168 8101 442 Force_txflow_en = (1 << 10), // 8168 8101 443 Cxpl_dbg_sel = (1 << 9), // 8168 8101 444 ASF = (1 << 8), // 8168 8101 445 PktCntrDisable = (1 << 7), // 8168 8101 446 Mac_dbgo_sel = 0x001c, // 8168 447 RxVlan = (1 << 6), 448 RxChkSum = (1 << 5), 449 PCIDAC = (1 << 4), 450 PCIMulRW = (1 << 3), 451 #define INTT_MASK GENMASK(1, 0) 452 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 453 454 /* rtl8169_PHYstatus */ 455 TBI_Enable = 0x80, 456 TxFlowCtrl = 0x40, 457 RxFlowCtrl = 0x20, 458 _1000bpsF = 0x10, 459 _100bps = 0x08, 460 _10bps = 0x04, 461 LinkStatus = 0x02, 462 FullDup = 0x01, 463 464 /* ResetCounterCommand */ 465 CounterReset = 0x1, 466 467 /* DumpCounterCommand */ 468 CounterDump = 0x8, 469 470 /* magic enable v2 */ 471 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 472 }; 473 474 enum rtl_desc_bit { 475 /* First doubleword. */ 476 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 477 RingEnd = (1 << 30), /* End of descriptor ring */ 478 FirstFrag = (1 << 29), /* First segment of a packet */ 479 LastFrag = (1 << 28), /* Final segment of a packet */ 480 }; 481 482 /* Generic case. */ 483 enum rtl_tx_desc_bit { 484 /* First doubleword. */ 485 TD_LSO = (1 << 27), /* Large Send Offload */ 486 #define TD_MSS_MAX 0x07ffu /* MSS value */ 487 488 /* Second doubleword. */ 489 TxVlanTag = (1 << 17), /* Add VLAN tag */ 490 }; 491 492 /* 8169, 8168b and 810x except 8102e. */ 493 enum rtl_tx_desc_bit_0 { 494 /* First doubleword. */ 495 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 496 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 497 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 498 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 499 }; 500 501 /* 8102e, 8168c and beyond. */ 502 enum rtl_tx_desc_bit_1 { 503 /* First doubleword. */ 504 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 505 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 506 #define GTTCPHO_SHIFT 18 507 #define GTTCPHO_MAX 0x7f 508 509 /* Second doubleword. */ 510 #define TCPHO_SHIFT 18 511 #define TCPHO_MAX 0x3ff 512 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 513 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 514 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 515 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 516 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 517 }; 518 519 enum rtl_rx_desc_bit { 520 /* Rx private */ 521 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 522 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 523 524 #define RxProtoUDP (PID1) 525 #define RxProtoTCP (PID0) 526 #define RxProtoIP (PID1 | PID0) 527 #define RxProtoMask RxProtoIP 528 529 IPFail = (1 << 16), /* IP checksum failed */ 530 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 531 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 532 RxVlanTag = (1 << 16), /* VLAN tag available */ 533 }; 534 535 #define RTL_GSO_MAX_SIZE_V1 32000 536 #define RTL_GSO_MAX_SEGS_V1 24 537 #define RTL_GSO_MAX_SIZE_V2 64000 538 #define RTL_GSO_MAX_SEGS_V2 64 539 540 struct TxDesc { 541 __le32 opts1; 542 __le32 opts2; 543 __le64 addr; 544 }; 545 546 struct RxDesc { 547 __le32 opts1; 548 __le32 opts2; 549 __le64 addr; 550 }; 551 552 struct ring_info { 553 struct sk_buff *skb; 554 u32 len; 555 }; 556 557 struct rtl8169_counters { 558 __le64 tx_packets; 559 __le64 rx_packets; 560 __le64 tx_errors; 561 __le32 rx_errors; 562 __le16 rx_missed; 563 __le16 align_errors; 564 __le32 tx_one_collision; 565 __le32 tx_multi_collision; 566 __le64 rx_unicast; 567 __le64 rx_broadcast; 568 __le32 rx_multicast; 569 __le16 tx_aborted; 570 __le16 tx_underun; 571 }; 572 573 struct rtl8169_tc_offsets { 574 bool inited; 575 __le64 tx_errors; 576 __le32 tx_multi_collision; 577 __le16 tx_aborted; 578 __le16 rx_missed; 579 }; 580 581 enum rtl_flag { 582 RTL_FLAG_TASK_ENABLED = 0, 583 RTL_FLAG_TASK_RESET_PENDING, 584 RTL_FLAG_MAX 585 }; 586 587 struct rtl8169_stats { 588 u64 packets; 589 u64 bytes; 590 struct u64_stats_sync syncp; 591 }; 592 593 struct rtl8169_private { 594 void __iomem *mmio_addr; /* memory map physical address */ 595 struct pci_dev *pci_dev; 596 struct net_device *dev; 597 struct phy_device *phydev; 598 struct napi_struct napi; 599 enum mac_version mac_version; 600 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 601 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 602 u32 dirty_tx; 603 struct rtl8169_stats rx_stats; 604 struct rtl8169_stats tx_stats; 605 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 606 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 607 dma_addr_t TxPhyAddr; 608 dma_addr_t RxPhyAddr; 609 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 610 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 611 u16 cp_cmd; 612 u32 irq_mask; 613 struct clk *clk; 614 615 struct { 616 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 617 struct work_struct work; 618 } wk; 619 620 unsigned supports_gmii:1; 621 unsigned aspm_manageable:1; 622 dma_addr_t counters_phys_addr; 623 struct rtl8169_counters *counters; 624 struct rtl8169_tc_offsets tc_offset; 625 u32 saved_wolopts; 626 int eee_adv; 627 628 const char *fw_name; 629 struct rtl_fw *rtl_fw; 630 631 u32 ocp_base; 632 }; 633 634 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 635 636 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 637 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 638 MODULE_SOFTDEP("pre: realtek"); 639 MODULE_LICENSE("GPL"); 640 MODULE_FIRMWARE(FIRMWARE_8168D_1); 641 MODULE_FIRMWARE(FIRMWARE_8168D_2); 642 MODULE_FIRMWARE(FIRMWARE_8168E_1); 643 MODULE_FIRMWARE(FIRMWARE_8168E_2); 644 MODULE_FIRMWARE(FIRMWARE_8168E_3); 645 MODULE_FIRMWARE(FIRMWARE_8105E_1); 646 MODULE_FIRMWARE(FIRMWARE_8168F_1); 647 MODULE_FIRMWARE(FIRMWARE_8168F_2); 648 MODULE_FIRMWARE(FIRMWARE_8402_1); 649 MODULE_FIRMWARE(FIRMWARE_8411_1); 650 MODULE_FIRMWARE(FIRMWARE_8411_2); 651 MODULE_FIRMWARE(FIRMWARE_8106E_1); 652 MODULE_FIRMWARE(FIRMWARE_8106E_2); 653 MODULE_FIRMWARE(FIRMWARE_8168G_2); 654 MODULE_FIRMWARE(FIRMWARE_8168G_3); 655 MODULE_FIRMWARE(FIRMWARE_8168H_1); 656 MODULE_FIRMWARE(FIRMWARE_8168H_2); 657 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 658 MODULE_FIRMWARE(FIRMWARE_8107E_1); 659 MODULE_FIRMWARE(FIRMWARE_8107E_2); 660 MODULE_FIRMWARE(FIRMWARE_8125A_3); 661 MODULE_FIRMWARE(FIRMWARE_8125B_2); 662 663 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 664 { 665 return &tp->pci_dev->dev; 666 } 667 668 static void rtl_lock_config_regs(struct rtl8169_private *tp) 669 { 670 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 671 } 672 673 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 674 { 675 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 676 } 677 678 static void rtl_pci_commit(struct rtl8169_private *tp) 679 { 680 /* Read an arbitrary register to commit a preceding PCI write */ 681 RTL_R8(tp, ChipCmd); 682 } 683 684 static bool rtl_is_8125(struct rtl8169_private *tp) 685 { 686 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 687 } 688 689 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 690 { 691 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 692 tp->mac_version != RTL_GIGA_MAC_VER_39 && 693 tp->mac_version <= RTL_GIGA_MAC_VER_52; 694 } 695 696 static bool rtl_supports_eee(struct rtl8169_private *tp) 697 { 698 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 699 tp->mac_version != RTL_GIGA_MAC_VER_37 && 700 tp->mac_version != RTL_GIGA_MAC_VER_39; 701 } 702 703 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 704 { 705 int i; 706 707 for (i = 0; i < ETH_ALEN; i++) 708 mac[i] = RTL_R8(tp, reg + i); 709 } 710 711 struct rtl_cond { 712 bool (*check)(struct rtl8169_private *); 713 const char *msg; 714 }; 715 716 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 717 unsigned long usecs, int n, bool high) 718 { 719 int i; 720 721 for (i = 0; i < n; i++) { 722 if (c->check(tp) == high) 723 return true; 724 fsleep(usecs); 725 } 726 727 if (net_ratelimit()) 728 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 729 c->msg, !high, n, usecs); 730 return false; 731 } 732 733 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 734 const struct rtl_cond *c, 735 unsigned long d, int n) 736 { 737 return rtl_loop_wait(tp, c, d, n, true); 738 } 739 740 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 741 const struct rtl_cond *c, 742 unsigned long d, int n) 743 { 744 return rtl_loop_wait(tp, c, d, n, false); 745 } 746 747 #define DECLARE_RTL_COND(name) \ 748 static bool name ## _check(struct rtl8169_private *); \ 749 \ 750 static const struct rtl_cond name = { \ 751 .check = name ## _check, \ 752 .msg = #name \ 753 }; \ 754 \ 755 static bool name ## _check(struct rtl8169_private *tp) 756 757 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 758 { 759 if (reg & 0xffff0001) { 760 if (net_ratelimit()) 761 netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg); 762 return true; 763 } 764 return false; 765 } 766 767 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 768 { 769 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 770 } 771 772 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 773 { 774 if (rtl_ocp_reg_failure(tp, reg)) 775 return; 776 777 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 778 779 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 780 } 781 782 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 783 { 784 if (rtl_ocp_reg_failure(tp, reg)) 785 return 0; 786 787 RTL_W32(tp, GPHY_OCP, reg << 15); 788 789 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 790 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 791 } 792 793 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 794 { 795 if (rtl_ocp_reg_failure(tp, reg)) 796 return; 797 798 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 799 } 800 801 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 802 { 803 if (rtl_ocp_reg_failure(tp, reg)) 804 return 0; 805 806 RTL_W32(tp, OCPDR, reg << 15); 807 808 return RTL_R32(tp, OCPDR); 809 } 810 811 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 812 u16 set) 813 { 814 u16 data = r8168_mac_ocp_read(tp, reg); 815 816 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 817 } 818 819 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 820 { 821 if (reg == 0x1f) { 822 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 823 return; 824 } 825 826 if (tp->ocp_base != OCP_STD_PHY_BASE) 827 reg -= 0x10; 828 829 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 830 } 831 832 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 833 { 834 if (reg == 0x1f) 835 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 836 837 if (tp->ocp_base != OCP_STD_PHY_BASE) 838 reg -= 0x10; 839 840 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 841 } 842 843 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 844 { 845 if (reg == 0x1f) { 846 tp->ocp_base = value << 4; 847 return; 848 } 849 850 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 851 } 852 853 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 854 { 855 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 856 } 857 858 DECLARE_RTL_COND(rtl_phyar_cond) 859 { 860 return RTL_R32(tp, PHYAR) & 0x80000000; 861 } 862 863 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 864 { 865 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 866 867 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 868 /* 869 * According to hardware specs a 20us delay is required after write 870 * complete indication, but before sending next command. 871 */ 872 udelay(20); 873 } 874 875 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 876 { 877 int value; 878 879 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 880 881 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 882 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 883 884 /* 885 * According to hardware specs a 20us delay is required after read 886 * complete indication, but before sending next command. 887 */ 888 udelay(20); 889 890 return value; 891 } 892 893 DECLARE_RTL_COND(rtl_ocpar_cond) 894 { 895 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 896 } 897 898 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 899 { 900 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 901 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 902 RTL_W32(tp, EPHY_RXER_NUM, 0); 903 904 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 905 } 906 907 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 908 { 909 r8168dp_1_mdio_access(tp, reg, 910 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 911 } 912 913 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 914 { 915 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 916 917 mdelay(1); 918 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 919 RTL_W32(tp, EPHY_RXER_NUM, 0); 920 921 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 922 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 923 } 924 925 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 926 927 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 928 { 929 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 930 } 931 932 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 933 { 934 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 935 } 936 937 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 938 { 939 r8168dp_2_mdio_start(tp); 940 941 r8169_mdio_write(tp, reg, value); 942 943 r8168dp_2_mdio_stop(tp); 944 } 945 946 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 947 { 948 int value; 949 950 /* Work around issue with chip reporting wrong PHY ID */ 951 if (reg == MII_PHYSID2) 952 return 0xc912; 953 954 r8168dp_2_mdio_start(tp); 955 956 value = r8169_mdio_read(tp, reg); 957 958 r8168dp_2_mdio_stop(tp); 959 960 return value; 961 } 962 963 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 964 { 965 switch (tp->mac_version) { 966 case RTL_GIGA_MAC_VER_27: 967 r8168dp_1_mdio_write(tp, location, val); 968 break; 969 case RTL_GIGA_MAC_VER_28: 970 case RTL_GIGA_MAC_VER_31: 971 r8168dp_2_mdio_write(tp, location, val); 972 break; 973 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 974 r8168g_mdio_write(tp, location, val); 975 break; 976 default: 977 r8169_mdio_write(tp, location, val); 978 break; 979 } 980 } 981 982 static int rtl_readphy(struct rtl8169_private *tp, int location) 983 { 984 switch (tp->mac_version) { 985 case RTL_GIGA_MAC_VER_27: 986 return r8168dp_1_mdio_read(tp, location); 987 case RTL_GIGA_MAC_VER_28: 988 case RTL_GIGA_MAC_VER_31: 989 return r8168dp_2_mdio_read(tp, location); 990 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 991 return r8168g_mdio_read(tp, location); 992 default: 993 return r8169_mdio_read(tp, location); 994 } 995 } 996 997 DECLARE_RTL_COND(rtl_ephyar_cond) 998 { 999 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1000 } 1001 1002 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1003 { 1004 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1005 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1006 1007 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1008 1009 udelay(10); 1010 } 1011 1012 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1013 { 1014 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1015 1016 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1017 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1018 } 1019 1020 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 1021 { 1022 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 1023 if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB) 1024 *cmd |= 0x7f0 << 18; 1025 } 1026 1027 DECLARE_RTL_COND(rtl_eriar_cond) 1028 { 1029 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1030 } 1031 1032 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1033 u32 val, int type) 1034 { 1035 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 1036 1037 BUG_ON((addr & 3) || (mask == 0)); 1038 RTL_W32(tp, ERIDR, val); 1039 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1040 RTL_W32(tp, ERIAR, cmd); 1041 1042 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1043 } 1044 1045 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1046 u32 val) 1047 { 1048 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1049 } 1050 1051 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1052 { 1053 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 1054 1055 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1056 RTL_W32(tp, ERIAR, cmd); 1057 1058 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1059 RTL_R32(tp, ERIDR) : ~0; 1060 } 1061 1062 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1063 { 1064 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1065 } 1066 1067 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 1068 { 1069 u32 val = rtl_eri_read(tp, addr); 1070 1071 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1072 } 1073 1074 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1075 { 1076 rtl_w0w1_eri(tp, addr, p, 0); 1077 } 1078 1079 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1080 { 1081 rtl_w0w1_eri(tp, addr, 0, m); 1082 } 1083 1084 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1085 { 1086 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1087 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1088 RTL_R32(tp, OCPDR) : ~0; 1089 } 1090 1091 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1092 { 1093 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1094 } 1095 1096 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1097 u32 data) 1098 { 1099 RTL_W32(tp, OCPDR, data); 1100 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1101 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1102 } 1103 1104 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1105 u32 data) 1106 { 1107 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1108 data, ERIAR_OOB); 1109 } 1110 1111 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1112 { 1113 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1114 1115 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1116 } 1117 1118 #define OOB_CMD_RESET 0x00 1119 #define OOB_CMD_DRIVER_START 0x05 1120 #define OOB_CMD_DRIVER_STOP 0x06 1121 1122 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1123 { 1124 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1125 } 1126 1127 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1128 { 1129 u16 reg; 1130 1131 reg = rtl8168_get_ocp_reg(tp); 1132 1133 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1134 } 1135 1136 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1137 { 1138 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1139 } 1140 1141 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1142 { 1143 return RTL_R8(tp, IBISR0) & 0x20; 1144 } 1145 1146 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1147 { 1148 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1149 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1150 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1151 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1152 } 1153 1154 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1155 { 1156 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1157 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1158 } 1159 1160 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1161 { 1162 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1163 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1164 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1165 } 1166 1167 static void rtl8168_driver_start(struct rtl8169_private *tp) 1168 { 1169 switch (tp->mac_version) { 1170 case RTL_GIGA_MAC_VER_27: 1171 case RTL_GIGA_MAC_VER_28: 1172 case RTL_GIGA_MAC_VER_31: 1173 rtl8168dp_driver_start(tp); 1174 break; 1175 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1176 rtl8168ep_driver_start(tp); 1177 break; 1178 default: 1179 BUG(); 1180 break; 1181 } 1182 } 1183 1184 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1185 { 1186 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1187 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1188 } 1189 1190 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1191 { 1192 rtl8168ep_stop_cmac(tp); 1193 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1194 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1195 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1196 } 1197 1198 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1199 { 1200 switch (tp->mac_version) { 1201 case RTL_GIGA_MAC_VER_27: 1202 case RTL_GIGA_MAC_VER_28: 1203 case RTL_GIGA_MAC_VER_31: 1204 rtl8168dp_driver_stop(tp); 1205 break; 1206 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1207 rtl8168ep_driver_stop(tp); 1208 break; 1209 default: 1210 BUG(); 1211 break; 1212 } 1213 } 1214 1215 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1216 { 1217 u16 reg = rtl8168_get_ocp_reg(tp); 1218 1219 return !!(r8168dp_ocp_read(tp, reg) & 0x00008000); 1220 } 1221 1222 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1223 { 1224 return r8168ep_ocp_read(tp, 0x128) & 0x00000001; 1225 } 1226 1227 static bool r8168_check_dash(struct rtl8169_private *tp) 1228 { 1229 switch (tp->mac_version) { 1230 case RTL_GIGA_MAC_VER_27: 1231 case RTL_GIGA_MAC_VER_28: 1232 case RTL_GIGA_MAC_VER_31: 1233 return r8168dp_check_dash(tp); 1234 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1235 return r8168ep_check_dash(tp); 1236 default: 1237 return false; 1238 } 1239 } 1240 1241 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1242 { 1243 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1244 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1245 } 1246 1247 DECLARE_RTL_COND(rtl_efusear_cond) 1248 { 1249 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1250 } 1251 1252 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1253 { 1254 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1255 1256 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1257 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1258 } 1259 1260 static u32 rtl_get_events(struct rtl8169_private *tp) 1261 { 1262 if (rtl_is_8125(tp)) 1263 return RTL_R32(tp, IntrStatus_8125); 1264 else 1265 return RTL_R16(tp, IntrStatus); 1266 } 1267 1268 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1269 { 1270 if (rtl_is_8125(tp)) 1271 RTL_W32(tp, IntrStatus_8125, bits); 1272 else 1273 RTL_W16(tp, IntrStatus, bits); 1274 } 1275 1276 static void rtl_irq_disable(struct rtl8169_private *tp) 1277 { 1278 if (rtl_is_8125(tp)) 1279 RTL_W32(tp, IntrMask_8125, 0); 1280 else 1281 RTL_W16(tp, IntrMask, 0); 1282 } 1283 1284 static void rtl_irq_enable(struct rtl8169_private *tp) 1285 { 1286 if (rtl_is_8125(tp)) 1287 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1288 else 1289 RTL_W16(tp, IntrMask, tp->irq_mask); 1290 } 1291 1292 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1293 { 1294 rtl_irq_disable(tp); 1295 rtl_ack_events(tp, 0xffffffff); 1296 rtl_pci_commit(tp); 1297 } 1298 1299 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1300 { 1301 struct phy_device *phydev = tp->phydev; 1302 1303 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1304 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1305 if (phydev->speed == SPEED_1000) { 1306 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1307 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1308 } else if (phydev->speed == SPEED_100) { 1309 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1310 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1311 } else { 1312 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1313 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1314 } 1315 rtl_reset_packet_filter(tp); 1316 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1317 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1318 if (phydev->speed == SPEED_1000) { 1319 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1320 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1321 } else { 1322 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1323 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1324 } 1325 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1326 if (phydev->speed == SPEED_10) { 1327 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1328 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1329 } else { 1330 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1331 } 1332 } 1333 } 1334 1335 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1336 1337 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1338 { 1339 struct rtl8169_private *tp = netdev_priv(dev); 1340 1341 wol->supported = WAKE_ANY; 1342 wol->wolopts = tp->saved_wolopts; 1343 } 1344 1345 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1346 { 1347 static const struct { 1348 u32 opt; 1349 u16 reg; 1350 u8 mask; 1351 } cfg[] = { 1352 { WAKE_PHY, Config3, LinkUp }, 1353 { WAKE_UCAST, Config5, UWF }, 1354 { WAKE_BCAST, Config5, BWF }, 1355 { WAKE_MCAST, Config5, MWF }, 1356 { WAKE_ANY, Config5, LanWake }, 1357 { WAKE_MAGIC, Config3, MagicPacket } 1358 }; 1359 unsigned int i, tmp = ARRAY_SIZE(cfg); 1360 u8 options; 1361 1362 rtl_unlock_config_regs(tp); 1363 1364 if (rtl_is_8168evl_up(tp)) { 1365 tmp--; 1366 if (wolopts & WAKE_MAGIC) 1367 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1368 else 1369 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1370 } else if (rtl_is_8125(tp)) { 1371 tmp--; 1372 if (wolopts & WAKE_MAGIC) 1373 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1374 else 1375 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1376 } 1377 1378 for (i = 0; i < tmp; i++) { 1379 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1380 if (wolopts & cfg[i].opt) 1381 options |= cfg[i].mask; 1382 RTL_W8(tp, cfg[i].reg, options); 1383 } 1384 1385 switch (tp->mac_version) { 1386 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1387 options = RTL_R8(tp, Config1) & ~PMEnable; 1388 if (wolopts) 1389 options |= PMEnable; 1390 RTL_W8(tp, Config1, options); 1391 break; 1392 case RTL_GIGA_MAC_VER_34: 1393 case RTL_GIGA_MAC_VER_37: 1394 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1395 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1396 if (wolopts) 1397 options |= PME_SIGNAL; 1398 RTL_W8(tp, Config2, options); 1399 break; 1400 default: 1401 break; 1402 } 1403 1404 rtl_lock_config_regs(tp); 1405 1406 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1407 tp->dev->wol_enabled = wolopts ? 1 : 0; 1408 } 1409 1410 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1411 { 1412 struct rtl8169_private *tp = netdev_priv(dev); 1413 1414 if (wol->wolopts & ~WAKE_ANY) 1415 return -EINVAL; 1416 1417 tp->saved_wolopts = wol->wolopts; 1418 __rtl8169_set_wol(tp, tp->saved_wolopts); 1419 1420 return 0; 1421 } 1422 1423 static void rtl8169_get_drvinfo(struct net_device *dev, 1424 struct ethtool_drvinfo *info) 1425 { 1426 struct rtl8169_private *tp = netdev_priv(dev); 1427 struct rtl_fw *rtl_fw = tp->rtl_fw; 1428 1429 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1430 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1431 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1432 if (rtl_fw) 1433 strlcpy(info->fw_version, rtl_fw->version, 1434 sizeof(info->fw_version)); 1435 } 1436 1437 static int rtl8169_get_regs_len(struct net_device *dev) 1438 { 1439 return R8169_REGS_SIZE; 1440 } 1441 1442 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1443 netdev_features_t features) 1444 { 1445 struct rtl8169_private *tp = netdev_priv(dev); 1446 1447 if (dev->mtu > TD_MSS_MAX) 1448 features &= ~NETIF_F_ALL_TSO; 1449 1450 if (dev->mtu > ETH_DATA_LEN && 1451 tp->mac_version > RTL_GIGA_MAC_VER_06) 1452 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1453 1454 return features; 1455 } 1456 1457 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1458 netdev_features_t features) 1459 { 1460 u32 rx_config = RTL_R32(tp, RxConfig); 1461 1462 if (features & NETIF_F_RXALL) 1463 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1464 else 1465 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1466 1467 if (rtl_is_8125(tp)) { 1468 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1469 rx_config |= RX_VLAN_8125; 1470 else 1471 rx_config &= ~RX_VLAN_8125; 1472 } 1473 1474 RTL_W32(tp, RxConfig, rx_config); 1475 } 1476 1477 static int rtl8169_set_features(struct net_device *dev, 1478 netdev_features_t features) 1479 { 1480 struct rtl8169_private *tp = netdev_priv(dev); 1481 1482 rtl_set_rx_config_features(tp, features); 1483 1484 if (features & NETIF_F_RXCSUM) 1485 tp->cp_cmd |= RxChkSum; 1486 else 1487 tp->cp_cmd &= ~RxChkSum; 1488 1489 if (!rtl_is_8125(tp)) { 1490 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1491 tp->cp_cmd |= RxVlan; 1492 else 1493 tp->cp_cmd &= ~RxVlan; 1494 } 1495 1496 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1497 rtl_pci_commit(tp); 1498 1499 return 0; 1500 } 1501 1502 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1503 { 1504 return (skb_vlan_tag_present(skb)) ? 1505 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1506 } 1507 1508 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1509 { 1510 u32 opts2 = le32_to_cpu(desc->opts2); 1511 1512 if (opts2 & RxVlanTag) 1513 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1514 } 1515 1516 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1517 void *p) 1518 { 1519 struct rtl8169_private *tp = netdev_priv(dev); 1520 u32 __iomem *data = tp->mmio_addr; 1521 u32 *dw = p; 1522 int i; 1523 1524 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1525 memcpy_fromio(dw++, data++, 4); 1526 } 1527 1528 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1529 "tx_packets", 1530 "rx_packets", 1531 "tx_errors", 1532 "rx_errors", 1533 "rx_missed", 1534 "align_errors", 1535 "tx_single_collisions", 1536 "tx_multi_collisions", 1537 "unicast", 1538 "broadcast", 1539 "multicast", 1540 "tx_aborted", 1541 "tx_underrun", 1542 }; 1543 1544 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1545 { 1546 switch (sset) { 1547 case ETH_SS_STATS: 1548 return ARRAY_SIZE(rtl8169_gstrings); 1549 default: 1550 return -EOPNOTSUPP; 1551 } 1552 } 1553 1554 DECLARE_RTL_COND(rtl_counters_cond) 1555 { 1556 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1557 } 1558 1559 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1560 { 1561 dma_addr_t paddr = tp->counters_phys_addr; 1562 u32 cmd; 1563 1564 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1565 rtl_pci_commit(tp); 1566 cmd = (u64)paddr & DMA_BIT_MASK(32); 1567 RTL_W32(tp, CounterAddrLow, cmd); 1568 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1569 1570 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1571 } 1572 1573 static void rtl8169_reset_counters(struct rtl8169_private *tp) 1574 { 1575 /* 1576 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1577 * tally counters. 1578 */ 1579 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) 1580 rtl8169_do_counters(tp, CounterReset); 1581 } 1582 1583 static void rtl8169_update_counters(struct rtl8169_private *tp) 1584 { 1585 u8 val = RTL_R8(tp, ChipCmd); 1586 1587 /* 1588 * Some chips are unable to dump tally counters when the receiver 1589 * is disabled. If 0xff chip may be in a PCI power-save state. 1590 */ 1591 if (val & CmdRxEnb && val != 0xff) 1592 rtl8169_do_counters(tp, CounterDump); 1593 } 1594 1595 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1596 { 1597 struct rtl8169_counters *counters = tp->counters; 1598 1599 /* 1600 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1601 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1602 * reset by a power cycle, while the counter values collected by the 1603 * driver are reset at every driver unload/load cycle. 1604 * 1605 * To make sure the HW values returned by @get_stats64 match the SW 1606 * values, we collect the initial values at first open(*) and use them 1607 * as offsets to normalize the values returned by @get_stats64. 1608 * 1609 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1610 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1611 * set at open time by rtl_hw_start. 1612 */ 1613 1614 if (tp->tc_offset.inited) 1615 return; 1616 1617 rtl8169_reset_counters(tp); 1618 rtl8169_update_counters(tp); 1619 1620 tp->tc_offset.tx_errors = counters->tx_errors; 1621 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1622 tp->tc_offset.tx_aborted = counters->tx_aborted; 1623 tp->tc_offset.rx_missed = counters->rx_missed; 1624 tp->tc_offset.inited = true; 1625 } 1626 1627 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1628 struct ethtool_stats *stats, u64 *data) 1629 { 1630 struct rtl8169_private *tp = netdev_priv(dev); 1631 struct rtl8169_counters *counters; 1632 1633 counters = tp->counters; 1634 rtl8169_update_counters(tp); 1635 1636 data[0] = le64_to_cpu(counters->tx_packets); 1637 data[1] = le64_to_cpu(counters->rx_packets); 1638 data[2] = le64_to_cpu(counters->tx_errors); 1639 data[3] = le32_to_cpu(counters->rx_errors); 1640 data[4] = le16_to_cpu(counters->rx_missed); 1641 data[5] = le16_to_cpu(counters->align_errors); 1642 data[6] = le32_to_cpu(counters->tx_one_collision); 1643 data[7] = le32_to_cpu(counters->tx_multi_collision); 1644 data[8] = le64_to_cpu(counters->rx_unicast); 1645 data[9] = le64_to_cpu(counters->rx_broadcast); 1646 data[10] = le32_to_cpu(counters->rx_multicast); 1647 data[11] = le16_to_cpu(counters->tx_aborted); 1648 data[12] = le16_to_cpu(counters->tx_underun); 1649 } 1650 1651 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1652 { 1653 switch(stringset) { 1654 case ETH_SS_STATS: 1655 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1656 break; 1657 } 1658 } 1659 1660 /* 1661 * Interrupt coalescing 1662 * 1663 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1664 * > 8169, 8168 and 810x line of chipsets 1665 * 1666 * 8169, 8168, and 8136(810x) serial chipsets support it. 1667 * 1668 * > 2 - the Tx timer unit at gigabit speed 1669 * 1670 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1671 * (0xe0) bit 1 and bit 0. 1672 * 1673 * For 8169 1674 * bit[1:0] \ speed 1000M 100M 10M 1675 * 0 0 320ns 2.56us 40.96us 1676 * 0 1 2.56us 20.48us 327.7us 1677 * 1 0 5.12us 40.96us 655.4us 1678 * 1 1 10.24us 81.92us 1.31ms 1679 * 1680 * For the other 1681 * bit[1:0] \ speed 1000M 100M 10M 1682 * 0 0 5us 2.56us 40.96us 1683 * 0 1 40us 20.48us 327.7us 1684 * 1 0 80us 40.96us 655.4us 1685 * 1 1 160us 81.92us 1.31ms 1686 */ 1687 1688 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1689 struct rtl_coalesce_info { 1690 u32 speed; 1691 u32 scale_nsecs[4]; 1692 }; 1693 1694 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1695 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1696 1697 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1698 { SPEED_1000, COALESCE_DELAY(320) }, 1699 { SPEED_100, COALESCE_DELAY(2560) }, 1700 { SPEED_10, COALESCE_DELAY(40960) }, 1701 { 0 }, 1702 }; 1703 1704 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1705 { SPEED_1000, COALESCE_DELAY(5000) }, 1706 { SPEED_100, COALESCE_DELAY(2560) }, 1707 { SPEED_10, COALESCE_DELAY(40960) }, 1708 { 0 }, 1709 }; 1710 #undef COALESCE_DELAY 1711 1712 /* get rx/tx scale vector corresponding to current speed */ 1713 static const struct rtl_coalesce_info * 1714 rtl_coalesce_info(struct rtl8169_private *tp) 1715 { 1716 const struct rtl_coalesce_info *ci; 1717 1718 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1719 ci = rtl_coalesce_info_8169; 1720 else 1721 ci = rtl_coalesce_info_8168_8136; 1722 1723 /* if speed is unknown assume highest one */ 1724 if (tp->phydev->speed == SPEED_UNKNOWN) 1725 return ci; 1726 1727 for (; ci->speed; ci++) { 1728 if (tp->phydev->speed == ci->speed) 1729 return ci; 1730 } 1731 1732 return ERR_PTR(-ELNRNG); 1733 } 1734 1735 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1736 { 1737 struct rtl8169_private *tp = netdev_priv(dev); 1738 const struct rtl_coalesce_info *ci; 1739 u32 scale, c_us, c_fr; 1740 u16 intrmit; 1741 1742 if (rtl_is_8125(tp)) 1743 return -EOPNOTSUPP; 1744 1745 memset(ec, 0, sizeof(*ec)); 1746 1747 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1748 ci = rtl_coalesce_info(tp); 1749 if (IS_ERR(ci)) 1750 return PTR_ERR(ci); 1751 1752 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1753 1754 intrmit = RTL_R16(tp, IntrMitigate); 1755 1756 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1757 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1758 1759 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1760 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1761 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1762 1763 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1764 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1765 1766 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1767 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1768 1769 return 0; 1770 } 1771 1772 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1773 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1774 u16 *cp01) 1775 { 1776 const struct rtl_coalesce_info *ci; 1777 u16 i; 1778 1779 ci = rtl_coalesce_info(tp); 1780 if (IS_ERR(ci)) 1781 return PTR_ERR(ci); 1782 1783 for (i = 0; i < 4; i++) { 1784 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1785 *cp01 = i; 1786 return ci->scale_nsecs[i]; 1787 } 1788 } 1789 1790 return -ERANGE; 1791 } 1792 1793 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1794 { 1795 struct rtl8169_private *tp = netdev_priv(dev); 1796 u32 tx_fr = ec->tx_max_coalesced_frames; 1797 u32 rx_fr = ec->rx_max_coalesced_frames; 1798 u32 coal_usec_max, units; 1799 u16 w = 0, cp01 = 0; 1800 int scale; 1801 1802 if (rtl_is_8125(tp)) 1803 return -EOPNOTSUPP; 1804 1805 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1806 return -ERANGE; 1807 1808 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1809 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1810 if (scale < 0) 1811 return scale; 1812 1813 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1814 * not only when usecs=0 because of e.g. the following scenario: 1815 * 1816 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1817 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1818 * - then user does `ethtool -C eth0 rx-usecs 100` 1819 * 1820 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1821 * if we want to ignore rx_frames then it has to be set to 0. 1822 */ 1823 if (rx_fr == 1) 1824 rx_fr = 0; 1825 if (tx_fr == 1) 1826 tx_fr = 0; 1827 1828 /* HW requires time limit to be set if frame limit is set */ 1829 if ((tx_fr && !ec->tx_coalesce_usecs) || 1830 (rx_fr && !ec->rx_coalesce_usecs)) 1831 return -EINVAL; 1832 1833 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1834 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1835 1836 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1837 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1838 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1839 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1840 1841 RTL_W16(tp, IntrMitigate, w); 1842 1843 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1844 if (rtl_is_8168evl_up(tp)) { 1845 if (!rx_fr && !tx_fr) 1846 /* disable packet counter */ 1847 tp->cp_cmd |= PktCntrDisable; 1848 else 1849 tp->cp_cmd &= ~PktCntrDisable; 1850 } 1851 1852 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1853 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1854 rtl_pci_commit(tp); 1855 1856 return 0; 1857 } 1858 1859 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1860 { 1861 struct rtl8169_private *tp = netdev_priv(dev); 1862 1863 if (!rtl_supports_eee(tp)) 1864 return -EOPNOTSUPP; 1865 1866 return phy_ethtool_get_eee(tp->phydev, data); 1867 } 1868 1869 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1870 { 1871 struct rtl8169_private *tp = netdev_priv(dev); 1872 int ret; 1873 1874 if (!rtl_supports_eee(tp)) 1875 return -EOPNOTSUPP; 1876 1877 ret = phy_ethtool_set_eee(tp->phydev, data); 1878 1879 if (!ret) 1880 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1881 MDIO_AN_EEE_ADV); 1882 return ret; 1883 } 1884 1885 static const struct ethtool_ops rtl8169_ethtool_ops = { 1886 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1887 ETHTOOL_COALESCE_MAX_FRAMES, 1888 .get_drvinfo = rtl8169_get_drvinfo, 1889 .get_regs_len = rtl8169_get_regs_len, 1890 .get_link = ethtool_op_get_link, 1891 .get_coalesce = rtl_get_coalesce, 1892 .set_coalesce = rtl_set_coalesce, 1893 .get_regs = rtl8169_get_regs, 1894 .get_wol = rtl8169_get_wol, 1895 .set_wol = rtl8169_set_wol, 1896 .get_strings = rtl8169_get_strings, 1897 .get_sset_count = rtl8169_get_sset_count, 1898 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1899 .get_ts_info = ethtool_op_get_ts_info, 1900 .nway_reset = phy_ethtool_nway_reset, 1901 .get_eee = rtl8169_get_eee, 1902 .set_eee = rtl8169_set_eee, 1903 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1904 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1905 }; 1906 1907 static void rtl_enable_eee(struct rtl8169_private *tp) 1908 { 1909 struct phy_device *phydev = tp->phydev; 1910 int adv; 1911 1912 /* respect EEE advertisement the user may have set */ 1913 if (tp->eee_adv >= 0) 1914 adv = tp->eee_adv; 1915 else 1916 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1917 1918 if (adv >= 0) 1919 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1920 } 1921 1922 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1923 { 1924 /* 1925 * The driver currently handles the 8168Bf and the 8168Be identically 1926 * but they can be identified more specifically through the test below 1927 * if needed: 1928 * 1929 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1930 * 1931 * Same thing for the 8101Eb and the 8101Ec: 1932 * 1933 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1934 */ 1935 static const struct rtl_mac_info { 1936 u16 mask; 1937 u16 val; 1938 enum mac_version ver; 1939 } mac_info[] = { 1940 /* 8125B family. */ 1941 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1942 1943 /* 8125A family. */ 1944 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1945 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1946 1947 /* RTL8117 */ 1948 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1949 1950 /* 8168EP family. */ 1951 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1952 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1953 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1954 1955 /* 8168H family. */ 1956 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1957 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1958 1959 /* 8168G family. */ 1960 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1961 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1962 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1963 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1964 1965 /* 8168F family. */ 1966 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 1967 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 1968 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 1969 1970 /* 8168E family. */ 1971 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 1972 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 1973 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 1974 1975 /* 8168D family. */ 1976 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 1977 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 1978 1979 /* 8168DP family. */ 1980 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 1981 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 1982 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 1983 1984 /* 8168C family. */ 1985 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 1986 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 1987 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 1988 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 1989 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 1990 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 1991 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 1992 1993 /* 8168B family. */ 1994 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 1995 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 1996 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 1997 1998 /* 8101 family. */ 1999 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2000 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2001 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2002 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2003 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2004 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2005 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2006 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2007 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2008 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2009 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2010 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2011 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2012 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2013 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2014 /* FIXME: where did these entries come from ? -- FR */ 2015 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2016 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2017 2018 /* 8110 family. */ 2019 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2020 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2021 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2022 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2023 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2024 2025 /* Catch-all */ 2026 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2027 }; 2028 const struct rtl_mac_info *p = mac_info; 2029 enum mac_version ver; 2030 2031 while ((xid & p->mask) != p->val) 2032 p++; 2033 ver = p->ver; 2034 2035 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2036 if (ver == RTL_GIGA_MAC_VER_42) 2037 ver = RTL_GIGA_MAC_VER_43; 2038 else if (ver == RTL_GIGA_MAC_VER_45) 2039 ver = RTL_GIGA_MAC_VER_47; 2040 else if (ver == RTL_GIGA_MAC_VER_46) 2041 ver = RTL_GIGA_MAC_VER_48; 2042 } 2043 2044 return ver; 2045 } 2046 2047 static void rtl_release_firmware(struct rtl8169_private *tp) 2048 { 2049 if (tp->rtl_fw) { 2050 rtl_fw_release_firmware(tp->rtl_fw); 2051 kfree(tp->rtl_fw); 2052 tp->rtl_fw = NULL; 2053 } 2054 } 2055 2056 void r8169_apply_firmware(struct rtl8169_private *tp) 2057 { 2058 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2059 if (tp->rtl_fw) { 2060 rtl_fw_write_firmware(tp, tp->rtl_fw); 2061 /* At least one firmware doesn't reset tp->ocp_base. */ 2062 tp->ocp_base = OCP_STD_PHY_BASE; 2063 } 2064 } 2065 2066 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2067 { 2068 /* Adjust EEE LED frequency */ 2069 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2070 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2071 2072 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2073 } 2074 2075 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2076 { 2077 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2078 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2079 } 2080 2081 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2082 { 2083 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2084 } 2085 2086 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2087 { 2088 rtl8125_set_eee_txidle_timer(tp); 2089 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2090 } 2091 2092 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2093 { 2094 const u16 w[] = { 2095 addr[0] | (addr[1] << 8), 2096 addr[2] | (addr[3] << 8), 2097 addr[4] | (addr[5] << 8) 2098 }; 2099 2100 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2101 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2102 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2103 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2104 } 2105 2106 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2107 { 2108 u16 data1, data2, ioffset; 2109 2110 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2111 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2112 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2113 2114 ioffset = (data2 >> 1) & 0x7ff8; 2115 ioffset |= data2 & 0x0007; 2116 if (data1 & BIT(7)) 2117 ioffset |= BIT(15); 2118 2119 return ioffset; 2120 } 2121 2122 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2123 { 2124 set_bit(flag, tp->wk.flags); 2125 schedule_work(&tp->wk.work); 2126 } 2127 2128 static void rtl8169_init_phy(struct rtl8169_private *tp) 2129 { 2130 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2131 2132 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2133 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2134 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2135 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2136 RTL_W8(tp, 0x82, 0x01); 2137 } 2138 2139 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2140 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2141 tp->pci_dev->subsystem_device == 0xe000) 2142 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2143 2144 /* We may have called phy_speed_down before */ 2145 phy_speed_up(tp->phydev); 2146 2147 if (rtl_supports_eee(tp)) 2148 rtl_enable_eee(tp); 2149 2150 genphy_soft_reset(tp->phydev); 2151 } 2152 2153 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2154 { 2155 rtl_unlock_config_regs(tp); 2156 2157 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2158 rtl_pci_commit(tp); 2159 2160 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2161 rtl_pci_commit(tp); 2162 2163 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2164 rtl_rar_exgmac_set(tp, addr); 2165 2166 rtl_lock_config_regs(tp); 2167 } 2168 2169 static int rtl_set_mac_address(struct net_device *dev, void *p) 2170 { 2171 struct rtl8169_private *tp = netdev_priv(dev); 2172 int ret; 2173 2174 ret = eth_mac_addr(dev, p); 2175 if (ret) 2176 return ret; 2177 2178 rtl_rar_set(tp, dev->dev_addr); 2179 2180 return 0; 2181 } 2182 2183 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2184 { 2185 switch (tp->mac_version) { 2186 case RTL_GIGA_MAC_VER_25: 2187 case RTL_GIGA_MAC_VER_26: 2188 case RTL_GIGA_MAC_VER_29: 2189 case RTL_GIGA_MAC_VER_30: 2190 case RTL_GIGA_MAC_VER_32: 2191 case RTL_GIGA_MAC_VER_33: 2192 case RTL_GIGA_MAC_VER_34: 2193 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63: 2194 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2195 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2196 break; 2197 default: 2198 break; 2199 } 2200 } 2201 2202 static void rtl_pll_power_down(struct rtl8169_private *tp) 2203 { 2204 if (r8168_check_dash(tp)) 2205 return; 2206 2207 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2208 tp->mac_version == RTL_GIGA_MAC_VER_33) 2209 rtl_ephy_write(tp, 0x19, 0xff64); 2210 2211 if (device_may_wakeup(tp_to_dev(tp))) { 2212 phy_speed_down(tp->phydev, false); 2213 rtl_wol_suspend_quirk(tp); 2214 return; 2215 } 2216 2217 switch (tp->mac_version) { 2218 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2219 case RTL_GIGA_MAC_VER_37: 2220 case RTL_GIGA_MAC_VER_39: 2221 case RTL_GIGA_MAC_VER_43: 2222 case RTL_GIGA_MAC_VER_44: 2223 case RTL_GIGA_MAC_VER_45: 2224 case RTL_GIGA_MAC_VER_46: 2225 case RTL_GIGA_MAC_VER_47: 2226 case RTL_GIGA_MAC_VER_48: 2227 case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63: 2228 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2229 break; 2230 case RTL_GIGA_MAC_VER_40: 2231 case RTL_GIGA_MAC_VER_41: 2232 case RTL_GIGA_MAC_VER_49: 2233 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 2234 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2235 break; 2236 default: 2237 break; 2238 } 2239 2240 clk_disable_unprepare(tp->clk); 2241 } 2242 2243 static void rtl_pll_power_up(struct rtl8169_private *tp) 2244 { 2245 clk_prepare_enable(tp->clk); 2246 2247 switch (tp->mac_version) { 2248 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2249 case RTL_GIGA_MAC_VER_37: 2250 case RTL_GIGA_MAC_VER_39: 2251 case RTL_GIGA_MAC_VER_43: 2252 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2253 break; 2254 case RTL_GIGA_MAC_VER_44: 2255 case RTL_GIGA_MAC_VER_45: 2256 case RTL_GIGA_MAC_VER_46: 2257 case RTL_GIGA_MAC_VER_47: 2258 case RTL_GIGA_MAC_VER_48: 2259 case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63: 2260 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2261 break; 2262 case RTL_GIGA_MAC_VER_40: 2263 case RTL_GIGA_MAC_VER_41: 2264 case RTL_GIGA_MAC_VER_49: 2265 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2266 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 2267 break; 2268 default: 2269 break; 2270 } 2271 2272 phy_resume(tp->phydev); 2273 } 2274 2275 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2276 { 2277 switch (tp->mac_version) { 2278 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2279 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2280 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2281 break; 2282 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2283 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2284 case RTL_GIGA_MAC_VER_38: 2285 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2286 break; 2287 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2288 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2289 break; 2290 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2291 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2292 break; 2293 default: 2294 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2295 break; 2296 } 2297 } 2298 2299 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2300 { 2301 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2302 } 2303 2304 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2305 { 2306 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2307 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2308 } 2309 2310 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2311 { 2312 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2313 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2314 } 2315 2316 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2317 { 2318 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2319 } 2320 2321 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2322 { 2323 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2324 } 2325 2326 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2327 { 2328 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2329 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2330 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2331 } 2332 2333 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2334 { 2335 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2336 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2337 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2338 } 2339 2340 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2341 { 2342 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2343 } 2344 2345 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2346 { 2347 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2348 } 2349 2350 static void rtl_jumbo_config(struct rtl8169_private *tp) 2351 { 2352 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2353 2354 rtl_unlock_config_regs(tp); 2355 switch (tp->mac_version) { 2356 case RTL_GIGA_MAC_VER_12: 2357 case RTL_GIGA_MAC_VER_17: 2358 if (jumbo) { 2359 pcie_set_readrq(tp->pci_dev, 512); 2360 r8168b_1_hw_jumbo_enable(tp); 2361 } else { 2362 r8168b_1_hw_jumbo_disable(tp); 2363 } 2364 break; 2365 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2366 if (jumbo) { 2367 pcie_set_readrq(tp->pci_dev, 512); 2368 r8168c_hw_jumbo_enable(tp); 2369 } else { 2370 r8168c_hw_jumbo_disable(tp); 2371 } 2372 break; 2373 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2374 if (jumbo) 2375 r8168dp_hw_jumbo_enable(tp); 2376 else 2377 r8168dp_hw_jumbo_disable(tp); 2378 break; 2379 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2380 if (jumbo) { 2381 pcie_set_readrq(tp->pci_dev, 512); 2382 r8168e_hw_jumbo_enable(tp); 2383 } else { 2384 r8168e_hw_jumbo_disable(tp); 2385 } 2386 break; 2387 default: 2388 break; 2389 } 2390 rtl_lock_config_regs(tp); 2391 2392 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2393 pcie_set_readrq(tp->pci_dev, 4096); 2394 } 2395 2396 DECLARE_RTL_COND(rtl_chipcmd_cond) 2397 { 2398 return RTL_R8(tp, ChipCmd) & CmdReset; 2399 } 2400 2401 static void rtl_hw_reset(struct rtl8169_private *tp) 2402 { 2403 RTL_W8(tp, ChipCmd, CmdReset); 2404 2405 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2406 } 2407 2408 static void rtl_request_firmware(struct rtl8169_private *tp) 2409 { 2410 struct rtl_fw *rtl_fw; 2411 2412 /* firmware loaded already or no firmware available */ 2413 if (tp->rtl_fw || !tp->fw_name) 2414 return; 2415 2416 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2417 if (!rtl_fw) 2418 return; 2419 2420 rtl_fw->phy_write = rtl_writephy; 2421 rtl_fw->phy_read = rtl_readphy; 2422 rtl_fw->mac_mcu_write = mac_mcu_write; 2423 rtl_fw->mac_mcu_read = mac_mcu_read; 2424 rtl_fw->fw_name = tp->fw_name; 2425 rtl_fw->dev = tp_to_dev(tp); 2426 2427 if (rtl_fw_request_firmware(rtl_fw)) 2428 kfree(rtl_fw); 2429 else 2430 tp->rtl_fw = rtl_fw; 2431 } 2432 2433 static void rtl_rx_close(struct rtl8169_private *tp) 2434 { 2435 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2436 } 2437 2438 DECLARE_RTL_COND(rtl_npq_cond) 2439 { 2440 return RTL_R8(tp, TxPoll) & NPQ; 2441 } 2442 2443 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2444 { 2445 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2446 } 2447 2448 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2449 { 2450 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2451 } 2452 2453 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2454 { 2455 /* IntrMitigate has new functionality on RTL8125 */ 2456 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2457 } 2458 2459 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2460 { 2461 switch (tp->mac_version) { 2462 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2463 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2464 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2465 break; 2466 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2467 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2468 break; 2469 case RTL_GIGA_MAC_VER_63: 2470 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2471 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2472 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2473 break; 2474 default: 2475 break; 2476 } 2477 } 2478 2479 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2480 { 2481 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2482 fsleep(2000); 2483 rtl_wait_txrx_fifo_empty(tp); 2484 } 2485 2486 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2487 { 2488 u32 val = TX_DMA_BURST << TxDMAShift | 2489 InterFrameGap << TxInterFrameGapShift; 2490 2491 if (rtl_is_8168evl_up(tp)) 2492 val |= TXCFG_AUTO_FIFO; 2493 2494 RTL_W32(tp, TxConfig, val); 2495 } 2496 2497 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2498 { 2499 /* Low hurts. Let's disable the filtering. */ 2500 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2501 } 2502 2503 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2504 { 2505 /* 2506 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2507 * register to be written before TxDescAddrLow to work. 2508 * Switching from MMIO to I/O access fixes the issue as well. 2509 */ 2510 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2511 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2512 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2513 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2514 } 2515 2516 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2517 { 2518 u32 val; 2519 2520 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2521 val = 0x000fff00; 2522 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2523 val = 0x00ffff00; 2524 else 2525 return; 2526 2527 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2528 val |= 0xff; 2529 2530 RTL_W32(tp, 0x7c, val); 2531 } 2532 2533 static void rtl_set_rx_mode(struct net_device *dev) 2534 { 2535 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2536 /* Multicast hash filter */ 2537 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2538 struct rtl8169_private *tp = netdev_priv(dev); 2539 u32 tmp; 2540 2541 if (dev->flags & IFF_PROMISC) { 2542 rx_mode |= AcceptAllPhys; 2543 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2544 dev->flags & IFF_ALLMULTI || 2545 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2546 /* accept all multicasts */ 2547 } else if (netdev_mc_empty(dev)) { 2548 rx_mode &= ~AcceptMulticast; 2549 } else { 2550 struct netdev_hw_addr *ha; 2551 2552 mc_filter[1] = mc_filter[0] = 0; 2553 netdev_for_each_mc_addr(ha, dev) { 2554 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2555 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2556 } 2557 2558 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2559 tmp = mc_filter[0]; 2560 mc_filter[0] = swab32(mc_filter[1]); 2561 mc_filter[1] = swab32(tmp); 2562 } 2563 } 2564 2565 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2566 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2567 2568 tmp = RTL_R32(tp, RxConfig); 2569 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2570 } 2571 2572 DECLARE_RTL_COND(rtl_csiar_cond) 2573 { 2574 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2575 } 2576 2577 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2578 { 2579 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2580 2581 RTL_W32(tp, CSIDR, value); 2582 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2583 CSIAR_BYTE_ENABLE | func << 16); 2584 2585 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2586 } 2587 2588 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2589 { 2590 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2591 2592 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2593 CSIAR_BYTE_ENABLE); 2594 2595 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2596 RTL_R32(tp, CSIDR) : ~0; 2597 } 2598 2599 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2600 { 2601 struct pci_dev *pdev = tp->pci_dev; 2602 u32 csi; 2603 2604 /* According to Realtek the value at config space address 0x070f 2605 * controls the L0s/L1 entrance latency. We try standard ECAM access 2606 * first and if it fails fall back to CSI. 2607 */ 2608 if (pdev->cfg_size > 0x070f && 2609 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2610 return; 2611 2612 netdev_notice_once(tp->dev, 2613 "No native access to PCI extended config space, falling back to CSI\n"); 2614 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2615 rtl_csi_write(tp, 0x070c, csi | val << 24); 2616 } 2617 2618 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2619 { 2620 rtl_csi_access_enable(tp, 0x27); 2621 } 2622 2623 struct ephy_info { 2624 unsigned int offset; 2625 u16 mask; 2626 u16 bits; 2627 }; 2628 2629 static void __rtl_ephy_init(struct rtl8169_private *tp, 2630 const struct ephy_info *e, int len) 2631 { 2632 u16 w; 2633 2634 while (len-- > 0) { 2635 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2636 rtl_ephy_write(tp, e->offset, w); 2637 e++; 2638 } 2639 } 2640 2641 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2642 2643 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2644 { 2645 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2646 PCI_EXP_LNKCTL_CLKREQ_EN); 2647 } 2648 2649 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2650 { 2651 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2652 PCI_EXP_LNKCTL_CLKREQ_EN); 2653 } 2654 2655 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2656 { 2657 /* work around an issue when PCI reset occurs during L2/L3 state */ 2658 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2659 } 2660 2661 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2662 { 2663 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2664 if (enable && tp->aspm_manageable) { 2665 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2666 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2667 } else { 2668 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2669 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2670 } 2671 2672 udelay(10); 2673 } 2674 2675 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2676 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2677 { 2678 /* Usage of dynamic vs. static FIFO is controlled by bit 2679 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2680 */ 2681 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2682 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2683 } 2684 2685 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2686 u8 low, u8 high) 2687 { 2688 /* FIFO thresholds for pause flow control */ 2689 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2690 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2691 } 2692 2693 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2694 { 2695 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2696 } 2697 2698 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2699 { 2700 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2701 2702 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2703 2704 rtl_disable_clock_request(tp); 2705 } 2706 2707 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2708 { 2709 static const struct ephy_info e_info_8168cp[] = { 2710 { 0x01, 0, 0x0001 }, 2711 { 0x02, 0x0800, 0x1000 }, 2712 { 0x03, 0, 0x0042 }, 2713 { 0x06, 0x0080, 0x0000 }, 2714 { 0x07, 0, 0x2000 } 2715 }; 2716 2717 rtl_set_def_aspm_entry_latency(tp); 2718 2719 rtl_ephy_init(tp, e_info_8168cp); 2720 2721 __rtl_hw_start_8168cp(tp); 2722 } 2723 2724 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2725 { 2726 rtl_set_def_aspm_entry_latency(tp); 2727 2728 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2729 } 2730 2731 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2732 { 2733 rtl_set_def_aspm_entry_latency(tp); 2734 2735 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2736 2737 /* Magic. */ 2738 RTL_W8(tp, DBG_REG, 0x20); 2739 } 2740 2741 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2742 { 2743 static const struct ephy_info e_info_8168c_1[] = { 2744 { 0x02, 0x0800, 0x1000 }, 2745 { 0x03, 0, 0x0002 }, 2746 { 0x06, 0x0080, 0x0000 } 2747 }; 2748 2749 rtl_set_def_aspm_entry_latency(tp); 2750 2751 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2752 2753 rtl_ephy_init(tp, e_info_8168c_1); 2754 2755 __rtl_hw_start_8168cp(tp); 2756 } 2757 2758 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2759 { 2760 static const struct ephy_info e_info_8168c_2[] = { 2761 { 0x01, 0, 0x0001 }, 2762 { 0x03, 0x0400, 0x0020 } 2763 }; 2764 2765 rtl_set_def_aspm_entry_latency(tp); 2766 2767 rtl_ephy_init(tp, e_info_8168c_2); 2768 2769 __rtl_hw_start_8168cp(tp); 2770 } 2771 2772 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2773 { 2774 rtl_hw_start_8168c_2(tp); 2775 } 2776 2777 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2778 { 2779 rtl_set_def_aspm_entry_latency(tp); 2780 2781 __rtl_hw_start_8168cp(tp); 2782 } 2783 2784 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2785 { 2786 rtl_set_def_aspm_entry_latency(tp); 2787 2788 rtl_disable_clock_request(tp); 2789 } 2790 2791 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2792 { 2793 static const struct ephy_info e_info_8168d_4[] = { 2794 { 0x0b, 0x0000, 0x0048 }, 2795 { 0x19, 0x0020, 0x0050 }, 2796 { 0x0c, 0x0100, 0x0020 }, 2797 { 0x10, 0x0004, 0x0000 }, 2798 }; 2799 2800 rtl_set_def_aspm_entry_latency(tp); 2801 2802 rtl_ephy_init(tp, e_info_8168d_4); 2803 2804 rtl_enable_clock_request(tp); 2805 } 2806 2807 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2808 { 2809 static const struct ephy_info e_info_8168e_1[] = { 2810 { 0x00, 0x0200, 0x0100 }, 2811 { 0x00, 0x0000, 0x0004 }, 2812 { 0x06, 0x0002, 0x0001 }, 2813 { 0x06, 0x0000, 0x0030 }, 2814 { 0x07, 0x0000, 0x2000 }, 2815 { 0x00, 0x0000, 0x0020 }, 2816 { 0x03, 0x5800, 0x2000 }, 2817 { 0x03, 0x0000, 0x0001 }, 2818 { 0x01, 0x0800, 0x1000 }, 2819 { 0x07, 0x0000, 0x4000 }, 2820 { 0x1e, 0x0000, 0x2000 }, 2821 { 0x19, 0xffff, 0xfe6c }, 2822 { 0x0a, 0x0000, 0x0040 } 2823 }; 2824 2825 rtl_set_def_aspm_entry_latency(tp); 2826 2827 rtl_ephy_init(tp, e_info_8168e_1); 2828 2829 rtl_disable_clock_request(tp); 2830 2831 /* Reset tx FIFO pointer */ 2832 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2833 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2834 2835 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2836 } 2837 2838 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2839 { 2840 static const struct ephy_info e_info_8168e_2[] = { 2841 { 0x09, 0x0000, 0x0080 }, 2842 { 0x19, 0x0000, 0x0224 }, 2843 { 0x00, 0x0000, 0x0004 }, 2844 { 0x0c, 0x3df0, 0x0200 }, 2845 }; 2846 2847 rtl_set_def_aspm_entry_latency(tp); 2848 2849 rtl_ephy_init(tp, e_info_8168e_2); 2850 2851 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2852 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2853 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2854 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2855 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2856 rtl_reset_packet_filter(tp); 2857 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2858 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2859 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2860 2861 rtl_disable_clock_request(tp); 2862 2863 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2864 2865 rtl8168_config_eee_mac(tp); 2866 2867 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2868 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2869 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2870 2871 rtl_hw_aspm_clkreq_enable(tp, true); 2872 } 2873 2874 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2875 { 2876 rtl_set_def_aspm_entry_latency(tp); 2877 2878 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2879 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2880 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2881 rtl_reset_packet_filter(tp); 2882 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2883 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2884 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2885 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2886 2887 rtl_disable_clock_request(tp); 2888 2889 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2890 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2891 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2892 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2893 2894 rtl8168_config_eee_mac(tp); 2895 } 2896 2897 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2898 { 2899 static const struct ephy_info e_info_8168f_1[] = { 2900 { 0x06, 0x00c0, 0x0020 }, 2901 { 0x08, 0x0001, 0x0002 }, 2902 { 0x09, 0x0000, 0x0080 }, 2903 { 0x19, 0x0000, 0x0224 }, 2904 { 0x00, 0x0000, 0x0004 }, 2905 { 0x0c, 0x3df0, 0x0200 }, 2906 }; 2907 2908 rtl_hw_start_8168f(tp); 2909 2910 rtl_ephy_init(tp, e_info_8168f_1); 2911 2912 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2913 } 2914 2915 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2916 { 2917 static const struct ephy_info e_info_8168f_1[] = { 2918 { 0x06, 0x00c0, 0x0020 }, 2919 { 0x0f, 0xffff, 0x5200 }, 2920 { 0x19, 0x0000, 0x0224 }, 2921 { 0x00, 0x0000, 0x0004 }, 2922 { 0x0c, 0x3df0, 0x0200 }, 2923 }; 2924 2925 rtl_hw_start_8168f(tp); 2926 rtl_pcie_state_l2l3_disable(tp); 2927 2928 rtl_ephy_init(tp, e_info_8168f_1); 2929 2930 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2931 } 2932 2933 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2934 { 2935 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2936 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2937 2938 rtl_set_def_aspm_entry_latency(tp); 2939 2940 rtl_reset_packet_filter(tp); 2941 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2942 2943 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2944 2945 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2946 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2947 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2948 2949 rtl8168_config_eee_mac(tp); 2950 2951 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2952 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2953 2954 rtl_pcie_state_l2l3_disable(tp); 2955 } 2956 2957 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2958 { 2959 static const struct ephy_info e_info_8168g_1[] = { 2960 { 0x00, 0x0008, 0x0000 }, 2961 { 0x0c, 0x3ff0, 0x0820 }, 2962 { 0x1e, 0x0000, 0x0001 }, 2963 { 0x19, 0x8000, 0x0000 } 2964 }; 2965 2966 rtl_hw_start_8168g(tp); 2967 2968 /* disable aspm and clock request before access ephy */ 2969 rtl_hw_aspm_clkreq_enable(tp, false); 2970 rtl_ephy_init(tp, e_info_8168g_1); 2971 rtl_hw_aspm_clkreq_enable(tp, true); 2972 } 2973 2974 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 2975 { 2976 static const struct ephy_info e_info_8168g_2[] = { 2977 { 0x00, 0x0008, 0x0000 }, 2978 { 0x0c, 0x3ff0, 0x0820 }, 2979 { 0x19, 0xffff, 0x7c00 }, 2980 { 0x1e, 0xffff, 0x20eb }, 2981 { 0x0d, 0xffff, 0x1666 }, 2982 { 0x00, 0xffff, 0x10a3 }, 2983 { 0x06, 0xffff, 0xf050 }, 2984 { 0x04, 0x0000, 0x0010 }, 2985 { 0x1d, 0x4000, 0x0000 }, 2986 }; 2987 2988 rtl_hw_start_8168g(tp); 2989 2990 /* disable aspm and clock request before access ephy */ 2991 rtl_hw_aspm_clkreq_enable(tp, false); 2992 rtl_ephy_init(tp, e_info_8168g_2); 2993 } 2994 2995 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 2996 { 2997 static const struct ephy_info e_info_8411_2[] = { 2998 { 0x00, 0x0008, 0x0000 }, 2999 { 0x0c, 0x37d0, 0x0820 }, 3000 { 0x1e, 0x0000, 0x0001 }, 3001 { 0x19, 0x8021, 0x0000 }, 3002 { 0x1e, 0x0000, 0x2000 }, 3003 { 0x0d, 0x0100, 0x0200 }, 3004 { 0x00, 0x0000, 0x0080 }, 3005 { 0x06, 0x0000, 0x0010 }, 3006 { 0x04, 0x0000, 0x0010 }, 3007 { 0x1d, 0x0000, 0x4000 }, 3008 }; 3009 3010 rtl_hw_start_8168g(tp); 3011 3012 /* disable aspm and clock request before access ephy */ 3013 rtl_hw_aspm_clkreq_enable(tp, false); 3014 rtl_ephy_init(tp, e_info_8411_2); 3015 3016 /* The following Realtek-provided magic fixes an issue with the RX unit 3017 * getting confused after the PHY having been powered-down. 3018 */ 3019 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3020 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3021 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3022 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3023 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3024 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3025 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3026 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3027 mdelay(3); 3028 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3029 3030 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3031 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3032 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3033 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3034 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3035 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3036 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3037 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3038 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3039 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3040 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3041 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3042 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3043 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3044 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3045 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3046 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3047 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3048 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3049 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3050 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3051 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3052 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3053 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3054 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3055 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3056 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3057 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3058 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3059 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3060 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3061 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3062 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3063 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3064 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3065 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3066 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3067 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3068 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3069 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3070 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3071 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3072 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3073 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3074 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3075 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3076 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3077 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3078 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3079 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3080 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3081 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3082 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3083 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3084 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3085 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3086 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3087 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3088 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3089 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3090 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3091 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3092 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3093 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3094 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3095 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3096 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3097 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3098 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3099 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3100 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3101 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3102 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3103 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3104 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3105 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3106 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3107 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3108 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3109 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3110 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3111 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3112 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3113 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3114 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3115 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3116 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3117 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3118 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3119 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3120 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3121 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3122 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3123 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3124 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3125 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3126 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3127 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3128 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3129 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3130 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3131 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3132 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3133 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3134 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3135 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3136 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3137 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3138 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3139 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3140 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3141 3142 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3143 3144 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3145 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3146 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3147 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3148 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3149 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3150 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3151 3152 rtl_hw_aspm_clkreq_enable(tp, true); 3153 } 3154 3155 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3156 { 3157 static const struct ephy_info e_info_8168h_1[] = { 3158 { 0x1e, 0x0800, 0x0001 }, 3159 { 0x1d, 0x0000, 0x0800 }, 3160 { 0x05, 0xffff, 0x2089 }, 3161 { 0x06, 0xffff, 0x5881 }, 3162 { 0x04, 0xffff, 0x854a }, 3163 { 0x01, 0xffff, 0x068b } 3164 }; 3165 int rg_saw_cnt; 3166 3167 /* disable aspm and clock request before access ephy */ 3168 rtl_hw_aspm_clkreq_enable(tp, false); 3169 rtl_ephy_init(tp, e_info_8168h_1); 3170 3171 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3172 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3173 3174 rtl_set_def_aspm_entry_latency(tp); 3175 3176 rtl_reset_packet_filter(tp); 3177 3178 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3179 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3180 3181 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3182 3183 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3184 3185 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3186 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3187 3188 rtl8168_config_eee_mac(tp); 3189 3190 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3191 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3192 3193 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3194 3195 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3196 3197 rtl_pcie_state_l2l3_disable(tp); 3198 3199 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3200 if (rg_saw_cnt > 0) { 3201 u16 sw_cnt_1ms_ini; 3202 3203 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3204 sw_cnt_1ms_ini &= 0x0fff; 3205 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3206 } 3207 3208 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3209 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3210 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3211 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3212 3213 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3214 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3215 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3216 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3217 3218 rtl_hw_aspm_clkreq_enable(tp, true); 3219 } 3220 3221 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3222 { 3223 rtl8168ep_stop_cmac(tp); 3224 3225 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3226 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3227 3228 rtl_set_def_aspm_entry_latency(tp); 3229 3230 rtl_reset_packet_filter(tp); 3231 3232 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3233 3234 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3235 3236 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3237 3238 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3239 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3240 3241 rtl8168_config_eee_mac(tp); 3242 3243 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3244 3245 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3246 3247 rtl_pcie_state_l2l3_disable(tp); 3248 } 3249 3250 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3251 { 3252 static const struct ephy_info e_info_8168ep_1[] = { 3253 { 0x00, 0xffff, 0x10ab }, 3254 { 0x06, 0xffff, 0xf030 }, 3255 { 0x08, 0xffff, 0x2006 }, 3256 { 0x0d, 0xffff, 0x1666 }, 3257 { 0x0c, 0x3ff0, 0x0000 } 3258 }; 3259 3260 /* disable aspm and clock request before access ephy */ 3261 rtl_hw_aspm_clkreq_enable(tp, false); 3262 rtl_ephy_init(tp, e_info_8168ep_1); 3263 3264 rtl_hw_start_8168ep(tp); 3265 3266 rtl_hw_aspm_clkreq_enable(tp, true); 3267 } 3268 3269 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3270 { 3271 static const struct ephy_info e_info_8168ep_2[] = { 3272 { 0x00, 0xffff, 0x10a3 }, 3273 { 0x19, 0xffff, 0xfc00 }, 3274 { 0x1e, 0xffff, 0x20ea } 3275 }; 3276 3277 /* disable aspm and clock request before access ephy */ 3278 rtl_hw_aspm_clkreq_enable(tp, false); 3279 rtl_ephy_init(tp, e_info_8168ep_2); 3280 3281 rtl_hw_start_8168ep(tp); 3282 3283 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3284 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3285 3286 rtl_hw_aspm_clkreq_enable(tp, true); 3287 } 3288 3289 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3290 { 3291 static const struct ephy_info e_info_8168ep_3[] = { 3292 { 0x00, 0x0000, 0x0080 }, 3293 { 0x0d, 0x0100, 0x0200 }, 3294 { 0x19, 0x8021, 0x0000 }, 3295 { 0x1e, 0x0000, 0x2000 }, 3296 }; 3297 3298 /* disable aspm and clock request before access ephy */ 3299 rtl_hw_aspm_clkreq_enable(tp, false); 3300 rtl_ephy_init(tp, e_info_8168ep_3); 3301 3302 rtl_hw_start_8168ep(tp); 3303 3304 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3305 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3306 3307 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3308 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3309 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3310 3311 rtl_hw_aspm_clkreq_enable(tp, true); 3312 } 3313 3314 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3315 { 3316 static const struct ephy_info e_info_8117[] = { 3317 { 0x19, 0x0040, 0x1100 }, 3318 { 0x59, 0x0040, 0x1100 }, 3319 }; 3320 int rg_saw_cnt; 3321 3322 rtl8168ep_stop_cmac(tp); 3323 3324 /* disable aspm and clock request before access ephy */ 3325 rtl_hw_aspm_clkreq_enable(tp, false); 3326 rtl_ephy_init(tp, e_info_8117); 3327 3328 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3329 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3330 3331 rtl_set_def_aspm_entry_latency(tp); 3332 3333 rtl_reset_packet_filter(tp); 3334 3335 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3336 3337 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3338 3339 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3340 3341 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3342 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3343 3344 rtl8168_config_eee_mac(tp); 3345 3346 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3347 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3348 3349 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3350 3351 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3352 3353 rtl_pcie_state_l2l3_disable(tp); 3354 3355 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3356 if (rg_saw_cnt > 0) { 3357 u16 sw_cnt_1ms_ini; 3358 3359 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3360 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3361 } 3362 3363 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3364 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3365 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3366 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3367 3368 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3369 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3370 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3371 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3372 3373 /* firmware is for MAC only */ 3374 r8169_apply_firmware(tp); 3375 3376 rtl_hw_aspm_clkreq_enable(tp, true); 3377 } 3378 3379 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3380 { 3381 static const struct ephy_info e_info_8102e_1[] = { 3382 { 0x01, 0, 0x6e65 }, 3383 { 0x02, 0, 0x091f }, 3384 { 0x03, 0, 0xc2f9 }, 3385 { 0x06, 0, 0xafb5 }, 3386 { 0x07, 0, 0x0e00 }, 3387 { 0x19, 0, 0xec80 }, 3388 { 0x01, 0, 0x2e65 }, 3389 { 0x01, 0, 0x6e65 } 3390 }; 3391 u8 cfg1; 3392 3393 rtl_set_def_aspm_entry_latency(tp); 3394 3395 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3396 3397 RTL_W8(tp, Config1, 3398 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3399 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3400 3401 cfg1 = RTL_R8(tp, Config1); 3402 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3403 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3404 3405 rtl_ephy_init(tp, e_info_8102e_1); 3406 } 3407 3408 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3409 { 3410 rtl_set_def_aspm_entry_latency(tp); 3411 3412 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3413 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3414 } 3415 3416 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3417 { 3418 rtl_hw_start_8102e_2(tp); 3419 3420 rtl_ephy_write(tp, 0x03, 0xc2f9); 3421 } 3422 3423 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3424 { 3425 static const struct ephy_info e_info_8401[] = { 3426 { 0x01, 0xffff, 0x6fe5 }, 3427 { 0x03, 0xffff, 0x0599 }, 3428 { 0x06, 0xffff, 0xaf25 }, 3429 { 0x07, 0xffff, 0x8e68 }, 3430 }; 3431 3432 rtl_ephy_init(tp, e_info_8401); 3433 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3434 } 3435 3436 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3437 { 3438 static const struct ephy_info e_info_8105e_1[] = { 3439 { 0x07, 0, 0x4000 }, 3440 { 0x19, 0, 0x0200 }, 3441 { 0x19, 0, 0x0020 }, 3442 { 0x1e, 0, 0x2000 }, 3443 { 0x03, 0, 0x0001 }, 3444 { 0x19, 0, 0x0100 }, 3445 { 0x19, 0, 0x0004 }, 3446 { 0x0a, 0, 0x0020 } 3447 }; 3448 3449 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3450 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3451 3452 /* Disable Early Tally Counter */ 3453 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3454 3455 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3456 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3457 3458 rtl_ephy_init(tp, e_info_8105e_1); 3459 3460 rtl_pcie_state_l2l3_disable(tp); 3461 } 3462 3463 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3464 { 3465 rtl_hw_start_8105e_1(tp); 3466 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3467 } 3468 3469 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3470 { 3471 static const struct ephy_info e_info_8402[] = { 3472 { 0x19, 0xffff, 0xff64 }, 3473 { 0x1e, 0, 0x4000 } 3474 }; 3475 3476 rtl_set_def_aspm_entry_latency(tp); 3477 3478 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3479 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3480 3481 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3482 3483 rtl_ephy_init(tp, e_info_8402); 3484 3485 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3486 rtl_reset_packet_filter(tp); 3487 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3488 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3489 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3490 3491 /* disable EEE */ 3492 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3493 3494 rtl_pcie_state_l2l3_disable(tp); 3495 } 3496 3497 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3498 { 3499 rtl_hw_aspm_clkreq_enable(tp, false); 3500 3501 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3502 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3503 3504 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3505 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3506 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3507 3508 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3509 3510 /* disable EEE */ 3511 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3512 3513 rtl_pcie_state_l2l3_disable(tp); 3514 rtl_hw_aspm_clkreq_enable(tp, true); 3515 } 3516 3517 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3518 { 3519 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3520 } 3521 3522 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3523 { 3524 rtl_pcie_state_l2l3_disable(tp); 3525 3526 RTL_W16(tp, 0x382, 0x221b); 3527 RTL_W8(tp, 0x4500, 0); 3528 RTL_W16(tp, 0x4800, 0); 3529 3530 /* disable UPS */ 3531 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3532 3533 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3534 3535 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3536 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3537 3538 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3539 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3540 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3541 3542 /* disable new tx descriptor format */ 3543 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3544 3545 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3546 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3547 else 3548 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3549 3550 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3551 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3552 else 3553 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3554 3555 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3556 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3557 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3558 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3559 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3560 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3561 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3562 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3563 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3564 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3565 3566 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3567 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3568 udelay(1); 3569 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3570 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3571 3572 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3573 3574 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3575 3576 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3577 rtl8125b_config_eee_mac(tp); 3578 else 3579 rtl8125a_config_eee_mac(tp); 3580 3581 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3582 udelay(10); 3583 } 3584 3585 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3586 { 3587 static const struct ephy_info e_info_8125a_1[] = { 3588 { 0x01, 0xffff, 0xa812 }, 3589 { 0x09, 0xffff, 0x520c }, 3590 { 0x04, 0xffff, 0xd000 }, 3591 { 0x0d, 0xffff, 0xf702 }, 3592 { 0x0a, 0xffff, 0x8653 }, 3593 { 0x06, 0xffff, 0x001e }, 3594 { 0x08, 0xffff, 0x3595 }, 3595 { 0x20, 0xffff, 0x9455 }, 3596 { 0x21, 0xffff, 0x99ff }, 3597 { 0x02, 0xffff, 0x6046 }, 3598 { 0x29, 0xffff, 0xfe00 }, 3599 { 0x23, 0xffff, 0xab62 }, 3600 3601 { 0x41, 0xffff, 0xa80c }, 3602 { 0x49, 0xffff, 0x520c }, 3603 { 0x44, 0xffff, 0xd000 }, 3604 { 0x4d, 0xffff, 0xf702 }, 3605 { 0x4a, 0xffff, 0x8653 }, 3606 { 0x46, 0xffff, 0x001e }, 3607 { 0x48, 0xffff, 0x3595 }, 3608 { 0x60, 0xffff, 0x9455 }, 3609 { 0x61, 0xffff, 0x99ff }, 3610 { 0x42, 0xffff, 0x6046 }, 3611 { 0x69, 0xffff, 0xfe00 }, 3612 { 0x63, 0xffff, 0xab62 }, 3613 }; 3614 3615 rtl_set_def_aspm_entry_latency(tp); 3616 3617 /* disable aspm and clock request before access ephy */ 3618 rtl_hw_aspm_clkreq_enable(tp, false); 3619 rtl_ephy_init(tp, e_info_8125a_1); 3620 3621 rtl_hw_start_8125_common(tp); 3622 rtl_hw_aspm_clkreq_enable(tp, true); 3623 } 3624 3625 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3626 { 3627 static const struct ephy_info e_info_8125a_2[] = { 3628 { 0x04, 0xffff, 0xd000 }, 3629 { 0x0a, 0xffff, 0x8653 }, 3630 { 0x23, 0xffff, 0xab66 }, 3631 { 0x20, 0xffff, 0x9455 }, 3632 { 0x21, 0xffff, 0x99ff }, 3633 { 0x29, 0xffff, 0xfe04 }, 3634 3635 { 0x44, 0xffff, 0xd000 }, 3636 { 0x4a, 0xffff, 0x8653 }, 3637 { 0x63, 0xffff, 0xab66 }, 3638 { 0x60, 0xffff, 0x9455 }, 3639 { 0x61, 0xffff, 0x99ff }, 3640 { 0x69, 0xffff, 0xfe04 }, 3641 }; 3642 3643 rtl_set_def_aspm_entry_latency(tp); 3644 3645 /* disable aspm and clock request before access ephy */ 3646 rtl_hw_aspm_clkreq_enable(tp, false); 3647 rtl_ephy_init(tp, e_info_8125a_2); 3648 3649 rtl_hw_start_8125_common(tp); 3650 rtl_hw_aspm_clkreq_enable(tp, true); 3651 } 3652 3653 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3654 { 3655 static const struct ephy_info e_info_8125b[] = { 3656 { 0x0b, 0xffff, 0xa908 }, 3657 { 0x1e, 0xffff, 0x20eb }, 3658 { 0x4b, 0xffff, 0xa908 }, 3659 { 0x5e, 0xffff, 0x20eb }, 3660 { 0x22, 0x0030, 0x0020 }, 3661 { 0x62, 0x0030, 0x0020 }, 3662 }; 3663 3664 rtl_set_def_aspm_entry_latency(tp); 3665 rtl_hw_aspm_clkreq_enable(tp, false); 3666 3667 rtl_ephy_init(tp, e_info_8125b); 3668 rtl_hw_start_8125_common(tp); 3669 3670 rtl_hw_aspm_clkreq_enable(tp, true); 3671 } 3672 3673 static void rtl_hw_config(struct rtl8169_private *tp) 3674 { 3675 static const rtl_generic_fct hw_configs[] = { 3676 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3677 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3678 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3679 [RTL_GIGA_MAC_VER_10] = NULL, 3680 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3681 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3682 [RTL_GIGA_MAC_VER_13] = NULL, 3683 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3684 [RTL_GIGA_MAC_VER_16] = NULL, 3685 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3686 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3687 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3688 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3689 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3690 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3691 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3692 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3693 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3694 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3695 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3696 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3697 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3698 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3699 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3700 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3701 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3702 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3703 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3704 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3705 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3706 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3707 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3708 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3709 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3710 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3711 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3712 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3713 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3714 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3715 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3716 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3717 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3718 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3719 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3720 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3721 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3722 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3723 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3724 }; 3725 3726 if (hw_configs[tp->mac_version]) 3727 hw_configs[tp->mac_version](tp); 3728 } 3729 3730 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3731 { 3732 int i; 3733 3734 /* disable interrupt coalescing */ 3735 for (i = 0xa00; i < 0xb00; i += 4) 3736 RTL_W32(tp, i, 0); 3737 3738 rtl_hw_config(tp); 3739 } 3740 3741 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3742 { 3743 if (rtl_is_8168evl_up(tp)) 3744 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3745 else 3746 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3747 3748 rtl_hw_config(tp); 3749 3750 /* disable interrupt coalescing */ 3751 RTL_W16(tp, IntrMitigate, 0x0000); 3752 } 3753 3754 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3755 { 3756 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3757 3758 tp->cp_cmd |= PCIMulRW; 3759 3760 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3761 tp->mac_version == RTL_GIGA_MAC_VER_03) 3762 tp->cp_cmd |= EnAnaPLL; 3763 3764 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3765 3766 rtl8169_set_magic_reg(tp); 3767 3768 /* disable interrupt coalescing */ 3769 RTL_W16(tp, IntrMitigate, 0x0000); 3770 } 3771 3772 static void rtl_hw_start(struct rtl8169_private *tp) 3773 { 3774 rtl_unlock_config_regs(tp); 3775 3776 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3777 3778 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3779 rtl_hw_start_8169(tp); 3780 else if (rtl_is_8125(tp)) 3781 rtl_hw_start_8125(tp); 3782 else 3783 rtl_hw_start_8168(tp); 3784 3785 rtl_set_rx_max_size(tp); 3786 rtl_set_rx_tx_desc_registers(tp); 3787 rtl_lock_config_regs(tp); 3788 3789 rtl_jumbo_config(tp); 3790 3791 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3792 rtl_pci_commit(tp); 3793 3794 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3795 rtl_init_rxcfg(tp); 3796 rtl_set_tx_config_registers(tp); 3797 rtl_set_rx_config_features(tp, tp->dev->features); 3798 rtl_set_rx_mode(tp->dev); 3799 rtl_irq_enable(tp); 3800 } 3801 3802 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3803 { 3804 struct rtl8169_private *tp = netdev_priv(dev); 3805 3806 dev->mtu = new_mtu; 3807 netdev_update_features(dev); 3808 rtl_jumbo_config(tp); 3809 3810 switch (tp->mac_version) { 3811 case RTL_GIGA_MAC_VER_61: 3812 case RTL_GIGA_MAC_VER_63: 3813 rtl8125_set_eee_txidle_timer(tp); 3814 break; 3815 default: 3816 break; 3817 } 3818 3819 return 0; 3820 } 3821 3822 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3823 { 3824 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3825 3826 desc->opts2 = 0; 3827 /* Force memory writes to complete before releasing descriptor */ 3828 dma_wmb(); 3829 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3830 } 3831 3832 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3833 struct RxDesc *desc) 3834 { 3835 struct device *d = tp_to_dev(tp); 3836 int node = dev_to_node(d); 3837 dma_addr_t mapping; 3838 struct page *data; 3839 3840 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3841 if (!data) 3842 return NULL; 3843 3844 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3845 if (unlikely(dma_mapping_error(d, mapping))) { 3846 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3847 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3848 return NULL; 3849 } 3850 3851 desc->addr = cpu_to_le64(mapping); 3852 rtl8169_mark_to_asic(desc); 3853 3854 return data; 3855 } 3856 3857 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3858 { 3859 unsigned int i; 3860 3861 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3862 dma_unmap_page(tp_to_dev(tp), 3863 le64_to_cpu(tp->RxDescArray[i].addr), 3864 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3865 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3866 tp->Rx_databuff[i] = NULL; 3867 tp->RxDescArray[i].addr = 0; 3868 tp->RxDescArray[i].opts1 = 0; 3869 } 3870 } 3871 3872 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3873 { 3874 unsigned int i; 3875 3876 for (i = 0; i < NUM_RX_DESC; i++) { 3877 struct page *data; 3878 3879 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3880 if (!data) { 3881 rtl8169_rx_clear(tp); 3882 return -ENOMEM; 3883 } 3884 tp->Rx_databuff[i] = data; 3885 } 3886 3887 /* mark as last descriptor in the ring */ 3888 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3889 3890 return 0; 3891 } 3892 3893 static int rtl8169_init_ring(struct rtl8169_private *tp) 3894 { 3895 rtl8169_init_ring_indexes(tp); 3896 3897 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3898 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3899 3900 return rtl8169_rx_fill(tp); 3901 } 3902 3903 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3904 { 3905 struct ring_info *tx_skb = tp->tx_skb + entry; 3906 struct TxDesc *desc = tp->TxDescArray + entry; 3907 3908 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3909 DMA_TO_DEVICE); 3910 memset(desc, 0, sizeof(*desc)); 3911 memset(tx_skb, 0, sizeof(*tx_skb)); 3912 } 3913 3914 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3915 unsigned int n) 3916 { 3917 unsigned int i; 3918 3919 for (i = 0; i < n; i++) { 3920 unsigned int entry = (start + i) % NUM_TX_DESC; 3921 struct ring_info *tx_skb = tp->tx_skb + entry; 3922 unsigned int len = tx_skb->len; 3923 3924 if (len) { 3925 struct sk_buff *skb = tx_skb->skb; 3926 3927 rtl8169_unmap_tx_skb(tp, entry); 3928 if (skb) 3929 dev_consume_skb_any(skb); 3930 } 3931 } 3932 } 3933 3934 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3935 { 3936 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3937 netdev_reset_queue(tp->dev); 3938 } 3939 3940 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3941 { 3942 napi_disable(&tp->napi); 3943 3944 /* Give a racing hard_start_xmit a few cycles to complete. */ 3945 synchronize_net(); 3946 3947 /* Disable interrupts */ 3948 rtl8169_irq_mask_and_ack(tp); 3949 3950 rtl_rx_close(tp); 3951 3952 if (going_down && tp->dev->wol_enabled) 3953 goto no_reset; 3954 3955 switch (tp->mac_version) { 3956 case RTL_GIGA_MAC_VER_27: 3957 case RTL_GIGA_MAC_VER_28: 3958 case RTL_GIGA_MAC_VER_31: 3959 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3960 break; 3961 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3962 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3963 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3964 break; 3965 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3966 rtl_enable_rxdvgate(tp); 3967 fsleep(2000); 3968 break; 3969 default: 3970 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3971 fsleep(100); 3972 break; 3973 } 3974 3975 rtl_hw_reset(tp); 3976 no_reset: 3977 rtl8169_tx_clear(tp); 3978 rtl8169_init_ring_indexes(tp); 3979 } 3980 3981 static void rtl_reset_work(struct rtl8169_private *tp) 3982 { 3983 int i; 3984 3985 netif_stop_queue(tp->dev); 3986 3987 rtl8169_cleanup(tp, false); 3988 3989 for (i = 0; i < NUM_RX_DESC; i++) 3990 rtl8169_mark_to_asic(tp->RxDescArray + i); 3991 3992 napi_enable(&tp->napi); 3993 rtl_hw_start(tp); 3994 } 3995 3996 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3997 { 3998 struct rtl8169_private *tp = netdev_priv(dev); 3999 4000 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4001 } 4002 4003 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4004 void *addr, unsigned int entry, bool desc_own) 4005 { 4006 struct TxDesc *txd = tp->TxDescArray + entry; 4007 struct device *d = tp_to_dev(tp); 4008 dma_addr_t mapping; 4009 u32 opts1; 4010 int ret; 4011 4012 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4013 ret = dma_mapping_error(d, mapping); 4014 if (unlikely(ret)) { 4015 if (net_ratelimit()) 4016 netdev_err(tp->dev, "Failed to map TX data!\n"); 4017 return ret; 4018 } 4019 4020 txd->addr = cpu_to_le64(mapping); 4021 txd->opts2 = cpu_to_le32(opts[1]); 4022 4023 opts1 = opts[0] | len; 4024 if (entry == NUM_TX_DESC - 1) 4025 opts1 |= RingEnd; 4026 if (desc_own) 4027 opts1 |= DescOwn; 4028 txd->opts1 = cpu_to_le32(opts1); 4029 4030 tp->tx_skb[entry].len = len; 4031 4032 return 0; 4033 } 4034 4035 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4036 const u32 *opts, unsigned int entry) 4037 { 4038 struct skb_shared_info *info = skb_shinfo(skb); 4039 unsigned int cur_frag; 4040 4041 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4042 const skb_frag_t *frag = info->frags + cur_frag; 4043 void *addr = skb_frag_address(frag); 4044 u32 len = skb_frag_size(frag); 4045 4046 entry = (entry + 1) % NUM_TX_DESC; 4047 4048 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4049 goto err_out; 4050 } 4051 4052 return 0; 4053 4054 err_out: 4055 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4056 return -EIO; 4057 } 4058 4059 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 4060 { 4061 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 4062 } 4063 4064 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4065 { 4066 u32 mss = skb_shinfo(skb)->gso_size; 4067 4068 if (mss) { 4069 opts[0] |= TD_LSO; 4070 opts[0] |= mss << TD0_MSS_SHIFT; 4071 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4072 const struct iphdr *ip = ip_hdr(skb); 4073 4074 if (ip->protocol == IPPROTO_TCP) 4075 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4076 else if (ip->protocol == IPPROTO_UDP) 4077 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4078 else 4079 WARN_ON_ONCE(1); 4080 } 4081 } 4082 4083 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4084 struct sk_buff *skb, u32 *opts) 4085 { 4086 u32 transport_offset = (u32)skb_transport_offset(skb); 4087 struct skb_shared_info *shinfo = skb_shinfo(skb); 4088 u32 mss = shinfo->gso_size; 4089 4090 if (mss) { 4091 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4092 opts[0] |= TD1_GTSENV4; 4093 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4094 if (skb_cow_head(skb, 0)) 4095 return false; 4096 4097 tcp_v6_gso_csum_prep(skb); 4098 opts[0] |= TD1_GTSENV6; 4099 } else { 4100 WARN_ON_ONCE(1); 4101 } 4102 4103 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4104 opts[1] |= mss << TD1_MSS_SHIFT; 4105 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4106 u8 ip_protocol; 4107 4108 switch (vlan_get_protocol(skb)) { 4109 case htons(ETH_P_IP): 4110 opts[1] |= TD1_IPv4_CS; 4111 ip_protocol = ip_hdr(skb)->protocol; 4112 break; 4113 4114 case htons(ETH_P_IPV6): 4115 opts[1] |= TD1_IPv6_CS; 4116 ip_protocol = ipv6_hdr(skb)->nexthdr; 4117 break; 4118 4119 default: 4120 ip_protocol = IPPROTO_RAW; 4121 break; 4122 } 4123 4124 if (ip_protocol == IPPROTO_TCP) 4125 opts[1] |= TD1_TCP_CS; 4126 else if (ip_protocol == IPPROTO_UDP) 4127 opts[1] |= TD1_UDP_CS; 4128 else 4129 WARN_ON_ONCE(1); 4130 4131 opts[1] |= transport_offset << TCPHO_SHIFT; 4132 } else { 4133 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 4134 return !eth_skb_pad(skb); 4135 } 4136 4137 return true; 4138 } 4139 4140 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4141 unsigned int nr_frags) 4142 { 4143 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4144 4145 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4146 return slots_avail > nr_frags; 4147 } 4148 4149 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4150 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4151 { 4152 switch (tp->mac_version) { 4153 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4154 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4155 return false; 4156 default: 4157 return true; 4158 } 4159 } 4160 4161 static void rtl8169_doorbell(struct rtl8169_private *tp) 4162 { 4163 if (rtl_is_8125(tp)) 4164 RTL_W16(tp, TxPoll_8125, BIT(0)); 4165 else 4166 RTL_W8(tp, TxPoll, NPQ); 4167 } 4168 4169 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4170 struct net_device *dev) 4171 { 4172 unsigned int frags = skb_shinfo(skb)->nr_frags; 4173 struct rtl8169_private *tp = netdev_priv(dev); 4174 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4175 struct TxDesc *txd_first, *txd_last; 4176 bool stop_queue, door_bell; 4177 u32 opts[2]; 4178 4179 txd_first = tp->TxDescArray + entry; 4180 4181 if (unlikely(!rtl_tx_slots_avail(tp, frags))) { 4182 if (net_ratelimit()) 4183 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4184 goto err_stop_0; 4185 } 4186 4187 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn)) 4188 goto err_stop_0; 4189 4190 opts[1] = rtl8169_tx_vlan_tag(skb); 4191 opts[0] = 0; 4192 4193 if (!rtl_chip_supports_csum_v2(tp)) 4194 rtl8169_tso_csum_v1(skb, opts); 4195 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4196 goto err_dma_0; 4197 4198 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4199 entry, false))) 4200 goto err_dma_0; 4201 4202 if (frags) { 4203 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4204 goto err_dma_1; 4205 entry = (entry + frags) % NUM_TX_DESC; 4206 } 4207 4208 txd_last = tp->TxDescArray + entry; 4209 txd_last->opts1 |= cpu_to_le32(LastFrag); 4210 tp->tx_skb[entry].skb = skb; 4211 4212 skb_tx_timestamp(skb); 4213 4214 /* Force memory writes to complete before releasing descriptor */ 4215 dma_wmb(); 4216 4217 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4218 4219 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4220 4221 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4222 smp_wmb(); 4223 4224 tp->cur_tx += frags + 1; 4225 4226 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4227 if (unlikely(stop_queue)) { 4228 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4229 * not miss a ring update when it notices a stopped queue. 4230 */ 4231 smp_wmb(); 4232 netif_stop_queue(dev); 4233 door_bell = true; 4234 } 4235 4236 if (door_bell) 4237 rtl8169_doorbell(tp); 4238 4239 if (unlikely(stop_queue)) { 4240 /* Sync with rtl_tx: 4241 * - publish queue status and cur_tx ring index (write barrier) 4242 * - refresh dirty_tx ring index (read barrier). 4243 * May the current thread have a pessimistic view of the ring 4244 * status and forget to wake up queue, a racing rtl_tx thread 4245 * can't. 4246 */ 4247 smp_mb(); 4248 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4249 netif_start_queue(dev); 4250 } 4251 4252 return NETDEV_TX_OK; 4253 4254 err_dma_1: 4255 rtl8169_unmap_tx_skb(tp, entry); 4256 err_dma_0: 4257 dev_kfree_skb_any(skb); 4258 dev->stats.tx_dropped++; 4259 return NETDEV_TX_OK; 4260 4261 err_stop_0: 4262 netif_stop_queue(dev); 4263 dev->stats.tx_dropped++; 4264 return NETDEV_TX_BUSY; 4265 } 4266 4267 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4268 { 4269 struct skb_shared_info *info = skb_shinfo(skb); 4270 unsigned int nr_frags = info->nr_frags; 4271 4272 if (!nr_frags) 4273 return UINT_MAX; 4274 4275 return skb_frag_size(info->frags + nr_frags - 1); 4276 } 4277 4278 /* Workaround for hw issues with TSO on RTL8168evl */ 4279 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4280 netdev_features_t features) 4281 { 4282 /* IPv4 header has options field */ 4283 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4284 ip_hdrlen(skb) > sizeof(struct iphdr)) 4285 features &= ~NETIF_F_ALL_TSO; 4286 4287 /* IPv4 TCP header has options field */ 4288 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4289 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4290 features &= ~NETIF_F_ALL_TSO; 4291 4292 else if (rtl_last_frag_len(skb) <= 6) 4293 features &= ~NETIF_F_ALL_TSO; 4294 4295 return features; 4296 } 4297 4298 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4299 struct net_device *dev, 4300 netdev_features_t features) 4301 { 4302 int transport_offset = skb_transport_offset(skb); 4303 struct rtl8169_private *tp = netdev_priv(dev); 4304 4305 if (skb_is_gso(skb)) { 4306 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4307 features = rtl8168evl_fix_tso(skb, features); 4308 4309 if (transport_offset > GTTCPHO_MAX && 4310 rtl_chip_supports_csum_v2(tp)) 4311 features &= ~NETIF_F_ALL_TSO; 4312 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4313 if (skb->len < ETH_ZLEN) { 4314 switch (tp->mac_version) { 4315 case RTL_GIGA_MAC_VER_11: 4316 case RTL_GIGA_MAC_VER_12: 4317 case RTL_GIGA_MAC_VER_17: 4318 case RTL_GIGA_MAC_VER_34: 4319 features &= ~NETIF_F_CSUM_MASK; 4320 break; 4321 default: 4322 break; 4323 } 4324 } 4325 4326 if (transport_offset > TCPHO_MAX && 4327 rtl_chip_supports_csum_v2(tp)) 4328 features &= ~NETIF_F_CSUM_MASK; 4329 } 4330 4331 return vlan_features_check(skb, features); 4332 } 4333 4334 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4335 { 4336 struct rtl8169_private *tp = netdev_priv(dev); 4337 struct pci_dev *pdev = tp->pci_dev; 4338 int pci_status_errs; 4339 u16 pci_cmd; 4340 4341 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4342 4343 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4344 4345 if (net_ratelimit()) 4346 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4347 pci_cmd, pci_status_errs); 4348 /* 4349 * The recovery sequence below admits a very elaborated explanation: 4350 * - it seems to work; 4351 * - I did not see what else could be done; 4352 * - it makes iop3xx happy. 4353 * 4354 * Feel free to adjust to your needs. 4355 */ 4356 if (pdev->broken_parity_status) 4357 pci_cmd &= ~PCI_COMMAND_PARITY; 4358 else 4359 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4360 4361 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4362 4363 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4364 } 4365 4366 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4367 int budget) 4368 { 4369 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4370 4371 dirty_tx = tp->dirty_tx; 4372 smp_rmb(); 4373 4374 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) { 4375 unsigned int entry = dirty_tx % NUM_TX_DESC; 4376 struct sk_buff *skb = tp->tx_skb[entry].skb; 4377 u32 status; 4378 4379 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4380 if (status & DescOwn) 4381 break; 4382 4383 rtl8169_unmap_tx_skb(tp, entry); 4384 4385 if (skb) { 4386 pkts_compl++; 4387 bytes_compl += skb->len; 4388 napi_consume_skb(skb, budget); 4389 } 4390 dirty_tx++; 4391 } 4392 4393 if (tp->dirty_tx != dirty_tx) { 4394 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4395 4396 u64_stats_update_begin(&tp->tx_stats.syncp); 4397 tp->tx_stats.packets += pkts_compl; 4398 tp->tx_stats.bytes += bytes_compl; 4399 u64_stats_update_end(&tp->tx_stats.syncp); 4400 4401 tp->dirty_tx = dirty_tx; 4402 /* Sync with rtl8169_start_xmit: 4403 * - publish dirty_tx ring index (write barrier) 4404 * - refresh cur_tx ring index and queue status (read barrier) 4405 * May the current thread miss the stopped queue condition, 4406 * a racing xmit thread can only have a right view of the 4407 * ring status. 4408 */ 4409 smp_mb(); 4410 if (netif_queue_stopped(dev) && 4411 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4412 netif_wake_queue(dev); 4413 } 4414 /* 4415 * 8168 hack: TxPoll requests are lost when the Tx packets are 4416 * too close. Let's kick an extra TxPoll request when a burst 4417 * of start_xmit activity is detected (if it is not detected, 4418 * it is slow enough). -- FR 4419 */ 4420 if (tp->cur_tx != dirty_tx) 4421 rtl8169_doorbell(tp); 4422 } 4423 } 4424 4425 static inline int rtl8169_fragmented_frame(u32 status) 4426 { 4427 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4428 } 4429 4430 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4431 { 4432 u32 status = opts1 & RxProtoMask; 4433 4434 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4435 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4436 skb->ip_summed = CHECKSUM_UNNECESSARY; 4437 else 4438 skb_checksum_none_assert(skb); 4439 } 4440 4441 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4442 { 4443 unsigned int cur_rx, rx_left, count; 4444 struct device *d = tp_to_dev(tp); 4445 4446 cur_rx = tp->cur_rx; 4447 4448 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4449 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC; 4450 struct RxDesc *desc = tp->RxDescArray + entry; 4451 struct sk_buff *skb; 4452 const void *rx_buf; 4453 dma_addr_t addr; 4454 u32 status; 4455 4456 status = le32_to_cpu(desc->opts1); 4457 if (status & DescOwn) 4458 break; 4459 4460 /* This barrier is needed to keep us from reading 4461 * any other fields out of the Rx descriptor until 4462 * we know the status of DescOwn 4463 */ 4464 dma_rmb(); 4465 4466 if (unlikely(status & RxRES)) { 4467 if (net_ratelimit()) 4468 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4469 status); 4470 dev->stats.rx_errors++; 4471 if (status & (RxRWT | RxRUNT)) 4472 dev->stats.rx_length_errors++; 4473 if (status & RxCRC) 4474 dev->stats.rx_crc_errors++; 4475 4476 if (!(dev->features & NETIF_F_RXALL)) 4477 goto release_descriptor; 4478 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4479 goto release_descriptor; 4480 } 4481 4482 pkt_size = status & GENMASK(13, 0); 4483 if (likely(!(dev->features & NETIF_F_RXFCS))) 4484 pkt_size -= ETH_FCS_LEN; 4485 4486 /* The driver does not support incoming fragmented frames. 4487 * They are seen as a symptom of over-mtu sized frames. 4488 */ 4489 if (unlikely(rtl8169_fragmented_frame(status))) { 4490 dev->stats.rx_dropped++; 4491 dev->stats.rx_length_errors++; 4492 goto release_descriptor; 4493 } 4494 4495 skb = napi_alloc_skb(&tp->napi, pkt_size); 4496 if (unlikely(!skb)) { 4497 dev->stats.rx_dropped++; 4498 goto release_descriptor; 4499 } 4500 4501 addr = le64_to_cpu(desc->addr); 4502 rx_buf = page_address(tp->Rx_databuff[entry]); 4503 4504 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4505 prefetch(rx_buf); 4506 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4507 skb->tail += pkt_size; 4508 skb->len = pkt_size; 4509 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4510 4511 rtl8169_rx_csum(skb, status); 4512 skb->protocol = eth_type_trans(skb, dev); 4513 4514 rtl8169_rx_vlan_tag(desc, skb); 4515 4516 if (skb->pkt_type == PACKET_MULTICAST) 4517 dev->stats.multicast++; 4518 4519 napi_gro_receive(&tp->napi, skb); 4520 4521 u64_stats_update_begin(&tp->rx_stats.syncp); 4522 tp->rx_stats.packets++; 4523 tp->rx_stats.bytes += pkt_size; 4524 u64_stats_update_end(&tp->rx_stats.syncp); 4525 4526 release_descriptor: 4527 rtl8169_mark_to_asic(desc); 4528 } 4529 4530 count = cur_rx - tp->cur_rx; 4531 tp->cur_rx = cur_rx; 4532 4533 return count; 4534 } 4535 4536 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4537 { 4538 struct rtl8169_private *tp = dev_instance; 4539 u32 status = rtl_get_events(tp); 4540 4541 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4542 return IRQ_NONE; 4543 4544 if (unlikely(status & SYSErr)) { 4545 rtl8169_pcierr_interrupt(tp->dev); 4546 goto out; 4547 } 4548 4549 if (status & LinkChg) 4550 phy_mac_interrupt(tp->phydev); 4551 4552 if (unlikely(status & RxFIFOOver && 4553 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4554 netif_stop_queue(tp->dev); 4555 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4556 } 4557 4558 rtl_irq_disable(tp); 4559 napi_schedule_irqoff(&tp->napi); 4560 out: 4561 rtl_ack_events(tp, status); 4562 4563 return IRQ_HANDLED; 4564 } 4565 4566 static void rtl_task(struct work_struct *work) 4567 { 4568 struct rtl8169_private *tp = 4569 container_of(work, struct rtl8169_private, wk.work); 4570 4571 rtnl_lock(); 4572 4573 if (!netif_running(tp->dev) || 4574 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4575 goto out_unlock; 4576 4577 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4578 rtl_reset_work(tp); 4579 netif_wake_queue(tp->dev); 4580 } 4581 out_unlock: 4582 rtnl_unlock(); 4583 } 4584 4585 static int rtl8169_poll(struct napi_struct *napi, int budget) 4586 { 4587 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4588 struct net_device *dev = tp->dev; 4589 int work_done; 4590 4591 work_done = rtl_rx(dev, tp, (u32) budget); 4592 4593 rtl_tx(dev, tp, budget); 4594 4595 if (work_done < budget && napi_complete_done(napi, work_done)) 4596 rtl_irq_enable(tp); 4597 4598 return work_done; 4599 } 4600 4601 static void r8169_phylink_handler(struct net_device *ndev) 4602 { 4603 struct rtl8169_private *tp = netdev_priv(ndev); 4604 4605 if (netif_carrier_ok(ndev)) { 4606 rtl_link_chg_patch(tp); 4607 pm_request_resume(&tp->pci_dev->dev); 4608 } else { 4609 pm_runtime_idle(&tp->pci_dev->dev); 4610 } 4611 4612 if (net_ratelimit()) 4613 phy_print_status(tp->phydev); 4614 } 4615 4616 static int r8169_phy_connect(struct rtl8169_private *tp) 4617 { 4618 struct phy_device *phydev = tp->phydev; 4619 phy_interface_t phy_mode; 4620 int ret; 4621 4622 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4623 PHY_INTERFACE_MODE_MII; 4624 4625 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4626 phy_mode); 4627 if (ret) 4628 return ret; 4629 4630 if (!tp->supports_gmii) 4631 phy_set_max_speed(phydev, SPEED_100); 4632 4633 phy_support_asym_pause(phydev); 4634 4635 phy_attached_info(phydev); 4636 4637 return 0; 4638 } 4639 4640 static void rtl8169_down(struct rtl8169_private *tp) 4641 { 4642 /* Clear all task flags */ 4643 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4644 4645 phy_stop(tp->phydev); 4646 4647 rtl8169_update_counters(tp); 4648 4649 rtl8169_cleanup(tp, true); 4650 4651 rtl_pll_power_down(tp); 4652 } 4653 4654 static void rtl8169_up(struct rtl8169_private *tp) 4655 { 4656 rtl_pll_power_up(tp); 4657 rtl8169_init_phy(tp); 4658 napi_enable(&tp->napi); 4659 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4660 rtl_reset_work(tp); 4661 4662 phy_start(tp->phydev); 4663 } 4664 4665 static int rtl8169_close(struct net_device *dev) 4666 { 4667 struct rtl8169_private *tp = netdev_priv(dev); 4668 struct pci_dev *pdev = tp->pci_dev; 4669 4670 pm_runtime_get_sync(&pdev->dev); 4671 4672 netif_stop_queue(dev); 4673 rtl8169_down(tp); 4674 rtl8169_rx_clear(tp); 4675 4676 cancel_work_sync(&tp->wk.work); 4677 4678 phy_disconnect(tp->phydev); 4679 4680 pci_free_irq(pdev, 0, tp); 4681 4682 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4683 tp->RxPhyAddr); 4684 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4685 tp->TxPhyAddr); 4686 tp->TxDescArray = NULL; 4687 tp->RxDescArray = NULL; 4688 4689 pm_runtime_put_sync(&pdev->dev); 4690 4691 return 0; 4692 } 4693 4694 #ifdef CONFIG_NET_POLL_CONTROLLER 4695 static void rtl8169_netpoll(struct net_device *dev) 4696 { 4697 struct rtl8169_private *tp = netdev_priv(dev); 4698 4699 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4700 } 4701 #endif 4702 4703 static int rtl_open(struct net_device *dev) 4704 { 4705 struct rtl8169_private *tp = netdev_priv(dev); 4706 struct pci_dev *pdev = tp->pci_dev; 4707 int retval = -ENOMEM; 4708 4709 pm_runtime_get_sync(&pdev->dev); 4710 4711 /* 4712 * Rx and Tx descriptors needs 256 bytes alignment. 4713 * dma_alloc_coherent provides more. 4714 */ 4715 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4716 &tp->TxPhyAddr, GFP_KERNEL); 4717 if (!tp->TxDescArray) 4718 goto err_pm_runtime_put; 4719 4720 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4721 &tp->RxPhyAddr, GFP_KERNEL); 4722 if (!tp->RxDescArray) 4723 goto err_free_tx_0; 4724 4725 retval = rtl8169_init_ring(tp); 4726 if (retval < 0) 4727 goto err_free_rx_1; 4728 4729 rtl_request_firmware(tp); 4730 4731 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 4732 dev->name); 4733 if (retval < 0) 4734 goto err_release_fw_2; 4735 4736 retval = r8169_phy_connect(tp); 4737 if (retval) 4738 goto err_free_irq; 4739 4740 rtl8169_up(tp); 4741 rtl8169_init_counter_offsets(tp); 4742 netif_start_queue(dev); 4743 4744 pm_runtime_put_sync(&pdev->dev); 4745 out: 4746 return retval; 4747 4748 err_free_irq: 4749 pci_free_irq(pdev, 0, tp); 4750 err_release_fw_2: 4751 rtl_release_firmware(tp); 4752 rtl8169_rx_clear(tp); 4753 err_free_rx_1: 4754 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4755 tp->RxPhyAddr); 4756 tp->RxDescArray = NULL; 4757 err_free_tx_0: 4758 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4759 tp->TxPhyAddr); 4760 tp->TxDescArray = NULL; 4761 err_pm_runtime_put: 4762 pm_runtime_put_noidle(&pdev->dev); 4763 goto out; 4764 } 4765 4766 static void 4767 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4768 { 4769 struct rtl8169_private *tp = netdev_priv(dev); 4770 struct pci_dev *pdev = tp->pci_dev; 4771 struct rtl8169_counters *counters = tp->counters; 4772 unsigned int start; 4773 4774 pm_runtime_get_noresume(&pdev->dev); 4775 4776 netdev_stats_to_stats64(stats, &dev->stats); 4777 4778 do { 4779 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 4780 stats->rx_packets = tp->rx_stats.packets; 4781 stats->rx_bytes = tp->rx_stats.bytes; 4782 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 4783 4784 do { 4785 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 4786 stats->tx_packets = tp->tx_stats.packets; 4787 stats->tx_bytes = tp->tx_stats.bytes; 4788 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 4789 4790 /* 4791 * Fetch additional counter values missing in stats collected by driver 4792 * from tally counters. 4793 */ 4794 if (pm_runtime_active(&pdev->dev)) 4795 rtl8169_update_counters(tp); 4796 4797 /* 4798 * Subtract values fetched during initalization. 4799 * See rtl8169_init_counter_offsets for a description why we do that. 4800 */ 4801 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4802 le64_to_cpu(tp->tc_offset.tx_errors); 4803 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4804 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4805 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4806 le16_to_cpu(tp->tc_offset.tx_aborted); 4807 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4808 le16_to_cpu(tp->tc_offset.rx_missed); 4809 4810 pm_runtime_put_noidle(&pdev->dev); 4811 } 4812 4813 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4814 { 4815 netif_device_detach(tp->dev); 4816 4817 if (netif_running(tp->dev)) 4818 rtl8169_down(tp); 4819 } 4820 4821 #ifdef CONFIG_PM 4822 4823 static int __maybe_unused rtl8169_suspend(struct device *device) 4824 { 4825 struct rtl8169_private *tp = dev_get_drvdata(device); 4826 4827 rtnl_lock(); 4828 rtl8169_net_suspend(tp); 4829 rtnl_unlock(); 4830 4831 return 0; 4832 } 4833 4834 static int rtl8169_resume(struct device *device) 4835 { 4836 struct rtl8169_private *tp = dev_get_drvdata(device); 4837 4838 rtl_rar_set(tp, tp->dev->dev_addr); 4839 4840 if (tp->TxDescArray) 4841 rtl8169_up(tp); 4842 4843 netif_device_attach(tp->dev); 4844 4845 return 0; 4846 } 4847 4848 static int rtl8169_runtime_suspend(struct device *device) 4849 { 4850 struct rtl8169_private *tp = dev_get_drvdata(device); 4851 4852 if (!tp->TxDescArray) { 4853 netif_device_detach(tp->dev); 4854 return 0; 4855 } 4856 4857 rtnl_lock(); 4858 __rtl8169_set_wol(tp, WAKE_PHY); 4859 rtl8169_net_suspend(tp); 4860 rtnl_unlock(); 4861 4862 return 0; 4863 } 4864 4865 static int rtl8169_runtime_resume(struct device *device) 4866 { 4867 struct rtl8169_private *tp = dev_get_drvdata(device); 4868 4869 __rtl8169_set_wol(tp, tp->saved_wolopts); 4870 4871 return rtl8169_resume(device); 4872 } 4873 4874 static int rtl8169_runtime_idle(struct device *device) 4875 { 4876 struct rtl8169_private *tp = dev_get_drvdata(device); 4877 4878 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4879 pm_schedule_suspend(device, 10000); 4880 4881 return -EBUSY; 4882 } 4883 4884 static const struct dev_pm_ops rtl8169_pm_ops = { 4885 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4886 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4887 rtl8169_runtime_idle) 4888 }; 4889 4890 #endif /* CONFIG_PM */ 4891 4892 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4893 { 4894 /* WoL fails with 8168b when the receiver is disabled. */ 4895 switch (tp->mac_version) { 4896 case RTL_GIGA_MAC_VER_11: 4897 case RTL_GIGA_MAC_VER_12: 4898 case RTL_GIGA_MAC_VER_17: 4899 pci_clear_master(tp->pci_dev); 4900 4901 RTL_W8(tp, ChipCmd, CmdRxEnb); 4902 rtl_pci_commit(tp); 4903 break; 4904 default: 4905 break; 4906 } 4907 } 4908 4909 static void rtl_shutdown(struct pci_dev *pdev) 4910 { 4911 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4912 4913 rtnl_lock(); 4914 rtl8169_net_suspend(tp); 4915 rtnl_unlock(); 4916 4917 /* Restore original MAC address */ 4918 rtl_rar_set(tp, tp->dev->perm_addr); 4919 4920 if (system_state == SYSTEM_POWER_OFF) { 4921 if (tp->saved_wolopts) { 4922 rtl_wol_suspend_quirk(tp); 4923 rtl_wol_shutdown_quirk(tp); 4924 } 4925 4926 pci_wake_from_d3(pdev, true); 4927 pci_set_power_state(pdev, PCI_D3hot); 4928 } 4929 } 4930 4931 static void rtl_remove_one(struct pci_dev *pdev) 4932 { 4933 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4934 4935 if (pci_dev_run_wake(pdev)) 4936 pm_runtime_get_noresume(&pdev->dev); 4937 4938 unregister_netdev(tp->dev); 4939 4940 if (r8168_check_dash(tp)) 4941 rtl8168_driver_stop(tp); 4942 4943 rtl_release_firmware(tp); 4944 4945 /* restore original MAC address */ 4946 rtl_rar_set(tp, tp->dev->perm_addr); 4947 } 4948 4949 static const struct net_device_ops rtl_netdev_ops = { 4950 .ndo_open = rtl_open, 4951 .ndo_stop = rtl8169_close, 4952 .ndo_get_stats64 = rtl8169_get_stats64, 4953 .ndo_start_xmit = rtl8169_start_xmit, 4954 .ndo_features_check = rtl8169_features_check, 4955 .ndo_tx_timeout = rtl8169_tx_timeout, 4956 .ndo_validate_addr = eth_validate_addr, 4957 .ndo_change_mtu = rtl8169_change_mtu, 4958 .ndo_fix_features = rtl8169_fix_features, 4959 .ndo_set_features = rtl8169_set_features, 4960 .ndo_set_mac_address = rtl_set_mac_address, 4961 .ndo_do_ioctl = phy_do_ioctl_running, 4962 .ndo_set_rx_mode = rtl_set_rx_mode, 4963 #ifdef CONFIG_NET_POLL_CONTROLLER 4964 .ndo_poll_controller = rtl8169_netpoll, 4965 #endif 4966 4967 }; 4968 4969 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4970 { 4971 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4972 4973 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4974 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4975 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4976 /* special workaround needed */ 4977 tp->irq_mask |= RxFIFOOver; 4978 else 4979 tp->irq_mask |= RxOverflow; 4980 } 4981 4982 static int rtl_alloc_irq(struct rtl8169_private *tp) 4983 { 4984 unsigned int flags; 4985 4986 switch (tp->mac_version) { 4987 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4988 rtl_unlock_config_regs(tp); 4989 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4990 rtl_lock_config_regs(tp); 4991 fallthrough; 4992 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4993 flags = PCI_IRQ_LEGACY; 4994 break; 4995 default: 4996 flags = PCI_IRQ_ALL_TYPES; 4997 break; 4998 } 4999 5000 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5001 } 5002 5003 static void rtl_read_mac_address(struct rtl8169_private *tp, 5004 u8 mac_addr[ETH_ALEN]) 5005 { 5006 /* Get MAC address */ 5007 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5008 u32 value = rtl_eri_read(tp, 0xe0); 5009 5010 mac_addr[0] = (value >> 0) & 0xff; 5011 mac_addr[1] = (value >> 8) & 0xff; 5012 mac_addr[2] = (value >> 16) & 0xff; 5013 mac_addr[3] = (value >> 24) & 0xff; 5014 5015 value = rtl_eri_read(tp, 0xe4); 5016 mac_addr[4] = (value >> 0) & 0xff; 5017 mac_addr[5] = (value >> 8) & 0xff; 5018 } else if (rtl_is_8125(tp)) { 5019 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5020 } 5021 } 5022 5023 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5024 { 5025 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5026 } 5027 5028 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5029 { 5030 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5031 } 5032 5033 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5034 { 5035 struct rtl8169_private *tp = mii_bus->priv; 5036 5037 if (phyaddr > 0) 5038 return -ENODEV; 5039 5040 return rtl_readphy(tp, phyreg); 5041 } 5042 5043 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5044 int phyreg, u16 val) 5045 { 5046 struct rtl8169_private *tp = mii_bus->priv; 5047 5048 if (phyaddr > 0) 5049 return -ENODEV; 5050 5051 rtl_writephy(tp, phyreg, val); 5052 5053 return 0; 5054 } 5055 5056 static int r8169_mdio_register(struct rtl8169_private *tp) 5057 { 5058 struct pci_dev *pdev = tp->pci_dev; 5059 struct mii_bus *new_bus; 5060 int ret; 5061 5062 new_bus = devm_mdiobus_alloc(&pdev->dev); 5063 if (!new_bus) 5064 return -ENOMEM; 5065 5066 new_bus->name = "r8169"; 5067 new_bus->priv = tp; 5068 new_bus->parent = &pdev->dev; 5069 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5070 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5071 5072 new_bus->read = r8169_mdio_read_reg; 5073 new_bus->write = r8169_mdio_write_reg; 5074 5075 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5076 if (ret) 5077 return ret; 5078 5079 tp->phydev = mdiobus_get_phy(new_bus, 0); 5080 if (!tp->phydev) { 5081 return -ENODEV; 5082 } else if (!tp->phydev->drv) { 5083 /* Most chip versions fail with the genphy driver. 5084 * Therefore ensure that the dedicated PHY driver is loaded. 5085 */ 5086 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5087 tp->phydev->phy_id); 5088 return -EUNATCH; 5089 } 5090 5091 /* PHY will be woken up in rtl_open() */ 5092 phy_suspend(tp->phydev); 5093 5094 return 0; 5095 } 5096 5097 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5098 { 5099 rtl_enable_rxdvgate(tp); 5100 5101 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5102 msleep(1); 5103 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5104 5105 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5106 r8168g_wait_ll_share_fifo_ready(tp); 5107 5108 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5109 r8168g_wait_ll_share_fifo_ready(tp); 5110 } 5111 5112 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5113 { 5114 rtl_enable_rxdvgate(tp); 5115 5116 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5117 msleep(1); 5118 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5119 5120 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5121 r8168g_wait_ll_share_fifo_ready(tp); 5122 5123 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5124 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5125 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5126 r8168g_wait_ll_share_fifo_ready(tp); 5127 } 5128 5129 static void rtl_hw_initialize(struct rtl8169_private *tp) 5130 { 5131 switch (tp->mac_version) { 5132 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5133 rtl8168ep_stop_cmac(tp); 5134 fallthrough; 5135 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5136 rtl_hw_init_8168g(tp); 5137 break; 5138 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5139 rtl_hw_init_8125(tp); 5140 break; 5141 default: 5142 break; 5143 } 5144 } 5145 5146 static int rtl_jumbo_max(struct rtl8169_private *tp) 5147 { 5148 /* Non-GBit versions don't support jumbo frames */ 5149 if (!tp->supports_gmii) 5150 return 0; 5151 5152 switch (tp->mac_version) { 5153 /* RTL8169 */ 5154 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5155 return JUMBO_7K; 5156 /* RTL8168b */ 5157 case RTL_GIGA_MAC_VER_11: 5158 case RTL_GIGA_MAC_VER_12: 5159 case RTL_GIGA_MAC_VER_17: 5160 return JUMBO_4K; 5161 /* RTL8168c */ 5162 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5163 return JUMBO_6K; 5164 default: 5165 return JUMBO_9K; 5166 } 5167 } 5168 5169 static void rtl_disable_clk(void *data) 5170 { 5171 clk_disable_unprepare(data); 5172 } 5173 5174 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5175 { 5176 struct device *d = tp_to_dev(tp); 5177 struct clk *clk; 5178 int rc; 5179 5180 clk = devm_clk_get(d, "ether_clk"); 5181 if (IS_ERR(clk)) { 5182 rc = PTR_ERR(clk); 5183 if (rc == -ENOENT) 5184 /* clk-core allows NULL (for suspend / resume) */ 5185 rc = 0; 5186 else if (rc != -EPROBE_DEFER) 5187 dev_err(d, "failed to get clk: %d\n", rc); 5188 } else { 5189 tp->clk = clk; 5190 rc = clk_prepare_enable(clk); 5191 if (rc) 5192 dev_err(d, "failed to enable clk: %d\n", rc); 5193 else 5194 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5195 } 5196 5197 return rc; 5198 } 5199 5200 static void rtl_init_mac_address(struct rtl8169_private *tp) 5201 { 5202 struct net_device *dev = tp->dev; 5203 u8 *mac_addr = dev->dev_addr; 5204 int rc; 5205 5206 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5207 if (!rc) 5208 goto done; 5209 5210 rtl_read_mac_address(tp, mac_addr); 5211 if (is_valid_ether_addr(mac_addr)) 5212 goto done; 5213 5214 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5215 if (is_valid_ether_addr(mac_addr)) 5216 goto done; 5217 5218 eth_hw_addr_random(dev); 5219 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5220 done: 5221 rtl_rar_set(tp, mac_addr); 5222 } 5223 5224 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5225 { 5226 struct rtl8169_private *tp; 5227 int jumbo_max, region, rc; 5228 enum mac_version chipset; 5229 struct net_device *dev; 5230 u16 xid; 5231 5232 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5233 if (!dev) 5234 return -ENOMEM; 5235 5236 SET_NETDEV_DEV(dev, &pdev->dev); 5237 dev->netdev_ops = &rtl_netdev_ops; 5238 tp = netdev_priv(dev); 5239 tp->dev = dev; 5240 tp->pci_dev = pdev; 5241 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5242 tp->eee_adv = -1; 5243 tp->ocp_base = OCP_STD_PHY_BASE; 5244 5245 /* Get the *optional* external "ether_clk" used on some boards */ 5246 rc = rtl_get_ether_clk(tp); 5247 if (rc) 5248 return rc; 5249 5250 /* Disable ASPM completely as that cause random device stop working 5251 * problems as well as full system hangs for some PCIe devices users. 5252 */ 5253 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5254 PCIE_LINK_STATE_L1); 5255 tp->aspm_manageable = !rc; 5256 5257 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5258 rc = pcim_enable_device(pdev); 5259 if (rc < 0) { 5260 dev_err(&pdev->dev, "enable failure\n"); 5261 return rc; 5262 } 5263 5264 if (pcim_set_mwi(pdev) < 0) 5265 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5266 5267 /* use first MMIO region */ 5268 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5269 if (region < 0) { 5270 dev_err(&pdev->dev, "no MMIO resource found\n"); 5271 return -ENODEV; 5272 } 5273 5274 /* check for weird/broken PCI region reporting */ 5275 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5276 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5277 return -ENODEV; 5278 } 5279 5280 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5281 if (rc < 0) { 5282 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5283 return rc; 5284 } 5285 5286 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5287 5288 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5289 5290 /* Identify chip attached to board */ 5291 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5292 if (chipset == RTL_GIGA_MAC_NONE) { 5293 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid); 5294 return -ENODEV; 5295 } 5296 5297 tp->mac_version = chipset; 5298 5299 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5300 5301 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5302 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5303 dev->features |= NETIF_F_HIGHDMA; 5304 5305 rtl_init_rxcfg(tp); 5306 5307 rtl8169_irq_mask_and_ack(tp); 5308 5309 rtl_hw_initialize(tp); 5310 5311 rtl_hw_reset(tp); 5312 5313 pci_set_master(pdev); 5314 5315 rc = rtl_alloc_irq(tp); 5316 if (rc < 0) { 5317 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5318 return rc; 5319 } 5320 5321 INIT_WORK(&tp->wk.work, rtl_task); 5322 u64_stats_init(&tp->rx_stats.syncp); 5323 u64_stats_init(&tp->tx_stats.syncp); 5324 5325 rtl_init_mac_address(tp); 5326 5327 dev->ethtool_ops = &rtl8169_ethtool_ops; 5328 5329 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5330 5331 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5332 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5333 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5334 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5335 5336 /* 5337 * Pretend we are using VLANs; This bypasses a nasty bug where 5338 * Interrupts stop flowing on high load on 8110SCd controllers. 5339 */ 5340 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5341 /* Disallow toggling */ 5342 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5343 5344 if (rtl_chip_supports_csum_v2(tp)) 5345 dev->hw_features |= NETIF_F_IPV6_CSUM; 5346 5347 dev->features |= dev->hw_features; 5348 5349 /* There has been a number of reports that using SG/TSO results in 5350 * tx timeouts. However for a lot of people SG/TSO works fine. 5351 * Therefore disable both features by default, but allow users to 5352 * enable them. Use at own risk! 5353 */ 5354 if (rtl_chip_supports_csum_v2(tp)) { 5355 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5356 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5357 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5358 } else { 5359 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5360 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5361 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5362 } 5363 5364 dev->hw_features |= NETIF_F_RXALL; 5365 dev->hw_features |= NETIF_F_RXFCS; 5366 5367 /* configure chip for default features */ 5368 rtl8169_set_features(dev, dev->features); 5369 5370 jumbo_max = rtl_jumbo_max(tp); 5371 if (jumbo_max) 5372 dev->max_mtu = jumbo_max; 5373 5374 rtl_set_irq_mask(tp); 5375 5376 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5377 5378 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5379 &tp->counters_phys_addr, 5380 GFP_KERNEL); 5381 if (!tp->counters) 5382 return -ENOMEM; 5383 5384 pci_set_drvdata(pdev, tp); 5385 5386 rc = r8169_mdio_register(tp); 5387 if (rc) 5388 return rc; 5389 5390 /* chip gets powered up in rtl_open() */ 5391 rtl_pll_power_down(tp); 5392 5393 rc = register_netdev(dev); 5394 if (rc) 5395 return rc; 5396 5397 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5398 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5399 pci_irq_vector(pdev, 0)); 5400 5401 if (jumbo_max) 5402 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5403 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5404 "ok" : "ko"); 5405 5406 if (r8168_check_dash(tp)) { 5407 netdev_info(dev, "DASH enabled\n"); 5408 rtl8168_driver_start(tp); 5409 } 5410 5411 if (pci_dev_run_wake(pdev)) 5412 pm_runtime_put_sync(&pdev->dev); 5413 5414 return 0; 5415 } 5416 5417 static struct pci_driver rtl8169_pci_driver = { 5418 .name = MODULENAME, 5419 .id_table = rtl8169_pci_tbl, 5420 .probe = rtl_init_one, 5421 .remove = rtl_remove_one, 5422 .shutdown = rtl_shutdown, 5423 #ifdef CONFIG_PM 5424 .driver.pm = &rtl8169_pm_ops, 5425 #endif 5426 }; 5427 5428 module_pci_driver(rtl8169_pci_driver); 5429