1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 52 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 62 #define MC_FILTER_LIMIT 32 63 64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 66 67 #define R8169_REGS_SIZE 256 68 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 69 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 70 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 73 74 #define OCP_STD_PHY_BASE 0xa400 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 91 static const struct { 92 const char *name; 93 const char *fw_name; 94 } rtl_chip_infos[] = { 95 /* PCI devices. */ 96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 101 /* PCI-E devices. */ 102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 109 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 110 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 111 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 112 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 118 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 119 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 120 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 121 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 122 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 124 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 125 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 126 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 127 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 128 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 129 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 130 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 131 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 132 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 133 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 134 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 135 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 136 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 137 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 138 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 139 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 140 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 141 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 142 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 143 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 144 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 145 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 147 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 148 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 149 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 150 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 151 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 152 }; 153 154 static const struct pci_device_id rtl8169_pci_tbl[] = { 155 { PCI_VDEVICE(REALTEK, 0x2502) }, 156 { PCI_VDEVICE(REALTEK, 0x2600) }, 157 { PCI_VDEVICE(REALTEK, 0x8129) }, 158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 159 { PCI_VDEVICE(REALTEK, 0x8161) }, 160 { PCI_VDEVICE(REALTEK, 0x8167) }, 161 { PCI_VDEVICE(REALTEK, 0x8168) }, 162 { PCI_VDEVICE(NCUBE, 0x8168) }, 163 { PCI_VDEVICE(REALTEK, 0x8169) }, 164 { PCI_VENDOR_ID_DLINK, 0x4300, 165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 166 { PCI_VDEVICE(DLINK, 0x4300) }, 167 { PCI_VDEVICE(DLINK, 0x4302) }, 168 { PCI_VDEVICE(AT, 0xc107) }, 169 { PCI_VDEVICE(USR, 0x0116) }, 170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 172 { PCI_VDEVICE(REALTEK, 0x8125) }, 173 { PCI_VDEVICE(REALTEK, 0x3000) }, 174 {} 175 }; 176 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 178 179 enum rtl_registers { 180 MAC0 = 0, /* Ethernet hardware address. */ 181 MAC4 = 4, 182 MAR0 = 8, /* Multicast filter. */ 183 CounterAddrLow = 0x10, 184 CounterAddrHigh = 0x14, 185 TxDescStartAddrLow = 0x20, 186 TxDescStartAddrHigh = 0x24, 187 TxHDescStartAddrLow = 0x28, 188 TxHDescStartAddrHigh = 0x2c, 189 FLASH = 0x30, 190 ERSR = 0x36, 191 ChipCmd = 0x37, 192 TxPoll = 0x38, 193 IntrMask = 0x3c, 194 IntrStatus = 0x3e, 195 196 TxConfig = 0x40, 197 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 198 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 199 200 RxConfig = 0x44, 201 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 202 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 203 #define RXCFG_FIFO_SHIFT 13 204 /* No threshold before first PCI xfer */ 205 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 206 #define RX_EARLY_OFF (1 << 11) 207 #define RXCFG_DMA_SHIFT 8 208 /* Unlimited maximum PCI burst. */ 209 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 210 211 Cfg9346 = 0x50, 212 Config0 = 0x51, 213 Config1 = 0x52, 214 Config2 = 0x53, 215 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 216 217 Config3 = 0x54, 218 Config4 = 0x55, 219 Config5 = 0x56, 220 PHYAR = 0x60, 221 PHYstatus = 0x6c, 222 RxMaxSize = 0xda, 223 CPlusCmd = 0xe0, 224 IntrMitigate = 0xe2, 225 226 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 227 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 228 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 229 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 230 231 #define RTL_COALESCE_T_MAX 0x0fU 232 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 233 234 RxDescAddrLow = 0xe4, 235 RxDescAddrHigh = 0xe8, 236 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 237 238 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 239 240 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 241 242 #define TxPacketMax (8064 >> 7) 243 #define EarlySize 0x27 244 245 FuncEvent = 0xf0, 246 FuncEventMask = 0xf4, 247 FuncPresetState = 0xf8, 248 IBCR0 = 0xf8, 249 IBCR2 = 0xf9, 250 IBIMR0 = 0xfa, 251 IBISR0 = 0xfb, 252 FuncForceEvent = 0xfc, 253 }; 254 255 enum rtl8168_8101_registers { 256 CSIDR = 0x64, 257 CSIAR = 0x68, 258 #define CSIAR_FLAG 0x80000000 259 #define CSIAR_WRITE_CMD 0x80000000 260 #define CSIAR_BYTE_ENABLE 0x0000f000 261 #define CSIAR_ADDR_MASK 0x00000fff 262 PMCH = 0x6f, 263 #define D3COLD_NO_PLL_DOWN BIT(7) 264 #define D3HOT_NO_PLL_DOWN BIT(6) 265 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 266 EPHYAR = 0x80, 267 #define EPHYAR_FLAG 0x80000000 268 #define EPHYAR_WRITE_CMD 0x80000000 269 #define EPHYAR_REG_MASK 0x1f 270 #define EPHYAR_REG_SHIFT 16 271 #define EPHYAR_DATA_MASK 0xffff 272 DLLPR = 0xd0, 273 #define PFM_EN (1 << 6) 274 #define TX_10M_PS_EN (1 << 7) 275 DBG_REG = 0xd1, 276 #define FIX_NAK_1 (1 << 4) 277 #define FIX_NAK_2 (1 << 3) 278 TWSI = 0xd2, 279 MCU = 0xd3, 280 #define NOW_IS_OOB (1 << 7) 281 #define TX_EMPTY (1 << 5) 282 #define RX_EMPTY (1 << 4) 283 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 284 #define EN_NDP (1 << 3) 285 #define EN_OOB_RESET (1 << 2) 286 #define LINK_LIST_RDY (1 << 1) 287 EFUSEAR = 0xdc, 288 #define EFUSEAR_FLAG 0x80000000 289 #define EFUSEAR_WRITE_CMD 0x80000000 290 #define EFUSEAR_READ_CMD 0x00000000 291 #define EFUSEAR_REG_MASK 0x03ff 292 #define EFUSEAR_REG_SHIFT 8 293 #define EFUSEAR_DATA_MASK 0xff 294 MISC_1 = 0xf2, 295 #define PFM_D3COLD_EN (1 << 6) 296 }; 297 298 enum rtl8168_registers { 299 LED_FREQ = 0x1a, 300 EEE_LED = 0x1b, 301 ERIDR = 0x70, 302 ERIAR = 0x74, 303 #define ERIAR_FLAG 0x80000000 304 #define ERIAR_WRITE_CMD 0x80000000 305 #define ERIAR_READ_CMD 0x00000000 306 #define ERIAR_ADDR_BYTE_ALIGN 4 307 #define ERIAR_TYPE_SHIFT 16 308 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 310 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 312 #define ERIAR_MASK_SHIFT 12 313 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 315 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 317 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 318 EPHY_RXER_NUM = 0x7c, 319 OCPDR = 0xb0, /* OCP GPHY access */ 320 #define OCPDR_WRITE_CMD 0x80000000 321 #define OCPDR_READ_CMD 0x00000000 322 #define OCPDR_REG_MASK 0x7f 323 #define OCPDR_GPHY_REG_SHIFT 16 324 #define OCPDR_DATA_MASK 0xffff 325 OCPAR = 0xb4, 326 #define OCPAR_FLAG 0x80000000 327 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 328 #define OCPAR_GPHY_READ_CMD 0x0000f060 329 GPHY_OCP = 0xb8, 330 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 331 MISC = 0xf0, /* 8168e only. */ 332 #define TXPLA_RST (1 << 29) 333 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 334 #define PWM_EN (1 << 22) 335 #define RXDV_GATED_EN (1 << 19) 336 #define EARLY_TALLY_EN (1 << 16) 337 }; 338 339 enum rtl8125_registers { 340 IntrMask_8125 = 0x38, 341 IntrStatus_8125 = 0x3c, 342 TxPoll_8125 = 0x90, 343 MAC0_BKP = 0x19e0, 344 EEE_TXIDLE_TIMER_8125 = 0x6048, 345 }; 346 347 #define RX_VLAN_INNER_8125 BIT(22) 348 #define RX_VLAN_OUTER_8125 BIT(23) 349 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 350 351 #define RX_FETCH_DFLT_8125 (8 << 27) 352 353 enum rtl_register_content { 354 /* InterruptStatusBits */ 355 SYSErr = 0x8000, 356 PCSTimeout = 0x4000, 357 SWInt = 0x0100, 358 TxDescUnavail = 0x0080, 359 RxFIFOOver = 0x0040, 360 LinkChg = 0x0020, 361 RxOverflow = 0x0010, 362 TxErr = 0x0008, 363 TxOK = 0x0004, 364 RxErr = 0x0002, 365 RxOK = 0x0001, 366 367 /* RxStatusDesc */ 368 RxRWT = (1 << 22), 369 RxRES = (1 << 21), 370 RxRUNT = (1 << 20), 371 RxCRC = (1 << 19), 372 373 /* ChipCmdBits */ 374 StopReq = 0x80, 375 CmdReset = 0x10, 376 CmdRxEnb = 0x08, 377 CmdTxEnb = 0x04, 378 RxBufEmpty = 0x01, 379 380 /* TXPoll register p.5 */ 381 HPQ = 0x80, /* Poll cmd on the high prio queue */ 382 NPQ = 0x40, /* Poll cmd on the low prio queue */ 383 FSWInt = 0x01, /* Forced software interrupt */ 384 385 /* Cfg9346Bits */ 386 Cfg9346_Lock = 0x00, 387 Cfg9346_Unlock = 0xc0, 388 389 /* rx_mode_bits */ 390 AcceptErr = 0x20, 391 AcceptRunt = 0x10, 392 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 393 AcceptBroadcast = 0x08, 394 AcceptMulticast = 0x04, 395 AcceptMyPhys = 0x02, 396 AcceptAllPhys = 0x01, 397 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 398 #define RX_CONFIG_ACCEPT_MASK 0x3f 399 400 /* TxConfigBits */ 401 TxInterFrameGapShift = 24, 402 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 403 404 /* Config1 register p.24 */ 405 LEDS1 = (1 << 7), 406 LEDS0 = (1 << 6), 407 Speed_down = (1 << 4), 408 MEMMAP = (1 << 3), 409 IOMAP = (1 << 2), 410 VPD = (1 << 1), 411 PMEnable = (1 << 0), /* Power Management Enable */ 412 413 /* Config2 register p. 25 */ 414 ClkReqEn = (1 << 7), /* Clock Request Enable */ 415 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 416 PCI_Clock_66MHz = 0x01, 417 PCI_Clock_33MHz = 0x00, 418 419 /* Config3 register p.25 */ 420 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 421 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 422 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 423 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 424 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 425 426 /* Config4 register */ 427 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 428 429 /* Config5 register p.27 */ 430 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 431 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 432 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 433 Spi_en = (1 << 3), 434 LanWake = (1 << 1), /* LanWake enable/disable */ 435 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 436 ASPM_en = (1 << 0), /* ASPM enable */ 437 438 /* CPlusCmd p.31 */ 439 EnableBist = (1 << 15), // 8168 8101 440 Mac_dbgo_oe = (1 << 14), // 8168 8101 441 EnAnaPLL = (1 << 14), // 8169 442 Normal_mode = (1 << 13), // unused 443 Force_half_dup = (1 << 12), // 8168 8101 444 Force_rxflow_en = (1 << 11), // 8168 8101 445 Force_txflow_en = (1 << 10), // 8168 8101 446 Cxpl_dbg_sel = (1 << 9), // 8168 8101 447 ASF = (1 << 8), // 8168 8101 448 PktCntrDisable = (1 << 7), // 8168 8101 449 Mac_dbgo_sel = 0x001c, // 8168 450 RxVlan = (1 << 6), 451 RxChkSum = (1 << 5), 452 PCIDAC = (1 << 4), 453 PCIMulRW = (1 << 3), 454 #define INTT_MASK GENMASK(1, 0) 455 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 456 457 /* rtl8169_PHYstatus */ 458 TBI_Enable = 0x80, 459 TxFlowCtrl = 0x40, 460 RxFlowCtrl = 0x20, 461 _1000bpsF = 0x10, 462 _100bps = 0x08, 463 _10bps = 0x04, 464 LinkStatus = 0x02, 465 FullDup = 0x01, 466 467 /* ResetCounterCommand */ 468 CounterReset = 0x1, 469 470 /* DumpCounterCommand */ 471 CounterDump = 0x8, 472 473 /* magic enable v2 */ 474 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 475 }; 476 477 enum rtl_desc_bit { 478 /* First doubleword. */ 479 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 480 RingEnd = (1 << 30), /* End of descriptor ring */ 481 FirstFrag = (1 << 29), /* First segment of a packet */ 482 LastFrag = (1 << 28), /* Final segment of a packet */ 483 }; 484 485 /* Generic case. */ 486 enum rtl_tx_desc_bit { 487 /* First doubleword. */ 488 TD_LSO = (1 << 27), /* Large Send Offload */ 489 #define TD_MSS_MAX 0x07ffu /* MSS value */ 490 491 /* Second doubleword. */ 492 TxVlanTag = (1 << 17), /* Add VLAN tag */ 493 }; 494 495 /* 8169, 8168b and 810x except 8102e. */ 496 enum rtl_tx_desc_bit_0 { 497 /* First doubleword. */ 498 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 499 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 500 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 501 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 502 }; 503 504 /* 8102e, 8168c and beyond. */ 505 enum rtl_tx_desc_bit_1 { 506 /* First doubleword. */ 507 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 508 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 509 #define GTTCPHO_SHIFT 18 510 #define GTTCPHO_MAX 0x7f 511 512 /* Second doubleword. */ 513 #define TCPHO_SHIFT 18 514 #define TCPHO_MAX 0x3ff 515 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 516 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 517 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 518 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 519 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 520 }; 521 522 enum rtl_rx_desc_bit { 523 /* Rx private */ 524 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 525 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 526 527 #define RxProtoUDP (PID1) 528 #define RxProtoTCP (PID0) 529 #define RxProtoIP (PID1 | PID0) 530 #define RxProtoMask RxProtoIP 531 532 IPFail = (1 << 16), /* IP checksum failed */ 533 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 534 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 535 536 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 537 538 RxVlanTag = (1 << 16), /* VLAN tag available */ 539 }; 540 541 #define RTL_GSO_MAX_SIZE_V1 32000 542 #define RTL_GSO_MAX_SEGS_V1 24 543 #define RTL_GSO_MAX_SIZE_V2 64000 544 #define RTL_GSO_MAX_SEGS_V2 64 545 546 struct TxDesc { 547 __le32 opts1; 548 __le32 opts2; 549 __le64 addr; 550 }; 551 552 struct RxDesc { 553 __le32 opts1; 554 __le32 opts2; 555 __le64 addr; 556 }; 557 558 struct ring_info { 559 struct sk_buff *skb; 560 u32 len; 561 }; 562 563 struct rtl8169_counters { 564 __le64 tx_packets; 565 __le64 rx_packets; 566 __le64 tx_errors; 567 __le32 rx_errors; 568 __le16 rx_missed; 569 __le16 align_errors; 570 __le32 tx_one_collision; 571 __le32 tx_multi_collision; 572 __le64 rx_unicast; 573 __le64 rx_broadcast; 574 __le32 rx_multicast; 575 __le16 tx_aborted; 576 __le16 tx_underun; 577 }; 578 579 struct rtl8169_tc_offsets { 580 bool inited; 581 __le64 tx_errors; 582 __le32 tx_multi_collision; 583 __le16 tx_aborted; 584 __le16 rx_missed; 585 }; 586 587 enum rtl_flag { 588 RTL_FLAG_TASK_ENABLED = 0, 589 RTL_FLAG_TASK_RESET_PENDING, 590 RTL_FLAG_MAX 591 }; 592 593 enum rtl_dash_type { 594 RTL_DASH_NONE, 595 RTL_DASH_DP, 596 RTL_DASH_EP, 597 }; 598 599 struct rtl8169_private { 600 void __iomem *mmio_addr; /* memory map physical address */ 601 struct pci_dev *pci_dev; 602 struct net_device *dev; 603 struct phy_device *phydev; 604 struct napi_struct napi; 605 enum mac_version mac_version; 606 enum rtl_dash_type dash_type; 607 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 608 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 609 u32 dirty_tx; 610 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 611 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 612 dma_addr_t TxPhyAddr; 613 dma_addr_t RxPhyAddr; 614 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 615 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 616 u16 cp_cmd; 617 u32 irq_mask; 618 struct clk *clk; 619 620 struct { 621 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 622 struct work_struct work; 623 } wk; 624 625 unsigned supports_gmii:1; 626 unsigned aspm_manageable:1; 627 dma_addr_t counters_phys_addr; 628 struct rtl8169_counters *counters; 629 struct rtl8169_tc_offsets tc_offset; 630 u32 saved_wolopts; 631 int eee_adv; 632 633 const char *fw_name; 634 struct rtl_fw *rtl_fw; 635 636 u32 ocp_base; 637 }; 638 639 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 640 641 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 642 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 643 MODULE_SOFTDEP("pre: realtek"); 644 MODULE_LICENSE("GPL"); 645 MODULE_FIRMWARE(FIRMWARE_8168D_1); 646 MODULE_FIRMWARE(FIRMWARE_8168D_2); 647 MODULE_FIRMWARE(FIRMWARE_8168E_1); 648 MODULE_FIRMWARE(FIRMWARE_8168E_2); 649 MODULE_FIRMWARE(FIRMWARE_8168E_3); 650 MODULE_FIRMWARE(FIRMWARE_8105E_1); 651 MODULE_FIRMWARE(FIRMWARE_8168F_1); 652 MODULE_FIRMWARE(FIRMWARE_8168F_2); 653 MODULE_FIRMWARE(FIRMWARE_8402_1); 654 MODULE_FIRMWARE(FIRMWARE_8411_1); 655 MODULE_FIRMWARE(FIRMWARE_8411_2); 656 MODULE_FIRMWARE(FIRMWARE_8106E_1); 657 MODULE_FIRMWARE(FIRMWARE_8106E_2); 658 MODULE_FIRMWARE(FIRMWARE_8168G_2); 659 MODULE_FIRMWARE(FIRMWARE_8168G_3); 660 MODULE_FIRMWARE(FIRMWARE_8168H_1); 661 MODULE_FIRMWARE(FIRMWARE_8168H_2); 662 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 663 MODULE_FIRMWARE(FIRMWARE_8107E_1); 664 MODULE_FIRMWARE(FIRMWARE_8107E_2); 665 MODULE_FIRMWARE(FIRMWARE_8125A_3); 666 MODULE_FIRMWARE(FIRMWARE_8125B_2); 667 668 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 669 { 670 return &tp->pci_dev->dev; 671 } 672 673 static void rtl_lock_config_regs(struct rtl8169_private *tp) 674 { 675 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 676 } 677 678 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 679 { 680 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 681 } 682 683 static void rtl_pci_commit(struct rtl8169_private *tp) 684 { 685 /* Read an arbitrary register to commit a preceding PCI write */ 686 RTL_R8(tp, ChipCmd); 687 } 688 689 static bool rtl_is_8125(struct rtl8169_private *tp) 690 { 691 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 692 } 693 694 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 695 { 696 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 697 tp->mac_version != RTL_GIGA_MAC_VER_39 && 698 tp->mac_version <= RTL_GIGA_MAC_VER_53; 699 } 700 701 static bool rtl_supports_eee(struct rtl8169_private *tp) 702 { 703 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 704 tp->mac_version != RTL_GIGA_MAC_VER_37 && 705 tp->mac_version != RTL_GIGA_MAC_VER_39; 706 } 707 708 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 709 { 710 int i; 711 712 for (i = 0; i < ETH_ALEN; i++) 713 mac[i] = RTL_R8(tp, reg + i); 714 } 715 716 struct rtl_cond { 717 bool (*check)(struct rtl8169_private *); 718 const char *msg; 719 }; 720 721 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 722 unsigned long usecs, int n, bool high) 723 { 724 int i; 725 726 for (i = 0; i < n; i++) { 727 if (c->check(tp) == high) 728 return true; 729 fsleep(usecs); 730 } 731 732 if (net_ratelimit()) 733 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 734 c->msg, !high, n, usecs); 735 return false; 736 } 737 738 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 739 const struct rtl_cond *c, 740 unsigned long d, int n) 741 { 742 return rtl_loop_wait(tp, c, d, n, true); 743 } 744 745 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 746 const struct rtl_cond *c, 747 unsigned long d, int n) 748 { 749 return rtl_loop_wait(tp, c, d, n, false); 750 } 751 752 #define DECLARE_RTL_COND(name) \ 753 static bool name ## _check(struct rtl8169_private *); \ 754 \ 755 static const struct rtl_cond name = { \ 756 .check = name ## _check, \ 757 .msg = #name \ 758 }; \ 759 \ 760 static bool name ## _check(struct rtl8169_private *tp) 761 762 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 763 { 764 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 765 if (type == ERIAR_OOB && 766 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 767 tp->mac_version == RTL_GIGA_MAC_VER_53)) 768 *cmd |= 0xf70 << 18; 769 } 770 771 DECLARE_RTL_COND(rtl_eriar_cond) 772 { 773 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 774 } 775 776 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 777 u32 val, int type) 778 { 779 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 780 781 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 782 return; 783 784 RTL_W32(tp, ERIDR, val); 785 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 786 RTL_W32(tp, ERIAR, cmd); 787 788 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 789 } 790 791 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 792 u32 val) 793 { 794 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 795 } 796 797 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 798 { 799 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 800 801 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 802 RTL_W32(tp, ERIAR, cmd); 803 804 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 805 RTL_R32(tp, ERIDR) : ~0; 806 } 807 808 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 809 { 810 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 811 } 812 813 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 814 { 815 u32 val = rtl_eri_read(tp, addr); 816 817 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 818 } 819 820 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 821 { 822 rtl_w0w1_eri(tp, addr, p, 0); 823 } 824 825 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 826 { 827 rtl_w0w1_eri(tp, addr, 0, m); 828 } 829 830 static bool rtl_ocp_reg_failure(u32 reg) 831 { 832 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 833 } 834 835 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 836 { 837 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 838 } 839 840 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 841 { 842 if (rtl_ocp_reg_failure(reg)) 843 return; 844 845 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 846 847 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 848 } 849 850 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 851 { 852 if (rtl_ocp_reg_failure(reg)) 853 return 0; 854 855 RTL_W32(tp, GPHY_OCP, reg << 15); 856 857 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 858 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 859 } 860 861 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 862 { 863 if (rtl_ocp_reg_failure(reg)) 864 return; 865 866 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 867 } 868 869 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 870 { 871 if (rtl_ocp_reg_failure(reg)) 872 return 0; 873 874 RTL_W32(tp, OCPDR, reg << 15); 875 876 return RTL_R32(tp, OCPDR); 877 } 878 879 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 880 u16 set) 881 { 882 u16 data = r8168_mac_ocp_read(tp, reg); 883 884 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 885 } 886 887 /* Work around a hw issue with RTL8168g PHY, the quirk disables 888 * PHY MCU interrupts before PHY power-down. 889 */ 890 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 891 { 892 switch (tp->mac_version) { 893 case RTL_GIGA_MAC_VER_40: 894 case RTL_GIGA_MAC_VER_41: 895 case RTL_GIGA_MAC_VER_49: 896 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 897 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 898 else 899 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 900 break; 901 default: 902 break; 903 } 904 }; 905 906 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 907 { 908 if (reg == 0x1f) { 909 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 910 return; 911 } 912 913 if (tp->ocp_base != OCP_STD_PHY_BASE) 914 reg -= 0x10; 915 916 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 917 rtl8168g_phy_suspend_quirk(tp, value); 918 919 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 920 } 921 922 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 923 { 924 if (reg == 0x1f) 925 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 926 927 if (tp->ocp_base != OCP_STD_PHY_BASE) 928 reg -= 0x10; 929 930 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 931 } 932 933 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 934 { 935 if (reg == 0x1f) { 936 tp->ocp_base = value << 4; 937 return; 938 } 939 940 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 941 } 942 943 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 944 { 945 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 946 } 947 948 DECLARE_RTL_COND(rtl_phyar_cond) 949 { 950 return RTL_R32(tp, PHYAR) & 0x80000000; 951 } 952 953 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 954 { 955 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 956 957 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 958 /* 959 * According to hardware specs a 20us delay is required after write 960 * complete indication, but before sending next command. 961 */ 962 udelay(20); 963 } 964 965 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 966 { 967 int value; 968 969 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 970 971 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 972 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 973 974 /* 975 * According to hardware specs a 20us delay is required after read 976 * complete indication, but before sending next command. 977 */ 978 udelay(20); 979 980 return value; 981 } 982 983 DECLARE_RTL_COND(rtl_ocpar_cond) 984 { 985 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 986 } 987 988 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 989 { 990 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 991 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 992 RTL_W32(tp, EPHY_RXER_NUM, 0); 993 994 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 995 } 996 997 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 998 { 999 r8168dp_1_mdio_access(tp, reg, 1000 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 1001 } 1002 1003 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 1004 { 1005 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 1006 1007 mdelay(1); 1008 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1009 RTL_W32(tp, EPHY_RXER_NUM, 0); 1010 1011 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1012 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1013 } 1014 1015 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1016 1017 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1018 { 1019 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1020 } 1021 1022 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1023 { 1024 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1025 } 1026 1027 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1028 { 1029 r8168dp_2_mdio_start(tp); 1030 1031 r8169_mdio_write(tp, reg, value); 1032 1033 r8168dp_2_mdio_stop(tp); 1034 } 1035 1036 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1037 { 1038 int value; 1039 1040 /* Work around issue with chip reporting wrong PHY ID */ 1041 if (reg == MII_PHYSID2) 1042 return 0xc912; 1043 1044 r8168dp_2_mdio_start(tp); 1045 1046 value = r8169_mdio_read(tp, reg); 1047 1048 r8168dp_2_mdio_stop(tp); 1049 1050 return value; 1051 } 1052 1053 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1054 { 1055 switch (tp->mac_version) { 1056 case RTL_GIGA_MAC_VER_27: 1057 r8168dp_1_mdio_write(tp, location, val); 1058 break; 1059 case RTL_GIGA_MAC_VER_28: 1060 case RTL_GIGA_MAC_VER_31: 1061 r8168dp_2_mdio_write(tp, location, val); 1062 break; 1063 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1064 r8168g_mdio_write(tp, location, val); 1065 break; 1066 default: 1067 r8169_mdio_write(tp, location, val); 1068 break; 1069 } 1070 } 1071 1072 static int rtl_readphy(struct rtl8169_private *tp, int location) 1073 { 1074 switch (tp->mac_version) { 1075 case RTL_GIGA_MAC_VER_27: 1076 return r8168dp_1_mdio_read(tp, location); 1077 case RTL_GIGA_MAC_VER_28: 1078 case RTL_GIGA_MAC_VER_31: 1079 return r8168dp_2_mdio_read(tp, location); 1080 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1081 return r8168g_mdio_read(tp, location); 1082 default: 1083 return r8169_mdio_read(tp, location); 1084 } 1085 } 1086 1087 DECLARE_RTL_COND(rtl_ephyar_cond) 1088 { 1089 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1090 } 1091 1092 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1093 { 1094 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1095 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1096 1097 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1098 1099 udelay(10); 1100 } 1101 1102 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1103 { 1104 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1105 1106 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1107 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1108 } 1109 1110 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1111 { 1112 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1113 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1114 RTL_R32(tp, OCPDR) : ~0; 1115 } 1116 1117 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1118 { 1119 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1120 } 1121 1122 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1123 u32 data) 1124 { 1125 RTL_W32(tp, OCPDR, data); 1126 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1127 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1128 } 1129 1130 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1131 u32 data) 1132 { 1133 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1134 data, ERIAR_OOB); 1135 } 1136 1137 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1138 { 1139 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1140 1141 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1142 } 1143 1144 #define OOB_CMD_RESET 0x00 1145 #define OOB_CMD_DRIVER_START 0x05 1146 #define OOB_CMD_DRIVER_STOP 0x06 1147 1148 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1149 { 1150 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1151 } 1152 1153 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1154 { 1155 u16 reg; 1156 1157 reg = rtl8168_get_ocp_reg(tp); 1158 1159 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1160 } 1161 1162 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1163 { 1164 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1165 } 1166 1167 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1168 { 1169 return RTL_R8(tp, IBISR0) & 0x20; 1170 } 1171 1172 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1173 { 1174 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1175 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1176 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1177 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1178 } 1179 1180 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1181 { 1182 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1183 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1184 } 1185 1186 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1187 { 1188 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1189 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1190 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1191 } 1192 1193 static void rtl8168_driver_start(struct rtl8169_private *tp) 1194 { 1195 if (tp->dash_type == RTL_DASH_DP) 1196 rtl8168dp_driver_start(tp); 1197 else 1198 rtl8168ep_driver_start(tp); 1199 } 1200 1201 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1202 { 1203 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1204 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1205 } 1206 1207 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1208 { 1209 rtl8168ep_stop_cmac(tp); 1210 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1211 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1212 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1213 } 1214 1215 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1216 { 1217 if (tp->dash_type == RTL_DASH_DP) 1218 rtl8168dp_driver_stop(tp); 1219 else 1220 rtl8168ep_driver_stop(tp); 1221 } 1222 1223 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1224 { 1225 u16 reg = rtl8168_get_ocp_reg(tp); 1226 1227 return r8168dp_ocp_read(tp, reg) & BIT(15); 1228 } 1229 1230 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1231 { 1232 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1233 } 1234 1235 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1236 { 1237 switch (tp->mac_version) { 1238 case RTL_GIGA_MAC_VER_27: 1239 case RTL_GIGA_MAC_VER_28: 1240 case RTL_GIGA_MAC_VER_31: 1241 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1242 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 1243 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1244 default: 1245 return RTL_DASH_NONE; 1246 } 1247 } 1248 1249 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1250 { 1251 switch (tp->mac_version) { 1252 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1253 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1254 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1255 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1256 if (enable) 1257 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1258 else 1259 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1260 break; 1261 default: 1262 break; 1263 } 1264 } 1265 1266 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1267 { 1268 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1269 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1270 } 1271 1272 DECLARE_RTL_COND(rtl_efusear_cond) 1273 { 1274 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1275 } 1276 1277 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1278 { 1279 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1280 1281 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1282 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1283 } 1284 1285 static u32 rtl_get_events(struct rtl8169_private *tp) 1286 { 1287 if (rtl_is_8125(tp)) 1288 return RTL_R32(tp, IntrStatus_8125); 1289 else 1290 return RTL_R16(tp, IntrStatus); 1291 } 1292 1293 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1294 { 1295 if (rtl_is_8125(tp)) 1296 RTL_W32(tp, IntrStatus_8125, bits); 1297 else 1298 RTL_W16(tp, IntrStatus, bits); 1299 } 1300 1301 static void rtl_irq_disable(struct rtl8169_private *tp) 1302 { 1303 if (rtl_is_8125(tp)) 1304 RTL_W32(tp, IntrMask_8125, 0); 1305 else 1306 RTL_W16(tp, IntrMask, 0); 1307 } 1308 1309 static void rtl_irq_enable(struct rtl8169_private *tp) 1310 { 1311 if (rtl_is_8125(tp)) 1312 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1313 else 1314 RTL_W16(tp, IntrMask, tp->irq_mask); 1315 } 1316 1317 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1318 { 1319 rtl_irq_disable(tp); 1320 rtl_ack_events(tp, 0xffffffff); 1321 rtl_pci_commit(tp); 1322 } 1323 1324 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1325 { 1326 struct phy_device *phydev = tp->phydev; 1327 1328 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1329 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1330 if (phydev->speed == SPEED_1000) { 1331 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1332 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1333 } else if (phydev->speed == SPEED_100) { 1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1336 } else { 1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1339 } 1340 rtl_reset_packet_filter(tp); 1341 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1342 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1343 if (phydev->speed == SPEED_1000) { 1344 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1345 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1346 } else { 1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1348 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1349 } 1350 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1351 if (phydev->speed == SPEED_10) { 1352 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1353 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1354 } else { 1355 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1356 } 1357 } 1358 } 1359 1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1361 1362 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1363 { 1364 struct rtl8169_private *tp = netdev_priv(dev); 1365 1366 wol->supported = WAKE_ANY; 1367 wol->wolopts = tp->saved_wolopts; 1368 } 1369 1370 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1371 { 1372 static const struct { 1373 u32 opt; 1374 u16 reg; 1375 u8 mask; 1376 } cfg[] = { 1377 { WAKE_PHY, Config3, LinkUp }, 1378 { WAKE_UCAST, Config5, UWF }, 1379 { WAKE_BCAST, Config5, BWF }, 1380 { WAKE_MCAST, Config5, MWF }, 1381 { WAKE_ANY, Config5, LanWake }, 1382 { WAKE_MAGIC, Config3, MagicPacket } 1383 }; 1384 unsigned int i, tmp = ARRAY_SIZE(cfg); 1385 u8 options; 1386 1387 rtl_unlock_config_regs(tp); 1388 1389 if (rtl_is_8168evl_up(tp)) { 1390 tmp--; 1391 if (wolopts & WAKE_MAGIC) 1392 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1393 else 1394 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1395 } else if (rtl_is_8125(tp)) { 1396 tmp--; 1397 if (wolopts & WAKE_MAGIC) 1398 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1399 else 1400 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1401 } 1402 1403 for (i = 0; i < tmp; i++) { 1404 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1405 if (wolopts & cfg[i].opt) 1406 options |= cfg[i].mask; 1407 RTL_W8(tp, cfg[i].reg, options); 1408 } 1409 1410 switch (tp->mac_version) { 1411 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1412 options = RTL_R8(tp, Config1) & ~PMEnable; 1413 if (wolopts) 1414 options |= PMEnable; 1415 RTL_W8(tp, Config1, options); 1416 break; 1417 case RTL_GIGA_MAC_VER_34: 1418 case RTL_GIGA_MAC_VER_37: 1419 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1420 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1421 if (wolopts) 1422 options |= PME_SIGNAL; 1423 RTL_W8(tp, Config2, options); 1424 break; 1425 default: 1426 break; 1427 } 1428 1429 rtl_lock_config_regs(tp); 1430 1431 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1432 rtl_set_d3_pll_down(tp, !wolopts); 1433 tp->dev->wol_enabled = wolopts ? 1 : 0; 1434 } 1435 1436 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1437 { 1438 struct rtl8169_private *tp = netdev_priv(dev); 1439 1440 if (wol->wolopts & ~WAKE_ANY) 1441 return -EINVAL; 1442 1443 tp->saved_wolopts = wol->wolopts; 1444 __rtl8169_set_wol(tp, tp->saved_wolopts); 1445 1446 return 0; 1447 } 1448 1449 static void rtl8169_get_drvinfo(struct net_device *dev, 1450 struct ethtool_drvinfo *info) 1451 { 1452 struct rtl8169_private *tp = netdev_priv(dev); 1453 struct rtl_fw *rtl_fw = tp->rtl_fw; 1454 1455 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1456 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1457 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1458 if (rtl_fw) 1459 strlcpy(info->fw_version, rtl_fw->version, 1460 sizeof(info->fw_version)); 1461 } 1462 1463 static int rtl8169_get_regs_len(struct net_device *dev) 1464 { 1465 return R8169_REGS_SIZE; 1466 } 1467 1468 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1469 netdev_features_t features) 1470 { 1471 struct rtl8169_private *tp = netdev_priv(dev); 1472 1473 if (dev->mtu > TD_MSS_MAX) 1474 features &= ~NETIF_F_ALL_TSO; 1475 1476 if (dev->mtu > ETH_DATA_LEN && 1477 tp->mac_version > RTL_GIGA_MAC_VER_06) 1478 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1479 1480 return features; 1481 } 1482 1483 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1484 netdev_features_t features) 1485 { 1486 u32 rx_config = RTL_R32(tp, RxConfig); 1487 1488 if (features & NETIF_F_RXALL) 1489 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1490 else 1491 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1492 1493 if (rtl_is_8125(tp)) { 1494 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1495 rx_config |= RX_VLAN_8125; 1496 else 1497 rx_config &= ~RX_VLAN_8125; 1498 } 1499 1500 RTL_W32(tp, RxConfig, rx_config); 1501 } 1502 1503 static int rtl8169_set_features(struct net_device *dev, 1504 netdev_features_t features) 1505 { 1506 struct rtl8169_private *tp = netdev_priv(dev); 1507 1508 rtl_set_rx_config_features(tp, features); 1509 1510 if (features & NETIF_F_RXCSUM) 1511 tp->cp_cmd |= RxChkSum; 1512 else 1513 tp->cp_cmd &= ~RxChkSum; 1514 1515 if (!rtl_is_8125(tp)) { 1516 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1517 tp->cp_cmd |= RxVlan; 1518 else 1519 tp->cp_cmd &= ~RxVlan; 1520 } 1521 1522 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1523 rtl_pci_commit(tp); 1524 1525 return 0; 1526 } 1527 1528 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1529 { 1530 return (skb_vlan_tag_present(skb)) ? 1531 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1532 } 1533 1534 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1535 { 1536 u32 opts2 = le32_to_cpu(desc->opts2); 1537 1538 if (opts2 & RxVlanTag) 1539 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1540 } 1541 1542 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1543 void *p) 1544 { 1545 struct rtl8169_private *tp = netdev_priv(dev); 1546 u32 __iomem *data = tp->mmio_addr; 1547 u32 *dw = p; 1548 int i; 1549 1550 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1551 memcpy_fromio(dw++, data++, 4); 1552 } 1553 1554 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1555 "tx_packets", 1556 "rx_packets", 1557 "tx_errors", 1558 "rx_errors", 1559 "rx_missed", 1560 "align_errors", 1561 "tx_single_collisions", 1562 "tx_multi_collisions", 1563 "unicast", 1564 "broadcast", 1565 "multicast", 1566 "tx_aborted", 1567 "tx_underrun", 1568 }; 1569 1570 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1571 { 1572 switch (sset) { 1573 case ETH_SS_STATS: 1574 return ARRAY_SIZE(rtl8169_gstrings); 1575 default: 1576 return -EOPNOTSUPP; 1577 } 1578 } 1579 1580 DECLARE_RTL_COND(rtl_counters_cond) 1581 { 1582 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1583 } 1584 1585 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1586 { 1587 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1588 1589 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1590 rtl_pci_commit(tp); 1591 RTL_W32(tp, CounterAddrLow, cmd); 1592 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1593 1594 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1595 } 1596 1597 static void rtl8169_update_counters(struct rtl8169_private *tp) 1598 { 1599 u8 val = RTL_R8(tp, ChipCmd); 1600 1601 /* 1602 * Some chips are unable to dump tally counters when the receiver 1603 * is disabled. If 0xff chip may be in a PCI power-save state. 1604 */ 1605 if (val & CmdRxEnb && val != 0xff) 1606 rtl8169_do_counters(tp, CounterDump); 1607 } 1608 1609 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1610 { 1611 struct rtl8169_counters *counters = tp->counters; 1612 1613 /* 1614 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1615 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1616 * reset by a power cycle, while the counter values collected by the 1617 * driver are reset at every driver unload/load cycle. 1618 * 1619 * To make sure the HW values returned by @get_stats64 match the SW 1620 * values, we collect the initial values at first open(*) and use them 1621 * as offsets to normalize the values returned by @get_stats64. 1622 * 1623 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1624 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1625 * set at open time by rtl_hw_start. 1626 */ 1627 1628 if (tp->tc_offset.inited) 1629 return; 1630 1631 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1632 rtl8169_do_counters(tp, CounterReset); 1633 } else { 1634 rtl8169_update_counters(tp); 1635 tp->tc_offset.tx_errors = counters->tx_errors; 1636 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1637 tp->tc_offset.tx_aborted = counters->tx_aborted; 1638 tp->tc_offset.rx_missed = counters->rx_missed; 1639 } 1640 1641 tp->tc_offset.inited = true; 1642 } 1643 1644 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1645 struct ethtool_stats *stats, u64 *data) 1646 { 1647 struct rtl8169_private *tp = netdev_priv(dev); 1648 struct rtl8169_counters *counters; 1649 1650 counters = tp->counters; 1651 rtl8169_update_counters(tp); 1652 1653 data[0] = le64_to_cpu(counters->tx_packets); 1654 data[1] = le64_to_cpu(counters->rx_packets); 1655 data[2] = le64_to_cpu(counters->tx_errors); 1656 data[3] = le32_to_cpu(counters->rx_errors); 1657 data[4] = le16_to_cpu(counters->rx_missed); 1658 data[5] = le16_to_cpu(counters->align_errors); 1659 data[6] = le32_to_cpu(counters->tx_one_collision); 1660 data[7] = le32_to_cpu(counters->tx_multi_collision); 1661 data[8] = le64_to_cpu(counters->rx_unicast); 1662 data[9] = le64_to_cpu(counters->rx_broadcast); 1663 data[10] = le32_to_cpu(counters->rx_multicast); 1664 data[11] = le16_to_cpu(counters->tx_aborted); 1665 data[12] = le16_to_cpu(counters->tx_underun); 1666 } 1667 1668 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1669 { 1670 switch(stringset) { 1671 case ETH_SS_STATS: 1672 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1673 break; 1674 } 1675 } 1676 1677 /* 1678 * Interrupt coalescing 1679 * 1680 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1681 * > 8169, 8168 and 810x line of chipsets 1682 * 1683 * 8169, 8168, and 8136(810x) serial chipsets support it. 1684 * 1685 * > 2 - the Tx timer unit at gigabit speed 1686 * 1687 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1688 * (0xe0) bit 1 and bit 0. 1689 * 1690 * For 8169 1691 * bit[1:0] \ speed 1000M 100M 10M 1692 * 0 0 320ns 2.56us 40.96us 1693 * 0 1 2.56us 20.48us 327.7us 1694 * 1 0 5.12us 40.96us 655.4us 1695 * 1 1 10.24us 81.92us 1.31ms 1696 * 1697 * For the other 1698 * bit[1:0] \ speed 1000M 100M 10M 1699 * 0 0 5us 2.56us 40.96us 1700 * 0 1 40us 20.48us 327.7us 1701 * 1 0 80us 40.96us 655.4us 1702 * 1 1 160us 81.92us 1.31ms 1703 */ 1704 1705 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1706 struct rtl_coalesce_info { 1707 u32 speed; 1708 u32 scale_nsecs[4]; 1709 }; 1710 1711 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1712 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1713 1714 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1715 { SPEED_1000, COALESCE_DELAY(320) }, 1716 { SPEED_100, COALESCE_DELAY(2560) }, 1717 { SPEED_10, COALESCE_DELAY(40960) }, 1718 { 0 }, 1719 }; 1720 1721 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1722 { SPEED_1000, COALESCE_DELAY(5000) }, 1723 { SPEED_100, COALESCE_DELAY(2560) }, 1724 { SPEED_10, COALESCE_DELAY(40960) }, 1725 { 0 }, 1726 }; 1727 #undef COALESCE_DELAY 1728 1729 /* get rx/tx scale vector corresponding to current speed */ 1730 static const struct rtl_coalesce_info * 1731 rtl_coalesce_info(struct rtl8169_private *tp) 1732 { 1733 const struct rtl_coalesce_info *ci; 1734 1735 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1736 ci = rtl_coalesce_info_8169; 1737 else 1738 ci = rtl_coalesce_info_8168_8136; 1739 1740 /* if speed is unknown assume highest one */ 1741 if (tp->phydev->speed == SPEED_UNKNOWN) 1742 return ci; 1743 1744 for (; ci->speed; ci++) { 1745 if (tp->phydev->speed == ci->speed) 1746 return ci; 1747 } 1748 1749 return ERR_PTR(-ELNRNG); 1750 } 1751 1752 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1753 { 1754 struct rtl8169_private *tp = netdev_priv(dev); 1755 const struct rtl_coalesce_info *ci; 1756 u32 scale, c_us, c_fr; 1757 u16 intrmit; 1758 1759 if (rtl_is_8125(tp)) 1760 return -EOPNOTSUPP; 1761 1762 memset(ec, 0, sizeof(*ec)); 1763 1764 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1765 ci = rtl_coalesce_info(tp); 1766 if (IS_ERR(ci)) 1767 return PTR_ERR(ci); 1768 1769 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1770 1771 intrmit = RTL_R16(tp, IntrMitigate); 1772 1773 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1774 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1775 1776 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1777 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1778 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1779 1780 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1781 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1782 1783 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1784 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1785 1786 return 0; 1787 } 1788 1789 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1790 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1791 u16 *cp01) 1792 { 1793 const struct rtl_coalesce_info *ci; 1794 u16 i; 1795 1796 ci = rtl_coalesce_info(tp); 1797 if (IS_ERR(ci)) 1798 return PTR_ERR(ci); 1799 1800 for (i = 0; i < 4; i++) { 1801 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1802 *cp01 = i; 1803 return ci->scale_nsecs[i]; 1804 } 1805 } 1806 1807 return -ERANGE; 1808 } 1809 1810 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1811 { 1812 struct rtl8169_private *tp = netdev_priv(dev); 1813 u32 tx_fr = ec->tx_max_coalesced_frames; 1814 u32 rx_fr = ec->rx_max_coalesced_frames; 1815 u32 coal_usec_max, units; 1816 u16 w = 0, cp01 = 0; 1817 int scale; 1818 1819 if (rtl_is_8125(tp)) 1820 return -EOPNOTSUPP; 1821 1822 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1823 return -ERANGE; 1824 1825 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1826 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1827 if (scale < 0) 1828 return scale; 1829 1830 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1831 * not only when usecs=0 because of e.g. the following scenario: 1832 * 1833 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1834 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1835 * - then user does `ethtool -C eth0 rx-usecs 100` 1836 * 1837 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1838 * if we want to ignore rx_frames then it has to be set to 0. 1839 */ 1840 if (rx_fr == 1) 1841 rx_fr = 0; 1842 if (tx_fr == 1) 1843 tx_fr = 0; 1844 1845 /* HW requires time limit to be set if frame limit is set */ 1846 if ((tx_fr && !ec->tx_coalesce_usecs) || 1847 (rx_fr && !ec->rx_coalesce_usecs)) 1848 return -EINVAL; 1849 1850 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1851 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1852 1853 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1854 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1855 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1856 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1857 1858 RTL_W16(tp, IntrMitigate, w); 1859 1860 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1861 if (rtl_is_8168evl_up(tp)) { 1862 if (!rx_fr && !tx_fr) 1863 /* disable packet counter */ 1864 tp->cp_cmd |= PktCntrDisable; 1865 else 1866 tp->cp_cmd &= ~PktCntrDisable; 1867 } 1868 1869 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1870 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1871 rtl_pci_commit(tp); 1872 1873 return 0; 1874 } 1875 1876 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1877 { 1878 struct rtl8169_private *tp = netdev_priv(dev); 1879 1880 if (!rtl_supports_eee(tp)) 1881 return -EOPNOTSUPP; 1882 1883 return phy_ethtool_get_eee(tp->phydev, data); 1884 } 1885 1886 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1887 { 1888 struct rtl8169_private *tp = netdev_priv(dev); 1889 int ret; 1890 1891 if (!rtl_supports_eee(tp)) 1892 return -EOPNOTSUPP; 1893 1894 ret = phy_ethtool_set_eee(tp->phydev, data); 1895 1896 if (!ret) 1897 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1898 MDIO_AN_EEE_ADV); 1899 return ret; 1900 } 1901 1902 static void rtl8169_get_ringparam(struct net_device *dev, 1903 struct ethtool_ringparam *data) 1904 { 1905 data->rx_max_pending = NUM_RX_DESC; 1906 data->rx_pending = NUM_RX_DESC; 1907 data->tx_max_pending = NUM_TX_DESC; 1908 data->tx_pending = NUM_TX_DESC; 1909 } 1910 1911 static void rtl8169_get_pauseparam(struct net_device *dev, 1912 struct ethtool_pauseparam *data) 1913 { 1914 struct rtl8169_private *tp = netdev_priv(dev); 1915 bool tx_pause, rx_pause; 1916 1917 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1918 1919 data->autoneg = tp->phydev->autoneg; 1920 data->tx_pause = tx_pause ? 1 : 0; 1921 data->rx_pause = rx_pause ? 1 : 0; 1922 } 1923 1924 static int rtl8169_set_pauseparam(struct net_device *dev, 1925 struct ethtool_pauseparam *data) 1926 { 1927 struct rtl8169_private *tp = netdev_priv(dev); 1928 1929 if (dev->mtu > ETH_DATA_LEN) 1930 return -EOPNOTSUPP; 1931 1932 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1933 1934 return 0; 1935 } 1936 1937 static const struct ethtool_ops rtl8169_ethtool_ops = { 1938 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1939 ETHTOOL_COALESCE_MAX_FRAMES, 1940 .get_drvinfo = rtl8169_get_drvinfo, 1941 .get_regs_len = rtl8169_get_regs_len, 1942 .get_link = ethtool_op_get_link, 1943 .get_coalesce = rtl_get_coalesce, 1944 .set_coalesce = rtl_set_coalesce, 1945 .get_regs = rtl8169_get_regs, 1946 .get_wol = rtl8169_get_wol, 1947 .set_wol = rtl8169_set_wol, 1948 .get_strings = rtl8169_get_strings, 1949 .get_sset_count = rtl8169_get_sset_count, 1950 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1951 .get_ts_info = ethtool_op_get_ts_info, 1952 .nway_reset = phy_ethtool_nway_reset, 1953 .get_eee = rtl8169_get_eee, 1954 .set_eee = rtl8169_set_eee, 1955 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1956 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1957 .get_ringparam = rtl8169_get_ringparam, 1958 .get_pauseparam = rtl8169_get_pauseparam, 1959 .set_pauseparam = rtl8169_set_pauseparam, 1960 }; 1961 1962 static void rtl_enable_eee(struct rtl8169_private *tp) 1963 { 1964 struct phy_device *phydev = tp->phydev; 1965 int adv; 1966 1967 /* respect EEE advertisement the user may have set */ 1968 if (tp->eee_adv >= 0) 1969 adv = tp->eee_adv; 1970 else 1971 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1972 1973 if (adv >= 0) 1974 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1975 } 1976 1977 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1978 { 1979 /* 1980 * The driver currently handles the 8168Bf and the 8168Be identically 1981 * but they can be identified more specifically through the test below 1982 * if needed: 1983 * 1984 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1985 * 1986 * Same thing for the 8101Eb and the 8101Ec: 1987 * 1988 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1989 */ 1990 static const struct rtl_mac_info { 1991 u16 mask; 1992 u16 val; 1993 enum mac_version ver; 1994 } mac_info[] = { 1995 /* 8125B family. */ 1996 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1997 1998 /* 8125A family. */ 1999 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2000 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2001 2002 /* RTL8117 */ 2003 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2004 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2005 2006 /* 8168EP family. */ 2007 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2008 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2009 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2010 2011 /* 8168H family. */ 2012 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2013 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2014 2015 /* 8168G family. */ 2016 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2017 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2018 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2019 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2020 2021 /* 8168F family. */ 2022 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2023 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2024 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2025 2026 /* 8168E family. */ 2027 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2028 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2029 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2030 2031 /* 8168D family. */ 2032 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2033 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2034 2035 /* 8168DP family. */ 2036 /* It seems this early RTL8168dp version never made it to 2037 * the wild. Let's see whether somebody complains, if not 2038 * we'll remove support for this chip version completely. 2039 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2040 */ 2041 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2042 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2043 2044 /* 8168C family. */ 2045 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2046 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2047 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2048 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2049 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2050 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2051 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2052 2053 /* 8168B family. */ 2054 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2055 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2056 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2057 2058 /* 8101 family. */ 2059 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2060 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2061 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2062 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2063 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2064 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2065 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2066 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2067 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2068 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2069 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2070 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2071 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2072 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2073 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2074 /* FIXME: where did these entries come from ? -- FR 2075 * Not even r8101 vendor driver knows these id's, 2076 * so let's disable detection for now. -- HK 2077 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2078 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2079 */ 2080 2081 /* 8110 family. */ 2082 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2083 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2084 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2085 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2086 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2087 2088 /* Catch-all */ 2089 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2090 }; 2091 const struct rtl_mac_info *p = mac_info; 2092 enum mac_version ver; 2093 2094 while ((xid & p->mask) != p->val) 2095 p++; 2096 ver = p->ver; 2097 2098 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2099 if (ver == RTL_GIGA_MAC_VER_42) 2100 ver = RTL_GIGA_MAC_VER_43; 2101 else if (ver == RTL_GIGA_MAC_VER_45) 2102 ver = RTL_GIGA_MAC_VER_47; 2103 else if (ver == RTL_GIGA_MAC_VER_46) 2104 ver = RTL_GIGA_MAC_VER_48; 2105 } 2106 2107 return ver; 2108 } 2109 2110 static void rtl_release_firmware(struct rtl8169_private *tp) 2111 { 2112 if (tp->rtl_fw) { 2113 rtl_fw_release_firmware(tp->rtl_fw); 2114 kfree(tp->rtl_fw); 2115 tp->rtl_fw = NULL; 2116 } 2117 } 2118 2119 void r8169_apply_firmware(struct rtl8169_private *tp) 2120 { 2121 int val; 2122 2123 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2124 if (tp->rtl_fw) { 2125 rtl_fw_write_firmware(tp, tp->rtl_fw); 2126 /* At least one firmware doesn't reset tp->ocp_base. */ 2127 tp->ocp_base = OCP_STD_PHY_BASE; 2128 2129 /* PHY soft reset may still be in progress */ 2130 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2131 !(val & BMCR_RESET), 2132 50000, 600000, true); 2133 } 2134 } 2135 2136 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2137 { 2138 /* Adjust EEE LED frequency */ 2139 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2140 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2141 2142 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2143 } 2144 2145 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2146 { 2147 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2148 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2149 } 2150 2151 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2152 { 2153 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2154 } 2155 2156 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2157 { 2158 rtl8125_set_eee_txidle_timer(tp); 2159 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2160 } 2161 2162 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2163 { 2164 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2165 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2166 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2167 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2168 } 2169 2170 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2171 { 2172 u16 data1, data2, ioffset; 2173 2174 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2175 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2176 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2177 2178 ioffset = (data2 >> 1) & 0x7ff8; 2179 ioffset |= data2 & 0x0007; 2180 if (data1 & BIT(7)) 2181 ioffset |= BIT(15); 2182 2183 return ioffset; 2184 } 2185 2186 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2187 { 2188 set_bit(flag, tp->wk.flags); 2189 schedule_work(&tp->wk.work); 2190 } 2191 2192 static void rtl8169_init_phy(struct rtl8169_private *tp) 2193 { 2194 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2195 2196 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2197 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2198 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2199 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2200 RTL_W8(tp, 0x82, 0x01); 2201 } 2202 2203 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2204 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2205 tp->pci_dev->subsystem_device == 0xe000) 2206 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2207 2208 /* We may have called phy_speed_down before */ 2209 phy_speed_up(tp->phydev); 2210 2211 if (rtl_supports_eee(tp)) 2212 rtl_enable_eee(tp); 2213 2214 genphy_soft_reset(tp->phydev); 2215 } 2216 2217 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2218 { 2219 rtl_unlock_config_regs(tp); 2220 2221 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2222 rtl_pci_commit(tp); 2223 2224 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2225 rtl_pci_commit(tp); 2226 2227 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2228 rtl_rar_exgmac_set(tp, addr); 2229 2230 rtl_lock_config_regs(tp); 2231 } 2232 2233 static int rtl_set_mac_address(struct net_device *dev, void *p) 2234 { 2235 struct rtl8169_private *tp = netdev_priv(dev); 2236 int ret; 2237 2238 ret = eth_mac_addr(dev, p); 2239 if (ret) 2240 return ret; 2241 2242 rtl_rar_set(tp, dev->dev_addr); 2243 2244 return 0; 2245 } 2246 2247 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2248 { 2249 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2250 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2251 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2252 } 2253 2254 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2255 { 2256 if (tp->dash_type != RTL_DASH_NONE) 2257 return; 2258 2259 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2260 tp->mac_version == RTL_GIGA_MAC_VER_33) 2261 rtl_ephy_write(tp, 0x19, 0xff64); 2262 2263 if (device_may_wakeup(tp_to_dev(tp))) { 2264 phy_speed_down(tp->phydev, false); 2265 rtl_wol_enable_rx(tp); 2266 } 2267 } 2268 2269 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2270 { 2271 switch (tp->mac_version) { 2272 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2273 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2274 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2275 break; 2276 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2277 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2278 case RTL_GIGA_MAC_VER_38: 2279 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2280 break; 2281 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2282 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2283 break; 2284 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2285 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2286 break; 2287 default: 2288 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2289 break; 2290 } 2291 } 2292 2293 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2294 { 2295 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2296 } 2297 2298 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2299 { 2300 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2301 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2302 } 2303 2304 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2305 { 2306 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2307 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2308 } 2309 2310 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2311 { 2312 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2313 } 2314 2315 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2316 { 2317 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2318 } 2319 2320 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2321 { 2322 RTL_W8(tp, MaxTxPacketSize, 0x24); 2323 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2324 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2325 } 2326 2327 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2328 { 2329 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2332 } 2333 2334 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2335 { 2336 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2337 } 2338 2339 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2340 { 2341 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2342 } 2343 2344 static void rtl_jumbo_config(struct rtl8169_private *tp) 2345 { 2346 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2347 int readrq = 4096; 2348 2349 rtl_unlock_config_regs(tp); 2350 switch (tp->mac_version) { 2351 case RTL_GIGA_MAC_VER_12: 2352 case RTL_GIGA_MAC_VER_17: 2353 if (jumbo) { 2354 readrq = 512; 2355 r8168b_1_hw_jumbo_enable(tp); 2356 } else { 2357 r8168b_1_hw_jumbo_disable(tp); 2358 } 2359 break; 2360 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2361 if (jumbo) { 2362 readrq = 512; 2363 r8168c_hw_jumbo_enable(tp); 2364 } else { 2365 r8168c_hw_jumbo_disable(tp); 2366 } 2367 break; 2368 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2369 if (jumbo) 2370 r8168dp_hw_jumbo_enable(tp); 2371 else 2372 r8168dp_hw_jumbo_disable(tp); 2373 break; 2374 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2375 if (jumbo) 2376 r8168e_hw_jumbo_enable(tp); 2377 else 2378 r8168e_hw_jumbo_disable(tp); 2379 break; 2380 default: 2381 break; 2382 } 2383 rtl_lock_config_regs(tp); 2384 2385 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2386 pcie_set_readrq(tp->pci_dev, readrq); 2387 2388 /* Chip doesn't support pause in jumbo mode */ 2389 if (jumbo) { 2390 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2391 tp->phydev->advertising); 2392 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2393 tp->phydev->advertising); 2394 phy_start_aneg(tp->phydev); 2395 } 2396 } 2397 2398 DECLARE_RTL_COND(rtl_chipcmd_cond) 2399 { 2400 return RTL_R8(tp, ChipCmd) & CmdReset; 2401 } 2402 2403 static void rtl_hw_reset(struct rtl8169_private *tp) 2404 { 2405 RTL_W8(tp, ChipCmd, CmdReset); 2406 2407 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2408 } 2409 2410 static void rtl_request_firmware(struct rtl8169_private *tp) 2411 { 2412 struct rtl_fw *rtl_fw; 2413 2414 /* firmware loaded already or no firmware available */ 2415 if (tp->rtl_fw || !tp->fw_name) 2416 return; 2417 2418 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2419 if (!rtl_fw) 2420 return; 2421 2422 rtl_fw->phy_write = rtl_writephy; 2423 rtl_fw->phy_read = rtl_readphy; 2424 rtl_fw->mac_mcu_write = mac_mcu_write; 2425 rtl_fw->mac_mcu_read = mac_mcu_read; 2426 rtl_fw->fw_name = tp->fw_name; 2427 rtl_fw->dev = tp_to_dev(tp); 2428 2429 if (rtl_fw_request_firmware(rtl_fw)) 2430 kfree(rtl_fw); 2431 else 2432 tp->rtl_fw = rtl_fw; 2433 } 2434 2435 static void rtl_rx_close(struct rtl8169_private *tp) 2436 { 2437 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2438 } 2439 2440 DECLARE_RTL_COND(rtl_npq_cond) 2441 { 2442 return RTL_R8(tp, TxPoll) & NPQ; 2443 } 2444 2445 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2446 { 2447 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2448 } 2449 2450 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2451 { 2452 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2453 } 2454 2455 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2456 { 2457 /* IntrMitigate has new functionality on RTL8125 */ 2458 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2459 } 2460 2461 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2462 { 2463 switch (tp->mac_version) { 2464 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2465 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2466 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2467 break; 2468 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2469 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2470 break; 2471 case RTL_GIGA_MAC_VER_63: 2472 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2473 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2474 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2475 break; 2476 default: 2477 break; 2478 } 2479 } 2480 2481 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2482 { 2483 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2484 fsleep(2000); 2485 rtl_wait_txrx_fifo_empty(tp); 2486 } 2487 2488 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2489 { 2490 u32 val = TX_DMA_BURST << TxDMAShift | 2491 InterFrameGap << TxInterFrameGapShift; 2492 2493 if (rtl_is_8168evl_up(tp)) 2494 val |= TXCFG_AUTO_FIFO; 2495 2496 RTL_W32(tp, TxConfig, val); 2497 } 2498 2499 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2500 { 2501 /* Low hurts. Let's disable the filtering. */ 2502 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2503 } 2504 2505 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2506 { 2507 /* 2508 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2509 * register to be written before TxDescAddrLow to work. 2510 * Switching from MMIO to I/O access fixes the issue as well. 2511 */ 2512 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2513 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2514 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2515 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2516 } 2517 2518 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2519 { 2520 u32 val; 2521 2522 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2523 val = 0x000fff00; 2524 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2525 val = 0x00ffff00; 2526 else 2527 return; 2528 2529 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2530 val |= 0xff; 2531 2532 RTL_W32(tp, 0x7c, val); 2533 } 2534 2535 static void rtl_set_rx_mode(struct net_device *dev) 2536 { 2537 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2538 /* Multicast hash filter */ 2539 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2540 struct rtl8169_private *tp = netdev_priv(dev); 2541 u32 tmp; 2542 2543 if (dev->flags & IFF_PROMISC) { 2544 rx_mode |= AcceptAllPhys; 2545 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2546 dev->flags & IFF_ALLMULTI || 2547 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2548 /* accept all multicasts */ 2549 } else if (netdev_mc_empty(dev)) { 2550 rx_mode &= ~AcceptMulticast; 2551 } else { 2552 struct netdev_hw_addr *ha; 2553 2554 mc_filter[1] = mc_filter[0] = 0; 2555 netdev_for_each_mc_addr(ha, dev) { 2556 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2557 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2558 } 2559 2560 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2561 tmp = mc_filter[0]; 2562 mc_filter[0] = swab32(mc_filter[1]); 2563 mc_filter[1] = swab32(tmp); 2564 } 2565 } 2566 2567 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2568 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2569 2570 tmp = RTL_R32(tp, RxConfig); 2571 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2572 } 2573 2574 DECLARE_RTL_COND(rtl_csiar_cond) 2575 { 2576 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2577 } 2578 2579 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2580 { 2581 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2582 2583 RTL_W32(tp, CSIDR, value); 2584 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2585 CSIAR_BYTE_ENABLE | func << 16); 2586 2587 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2588 } 2589 2590 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2591 { 2592 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2593 2594 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2595 CSIAR_BYTE_ENABLE); 2596 2597 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2598 RTL_R32(tp, CSIDR) : ~0; 2599 } 2600 2601 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2602 { 2603 struct pci_dev *pdev = tp->pci_dev; 2604 u32 csi; 2605 2606 /* According to Realtek the value at config space address 0x070f 2607 * controls the L0s/L1 entrance latency. We try standard ECAM access 2608 * first and if it fails fall back to CSI. 2609 */ 2610 if (pdev->cfg_size > 0x070f && 2611 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2612 return; 2613 2614 netdev_notice_once(tp->dev, 2615 "No native access to PCI extended config space, falling back to CSI\n"); 2616 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2617 rtl_csi_write(tp, 0x070c, csi | val << 24); 2618 } 2619 2620 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2621 { 2622 rtl_csi_access_enable(tp, 0x27); 2623 } 2624 2625 struct ephy_info { 2626 unsigned int offset; 2627 u16 mask; 2628 u16 bits; 2629 }; 2630 2631 static void __rtl_ephy_init(struct rtl8169_private *tp, 2632 const struct ephy_info *e, int len) 2633 { 2634 u16 w; 2635 2636 while (len-- > 0) { 2637 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2638 rtl_ephy_write(tp, e->offset, w); 2639 e++; 2640 } 2641 } 2642 2643 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2644 2645 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2646 { 2647 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2648 PCI_EXP_LNKCTL_CLKREQ_EN); 2649 } 2650 2651 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2652 { 2653 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2654 PCI_EXP_LNKCTL_CLKREQ_EN); 2655 } 2656 2657 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2658 { 2659 /* work around an issue when PCI reset occurs during L2/L3 state */ 2660 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2661 } 2662 2663 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2664 { 2665 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2666 if (enable && tp->aspm_manageable) { 2667 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2668 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2669 } else { 2670 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2671 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2672 } 2673 2674 udelay(10); 2675 } 2676 2677 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2678 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2679 { 2680 /* Usage of dynamic vs. static FIFO is controlled by bit 2681 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2682 */ 2683 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2684 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2685 } 2686 2687 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2688 u8 low, u8 high) 2689 { 2690 /* FIFO thresholds for pause flow control */ 2691 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2692 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2693 } 2694 2695 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2696 { 2697 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2698 } 2699 2700 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2701 { 2702 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2703 2704 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2705 2706 rtl_disable_clock_request(tp); 2707 } 2708 2709 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2710 { 2711 static const struct ephy_info e_info_8168cp[] = { 2712 { 0x01, 0, 0x0001 }, 2713 { 0x02, 0x0800, 0x1000 }, 2714 { 0x03, 0, 0x0042 }, 2715 { 0x06, 0x0080, 0x0000 }, 2716 { 0x07, 0, 0x2000 } 2717 }; 2718 2719 rtl_set_def_aspm_entry_latency(tp); 2720 2721 rtl_ephy_init(tp, e_info_8168cp); 2722 2723 __rtl_hw_start_8168cp(tp); 2724 } 2725 2726 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2727 { 2728 rtl_set_def_aspm_entry_latency(tp); 2729 2730 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2731 } 2732 2733 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2734 { 2735 rtl_set_def_aspm_entry_latency(tp); 2736 2737 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2738 2739 /* Magic. */ 2740 RTL_W8(tp, DBG_REG, 0x20); 2741 } 2742 2743 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2744 { 2745 static const struct ephy_info e_info_8168c_1[] = { 2746 { 0x02, 0x0800, 0x1000 }, 2747 { 0x03, 0, 0x0002 }, 2748 { 0x06, 0x0080, 0x0000 } 2749 }; 2750 2751 rtl_set_def_aspm_entry_latency(tp); 2752 2753 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2754 2755 rtl_ephy_init(tp, e_info_8168c_1); 2756 2757 __rtl_hw_start_8168cp(tp); 2758 } 2759 2760 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2761 { 2762 static const struct ephy_info e_info_8168c_2[] = { 2763 { 0x01, 0, 0x0001 }, 2764 { 0x03, 0x0400, 0x0020 } 2765 }; 2766 2767 rtl_set_def_aspm_entry_latency(tp); 2768 2769 rtl_ephy_init(tp, e_info_8168c_2); 2770 2771 __rtl_hw_start_8168cp(tp); 2772 } 2773 2774 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2775 { 2776 rtl_set_def_aspm_entry_latency(tp); 2777 2778 __rtl_hw_start_8168cp(tp); 2779 } 2780 2781 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2782 { 2783 rtl_set_def_aspm_entry_latency(tp); 2784 2785 rtl_disable_clock_request(tp); 2786 } 2787 2788 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2789 { 2790 static const struct ephy_info e_info_8168d_4[] = { 2791 { 0x0b, 0x0000, 0x0048 }, 2792 { 0x19, 0x0020, 0x0050 }, 2793 { 0x0c, 0x0100, 0x0020 }, 2794 { 0x10, 0x0004, 0x0000 }, 2795 }; 2796 2797 rtl_set_def_aspm_entry_latency(tp); 2798 2799 rtl_ephy_init(tp, e_info_8168d_4); 2800 2801 rtl_enable_clock_request(tp); 2802 } 2803 2804 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2805 { 2806 static const struct ephy_info e_info_8168e_1[] = { 2807 { 0x00, 0x0200, 0x0100 }, 2808 { 0x00, 0x0000, 0x0004 }, 2809 { 0x06, 0x0002, 0x0001 }, 2810 { 0x06, 0x0000, 0x0030 }, 2811 { 0x07, 0x0000, 0x2000 }, 2812 { 0x00, 0x0000, 0x0020 }, 2813 { 0x03, 0x5800, 0x2000 }, 2814 { 0x03, 0x0000, 0x0001 }, 2815 { 0x01, 0x0800, 0x1000 }, 2816 { 0x07, 0x0000, 0x4000 }, 2817 { 0x1e, 0x0000, 0x2000 }, 2818 { 0x19, 0xffff, 0xfe6c }, 2819 { 0x0a, 0x0000, 0x0040 } 2820 }; 2821 2822 rtl_set_def_aspm_entry_latency(tp); 2823 2824 rtl_ephy_init(tp, e_info_8168e_1); 2825 2826 rtl_disable_clock_request(tp); 2827 2828 /* Reset tx FIFO pointer */ 2829 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2830 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2831 2832 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2833 } 2834 2835 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2836 { 2837 static const struct ephy_info e_info_8168e_2[] = { 2838 { 0x09, 0x0000, 0x0080 }, 2839 { 0x19, 0x0000, 0x0224 }, 2840 { 0x00, 0x0000, 0x0004 }, 2841 { 0x0c, 0x3df0, 0x0200 }, 2842 }; 2843 2844 rtl_set_def_aspm_entry_latency(tp); 2845 2846 rtl_ephy_init(tp, e_info_8168e_2); 2847 2848 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2849 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2850 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2851 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2852 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2853 rtl_reset_packet_filter(tp); 2854 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2855 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2856 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2857 2858 rtl_disable_clock_request(tp); 2859 2860 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2861 2862 rtl8168_config_eee_mac(tp); 2863 2864 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2865 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2866 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2867 2868 rtl_hw_aspm_clkreq_enable(tp, true); 2869 } 2870 2871 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2872 { 2873 rtl_set_def_aspm_entry_latency(tp); 2874 2875 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2876 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2877 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2878 rtl_reset_packet_filter(tp); 2879 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2880 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2881 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2882 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2883 2884 rtl_disable_clock_request(tp); 2885 2886 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2887 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2888 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2889 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2890 2891 rtl8168_config_eee_mac(tp); 2892 } 2893 2894 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2895 { 2896 static const struct ephy_info e_info_8168f_1[] = { 2897 { 0x06, 0x00c0, 0x0020 }, 2898 { 0x08, 0x0001, 0x0002 }, 2899 { 0x09, 0x0000, 0x0080 }, 2900 { 0x19, 0x0000, 0x0224 }, 2901 { 0x00, 0x0000, 0x0008 }, 2902 { 0x0c, 0x3df0, 0x0200 }, 2903 }; 2904 2905 rtl_hw_start_8168f(tp); 2906 2907 rtl_ephy_init(tp, e_info_8168f_1); 2908 2909 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2910 } 2911 2912 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2913 { 2914 static const struct ephy_info e_info_8168f_1[] = { 2915 { 0x06, 0x00c0, 0x0020 }, 2916 { 0x0f, 0xffff, 0x5200 }, 2917 { 0x19, 0x0000, 0x0224 }, 2918 { 0x00, 0x0000, 0x0008 }, 2919 { 0x0c, 0x3df0, 0x0200 }, 2920 }; 2921 2922 rtl_hw_start_8168f(tp); 2923 rtl_pcie_state_l2l3_disable(tp); 2924 2925 rtl_ephy_init(tp, e_info_8168f_1); 2926 2927 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2928 } 2929 2930 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2931 { 2932 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2933 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2934 2935 rtl_set_def_aspm_entry_latency(tp); 2936 2937 rtl_reset_packet_filter(tp); 2938 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2939 2940 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2941 2942 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2943 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2944 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2945 2946 rtl8168_config_eee_mac(tp); 2947 2948 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2949 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2950 2951 rtl_pcie_state_l2l3_disable(tp); 2952 } 2953 2954 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2955 { 2956 static const struct ephy_info e_info_8168g_1[] = { 2957 { 0x00, 0x0008, 0x0000 }, 2958 { 0x0c, 0x3ff0, 0x0820 }, 2959 { 0x1e, 0x0000, 0x0001 }, 2960 { 0x19, 0x8000, 0x0000 } 2961 }; 2962 2963 rtl_hw_start_8168g(tp); 2964 2965 /* disable aspm and clock request before access ephy */ 2966 rtl_hw_aspm_clkreq_enable(tp, false); 2967 rtl_ephy_init(tp, e_info_8168g_1); 2968 rtl_hw_aspm_clkreq_enable(tp, true); 2969 } 2970 2971 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 2972 { 2973 static const struct ephy_info e_info_8168g_2[] = { 2974 { 0x00, 0x0008, 0x0000 }, 2975 { 0x0c, 0x3ff0, 0x0820 }, 2976 { 0x19, 0xffff, 0x7c00 }, 2977 { 0x1e, 0xffff, 0x20eb }, 2978 { 0x0d, 0xffff, 0x1666 }, 2979 { 0x00, 0xffff, 0x10a3 }, 2980 { 0x06, 0xffff, 0xf050 }, 2981 { 0x04, 0x0000, 0x0010 }, 2982 { 0x1d, 0x4000, 0x0000 }, 2983 }; 2984 2985 rtl_hw_start_8168g(tp); 2986 2987 /* disable aspm and clock request before access ephy */ 2988 rtl_hw_aspm_clkreq_enable(tp, false); 2989 rtl_ephy_init(tp, e_info_8168g_2); 2990 } 2991 2992 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 2993 { 2994 static const struct ephy_info e_info_8411_2[] = { 2995 { 0x00, 0x0008, 0x0000 }, 2996 { 0x0c, 0x37d0, 0x0820 }, 2997 { 0x1e, 0x0000, 0x0001 }, 2998 { 0x19, 0x8021, 0x0000 }, 2999 { 0x1e, 0x0000, 0x2000 }, 3000 { 0x0d, 0x0100, 0x0200 }, 3001 { 0x00, 0x0000, 0x0080 }, 3002 { 0x06, 0x0000, 0x0010 }, 3003 { 0x04, 0x0000, 0x0010 }, 3004 { 0x1d, 0x0000, 0x4000 }, 3005 }; 3006 3007 rtl_hw_start_8168g(tp); 3008 3009 /* disable aspm and clock request before access ephy */ 3010 rtl_hw_aspm_clkreq_enable(tp, false); 3011 rtl_ephy_init(tp, e_info_8411_2); 3012 3013 /* The following Realtek-provided magic fixes an issue with the RX unit 3014 * getting confused after the PHY having been powered-down. 3015 */ 3016 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3017 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3018 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3019 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3020 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3021 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3022 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3023 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3024 mdelay(3); 3025 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3026 3027 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3028 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3029 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3030 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3031 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3032 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3033 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3034 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3035 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3036 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3037 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3038 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3039 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3040 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3041 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3042 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3043 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3044 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3045 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3046 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3047 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3048 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3049 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3050 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3051 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3052 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3053 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3054 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3055 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3056 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3057 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3058 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3059 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3060 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3061 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3062 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3063 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3064 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3065 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3066 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3067 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3068 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3069 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3070 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3071 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3072 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3073 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3074 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3075 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3076 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3077 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3078 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3079 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3080 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3081 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3082 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3083 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3084 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3085 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3086 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3087 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3088 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3089 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3090 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3091 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3092 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3093 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3094 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3095 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3096 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3097 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3098 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3099 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3100 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3101 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3102 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3103 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3104 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3105 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3106 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3107 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3108 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3109 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3110 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3111 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3112 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3113 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3114 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3115 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3116 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3117 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3118 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3119 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3120 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3121 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3122 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3123 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3124 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3125 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3126 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3127 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3128 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3129 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3130 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3131 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3132 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3133 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3134 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3135 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3136 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3137 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3138 3139 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3140 3141 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3142 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3143 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3144 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3145 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3146 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3147 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3148 3149 rtl_hw_aspm_clkreq_enable(tp, true); 3150 } 3151 3152 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3153 { 3154 static const struct ephy_info e_info_8168h_1[] = { 3155 { 0x1e, 0x0800, 0x0001 }, 3156 { 0x1d, 0x0000, 0x0800 }, 3157 { 0x05, 0xffff, 0x2089 }, 3158 { 0x06, 0xffff, 0x5881 }, 3159 { 0x04, 0xffff, 0x854a }, 3160 { 0x01, 0xffff, 0x068b } 3161 }; 3162 int rg_saw_cnt; 3163 3164 /* disable aspm and clock request before access ephy */ 3165 rtl_hw_aspm_clkreq_enable(tp, false); 3166 rtl_ephy_init(tp, e_info_8168h_1); 3167 3168 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3169 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3170 3171 rtl_set_def_aspm_entry_latency(tp); 3172 3173 rtl_reset_packet_filter(tp); 3174 3175 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3176 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3177 3178 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3179 3180 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3181 3182 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3183 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3184 3185 rtl8168_config_eee_mac(tp); 3186 3187 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3188 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3189 3190 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3191 3192 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3193 3194 rtl_pcie_state_l2l3_disable(tp); 3195 3196 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3197 if (rg_saw_cnt > 0) { 3198 u16 sw_cnt_1ms_ini; 3199 3200 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3201 sw_cnt_1ms_ini &= 0x0fff; 3202 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3203 } 3204 3205 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3206 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3207 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3208 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3209 3210 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3211 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3212 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3213 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3214 3215 rtl_hw_aspm_clkreq_enable(tp, true); 3216 } 3217 3218 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3219 { 3220 rtl8168ep_stop_cmac(tp); 3221 3222 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3223 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3224 3225 rtl_set_def_aspm_entry_latency(tp); 3226 3227 rtl_reset_packet_filter(tp); 3228 3229 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3230 3231 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3232 3233 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3234 3235 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3236 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3237 3238 rtl8168_config_eee_mac(tp); 3239 3240 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3241 3242 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3243 3244 rtl_pcie_state_l2l3_disable(tp); 3245 } 3246 3247 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3248 { 3249 static const struct ephy_info e_info_8168ep_1[] = { 3250 { 0x00, 0xffff, 0x10ab }, 3251 { 0x06, 0xffff, 0xf030 }, 3252 { 0x08, 0xffff, 0x2006 }, 3253 { 0x0d, 0xffff, 0x1666 }, 3254 { 0x0c, 0x3ff0, 0x0000 } 3255 }; 3256 3257 /* disable aspm and clock request before access ephy */ 3258 rtl_hw_aspm_clkreq_enable(tp, false); 3259 rtl_ephy_init(tp, e_info_8168ep_1); 3260 3261 rtl_hw_start_8168ep(tp); 3262 3263 rtl_hw_aspm_clkreq_enable(tp, true); 3264 } 3265 3266 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3267 { 3268 static const struct ephy_info e_info_8168ep_2[] = { 3269 { 0x00, 0xffff, 0x10a3 }, 3270 { 0x19, 0xffff, 0xfc00 }, 3271 { 0x1e, 0xffff, 0x20ea } 3272 }; 3273 3274 /* disable aspm and clock request before access ephy */ 3275 rtl_hw_aspm_clkreq_enable(tp, false); 3276 rtl_ephy_init(tp, e_info_8168ep_2); 3277 3278 rtl_hw_start_8168ep(tp); 3279 3280 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3281 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3282 3283 rtl_hw_aspm_clkreq_enable(tp, true); 3284 } 3285 3286 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3287 { 3288 static const struct ephy_info e_info_8168ep_3[] = { 3289 { 0x00, 0x0000, 0x0080 }, 3290 { 0x0d, 0x0100, 0x0200 }, 3291 { 0x19, 0x8021, 0x0000 }, 3292 { 0x1e, 0x0000, 0x2000 }, 3293 }; 3294 3295 /* disable aspm and clock request before access ephy */ 3296 rtl_hw_aspm_clkreq_enable(tp, false); 3297 rtl_ephy_init(tp, e_info_8168ep_3); 3298 3299 rtl_hw_start_8168ep(tp); 3300 3301 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3302 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3303 3304 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3305 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3306 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3307 3308 rtl_hw_aspm_clkreq_enable(tp, true); 3309 } 3310 3311 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3312 { 3313 static const struct ephy_info e_info_8117[] = { 3314 { 0x19, 0x0040, 0x1100 }, 3315 { 0x59, 0x0040, 0x1100 }, 3316 }; 3317 int rg_saw_cnt; 3318 3319 rtl8168ep_stop_cmac(tp); 3320 3321 /* disable aspm and clock request before access ephy */ 3322 rtl_hw_aspm_clkreq_enable(tp, false); 3323 rtl_ephy_init(tp, e_info_8117); 3324 3325 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3326 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3327 3328 rtl_set_def_aspm_entry_latency(tp); 3329 3330 rtl_reset_packet_filter(tp); 3331 3332 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3333 3334 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3335 3336 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3337 3338 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3339 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3340 3341 rtl8168_config_eee_mac(tp); 3342 3343 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3344 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3345 3346 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3347 3348 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3349 3350 rtl_pcie_state_l2l3_disable(tp); 3351 3352 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3353 if (rg_saw_cnt > 0) { 3354 u16 sw_cnt_1ms_ini; 3355 3356 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3357 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3358 } 3359 3360 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3361 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3362 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3363 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3364 3365 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3366 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3367 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3368 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3369 3370 /* firmware is for MAC only */ 3371 r8169_apply_firmware(tp); 3372 3373 rtl_hw_aspm_clkreq_enable(tp, true); 3374 } 3375 3376 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3377 { 3378 static const struct ephy_info e_info_8102e_1[] = { 3379 { 0x01, 0, 0x6e65 }, 3380 { 0x02, 0, 0x091f }, 3381 { 0x03, 0, 0xc2f9 }, 3382 { 0x06, 0, 0xafb5 }, 3383 { 0x07, 0, 0x0e00 }, 3384 { 0x19, 0, 0xec80 }, 3385 { 0x01, 0, 0x2e65 }, 3386 { 0x01, 0, 0x6e65 } 3387 }; 3388 u8 cfg1; 3389 3390 rtl_set_def_aspm_entry_latency(tp); 3391 3392 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3393 3394 RTL_W8(tp, Config1, 3395 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3396 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3397 3398 cfg1 = RTL_R8(tp, Config1); 3399 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3400 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3401 3402 rtl_ephy_init(tp, e_info_8102e_1); 3403 } 3404 3405 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3406 { 3407 rtl_set_def_aspm_entry_latency(tp); 3408 3409 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3410 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3411 } 3412 3413 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3414 { 3415 rtl_hw_start_8102e_2(tp); 3416 3417 rtl_ephy_write(tp, 0x03, 0xc2f9); 3418 } 3419 3420 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3421 { 3422 static const struct ephy_info e_info_8401[] = { 3423 { 0x01, 0xffff, 0x6fe5 }, 3424 { 0x03, 0xffff, 0x0599 }, 3425 { 0x06, 0xffff, 0xaf25 }, 3426 { 0x07, 0xffff, 0x8e68 }, 3427 }; 3428 3429 rtl_ephy_init(tp, e_info_8401); 3430 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3431 } 3432 3433 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3434 { 3435 static const struct ephy_info e_info_8105e_1[] = { 3436 { 0x07, 0, 0x4000 }, 3437 { 0x19, 0, 0x0200 }, 3438 { 0x19, 0, 0x0020 }, 3439 { 0x1e, 0, 0x2000 }, 3440 { 0x03, 0, 0x0001 }, 3441 { 0x19, 0, 0x0100 }, 3442 { 0x19, 0, 0x0004 }, 3443 { 0x0a, 0, 0x0020 } 3444 }; 3445 3446 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3447 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3448 3449 /* Disable Early Tally Counter */ 3450 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3451 3452 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3453 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3454 3455 rtl_ephy_init(tp, e_info_8105e_1); 3456 3457 rtl_pcie_state_l2l3_disable(tp); 3458 } 3459 3460 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3461 { 3462 rtl_hw_start_8105e_1(tp); 3463 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3464 } 3465 3466 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3467 { 3468 static const struct ephy_info e_info_8402[] = { 3469 { 0x19, 0xffff, 0xff64 }, 3470 { 0x1e, 0, 0x4000 } 3471 }; 3472 3473 rtl_set_def_aspm_entry_latency(tp); 3474 3475 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3476 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3477 3478 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3479 3480 rtl_ephy_init(tp, e_info_8402); 3481 3482 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3483 rtl_reset_packet_filter(tp); 3484 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3485 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3486 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3487 3488 /* disable EEE */ 3489 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3490 3491 rtl_pcie_state_l2l3_disable(tp); 3492 } 3493 3494 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3495 { 3496 rtl_hw_aspm_clkreq_enable(tp, false); 3497 3498 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3499 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3500 3501 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3502 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3503 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3504 3505 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3506 3507 /* disable EEE */ 3508 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3509 3510 rtl_pcie_state_l2l3_disable(tp); 3511 } 3512 3513 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3514 { 3515 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3516 } 3517 3518 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3519 { 3520 rtl_pcie_state_l2l3_disable(tp); 3521 3522 RTL_W16(tp, 0x382, 0x221b); 3523 RTL_W8(tp, 0x4500, 0); 3524 RTL_W16(tp, 0x4800, 0); 3525 3526 /* disable UPS */ 3527 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3528 3529 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3530 3531 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3532 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3533 3534 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3535 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3536 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3537 3538 /* disable new tx descriptor format */ 3539 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3540 3541 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3542 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3543 else 3544 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3545 3546 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3547 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3548 else 3549 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3550 3551 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3552 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3553 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3554 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3555 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3556 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3557 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3558 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3559 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3560 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3561 3562 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3563 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3564 udelay(1); 3565 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3566 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3567 3568 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3569 3570 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3571 3572 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3573 rtl8125b_config_eee_mac(tp); 3574 else 3575 rtl8125a_config_eee_mac(tp); 3576 3577 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3578 udelay(10); 3579 } 3580 3581 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3582 { 3583 static const struct ephy_info e_info_8125a_1[] = { 3584 { 0x01, 0xffff, 0xa812 }, 3585 { 0x09, 0xffff, 0x520c }, 3586 { 0x04, 0xffff, 0xd000 }, 3587 { 0x0d, 0xffff, 0xf702 }, 3588 { 0x0a, 0xffff, 0x8653 }, 3589 { 0x06, 0xffff, 0x001e }, 3590 { 0x08, 0xffff, 0x3595 }, 3591 { 0x20, 0xffff, 0x9455 }, 3592 { 0x21, 0xffff, 0x99ff }, 3593 { 0x02, 0xffff, 0x6046 }, 3594 { 0x29, 0xffff, 0xfe00 }, 3595 { 0x23, 0xffff, 0xab62 }, 3596 3597 { 0x41, 0xffff, 0xa80c }, 3598 { 0x49, 0xffff, 0x520c }, 3599 { 0x44, 0xffff, 0xd000 }, 3600 { 0x4d, 0xffff, 0xf702 }, 3601 { 0x4a, 0xffff, 0x8653 }, 3602 { 0x46, 0xffff, 0x001e }, 3603 { 0x48, 0xffff, 0x3595 }, 3604 { 0x60, 0xffff, 0x9455 }, 3605 { 0x61, 0xffff, 0x99ff }, 3606 { 0x42, 0xffff, 0x6046 }, 3607 { 0x69, 0xffff, 0xfe00 }, 3608 { 0x63, 0xffff, 0xab62 }, 3609 }; 3610 3611 rtl_set_def_aspm_entry_latency(tp); 3612 3613 /* disable aspm and clock request before access ephy */ 3614 rtl_hw_aspm_clkreq_enable(tp, false); 3615 rtl_ephy_init(tp, e_info_8125a_1); 3616 3617 rtl_hw_start_8125_common(tp); 3618 rtl_hw_aspm_clkreq_enable(tp, true); 3619 } 3620 3621 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3622 { 3623 static const struct ephy_info e_info_8125a_2[] = { 3624 { 0x04, 0xffff, 0xd000 }, 3625 { 0x0a, 0xffff, 0x8653 }, 3626 { 0x23, 0xffff, 0xab66 }, 3627 { 0x20, 0xffff, 0x9455 }, 3628 { 0x21, 0xffff, 0x99ff }, 3629 { 0x29, 0xffff, 0xfe04 }, 3630 3631 { 0x44, 0xffff, 0xd000 }, 3632 { 0x4a, 0xffff, 0x8653 }, 3633 { 0x63, 0xffff, 0xab66 }, 3634 { 0x60, 0xffff, 0x9455 }, 3635 { 0x61, 0xffff, 0x99ff }, 3636 { 0x69, 0xffff, 0xfe04 }, 3637 }; 3638 3639 rtl_set_def_aspm_entry_latency(tp); 3640 3641 /* disable aspm and clock request before access ephy */ 3642 rtl_hw_aspm_clkreq_enable(tp, false); 3643 rtl_ephy_init(tp, e_info_8125a_2); 3644 3645 rtl_hw_start_8125_common(tp); 3646 rtl_hw_aspm_clkreq_enable(tp, true); 3647 } 3648 3649 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3650 { 3651 static const struct ephy_info e_info_8125b[] = { 3652 { 0x0b, 0xffff, 0xa908 }, 3653 { 0x1e, 0xffff, 0x20eb }, 3654 { 0x4b, 0xffff, 0xa908 }, 3655 { 0x5e, 0xffff, 0x20eb }, 3656 { 0x22, 0x0030, 0x0020 }, 3657 { 0x62, 0x0030, 0x0020 }, 3658 }; 3659 3660 rtl_set_def_aspm_entry_latency(tp); 3661 rtl_hw_aspm_clkreq_enable(tp, false); 3662 3663 rtl_ephy_init(tp, e_info_8125b); 3664 rtl_hw_start_8125_common(tp); 3665 3666 rtl_hw_aspm_clkreq_enable(tp, true); 3667 } 3668 3669 static void rtl_hw_config(struct rtl8169_private *tp) 3670 { 3671 static const rtl_generic_fct hw_configs[] = { 3672 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3673 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3674 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3675 [RTL_GIGA_MAC_VER_10] = NULL, 3676 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3677 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3678 [RTL_GIGA_MAC_VER_13] = NULL, 3679 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3680 [RTL_GIGA_MAC_VER_16] = NULL, 3681 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3682 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3683 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3684 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3685 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3686 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3687 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3688 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3689 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3690 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3691 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3692 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3693 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3694 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3695 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3696 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3697 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3698 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3699 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3700 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3701 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3702 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3703 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3704 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3705 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3706 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3707 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3708 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3709 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3710 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3711 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3712 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3713 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3714 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3715 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3716 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3717 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3718 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3719 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3720 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3721 }; 3722 3723 if (hw_configs[tp->mac_version]) 3724 hw_configs[tp->mac_version](tp); 3725 } 3726 3727 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3728 { 3729 int i; 3730 3731 /* disable interrupt coalescing */ 3732 for (i = 0xa00; i < 0xb00; i += 4) 3733 RTL_W32(tp, i, 0); 3734 3735 rtl_hw_config(tp); 3736 } 3737 3738 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3739 { 3740 if (rtl_is_8168evl_up(tp)) 3741 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3742 else 3743 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3744 3745 rtl_hw_config(tp); 3746 3747 /* disable interrupt coalescing */ 3748 RTL_W16(tp, IntrMitigate, 0x0000); 3749 } 3750 3751 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3752 { 3753 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3754 3755 tp->cp_cmd |= PCIMulRW; 3756 3757 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3758 tp->mac_version == RTL_GIGA_MAC_VER_03) 3759 tp->cp_cmd |= EnAnaPLL; 3760 3761 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3762 3763 rtl8169_set_magic_reg(tp); 3764 3765 /* disable interrupt coalescing */ 3766 RTL_W16(tp, IntrMitigate, 0x0000); 3767 } 3768 3769 static void rtl_hw_start(struct rtl8169_private *tp) 3770 { 3771 rtl_unlock_config_regs(tp); 3772 3773 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3774 3775 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3776 rtl_hw_start_8169(tp); 3777 else if (rtl_is_8125(tp)) 3778 rtl_hw_start_8125(tp); 3779 else 3780 rtl_hw_start_8168(tp); 3781 3782 rtl_set_rx_max_size(tp); 3783 rtl_set_rx_tx_desc_registers(tp); 3784 rtl_lock_config_regs(tp); 3785 3786 rtl_jumbo_config(tp); 3787 3788 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3789 rtl_pci_commit(tp); 3790 3791 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3792 rtl_init_rxcfg(tp); 3793 rtl_set_tx_config_registers(tp); 3794 rtl_set_rx_config_features(tp, tp->dev->features); 3795 rtl_set_rx_mode(tp->dev); 3796 rtl_irq_enable(tp); 3797 } 3798 3799 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3800 { 3801 struct rtl8169_private *tp = netdev_priv(dev); 3802 3803 dev->mtu = new_mtu; 3804 netdev_update_features(dev); 3805 rtl_jumbo_config(tp); 3806 3807 switch (tp->mac_version) { 3808 case RTL_GIGA_MAC_VER_61: 3809 case RTL_GIGA_MAC_VER_63: 3810 rtl8125_set_eee_txidle_timer(tp); 3811 break; 3812 default: 3813 break; 3814 } 3815 3816 return 0; 3817 } 3818 3819 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3820 { 3821 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3822 3823 desc->opts2 = 0; 3824 /* Force memory writes to complete before releasing descriptor */ 3825 dma_wmb(); 3826 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3827 } 3828 3829 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3830 struct RxDesc *desc) 3831 { 3832 struct device *d = tp_to_dev(tp); 3833 int node = dev_to_node(d); 3834 dma_addr_t mapping; 3835 struct page *data; 3836 3837 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3838 if (!data) 3839 return NULL; 3840 3841 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3842 if (unlikely(dma_mapping_error(d, mapping))) { 3843 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3844 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3845 return NULL; 3846 } 3847 3848 desc->addr = cpu_to_le64(mapping); 3849 rtl8169_mark_to_asic(desc); 3850 3851 return data; 3852 } 3853 3854 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3855 { 3856 int i; 3857 3858 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3859 dma_unmap_page(tp_to_dev(tp), 3860 le64_to_cpu(tp->RxDescArray[i].addr), 3861 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3862 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3863 tp->Rx_databuff[i] = NULL; 3864 tp->RxDescArray[i].addr = 0; 3865 tp->RxDescArray[i].opts1 = 0; 3866 } 3867 } 3868 3869 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3870 { 3871 int i; 3872 3873 for (i = 0; i < NUM_RX_DESC; i++) { 3874 struct page *data; 3875 3876 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3877 if (!data) { 3878 rtl8169_rx_clear(tp); 3879 return -ENOMEM; 3880 } 3881 tp->Rx_databuff[i] = data; 3882 } 3883 3884 /* mark as last descriptor in the ring */ 3885 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3886 3887 return 0; 3888 } 3889 3890 static int rtl8169_init_ring(struct rtl8169_private *tp) 3891 { 3892 rtl8169_init_ring_indexes(tp); 3893 3894 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3895 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3896 3897 return rtl8169_rx_fill(tp); 3898 } 3899 3900 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3901 { 3902 struct ring_info *tx_skb = tp->tx_skb + entry; 3903 struct TxDesc *desc = tp->TxDescArray + entry; 3904 3905 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3906 DMA_TO_DEVICE); 3907 memset(desc, 0, sizeof(*desc)); 3908 memset(tx_skb, 0, sizeof(*tx_skb)); 3909 } 3910 3911 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3912 unsigned int n) 3913 { 3914 unsigned int i; 3915 3916 for (i = 0; i < n; i++) { 3917 unsigned int entry = (start + i) % NUM_TX_DESC; 3918 struct ring_info *tx_skb = tp->tx_skb + entry; 3919 unsigned int len = tx_skb->len; 3920 3921 if (len) { 3922 struct sk_buff *skb = tx_skb->skb; 3923 3924 rtl8169_unmap_tx_skb(tp, entry); 3925 if (skb) 3926 dev_consume_skb_any(skb); 3927 } 3928 } 3929 } 3930 3931 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3932 { 3933 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3934 netdev_reset_queue(tp->dev); 3935 } 3936 3937 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3938 { 3939 napi_disable(&tp->napi); 3940 3941 /* Give a racing hard_start_xmit a few cycles to complete. */ 3942 synchronize_net(); 3943 3944 /* Disable interrupts */ 3945 rtl8169_irq_mask_and_ack(tp); 3946 3947 rtl_rx_close(tp); 3948 3949 if (going_down && tp->dev->wol_enabled) 3950 goto no_reset; 3951 3952 switch (tp->mac_version) { 3953 case RTL_GIGA_MAC_VER_27: 3954 case RTL_GIGA_MAC_VER_28: 3955 case RTL_GIGA_MAC_VER_31: 3956 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3957 break; 3958 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3959 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3960 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3961 break; 3962 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3963 rtl_enable_rxdvgate(tp); 3964 fsleep(2000); 3965 break; 3966 default: 3967 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3968 fsleep(100); 3969 break; 3970 } 3971 3972 rtl_hw_reset(tp); 3973 no_reset: 3974 rtl8169_tx_clear(tp); 3975 rtl8169_init_ring_indexes(tp); 3976 } 3977 3978 static void rtl_reset_work(struct rtl8169_private *tp) 3979 { 3980 int i; 3981 3982 netif_stop_queue(tp->dev); 3983 3984 rtl8169_cleanup(tp, false); 3985 3986 for (i = 0; i < NUM_RX_DESC; i++) 3987 rtl8169_mark_to_asic(tp->RxDescArray + i); 3988 3989 napi_enable(&tp->napi); 3990 rtl_hw_start(tp); 3991 } 3992 3993 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3994 { 3995 struct rtl8169_private *tp = netdev_priv(dev); 3996 3997 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3998 } 3999 4000 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4001 void *addr, unsigned int entry, bool desc_own) 4002 { 4003 struct TxDesc *txd = tp->TxDescArray + entry; 4004 struct device *d = tp_to_dev(tp); 4005 dma_addr_t mapping; 4006 u32 opts1; 4007 int ret; 4008 4009 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4010 ret = dma_mapping_error(d, mapping); 4011 if (unlikely(ret)) { 4012 if (net_ratelimit()) 4013 netdev_err(tp->dev, "Failed to map TX data!\n"); 4014 return ret; 4015 } 4016 4017 txd->addr = cpu_to_le64(mapping); 4018 txd->opts2 = cpu_to_le32(opts[1]); 4019 4020 opts1 = opts[0] | len; 4021 if (entry == NUM_TX_DESC - 1) 4022 opts1 |= RingEnd; 4023 if (desc_own) 4024 opts1 |= DescOwn; 4025 txd->opts1 = cpu_to_le32(opts1); 4026 4027 tp->tx_skb[entry].len = len; 4028 4029 return 0; 4030 } 4031 4032 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4033 const u32 *opts, unsigned int entry) 4034 { 4035 struct skb_shared_info *info = skb_shinfo(skb); 4036 unsigned int cur_frag; 4037 4038 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4039 const skb_frag_t *frag = info->frags + cur_frag; 4040 void *addr = skb_frag_address(frag); 4041 u32 len = skb_frag_size(frag); 4042 4043 entry = (entry + 1) % NUM_TX_DESC; 4044 4045 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4046 goto err_out; 4047 } 4048 4049 return 0; 4050 4051 err_out: 4052 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4053 return -EIO; 4054 } 4055 4056 static bool rtl_skb_is_udp(struct sk_buff *skb) 4057 { 4058 int no = skb_network_offset(skb); 4059 struct ipv6hdr *i6h, _i6h; 4060 struct iphdr *ih, _ih; 4061 4062 switch (vlan_get_protocol(skb)) { 4063 case htons(ETH_P_IP): 4064 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4065 return ih && ih->protocol == IPPROTO_UDP; 4066 case htons(ETH_P_IPV6): 4067 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4068 return i6h && i6h->nexthdr == IPPROTO_UDP; 4069 default: 4070 return false; 4071 } 4072 } 4073 4074 #define RTL_MIN_PATCH_LEN 47 4075 4076 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4077 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4078 struct sk_buff *skb) 4079 { 4080 unsigned int padto = 0, len = skb->len; 4081 4082 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4083 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4084 unsigned int trans_data_len = skb_tail_pointer(skb) - 4085 skb_transport_header(skb); 4086 4087 if (trans_data_len >= offsetof(struct udphdr, len) && 4088 trans_data_len < RTL_MIN_PATCH_LEN) { 4089 u16 dest = ntohs(udp_hdr(skb)->dest); 4090 4091 /* dest is a standard PTP port */ 4092 if (dest == 319 || dest == 320) 4093 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4094 } 4095 4096 if (trans_data_len < sizeof(struct udphdr)) 4097 padto = max_t(unsigned int, padto, 4098 len + sizeof(struct udphdr) - trans_data_len); 4099 } 4100 4101 return padto; 4102 } 4103 4104 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4105 struct sk_buff *skb) 4106 { 4107 unsigned int padto; 4108 4109 padto = rtl8125_quirk_udp_padto(tp, skb); 4110 4111 switch (tp->mac_version) { 4112 case RTL_GIGA_MAC_VER_34: 4113 case RTL_GIGA_MAC_VER_60: 4114 case RTL_GIGA_MAC_VER_61: 4115 case RTL_GIGA_MAC_VER_63: 4116 padto = max_t(unsigned int, padto, ETH_ZLEN); 4117 break; 4118 default: 4119 break; 4120 } 4121 4122 return padto; 4123 } 4124 4125 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4126 { 4127 u32 mss = skb_shinfo(skb)->gso_size; 4128 4129 if (mss) { 4130 opts[0] |= TD_LSO; 4131 opts[0] |= mss << TD0_MSS_SHIFT; 4132 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4133 const struct iphdr *ip = ip_hdr(skb); 4134 4135 if (ip->protocol == IPPROTO_TCP) 4136 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4137 else if (ip->protocol == IPPROTO_UDP) 4138 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4139 else 4140 WARN_ON_ONCE(1); 4141 } 4142 } 4143 4144 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4145 struct sk_buff *skb, u32 *opts) 4146 { 4147 u32 transport_offset = (u32)skb_transport_offset(skb); 4148 struct skb_shared_info *shinfo = skb_shinfo(skb); 4149 u32 mss = shinfo->gso_size; 4150 4151 if (mss) { 4152 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4153 opts[0] |= TD1_GTSENV4; 4154 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4155 if (skb_cow_head(skb, 0)) 4156 return false; 4157 4158 tcp_v6_gso_csum_prep(skb); 4159 opts[0] |= TD1_GTSENV6; 4160 } else { 4161 WARN_ON_ONCE(1); 4162 } 4163 4164 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4165 opts[1] |= mss << TD1_MSS_SHIFT; 4166 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4167 u8 ip_protocol; 4168 4169 switch (vlan_get_protocol(skb)) { 4170 case htons(ETH_P_IP): 4171 opts[1] |= TD1_IPv4_CS; 4172 ip_protocol = ip_hdr(skb)->protocol; 4173 break; 4174 4175 case htons(ETH_P_IPV6): 4176 opts[1] |= TD1_IPv6_CS; 4177 ip_protocol = ipv6_hdr(skb)->nexthdr; 4178 break; 4179 4180 default: 4181 ip_protocol = IPPROTO_RAW; 4182 break; 4183 } 4184 4185 if (ip_protocol == IPPROTO_TCP) 4186 opts[1] |= TD1_TCP_CS; 4187 else if (ip_protocol == IPPROTO_UDP) 4188 opts[1] |= TD1_UDP_CS; 4189 else 4190 WARN_ON_ONCE(1); 4191 4192 opts[1] |= transport_offset << TCPHO_SHIFT; 4193 } else { 4194 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4195 4196 /* skb_padto would free the skb on error */ 4197 return !__skb_put_padto(skb, padto, false); 4198 } 4199 4200 return true; 4201 } 4202 4203 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4204 { 4205 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4206 - READ_ONCE(tp->cur_tx); 4207 4208 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4209 return slots_avail > MAX_SKB_FRAGS; 4210 } 4211 4212 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4213 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4214 { 4215 switch (tp->mac_version) { 4216 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4217 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4218 return false; 4219 default: 4220 return true; 4221 } 4222 } 4223 4224 static void rtl8169_doorbell(struct rtl8169_private *tp) 4225 { 4226 if (rtl_is_8125(tp)) 4227 RTL_W16(tp, TxPoll_8125, BIT(0)); 4228 else 4229 RTL_W8(tp, TxPoll, NPQ); 4230 } 4231 4232 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4233 struct net_device *dev) 4234 { 4235 unsigned int frags = skb_shinfo(skb)->nr_frags; 4236 struct rtl8169_private *tp = netdev_priv(dev); 4237 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4238 struct TxDesc *txd_first, *txd_last; 4239 bool stop_queue, door_bell; 4240 u32 opts[2]; 4241 4242 if (unlikely(!rtl_tx_slots_avail(tp))) { 4243 if (net_ratelimit()) 4244 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4245 goto err_stop_0; 4246 } 4247 4248 opts[1] = rtl8169_tx_vlan_tag(skb); 4249 opts[0] = 0; 4250 4251 if (!rtl_chip_supports_csum_v2(tp)) 4252 rtl8169_tso_csum_v1(skb, opts); 4253 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4254 goto err_dma_0; 4255 4256 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4257 entry, false))) 4258 goto err_dma_0; 4259 4260 txd_first = tp->TxDescArray + entry; 4261 4262 if (frags) { 4263 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4264 goto err_dma_1; 4265 entry = (entry + frags) % NUM_TX_DESC; 4266 } 4267 4268 txd_last = tp->TxDescArray + entry; 4269 txd_last->opts1 |= cpu_to_le32(LastFrag); 4270 tp->tx_skb[entry].skb = skb; 4271 4272 skb_tx_timestamp(skb); 4273 4274 /* Force memory writes to complete before releasing descriptor */ 4275 dma_wmb(); 4276 4277 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4278 4279 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4280 4281 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4282 smp_wmb(); 4283 4284 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4285 4286 stop_queue = !rtl_tx_slots_avail(tp); 4287 if (unlikely(stop_queue)) { 4288 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4289 * not miss a ring update when it notices a stopped queue. 4290 */ 4291 smp_wmb(); 4292 netif_stop_queue(dev); 4293 /* Sync with rtl_tx: 4294 * - publish queue status and cur_tx ring index (write barrier) 4295 * - refresh dirty_tx ring index (read barrier). 4296 * May the current thread have a pessimistic view of the ring 4297 * status and forget to wake up queue, a racing rtl_tx thread 4298 * can't. 4299 */ 4300 smp_mb__after_atomic(); 4301 if (rtl_tx_slots_avail(tp)) 4302 netif_start_queue(dev); 4303 door_bell = true; 4304 } 4305 4306 if (door_bell) 4307 rtl8169_doorbell(tp); 4308 4309 return NETDEV_TX_OK; 4310 4311 err_dma_1: 4312 rtl8169_unmap_tx_skb(tp, entry); 4313 err_dma_0: 4314 dev_kfree_skb_any(skb); 4315 dev->stats.tx_dropped++; 4316 return NETDEV_TX_OK; 4317 4318 err_stop_0: 4319 netif_stop_queue(dev); 4320 dev->stats.tx_dropped++; 4321 return NETDEV_TX_BUSY; 4322 } 4323 4324 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4325 { 4326 struct skb_shared_info *info = skb_shinfo(skb); 4327 unsigned int nr_frags = info->nr_frags; 4328 4329 if (!nr_frags) 4330 return UINT_MAX; 4331 4332 return skb_frag_size(info->frags + nr_frags - 1); 4333 } 4334 4335 /* Workaround for hw issues with TSO on RTL8168evl */ 4336 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4337 netdev_features_t features) 4338 { 4339 /* IPv4 header has options field */ 4340 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4341 ip_hdrlen(skb) > sizeof(struct iphdr)) 4342 features &= ~NETIF_F_ALL_TSO; 4343 4344 /* IPv4 TCP header has options field */ 4345 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4346 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4347 features &= ~NETIF_F_ALL_TSO; 4348 4349 else if (rtl_last_frag_len(skb) <= 6) 4350 features &= ~NETIF_F_ALL_TSO; 4351 4352 return features; 4353 } 4354 4355 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4356 struct net_device *dev, 4357 netdev_features_t features) 4358 { 4359 int transport_offset = skb_transport_offset(skb); 4360 struct rtl8169_private *tp = netdev_priv(dev); 4361 4362 if (skb_is_gso(skb)) { 4363 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4364 features = rtl8168evl_fix_tso(skb, features); 4365 4366 if (transport_offset > GTTCPHO_MAX && 4367 rtl_chip_supports_csum_v2(tp)) 4368 features &= ~NETIF_F_ALL_TSO; 4369 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4370 /* work around hw bug on some chip versions */ 4371 if (skb->len < ETH_ZLEN) 4372 features &= ~NETIF_F_CSUM_MASK; 4373 4374 if (rtl_quirk_packet_padto(tp, skb)) 4375 features &= ~NETIF_F_CSUM_MASK; 4376 4377 if (transport_offset > TCPHO_MAX && 4378 rtl_chip_supports_csum_v2(tp)) 4379 features &= ~NETIF_F_CSUM_MASK; 4380 } 4381 4382 return vlan_features_check(skb, features); 4383 } 4384 4385 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4386 { 4387 struct rtl8169_private *tp = netdev_priv(dev); 4388 struct pci_dev *pdev = tp->pci_dev; 4389 int pci_status_errs; 4390 u16 pci_cmd; 4391 4392 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4393 4394 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4395 4396 if (net_ratelimit()) 4397 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4398 pci_cmd, pci_status_errs); 4399 4400 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4401 } 4402 4403 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4404 int budget) 4405 { 4406 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4407 struct sk_buff *skb; 4408 4409 dirty_tx = tp->dirty_tx; 4410 4411 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4412 unsigned int entry = dirty_tx % NUM_TX_DESC; 4413 u32 status; 4414 4415 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4416 if (status & DescOwn) 4417 break; 4418 4419 skb = tp->tx_skb[entry].skb; 4420 rtl8169_unmap_tx_skb(tp, entry); 4421 4422 if (skb) { 4423 pkts_compl++; 4424 bytes_compl += skb->len; 4425 napi_consume_skb(skb, budget); 4426 } 4427 dirty_tx++; 4428 } 4429 4430 if (tp->dirty_tx != dirty_tx) { 4431 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4432 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4433 4434 /* Sync with rtl8169_start_xmit: 4435 * - publish dirty_tx ring index (write barrier) 4436 * - refresh cur_tx ring index and queue status (read barrier) 4437 * May the current thread miss the stopped queue condition, 4438 * a racing xmit thread can only have a right view of the 4439 * ring status. 4440 */ 4441 smp_store_mb(tp->dirty_tx, dirty_tx); 4442 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4443 netif_wake_queue(dev); 4444 /* 4445 * 8168 hack: TxPoll requests are lost when the Tx packets are 4446 * too close. Let's kick an extra TxPoll request when a burst 4447 * of start_xmit activity is detected (if it is not detected, 4448 * it is slow enough). -- FR 4449 * If skb is NULL then we come here again once a tx irq is 4450 * triggered after the last fragment is marked transmitted. 4451 */ 4452 if (tp->cur_tx != dirty_tx && skb) 4453 rtl8169_doorbell(tp); 4454 } 4455 } 4456 4457 static inline int rtl8169_fragmented_frame(u32 status) 4458 { 4459 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4460 } 4461 4462 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4463 { 4464 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4465 4466 if (status == RxProtoTCP || status == RxProtoUDP) 4467 skb->ip_summed = CHECKSUM_UNNECESSARY; 4468 else 4469 skb_checksum_none_assert(skb); 4470 } 4471 4472 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4473 { 4474 struct device *d = tp_to_dev(tp); 4475 int count; 4476 4477 for (count = 0; count < budget; count++, tp->cur_rx++) { 4478 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4479 struct RxDesc *desc = tp->RxDescArray + entry; 4480 struct sk_buff *skb; 4481 const void *rx_buf; 4482 dma_addr_t addr; 4483 u32 status; 4484 4485 status = le32_to_cpu(desc->opts1); 4486 if (status & DescOwn) 4487 break; 4488 4489 /* This barrier is needed to keep us from reading 4490 * any other fields out of the Rx descriptor until 4491 * we know the status of DescOwn 4492 */ 4493 dma_rmb(); 4494 4495 if (unlikely(status & RxRES)) { 4496 if (net_ratelimit()) 4497 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4498 status); 4499 dev->stats.rx_errors++; 4500 if (status & (RxRWT | RxRUNT)) 4501 dev->stats.rx_length_errors++; 4502 if (status & RxCRC) 4503 dev->stats.rx_crc_errors++; 4504 4505 if (!(dev->features & NETIF_F_RXALL)) 4506 goto release_descriptor; 4507 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4508 goto release_descriptor; 4509 } 4510 4511 pkt_size = status & GENMASK(13, 0); 4512 if (likely(!(dev->features & NETIF_F_RXFCS))) 4513 pkt_size -= ETH_FCS_LEN; 4514 4515 /* The driver does not support incoming fragmented frames. 4516 * They are seen as a symptom of over-mtu sized frames. 4517 */ 4518 if (unlikely(rtl8169_fragmented_frame(status))) { 4519 dev->stats.rx_dropped++; 4520 dev->stats.rx_length_errors++; 4521 goto release_descriptor; 4522 } 4523 4524 skb = napi_alloc_skb(&tp->napi, pkt_size); 4525 if (unlikely(!skb)) { 4526 dev->stats.rx_dropped++; 4527 goto release_descriptor; 4528 } 4529 4530 addr = le64_to_cpu(desc->addr); 4531 rx_buf = page_address(tp->Rx_databuff[entry]); 4532 4533 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4534 prefetch(rx_buf); 4535 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4536 skb->tail += pkt_size; 4537 skb->len = pkt_size; 4538 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4539 4540 rtl8169_rx_csum(skb, status); 4541 skb->protocol = eth_type_trans(skb, dev); 4542 4543 rtl8169_rx_vlan_tag(desc, skb); 4544 4545 if (skb->pkt_type == PACKET_MULTICAST) 4546 dev->stats.multicast++; 4547 4548 napi_gro_receive(&tp->napi, skb); 4549 4550 dev_sw_netstats_rx_add(dev, pkt_size); 4551 release_descriptor: 4552 rtl8169_mark_to_asic(desc); 4553 } 4554 4555 return count; 4556 } 4557 4558 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4559 { 4560 struct rtl8169_private *tp = dev_instance; 4561 u32 status = rtl_get_events(tp); 4562 4563 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4564 return IRQ_NONE; 4565 4566 if (unlikely(status & SYSErr)) { 4567 rtl8169_pcierr_interrupt(tp->dev); 4568 goto out; 4569 } 4570 4571 if (status & LinkChg) 4572 phy_mac_interrupt(tp->phydev); 4573 4574 if (unlikely(status & RxFIFOOver && 4575 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4576 netif_stop_queue(tp->dev); 4577 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4578 } 4579 4580 if (napi_schedule_prep(&tp->napi)) { 4581 rtl_irq_disable(tp); 4582 __napi_schedule(&tp->napi); 4583 } 4584 out: 4585 rtl_ack_events(tp, status); 4586 4587 return IRQ_HANDLED; 4588 } 4589 4590 static void rtl_task(struct work_struct *work) 4591 { 4592 struct rtl8169_private *tp = 4593 container_of(work, struct rtl8169_private, wk.work); 4594 4595 rtnl_lock(); 4596 4597 if (!netif_running(tp->dev) || 4598 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4599 goto out_unlock; 4600 4601 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4602 rtl_reset_work(tp); 4603 netif_wake_queue(tp->dev); 4604 } 4605 out_unlock: 4606 rtnl_unlock(); 4607 } 4608 4609 static int rtl8169_poll(struct napi_struct *napi, int budget) 4610 { 4611 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4612 struct net_device *dev = tp->dev; 4613 int work_done; 4614 4615 rtl_tx(dev, tp, budget); 4616 4617 work_done = rtl_rx(dev, tp, budget); 4618 4619 if (work_done < budget && napi_complete_done(napi, work_done)) 4620 rtl_irq_enable(tp); 4621 4622 return work_done; 4623 } 4624 4625 static void r8169_phylink_handler(struct net_device *ndev) 4626 { 4627 struct rtl8169_private *tp = netdev_priv(ndev); 4628 4629 if (netif_carrier_ok(ndev)) { 4630 rtl_link_chg_patch(tp); 4631 pm_request_resume(&tp->pci_dev->dev); 4632 } else { 4633 pm_runtime_idle(&tp->pci_dev->dev); 4634 } 4635 4636 if (net_ratelimit()) 4637 phy_print_status(tp->phydev); 4638 } 4639 4640 static int r8169_phy_connect(struct rtl8169_private *tp) 4641 { 4642 struct phy_device *phydev = tp->phydev; 4643 phy_interface_t phy_mode; 4644 int ret; 4645 4646 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4647 PHY_INTERFACE_MODE_MII; 4648 4649 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4650 phy_mode); 4651 if (ret) 4652 return ret; 4653 4654 if (!tp->supports_gmii) 4655 phy_set_max_speed(phydev, SPEED_100); 4656 4657 phy_attached_info(phydev); 4658 4659 return 0; 4660 } 4661 4662 static void rtl8169_down(struct rtl8169_private *tp) 4663 { 4664 /* Clear all task flags */ 4665 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4666 4667 phy_stop(tp->phydev); 4668 4669 rtl8169_update_counters(tp); 4670 4671 pci_clear_master(tp->pci_dev); 4672 rtl_pci_commit(tp); 4673 4674 rtl8169_cleanup(tp, true); 4675 4676 rtl_prepare_power_down(tp); 4677 } 4678 4679 static void rtl8169_up(struct rtl8169_private *tp) 4680 { 4681 pci_set_master(tp->pci_dev); 4682 phy_init_hw(tp->phydev); 4683 phy_resume(tp->phydev); 4684 rtl8169_init_phy(tp); 4685 napi_enable(&tp->napi); 4686 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4687 rtl_reset_work(tp); 4688 4689 phy_start(tp->phydev); 4690 } 4691 4692 static int rtl8169_close(struct net_device *dev) 4693 { 4694 struct rtl8169_private *tp = netdev_priv(dev); 4695 struct pci_dev *pdev = tp->pci_dev; 4696 4697 pm_runtime_get_sync(&pdev->dev); 4698 4699 netif_stop_queue(dev); 4700 rtl8169_down(tp); 4701 rtl8169_rx_clear(tp); 4702 4703 cancel_work_sync(&tp->wk.work); 4704 4705 free_irq(pci_irq_vector(pdev, 0), tp); 4706 4707 phy_disconnect(tp->phydev); 4708 4709 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4710 tp->RxPhyAddr); 4711 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4712 tp->TxPhyAddr); 4713 tp->TxDescArray = NULL; 4714 tp->RxDescArray = NULL; 4715 4716 pm_runtime_put_sync(&pdev->dev); 4717 4718 return 0; 4719 } 4720 4721 #ifdef CONFIG_NET_POLL_CONTROLLER 4722 static void rtl8169_netpoll(struct net_device *dev) 4723 { 4724 struct rtl8169_private *tp = netdev_priv(dev); 4725 4726 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4727 } 4728 #endif 4729 4730 static int rtl_open(struct net_device *dev) 4731 { 4732 struct rtl8169_private *tp = netdev_priv(dev); 4733 struct pci_dev *pdev = tp->pci_dev; 4734 unsigned long irqflags; 4735 int retval = -ENOMEM; 4736 4737 pm_runtime_get_sync(&pdev->dev); 4738 4739 /* 4740 * Rx and Tx descriptors needs 256 bytes alignment. 4741 * dma_alloc_coherent provides more. 4742 */ 4743 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4744 &tp->TxPhyAddr, GFP_KERNEL); 4745 if (!tp->TxDescArray) 4746 goto out; 4747 4748 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4749 &tp->RxPhyAddr, GFP_KERNEL); 4750 if (!tp->RxDescArray) 4751 goto err_free_tx_0; 4752 4753 retval = rtl8169_init_ring(tp); 4754 if (retval < 0) 4755 goto err_free_rx_1; 4756 4757 rtl_request_firmware(tp); 4758 4759 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4760 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt, 4761 irqflags, dev->name, tp); 4762 if (retval < 0) 4763 goto err_release_fw_2; 4764 4765 retval = r8169_phy_connect(tp); 4766 if (retval) 4767 goto err_free_irq; 4768 4769 rtl8169_up(tp); 4770 rtl8169_init_counter_offsets(tp); 4771 netif_start_queue(dev); 4772 out: 4773 pm_runtime_put_sync(&pdev->dev); 4774 4775 return retval; 4776 4777 err_free_irq: 4778 free_irq(pci_irq_vector(pdev, 0), tp); 4779 err_release_fw_2: 4780 rtl_release_firmware(tp); 4781 rtl8169_rx_clear(tp); 4782 err_free_rx_1: 4783 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4784 tp->RxPhyAddr); 4785 tp->RxDescArray = NULL; 4786 err_free_tx_0: 4787 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4788 tp->TxPhyAddr); 4789 tp->TxDescArray = NULL; 4790 goto out; 4791 } 4792 4793 static void 4794 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4795 { 4796 struct rtl8169_private *tp = netdev_priv(dev); 4797 struct pci_dev *pdev = tp->pci_dev; 4798 struct rtl8169_counters *counters = tp->counters; 4799 4800 pm_runtime_get_noresume(&pdev->dev); 4801 4802 netdev_stats_to_stats64(stats, &dev->stats); 4803 dev_fetch_sw_netstats(stats, dev->tstats); 4804 4805 /* 4806 * Fetch additional counter values missing in stats collected by driver 4807 * from tally counters. 4808 */ 4809 if (pm_runtime_active(&pdev->dev)) 4810 rtl8169_update_counters(tp); 4811 4812 /* 4813 * Subtract values fetched during initalization. 4814 * See rtl8169_init_counter_offsets for a description why we do that. 4815 */ 4816 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4817 le64_to_cpu(tp->tc_offset.tx_errors); 4818 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4819 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4820 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4821 le16_to_cpu(tp->tc_offset.tx_aborted); 4822 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4823 le16_to_cpu(tp->tc_offset.rx_missed); 4824 4825 pm_runtime_put_noidle(&pdev->dev); 4826 } 4827 4828 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4829 { 4830 netif_device_detach(tp->dev); 4831 4832 if (netif_running(tp->dev)) 4833 rtl8169_down(tp); 4834 } 4835 4836 #ifdef CONFIG_PM 4837 4838 static int rtl8169_runtime_resume(struct device *dev) 4839 { 4840 struct rtl8169_private *tp = dev_get_drvdata(dev); 4841 4842 rtl_rar_set(tp, tp->dev->dev_addr); 4843 __rtl8169_set_wol(tp, tp->saved_wolopts); 4844 4845 if (tp->TxDescArray) 4846 rtl8169_up(tp); 4847 4848 netif_device_attach(tp->dev); 4849 4850 return 0; 4851 } 4852 4853 static int __maybe_unused rtl8169_suspend(struct device *device) 4854 { 4855 struct rtl8169_private *tp = dev_get_drvdata(device); 4856 4857 rtnl_lock(); 4858 rtl8169_net_suspend(tp); 4859 if (!device_may_wakeup(tp_to_dev(tp))) 4860 clk_disable_unprepare(tp->clk); 4861 rtnl_unlock(); 4862 4863 return 0; 4864 } 4865 4866 static int __maybe_unused rtl8169_resume(struct device *device) 4867 { 4868 struct rtl8169_private *tp = dev_get_drvdata(device); 4869 4870 if (!device_may_wakeup(tp_to_dev(tp))) 4871 clk_prepare_enable(tp->clk); 4872 4873 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4874 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4875 rtl_init_rxcfg(tp); 4876 4877 return rtl8169_runtime_resume(device); 4878 } 4879 4880 static int rtl8169_runtime_suspend(struct device *device) 4881 { 4882 struct rtl8169_private *tp = dev_get_drvdata(device); 4883 4884 if (!tp->TxDescArray) { 4885 netif_device_detach(tp->dev); 4886 return 0; 4887 } 4888 4889 rtnl_lock(); 4890 __rtl8169_set_wol(tp, WAKE_PHY); 4891 rtl8169_net_suspend(tp); 4892 rtnl_unlock(); 4893 4894 return 0; 4895 } 4896 4897 static int rtl8169_runtime_idle(struct device *device) 4898 { 4899 struct rtl8169_private *tp = dev_get_drvdata(device); 4900 4901 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4902 pm_schedule_suspend(device, 10000); 4903 4904 return -EBUSY; 4905 } 4906 4907 static const struct dev_pm_ops rtl8169_pm_ops = { 4908 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4909 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4910 rtl8169_runtime_idle) 4911 }; 4912 4913 #endif /* CONFIG_PM */ 4914 4915 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4916 { 4917 /* WoL fails with 8168b when the receiver is disabled. */ 4918 switch (tp->mac_version) { 4919 case RTL_GIGA_MAC_VER_11: 4920 case RTL_GIGA_MAC_VER_12: 4921 case RTL_GIGA_MAC_VER_17: 4922 pci_clear_master(tp->pci_dev); 4923 4924 RTL_W8(tp, ChipCmd, CmdRxEnb); 4925 rtl_pci_commit(tp); 4926 break; 4927 default: 4928 break; 4929 } 4930 } 4931 4932 static void rtl_shutdown(struct pci_dev *pdev) 4933 { 4934 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4935 4936 rtnl_lock(); 4937 rtl8169_net_suspend(tp); 4938 rtnl_unlock(); 4939 4940 /* Restore original MAC address */ 4941 rtl_rar_set(tp, tp->dev->perm_addr); 4942 4943 if (system_state == SYSTEM_POWER_OFF) { 4944 if (tp->saved_wolopts) 4945 rtl_wol_shutdown_quirk(tp); 4946 4947 pci_wake_from_d3(pdev, tp->saved_wolopts); 4948 pci_set_power_state(pdev, PCI_D3hot); 4949 } 4950 } 4951 4952 static void rtl_remove_one(struct pci_dev *pdev) 4953 { 4954 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4955 4956 if (pci_dev_run_wake(pdev)) 4957 pm_runtime_get_noresume(&pdev->dev); 4958 4959 unregister_netdev(tp->dev); 4960 4961 if (tp->dash_type != RTL_DASH_NONE) 4962 rtl8168_driver_stop(tp); 4963 4964 rtl_release_firmware(tp); 4965 4966 /* restore original MAC address */ 4967 rtl_rar_set(tp, tp->dev->perm_addr); 4968 } 4969 4970 static const struct net_device_ops rtl_netdev_ops = { 4971 .ndo_open = rtl_open, 4972 .ndo_stop = rtl8169_close, 4973 .ndo_get_stats64 = rtl8169_get_stats64, 4974 .ndo_start_xmit = rtl8169_start_xmit, 4975 .ndo_features_check = rtl8169_features_check, 4976 .ndo_tx_timeout = rtl8169_tx_timeout, 4977 .ndo_validate_addr = eth_validate_addr, 4978 .ndo_change_mtu = rtl8169_change_mtu, 4979 .ndo_fix_features = rtl8169_fix_features, 4980 .ndo_set_features = rtl8169_set_features, 4981 .ndo_set_mac_address = rtl_set_mac_address, 4982 .ndo_do_ioctl = phy_do_ioctl_running, 4983 .ndo_set_rx_mode = rtl_set_rx_mode, 4984 #ifdef CONFIG_NET_POLL_CONTROLLER 4985 .ndo_poll_controller = rtl8169_netpoll, 4986 #endif 4987 4988 }; 4989 4990 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4991 { 4992 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4993 4994 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4995 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4996 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4997 /* special workaround needed */ 4998 tp->irq_mask |= RxFIFOOver; 4999 else 5000 tp->irq_mask |= RxOverflow; 5001 } 5002 5003 static int rtl_alloc_irq(struct rtl8169_private *tp) 5004 { 5005 unsigned int flags; 5006 5007 switch (tp->mac_version) { 5008 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5009 rtl_unlock_config_regs(tp); 5010 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5011 rtl_lock_config_regs(tp); 5012 fallthrough; 5013 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5014 flags = PCI_IRQ_LEGACY; 5015 break; 5016 default: 5017 flags = PCI_IRQ_ALL_TYPES; 5018 break; 5019 } 5020 5021 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5022 } 5023 5024 static void rtl_read_mac_address(struct rtl8169_private *tp, 5025 u8 mac_addr[ETH_ALEN]) 5026 { 5027 /* Get MAC address */ 5028 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5029 u32 value; 5030 5031 value = rtl_eri_read(tp, 0xe0); 5032 put_unaligned_le32(value, mac_addr); 5033 value = rtl_eri_read(tp, 0xe4); 5034 put_unaligned_le16(value, mac_addr + 4); 5035 } else if (rtl_is_8125(tp)) { 5036 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5037 } 5038 } 5039 5040 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5041 { 5042 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5043 } 5044 5045 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5046 { 5047 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5048 } 5049 5050 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5051 { 5052 struct rtl8169_private *tp = mii_bus->priv; 5053 5054 if (phyaddr > 0) 5055 return -ENODEV; 5056 5057 return rtl_readphy(tp, phyreg); 5058 } 5059 5060 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5061 int phyreg, u16 val) 5062 { 5063 struct rtl8169_private *tp = mii_bus->priv; 5064 5065 if (phyaddr > 0) 5066 return -ENODEV; 5067 5068 rtl_writephy(tp, phyreg, val); 5069 5070 return 0; 5071 } 5072 5073 static int r8169_mdio_register(struct rtl8169_private *tp) 5074 { 5075 struct pci_dev *pdev = tp->pci_dev; 5076 struct mii_bus *new_bus; 5077 int ret; 5078 5079 new_bus = devm_mdiobus_alloc(&pdev->dev); 5080 if (!new_bus) 5081 return -ENOMEM; 5082 5083 new_bus->name = "r8169"; 5084 new_bus->priv = tp; 5085 new_bus->parent = &pdev->dev; 5086 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5087 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5088 5089 new_bus->read = r8169_mdio_read_reg; 5090 new_bus->write = r8169_mdio_write_reg; 5091 5092 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5093 if (ret) 5094 return ret; 5095 5096 tp->phydev = mdiobus_get_phy(new_bus, 0); 5097 if (!tp->phydev) { 5098 return -ENODEV; 5099 } else if (!tp->phydev->drv) { 5100 /* Most chip versions fail with the genphy driver. 5101 * Therefore ensure that the dedicated PHY driver is loaded. 5102 */ 5103 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5104 tp->phydev->phy_id); 5105 return -EUNATCH; 5106 } 5107 5108 tp->phydev->mac_managed_pm = 1; 5109 5110 phy_support_asym_pause(tp->phydev); 5111 5112 /* PHY will be woken up in rtl_open() */ 5113 phy_suspend(tp->phydev); 5114 5115 return 0; 5116 } 5117 5118 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5119 { 5120 rtl_enable_rxdvgate(tp); 5121 5122 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5123 msleep(1); 5124 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5125 5126 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5127 r8168g_wait_ll_share_fifo_ready(tp); 5128 5129 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5130 r8168g_wait_ll_share_fifo_ready(tp); 5131 } 5132 5133 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5134 { 5135 rtl_enable_rxdvgate(tp); 5136 5137 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5138 msleep(1); 5139 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5140 5141 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5142 r8168g_wait_ll_share_fifo_ready(tp); 5143 5144 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5145 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5146 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5147 r8168g_wait_ll_share_fifo_ready(tp); 5148 } 5149 5150 static void rtl_hw_initialize(struct rtl8169_private *tp) 5151 { 5152 switch (tp->mac_version) { 5153 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 5154 rtl8168ep_stop_cmac(tp); 5155 fallthrough; 5156 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5157 rtl_hw_init_8168g(tp); 5158 break; 5159 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5160 rtl_hw_init_8125(tp); 5161 break; 5162 default: 5163 break; 5164 } 5165 } 5166 5167 static int rtl_jumbo_max(struct rtl8169_private *tp) 5168 { 5169 /* Non-GBit versions don't support jumbo frames */ 5170 if (!tp->supports_gmii) 5171 return 0; 5172 5173 switch (tp->mac_version) { 5174 /* RTL8169 */ 5175 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5176 return JUMBO_7K; 5177 /* RTL8168b */ 5178 case RTL_GIGA_MAC_VER_11: 5179 case RTL_GIGA_MAC_VER_12: 5180 case RTL_GIGA_MAC_VER_17: 5181 return JUMBO_4K; 5182 /* RTL8168c */ 5183 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5184 return JUMBO_6K; 5185 default: 5186 return JUMBO_9K; 5187 } 5188 } 5189 5190 static void rtl_disable_clk(void *data) 5191 { 5192 clk_disable_unprepare(data); 5193 } 5194 5195 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5196 { 5197 struct device *d = tp_to_dev(tp); 5198 struct clk *clk; 5199 int rc; 5200 5201 clk = devm_clk_get(d, "ether_clk"); 5202 if (IS_ERR(clk)) { 5203 rc = PTR_ERR(clk); 5204 if (rc == -ENOENT) 5205 /* clk-core allows NULL (for suspend / resume) */ 5206 rc = 0; 5207 else 5208 dev_err_probe(d, rc, "failed to get clk\n"); 5209 } else { 5210 tp->clk = clk; 5211 rc = clk_prepare_enable(clk); 5212 if (rc) 5213 dev_err(d, "failed to enable clk: %d\n", rc); 5214 else 5215 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5216 } 5217 5218 return rc; 5219 } 5220 5221 static void rtl_init_mac_address(struct rtl8169_private *tp) 5222 { 5223 struct net_device *dev = tp->dev; 5224 u8 *mac_addr = dev->dev_addr; 5225 int rc; 5226 5227 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5228 if (!rc) 5229 goto done; 5230 5231 rtl_read_mac_address(tp, mac_addr); 5232 if (is_valid_ether_addr(mac_addr)) 5233 goto done; 5234 5235 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5236 if (is_valid_ether_addr(mac_addr)) 5237 goto done; 5238 5239 eth_hw_addr_random(dev); 5240 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5241 done: 5242 rtl_rar_set(tp, mac_addr); 5243 } 5244 5245 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5246 { 5247 struct rtl8169_private *tp; 5248 int jumbo_max, region, rc; 5249 enum mac_version chipset; 5250 struct net_device *dev; 5251 u16 xid; 5252 5253 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5254 if (!dev) 5255 return -ENOMEM; 5256 5257 SET_NETDEV_DEV(dev, &pdev->dev); 5258 dev->netdev_ops = &rtl_netdev_ops; 5259 tp = netdev_priv(dev); 5260 tp->dev = dev; 5261 tp->pci_dev = pdev; 5262 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5263 tp->eee_adv = -1; 5264 tp->ocp_base = OCP_STD_PHY_BASE; 5265 5266 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5267 struct pcpu_sw_netstats); 5268 if (!dev->tstats) 5269 return -ENOMEM; 5270 5271 /* Get the *optional* external "ether_clk" used on some boards */ 5272 rc = rtl_get_ether_clk(tp); 5273 if (rc) 5274 return rc; 5275 5276 /* Disable ASPM completely as that cause random device stop working 5277 * problems as well as full system hangs for some PCIe devices users. 5278 */ 5279 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5280 PCIE_LINK_STATE_L1); 5281 tp->aspm_manageable = !rc; 5282 5283 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5284 rc = pcim_enable_device(pdev); 5285 if (rc < 0) { 5286 dev_err(&pdev->dev, "enable failure\n"); 5287 return rc; 5288 } 5289 5290 if (pcim_set_mwi(pdev) < 0) 5291 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5292 5293 /* use first MMIO region */ 5294 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5295 if (region < 0) { 5296 dev_err(&pdev->dev, "no MMIO resource found\n"); 5297 return -ENODEV; 5298 } 5299 5300 /* check for weird/broken PCI region reporting */ 5301 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5302 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5303 return -ENODEV; 5304 } 5305 5306 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5307 if (rc < 0) { 5308 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5309 return rc; 5310 } 5311 5312 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5313 5314 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5315 5316 /* Identify chip attached to board */ 5317 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5318 if (chipset == RTL_GIGA_MAC_NONE) { 5319 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5320 return -ENODEV; 5321 } 5322 5323 tp->mac_version = chipset; 5324 5325 tp->dash_type = rtl_check_dash(tp); 5326 5327 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5328 5329 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5330 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5331 dev->features |= NETIF_F_HIGHDMA; 5332 5333 rtl_init_rxcfg(tp); 5334 5335 rtl8169_irq_mask_and_ack(tp); 5336 5337 rtl_hw_initialize(tp); 5338 5339 rtl_hw_reset(tp); 5340 5341 rc = rtl_alloc_irq(tp); 5342 if (rc < 0) { 5343 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5344 return rc; 5345 } 5346 5347 INIT_WORK(&tp->wk.work, rtl_task); 5348 5349 rtl_init_mac_address(tp); 5350 5351 dev->ethtool_ops = &rtl8169_ethtool_ops; 5352 5353 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5354 5355 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5356 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5357 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5358 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5359 5360 /* 5361 * Pretend we are using VLANs; This bypasses a nasty bug where 5362 * Interrupts stop flowing on high load on 8110SCd controllers. 5363 */ 5364 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5365 /* Disallow toggling */ 5366 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5367 5368 if (rtl_chip_supports_csum_v2(tp)) 5369 dev->hw_features |= NETIF_F_IPV6_CSUM; 5370 5371 dev->features |= dev->hw_features; 5372 5373 /* There has been a number of reports that using SG/TSO results in 5374 * tx timeouts. However for a lot of people SG/TSO works fine. 5375 * Therefore disable both features by default, but allow users to 5376 * enable them. Use at own risk! 5377 */ 5378 if (rtl_chip_supports_csum_v2(tp)) { 5379 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5380 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5381 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5382 } else { 5383 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5384 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5385 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5386 } 5387 5388 dev->hw_features |= NETIF_F_RXALL; 5389 dev->hw_features |= NETIF_F_RXFCS; 5390 5391 /* configure chip for default features */ 5392 rtl8169_set_features(dev, dev->features); 5393 5394 rtl_set_d3_pll_down(tp, true); 5395 5396 jumbo_max = rtl_jumbo_max(tp); 5397 if (jumbo_max) 5398 dev->max_mtu = jumbo_max; 5399 5400 rtl_set_irq_mask(tp); 5401 5402 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5403 5404 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5405 &tp->counters_phys_addr, 5406 GFP_KERNEL); 5407 if (!tp->counters) 5408 return -ENOMEM; 5409 5410 pci_set_drvdata(pdev, tp); 5411 5412 rc = r8169_mdio_register(tp); 5413 if (rc) 5414 return rc; 5415 5416 rc = register_netdev(dev); 5417 if (rc) 5418 return rc; 5419 5420 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5421 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5422 pci_irq_vector(pdev, 0)); 5423 5424 if (jumbo_max) 5425 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5426 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5427 "ok" : "ko"); 5428 5429 if (tp->dash_type != RTL_DASH_NONE) { 5430 netdev_info(dev, "DASH enabled\n"); 5431 rtl8168_driver_start(tp); 5432 } 5433 5434 if (pci_dev_run_wake(pdev)) 5435 pm_runtime_put_sync(&pdev->dev); 5436 5437 return 0; 5438 } 5439 5440 static struct pci_driver rtl8169_pci_driver = { 5441 .name = KBUILD_MODNAME, 5442 .id_table = rtl8169_pci_tbl, 5443 .probe = rtl_init_one, 5444 .remove = rtl_remove_one, 5445 .shutdown = rtl_shutdown, 5446 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5447 }; 5448 5449 module_pci_driver(rtl8169_pci_driver); 5450