1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define MODULENAME "r8169" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 56 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 59 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 60 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define OCP_STD_PHY_BASE 0xa400 77 78 #define RTL_CFG_NO_GBIT 1 79 80 /* write/read MMIO register */ 81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 87 88 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 92 93 static const struct { 94 const char *name; 95 const char *fw_name; 96 } rtl_chip_infos[] = { 97 /* PCI devices. */ 98 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 99 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 100 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 101 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 102 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 103 /* PCI-E devices. */ 104 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 106 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 107 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 108 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 111 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 112 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 113 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 114 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 115 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 119 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 121 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 122 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 123 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 125 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 127 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 128 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 129 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 130 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 131 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 132 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 133 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 134 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 135 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 136 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 137 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 138 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 139 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 140 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 141 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 142 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 143 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 144 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 145 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 148 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 149 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 150 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 151 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 152 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 153 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 154 }; 155 156 static const struct pci_device_id rtl8169_pci_tbl[] = { 157 { PCI_VDEVICE(REALTEK, 0x2502) }, 158 { PCI_VDEVICE(REALTEK, 0x2600) }, 159 { PCI_VDEVICE(REALTEK, 0x8129) }, 160 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 161 { PCI_VDEVICE(REALTEK, 0x8161) }, 162 { PCI_VDEVICE(REALTEK, 0x8167) }, 163 { PCI_VDEVICE(REALTEK, 0x8168) }, 164 { PCI_VDEVICE(NCUBE, 0x8168) }, 165 { PCI_VDEVICE(REALTEK, 0x8169) }, 166 { PCI_VENDOR_ID_DLINK, 0x4300, 167 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 168 { PCI_VDEVICE(DLINK, 0x4300) }, 169 { PCI_VDEVICE(DLINK, 0x4302) }, 170 { PCI_VDEVICE(AT, 0xc107) }, 171 { PCI_VDEVICE(USR, 0x0116) }, 172 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 173 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 174 { PCI_VDEVICE(REALTEK, 0x8125) }, 175 { PCI_VDEVICE(REALTEK, 0x3000) }, 176 {} 177 }; 178 179 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 180 181 enum rtl_registers { 182 MAC0 = 0, /* Ethernet hardware address. */ 183 MAC4 = 4, 184 MAR0 = 8, /* Multicast filter. */ 185 CounterAddrLow = 0x10, 186 CounterAddrHigh = 0x14, 187 TxDescStartAddrLow = 0x20, 188 TxDescStartAddrHigh = 0x24, 189 TxHDescStartAddrLow = 0x28, 190 TxHDescStartAddrHigh = 0x2c, 191 FLASH = 0x30, 192 ERSR = 0x36, 193 ChipCmd = 0x37, 194 TxPoll = 0x38, 195 IntrMask = 0x3c, 196 IntrStatus = 0x3e, 197 198 TxConfig = 0x40, 199 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 200 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 201 202 RxConfig = 0x44, 203 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 204 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 205 #define RXCFG_FIFO_SHIFT 13 206 /* No threshold before first PCI xfer */ 207 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 208 #define RX_EARLY_OFF (1 << 11) 209 #define RXCFG_DMA_SHIFT 8 210 /* Unlimited maximum PCI burst. */ 211 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 212 213 Cfg9346 = 0x50, 214 Config0 = 0x51, 215 Config1 = 0x52, 216 Config2 = 0x53, 217 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 218 219 Config3 = 0x54, 220 Config4 = 0x55, 221 Config5 = 0x56, 222 PHYAR = 0x60, 223 PHYstatus = 0x6c, 224 RxMaxSize = 0xda, 225 CPlusCmd = 0xe0, 226 IntrMitigate = 0xe2, 227 228 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 229 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 230 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 231 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 232 233 #define RTL_COALESCE_T_MAX 0x0fU 234 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 235 236 RxDescAddrLow = 0xe4, 237 RxDescAddrHigh = 0xe8, 238 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 239 240 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 241 242 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 243 244 #define TxPacketMax (8064 >> 7) 245 #define EarlySize 0x27 246 247 FuncEvent = 0xf0, 248 FuncEventMask = 0xf4, 249 FuncPresetState = 0xf8, 250 IBCR0 = 0xf8, 251 IBCR2 = 0xf9, 252 IBIMR0 = 0xfa, 253 IBISR0 = 0xfb, 254 FuncForceEvent = 0xfc, 255 }; 256 257 enum rtl8168_8101_registers { 258 CSIDR = 0x64, 259 CSIAR = 0x68, 260 #define CSIAR_FLAG 0x80000000 261 #define CSIAR_WRITE_CMD 0x80000000 262 #define CSIAR_BYTE_ENABLE 0x0000f000 263 #define CSIAR_ADDR_MASK 0x00000fff 264 PMCH = 0x6f, 265 #define D3COLD_NO_PLL_DOWN BIT(7) 266 #define D3HOT_NO_PLL_DOWN BIT(6) 267 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 268 EPHYAR = 0x80, 269 #define EPHYAR_FLAG 0x80000000 270 #define EPHYAR_WRITE_CMD 0x80000000 271 #define EPHYAR_REG_MASK 0x1f 272 #define EPHYAR_REG_SHIFT 16 273 #define EPHYAR_DATA_MASK 0xffff 274 DLLPR = 0xd0, 275 #define PFM_EN (1 << 6) 276 #define TX_10M_PS_EN (1 << 7) 277 DBG_REG = 0xd1, 278 #define FIX_NAK_1 (1 << 4) 279 #define FIX_NAK_2 (1 << 3) 280 TWSI = 0xd2, 281 MCU = 0xd3, 282 #define NOW_IS_OOB (1 << 7) 283 #define TX_EMPTY (1 << 5) 284 #define RX_EMPTY (1 << 4) 285 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 286 #define EN_NDP (1 << 3) 287 #define EN_OOB_RESET (1 << 2) 288 #define LINK_LIST_RDY (1 << 1) 289 EFUSEAR = 0xdc, 290 #define EFUSEAR_FLAG 0x80000000 291 #define EFUSEAR_WRITE_CMD 0x80000000 292 #define EFUSEAR_READ_CMD 0x00000000 293 #define EFUSEAR_REG_MASK 0x03ff 294 #define EFUSEAR_REG_SHIFT 8 295 #define EFUSEAR_DATA_MASK 0xff 296 MISC_1 = 0xf2, 297 #define PFM_D3COLD_EN (1 << 6) 298 }; 299 300 enum rtl8168_registers { 301 LED_FREQ = 0x1a, 302 EEE_LED = 0x1b, 303 ERIDR = 0x70, 304 ERIAR = 0x74, 305 #define ERIAR_FLAG 0x80000000 306 #define ERIAR_WRITE_CMD 0x80000000 307 #define ERIAR_READ_CMD 0x00000000 308 #define ERIAR_ADDR_BYTE_ALIGN 4 309 #define ERIAR_TYPE_SHIFT 16 310 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 312 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 313 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 314 #define ERIAR_MASK_SHIFT 12 315 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 317 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 318 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 319 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 320 EPHY_RXER_NUM = 0x7c, 321 OCPDR = 0xb0, /* OCP GPHY access */ 322 #define OCPDR_WRITE_CMD 0x80000000 323 #define OCPDR_READ_CMD 0x00000000 324 #define OCPDR_REG_MASK 0x7f 325 #define OCPDR_GPHY_REG_SHIFT 16 326 #define OCPDR_DATA_MASK 0xffff 327 OCPAR = 0xb4, 328 #define OCPAR_FLAG 0x80000000 329 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 330 #define OCPAR_GPHY_READ_CMD 0x0000f060 331 GPHY_OCP = 0xb8, 332 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 333 MISC = 0xf0, /* 8168e only. */ 334 #define TXPLA_RST (1 << 29) 335 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 336 #define PWM_EN (1 << 22) 337 #define RXDV_GATED_EN (1 << 19) 338 #define EARLY_TALLY_EN (1 << 16) 339 }; 340 341 enum rtl8125_registers { 342 IntrMask_8125 = 0x38, 343 IntrStatus_8125 = 0x3c, 344 TxPoll_8125 = 0x90, 345 MAC0_BKP = 0x19e0, 346 EEE_TXIDLE_TIMER_8125 = 0x6048, 347 }; 348 349 #define RX_VLAN_INNER_8125 BIT(22) 350 #define RX_VLAN_OUTER_8125 BIT(23) 351 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 352 353 #define RX_FETCH_DFLT_8125 (8 << 27) 354 355 enum rtl_register_content { 356 /* InterruptStatusBits */ 357 SYSErr = 0x8000, 358 PCSTimeout = 0x4000, 359 SWInt = 0x0100, 360 TxDescUnavail = 0x0080, 361 RxFIFOOver = 0x0040, 362 LinkChg = 0x0020, 363 RxOverflow = 0x0010, 364 TxErr = 0x0008, 365 TxOK = 0x0004, 366 RxErr = 0x0002, 367 RxOK = 0x0001, 368 369 /* RxStatusDesc */ 370 RxRWT = (1 << 22), 371 RxRES = (1 << 21), 372 RxRUNT = (1 << 20), 373 RxCRC = (1 << 19), 374 375 /* ChipCmdBits */ 376 StopReq = 0x80, 377 CmdReset = 0x10, 378 CmdRxEnb = 0x08, 379 CmdTxEnb = 0x04, 380 RxBufEmpty = 0x01, 381 382 /* TXPoll register p.5 */ 383 HPQ = 0x80, /* Poll cmd on the high prio queue */ 384 NPQ = 0x40, /* Poll cmd on the low prio queue */ 385 FSWInt = 0x01, /* Forced software interrupt */ 386 387 /* Cfg9346Bits */ 388 Cfg9346_Lock = 0x00, 389 Cfg9346_Unlock = 0xc0, 390 391 /* rx_mode_bits */ 392 AcceptErr = 0x20, 393 AcceptRunt = 0x10, 394 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 395 AcceptBroadcast = 0x08, 396 AcceptMulticast = 0x04, 397 AcceptMyPhys = 0x02, 398 AcceptAllPhys = 0x01, 399 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 400 #define RX_CONFIG_ACCEPT_MASK 0x3f 401 402 /* TxConfigBits */ 403 TxInterFrameGapShift = 24, 404 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 405 406 /* Config1 register p.24 */ 407 LEDS1 = (1 << 7), 408 LEDS0 = (1 << 6), 409 Speed_down = (1 << 4), 410 MEMMAP = (1 << 3), 411 IOMAP = (1 << 2), 412 VPD = (1 << 1), 413 PMEnable = (1 << 0), /* Power Management Enable */ 414 415 /* Config2 register p. 25 */ 416 ClkReqEn = (1 << 7), /* Clock Request Enable */ 417 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 418 PCI_Clock_66MHz = 0x01, 419 PCI_Clock_33MHz = 0x00, 420 421 /* Config3 register p.25 */ 422 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 423 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 424 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 425 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 426 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 427 428 /* Config4 register */ 429 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 430 431 /* Config5 register p.27 */ 432 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 433 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 434 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 435 Spi_en = (1 << 3), 436 LanWake = (1 << 1), /* LanWake enable/disable */ 437 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 438 ASPM_en = (1 << 0), /* ASPM enable */ 439 440 /* CPlusCmd p.31 */ 441 EnableBist = (1 << 15), // 8168 8101 442 Mac_dbgo_oe = (1 << 14), // 8168 8101 443 EnAnaPLL = (1 << 14), // 8169 444 Normal_mode = (1 << 13), // unused 445 Force_half_dup = (1 << 12), // 8168 8101 446 Force_rxflow_en = (1 << 11), // 8168 8101 447 Force_txflow_en = (1 << 10), // 8168 8101 448 Cxpl_dbg_sel = (1 << 9), // 8168 8101 449 ASF = (1 << 8), // 8168 8101 450 PktCntrDisable = (1 << 7), // 8168 8101 451 Mac_dbgo_sel = 0x001c, // 8168 452 RxVlan = (1 << 6), 453 RxChkSum = (1 << 5), 454 PCIDAC = (1 << 4), 455 PCIMulRW = (1 << 3), 456 #define INTT_MASK GENMASK(1, 0) 457 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 458 459 /* rtl8169_PHYstatus */ 460 TBI_Enable = 0x80, 461 TxFlowCtrl = 0x40, 462 RxFlowCtrl = 0x20, 463 _1000bpsF = 0x10, 464 _100bps = 0x08, 465 _10bps = 0x04, 466 LinkStatus = 0x02, 467 FullDup = 0x01, 468 469 /* ResetCounterCommand */ 470 CounterReset = 0x1, 471 472 /* DumpCounterCommand */ 473 CounterDump = 0x8, 474 475 /* magic enable v2 */ 476 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 477 }; 478 479 enum rtl_desc_bit { 480 /* First doubleword. */ 481 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 482 RingEnd = (1 << 30), /* End of descriptor ring */ 483 FirstFrag = (1 << 29), /* First segment of a packet */ 484 LastFrag = (1 << 28), /* Final segment of a packet */ 485 }; 486 487 /* Generic case. */ 488 enum rtl_tx_desc_bit { 489 /* First doubleword. */ 490 TD_LSO = (1 << 27), /* Large Send Offload */ 491 #define TD_MSS_MAX 0x07ffu /* MSS value */ 492 493 /* Second doubleword. */ 494 TxVlanTag = (1 << 17), /* Add VLAN tag */ 495 }; 496 497 /* 8169, 8168b and 810x except 8102e. */ 498 enum rtl_tx_desc_bit_0 { 499 /* First doubleword. */ 500 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 501 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 502 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 503 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 504 }; 505 506 /* 8102e, 8168c and beyond. */ 507 enum rtl_tx_desc_bit_1 { 508 /* First doubleword. */ 509 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 510 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 511 #define GTTCPHO_SHIFT 18 512 #define GTTCPHO_MAX 0x7f 513 514 /* Second doubleword. */ 515 #define TCPHO_SHIFT 18 516 #define TCPHO_MAX 0x3ff 517 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 518 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 519 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 520 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 521 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 522 }; 523 524 enum rtl_rx_desc_bit { 525 /* Rx private */ 526 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 527 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 528 529 #define RxProtoUDP (PID1) 530 #define RxProtoTCP (PID0) 531 #define RxProtoIP (PID1 | PID0) 532 #define RxProtoMask RxProtoIP 533 534 IPFail = (1 << 16), /* IP checksum failed */ 535 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 536 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 537 538 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 539 540 RxVlanTag = (1 << 16), /* VLAN tag available */ 541 }; 542 543 #define RTL_GSO_MAX_SIZE_V1 32000 544 #define RTL_GSO_MAX_SEGS_V1 24 545 #define RTL_GSO_MAX_SIZE_V2 64000 546 #define RTL_GSO_MAX_SEGS_V2 64 547 548 struct TxDesc { 549 __le32 opts1; 550 __le32 opts2; 551 __le64 addr; 552 }; 553 554 struct RxDesc { 555 __le32 opts1; 556 __le32 opts2; 557 __le64 addr; 558 }; 559 560 struct ring_info { 561 struct sk_buff *skb; 562 u32 len; 563 }; 564 565 struct rtl8169_counters { 566 __le64 tx_packets; 567 __le64 rx_packets; 568 __le64 tx_errors; 569 __le32 rx_errors; 570 __le16 rx_missed; 571 __le16 align_errors; 572 __le32 tx_one_collision; 573 __le32 tx_multi_collision; 574 __le64 rx_unicast; 575 __le64 rx_broadcast; 576 __le32 rx_multicast; 577 __le16 tx_aborted; 578 __le16 tx_underun; 579 }; 580 581 struct rtl8169_tc_offsets { 582 bool inited; 583 __le64 tx_errors; 584 __le32 tx_multi_collision; 585 __le16 tx_aborted; 586 __le16 rx_missed; 587 }; 588 589 enum rtl_flag { 590 RTL_FLAG_TASK_ENABLED = 0, 591 RTL_FLAG_TASK_RESET_PENDING, 592 RTL_FLAG_MAX 593 }; 594 595 enum rtl_dash_type { 596 RTL_DASH_NONE, 597 RTL_DASH_DP, 598 RTL_DASH_EP, 599 }; 600 601 struct rtl8169_private { 602 void __iomem *mmio_addr; /* memory map physical address */ 603 struct pci_dev *pci_dev; 604 struct net_device *dev; 605 struct phy_device *phydev; 606 struct napi_struct napi; 607 enum mac_version mac_version; 608 enum rtl_dash_type dash_type; 609 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 610 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 611 u32 dirty_tx; 612 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 613 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 614 dma_addr_t TxPhyAddr; 615 dma_addr_t RxPhyAddr; 616 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 617 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 618 u16 cp_cmd; 619 u32 irq_mask; 620 struct clk *clk; 621 622 struct { 623 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 624 struct work_struct work; 625 } wk; 626 627 unsigned supports_gmii:1; 628 unsigned aspm_manageable:1; 629 dma_addr_t counters_phys_addr; 630 struct rtl8169_counters *counters; 631 struct rtl8169_tc_offsets tc_offset; 632 u32 saved_wolopts; 633 int eee_adv; 634 635 const char *fw_name; 636 struct rtl_fw *rtl_fw; 637 638 u32 ocp_base; 639 }; 640 641 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 642 643 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 644 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 645 MODULE_SOFTDEP("pre: realtek"); 646 MODULE_LICENSE("GPL"); 647 MODULE_FIRMWARE(FIRMWARE_8168D_1); 648 MODULE_FIRMWARE(FIRMWARE_8168D_2); 649 MODULE_FIRMWARE(FIRMWARE_8168E_1); 650 MODULE_FIRMWARE(FIRMWARE_8168E_2); 651 MODULE_FIRMWARE(FIRMWARE_8168E_3); 652 MODULE_FIRMWARE(FIRMWARE_8105E_1); 653 MODULE_FIRMWARE(FIRMWARE_8168F_1); 654 MODULE_FIRMWARE(FIRMWARE_8168F_2); 655 MODULE_FIRMWARE(FIRMWARE_8402_1); 656 MODULE_FIRMWARE(FIRMWARE_8411_1); 657 MODULE_FIRMWARE(FIRMWARE_8411_2); 658 MODULE_FIRMWARE(FIRMWARE_8106E_1); 659 MODULE_FIRMWARE(FIRMWARE_8106E_2); 660 MODULE_FIRMWARE(FIRMWARE_8168G_2); 661 MODULE_FIRMWARE(FIRMWARE_8168G_3); 662 MODULE_FIRMWARE(FIRMWARE_8168H_1); 663 MODULE_FIRMWARE(FIRMWARE_8168H_2); 664 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 665 MODULE_FIRMWARE(FIRMWARE_8107E_1); 666 MODULE_FIRMWARE(FIRMWARE_8107E_2); 667 MODULE_FIRMWARE(FIRMWARE_8125A_3); 668 MODULE_FIRMWARE(FIRMWARE_8125B_2); 669 670 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 671 { 672 return &tp->pci_dev->dev; 673 } 674 675 static void rtl_lock_config_regs(struct rtl8169_private *tp) 676 { 677 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 678 } 679 680 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 681 { 682 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 683 } 684 685 static void rtl_pci_commit(struct rtl8169_private *tp) 686 { 687 /* Read an arbitrary register to commit a preceding PCI write */ 688 RTL_R8(tp, ChipCmd); 689 } 690 691 static bool rtl_is_8125(struct rtl8169_private *tp) 692 { 693 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 694 } 695 696 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 697 { 698 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 699 tp->mac_version != RTL_GIGA_MAC_VER_39 && 700 tp->mac_version <= RTL_GIGA_MAC_VER_53; 701 } 702 703 static bool rtl_supports_eee(struct rtl8169_private *tp) 704 { 705 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 706 tp->mac_version != RTL_GIGA_MAC_VER_37 && 707 tp->mac_version != RTL_GIGA_MAC_VER_39; 708 } 709 710 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 711 { 712 int i; 713 714 for (i = 0; i < ETH_ALEN; i++) 715 mac[i] = RTL_R8(tp, reg + i); 716 } 717 718 struct rtl_cond { 719 bool (*check)(struct rtl8169_private *); 720 const char *msg; 721 }; 722 723 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 724 unsigned long usecs, int n, bool high) 725 { 726 int i; 727 728 for (i = 0; i < n; i++) { 729 if (c->check(tp) == high) 730 return true; 731 fsleep(usecs); 732 } 733 734 if (net_ratelimit()) 735 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 736 c->msg, !high, n, usecs); 737 return false; 738 } 739 740 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 741 const struct rtl_cond *c, 742 unsigned long d, int n) 743 { 744 return rtl_loop_wait(tp, c, d, n, true); 745 } 746 747 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 748 const struct rtl_cond *c, 749 unsigned long d, int n) 750 { 751 return rtl_loop_wait(tp, c, d, n, false); 752 } 753 754 #define DECLARE_RTL_COND(name) \ 755 static bool name ## _check(struct rtl8169_private *); \ 756 \ 757 static const struct rtl_cond name = { \ 758 .check = name ## _check, \ 759 .msg = #name \ 760 }; \ 761 \ 762 static bool name ## _check(struct rtl8169_private *tp) 763 764 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 765 { 766 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 767 if (type == ERIAR_OOB && 768 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 769 tp->mac_version == RTL_GIGA_MAC_VER_53)) 770 *cmd |= 0xf70 << 18; 771 } 772 773 DECLARE_RTL_COND(rtl_eriar_cond) 774 { 775 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 776 } 777 778 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 779 u32 val, int type) 780 { 781 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 782 783 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 784 return; 785 786 RTL_W32(tp, ERIDR, val); 787 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 788 RTL_W32(tp, ERIAR, cmd); 789 790 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 791 } 792 793 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 794 u32 val) 795 { 796 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 797 } 798 799 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 800 { 801 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 802 803 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 804 RTL_W32(tp, ERIAR, cmd); 805 806 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 807 RTL_R32(tp, ERIDR) : ~0; 808 } 809 810 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 811 { 812 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 813 } 814 815 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 816 { 817 u32 val = rtl_eri_read(tp, addr); 818 819 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 820 } 821 822 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 823 { 824 rtl_w0w1_eri(tp, addr, p, 0); 825 } 826 827 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 828 { 829 rtl_w0w1_eri(tp, addr, 0, m); 830 } 831 832 static bool rtl_ocp_reg_failure(u32 reg) 833 { 834 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 835 } 836 837 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 838 { 839 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 840 } 841 842 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 843 { 844 if (rtl_ocp_reg_failure(reg)) 845 return; 846 847 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 848 849 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 850 } 851 852 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 853 { 854 if (rtl_ocp_reg_failure(reg)) 855 return 0; 856 857 RTL_W32(tp, GPHY_OCP, reg << 15); 858 859 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 860 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 861 } 862 863 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 864 { 865 if (rtl_ocp_reg_failure(reg)) 866 return; 867 868 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 869 } 870 871 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 872 { 873 if (rtl_ocp_reg_failure(reg)) 874 return 0; 875 876 RTL_W32(tp, OCPDR, reg << 15); 877 878 return RTL_R32(tp, OCPDR); 879 } 880 881 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 882 u16 set) 883 { 884 u16 data = r8168_mac_ocp_read(tp, reg); 885 886 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 887 } 888 889 /* Work around a hw issue with RTL8168g PHY, the quirk disables 890 * PHY MCU interrupts before PHY power-down. 891 */ 892 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 893 { 894 switch (tp->mac_version) { 895 case RTL_GIGA_MAC_VER_40: 896 case RTL_GIGA_MAC_VER_41: 897 case RTL_GIGA_MAC_VER_49: 898 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 899 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 900 else 901 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 902 break; 903 default: 904 break; 905 } 906 }; 907 908 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 909 { 910 if (reg == 0x1f) { 911 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 912 return; 913 } 914 915 if (tp->ocp_base != OCP_STD_PHY_BASE) 916 reg -= 0x10; 917 918 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 919 rtl8168g_phy_suspend_quirk(tp, value); 920 921 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 922 } 923 924 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 925 { 926 if (reg == 0x1f) 927 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 928 929 if (tp->ocp_base != OCP_STD_PHY_BASE) 930 reg -= 0x10; 931 932 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 933 } 934 935 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 936 { 937 if (reg == 0x1f) { 938 tp->ocp_base = value << 4; 939 return; 940 } 941 942 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 943 } 944 945 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 946 { 947 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 948 } 949 950 DECLARE_RTL_COND(rtl_phyar_cond) 951 { 952 return RTL_R32(tp, PHYAR) & 0x80000000; 953 } 954 955 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 956 { 957 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 958 959 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 960 /* 961 * According to hardware specs a 20us delay is required after write 962 * complete indication, but before sending next command. 963 */ 964 udelay(20); 965 } 966 967 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 968 { 969 int value; 970 971 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 972 973 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 974 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 975 976 /* 977 * According to hardware specs a 20us delay is required after read 978 * complete indication, but before sending next command. 979 */ 980 udelay(20); 981 982 return value; 983 } 984 985 DECLARE_RTL_COND(rtl_ocpar_cond) 986 { 987 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 988 } 989 990 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 991 { 992 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 993 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 994 RTL_W32(tp, EPHY_RXER_NUM, 0); 995 996 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 997 } 998 999 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 1000 { 1001 r8168dp_1_mdio_access(tp, reg, 1002 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 1003 } 1004 1005 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 1006 { 1007 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 1008 1009 mdelay(1); 1010 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1011 RTL_W32(tp, EPHY_RXER_NUM, 0); 1012 1013 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1014 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1015 } 1016 1017 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1018 1019 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1020 { 1021 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1022 } 1023 1024 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1025 { 1026 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1027 } 1028 1029 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1030 { 1031 r8168dp_2_mdio_start(tp); 1032 1033 r8169_mdio_write(tp, reg, value); 1034 1035 r8168dp_2_mdio_stop(tp); 1036 } 1037 1038 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1039 { 1040 int value; 1041 1042 /* Work around issue with chip reporting wrong PHY ID */ 1043 if (reg == MII_PHYSID2) 1044 return 0xc912; 1045 1046 r8168dp_2_mdio_start(tp); 1047 1048 value = r8169_mdio_read(tp, reg); 1049 1050 r8168dp_2_mdio_stop(tp); 1051 1052 return value; 1053 } 1054 1055 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1056 { 1057 switch (tp->mac_version) { 1058 case RTL_GIGA_MAC_VER_27: 1059 r8168dp_1_mdio_write(tp, location, val); 1060 break; 1061 case RTL_GIGA_MAC_VER_28: 1062 case RTL_GIGA_MAC_VER_31: 1063 r8168dp_2_mdio_write(tp, location, val); 1064 break; 1065 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1066 r8168g_mdio_write(tp, location, val); 1067 break; 1068 default: 1069 r8169_mdio_write(tp, location, val); 1070 break; 1071 } 1072 } 1073 1074 static int rtl_readphy(struct rtl8169_private *tp, int location) 1075 { 1076 switch (tp->mac_version) { 1077 case RTL_GIGA_MAC_VER_27: 1078 return r8168dp_1_mdio_read(tp, location); 1079 case RTL_GIGA_MAC_VER_28: 1080 case RTL_GIGA_MAC_VER_31: 1081 return r8168dp_2_mdio_read(tp, location); 1082 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1083 return r8168g_mdio_read(tp, location); 1084 default: 1085 return r8169_mdio_read(tp, location); 1086 } 1087 } 1088 1089 DECLARE_RTL_COND(rtl_ephyar_cond) 1090 { 1091 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1092 } 1093 1094 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1095 { 1096 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1097 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1098 1099 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1100 1101 udelay(10); 1102 } 1103 1104 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1105 { 1106 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1107 1108 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1109 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1110 } 1111 1112 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1113 { 1114 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1115 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1116 RTL_R32(tp, OCPDR) : ~0; 1117 } 1118 1119 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1120 { 1121 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1122 } 1123 1124 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1125 u32 data) 1126 { 1127 RTL_W32(tp, OCPDR, data); 1128 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1129 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1130 } 1131 1132 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1133 u32 data) 1134 { 1135 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1136 data, ERIAR_OOB); 1137 } 1138 1139 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1140 { 1141 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1142 1143 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1144 } 1145 1146 #define OOB_CMD_RESET 0x00 1147 #define OOB_CMD_DRIVER_START 0x05 1148 #define OOB_CMD_DRIVER_STOP 0x06 1149 1150 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1151 { 1152 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1153 } 1154 1155 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1156 { 1157 u16 reg; 1158 1159 reg = rtl8168_get_ocp_reg(tp); 1160 1161 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1162 } 1163 1164 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1165 { 1166 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1167 } 1168 1169 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1170 { 1171 return RTL_R8(tp, IBISR0) & 0x20; 1172 } 1173 1174 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1175 { 1176 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1177 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1178 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1179 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1180 } 1181 1182 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1183 { 1184 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1185 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1186 } 1187 1188 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1189 { 1190 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1191 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1192 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1193 } 1194 1195 static void rtl8168_driver_start(struct rtl8169_private *tp) 1196 { 1197 if (tp->dash_type == RTL_DASH_DP) 1198 rtl8168dp_driver_start(tp); 1199 else 1200 rtl8168ep_driver_start(tp); 1201 } 1202 1203 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1204 { 1205 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1206 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1207 } 1208 1209 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1210 { 1211 rtl8168ep_stop_cmac(tp); 1212 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1213 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1214 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1215 } 1216 1217 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1218 { 1219 if (tp->dash_type == RTL_DASH_DP) 1220 rtl8168dp_driver_stop(tp); 1221 else 1222 rtl8168ep_driver_stop(tp); 1223 } 1224 1225 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1226 { 1227 u16 reg = rtl8168_get_ocp_reg(tp); 1228 1229 return r8168dp_ocp_read(tp, reg) & BIT(15); 1230 } 1231 1232 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1233 { 1234 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1235 } 1236 1237 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1238 { 1239 switch (tp->mac_version) { 1240 case RTL_GIGA_MAC_VER_27: 1241 case RTL_GIGA_MAC_VER_28: 1242 case RTL_GIGA_MAC_VER_31: 1243 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1244 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 1245 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1246 default: 1247 return RTL_DASH_NONE; 1248 } 1249 } 1250 1251 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1252 { 1253 switch (tp->mac_version) { 1254 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1255 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1256 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1257 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1258 if (enable) 1259 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1260 else 1261 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1262 break; 1263 default: 1264 break; 1265 } 1266 } 1267 1268 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1269 { 1270 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1271 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1272 } 1273 1274 DECLARE_RTL_COND(rtl_efusear_cond) 1275 { 1276 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1277 } 1278 1279 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1280 { 1281 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1282 1283 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1284 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1285 } 1286 1287 static u32 rtl_get_events(struct rtl8169_private *tp) 1288 { 1289 if (rtl_is_8125(tp)) 1290 return RTL_R32(tp, IntrStatus_8125); 1291 else 1292 return RTL_R16(tp, IntrStatus); 1293 } 1294 1295 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1296 { 1297 if (rtl_is_8125(tp)) 1298 RTL_W32(tp, IntrStatus_8125, bits); 1299 else 1300 RTL_W16(tp, IntrStatus, bits); 1301 } 1302 1303 static void rtl_irq_disable(struct rtl8169_private *tp) 1304 { 1305 if (rtl_is_8125(tp)) 1306 RTL_W32(tp, IntrMask_8125, 0); 1307 else 1308 RTL_W16(tp, IntrMask, 0); 1309 } 1310 1311 static void rtl_irq_enable(struct rtl8169_private *tp) 1312 { 1313 if (rtl_is_8125(tp)) 1314 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1315 else 1316 RTL_W16(tp, IntrMask, tp->irq_mask); 1317 } 1318 1319 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1320 { 1321 rtl_irq_disable(tp); 1322 rtl_ack_events(tp, 0xffffffff); 1323 rtl_pci_commit(tp); 1324 } 1325 1326 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1327 { 1328 struct phy_device *phydev = tp->phydev; 1329 1330 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1331 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1332 if (phydev->speed == SPEED_1000) { 1333 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1334 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1335 } else if (phydev->speed == SPEED_100) { 1336 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1337 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1338 } else { 1339 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1340 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1341 } 1342 rtl_reset_packet_filter(tp); 1343 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1344 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1345 if (phydev->speed == SPEED_1000) { 1346 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1347 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1348 } else { 1349 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1350 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1351 } 1352 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1353 if (phydev->speed == SPEED_10) { 1354 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1355 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1356 } else { 1357 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1358 } 1359 } 1360 } 1361 1362 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1363 1364 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1365 { 1366 struct rtl8169_private *tp = netdev_priv(dev); 1367 1368 wol->supported = WAKE_ANY; 1369 wol->wolopts = tp->saved_wolopts; 1370 } 1371 1372 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1373 { 1374 static const struct { 1375 u32 opt; 1376 u16 reg; 1377 u8 mask; 1378 } cfg[] = { 1379 { WAKE_PHY, Config3, LinkUp }, 1380 { WAKE_UCAST, Config5, UWF }, 1381 { WAKE_BCAST, Config5, BWF }, 1382 { WAKE_MCAST, Config5, MWF }, 1383 { WAKE_ANY, Config5, LanWake }, 1384 { WAKE_MAGIC, Config3, MagicPacket } 1385 }; 1386 unsigned int i, tmp = ARRAY_SIZE(cfg); 1387 u8 options; 1388 1389 rtl_unlock_config_regs(tp); 1390 1391 if (rtl_is_8168evl_up(tp)) { 1392 tmp--; 1393 if (wolopts & WAKE_MAGIC) 1394 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1395 else 1396 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1397 } else if (rtl_is_8125(tp)) { 1398 tmp--; 1399 if (wolopts & WAKE_MAGIC) 1400 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1401 else 1402 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1403 } 1404 1405 for (i = 0; i < tmp; i++) { 1406 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1407 if (wolopts & cfg[i].opt) 1408 options |= cfg[i].mask; 1409 RTL_W8(tp, cfg[i].reg, options); 1410 } 1411 1412 switch (tp->mac_version) { 1413 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1414 options = RTL_R8(tp, Config1) & ~PMEnable; 1415 if (wolopts) 1416 options |= PMEnable; 1417 RTL_W8(tp, Config1, options); 1418 break; 1419 case RTL_GIGA_MAC_VER_34: 1420 case RTL_GIGA_MAC_VER_37: 1421 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1422 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1423 if (wolopts) 1424 options |= PME_SIGNAL; 1425 RTL_W8(tp, Config2, options); 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 rtl_lock_config_regs(tp); 1432 1433 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1434 rtl_set_d3_pll_down(tp, !wolopts); 1435 tp->dev->wol_enabled = wolopts ? 1 : 0; 1436 } 1437 1438 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1439 { 1440 struct rtl8169_private *tp = netdev_priv(dev); 1441 1442 if (wol->wolopts & ~WAKE_ANY) 1443 return -EINVAL; 1444 1445 tp->saved_wolopts = wol->wolopts; 1446 __rtl8169_set_wol(tp, tp->saved_wolopts); 1447 1448 return 0; 1449 } 1450 1451 static void rtl8169_get_drvinfo(struct net_device *dev, 1452 struct ethtool_drvinfo *info) 1453 { 1454 struct rtl8169_private *tp = netdev_priv(dev); 1455 struct rtl_fw *rtl_fw = tp->rtl_fw; 1456 1457 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1458 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1459 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1460 if (rtl_fw) 1461 strlcpy(info->fw_version, rtl_fw->version, 1462 sizeof(info->fw_version)); 1463 } 1464 1465 static int rtl8169_get_regs_len(struct net_device *dev) 1466 { 1467 return R8169_REGS_SIZE; 1468 } 1469 1470 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1471 netdev_features_t features) 1472 { 1473 struct rtl8169_private *tp = netdev_priv(dev); 1474 1475 if (dev->mtu > TD_MSS_MAX) 1476 features &= ~NETIF_F_ALL_TSO; 1477 1478 if (dev->mtu > ETH_DATA_LEN && 1479 tp->mac_version > RTL_GIGA_MAC_VER_06) 1480 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1481 1482 return features; 1483 } 1484 1485 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1486 netdev_features_t features) 1487 { 1488 u32 rx_config = RTL_R32(tp, RxConfig); 1489 1490 if (features & NETIF_F_RXALL) 1491 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1492 else 1493 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1494 1495 if (rtl_is_8125(tp)) { 1496 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1497 rx_config |= RX_VLAN_8125; 1498 else 1499 rx_config &= ~RX_VLAN_8125; 1500 } 1501 1502 RTL_W32(tp, RxConfig, rx_config); 1503 } 1504 1505 static int rtl8169_set_features(struct net_device *dev, 1506 netdev_features_t features) 1507 { 1508 struct rtl8169_private *tp = netdev_priv(dev); 1509 1510 rtl_set_rx_config_features(tp, features); 1511 1512 if (features & NETIF_F_RXCSUM) 1513 tp->cp_cmd |= RxChkSum; 1514 else 1515 tp->cp_cmd &= ~RxChkSum; 1516 1517 if (!rtl_is_8125(tp)) { 1518 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1519 tp->cp_cmd |= RxVlan; 1520 else 1521 tp->cp_cmd &= ~RxVlan; 1522 } 1523 1524 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1525 rtl_pci_commit(tp); 1526 1527 return 0; 1528 } 1529 1530 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1531 { 1532 return (skb_vlan_tag_present(skb)) ? 1533 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1534 } 1535 1536 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1537 { 1538 u32 opts2 = le32_to_cpu(desc->opts2); 1539 1540 if (opts2 & RxVlanTag) 1541 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1542 } 1543 1544 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1545 void *p) 1546 { 1547 struct rtl8169_private *tp = netdev_priv(dev); 1548 u32 __iomem *data = tp->mmio_addr; 1549 u32 *dw = p; 1550 int i; 1551 1552 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1553 memcpy_fromio(dw++, data++, 4); 1554 } 1555 1556 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1557 "tx_packets", 1558 "rx_packets", 1559 "tx_errors", 1560 "rx_errors", 1561 "rx_missed", 1562 "align_errors", 1563 "tx_single_collisions", 1564 "tx_multi_collisions", 1565 "unicast", 1566 "broadcast", 1567 "multicast", 1568 "tx_aborted", 1569 "tx_underrun", 1570 }; 1571 1572 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1573 { 1574 switch (sset) { 1575 case ETH_SS_STATS: 1576 return ARRAY_SIZE(rtl8169_gstrings); 1577 default: 1578 return -EOPNOTSUPP; 1579 } 1580 } 1581 1582 DECLARE_RTL_COND(rtl_counters_cond) 1583 { 1584 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1585 } 1586 1587 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1588 { 1589 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1590 1591 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1592 rtl_pci_commit(tp); 1593 RTL_W32(tp, CounterAddrLow, cmd); 1594 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1595 1596 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1597 } 1598 1599 static void rtl8169_update_counters(struct rtl8169_private *tp) 1600 { 1601 u8 val = RTL_R8(tp, ChipCmd); 1602 1603 /* 1604 * Some chips are unable to dump tally counters when the receiver 1605 * is disabled. If 0xff chip may be in a PCI power-save state. 1606 */ 1607 if (val & CmdRxEnb && val != 0xff) 1608 rtl8169_do_counters(tp, CounterDump); 1609 } 1610 1611 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1612 { 1613 struct rtl8169_counters *counters = tp->counters; 1614 1615 /* 1616 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1617 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1618 * reset by a power cycle, while the counter values collected by the 1619 * driver are reset at every driver unload/load cycle. 1620 * 1621 * To make sure the HW values returned by @get_stats64 match the SW 1622 * values, we collect the initial values at first open(*) and use them 1623 * as offsets to normalize the values returned by @get_stats64. 1624 * 1625 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1626 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1627 * set at open time by rtl_hw_start. 1628 */ 1629 1630 if (tp->tc_offset.inited) 1631 return; 1632 1633 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1634 rtl8169_do_counters(tp, CounterReset); 1635 } else { 1636 rtl8169_update_counters(tp); 1637 tp->tc_offset.tx_errors = counters->tx_errors; 1638 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1639 tp->tc_offset.tx_aborted = counters->tx_aborted; 1640 tp->tc_offset.rx_missed = counters->rx_missed; 1641 } 1642 1643 tp->tc_offset.inited = true; 1644 } 1645 1646 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1647 struct ethtool_stats *stats, u64 *data) 1648 { 1649 struct rtl8169_private *tp = netdev_priv(dev); 1650 struct rtl8169_counters *counters; 1651 1652 counters = tp->counters; 1653 rtl8169_update_counters(tp); 1654 1655 data[0] = le64_to_cpu(counters->tx_packets); 1656 data[1] = le64_to_cpu(counters->rx_packets); 1657 data[2] = le64_to_cpu(counters->tx_errors); 1658 data[3] = le32_to_cpu(counters->rx_errors); 1659 data[4] = le16_to_cpu(counters->rx_missed); 1660 data[5] = le16_to_cpu(counters->align_errors); 1661 data[6] = le32_to_cpu(counters->tx_one_collision); 1662 data[7] = le32_to_cpu(counters->tx_multi_collision); 1663 data[8] = le64_to_cpu(counters->rx_unicast); 1664 data[9] = le64_to_cpu(counters->rx_broadcast); 1665 data[10] = le32_to_cpu(counters->rx_multicast); 1666 data[11] = le16_to_cpu(counters->tx_aborted); 1667 data[12] = le16_to_cpu(counters->tx_underun); 1668 } 1669 1670 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1671 { 1672 switch(stringset) { 1673 case ETH_SS_STATS: 1674 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1675 break; 1676 } 1677 } 1678 1679 /* 1680 * Interrupt coalescing 1681 * 1682 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1683 * > 8169, 8168 and 810x line of chipsets 1684 * 1685 * 8169, 8168, and 8136(810x) serial chipsets support it. 1686 * 1687 * > 2 - the Tx timer unit at gigabit speed 1688 * 1689 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1690 * (0xe0) bit 1 and bit 0. 1691 * 1692 * For 8169 1693 * bit[1:0] \ speed 1000M 100M 10M 1694 * 0 0 320ns 2.56us 40.96us 1695 * 0 1 2.56us 20.48us 327.7us 1696 * 1 0 5.12us 40.96us 655.4us 1697 * 1 1 10.24us 81.92us 1.31ms 1698 * 1699 * For the other 1700 * bit[1:0] \ speed 1000M 100M 10M 1701 * 0 0 5us 2.56us 40.96us 1702 * 0 1 40us 20.48us 327.7us 1703 * 1 0 80us 40.96us 655.4us 1704 * 1 1 160us 81.92us 1.31ms 1705 */ 1706 1707 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1708 struct rtl_coalesce_info { 1709 u32 speed; 1710 u32 scale_nsecs[4]; 1711 }; 1712 1713 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1714 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1715 1716 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1717 { SPEED_1000, COALESCE_DELAY(320) }, 1718 { SPEED_100, COALESCE_DELAY(2560) }, 1719 { SPEED_10, COALESCE_DELAY(40960) }, 1720 { 0 }, 1721 }; 1722 1723 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1724 { SPEED_1000, COALESCE_DELAY(5000) }, 1725 { SPEED_100, COALESCE_DELAY(2560) }, 1726 { SPEED_10, COALESCE_DELAY(40960) }, 1727 { 0 }, 1728 }; 1729 #undef COALESCE_DELAY 1730 1731 /* get rx/tx scale vector corresponding to current speed */ 1732 static const struct rtl_coalesce_info * 1733 rtl_coalesce_info(struct rtl8169_private *tp) 1734 { 1735 const struct rtl_coalesce_info *ci; 1736 1737 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1738 ci = rtl_coalesce_info_8169; 1739 else 1740 ci = rtl_coalesce_info_8168_8136; 1741 1742 /* if speed is unknown assume highest one */ 1743 if (tp->phydev->speed == SPEED_UNKNOWN) 1744 return ci; 1745 1746 for (; ci->speed; ci++) { 1747 if (tp->phydev->speed == ci->speed) 1748 return ci; 1749 } 1750 1751 return ERR_PTR(-ELNRNG); 1752 } 1753 1754 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1755 { 1756 struct rtl8169_private *tp = netdev_priv(dev); 1757 const struct rtl_coalesce_info *ci; 1758 u32 scale, c_us, c_fr; 1759 u16 intrmit; 1760 1761 if (rtl_is_8125(tp)) 1762 return -EOPNOTSUPP; 1763 1764 memset(ec, 0, sizeof(*ec)); 1765 1766 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1767 ci = rtl_coalesce_info(tp); 1768 if (IS_ERR(ci)) 1769 return PTR_ERR(ci); 1770 1771 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1772 1773 intrmit = RTL_R16(tp, IntrMitigate); 1774 1775 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1776 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1777 1778 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1779 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1780 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1781 1782 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1783 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1784 1785 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1786 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1787 1788 return 0; 1789 } 1790 1791 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1792 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1793 u16 *cp01) 1794 { 1795 const struct rtl_coalesce_info *ci; 1796 u16 i; 1797 1798 ci = rtl_coalesce_info(tp); 1799 if (IS_ERR(ci)) 1800 return PTR_ERR(ci); 1801 1802 for (i = 0; i < 4; i++) { 1803 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1804 *cp01 = i; 1805 return ci->scale_nsecs[i]; 1806 } 1807 } 1808 1809 return -ERANGE; 1810 } 1811 1812 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1813 { 1814 struct rtl8169_private *tp = netdev_priv(dev); 1815 u32 tx_fr = ec->tx_max_coalesced_frames; 1816 u32 rx_fr = ec->rx_max_coalesced_frames; 1817 u32 coal_usec_max, units; 1818 u16 w = 0, cp01 = 0; 1819 int scale; 1820 1821 if (rtl_is_8125(tp)) 1822 return -EOPNOTSUPP; 1823 1824 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1825 return -ERANGE; 1826 1827 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1828 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1829 if (scale < 0) 1830 return scale; 1831 1832 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1833 * not only when usecs=0 because of e.g. the following scenario: 1834 * 1835 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1836 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1837 * - then user does `ethtool -C eth0 rx-usecs 100` 1838 * 1839 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1840 * if we want to ignore rx_frames then it has to be set to 0. 1841 */ 1842 if (rx_fr == 1) 1843 rx_fr = 0; 1844 if (tx_fr == 1) 1845 tx_fr = 0; 1846 1847 /* HW requires time limit to be set if frame limit is set */ 1848 if ((tx_fr && !ec->tx_coalesce_usecs) || 1849 (rx_fr && !ec->rx_coalesce_usecs)) 1850 return -EINVAL; 1851 1852 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1853 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1854 1855 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1856 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1857 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1858 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1859 1860 RTL_W16(tp, IntrMitigate, w); 1861 1862 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1863 if (rtl_is_8168evl_up(tp)) { 1864 if (!rx_fr && !tx_fr) 1865 /* disable packet counter */ 1866 tp->cp_cmd |= PktCntrDisable; 1867 else 1868 tp->cp_cmd &= ~PktCntrDisable; 1869 } 1870 1871 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1872 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1873 rtl_pci_commit(tp); 1874 1875 return 0; 1876 } 1877 1878 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1879 { 1880 struct rtl8169_private *tp = netdev_priv(dev); 1881 1882 if (!rtl_supports_eee(tp)) 1883 return -EOPNOTSUPP; 1884 1885 return phy_ethtool_get_eee(tp->phydev, data); 1886 } 1887 1888 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1889 { 1890 struct rtl8169_private *tp = netdev_priv(dev); 1891 int ret; 1892 1893 if (!rtl_supports_eee(tp)) 1894 return -EOPNOTSUPP; 1895 1896 ret = phy_ethtool_set_eee(tp->phydev, data); 1897 1898 if (!ret) 1899 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1900 MDIO_AN_EEE_ADV); 1901 return ret; 1902 } 1903 1904 static void rtl8169_get_ringparam(struct net_device *dev, 1905 struct ethtool_ringparam *data) 1906 { 1907 data->rx_max_pending = NUM_RX_DESC; 1908 data->rx_pending = NUM_RX_DESC; 1909 data->tx_max_pending = NUM_TX_DESC; 1910 data->tx_pending = NUM_TX_DESC; 1911 } 1912 1913 static const struct ethtool_ops rtl8169_ethtool_ops = { 1914 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1915 ETHTOOL_COALESCE_MAX_FRAMES, 1916 .get_drvinfo = rtl8169_get_drvinfo, 1917 .get_regs_len = rtl8169_get_regs_len, 1918 .get_link = ethtool_op_get_link, 1919 .get_coalesce = rtl_get_coalesce, 1920 .set_coalesce = rtl_set_coalesce, 1921 .get_regs = rtl8169_get_regs, 1922 .get_wol = rtl8169_get_wol, 1923 .set_wol = rtl8169_set_wol, 1924 .get_strings = rtl8169_get_strings, 1925 .get_sset_count = rtl8169_get_sset_count, 1926 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1927 .get_ts_info = ethtool_op_get_ts_info, 1928 .nway_reset = phy_ethtool_nway_reset, 1929 .get_eee = rtl8169_get_eee, 1930 .set_eee = rtl8169_set_eee, 1931 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1932 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1933 .get_ringparam = rtl8169_get_ringparam, 1934 }; 1935 1936 static void rtl_enable_eee(struct rtl8169_private *tp) 1937 { 1938 struct phy_device *phydev = tp->phydev; 1939 int adv; 1940 1941 /* respect EEE advertisement the user may have set */ 1942 if (tp->eee_adv >= 0) 1943 adv = tp->eee_adv; 1944 else 1945 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1946 1947 if (adv >= 0) 1948 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1949 } 1950 1951 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1952 { 1953 /* 1954 * The driver currently handles the 8168Bf and the 8168Be identically 1955 * but they can be identified more specifically through the test below 1956 * if needed: 1957 * 1958 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1959 * 1960 * Same thing for the 8101Eb and the 8101Ec: 1961 * 1962 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1963 */ 1964 static const struct rtl_mac_info { 1965 u16 mask; 1966 u16 val; 1967 enum mac_version ver; 1968 } mac_info[] = { 1969 /* 8125B family. */ 1970 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1971 1972 /* 8125A family. */ 1973 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1974 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1975 1976 /* RTL8117 */ 1977 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 1978 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1979 1980 /* 8168EP family. */ 1981 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1982 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1983 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1984 1985 /* 8168H family. */ 1986 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1987 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1988 1989 /* 8168G family. */ 1990 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1991 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1992 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1993 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1994 1995 /* 8168F family. */ 1996 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 1997 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 1998 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 1999 2000 /* 8168E family. */ 2001 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2002 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2003 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2004 2005 /* 8168D family. */ 2006 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2007 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2008 2009 /* 8168DP family. */ 2010 /* It seems this early RTL8168dp version never made it to 2011 * the wild. Let's see whether somebody complains, if not 2012 * we'll remove support for this chip version completely. 2013 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2014 */ 2015 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2016 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2017 2018 /* 8168C family. */ 2019 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2020 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2021 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2022 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2023 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2024 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2025 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2026 2027 /* 8168B family. */ 2028 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2029 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2030 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2031 2032 /* 8101 family. */ 2033 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2034 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2035 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2036 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2037 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2038 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2039 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2040 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2041 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2042 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2043 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2044 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2045 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2046 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2047 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2048 /* FIXME: where did these entries come from ? -- FR 2049 * Not even r8101 vendor driver knows these id's, 2050 * so let's disable detection for now. -- HK 2051 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2052 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2053 */ 2054 2055 /* 8110 family. */ 2056 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2057 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2058 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2059 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2060 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2061 2062 /* Catch-all */ 2063 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2064 }; 2065 const struct rtl_mac_info *p = mac_info; 2066 enum mac_version ver; 2067 2068 while ((xid & p->mask) != p->val) 2069 p++; 2070 ver = p->ver; 2071 2072 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2073 if (ver == RTL_GIGA_MAC_VER_42) 2074 ver = RTL_GIGA_MAC_VER_43; 2075 else if (ver == RTL_GIGA_MAC_VER_45) 2076 ver = RTL_GIGA_MAC_VER_47; 2077 else if (ver == RTL_GIGA_MAC_VER_46) 2078 ver = RTL_GIGA_MAC_VER_48; 2079 } 2080 2081 return ver; 2082 } 2083 2084 static void rtl_release_firmware(struct rtl8169_private *tp) 2085 { 2086 if (tp->rtl_fw) { 2087 rtl_fw_release_firmware(tp->rtl_fw); 2088 kfree(tp->rtl_fw); 2089 tp->rtl_fw = NULL; 2090 } 2091 } 2092 2093 void r8169_apply_firmware(struct rtl8169_private *tp) 2094 { 2095 int val; 2096 2097 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2098 if (tp->rtl_fw) { 2099 rtl_fw_write_firmware(tp, tp->rtl_fw); 2100 /* At least one firmware doesn't reset tp->ocp_base. */ 2101 tp->ocp_base = OCP_STD_PHY_BASE; 2102 2103 /* PHY soft reset may still be in progress */ 2104 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2105 !(val & BMCR_RESET), 2106 50000, 600000, true); 2107 } 2108 } 2109 2110 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2111 { 2112 /* Adjust EEE LED frequency */ 2113 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2114 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2115 2116 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2117 } 2118 2119 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2120 { 2121 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2122 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2123 } 2124 2125 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2126 { 2127 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2128 } 2129 2130 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2131 { 2132 rtl8125_set_eee_txidle_timer(tp); 2133 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2134 } 2135 2136 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2137 { 2138 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2139 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2140 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2141 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2142 } 2143 2144 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2145 { 2146 u16 data1, data2, ioffset; 2147 2148 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2149 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2150 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2151 2152 ioffset = (data2 >> 1) & 0x7ff8; 2153 ioffset |= data2 & 0x0007; 2154 if (data1 & BIT(7)) 2155 ioffset |= BIT(15); 2156 2157 return ioffset; 2158 } 2159 2160 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2161 { 2162 set_bit(flag, tp->wk.flags); 2163 schedule_work(&tp->wk.work); 2164 } 2165 2166 static void rtl8169_init_phy(struct rtl8169_private *tp) 2167 { 2168 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2169 2170 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2171 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2172 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2173 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2174 RTL_W8(tp, 0x82, 0x01); 2175 } 2176 2177 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2178 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2179 tp->pci_dev->subsystem_device == 0xe000) 2180 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2181 2182 /* We may have called phy_speed_down before */ 2183 phy_speed_up(tp->phydev); 2184 2185 if (rtl_supports_eee(tp)) 2186 rtl_enable_eee(tp); 2187 2188 genphy_soft_reset(tp->phydev); 2189 } 2190 2191 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2192 { 2193 rtl_unlock_config_regs(tp); 2194 2195 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2196 rtl_pci_commit(tp); 2197 2198 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2199 rtl_pci_commit(tp); 2200 2201 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2202 rtl_rar_exgmac_set(tp, addr); 2203 2204 rtl_lock_config_regs(tp); 2205 } 2206 2207 static int rtl_set_mac_address(struct net_device *dev, void *p) 2208 { 2209 struct rtl8169_private *tp = netdev_priv(dev); 2210 int ret; 2211 2212 ret = eth_mac_addr(dev, p); 2213 if (ret) 2214 return ret; 2215 2216 rtl_rar_set(tp, dev->dev_addr); 2217 2218 return 0; 2219 } 2220 2221 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2222 { 2223 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2224 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2225 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2226 } 2227 2228 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2229 { 2230 if (tp->dash_type != RTL_DASH_NONE) 2231 return; 2232 2233 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2234 tp->mac_version == RTL_GIGA_MAC_VER_33) 2235 rtl_ephy_write(tp, 0x19, 0xff64); 2236 2237 if (device_may_wakeup(tp_to_dev(tp))) { 2238 phy_speed_down(tp->phydev, false); 2239 rtl_wol_enable_rx(tp); 2240 } 2241 } 2242 2243 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2244 { 2245 switch (tp->mac_version) { 2246 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2247 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2248 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2249 break; 2250 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2251 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2252 case RTL_GIGA_MAC_VER_38: 2253 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2254 break; 2255 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2256 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2257 break; 2258 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2259 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2260 break; 2261 default: 2262 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2263 break; 2264 } 2265 } 2266 2267 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2268 { 2269 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2270 } 2271 2272 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2273 { 2274 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2275 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2276 } 2277 2278 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2279 { 2280 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2281 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2282 } 2283 2284 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2285 { 2286 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2287 } 2288 2289 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2290 { 2291 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2292 } 2293 2294 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2295 { 2296 RTL_W8(tp, MaxTxPacketSize, 0x24); 2297 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2298 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2299 } 2300 2301 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2302 { 2303 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2304 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2305 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2306 } 2307 2308 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2309 { 2310 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2311 } 2312 2313 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2314 { 2315 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2316 } 2317 2318 static void rtl_jumbo_config(struct rtl8169_private *tp) 2319 { 2320 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2321 int readrq = 4096; 2322 2323 rtl_unlock_config_regs(tp); 2324 switch (tp->mac_version) { 2325 case RTL_GIGA_MAC_VER_12: 2326 case RTL_GIGA_MAC_VER_17: 2327 if (jumbo) { 2328 readrq = 512; 2329 r8168b_1_hw_jumbo_enable(tp); 2330 } else { 2331 r8168b_1_hw_jumbo_disable(tp); 2332 } 2333 break; 2334 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2335 if (jumbo) { 2336 readrq = 512; 2337 r8168c_hw_jumbo_enable(tp); 2338 } else { 2339 r8168c_hw_jumbo_disable(tp); 2340 } 2341 break; 2342 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2343 if (jumbo) 2344 r8168dp_hw_jumbo_enable(tp); 2345 else 2346 r8168dp_hw_jumbo_disable(tp); 2347 break; 2348 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2349 if (jumbo) 2350 r8168e_hw_jumbo_enable(tp); 2351 else 2352 r8168e_hw_jumbo_disable(tp); 2353 break; 2354 default: 2355 break; 2356 } 2357 rtl_lock_config_regs(tp); 2358 2359 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2360 pcie_set_readrq(tp->pci_dev, readrq); 2361 } 2362 2363 DECLARE_RTL_COND(rtl_chipcmd_cond) 2364 { 2365 return RTL_R8(tp, ChipCmd) & CmdReset; 2366 } 2367 2368 static void rtl_hw_reset(struct rtl8169_private *tp) 2369 { 2370 RTL_W8(tp, ChipCmd, CmdReset); 2371 2372 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2373 } 2374 2375 static void rtl_request_firmware(struct rtl8169_private *tp) 2376 { 2377 struct rtl_fw *rtl_fw; 2378 2379 /* firmware loaded already or no firmware available */ 2380 if (tp->rtl_fw || !tp->fw_name) 2381 return; 2382 2383 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2384 if (!rtl_fw) 2385 return; 2386 2387 rtl_fw->phy_write = rtl_writephy; 2388 rtl_fw->phy_read = rtl_readphy; 2389 rtl_fw->mac_mcu_write = mac_mcu_write; 2390 rtl_fw->mac_mcu_read = mac_mcu_read; 2391 rtl_fw->fw_name = tp->fw_name; 2392 rtl_fw->dev = tp_to_dev(tp); 2393 2394 if (rtl_fw_request_firmware(rtl_fw)) 2395 kfree(rtl_fw); 2396 else 2397 tp->rtl_fw = rtl_fw; 2398 } 2399 2400 static void rtl_rx_close(struct rtl8169_private *tp) 2401 { 2402 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2403 } 2404 2405 DECLARE_RTL_COND(rtl_npq_cond) 2406 { 2407 return RTL_R8(tp, TxPoll) & NPQ; 2408 } 2409 2410 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2411 { 2412 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2413 } 2414 2415 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2416 { 2417 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2418 } 2419 2420 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2421 { 2422 /* IntrMitigate has new functionality on RTL8125 */ 2423 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2424 } 2425 2426 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2427 { 2428 switch (tp->mac_version) { 2429 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2430 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2431 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2432 break; 2433 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2434 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2435 break; 2436 case RTL_GIGA_MAC_VER_63: 2437 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2438 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2439 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2440 break; 2441 default: 2442 break; 2443 } 2444 } 2445 2446 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2447 { 2448 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2449 fsleep(2000); 2450 rtl_wait_txrx_fifo_empty(tp); 2451 } 2452 2453 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2454 { 2455 u32 val = TX_DMA_BURST << TxDMAShift | 2456 InterFrameGap << TxInterFrameGapShift; 2457 2458 if (rtl_is_8168evl_up(tp)) 2459 val |= TXCFG_AUTO_FIFO; 2460 2461 RTL_W32(tp, TxConfig, val); 2462 } 2463 2464 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2465 { 2466 /* Low hurts. Let's disable the filtering. */ 2467 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2468 } 2469 2470 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2471 { 2472 /* 2473 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2474 * register to be written before TxDescAddrLow to work. 2475 * Switching from MMIO to I/O access fixes the issue as well. 2476 */ 2477 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2478 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2479 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2480 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2481 } 2482 2483 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2484 { 2485 u32 val; 2486 2487 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2488 val = 0x000fff00; 2489 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2490 val = 0x00ffff00; 2491 else 2492 return; 2493 2494 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2495 val |= 0xff; 2496 2497 RTL_W32(tp, 0x7c, val); 2498 } 2499 2500 static void rtl_set_rx_mode(struct net_device *dev) 2501 { 2502 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2503 /* Multicast hash filter */ 2504 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2505 struct rtl8169_private *tp = netdev_priv(dev); 2506 u32 tmp; 2507 2508 if (dev->flags & IFF_PROMISC) { 2509 rx_mode |= AcceptAllPhys; 2510 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2511 dev->flags & IFF_ALLMULTI || 2512 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2513 /* accept all multicasts */ 2514 } else if (netdev_mc_empty(dev)) { 2515 rx_mode &= ~AcceptMulticast; 2516 } else { 2517 struct netdev_hw_addr *ha; 2518 2519 mc_filter[1] = mc_filter[0] = 0; 2520 netdev_for_each_mc_addr(ha, dev) { 2521 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2522 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2523 } 2524 2525 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2526 tmp = mc_filter[0]; 2527 mc_filter[0] = swab32(mc_filter[1]); 2528 mc_filter[1] = swab32(tmp); 2529 } 2530 } 2531 2532 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2533 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2534 2535 tmp = RTL_R32(tp, RxConfig); 2536 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2537 } 2538 2539 DECLARE_RTL_COND(rtl_csiar_cond) 2540 { 2541 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2542 } 2543 2544 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2545 { 2546 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2547 2548 RTL_W32(tp, CSIDR, value); 2549 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2550 CSIAR_BYTE_ENABLE | func << 16); 2551 2552 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2553 } 2554 2555 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2556 { 2557 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2558 2559 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2560 CSIAR_BYTE_ENABLE); 2561 2562 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2563 RTL_R32(tp, CSIDR) : ~0; 2564 } 2565 2566 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2567 { 2568 struct pci_dev *pdev = tp->pci_dev; 2569 u32 csi; 2570 2571 /* According to Realtek the value at config space address 0x070f 2572 * controls the L0s/L1 entrance latency. We try standard ECAM access 2573 * first and if it fails fall back to CSI. 2574 */ 2575 if (pdev->cfg_size > 0x070f && 2576 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2577 return; 2578 2579 netdev_notice_once(tp->dev, 2580 "No native access to PCI extended config space, falling back to CSI\n"); 2581 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2582 rtl_csi_write(tp, 0x070c, csi | val << 24); 2583 } 2584 2585 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2586 { 2587 rtl_csi_access_enable(tp, 0x27); 2588 } 2589 2590 struct ephy_info { 2591 unsigned int offset; 2592 u16 mask; 2593 u16 bits; 2594 }; 2595 2596 static void __rtl_ephy_init(struct rtl8169_private *tp, 2597 const struct ephy_info *e, int len) 2598 { 2599 u16 w; 2600 2601 while (len-- > 0) { 2602 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2603 rtl_ephy_write(tp, e->offset, w); 2604 e++; 2605 } 2606 } 2607 2608 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2609 2610 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2611 { 2612 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2613 PCI_EXP_LNKCTL_CLKREQ_EN); 2614 } 2615 2616 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2617 { 2618 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2619 PCI_EXP_LNKCTL_CLKREQ_EN); 2620 } 2621 2622 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2623 { 2624 /* work around an issue when PCI reset occurs during L2/L3 state */ 2625 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2626 } 2627 2628 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2629 { 2630 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2631 if (enable && tp->aspm_manageable) { 2632 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2633 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2634 } else { 2635 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2636 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2637 } 2638 2639 udelay(10); 2640 } 2641 2642 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2643 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2644 { 2645 /* Usage of dynamic vs. static FIFO is controlled by bit 2646 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2647 */ 2648 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2649 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2650 } 2651 2652 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2653 u8 low, u8 high) 2654 { 2655 /* FIFO thresholds for pause flow control */ 2656 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2657 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2658 } 2659 2660 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2661 { 2662 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2663 } 2664 2665 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2666 { 2667 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2668 2669 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2670 2671 rtl_disable_clock_request(tp); 2672 } 2673 2674 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2675 { 2676 static const struct ephy_info e_info_8168cp[] = { 2677 { 0x01, 0, 0x0001 }, 2678 { 0x02, 0x0800, 0x1000 }, 2679 { 0x03, 0, 0x0042 }, 2680 { 0x06, 0x0080, 0x0000 }, 2681 { 0x07, 0, 0x2000 } 2682 }; 2683 2684 rtl_set_def_aspm_entry_latency(tp); 2685 2686 rtl_ephy_init(tp, e_info_8168cp); 2687 2688 __rtl_hw_start_8168cp(tp); 2689 } 2690 2691 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2692 { 2693 rtl_set_def_aspm_entry_latency(tp); 2694 2695 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2696 } 2697 2698 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2699 { 2700 rtl_set_def_aspm_entry_latency(tp); 2701 2702 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2703 2704 /* Magic. */ 2705 RTL_W8(tp, DBG_REG, 0x20); 2706 } 2707 2708 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2709 { 2710 static const struct ephy_info e_info_8168c_1[] = { 2711 { 0x02, 0x0800, 0x1000 }, 2712 { 0x03, 0, 0x0002 }, 2713 { 0x06, 0x0080, 0x0000 } 2714 }; 2715 2716 rtl_set_def_aspm_entry_latency(tp); 2717 2718 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2719 2720 rtl_ephy_init(tp, e_info_8168c_1); 2721 2722 __rtl_hw_start_8168cp(tp); 2723 } 2724 2725 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2726 { 2727 static const struct ephy_info e_info_8168c_2[] = { 2728 { 0x01, 0, 0x0001 }, 2729 { 0x03, 0x0400, 0x0020 } 2730 }; 2731 2732 rtl_set_def_aspm_entry_latency(tp); 2733 2734 rtl_ephy_init(tp, e_info_8168c_2); 2735 2736 __rtl_hw_start_8168cp(tp); 2737 } 2738 2739 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2740 { 2741 rtl_set_def_aspm_entry_latency(tp); 2742 2743 __rtl_hw_start_8168cp(tp); 2744 } 2745 2746 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2747 { 2748 rtl_set_def_aspm_entry_latency(tp); 2749 2750 rtl_disable_clock_request(tp); 2751 } 2752 2753 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2754 { 2755 static const struct ephy_info e_info_8168d_4[] = { 2756 { 0x0b, 0x0000, 0x0048 }, 2757 { 0x19, 0x0020, 0x0050 }, 2758 { 0x0c, 0x0100, 0x0020 }, 2759 { 0x10, 0x0004, 0x0000 }, 2760 }; 2761 2762 rtl_set_def_aspm_entry_latency(tp); 2763 2764 rtl_ephy_init(tp, e_info_8168d_4); 2765 2766 rtl_enable_clock_request(tp); 2767 } 2768 2769 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2770 { 2771 static const struct ephy_info e_info_8168e_1[] = { 2772 { 0x00, 0x0200, 0x0100 }, 2773 { 0x00, 0x0000, 0x0004 }, 2774 { 0x06, 0x0002, 0x0001 }, 2775 { 0x06, 0x0000, 0x0030 }, 2776 { 0x07, 0x0000, 0x2000 }, 2777 { 0x00, 0x0000, 0x0020 }, 2778 { 0x03, 0x5800, 0x2000 }, 2779 { 0x03, 0x0000, 0x0001 }, 2780 { 0x01, 0x0800, 0x1000 }, 2781 { 0x07, 0x0000, 0x4000 }, 2782 { 0x1e, 0x0000, 0x2000 }, 2783 { 0x19, 0xffff, 0xfe6c }, 2784 { 0x0a, 0x0000, 0x0040 } 2785 }; 2786 2787 rtl_set_def_aspm_entry_latency(tp); 2788 2789 rtl_ephy_init(tp, e_info_8168e_1); 2790 2791 rtl_disable_clock_request(tp); 2792 2793 /* Reset tx FIFO pointer */ 2794 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2795 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2796 2797 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2798 } 2799 2800 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2801 { 2802 static const struct ephy_info e_info_8168e_2[] = { 2803 { 0x09, 0x0000, 0x0080 }, 2804 { 0x19, 0x0000, 0x0224 }, 2805 { 0x00, 0x0000, 0x0004 }, 2806 { 0x0c, 0x3df0, 0x0200 }, 2807 }; 2808 2809 rtl_set_def_aspm_entry_latency(tp); 2810 2811 rtl_ephy_init(tp, e_info_8168e_2); 2812 2813 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2814 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2815 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2816 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2817 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2818 rtl_reset_packet_filter(tp); 2819 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2820 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2821 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2822 2823 rtl_disable_clock_request(tp); 2824 2825 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2826 2827 rtl8168_config_eee_mac(tp); 2828 2829 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2830 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2831 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2832 2833 rtl_hw_aspm_clkreq_enable(tp, true); 2834 } 2835 2836 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2837 { 2838 rtl_set_def_aspm_entry_latency(tp); 2839 2840 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2841 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2842 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2843 rtl_reset_packet_filter(tp); 2844 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2845 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2846 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2847 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2848 2849 rtl_disable_clock_request(tp); 2850 2851 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2852 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2853 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2854 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2855 2856 rtl8168_config_eee_mac(tp); 2857 } 2858 2859 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2860 { 2861 static const struct ephy_info e_info_8168f_1[] = { 2862 { 0x06, 0x00c0, 0x0020 }, 2863 { 0x08, 0x0001, 0x0002 }, 2864 { 0x09, 0x0000, 0x0080 }, 2865 { 0x19, 0x0000, 0x0224 }, 2866 { 0x00, 0x0000, 0x0008 }, 2867 { 0x0c, 0x3df0, 0x0200 }, 2868 }; 2869 2870 rtl_hw_start_8168f(tp); 2871 2872 rtl_ephy_init(tp, e_info_8168f_1); 2873 2874 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2875 } 2876 2877 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2878 { 2879 static const struct ephy_info e_info_8168f_1[] = { 2880 { 0x06, 0x00c0, 0x0020 }, 2881 { 0x0f, 0xffff, 0x5200 }, 2882 { 0x19, 0x0000, 0x0224 }, 2883 { 0x00, 0x0000, 0x0008 }, 2884 { 0x0c, 0x3df0, 0x0200 }, 2885 }; 2886 2887 rtl_hw_start_8168f(tp); 2888 rtl_pcie_state_l2l3_disable(tp); 2889 2890 rtl_ephy_init(tp, e_info_8168f_1); 2891 2892 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2893 } 2894 2895 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2896 { 2897 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2898 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2899 2900 rtl_set_def_aspm_entry_latency(tp); 2901 2902 rtl_reset_packet_filter(tp); 2903 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2904 2905 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2906 2907 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2908 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2909 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2910 2911 rtl8168_config_eee_mac(tp); 2912 2913 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2914 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2915 2916 rtl_pcie_state_l2l3_disable(tp); 2917 } 2918 2919 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2920 { 2921 static const struct ephy_info e_info_8168g_1[] = { 2922 { 0x00, 0x0008, 0x0000 }, 2923 { 0x0c, 0x3ff0, 0x0820 }, 2924 { 0x1e, 0x0000, 0x0001 }, 2925 { 0x19, 0x8000, 0x0000 } 2926 }; 2927 2928 rtl_hw_start_8168g(tp); 2929 2930 /* disable aspm and clock request before access ephy */ 2931 rtl_hw_aspm_clkreq_enable(tp, false); 2932 rtl_ephy_init(tp, e_info_8168g_1); 2933 rtl_hw_aspm_clkreq_enable(tp, true); 2934 } 2935 2936 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 2937 { 2938 static const struct ephy_info e_info_8168g_2[] = { 2939 { 0x00, 0x0008, 0x0000 }, 2940 { 0x0c, 0x3ff0, 0x0820 }, 2941 { 0x19, 0xffff, 0x7c00 }, 2942 { 0x1e, 0xffff, 0x20eb }, 2943 { 0x0d, 0xffff, 0x1666 }, 2944 { 0x00, 0xffff, 0x10a3 }, 2945 { 0x06, 0xffff, 0xf050 }, 2946 { 0x04, 0x0000, 0x0010 }, 2947 { 0x1d, 0x4000, 0x0000 }, 2948 }; 2949 2950 rtl_hw_start_8168g(tp); 2951 2952 /* disable aspm and clock request before access ephy */ 2953 rtl_hw_aspm_clkreq_enable(tp, false); 2954 rtl_ephy_init(tp, e_info_8168g_2); 2955 } 2956 2957 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 2958 { 2959 static const struct ephy_info e_info_8411_2[] = { 2960 { 0x00, 0x0008, 0x0000 }, 2961 { 0x0c, 0x37d0, 0x0820 }, 2962 { 0x1e, 0x0000, 0x0001 }, 2963 { 0x19, 0x8021, 0x0000 }, 2964 { 0x1e, 0x0000, 0x2000 }, 2965 { 0x0d, 0x0100, 0x0200 }, 2966 { 0x00, 0x0000, 0x0080 }, 2967 { 0x06, 0x0000, 0x0010 }, 2968 { 0x04, 0x0000, 0x0010 }, 2969 { 0x1d, 0x0000, 0x4000 }, 2970 }; 2971 2972 rtl_hw_start_8168g(tp); 2973 2974 /* disable aspm and clock request before access ephy */ 2975 rtl_hw_aspm_clkreq_enable(tp, false); 2976 rtl_ephy_init(tp, e_info_8411_2); 2977 2978 /* The following Realtek-provided magic fixes an issue with the RX unit 2979 * getting confused after the PHY having been powered-down. 2980 */ 2981 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 2982 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 2983 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 2984 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 2985 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 2986 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 2987 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 2988 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 2989 mdelay(3); 2990 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 2991 2992 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 2993 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 2994 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 2995 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 2996 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 2997 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 2998 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 2999 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3000 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3001 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3002 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3003 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3004 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3005 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3006 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3007 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3008 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3009 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3010 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3011 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3012 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3013 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3014 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3015 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3016 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3017 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3018 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3019 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3020 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3021 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3022 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3023 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3024 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3025 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3026 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3027 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3028 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3029 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3030 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3031 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3032 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3033 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3034 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3035 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3036 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3037 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3038 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3039 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3040 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3041 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3042 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3043 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3044 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3045 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3046 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3047 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3048 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3049 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3050 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3051 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3052 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3053 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3054 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3055 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3056 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3057 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3058 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3059 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3060 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3061 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3062 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3063 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3064 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3065 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3066 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3067 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3068 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3069 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3070 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3071 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3072 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3073 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3074 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3075 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3076 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3077 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3078 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3079 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3080 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3081 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3082 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3083 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3084 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3085 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3086 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3087 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3088 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3089 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3090 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3091 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3092 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3093 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3094 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3095 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3096 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3097 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3098 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3099 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3100 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3101 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3102 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3103 3104 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3105 3106 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3107 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3108 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3109 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3110 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3111 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3112 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3113 3114 rtl_hw_aspm_clkreq_enable(tp, true); 3115 } 3116 3117 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3118 { 3119 static const struct ephy_info e_info_8168h_1[] = { 3120 { 0x1e, 0x0800, 0x0001 }, 3121 { 0x1d, 0x0000, 0x0800 }, 3122 { 0x05, 0xffff, 0x2089 }, 3123 { 0x06, 0xffff, 0x5881 }, 3124 { 0x04, 0xffff, 0x854a }, 3125 { 0x01, 0xffff, 0x068b } 3126 }; 3127 int rg_saw_cnt; 3128 3129 /* disable aspm and clock request before access ephy */ 3130 rtl_hw_aspm_clkreq_enable(tp, false); 3131 rtl_ephy_init(tp, e_info_8168h_1); 3132 3133 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3134 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3135 3136 rtl_set_def_aspm_entry_latency(tp); 3137 3138 rtl_reset_packet_filter(tp); 3139 3140 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3141 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3142 3143 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3144 3145 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3146 3147 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3148 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3149 3150 rtl8168_config_eee_mac(tp); 3151 3152 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3153 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3154 3155 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3156 3157 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3158 3159 rtl_pcie_state_l2l3_disable(tp); 3160 3161 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3162 if (rg_saw_cnt > 0) { 3163 u16 sw_cnt_1ms_ini; 3164 3165 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3166 sw_cnt_1ms_ini &= 0x0fff; 3167 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3168 } 3169 3170 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3171 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3172 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3173 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3174 3175 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3176 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3177 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3178 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3179 3180 rtl_hw_aspm_clkreq_enable(tp, true); 3181 } 3182 3183 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3184 { 3185 rtl8168ep_stop_cmac(tp); 3186 3187 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3188 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3189 3190 rtl_set_def_aspm_entry_latency(tp); 3191 3192 rtl_reset_packet_filter(tp); 3193 3194 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3195 3196 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3197 3198 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3199 3200 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3201 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3202 3203 rtl8168_config_eee_mac(tp); 3204 3205 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3206 3207 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3208 3209 rtl_pcie_state_l2l3_disable(tp); 3210 } 3211 3212 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3213 { 3214 static const struct ephy_info e_info_8168ep_1[] = { 3215 { 0x00, 0xffff, 0x10ab }, 3216 { 0x06, 0xffff, 0xf030 }, 3217 { 0x08, 0xffff, 0x2006 }, 3218 { 0x0d, 0xffff, 0x1666 }, 3219 { 0x0c, 0x3ff0, 0x0000 } 3220 }; 3221 3222 /* disable aspm and clock request before access ephy */ 3223 rtl_hw_aspm_clkreq_enable(tp, false); 3224 rtl_ephy_init(tp, e_info_8168ep_1); 3225 3226 rtl_hw_start_8168ep(tp); 3227 3228 rtl_hw_aspm_clkreq_enable(tp, true); 3229 } 3230 3231 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3232 { 3233 static const struct ephy_info e_info_8168ep_2[] = { 3234 { 0x00, 0xffff, 0x10a3 }, 3235 { 0x19, 0xffff, 0xfc00 }, 3236 { 0x1e, 0xffff, 0x20ea } 3237 }; 3238 3239 /* disable aspm and clock request before access ephy */ 3240 rtl_hw_aspm_clkreq_enable(tp, false); 3241 rtl_ephy_init(tp, e_info_8168ep_2); 3242 3243 rtl_hw_start_8168ep(tp); 3244 3245 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3246 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3247 3248 rtl_hw_aspm_clkreq_enable(tp, true); 3249 } 3250 3251 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3252 { 3253 static const struct ephy_info e_info_8168ep_3[] = { 3254 { 0x00, 0x0000, 0x0080 }, 3255 { 0x0d, 0x0100, 0x0200 }, 3256 { 0x19, 0x8021, 0x0000 }, 3257 { 0x1e, 0x0000, 0x2000 }, 3258 }; 3259 3260 /* disable aspm and clock request before access ephy */ 3261 rtl_hw_aspm_clkreq_enable(tp, false); 3262 rtl_ephy_init(tp, e_info_8168ep_3); 3263 3264 rtl_hw_start_8168ep(tp); 3265 3266 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3267 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3268 3269 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3270 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3271 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3272 3273 rtl_hw_aspm_clkreq_enable(tp, true); 3274 } 3275 3276 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3277 { 3278 static const struct ephy_info e_info_8117[] = { 3279 { 0x19, 0x0040, 0x1100 }, 3280 { 0x59, 0x0040, 0x1100 }, 3281 }; 3282 int rg_saw_cnt; 3283 3284 rtl8168ep_stop_cmac(tp); 3285 3286 /* disable aspm and clock request before access ephy */ 3287 rtl_hw_aspm_clkreq_enable(tp, false); 3288 rtl_ephy_init(tp, e_info_8117); 3289 3290 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3291 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3292 3293 rtl_set_def_aspm_entry_latency(tp); 3294 3295 rtl_reset_packet_filter(tp); 3296 3297 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3298 3299 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3300 3301 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3302 3303 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3304 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3305 3306 rtl8168_config_eee_mac(tp); 3307 3308 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3309 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3310 3311 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3312 3313 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3314 3315 rtl_pcie_state_l2l3_disable(tp); 3316 3317 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3318 if (rg_saw_cnt > 0) { 3319 u16 sw_cnt_1ms_ini; 3320 3321 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3322 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3323 } 3324 3325 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3326 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3327 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3328 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3329 3330 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3331 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3332 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3333 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3334 3335 /* firmware is for MAC only */ 3336 r8169_apply_firmware(tp); 3337 3338 rtl_hw_aspm_clkreq_enable(tp, true); 3339 } 3340 3341 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3342 { 3343 static const struct ephy_info e_info_8102e_1[] = { 3344 { 0x01, 0, 0x6e65 }, 3345 { 0x02, 0, 0x091f }, 3346 { 0x03, 0, 0xc2f9 }, 3347 { 0x06, 0, 0xafb5 }, 3348 { 0x07, 0, 0x0e00 }, 3349 { 0x19, 0, 0xec80 }, 3350 { 0x01, 0, 0x2e65 }, 3351 { 0x01, 0, 0x6e65 } 3352 }; 3353 u8 cfg1; 3354 3355 rtl_set_def_aspm_entry_latency(tp); 3356 3357 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3358 3359 RTL_W8(tp, Config1, 3360 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3361 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3362 3363 cfg1 = RTL_R8(tp, Config1); 3364 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3365 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3366 3367 rtl_ephy_init(tp, e_info_8102e_1); 3368 } 3369 3370 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3371 { 3372 rtl_set_def_aspm_entry_latency(tp); 3373 3374 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3375 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3376 } 3377 3378 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3379 { 3380 rtl_hw_start_8102e_2(tp); 3381 3382 rtl_ephy_write(tp, 0x03, 0xc2f9); 3383 } 3384 3385 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3386 { 3387 static const struct ephy_info e_info_8401[] = { 3388 { 0x01, 0xffff, 0x6fe5 }, 3389 { 0x03, 0xffff, 0x0599 }, 3390 { 0x06, 0xffff, 0xaf25 }, 3391 { 0x07, 0xffff, 0x8e68 }, 3392 }; 3393 3394 rtl_ephy_init(tp, e_info_8401); 3395 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3396 } 3397 3398 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3399 { 3400 static const struct ephy_info e_info_8105e_1[] = { 3401 { 0x07, 0, 0x4000 }, 3402 { 0x19, 0, 0x0200 }, 3403 { 0x19, 0, 0x0020 }, 3404 { 0x1e, 0, 0x2000 }, 3405 { 0x03, 0, 0x0001 }, 3406 { 0x19, 0, 0x0100 }, 3407 { 0x19, 0, 0x0004 }, 3408 { 0x0a, 0, 0x0020 } 3409 }; 3410 3411 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3412 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3413 3414 /* Disable Early Tally Counter */ 3415 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3416 3417 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3418 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3419 3420 rtl_ephy_init(tp, e_info_8105e_1); 3421 3422 rtl_pcie_state_l2l3_disable(tp); 3423 } 3424 3425 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3426 { 3427 rtl_hw_start_8105e_1(tp); 3428 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3429 } 3430 3431 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3432 { 3433 static const struct ephy_info e_info_8402[] = { 3434 { 0x19, 0xffff, 0xff64 }, 3435 { 0x1e, 0, 0x4000 } 3436 }; 3437 3438 rtl_set_def_aspm_entry_latency(tp); 3439 3440 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3441 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3442 3443 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3444 3445 rtl_ephy_init(tp, e_info_8402); 3446 3447 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3448 rtl_reset_packet_filter(tp); 3449 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3450 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3451 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3452 3453 /* disable EEE */ 3454 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3455 3456 rtl_pcie_state_l2l3_disable(tp); 3457 } 3458 3459 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3460 { 3461 rtl_hw_aspm_clkreq_enable(tp, false); 3462 3463 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3464 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3465 3466 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3467 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3468 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3469 3470 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3471 3472 /* disable EEE */ 3473 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3474 3475 rtl_pcie_state_l2l3_disable(tp); 3476 rtl_hw_aspm_clkreq_enable(tp, true); 3477 } 3478 3479 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3480 { 3481 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3482 } 3483 3484 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3485 { 3486 rtl_pcie_state_l2l3_disable(tp); 3487 3488 RTL_W16(tp, 0x382, 0x221b); 3489 RTL_W8(tp, 0x4500, 0); 3490 RTL_W16(tp, 0x4800, 0); 3491 3492 /* disable UPS */ 3493 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3494 3495 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3496 3497 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3498 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3499 3500 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3501 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3502 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3503 3504 /* disable new tx descriptor format */ 3505 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3506 3507 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3508 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3509 else 3510 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3511 3512 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3513 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3514 else 3515 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3516 3517 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3518 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3519 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3520 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3521 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3522 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3523 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3524 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3525 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3526 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3527 3528 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3529 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3530 udelay(1); 3531 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3532 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3533 3534 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3535 3536 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3537 3538 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3539 rtl8125b_config_eee_mac(tp); 3540 else 3541 rtl8125a_config_eee_mac(tp); 3542 3543 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3544 udelay(10); 3545 } 3546 3547 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3548 { 3549 static const struct ephy_info e_info_8125a_1[] = { 3550 { 0x01, 0xffff, 0xa812 }, 3551 { 0x09, 0xffff, 0x520c }, 3552 { 0x04, 0xffff, 0xd000 }, 3553 { 0x0d, 0xffff, 0xf702 }, 3554 { 0x0a, 0xffff, 0x8653 }, 3555 { 0x06, 0xffff, 0x001e }, 3556 { 0x08, 0xffff, 0x3595 }, 3557 { 0x20, 0xffff, 0x9455 }, 3558 { 0x21, 0xffff, 0x99ff }, 3559 { 0x02, 0xffff, 0x6046 }, 3560 { 0x29, 0xffff, 0xfe00 }, 3561 { 0x23, 0xffff, 0xab62 }, 3562 3563 { 0x41, 0xffff, 0xa80c }, 3564 { 0x49, 0xffff, 0x520c }, 3565 { 0x44, 0xffff, 0xd000 }, 3566 { 0x4d, 0xffff, 0xf702 }, 3567 { 0x4a, 0xffff, 0x8653 }, 3568 { 0x46, 0xffff, 0x001e }, 3569 { 0x48, 0xffff, 0x3595 }, 3570 { 0x60, 0xffff, 0x9455 }, 3571 { 0x61, 0xffff, 0x99ff }, 3572 { 0x42, 0xffff, 0x6046 }, 3573 { 0x69, 0xffff, 0xfe00 }, 3574 { 0x63, 0xffff, 0xab62 }, 3575 }; 3576 3577 rtl_set_def_aspm_entry_latency(tp); 3578 3579 /* disable aspm and clock request before access ephy */ 3580 rtl_hw_aspm_clkreq_enable(tp, false); 3581 rtl_ephy_init(tp, e_info_8125a_1); 3582 3583 rtl_hw_start_8125_common(tp); 3584 rtl_hw_aspm_clkreq_enable(tp, true); 3585 } 3586 3587 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3588 { 3589 static const struct ephy_info e_info_8125a_2[] = { 3590 { 0x04, 0xffff, 0xd000 }, 3591 { 0x0a, 0xffff, 0x8653 }, 3592 { 0x23, 0xffff, 0xab66 }, 3593 { 0x20, 0xffff, 0x9455 }, 3594 { 0x21, 0xffff, 0x99ff }, 3595 { 0x29, 0xffff, 0xfe04 }, 3596 3597 { 0x44, 0xffff, 0xd000 }, 3598 { 0x4a, 0xffff, 0x8653 }, 3599 { 0x63, 0xffff, 0xab66 }, 3600 { 0x60, 0xffff, 0x9455 }, 3601 { 0x61, 0xffff, 0x99ff }, 3602 { 0x69, 0xffff, 0xfe04 }, 3603 }; 3604 3605 rtl_set_def_aspm_entry_latency(tp); 3606 3607 /* disable aspm and clock request before access ephy */ 3608 rtl_hw_aspm_clkreq_enable(tp, false); 3609 rtl_ephy_init(tp, e_info_8125a_2); 3610 3611 rtl_hw_start_8125_common(tp); 3612 rtl_hw_aspm_clkreq_enable(tp, true); 3613 } 3614 3615 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3616 { 3617 static const struct ephy_info e_info_8125b[] = { 3618 { 0x0b, 0xffff, 0xa908 }, 3619 { 0x1e, 0xffff, 0x20eb }, 3620 { 0x4b, 0xffff, 0xa908 }, 3621 { 0x5e, 0xffff, 0x20eb }, 3622 { 0x22, 0x0030, 0x0020 }, 3623 { 0x62, 0x0030, 0x0020 }, 3624 }; 3625 3626 rtl_set_def_aspm_entry_latency(tp); 3627 rtl_hw_aspm_clkreq_enable(tp, false); 3628 3629 rtl_ephy_init(tp, e_info_8125b); 3630 rtl_hw_start_8125_common(tp); 3631 3632 rtl_hw_aspm_clkreq_enable(tp, true); 3633 } 3634 3635 static void rtl_hw_config(struct rtl8169_private *tp) 3636 { 3637 static const rtl_generic_fct hw_configs[] = { 3638 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3639 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3640 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3641 [RTL_GIGA_MAC_VER_10] = NULL, 3642 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3643 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3644 [RTL_GIGA_MAC_VER_13] = NULL, 3645 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3646 [RTL_GIGA_MAC_VER_16] = NULL, 3647 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3648 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3649 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3650 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3651 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3652 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3653 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3654 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3655 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3656 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3657 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3658 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3659 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3660 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3661 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3662 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3663 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3664 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3665 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3666 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3667 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3668 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3669 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3670 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3671 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3672 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3673 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3674 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3675 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3676 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3677 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3678 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3679 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3680 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3681 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3682 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3683 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3684 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3685 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3686 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3687 }; 3688 3689 if (hw_configs[tp->mac_version]) 3690 hw_configs[tp->mac_version](tp); 3691 } 3692 3693 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3694 { 3695 int i; 3696 3697 /* disable interrupt coalescing */ 3698 for (i = 0xa00; i < 0xb00; i += 4) 3699 RTL_W32(tp, i, 0); 3700 3701 rtl_hw_config(tp); 3702 } 3703 3704 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3705 { 3706 if (rtl_is_8168evl_up(tp)) 3707 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3708 else 3709 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3710 3711 rtl_hw_config(tp); 3712 3713 /* disable interrupt coalescing */ 3714 RTL_W16(tp, IntrMitigate, 0x0000); 3715 } 3716 3717 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3718 { 3719 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3720 3721 tp->cp_cmd |= PCIMulRW; 3722 3723 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3724 tp->mac_version == RTL_GIGA_MAC_VER_03) 3725 tp->cp_cmd |= EnAnaPLL; 3726 3727 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3728 3729 rtl8169_set_magic_reg(tp); 3730 3731 /* disable interrupt coalescing */ 3732 RTL_W16(tp, IntrMitigate, 0x0000); 3733 } 3734 3735 static void rtl_hw_start(struct rtl8169_private *tp) 3736 { 3737 rtl_unlock_config_regs(tp); 3738 3739 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3740 3741 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3742 rtl_hw_start_8169(tp); 3743 else if (rtl_is_8125(tp)) 3744 rtl_hw_start_8125(tp); 3745 else 3746 rtl_hw_start_8168(tp); 3747 3748 rtl_set_rx_max_size(tp); 3749 rtl_set_rx_tx_desc_registers(tp); 3750 rtl_lock_config_regs(tp); 3751 3752 rtl_jumbo_config(tp); 3753 3754 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3755 rtl_pci_commit(tp); 3756 3757 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3758 rtl_init_rxcfg(tp); 3759 rtl_set_tx_config_registers(tp); 3760 rtl_set_rx_config_features(tp, tp->dev->features); 3761 rtl_set_rx_mode(tp->dev); 3762 rtl_irq_enable(tp); 3763 } 3764 3765 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3766 { 3767 struct rtl8169_private *tp = netdev_priv(dev); 3768 3769 dev->mtu = new_mtu; 3770 netdev_update_features(dev); 3771 rtl_jumbo_config(tp); 3772 3773 switch (tp->mac_version) { 3774 case RTL_GIGA_MAC_VER_61: 3775 case RTL_GIGA_MAC_VER_63: 3776 rtl8125_set_eee_txidle_timer(tp); 3777 break; 3778 default: 3779 break; 3780 } 3781 3782 return 0; 3783 } 3784 3785 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3786 { 3787 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3788 3789 desc->opts2 = 0; 3790 /* Force memory writes to complete before releasing descriptor */ 3791 dma_wmb(); 3792 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3793 } 3794 3795 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3796 struct RxDesc *desc) 3797 { 3798 struct device *d = tp_to_dev(tp); 3799 int node = dev_to_node(d); 3800 dma_addr_t mapping; 3801 struct page *data; 3802 3803 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3804 if (!data) 3805 return NULL; 3806 3807 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3808 if (unlikely(dma_mapping_error(d, mapping))) { 3809 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3810 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3811 return NULL; 3812 } 3813 3814 desc->addr = cpu_to_le64(mapping); 3815 rtl8169_mark_to_asic(desc); 3816 3817 return data; 3818 } 3819 3820 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3821 { 3822 int i; 3823 3824 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3825 dma_unmap_page(tp_to_dev(tp), 3826 le64_to_cpu(tp->RxDescArray[i].addr), 3827 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3828 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3829 tp->Rx_databuff[i] = NULL; 3830 tp->RxDescArray[i].addr = 0; 3831 tp->RxDescArray[i].opts1 = 0; 3832 } 3833 } 3834 3835 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3836 { 3837 int i; 3838 3839 for (i = 0; i < NUM_RX_DESC; i++) { 3840 struct page *data; 3841 3842 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3843 if (!data) { 3844 rtl8169_rx_clear(tp); 3845 return -ENOMEM; 3846 } 3847 tp->Rx_databuff[i] = data; 3848 } 3849 3850 /* mark as last descriptor in the ring */ 3851 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3852 3853 return 0; 3854 } 3855 3856 static int rtl8169_init_ring(struct rtl8169_private *tp) 3857 { 3858 rtl8169_init_ring_indexes(tp); 3859 3860 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3861 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3862 3863 return rtl8169_rx_fill(tp); 3864 } 3865 3866 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3867 { 3868 struct ring_info *tx_skb = tp->tx_skb + entry; 3869 struct TxDesc *desc = tp->TxDescArray + entry; 3870 3871 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3872 DMA_TO_DEVICE); 3873 memset(desc, 0, sizeof(*desc)); 3874 memset(tx_skb, 0, sizeof(*tx_skb)); 3875 } 3876 3877 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3878 unsigned int n) 3879 { 3880 unsigned int i; 3881 3882 for (i = 0; i < n; i++) { 3883 unsigned int entry = (start + i) % NUM_TX_DESC; 3884 struct ring_info *tx_skb = tp->tx_skb + entry; 3885 unsigned int len = tx_skb->len; 3886 3887 if (len) { 3888 struct sk_buff *skb = tx_skb->skb; 3889 3890 rtl8169_unmap_tx_skb(tp, entry); 3891 if (skb) 3892 dev_consume_skb_any(skb); 3893 } 3894 } 3895 } 3896 3897 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3898 { 3899 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3900 netdev_reset_queue(tp->dev); 3901 } 3902 3903 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3904 { 3905 napi_disable(&tp->napi); 3906 3907 /* Give a racing hard_start_xmit a few cycles to complete. */ 3908 synchronize_net(); 3909 3910 /* Disable interrupts */ 3911 rtl8169_irq_mask_and_ack(tp); 3912 3913 rtl_rx_close(tp); 3914 3915 if (going_down && tp->dev->wol_enabled) 3916 goto no_reset; 3917 3918 switch (tp->mac_version) { 3919 case RTL_GIGA_MAC_VER_27: 3920 case RTL_GIGA_MAC_VER_28: 3921 case RTL_GIGA_MAC_VER_31: 3922 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3923 break; 3924 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3925 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3926 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3927 break; 3928 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3929 rtl_enable_rxdvgate(tp); 3930 fsleep(2000); 3931 break; 3932 default: 3933 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3934 fsleep(100); 3935 break; 3936 } 3937 3938 rtl_hw_reset(tp); 3939 no_reset: 3940 rtl8169_tx_clear(tp); 3941 rtl8169_init_ring_indexes(tp); 3942 } 3943 3944 static void rtl_reset_work(struct rtl8169_private *tp) 3945 { 3946 int i; 3947 3948 netif_stop_queue(tp->dev); 3949 3950 rtl8169_cleanup(tp, false); 3951 3952 for (i = 0; i < NUM_RX_DESC; i++) 3953 rtl8169_mark_to_asic(tp->RxDescArray + i); 3954 3955 napi_enable(&tp->napi); 3956 rtl_hw_start(tp); 3957 } 3958 3959 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3960 { 3961 struct rtl8169_private *tp = netdev_priv(dev); 3962 3963 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3964 } 3965 3966 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3967 void *addr, unsigned int entry, bool desc_own) 3968 { 3969 struct TxDesc *txd = tp->TxDescArray + entry; 3970 struct device *d = tp_to_dev(tp); 3971 dma_addr_t mapping; 3972 u32 opts1; 3973 int ret; 3974 3975 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3976 ret = dma_mapping_error(d, mapping); 3977 if (unlikely(ret)) { 3978 if (net_ratelimit()) 3979 netdev_err(tp->dev, "Failed to map TX data!\n"); 3980 return ret; 3981 } 3982 3983 txd->addr = cpu_to_le64(mapping); 3984 txd->opts2 = cpu_to_le32(opts[1]); 3985 3986 opts1 = opts[0] | len; 3987 if (entry == NUM_TX_DESC - 1) 3988 opts1 |= RingEnd; 3989 if (desc_own) 3990 opts1 |= DescOwn; 3991 txd->opts1 = cpu_to_le32(opts1); 3992 3993 tp->tx_skb[entry].len = len; 3994 3995 return 0; 3996 } 3997 3998 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3999 const u32 *opts, unsigned int entry) 4000 { 4001 struct skb_shared_info *info = skb_shinfo(skb); 4002 unsigned int cur_frag; 4003 4004 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4005 const skb_frag_t *frag = info->frags + cur_frag; 4006 void *addr = skb_frag_address(frag); 4007 u32 len = skb_frag_size(frag); 4008 4009 entry = (entry + 1) % NUM_TX_DESC; 4010 4011 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4012 goto err_out; 4013 } 4014 4015 return 0; 4016 4017 err_out: 4018 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4019 return -EIO; 4020 } 4021 4022 static bool rtl_skb_is_udp(struct sk_buff *skb) 4023 { 4024 int no = skb_network_offset(skb); 4025 struct ipv6hdr *i6h, _i6h; 4026 struct iphdr *ih, _ih; 4027 4028 switch (vlan_get_protocol(skb)) { 4029 case htons(ETH_P_IP): 4030 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4031 return ih && ih->protocol == IPPROTO_UDP; 4032 case htons(ETH_P_IPV6): 4033 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4034 return i6h && i6h->nexthdr == IPPROTO_UDP; 4035 default: 4036 return false; 4037 } 4038 } 4039 4040 #define RTL_MIN_PATCH_LEN 47 4041 4042 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4043 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4044 struct sk_buff *skb) 4045 { 4046 unsigned int padto = 0, len = skb->len; 4047 4048 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4049 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4050 unsigned int trans_data_len = skb_tail_pointer(skb) - 4051 skb_transport_header(skb); 4052 4053 if (trans_data_len >= offsetof(struct udphdr, len) && 4054 trans_data_len < RTL_MIN_PATCH_LEN) { 4055 u16 dest = ntohs(udp_hdr(skb)->dest); 4056 4057 /* dest is a standard PTP port */ 4058 if (dest == 319 || dest == 320) 4059 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4060 } 4061 4062 if (trans_data_len < sizeof(struct udphdr)) 4063 padto = max_t(unsigned int, padto, 4064 len + sizeof(struct udphdr) - trans_data_len); 4065 } 4066 4067 return padto; 4068 } 4069 4070 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4071 struct sk_buff *skb) 4072 { 4073 unsigned int padto; 4074 4075 padto = rtl8125_quirk_udp_padto(tp, skb); 4076 4077 switch (tp->mac_version) { 4078 case RTL_GIGA_MAC_VER_34: 4079 case RTL_GIGA_MAC_VER_60: 4080 case RTL_GIGA_MAC_VER_61: 4081 case RTL_GIGA_MAC_VER_63: 4082 padto = max_t(unsigned int, padto, ETH_ZLEN); 4083 default: 4084 break; 4085 } 4086 4087 return padto; 4088 } 4089 4090 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4091 { 4092 u32 mss = skb_shinfo(skb)->gso_size; 4093 4094 if (mss) { 4095 opts[0] |= TD_LSO; 4096 opts[0] |= mss << TD0_MSS_SHIFT; 4097 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4098 const struct iphdr *ip = ip_hdr(skb); 4099 4100 if (ip->protocol == IPPROTO_TCP) 4101 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4102 else if (ip->protocol == IPPROTO_UDP) 4103 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4104 else 4105 WARN_ON_ONCE(1); 4106 } 4107 } 4108 4109 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4110 struct sk_buff *skb, u32 *opts) 4111 { 4112 u32 transport_offset = (u32)skb_transport_offset(skb); 4113 struct skb_shared_info *shinfo = skb_shinfo(skb); 4114 u32 mss = shinfo->gso_size; 4115 4116 if (mss) { 4117 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4118 opts[0] |= TD1_GTSENV4; 4119 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4120 if (skb_cow_head(skb, 0)) 4121 return false; 4122 4123 tcp_v6_gso_csum_prep(skb); 4124 opts[0] |= TD1_GTSENV6; 4125 } else { 4126 WARN_ON_ONCE(1); 4127 } 4128 4129 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4130 opts[1] |= mss << TD1_MSS_SHIFT; 4131 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4132 u8 ip_protocol; 4133 4134 switch (vlan_get_protocol(skb)) { 4135 case htons(ETH_P_IP): 4136 opts[1] |= TD1_IPv4_CS; 4137 ip_protocol = ip_hdr(skb)->protocol; 4138 break; 4139 4140 case htons(ETH_P_IPV6): 4141 opts[1] |= TD1_IPv6_CS; 4142 ip_protocol = ipv6_hdr(skb)->nexthdr; 4143 break; 4144 4145 default: 4146 ip_protocol = IPPROTO_RAW; 4147 break; 4148 } 4149 4150 if (ip_protocol == IPPROTO_TCP) 4151 opts[1] |= TD1_TCP_CS; 4152 else if (ip_protocol == IPPROTO_UDP) 4153 opts[1] |= TD1_UDP_CS; 4154 else 4155 WARN_ON_ONCE(1); 4156 4157 opts[1] |= transport_offset << TCPHO_SHIFT; 4158 } else { 4159 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4160 4161 /* skb_padto would free the skb on error */ 4162 return !__skb_put_padto(skb, padto, false); 4163 } 4164 4165 return true; 4166 } 4167 4168 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4169 { 4170 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4171 - READ_ONCE(tp->cur_tx); 4172 4173 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4174 return slots_avail > MAX_SKB_FRAGS; 4175 } 4176 4177 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4178 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4179 { 4180 switch (tp->mac_version) { 4181 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4182 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4183 return false; 4184 default: 4185 return true; 4186 } 4187 } 4188 4189 static void rtl8169_doorbell(struct rtl8169_private *tp) 4190 { 4191 if (rtl_is_8125(tp)) 4192 RTL_W16(tp, TxPoll_8125, BIT(0)); 4193 else 4194 RTL_W8(tp, TxPoll, NPQ); 4195 } 4196 4197 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4198 struct net_device *dev) 4199 { 4200 unsigned int frags = skb_shinfo(skb)->nr_frags; 4201 struct rtl8169_private *tp = netdev_priv(dev); 4202 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4203 struct TxDesc *txd_first, *txd_last; 4204 bool stop_queue, door_bell; 4205 u32 opts[2]; 4206 4207 if (unlikely(!rtl_tx_slots_avail(tp))) { 4208 if (net_ratelimit()) 4209 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4210 goto err_stop_0; 4211 } 4212 4213 opts[1] = rtl8169_tx_vlan_tag(skb); 4214 opts[0] = 0; 4215 4216 if (!rtl_chip_supports_csum_v2(tp)) 4217 rtl8169_tso_csum_v1(skb, opts); 4218 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4219 goto err_dma_0; 4220 4221 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4222 entry, false))) 4223 goto err_dma_0; 4224 4225 txd_first = tp->TxDescArray + entry; 4226 4227 if (frags) { 4228 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4229 goto err_dma_1; 4230 entry = (entry + frags) % NUM_TX_DESC; 4231 } 4232 4233 txd_last = tp->TxDescArray + entry; 4234 txd_last->opts1 |= cpu_to_le32(LastFrag); 4235 tp->tx_skb[entry].skb = skb; 4236 4237 skb_tx_timestamp(skb); 4238 4239 /* Force memory writes to complete before releasing descriptor */ 4240 dma_wmb(); 4241 4242 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4243 4244 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4245 4246 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4247 smp_wmb(); 4248 4249 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4250 4251 stop_queue = !rtl_tx_slots_avail(tp); 4252 if (unlikely(stop_queue)) { 4253 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4254 * not miss a ring update when it notices a stopped queue. 4255 */ 4256 smp_wmb(); 4257 netif_stop_queue(dev); 4258 /* Sync with rtl_tx: 4259 * - publish queue status and cur_tx ring index (write barrier) 4260 * - refresh dirty_tx ring index (read barrier). 4261 * May the current thread have a pessimistic view of the ring 4262 * status and forget to wake up queue, a racing rtl_tx thread 4263 * can't. 4264 */ 4265 smp_mb__after_atomic(); 4266 if (rtl_tx_slots_avail(tp)) 4267 netif_start_queue(dev); 4268 door_bell = true; 4269 } 4270 4271 if (door_bell) 4272 rtl8169_doorbell(tp); 4273 4274 return NETDEV_TX_OK; 4275 4276 err_dma_1: 4277 rtl8169_unmap_tx_skb(tp, entry); 4278 err_dma_0: 4279 dev_kfree_skb_any(skb); 4280 dev->stats.tx_dropped++; 4281 return NETDEV_TX_OK; 4282 4283 err_stop_0: 4284 netif_stop_queue(dev); 4285 dev->stats.tx_dropped++; 4286 return NETDEV_TX_BUSY; 4287 } 4288 4289 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4290 { 4291 struct skb_shared_info *info = skb_shinfo(skb); 4292 unsigned int nr_frags = info->nr_frags; 4293 4294 if (!nr_frags) 4295 return UINT_MAX; 4296 4297 return skb_frag_size(info->frags + nr_frags - 1); 4298 } 4299 4300 /* Workaround for hw issues with TSO on RTL8168evl */ 4301 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4302 netdev_features_t features) 4303 { 4304 /* IPv4 header has options field */ 4305 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4306 ip_hdrlen(skb) > sizeof(struct iphdr)) 4307 features &= ~NETIF_F_ALL_TSO; 4308 4309 /* IPv4 TCP header has options field */ 4310 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4311 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4312 features &= ~NETIF_F_ALL_TSO; 4313 4314 else if (rtl_last_frag_len(skb) <= 6) 4315 features &= ~NETIF_F_ALL_TSO; 4316 4317 return features; 4318 } 4319 4320 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4321 struct net_device *dev, 4322 netdev_features_t features) 4323 { 4324 int transport_offset = skb_transport_offset(skb); 4325 struct rtl8169_private *tp = netdev_priv(dev); 4326 4327 if (skb_is_gso(skb)) { 4328 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4329 features = rtl8168evl_fix_tso(skb, features); 4330 4331 if (transport_offset > GTTCPHO_MAX && 4332 rtl_chip_supports_csum_v2(tp)) 4333 features &= ~NETIF_F_ALL_TSO; 4334 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4335 /* work around hw bug on some chip versions */ 4336 if (skb->len < ETH_ZLEN) 4337 features &= ~NETIF_F_CSUM_MASK; 4338 4339 if (rtl_quirk_packet_padto(tp, skb)) 4340 features &= ~NETIF_F_CSUM_MASK; 4341 4342 if (transport_offset > TCPHO_MAX && 4343 rtl_chip_supports_csum_v2(tp)) 4344 features &= ~NETIF_F_CSUM_MASK; 4345 } 4346 4347 return vlan_features_check(skb, features); 4348 } 4349 4350 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4351 { 4352 struct rtl8169_private *tp = netdev_priv(dev); 4353 struct pci_dev *pdev = tp->pci_dev; 4354 int pci_status_errs; 4355 u16 pci_cmd; 4356 4357 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4358 4359 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4360 4361 if (net_ratelimit()) 4362 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4363 pci_cmd, pci_status_errs); 4364 /* 4365 * The recovery sequence below admits a very elaborated explanation: 4366 * - it seems to work; 4367 * - I did not see what else could be done; 4368 * - it makes iop3xx happy. 4369 * 4370 * Feel free to adjust to your needs. 4371 */ 4372 if (pdev->broken_parity_status) 4373 pci_cmd &= ~PCI_COMMAND_PARITY; 4374 else 4375 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4376 4377 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4378 4379 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4380 } 4381 4382 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4383 int budget) 4384 { 4385 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4386 struct sk_buff *skb; 4387 4388 dirty_tx = tp->dirty_tx; 4389 4390 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4391 unsigned int entry = dirty_tx % NUM_TX_DESC; 4392 u32 status; 4393 4394 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4395 if (status & DescOwn) 4396 break; 4397 4398 skb = tp->tx_skb[entry].skb; 4399 rtl8169_unmap_tx_skb(tp, entry); 4400 4401 if (skb) { 4402 pkts_compl++; 4403 bytes_compl += skb->len; 4404 napi_consume_skb(skb, budget); 4405 } 4406 dirty_tx++; 4407 } 4408 4409 if (tp->dirty_tx != dirty_tx) { 4410 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4411 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4412 4413 /* Sync with rtl8169_start_xmit: 4414 * - publish dirty_tx ring index (write barrier) 4415 * - refresh cur_tx ring index and queue status (read barrier) 4416 * May the current thread miss the stopped queue condition, 4417 * a racing xmit thread can only have a right view of the 4418 * ring status. 4419 */ 4420 smp_store_mb(tp->dirty_tx, dirty_tx); 4421 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4422 netif_wake_queue(dev); 4423 /* 4424 * 8168 hack: TxPoll requests are lost when the Tx packets are 4425 * too close. Let's kick an extra TxPoll request when a burst 4426 * of start_xmit activity is detected (if it is not detected, 4427 * it is slow enough). -- FR 4428 * If skb is NULL then we come here again once a tx irq is 4429 * triggered after the last fragment is marked transmitted. 4430 */ 4431 if (tp->cur_tx != dirty_tx && skb) 4432 rtl8169_doorbell(tp); 4433 } 4434 } 4435 4436 static inline int rtl8169_fragmented_frame(u32 status) 4437 { 4438 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4439 } 4440 4441 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4442 { 4443 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4444 4445 if (status == RxProtoTCP || status == RxProtoUDP) 4446 skb->ip_summed = CHECKSUM_UNNECESSARY; 4447 else 4448 skb_checksum_none_assert(skb); 4449 } 4450 4451 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4452 { 4453 struct device *d = tp_to_dev(tp); 4454 int count; 4455 4456 for (count = 0; count < budget; count++, tp->cur_rx++) { 4457 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4458 struct RxDesc *desc = tp->RxDescArray + entry; 4459 struct sk_buff *skb; 4460 const void *rx_buf; 4461 dma_addr_t addr; 4462 u32 status; 4463 4464 status = le32_to_cpu(desc->opts1); 4465 if (status & DescOwn) 4466 break; 4467 4468 /* This barrier is needed to keep us from reading 4469 * any other fields out of the Rx descriptor until 4470 * we know the status of DescOwn 4471 */ 4472 dma_rmb(); 4473 4474 if (unlikely(status & RxRES)) { 4475 if (net_ratelimit()) 4476 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4477 status); 4478 dev->stats.rx_errors++; 4479 if (status & (RxRWT | RxRUNT)) 4480 dev->stats.rx_length_errors++; 4481 if (status & RxCRC) 4482 dev->stats.rx_crc_errors++; 4483 4484 if (!(dev->features & NETIF_F_RXALL)) 4485 goto release_descriptor; 4486 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4487 goto release_descriptor; 4488 } 4489 4490 pkt_size = status & GENMASK(13, 0); 4491 if (likely(!(dev->features & NETIF_F_RXFCS))) 4492 pkt_size -= ETH_FCS_LEN; 4493 4494 /* The driver does not support incoming fragmented frames. 4495 * They are seen as a symptom of over-mtu sized frames. 4496 */ 4497 if (unlikely(rtl8169_fragmented_frame(status))) { 4498 dev->stats.rx_dropped++; 4499 dev->stats.rx_length_errors++; 4500 goto release_descriptor; 4501 } 4502 4503 skb = napi_alloc_skb(&tp->napi, pkt_size); 4504 if (unlikely(!skb)) { 4505 dev->stats.rx_dropped++; 4506 goto release_descriptor; 4507 } 4508 4509 addr = le64_to_cpu(desc->addr); 4510 rx_buf = page_address(tp->Rx_databuff[entry]); 4511 4512 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4513 prefetch(rx_buf); 4514 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4515 skb->tail += pkt_size; 4516 skb->len = pkt_size; 4517 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4518 4519 rtl8169_rx_csum(skb, status); 4520 skb->protocol = eth_type_trans(skb, dev); 4521 4522 rtl8169_rx_vlan_tag(desc, skb); 4523 4524 if (skb->pkt_type == PACKET_MULTICAST) 4525 dev->stats.multicast++; 4526 4527 napi_gro_receive(&tp->napi, skb); 4528 4529 dev_sw_netstats_rx_add(dev, pkt_size); 4530 release_descriptor: 4531 rtl8169_mark_to_asic(desc); 4532 } 4533 4534 return count; 4535 } 4536 4537 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4538 { 4539 struct rtl8169_private *tp = dev_instance; 4540 u32 status = rtl_get_events(tp); 4541 4542 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4543 return IRQ_NONE; 4544 4545 if (unlikely(status & SYSErr)) { 4546 rtl8169_pcierr_interrupt(tp->dev); 4547 goto out; 4548 } 4549 4550 if (status & LinkChg) 4551 phy_mac_interrupt(tp->phydev); 4552 4553 if (unlikely(status & RxFIFOOver && 4554 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4555 netif_stop_queue(tp->dev); 4556 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4557 } 4558 4559 if (napi_schedule_prep(&tp->napi)) { 4560 rtl_irq_disable(tp); 4561 __napi_schedule(&tp->napi); 4562 } 4563 out: 4564 rtl_ack_events(tp, status); 4565 4566 return IRQ_HANDLED; 4567 } 4568 4569 static void rtl_task(struct work_struct *work) 4570 { 4571 struct rtl8169_private *tp = 4572 container_of(work, struct rtl8169_private, wk.work); 4573 4574 rtnl_lock(); 4575 4576 if (!netif_running(tp->dev) || 4577 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4578 goto out_unlock; 4579 4580 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4581 rtl_reset_work(tp); 4582 netif_wake_queue(tp->dev); 4583 } 4584 out_unlock: 4585 rtnl_unlock(); 4586 } 4587 4588 static int rtl8169_poll(struct napi_struct *napi, int budget) 4589 { 4590 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4591 struct net_device *dev = tp->dev; 4592 int work_done; 4593 4594 rtl_tx(dev, tp, budget); 4595 4596 work_done = rtl_rx(dev, tp, budget); 4597 4598 if (work_done < budget && napi_complete_done(napi, work_done)) 4599 rtl_irq_enable(tp); 4600 4601 return work_done; 4602 } 4603 4604 static void r8169_phylink_handler(struct net_device *ndev) 4605 { 4606 struct rtl8169_private *tp = netdev_priv(ndev); 4607 4608 if (netif_carrier_ok(ndev)) { 4609 rtl_link_chg_patch(tp); 4610 pm_request_resume(&tp->pci_dev->dev); 4611 } else { 4612 pm_runtime_idle(&tp->pci_dev->dev); 4613 } 4614 4615 if (net_ratelimit()) 4616 phy_print_status(tp->phydev); 4617 } 4618 4619 static int r8169_phy_connect(struct rtl8169_private *tp) 4620 { 4621 struct phy_device *phydev = tp->phydev; 4622 phy_interface_t phy_mode; 4623 int ret; 4624 4625 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4626 PHY_INTERFACE_MODE_MII; 4627 4628 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4629 phy_mode); 4630 if (ret) 4631 return ret; 4632 4633 if (!tp->supports_gmii) 4634 phy_set_max_speed(phydev, SPEED_100); 4635 4636 phy_support_asym_pause(phydev); 4637 4638 phy_attached_info(phydev); 4639 4640 return 0; 4641 } 4642 4643 static void rtl8169_down(struct rtl8169_private *tp) 4644 { 4645 /* Clear all task flags */ 4646 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4647 4648 phy_stop(tp->phydev); 4649 4650 rtl8169_update_counters(tp); 4651 4652 pci_clear_master(tp->pci_dev); 4653 rtl_pci_commit(tp); 4654 4655 rtl8169_cleanup(tp, true); 4656 4657 rtl_prepare_power_down(tp); 4658 } 4659 4660 static void rtl8169_up(struct rtl8169_private *tp) 4661 { 4662 pci_set_master(tp->pci_dev); 4663 phy_resume(tp->phydev); 4664 rtl8169_init_phy(tp); 4665 napi_enable(&tp->napi); 4666 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4667 rtl_reset_work(tp); 4668 4669 phy_start(tp->phydev); 4670 } 4671 4672 static int rtl8169_close(struct net_device *dev) 4673 { 4674 struct rtl8169_private *tp = netdev_priv(dev); 4675 struct pci_dev *pdev = tp->pci_dev; 4676 4677 pm_runtime_get_sync(&pdev->dev); 4678 4679 netif_stop_queue(dev); 4680 rtl8169_down(tp); 4681 rtl8169_rx_clear(tp); 4682 4683 cancel_work_sync(&tp->wk.work); 4684 4685 free_irq(pci_irq_vector(pdev, 0), tp); 4686 4687 phy_disconnect(tp->phydev); 4688 4689 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4690 tp->RxPhyAddr); 4691 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4692 tp->TxPhyAddr); 4693 tp->TxDescArray = NULL; 4694 tp->RxDescArray = NULL; 4695 4696 pm_runtime_put_sync(&pdev->dev); 4697 4698 return 0; 4699 } 4700 4701 #ifdef CONFIG_NET_POLL_CONTROLLER 4702 static void rtl8169_netpoll(struct net_device *dev) 4703 { 4704 struct rtl8169_private *tp = netdev_priv(dev); 4705 4706 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4707 } 4708 #endif 4709 4710 static int rtl_open(struct net_device *dev) 4711 { 4712 struct rtl8169_private *tp = netdev_priv(dev); 4713 struct pci_dev *pdev = tp->pci_dev; 4714 unsigned long irqflags; 4715 int retval = -ENOMEM; 4716 4717 pm_runtime_get_sync(&pdev->dev); 4718 4719 /* 4720 * Rx and Tx descriptors needs 256 bytes alignment. 4721 * dma_alloc_coherent provides more. 4722 */ 4723 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4724 &tp->TxPhyAddr, GFP_KERNEL); 4725 if (!tp->TxDescArray) 4726 goto out; 4727 4728 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4729 &tp->RxPhyAddr, GFP_KERNEL); 4730 if (!tp->RxDescArray) 4731 goto err_free_tx_0; 4732 4733 retval = rtl8169_init_ring(tp); 4734 if (retval < 0) 4735 goto err_free_rx_1; 4736 4737 rtl_request_firmware(tp); 4738 4739 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4740 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt, 4741 irqflags, dev->name, tp); 4742 if (retval < 0) 4743 goto err_release_fw_2; 4744 4745 retval = r8169_phy_connect(tp); 4746 if (retval) 4747 goto err_free_irq; 4748 4749 rtl8169_up(tp); 4750 rtl8169_init_counter_offsets(tp); 4751 netif_start_queue(dev); 4752 out: 4753 pm_runtime_put_sync(&pdev->dev); 4754 4755 return retval; 4756 4757 err_free_irq: 4758 free_irq(pci_irq_vector(pdev, 0), tp); 4759 err_release_fw_2: 4760 rtl_release_firmware(tp); 4761 rtl8169_rx_clear(tp); 4762 err_free_rx_1: 4763 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4764 tp->RxPhyAddr); 4765 tp->RxDescArray = NULL; 4766 err_free_tx_0: 4767 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4768 tp->TxPhyAddr); 4769 tp->TxDescArray = NULL; 4770 goto out; 4771 } 4772 4773 static void 4774 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4775 { 4776 struct rtl8169_private *tp = netdev_priv(dev); 4777 struct pci_dev *pdev = tp->pci_dev; 4778 struct rtl8169_counters *counters = tp->counters; 4779 4780 pm_runtime_get_noresume(&pdev->dev); 4781 4782 netdev_stats_to_stats64(stats, &dev->stats); 4783 dev_fetch_sw_netstats(stats, dev->tstats); 4784 4785 /* 4786 * Fetch additional counter values missing in stats collected by driver 4787 * from tally counters. 4788 */ 4789 if (pm_runtime_active(&pdev->dev)) 4790 rtl8169_update_counters(tp); 4791 4792 /* 4793 * Subtract values fetched during initalization. 4794 * See rtl8169_init_counter_offsets for a description why we do that. 4795 */ 4796 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4797 le64_to_cpu(tp->tc_offset.tx_errors); 4798 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4799 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4800 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4801 le16_to_cpu(tp->tc_offset.tx_aborted); 4802 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4803 le16_to_cpu(tp->tc_offset.rx_missed); 4804 4805 pm_runtime_put_noidle(&pdev->dev); 4806 } 4807 4808 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4809 { 4810 netif_device_detach(tp->dev); 4811 4812 if (netif_running(tp->dev)) 4813 rtl8169_down(tp); 4814 } 4815 4816 #ifdef CONFIG_PM 4817 4818 static int rtl8169_runtime_resume(struct device *dev) 4819 { 4820 struct rtl8169_private *tp = dev_get_drvdata(dev); 4821 4822 rtl_rar_set(tp, tp->dev->dev_addr); 4823 __rtl8169_set_wol(tp, tp->saved_wolopts); 4824 4825 if (tp->TxDescArray) 4826 rtl8169_up(tp); 4827 4828 netif_device_attach(tp->dev); 4829 4830 return 0; 4831 } 4832 4833 static int __maybe_unused rtl8169_suspend(struct device *device) 4834 { 4835 struct rtl8169_private *tp = dev_get_drvdata(device); 4836 4837 rtnl_lock(); 4838 rtl8169_net_suspend(tp); 4839 if (!device_may_wakeup(tp_to_dev(tp))) 4840 clk_disable_unprepare(tp->clk); 4841 rtnl_unlock(); 4842 4843 return 0; 4844 } 4845 4846 static int __maybe_unused rtl8169_resume(struct device *device) 4847 { 4848 struct rtl8169_private *tp = dev_get_drvdata(device); 4849 4850 if (!device_may_wakeup(tp_to_dev(tp))) 4851 clk_prepare_enable(tp->clk); 4852 4853 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4854 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4855 rtl_init_rxcfg(tp); 4856 4857 return rtl8169_runtime_resume(device); 4858 } 4859 4860 static int rtl8169_runtime_suspend(struct device *device) 4861 { 4862 struct rtl8169_private *tp = dev_get_drvdata(device); 4863 4864 if (!tp->TxDescArray) { 4865 netif_device_detach(tp->dev); 4866 return 0; 4867 } 4868 4869 rtnl_lock(); 4870 __rtl8169_set_wol(tp, WAKE_PHY); 4871 rtl8169_net_suspend(tp); 4872 rtnl_unlock(); 4873 4874 return 0; 4875 } 4876 4877 static int rtl8169_runtime_idle(struct device *device) 4878 { 4879 struct rtl8169_private *tp = dev_get_drvdata(device); 4880 4881 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4882 pm_schedule_suspend(device, 10000); 4883 4884 return -EBUSY; 4885 } 4886 4887 static const struct dev_pm_ops rtl8169_pm_ops = { 4888 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4889 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4890 rtl8169_runtime_idle) 4891 }; 4892 4893 #endif /* CONFIG_PM */ 4894 4895 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4896 { 4897 /* WoL fails with 8168b when the receiver is disabled. */ 4898 switch (tp->mac_version) { 4899 case RTL_GIGA_MAC_VER_11: 4900 case RTL_GIGA_MAC_VER_12: 4901 case RTL_GIGA_MAC_VER_17: 4902 pci_clear_master(tp->pci_dev); 4903 4904 RTL_W8(tp, ChipCmd, CmdRxEnb); 4905 rtl_pci_commit(tp); 4906 break; 4907 default: 4908 break; 4909 } 4910 } 4911 4912 static void rtl_shutdown(struct pci_dev *pdev) 4913 { 4914 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4915 4916 rtnl_lock(); 4917 rtl8169_net_suspend(tp); 4918 rtnl_unlock(); 4919 4920 /* Restore original MAC address */ 4921 rtl_rar_set(tp, tp->dev->perm_addr); 4922 4923 if (system_state == SYSTEM_POWER_OFF) { 4924 if (tp->saved_wolopts) 4925 rtl_wol_shutdown_quirk(tp); 4926 4927 pci_wake_from_d3(pdev, tp->saved_wolopts); 4928 pci_set_power_state(pdev, PCI_D3hot); 4929 } 4930 } 4931 4932 static void rtl_remove_one(struct pci_dev *pdev) 4933 { 4934 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4935 4936 if (pci_dev_run_wake(pdev)) 4937 pm_runtime_get_noresume(&pdev->dev); 4938 4939 unregister_netdev(tp->dev); 4940 4941 if (tp->dash_type != RTL_DASH_NONE) 4942 rtl8168_driver_stop(tp); 4943 4944 rtl_release_firmware(tp); 4945 4946 /* restore original MAC address */ 4947 rtl_rar_set(tp, tp->dev->perm_addr); 4948 } 4949 4950 static const struct net_device_ops rtl_netdev_ops = { 4951 .ndo_open = rtl_open, 4952 .ndo_stop = rtl8169_close, 4953 .ndo_get_stats64 = rtl8169_get_stats64, 4954 .ndo_start_xmit = rtl8169_start_xmit, 4955 .ndo_features_check = rtl8169_features_check, 4956 .ndo_tx_timeout = rtl8169_tx_timeout, 4957 .ndo_validate_addr = eth_validate_addr, 4958 .ndo_change_mtu = rtl8169_change_mtu, 4959 .ndo_fix_features = rtl8169_fix_features, 4960 .ndo_set_features = rtl8169_set_features, 4961 .ndo_set_mac_address = rtl_set_mac_address, 4962 .ndo_do_ioctl = phy_do_ioctl_running, 4963 .ndo_set_rx_mode = rtl_set_rx_mode, 4964 #ifdef CONFIG_NET_POLL_CONTROLLER 4965 .ndo_poll_controller = rtl8169_netpoll, 4966 #endif 4967 4968 }; 4969 4970 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4971 { 4972 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4973 4974 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4975 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4976 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4977 /* special workaround needed */ 4978 tp->irq_mask |= RxFIFOOver; 4979 else 4980 tp->irq_mask |= RxOverflow; 4981 } 4982 4983 static int rtl_alloc_irq(struct rtl8169_private *tp) 4984 { 4985 unsigned int flags; 4986 4987 switch (tp->mac_version) { 4988 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4989 rtl_unlock_config_regs(tp); 4990 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4991 rtl_lock_config_regs(tp); 4992 fallthrough; 4993 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4994 flags = PCI_IRQ_LEGACY; 4995 break; 4996 default: 4997 flags = PCI_IRQ_ALL_TYPES; 4998 break; 4999 } 5000 5001 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5002 } 5003 5004 static void rtl_read_mac_address(struct rtl8169_private *tp, 5005 u8 mac_addr[ETH_ALEN]) 5006 { 5007 /* Get MAC address */ 5008 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5009 u32 value; 5010 5011 value = rtl_eri_read(tp, 0xe0); 5012 put_unaligned_le32(value, mac_addr); 5013 value = rtl_eri_read(tp, 0xe4); 5014 put_unaligned_le16(value, mac_addr + 4); 5015 } else if (rtl_is_8125(tp)) { 5016 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5017 } 5018 } 5019 5020 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5021 { 5022 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5023 } 5024 5025 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5026 { 5027 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5028 } 5029 5030 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5031 { 5032 struct rtl8169_private *tp = mii_bus->priv; 5033 5034 if (phyaddr > 0) 5035 return -ENODEV; 5036 5037 return rtl_readphy(tp, phyreg); 5038 } 5039 5040 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5041 int phyreg, u16 val) 5042 { 5043 struct rtl8169_private *tp = mii_bus->priv; 5044 5045 if (phyaddr > 0) 5046 return -ENODEV; 5047 5048 rtl_writephy(tp, phyreg, val); 5049 5050 return 0; 5051 } 5052 5053 static int r8169_mdio_register(struct rtl8169_private *tp) 5054 { 5055 struct pci_dev *pdev = tp->pci_dev; 5056 struct mii_bus *new_bus; 5057 int ret; 5058 5059 new_bus = devm_mdiobus_alloc(&pdev->dev); 5060 if (!new_bus) 5061 return -ENOMEM; 5062 5063 new_bus->name = "r8169"; 5064 new_bus->priv = tp; 5065 new_bus->parent = &pdev->dev; 5066 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5067 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5068 5069 new_bus->read = r8169_mdio_read_reg; 5070 new_bus->write = r8169_mdio_write_reg; 5071 5072 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5073 if (ret) 5074 return ret; 5075 5076 tp->phydev = mdiobus_get_phy(new_bus, 0); 5077 if (!tp->phydev) { 5078 return -ENODEV; 5079 } else if (!tp->phydev->drv) { 5080 /* Most chip versions fail with the genphy driver. 5081 * Therefore ensure that the dedicated PHY driver is loaded. 5082 */ 5083 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5084 tp->phydev->phy_id); 5085 return -EUNATCH; 5086 } 5087 5088 /* PHY will be woken up in rtl_open() */ 5089 phy_suspend(tp->phydev); 5090 5091 return 0; 5092 } 5093 5094 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5095 { 5096 rtl_enable_rxdvgate(tp); 5097 5098 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5099 msleep(1); 5100 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5101 5102 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5103 r8168g_wait_ll_share_fifo_ready(tp); 5104 5105 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5106 r8168g_wait_ll_share_fifo_ready(tp); 5107 } 5108 5109 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5110 { 5111 rtl_enable_rxdvgate(tp); 5112 5113 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5114 msleep(1); 5115 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5116 5117 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5118 r8168g_wait_ll_share_fifo_ready(tp); 5119 5120 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5121 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5122 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5123 r8168g_wait_ll_share_fifo_ready(tp); 5124 } 5125 5126 static void rtl_hw_initialize(struct rtl8169_private *tp) 5127 { 5128 switch (tp->mac_version) { 5129 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 5130 rtl8168ep_stop_cmac(tp); 5131 fallthrough; 5132 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5133 rtl_hw_init_8168g(tp); 5134 break; 5135 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5136 rtl_hw_init_8125(tp); 5137 break; 5138 default: 5139 break; 5140 } 5141 } 5142 5143 static int rtl_jumbo_max(struct rtl8169_private *tp) 5144 { 5145 /* Non-GBit versions don't support jumbo frames */ 5146 if (!tp->supports_gmii) 5147 return 0; 5148 5149 switch (tp->mac_version) { 5150 /* RTL8169 */ 5151 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5152 return JUMBO_7K; 5153 /* RTL8168b */ 5154 case RTL_GIGA_MAC_VER_11: 5155 case RTL_GIGA_MAC_VER_12: 5156 case RTL_GIGA_MAC_VER_17: 5157 return JUMBO_4K; 5158 /* RTL8168c */ 5159 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5160 return JUMBO_6K; 5161 default: 5162 return JUMBO_9K; 5163 } 5164 } 5165 5166 static void rtl_disable_clk(void *data) 5167 { 5168 clk_disable_unprepare(data); 5169 } 5170 5171 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5172 { 5173 struct device *d = tp_to_dev(tp); 5174 struct clk *clk; 5175 int rc; 5176 5177 clk = devm_clk_get(d, "ether_clk"); 5178 if (IS_ERR(clk)) { 5179 rc = PTR_ERR(clk); 5180 if (rc == -ENOENT) 5181 /* clk-core allows NULL (for suspend / resume) */ 5182 rc = 0; 5183 else 5184 dev_err_probe(d, rc, "failed to get clk\n"); 5185 } else { 5186 tp->clk = clk; 5187 rc = clk_prepare_enable(clk); 5188 if (rc) 5189 dev_err(d, "failed to enable clk: %d\n", rc); 5190 else 5191 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5192 } 5193 5194 return rc; 5195 } 5196 5197 static void rtl_init_mac_address(struct rtl8169_private *tp) 5198 { 5199 struct net_device *dev = tp->dev; 5200 u8 *mac_addr = dev->dev_addr; 5201 int rc; 5202 5203 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5204 if (!rc) 5205 goto done; 5206 5207 rtl_read_mac_address(tp, mac_addr); 5208 if (is_valid_ether_addr(mac_addr)) 5209 goto done; 5210 5211 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5212 if (is_valid_ether_addr(mac_addr)) 5213 goto done; 5214 5215 eth_hw_addr_random(dev); 5216 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5217 done: 5218 rtl_rar_set(tp, mac_addr); 5219 } 5220 5221 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5222 { 5223 struct rtl8169_private *tp; 5224 int jumbo_max, region, rc; 5225 enum mac_version chipset; 5226 struct net_device *dev; 5227 u16 xid; 5228 5229 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5230 if (!dev) 5231 return -ENOMEM; 5232 5233 SET_NETDEV_DEV(dev, &pdev->dev); 5234 dev->netdev_ops = &rtl_netdev_ops; 5235 tp = netdev_priv(dev); 5236 tp->dev = dev; 5237 tp->pci_dev = pdev; 5238 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5239 tp->eee_adv = -1; 5240 tp->ocp_base = OCP_STD_PHY_BASE; 5241 5242 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5243 struct pcpu_sw_netstats); 5244 if (!dev->tstats) 5245 return -ENOMEM; 5246 5247 /* Get the *optional* external "ether_clk" used on some boards */ 5248 rc = rtl_get_ether_clk(tp); 5249 if (rc) 5250 return rc; 5251 5252 /* Disable ASPM completely as that cause random device stop working 5253 * problems as well as full system hangs for some PCIe devices users. 5254 */ 5255 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5256 PCIE_LINK_STATE_L1); 5257 tp->aspm_manageable = !rc; 5258 5259 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5260 rc = pcim_enable_device(pdev); 5261 if (rc < 0) { 5262 dev_err(&pdev->dev, "enable failure\n"); 5263 return rc; 5264 } 5265 5266 if (pcim_set_mwi(pdev) < 0) 5267 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5268 5269 /* use first MMIO region */ 5270 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5271 if (region < 0) { 5272 dev_err(&pdev->dev, "no MMIO resource found\n"); 5273 return -ENODEV; 5274 } 5275 5276 /* check for weird/broken PCI region reporting */ 5277 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5278 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5279 return -ENODEV; 5280 } 5281 5282 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5283 if (rc < 0) { 5284 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5285 return rc; 5286 } 5287 5288 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5289 5290 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5291 5292 /* Identify chip attached to board */ 5293 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5294 if (chipset == RTL_GIGA_MAC_NONE) { 5295 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5296 return -ENODEV; 5297 } 5298 5299 tp->mac_version = chipset; 5300 5301 tp->dash_type = rtl_check_dash(tp); 5302 5303 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5304 5305 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5306 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5307 dev->features |= NETIF_F_HIGHDMA; 5308 5309 rtl_init_rxcfg(tp); 5310 5311 rtl8169_irq_mask_and_ack(tp); 5312 5313 rtl_hw_initialize(tp); 5314 5315 rtl_hw_reset(tp); 5316 5317 rc = rtl_alloc_irq(tp); 5318 if (rc < 0) { 5319 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5320 return rc; 5321 } 5322 5323 INIT_WORK(&tp->wk.work, rtl_task); 5324 5325 rtl_init_mac_address(tp); 5326 5327 dev->ethtool_ops = &rtl8169_ethtool_ops; 5328 5329 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5330 5331 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5332 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5333 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5334 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5335 5336 /* 5337 * Pretend we are using VLANs; This bypasses a nasty bug where 5338 * Interrupts stop flowing on high load on 8110SCd controllers. 5339 */ 5340 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5341 /* Disallow toggling */ 5342 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5343 5344 if (rtl_chip_supports_csum_v2(tp)) 5345 dev->hw_features |= NETIF_F_IPV6_CSUM; 5346 5347 dev->features |= dev->hw_features; 5348 5349 /* There has been a number of reports that using SG/TSO results in 5350 * tx timeouts. However for a lot of people SG/TSO works fine. 5351 * Therefore disable both features by default, but allow users to 5352 * enable them. Use at own risk! 5353 */ 5354 if (rtl_chip_supports_csum_v2(tp)) { 5355 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5356 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5357 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5358 } else { 5359 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5360 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5361 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5362 } 5363 5364 dev->hw_features |= NETIF_F_RXALL; 5365 dev->hw_features |= NETIF_F_RXFCS; 5366 5367 /* configure chip for default features */ 5368 rtl8169_set_features(dev, dev->features); 5369 5370 rtl_set_d3_pll_down(tp, true); 5371 5372 jumbo_max = rtl_jumbo_max(tp); 5373 if (jumbo_max) 5374 dev->max_mtu = jumbo_max; 5375 5376 rtl_set_irq_mask(tp); 5377 5378 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5379 5380 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5381 &tp->counters_phys_addr, 5382 GFP_KERNEL); 5383 if (!tp->counters) 5384 return -ENOMEM; 5385 5386 pci_set_drvdata(pdev, tp); 5387 5388 rc = r8169_mdio_register(tp); 5389 if (rc) 5390 return rc; 5391 5392 rc = register_netdev(dev); 5393 if (rc) 5394 return rc; 5395 5396 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5397 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5398 pci_irq_vector(pdev, 0)); 5399 5400 if (jumbo_max) 5401 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5402 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5403 "ok" : "ko"); 5404 5405 if (tp->dash_type != RTL_DASH_NONE) { 5406 netdev_info(dev, "DASH enabled\n"); 5407 rtl8168_driver_start(tp); 5408 } 5409 5410 if (pci_dev_run_wake(pdev)) 5411 pm_runtime_put_sync(&pdev->dev); 5412 5413 return 0; 5414 } 5415 5416 static struct pci_driver rtl8169_pci_driver = { 5417 .name = MODULENAME, 5418 .id_table = rtl8169_pci_tbl, 5419 .probe = rtl_init_one, 5420 .remove = rtl_remove_one, 5421 .shutdown = rtl_shutdown, 5422 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5423 }; 5424 5425 module_pci_driver(rtl8169_pci_driver); 5426