1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <net/ip6_checksum.h> 32 33 #include "r8169.h" 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 58 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 59 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 60 61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 63 #define MC_FILTER_LIMIT 32 64 65 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 66 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 67 68 #define R8169_REGS_SIZE 256 69 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 70 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 71 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 72 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 73 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 74 75 #define OCP_STD_PHY_BASE 0xa400 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92 static const struct { 93 const char *name; 94 const char *fw_name; 95 } rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 110 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 111 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 112 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 113 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 119 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 121 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 122 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 125 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 127 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 128 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 129 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 130 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 131 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 132 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 133 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 134 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 135 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 136 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 137 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 138 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 139 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 140 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 141 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 142 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 143 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 144 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 145 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 148 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 149 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 150 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 151 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 152 }; 153 154 static const struct pci_device_id rtl8169_pci_tbl[] = { 155 { PCI_VDEVICE(REALTEK, 0x2502) }, 156 { PCI_VDEVICE(REALTEK, 0x2600) }, 157 { PCI_VDEVICE(REALTEK, 0x8129) }, 158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 159 { PCI_VDEVICE(REALTEK, 0x8161) }, 160 { PCI_VDEVICE(REALTEK, 0x8167) }, 161 { PCI_VDEVICE(REALTEK, 0x8168) }, 162 { PCI_VDEVICE(NCUBE, 0x8168) }, 163 { PCI_VDEVICE(REALTEK, 0x8169) }, 164 { PCI_VENDOR_ID_DLINK, 0x4300, 165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 166 { PCI_VDEVICE(DLINK, 0x4300) }, 167 { PCI_VDEVICE(DLINK, 0x4302) }, 168 { PCI_VDEVICE(AT, 0xc107) }, 169 { PCI_VDEVICE(USR, 0x0116) }, 170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 172 { PCI_VDEVICE(REALTEK, 0x8125) }, 173 { PCI_VDEVICE(REALTEK, 0x3000) }, 174 {} 175 }; 176 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 178 179 enum rtl_registers { 180 MAC0 = 0, /* Ethernet hardware address. */ 181 MAC4 = 4, 182 MAR0 = 8, /* Multicast filter. */ 183 CounterAddrLow = 0x10, 184 CounterAddrHigh = 0x14, 185 TxDescStartAddrLow = 0x20, 186 TxDescStartAddrHigh = 0x24, 187 TxHDescStartAddrLow = 0x28, 188 TxHDescStartAddrHigh = 0x2c, 189 FLASH = 0x30, 190 ERSR = 0x36, 191 ChipCmd = 0x37, 192 TxPoll = 0x38, 193 IntrMask = 0x3c, 194 IntrStatus = 0x3e, 195 196 TxConfig = 0x40, 197 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 198 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 199 200 RxConfig = 0x44, 201 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 202 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 203 #define RXCFG_FIFO_SHIFT 13 204 /* No threshold before first PCI xfer */ 205 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 206 #define RX_EARLY_OFF (1 << 11) 207 #define RXCFG_DMA_SHIFT 8 208 /* Unlimited maximum PCI burst. */ 209 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 210 211 Cfg9346 = 0x50, 212 Config0 = 0x51, 213 Config1 = 0x52, 214 Config2 = 0x53, 215 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 216 217 Config3 = 0x54, 218 Config4 = 0x55, 219 Config5 = 0x56, 220 PHYAR = 0x60, 221 PHYstatus = 0x6c, 222 RxMaxSize = 0xda, 223 CPlusCmd = 0xe0, 224 IntrMitigate = 0xe2, 225 226 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 227 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 228 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 229 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 230 231 #define RTL_COALESCE_T_MAX 0x0fU 232 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 233 234 RxDescAddrLow = 0xe4, 235 RxDescAddrHigh = 0xe8, 236 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 237 238 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 239 240 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 241 242 #define TxPacketMax (8064 >> 7) 243 #define EarlySize 0x27 244 245 FuncEvent = 0xf0, 246 FuncEventMask = 0xf4, 247 FuncPresetState = 0xf8, 248 IBCR0 = 0xf8, 249 IBCR2 = 0xf9, 250 IBIMR0 = 0xfa, 251 IBISR0 = 0xfb, 252 FuncForceEvent = 0xfc, 253 }; 254 255 enum rtl8168_8101_registers { 256 CSIDR = 0x64, 257 CSIAR = 0x68, 258 #define CSIAR_FLAG 0x80000000 259 #define CSIAR_WRITE_CMD 0x80000000 260 #define CSIAR_BYTE_ENABLE 0x0000f000 261 #define CSIAR_ADDR_MASK 0x00000fff 262 PMCH = 0x6f, 263 EPHYAR = 0x80, 264 #define EPHYAR_FLAG 0x80000000 265 #define EPHYAR_WRITE_CMD 0x80000000 266 #define EPHYAR_REG_MASK 0x1f 267 #define EPHYAR_REG_SHIFT 16 268 #define EPHYAR_DATA_MASK 0xffff 269 DLLPR = 0xd0, 270 #define PFM_EN (1 << 6) 271 #define TX_10M_PS_EN (1 << 7) 272 DBG_REG = 0xd1, 273 #define FIX_NAK_1 (1 << 4) 274 #define FIX_NAK_2 (1 << 3) 275 TWSI = 0xd2, 276 MCU = 0xd3, 277 #define NOW_IS_OOB (1 << 7) 278 #define TX_EMPTY (1 << 5) 279 #define RX_EMPTY (1 << 4) 280 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 281 #define EN_NDP (1 << 3) 282 #define EN_OOB_RESET (1 << 2) 283 #define LINK_LIST_RDY (1 << 1) 284 EFUSEAR = 0xdc, 285 #define EFUSEAR_FLAG 0x80000000 286 #define EFUSEAR_WRITE_CMD 0x80000000 287 #define EFUSEAR_READ_CMD 0x00000000 288 #define EFUSEAR_REG_MASK 0x03ff 289 #define EFUSEAR_REG_SHIFT 8 290 #define EFUSEAR_DATA_MASK 0xff 291 MISC_1 = 0xf2, 292 #define PFM_D3COLD_EN (1 << 6) 293 }; 294 295 enum rtl8168_registers { 296 LED_FREQ = 0x1a, 297 EEE_LED = 0x1b, 298 ERIDR = 0x70, 299 ERIAR = 0x74, 300 #define ERIAR_FLAG 0x80000000 301 #define ERIAR_WRITE_CMD 0x80000000 302 #define ERIAR_READ_CMD 0x00000000 303 #define ERIAR_ADDR_BYTE_ALIGN 4 304 #define ERIAR_TYPE_SHIFT 16 305 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_MASK_SHIFT 12 310 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 315 EPHY_RXER_NUM = 0x7c, 316 OCPDR = 0xb0, /* OCP GPHY access */ 317 #define OCPDR_WRITE_CMD 0x80000000 318 #define OCPDR_READ_CMD 0x00000000 319 #define OCPDR_REG_MASK 0x7f 320 #define OCPDR_GPHY_REG_SHIFT 16 321 #define OCPDR_DATA_MASK 0xffff 322 OCPAR = 0xb4, 323 #define OCPAR_FLAG 0x80000000 324 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 325 #define OCPAR_GPHY_READ_CMD 0x0000f060 326 GPHY_OCP = 0xb8, 327 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 328 MISC = 0xf0, /* 8168e only. */ 329 #define TXPLA_RST (1 << 29) 330 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 331 #define PWM_EN (1 << 22) 332 #define RXDV_GATED_EN (1 << 19) 333 #define EARLY_TALLY_EN (1 << 16) 334 }; 335 336 enum rtl8125_registers { 337 IntrMask_8125 = 0x38, 338 IntrStatus_8125 = 0x3c, 339 TxPoll_8125 = 0x90, 340 MAC0_BKP = 0x19e0, 341 EEE_TXIDLE_TIMER_8125 = 0x6048, 342 }; 343 344 #define RX_VLAN_INNER_8125 BIT(22) 345 #define RX_VLAN_OUTER_8125 BIT(23) 346 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 347 348 #define RX_FETCH_DFLT_8125 (8 << 27) 349 350 enum rtl_register_content { 351 /* InterruptStatusBits */ 352 SYSErr = 0x8000, 353 PCSTimeout = 0x4000, 354 SWInt = 0x0100, 355 TxDescUnavail = 0x0080, 356 RxFIFOOver = 0x0040, 357 LinkChg = 0x0020, 358 RxOverflow = 0x0010, 359 TxErr = 0x0008, 360 TxOK = 0x0004, 361 RxErr = 0x0002, 362 RxOK = 0x0001, 363 364 /* RxStatusDesc */ 365 RxRWT = (1 << 22), 366 RxRES = (1 << 21), 367 RxRUNT = (1 << 20), 368 RxCRC = (1 << 19), 369 370 /* ChipCmdBits */ 371 StopReq = 0x80, 372 CmdReset = 0x10, 373 CmdRxEnb = 0x08, 374 CmdTxEnb = 0x04, 375 RxBufEmpty = 0x01, 376 377 /* TXPoll register p.5 */ 378 HPQ = 0x80, /* Poll cmd on the high prio queue */ 379 NPQ = 0x40, /* Poll cmd on the low prio queue */ 380 FSWInt = 0x01, /* Forced software interrupt */ 381 382 /* Cfg9346Bits */ 383 Cfg9346_Lock = 0x00, 384 Cfg9346_Unlock = 0xc0, 385 386 /* rx_mode_bits */ 387 AcceptErr = 0x20, 388 AcceptRunt = 0x10, 389 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 390 AcceptBroadcast = 0x08, 391 AcceptMulticast = 0x04, 392 AcceptMyPhys = 0x02, 393 AcceptAllPhys = 0x01, 394 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 395 #define RX_CONFIG_ACCEPT_MASK 0x3f 396 397 /* TxConfigBits */ 398 TxInterFrameGapShift = 24, 399 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 400 401 /* Config1 register p.24 */ 402 LEDS1 = (1 << 7), 403 LEDS0 = (1 << 6), 404 Speed_down = (1 << 4), 405 MEMMAP = (1 << 3), 406 IOMAP = (1 << 2), 407 VPD = (1 << 1), 408 PMEnable = (1 << 0), /* Power Management Enable */ 409 410 /* Config2 register p. 25 */ 411 ClkReqEn = (1 << 7), /* Clock Request Enable */ 412 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 413 PCI_Clock_66MHz = 0x01, 414 PCI_Clock_33MHz = 0x00, 415 416 /* Config3 register p.25 */ 417 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 418 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 419 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 420 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 421 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 422 423 /* Config4 register */ 424 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 425 426 /* Config5 register p.27 */ 427 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 428 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 429 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 430 Spi_en = (1 << 3), 431 LanWake = (1 << 1), /* LanWake enable/disable */ 432 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 433 ASPM_en = (1 << 0), /* ASPM enable */ 434 435 /* CPlusCmd p.31 */ 436 EnableBist = (1 << 15), // 8168 8101 437 Mac_dbgo_oe = (1 << 14), // 8168 8101 438 EnAnaPLL = (1 << 14), // 8169 439 Normal_mode = (1 << 13), // unused 440 Force_half_dup = (1 << 12), // 8168 8101 441 Force_rxflow_en = (1 << 11), // 8168 8101 442 Force_txflow_en = (1 << 10), // 8168 8101 443 Cxpl_dbg_sel = (1 << 9), // 8168 8101 444 ASF = (1 << 8), // 8168 8101 445 PktCntrDisable = (1 << 7), // 8168 8101 446 Mac_dbgo_sel = 0x001c, // 8168 447 RxVlan = (1 << 6), 448 RxChkSum = (1 << 5), 449 PCIDAC = (1 << 4), 450 PCIMulRW = (1 << 3), 451 #define INTT_MASK GENMASK(1, 0) 452 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 453 454 /* rtl8169_PHYstatus */ 455 TBI_Enable = 0x80, 456 TxFlowCtrl = 0x40, 457 RxFlowCtrl = 0x20, 458 _1000bpsF = 0x10, 459 _100bps = 0x08, 460 _10bps = 0x04, 461 LinkStatus = 0x02, 462 FullDup = 0x01, 463 464 /* ResetCounterCommand */ 465 CounterReset = 0x1, 466 467 /* DumpCounterCommand */ 468 CounterDump = 0x8, 469 470 /* magic enable v2 */ 471 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 472 }; 473 474 enum rtl_desc_bit { 475 /* First doubleword. */ 476 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 477 RingEnd = (1 << 30), /* End of descriptor ring */ 478 FirstFrag = (1 << 29), /* First segment of a packet */ 479 LastFrag = (1 << 28), /* Final segment of a packet */ 480 }; 481 482 /* Generic case. */ 483 enum rtl_tx_desc_bit { 484 /* First doubleword. */ 485 TD_LSO = (1 << 27), /* Large Send Offload */ 486 #define TD_MSS_MAX 0x07ffu /* MSS value */ 487 488 /* Second doubleword. */ 489 TxVlanTag = (1 << 17), /* Add VLAN tag */ 490 }; 491 492 /* 8169, 8168b and 810x except 8102e. */ 493 enum rtl_tx_desc_bit_0 { 494 /* First doubleword. */ 495 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 496 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 497 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 498 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 499 }; 500 501 /* 8102e, 8168c and beyond. */ 502 enum rtl_tx_desc_bit_1 { 503 /* First doubleword. */ 504 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 505 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 506 #define GTTCPHO_SHIFT 18 507 #define GTTCPHO_MAX 0x7f 508 509 /* Second doubleword. */ 510 #define TCPHO_SHIFT 18 511 #define TCPHO_MAX 0x3ff 512 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 513 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 514 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 515 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 516 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 517 }; 518 519 enum rtl_rx_desc_bit { 520 /* Rx private */ 521 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 522 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 523 524 #define RxProtoUDP (PID1) 525 #define RxProtoTCP (PID0) 526 #define RxProtoIP (PID1 | PID0) 527 #define RxProtoMask RxProtoIP 528 529 IPFail = (1 << 16), /* IP checksum failed */ 530 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 531 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 532 RxVlanTag = (1 << 16), /* VLAN tag available */ 533 }; 534 535 #define RTL_GSO_MAX_SIZE_V1 32000 536 #define RTL_GSO_MAX_SEGS_V1 24 537 #define RTL_GSO_MAX_SIZE_V2 64000 538 #define RTL_GSO_MAX_SEGS_V2 64 539 540 struct TxDesc { 541 __le32 opts1; 542 __le32 opts2; 543 __le64 addr; 544 }; 545 546 struct RxDesc { 547 __le32 opts1; 548 __le32 opts2; 549 __le64 addr; 550 }; 551 552 struct ring_info { 553 struct sk_buff *skb; 554 u32 len; 555 }; 556 557 struct rtl8169_counters { 558 __le64 tx_packets; 559 __le64 rx_packets; 560 __le64 tx_errors; 561 __le32 rx_errors; 562 __le16 rx_missed; 563 __le16 align_errors; 564 __le32 tx_one_collision; 565 __le32 tx_multi_collision; 566 __le64 rx_unicast; 567 __le64 rx_broadcast; 568 __le32 rx_multicast; 569 __le16 tx_aborted; 570 __le16 tx_underun; 571 }; 572 573 struct rtl8169_tc_offsets { 574 bool inited; 575 __le64 tx_errors; 576 __le32 tx_multi_collision; 577 __le16 tx_aborted; 578 __le16 rx_missed; 579 }; 580 581 enum rtl_flag { 582 RTL_FLAG_TASK_ENABLED = 0, 583 RTL_FLAG_TASK_RESET_PENDING, 584 RTL_FLAG_MAX 585 }; 586 587 struct rtl8169_stats { 588 u64 packets; 589 u64 bytes; 590 struct u64_stats_sync syncp; 591 }; 592 593 struct rtl8169_private { 594 void __iomem *mmio_addr; /* memory map physical address */ 595 struct pci_dev *pci_dev; 596 struct net_device *dev; 597 struct phy_device *phydev; 598 struct napi_struct napi; 599 enum mac_version mac_version; 600 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 601 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 602 u32 dirty_tx; 603 struct rtl8169_stats rx_stats; 604 struct rtl8169_stats tx_stats; 605 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 606 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 607 dma_addr_t TxPhyAddr; 608 dma_addr_t RxPhyAddr; 609 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 610 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 611 u16 cp_cmd; 612 u32 irq_mask; 613 struct clk *clk; 614 615 struct { 616 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 617 struct work_struct work; 618 } wk; 619 620 unsigned irq_enabled:1; 621 unsigned supports_gmii:1; 622 unsigned aspm_manageable:1; 623 dma_addr_t counters_phys_addr; 624 struct rtl8169_counters *counters; 625 struct rtl8169_tc_offsets tc_offset; 626 u32 saved_wolopts; 627 int eee_adv; 628 629 const char *fw_name; 630 struct rtl_fw *rtl_fw; 631 632 u32 ocp_base; 633 }; 634 635 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 636 637 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 638 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 639 MODULE_SOFTDEP("pre: realtek"); 640 MODULE_LICENSE("GPL"); 641 MODULE_FIRMWARE(FIRMWARE_8168D_1); 642 MODULE_FIRMWARE(FIRMWARE_8168D_2); 643 MODULE_FIRMWARE(FIRMWARE_8168E_1); 644 MODULE_FIRMWARE(FIRMWARE_8168E_2); 645 MODULE_FIRMWARE(FIRMWARE_8168E_3); 646 MODULE_FIRMWARE(FIRMWARE_8105E_1); 647 MODULE_FIRMWARE(FIRMWARE_8168F_1); 648 MODULE_FIRMWARE(FIRMWARE_8168F_2); 649 MODULE_FIRMWARE(FIRMWARE_8402_1); 650 MODULE_FIRMWARE(FIRMWARE_8411_1); 651 MODULE_FIRMWARE(FIRMWARE_8411_2); 652 MODULE_FIRMWARE(FIRMWARE_8106E_1); 653 MODULE_FIRMWARE(FIRMWARE_8106E_2); 654 MODULE_FIRMWARE(FIRMWARE_8168G_2); 655 MODULE_FIRMWARE(FIRMWARE_8168G_3); 656 MODULE_FIRMWARE(FIRMWARE_8168H_1); 657 MODULE_FIRMWARE(FIRMWARE_8168H_2); 658 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 659 MODULE_FIRMWARE(FIRMWARE_8107E_1); 660 MODULE_FIRMWARE(FIRMWARE_8107E_2); 661 MODULE_FIRMWARE(FIRMWARE_8125A_3); 662 MODULE_FIRMWARE(FIRMWARE_8125B_2); 663 664 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 665 { 666 return &tp->pci_dev->dev; 667 } 668 669 static void rtl_lock_config_regs(struct rtl8169_private *tp) 670 { 671 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 672 } 673 674 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 675 { 676 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 677 } 678 679 static void rtl_pci_commit(struct rtl8169_private *tp) 680 { 681 /* Read an arbitrary register to commit a preceding PCI write */ 682 RTL_R8(tp, ChipCmd); 683 } 684 685 static bool rtl_is_8125(struct rtl8169_private *tp) 686 { 687 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 688 } 689 690 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 691 { 692 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 693 tp->mac_version != RTL_GIGA_MAC_VER_39 && 694 tp->mac_version <= RTL_GIGA_MAC_VER_52; 695 } 696 697 static bool rtl_supports_eee(struct rtl8169_private *tp) 698 { 699 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 700 tp->mac_version != RTL_GIGA_MAC_VER_37 && 701 tp->mac_version != RTL_GIGA_MAC_VER_39; 702 } 703 704 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 705 { 706 int i; 707 708 for (i = 0; i < ETH_ALEN; i++) 709 mac[i] = RTL_R8(tp, reg + i); 710 } 711 712 struct rtl_cond { 713 bool (*check)(struct rtl8169_private *); 714 const char *msg; 715 }; 716 717 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 718 unsigned long usecs, int n, bool high) 719 { 720 int i; 721 722 for (i = 0; i < n; i++) { 723 if (c->check(tp) == high) 724 return true; 725 fsleep(usecs); 726 } 727 728 if (net_ratelimit()) 729 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 730 c->msg, !high, n, usecs); 731 return false; 732 } 733 734 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 735 const struct rtl_cond *c, 736 unsigned long d, int n) 737 { 738 return rtl_loop_wait(tp, c, d, n, true); 739 } 740 741 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 742 const struct rtl_cond *c, 743 unsigned long d, int n) 744 { 745 return rtl_loop_wait(tp, c, d, n, false); 746 } 747 748 #define DECLARE_RTL_COND(name) \ 749 static bool name ## _check(struct rtl8169_private *); \ 750 \ 751 static const struct rtl_cond name = { \ 752 .check = name ## _check, \ 753 .msg = #name \ 754 }; \ 755 \ 756 static bool name ## _check(struct rtl8169_private *tp) 757 758 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 759 { 760 if (reg & 0xffff0001) { 761 if (net_ratelimit()) 762 netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg); 763 return true; 764 } 765 return false; 766 } 767 768 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 769 { 770 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 771 } 772 773 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 774 { 775 if (rtl_ocp_reg_failure(tp, reg)) 776 return; 777 778 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 779 780 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 781 } 782 783 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 784 { 785 if (rtl_ocp_reg_failure(tp, reg)) 786 return 0; 787 788 RTL_W32(tp, GPHY_OCP, reg << 15); 789 790 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 791 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 792 } 793 794 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 795 { 796 if (rtl_ocp_reg_failure(tp, reg)) 797 return; 798 799 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 800 } 801 802 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 803 { 804 if (rtl_ocp_reg_failure(tp, reg)) 805 return 0; 806 807 RTL_W32(tp, OCPDR, reg << 15); 808 809 return RTL_R32(tp, OCPDR); 810 } 811 812 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 813 u16 set) 814 { 815 u16 data = r8168_mac_ocp_read(tp, reg); 816 817 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 818 } 819 820 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 821 { 822 if (reg == 0x1f) { 823 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 824 return; 825 } 826 827 if (tp->ocp_base != OCP_STD_PHY_BASE) 828 reg -= 0x10; 829 830 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 831 } 832 833 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 834 { 835 if (reg == 0x1f) 836 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 837 838 if (tp->ocp_base != OCP_STD_PHY_BASE) 839 reg -= 0x10; 840 841 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 842 } 843 844 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 845 { 846 if (reg == 0x1f) { 847 tp->ocp_base = value << 4; 848 return; 849 } 850 851 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 852 } 853 854 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 855 { 856 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 857 } 858 859 DECLARE_RTL_COND(rtl_phyar_cond) 860 { 861 return RTL_R32(tp, PHYAR) & 0x80000000; 862 } 863 864 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 865 { 866 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 867 868 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 869 /* 870 * According to hardware specs a 20us delay is required after write 871 * complete indication, but before sending next command. 872 */ 873 udelay(20); 874 } 875 876 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 877 { 878 int value; 879 880 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 881 882 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 883 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 884 885 /* 886 * According to hardware specs a 20us delay is required after read 887 * complete indication, but before sending next command. 888 */ 889 udelay(20); 890 891 return value; 892 } 893 894 DECLARE_RTL_COND(rtl_ocpar_cond) 895 { 896 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 897 } 898 899 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 900 { 901 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 902 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 903 RTL_W32(tp, EPHY_RXER_NUM, 0); 904 905 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 906 } 907 908 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 909 { 910 r8168dp_1_mdio_access(tp, reg, 911 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 912 } 913 914 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 915 { 916 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 917 918 mdelay(1); 919 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 920 RTL_W32(tp, EPHY_RXER_NUM, 0); 921 922 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 923 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 924 } 925 926 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 927 928 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 929 { 930 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 931 } 932 933 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 934 { 935 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 936 } 937 938 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 939 { 940 r8168dp_2_mdio_start(tp); 941 942 r8169_mdio_write(tp, reg, value); 943 944 r8168dp_2_mdio_stop(tp); 945 } 946 947 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 948 { 949 int value; 950 951 /* Work around issue with chip reporting wrong PHY ID */ 952 if (reg == MII_PHYSID2) 953 return 0xc912; 954 955 r8168dp_2_mdio_start(tp); 956 957 value = r8169_mdio_read(tp, reg); 958 959 r8168dp_2_mdio_stop(tp); 960 961 return value; 962 } 963 964 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 965 { 966 switch (tp->mac_version) { 967 case RTL_GIGA_MAC_VER_27: 968 r8168dp_1_mdio_write(tp, location, val); 969 break; 970 case RTL_GIGA_MAC_VER_28: 971 case RTL_GIGA_MAC_VER_31: 972 r8168dp_2_mdio_write(tp, location, val); 973 break; 974 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 975 r8168g_mdio_write(tp, location, val); 976 break; 977 default: 978 r8169_mdio_write(tp, location, val); 979 break; 980 } 981 } 982 983 static int rtl_readphy(struct rtl8169_private *tp, int location) 984 { 985 switch (tp->mac_version) { 986 case RTL_GIGA_MAC_VER_27: 987 return r8168dp_1_mdio_read(tp, location); 988 case RTL_GIGA_MAC_VER_28: 989 case RTL_GIGA_MAC_VER_31: 990 return r8168dp_2_mdio_read(tp, location); 991 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 992 return r8168g_mdio_read(tp, location); 993 default: 994 return r8169_mdio_read(tp, location); 995 } 996 } 997 998 DECLARE_RTL_COND(rtl_ephyar_cond) 999 { 1000 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1001 } 1002 1003 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1004 { 1005 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1006 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1007 1008 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1009 1010 udelay(10); 1011 } 1012 1013 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1014 { 1015 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1016 1017 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1018 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1019 } 1020 1021 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 1022 { 1023 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 1024 if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB) 1025 *cmd |= 0x7f0 << 18; 1026 } 1027 1028 DECLARE_RTL_COND(rtl_eriar_cond) 1029 { 1030 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1031 } 1032 1033 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1034 u32 val, int type) 1035 { 1036 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 1037 1038 BUG_ON((addr & 3) || (mask == 0)); 1039 RTL_W32(tp, ERIDR, val); 1040 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1041 RTL_W32(tp, ERIAR, cmd); 1042 1043 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1044 } 1045 1046 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1047 u32 val) 1048 { 1049 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1050 } 1051 1052 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1053 { 1054 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 1055 1056 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1057 RTL_W32(tp, ERIAR, cmd); 1058 1059 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1060 RTL_R32(tp, ERIDR) : ~0; 1061 } 1062 1063 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1064 { 1065 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1066 } 1067 1068 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 1069 { 1070 u32 val = rtl_eri_read(tp, addr); 1071 1072 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1073 } 1074 1075 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1076 { 1077 rtl_w0w1_eri(tp, addr, p, 0); 1078 } 1079 1080 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1081 { 1082 rtl_w0w1_eri(tp, addr, 0, m); 1083 } 1084 1085 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1086 { 1087 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1088 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1089 RTL_R32(tp, OCPDR) : ~0; 1090 } 1091 1092 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1093 { 1094 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1095 } 1096 1097 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1098 u32 data) 1099 { 1100 RTL_W32(tp, OCPDR, data); 1101 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1102 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1103 } 1104 1105 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1106 u32 data) 1107 { 1108 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1109 data, ERIAR_OOB); 1110 } 1111 1112 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1113 { 1114 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1115 1116 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1117 } 1118 1119 #define OOB_CMD_RESET 0x00 1120 #define OOB_CMD_DRIVER_START 0x05 1121 #define OOB_CMD_DRIVER_STOP 0x06 1122 1123 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1124 { 1125 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1126 } 1127 1128 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1129 { 1130 u16 reg; 1131 1132 reg = rtl8168_get_ocp_reg(tp); 1133 1134 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1135 } 1136 1137 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1138 { 1139 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1140 } 1141 1142 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1143 { 1144 return RTL_R8(tp, IBISR0) & 0x20; 1145 } 1146 1147 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1148 { 1149 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1150 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1151 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1152 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1153 } 1154 1155 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1156 { 1157 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1158 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1159 } 1160 1161 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1162 { 1163 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1164 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1165 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1166 } 1167 1168 static void rtl8168_driver_start(struct rtl8169_private *tp) 1169 { 1170 switch (tp->mac_version) { 1171 case RTL_GIGA_MAC_VER_27: 1172 case RTL_GIGA_MAC_VER_28: 1173 case RTL_GIGA_MAC_VER_31: 1174 rtl8168dp_driver_start(tp); 1175 break; 1176 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1177 rtl8168ep_driver_start(tp); 1178 break; 1179 default: 1180 BUG(); 1181 break; 1182 } 1183 } 1184 1185 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1186 { 1187 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1188 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1189 } 1190 1191 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1192 { 1193 rtl8168ep_stop_cmac(tp); 1194 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1195 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1196 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1197 } 1198 1199 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1200 { 1201 switch (tp->mac_version) { 1202 case RTL_GIGA_MAC_VER_27: 1203 case RTL_GIGA_MAC_VER_28: 1204 case RTL_GIGA_MAC_VER_31: 1205 rtl8168dp_driver_stop(tp); 1206 break; 1207 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1208 rtl8168ep_driver_stop(tp); 1209 break; 1210 default: 1211 BUG(); 1212 break; 1213 } 1214 } 1215 1216 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1217 { 1218 u16 reg = rtl8168_get_ocp_reg(tp); 1219 1220 return !!(r8168dp_ocp_read(tp, reg) & 0x00008000); 1221 } 1222 1223 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1224 { 1225 return r8168ep_ocp_read(tp, 0x128) & 0x00000001; 1226 } 1227 1228 static bool r8168_check_dash(struct rtl8169_private *tp) 1229 { 1230 switch (tp->mac_version) { 1231 case RTL_GIGA_MAC_VER_27: 1232 case RTL_GIGA_MAC_VER_28: 1233 case RTL_GIGA_MAC_VER_31: 1234 return r8168dp_check_dash(tp); 1235 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1236 return r8168ep_check_dash(tp); 1237 default: 1238 return false; 1239 } 1240 } 1241 1242 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1243 { 1244 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1245 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1246 } 1247 1248 DECLARE_RTL_COND(rtl_efusear_cond) 1249 { 1250 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1251 } 1252 1253 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1254 { 1255 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1256 1257 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1258 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1259 } 1260 1261 static u32 rtl_get_events(struct rtl8169_private *tp) 1262 { 1263 if (rtl_is_8125(tp)) 1264 return RTL_R32(tp, IntrStatus_8125); 1265 else 1266 return RTL_R16(tp, IntrStatus); 1267 } 1268 1269 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1270 { 1271 if (rtl_is_8125(tp)) 1272 RTL_W32(tp, IntrStatus_8125, bits); 1273 else 1274 RTL_W16(tp, IntrStatus, bits); 1275 } 1276 1277 static void rtl_irq_disable(struct rtl8169_private *tp) 1278 { 1279 if (rtl_is_8125(tp)) 1280 RTL_W32(tp, IntrMask_8125, 0); 1281 else 1282 RTL_W16(tp, IntrMask, 0); 1283 tp->irq_enabled = 0; 1284 } 1285 1286 static void rtl_irq_enable(struct rtl8169_private *tp) 1287 { 1288 tp->irq_enabled = 1; 1289 if (rtl_is_8125(tp)) 1290 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1291 else 1292 RTL_W16(tp, IntrMask, tp->irq_mask); 1293 } 1294 1295 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1296 { 1297 rtl_irq_disable(tp); 1298 rtl_ack_events(tp, 0xffffffff); 1299 rtl_pci_commit(tp); 1300 } 1301 1302 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1303 { 1304 struct phy_device *phydev = tp->phydev; 1305 1306 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1307 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1308 if (phydev->speed == SPEED_1000) { 1309 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1310 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1311 } else if (phydev->speed == SPEED_100) { 1312 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1313 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1314 } else { 1315 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1316 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1317 } 1318 rtl_reset_packet_filter(tp); 1319 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1320 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1321 if (phydev->speed == SPEED_1000) { 1322 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1323 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1324 } else { 1325 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1326 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1327 } 1328 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1329 if (phydev->speed == SPEED_10) { 1330 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1331 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1332 } else { 1333 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1334 } 1335 } 1336 } 1337 1338 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1339 1340 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1341 { 1342 struct rtl8169_private *tp = netdev_priv(dev); 1343 1344 wol->supported = WAKE_ANY; 1345 wol->wolopts = tp->saved_wolopts; 1346 } 1347 1348 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1349 { 1350 static const struct { 1351 u32 opt; 1352 u16 reg; 1353 u8 mask; 1354 } cfg[] = { 1355 { WAKE_PHY, Config3, LinkUp }, 1356 { WAKE_UCAST, Config5, UWF }, 1357 { WAKE_BCAST, Config5, BWF }, 1358 { WAKE_MCAST, Config5, MWF }, 1359 { WAKE_ANY, Config5, LanWake }, 1360 { WAKE_MAGIC, Config3, MagicPacket } 1361 }; 1362 unsigned int i, tmp = ARRAY_SIZE(cfg); 1363 u8 options; 1364 1365 rtl_unlock_config_regs(tp); 1366 1367 if (rtl_is_8168evl_up(tp)) { 1368 tmp--; 1369 if (wolopts & WAKE_MAGIC) 1370 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1371 else 1372 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1373 } else if (rtl_is_8125(tp)) { 1374 tmp--; 1375 if (wolopts & WAKE_MAGIC) 1376 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1377 else 1378 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1379 } 1380 1381 for (i = 0; i < tmp; i++) { 1382 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1383 if (wolopts & cfg[i].opt) 1384 options |= cfg[i].mask; 1385 RTL_W8(tp, cfg[i].reg, options); 1386 } 1387 1388 switch (tp->mac_version) { 1389 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1390 options = RTL_R8(tp, Config1) & ~PMEnable; 1391 if (wolopts) 1392 options |= PMEnable; 1393 RTL_W8(tp, Config1, options); 1394 break; 1395 case RTL_GIGA_MAC_VER_34: 1396 case RTL_GIGA_MAC_VER_37: 1397 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1398 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1399 if (wolopts) 1400 options |= PME_SIGNAL; 1401 RTL_W8(tp, Config2, options); 1402 break; 1403 default: 1404 break; 1405 } 1406 1407 rtl_lock_config_regs(tp); 1408 1409 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1410 tp->dev->wol_enabled = wolopts ? 1 : 0; 1411 } 1412 1413 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1414 { 1415 struct rtl8169_private *tp = netdev_priv(dev); 1416 1417 if (wol->wolopts & ~WAKE_ANY) 1418 return -EINVAL; 1419 1420 tp->saved_wolopts = wol->wolopts; 1421 __rtl8169_set_wol(tp, tp->saved_wolopts); 1422 1423 return 0; 1424 } 1425 1426 static void rtl8169_get_drvinfo(struct net_device *dev, 1427 struct ethtool_drvinfo *info) 1428 { 1429 struct rtl8169_private *tp = netdev_priv(dev); 1430 struct rtl_fw *rtl_fw = tp->rtl_fw; 1431 1432 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1433 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1434 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1435 if (rtl_fw) 1436 strlcpy(info->fw_version, rtl_fw->version, 1437 sizeof(info->fw_version)); 1438 } 1439 1440 static int rtl8169_get_regs_len(struct net_device *dev) 1441 { 1442 return R8169_REGS_SIZE; 1443 } 1444 1445 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1446 netdev_features_t features) 1447 { 1448 struct rtl8169_private *tp = netdev_priv(dev); 1449 1450 if (dev->mtu > TD_MSS_MAX) 1451 features &= ~NETIF_F_ALL_TSO; 1452 1453 if (dev->mtu > ETH_DATA_LEN && 1454 tp->mac_version > RTL_GIGA_MAC_VER_06) 1455 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1456 1457 return features; 1458 } 1459 1460 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1461 netdev_features_t features) 1462 { 1463 u32 rx_config = RTL_R32(tp, RxConfig); 1464 1465 if (features & NETIF_F_RXALL) 1466 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1467 else 1468 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1469 1470 if (rtl_is_8125(tp)) { 1471 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1472 rx_config |= RX_VLAN_8125; 1473 else 1474 rx_config &= ~RX_VLAN_8125; 1475 } 1476 1477 RTL_W32(tp, RxConfig, rx_config); 1478 } 1479 1480 static int rtl8169_set_features(struct net_device *dev, 1481 netdev_features_t features) 1482 { 1483 struct rtl8169_private *tp = netdev_priv(dev); 1484 1485 rtl_set_rx_config_features(tp, features); 1486 1487 if (features & NETIF_F_RXCSUM) 1488 tp->cp_cmd |= RxChkSum; 1489 else 1490 tp->cp_cmd &= ~RxChkSum; 1491 1492 if (!rtl_is_8125(tp)) { 1493 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1494 tp->cp_cmd |= RxVlan; 1495 else 1496 tp->cp_cmd &= ~RxVlan; 1497 } 1498 1499 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1500 rtl_pci_commit(tp); 1501 1502 return 0; 1503 } 1504 1505 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1506 { 1507 return (skb_vlan_tag_present(skb)) ? 1508 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1509 } 1510 1511 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1512 { 1513 u32 opts2 = le32_to_cpu(desc->opts2); 1514 1515 if (opts2 & RxVlanTag) 1516 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1517 } 1518 1519 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1520 void *p) 1521 { 1522 struct rtl8169_private *tp = netdev_priv(dev); 1523 u32 __iomem *data = tp->mmio_addr; 1524 u32 *dw = p; 1525 int i; 1526 1527 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1528 memcpy_fromio(dw++, data++, 4); 1529 } 1530 1531 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1532 "tx_packets", 1533 "rx_packets", 1534 "tx_errors", 1535 "rx_errors", 1536 "rx_missed", 1537 "align_errors", 1538 "tx_single_collisions", 1539 "tx_multi_collisions", 1540 "unicast", 1541 "broadcast", 1542 "multicast", 1543 "tx_aborted", 1544 "tx_underrun", 1545 }; 1546 1547 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1548 { 1549 switch (sset) { 1550 case ETH_SS_STATS: 1551 return ARRAY_SIZE(rtl8169_gstrings); 1552 default: 1553 return -EOPNOTSUPP; 1554 } 1555 } 1556 1557 DECLARE_RTL_COND(rtl_counters_cond) 1558 { 1559 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1560 } 1561 1562 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1563 { 1564 dma_addr_t paddr = tp->counters_phys_addr; 1565 u32 cmd; 1566 1567 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1568 rtl_pci_commit(tp); 1569 cmd = (u64)paddr & DMA_BIT_MASK(32); 1570 RTL_W32(tp, CounterAddrLow, cmd); 1571 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1572 1573 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1574 } 1575 1576 static void rtl8169_reset_counters(struct rtl8169_private *tp) 1577 { 1578 /* 1579 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1580 * tally counters. 1581 */ 1582 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) 1583 rtl8169_do_counters(tp, CounterReset); 1584 } 1585 1586 static void rtl8169_update_counters(struct rtl8169_private *tp) 1587 { 1588 u8 val = RTL_R8(tp, ChipCmd); 1589 1590 /* 1591 * Some chips are unable to dump tally counters when the receiver 1592 * is disabled. If 0xff chip may be in a PCI power-save state. 1593 */ 1594 if (val & CmdRxEnb && val != 0xff) 1595 rtl8169_do_counters(tp, CounterDump); 1596 } 1597 1598 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1599 { 1600 struct rtl8169_counters *counters = tp->counters; 1601 1602 /* 1603 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1604 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1605 * reset by a power cycle, while the counter values collected by the 1606 * driver are reset at every driver unload/load cycle. 1607 * 1608 * To make sure the HW values returned by @get_stats64 match the SW 1609 * values, we collect the initial values at first open(*) and use them 1610 * as offsets to normalize the values returned by @get_stats64. 1611 * 1612 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1613 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1614 * set at open time by rtl_hw_start. 1615 */ 1616 1617 if (tp->tc_offset.inited) 1618 return; 1619 1620 rtl8169_reset_counters(tp); 1621 rtl8169_update_counters(tp); 1622 1623 tp->tc_offset.tx_errors = counters->tx_errors; 1624 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1625 tp->tc_offset.tx_aborted = counters->tx_aborted; 1626 tp->tc_offset.rx_missed = counters->rx_missed; 1627 tp->tc_offset.inited = true; 1628 } 1629 1630 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1631 struct ethtool_stats *stats, u64 *data) 1632 { 1633 struct rtl8169_private *tp = netdev_priv(dev); 1634 struct rtl8169_counters *counters; 1635 1636 counters = tp->counters; 1637 rtl8169_update_counters(tp); 1638 1639 data[0] = le64_to_cpu(counters->tx_packets); 1640 data[1] = le64_to_cpu(counters->rx_packets); 1641 data[2] = le64_to_cpu(counters->tx_errors); 1642 data[3] = le32_to_cpu(counters->rx_errors); 1643 data[4] = le16_to_cpu(counters->rx_missed); 1644 data[5] = le16_to_cpu(counters->align_errors); 1645 data[6] = le32_to_cpu(counters->tx_one_collision); 1646 data[7] = le32_to_cpu(counters->tx_multi_collision); 1647 data[8] = le64_to_cpu(counters->rx_unicast); 1648 data[9] = le64_to_cpu(counters->rx_broadcast); 1649 data[10] = le32_to_cpu(counters->rx_multicast); 1650 data[11] = le16_to_cpu(counters->tx_aborted); 1651 data[12] = le16_to_cpu(counters->tx_underun); 1652 } 1653 1654 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1655 { 1656 switch(stringset) { 1657 case ETH_SS_STATS: 1658 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1659 break; 1660 } 1661 } 1662 1663 /* 1664 * Interrupt coalescing 1665 * 1666 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1667 * > 8169, 8168 and 810x line of chipsets 1668 * 1669 * 8169, 8168, and 8136(810x) serial chipsets support it. 1670 * 1671 * > 2 - the Tx timer unit at gigabit speed 1672 * 1673 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1674 * (0xe0) bit 1 and bit 0. 1675 * 1676 * For 8169 1677 * bit[1:0] \ speed 1000M 100M 10M 1678 * 0 0 320ns 2.56us 40.96us 1679 * 0 1 2.56us 20.48us 327.7us 1680 * 1 0 5.12us 40.96us 655.4us 1681 * 1 1 10.24us 81.92us 1.31ms 1682 * 1683 * For the other 1684 * bit[1:0] \ speed 1000M 100M 10M 1685 * 0 0 5us 2.56us 40.96us 1686 * 0 1 40us 20.48us 327.7us 1687 * 1 0 80us 40.96us 655.4us 1688 * 1 1 160us 81.92us 1.31ms 1689 */ 1690 1691 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1692 struct rtl_coalesce_info { 1693 u32 speed; 1694 u32 scale_nsecs[4]; 1695 }; 1696 1697 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1698 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1699 1700 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1701 { SPEED_1000, COALESCE_DELAY(320) }, 1702 { SPEED_100, COALESCE_DELAY(2560) }, 1703 { SPEED_10, COALESCE_DELAY(40960) }, 1704 { 0 }, 1705 }; 1706 1707 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1708 { SPEED_1000, COALESCE_DELAY(5000) }, 1709 { SPEED_100, COALESCE_DELAY(2560) }, 1710 { SPEED_10, COALESCE_DELAY(40960) }, 1711 { 0 }, 1712 }; 1713 #undef COALESCE_DELAY 1714 1715 /* get rx/tx scale vector corresponding to current speed */ 1716 static const struct rtl_coalesce_info * 1717 rtl_coalesce_info(struct rtl8169_private *tp) 1718 { 1719 const struct rtl_coalesce_info *ci; 1720 1721 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1722 ci = rtl_coalesce_info_8169; 1723 else 1724 ci = rtl_coalesce_info_8168_8136; 1725 1726 /* if speed is unknown assume highest one */ 1727 if (tp->phydev->speed == SPEED_UNKNOWN) 1728 return ci; 1729 1730 for (; ci->speed; ci++) { 1731 if (tp->phydev->speed == ci->speed) 1732 return ci; 1733 } 1734 1735 return ERR_PTR(-ELNRNG); 1736 } 1737 1738 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1739 { 1740 struct rtl8169_private *tp = netdev_priv(dev); 1741 const struct rtl_coalesce_info *ci; 1742 u32 scale, c_us, c_fr; 1743 u16 intrmit; 1744 1745 if (rtl_is_8125(tp)) 1746 return -EOPNOTSUPP; 1747 1748 memset(ec, 0, sizeof(*ec)); 1749 1750 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1751 ci = rtl_coalesce_info(tp); 1752 if (IS_ERR(ci)) 1753 return PTR_ERR(ci); 1754 1755 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1756 1757 intrmit = RTL_R16(tp, IntrMitigate); 1758 1759 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1760 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1761 1762 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1763 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1764 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1765 1766 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1767 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1768 1769 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1770 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1771 1772 return 0; 1773 } 1774 1775 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1776 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1777 u16 *cp01) 1778 { 1779 const struct rtl_coalesce_info *ci; 1780 u16 i; 1781 1782 ci = rtl_coalesce_info(tp); 1783 if (IS_ERR(ci)) 1784 return PTR_ERR(ci); 1785 1786 for (i = 0; i < 4; i++) { 1787 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1788 *cp01 = i; 1789 return ci->scale_nsecs[i]; 1790 } 1791 } 1792 1793 return -ERANGE; 1794 } 1795 1796 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1797 { 1798 struct rtl8169_private *tp = netdev_priv(dev); 1799 u32 tx_fr = ec->tx_max_coalesced_frames; 1800 u32 rx_fr = ec->rx_max_coalesced_frames; 1801 u32 coal_usec_max, units; 1802 u16 w = 0, cp01 = 0; 1803 int scale; 1804 1805 if (rtl_is_8125(tp)) 1806 return -EOPNOTSUPP; 1807 1808 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1809 return -ERANGE; 1810 1811 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1812 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1813 if (scale < 0) 1814 return scale; 1815 1816 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1817 * not only when usecs=0 because of e.g. the following scenario: 1818 * 1819 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1820 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1821 * - then user does `ethtool -C eth0 rx-usecs 100` 1822 * 1823 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1824 * if we want to ignore rx_frames then it has to be set to 0. 1825 */ 1826 if (rx_fr == 1) 1827 rx_fr = 0; 1828 if (tx_fr == 1) 1829 tx_fr = 0; 1830 1831 /* HW requires time limit to be set if frame limit is set */ 1832 if ((tx_fr && !ec->tx_coalesce_usecs) || 1833 (rx_fr && !ec->rx_coalesce_usecs)) 1834 return -EINVAL; 1835 1836 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1837 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1838 1839 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1840 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1841 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1842 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1843 1844 RTL_W16(tp, IntrMitigate, w); 1845 1846 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1847 if (rtl_is_8168evl_up(tp)) { 1848 if (!rx_fr && !tx_fr) 1849 /* disable packet counter */ 1850 tp->cp_cmd |= PktCntrDisable; 1851 else 1852 tp->cp_cmd &= ~PktCntrDisable; 1853 } 1854 1855 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1856 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1857 rtl_pci_commit(tp); 1858 1859 return 0; 1860 } 1861 1862 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1863 { 1864 struct rtl8169_private *tp = netdev_priv(dev); 1865 1866 if (!rtl_supports_eee(tp)) 1867 return -EOPNOTSUPP; 1868 1869 return phy_ethtool_get_eee(tp->phydev, data); 1870 } 1871 1872 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1873 { 1874 struct rtl8169_private *tp = netdev_priv(dev); 1875 int ret; 1876 1877 if (!rtl_supports_eee(tp)) 1878 return -EOPNOTSUPP; 1879 1880 ret = phy_ethtool_set_eee(tp->phydev, data); 1881 1882 if (!ret) 1883 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1884 MDIO_AN_EEE_ADV); 1885 return ret; 1886 } 1887 1888 static const struct ethtool_ops rtl8169_ethtool_ops = { 1889 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1890 ETHTOOL_COALESCE_MAX_FRAMES, 1891 .get_drvinfo = rtl8169_get_drvinfo, 1892 .get_regs_len = rtl8169_get_regs_len, 1893 .get_link = ethtool_op_get_link, 1894 .get_coalesce = rtl_get_coalesce, 1895 .set_coalesce = rtl_set_coalesce, 1896 .get_regs = rtl8169_get_regs, 1897 .get_wol = rtl8169_get_wol, 1898 .set_wol = rtl8169_set_wol, 1899 .get_strings = rtl8169_get_strings, 1900 .get_sset_count = rtl8169_get_sset_count, 1901 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1902 .get_ts_info = ethtool_op_get_ts_info, 1903 .nway_reset = phy_ethtool_nway_reset, 1904 .get_eee = rtl8169_get_eee, 1905 .set_eee = rtl8169_set_eee, 1906 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1907 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1908 }; 1909 1910 static void rtl_enable_eee(struct rtl8169_private *tp) 1911 { 1912 struct phy_device *phydev = tp->phydev; 1913 int adv; 1914 1915 /* respect EEE advertisement the user may have set */ 1916 if (tp->eee_adv >= 0) 1917 adv = tp->eee_adv; 1918 else 1919 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1920 1921 if (adv >= 0) 1922 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1923 } 1924 1925 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1926 { 1927 /* 1928 * The driver currently handles the 8168Bf and the 8168Be identically 1929 * but they can be identified more specifically through the test below 1930 * if needed: 1931 * 1932 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1933 * 1934 * Same thing for the 8101Eb and the 8101Ec: 1935 * 1936 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1937 */ 1938 static const struct rtl_mac_info { 1939 u16 mask; 1940 u16 val; 1941 enum mac_version ver; 1942 } mac_info[] = { 1943 /* 8125B family. */ 1944 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1945 1946 /* 8125A family. */ 1947 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1948 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1949 1950 /* RTL8117 */ 1951 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1952 1953 /* 8168EP family. */ 1954 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1955 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1956 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1957 1958 /* 8168H family. */ 1959 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1960 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1961 1962 /* 8168G family. */ 1963 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1964 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1965 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1966 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1967 1968 /* 8168F family. */ 1969 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 1970 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 1971 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 1972 1973 /* 8168E family. */ 1974 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 1975 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 1976 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 1977 1978 /* 8168D family. */ 1979 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 1980 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 1981 1982 /* 8168DP family. */ 1983 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 1984 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 1985 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 1986 1987 /* 8168C family. */ 1988 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 1989 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 1990 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 1991 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 1992 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 1993 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 1994 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 1995 1996 /* 8168B family. */ 1997 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 1998 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 1999 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2000 2001 /* 8101 family. */ 2002 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2003 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2004 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2005 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2006 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2007 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2008 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2009 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2010 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2011 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2012 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2013 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2014 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2015 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2016 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2017 /* FIXME: where did these entries come from ? -- FR */ 2018 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2019 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2020 2021 /* 8110 family. */ 2022 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2023 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2024 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2025 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2026 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2027 2028 /* Catch-all */ 2029 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2030 }; 2031 const struct rtl_mac_info *p = mac_info; 2032 enum mac_version ver; 2033 2034 while ((xid & p->mask) != p->val) 2035 p++; 2036 ver = p->ver; 2037 2038 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2039 if (ver == RTL_GIGA_MAC_VER_42) 2040 ver = RTL_GIGA_MAC_VER_43; 2041 else if (ver == RTL_GIGA_MAC_VER_45) 2042 ver = RTL_GIGA_MAC_VER_47; 2043 else if (ver == RTL_GIGA_MAC_VER_46) 2044 ver = RTL_GIGA_MAC_VER_48; 2045 } 2046 2047 return ver; 2048 } 2049 2050 static void rtl_release_firmware(struct rtl8169_private *tp) 2051 { 2052 if (tp->rtl_fw) { 2053 rtl_fw_release_firmware(tp->rtl_fw); 2054 kfree(tp->rtl_fw); 2055 tp->rtl_fw = NULL; 2056 } 2057 } 2058 2059 void r8169_apply_firmware(struct rtl8169_private *tp) 2060 { 2061 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2062 if (tp->rtl_fw) { 2063 rtl_fw_write_firmware(tp, tp->rtl_fw); 2064 /* At least one firmware doesn't reset tp->ocp_base. */ 2065 tp->ocp_base = OCP_STD_PHY_BASE; 2066 } 2067 } 2068 2069 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2070 { 2071 /* Adjust EEE LED frequency */ 2072 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2073 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2074 2075 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2076 } 2077 2078 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2079 { 2080 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2081 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2082 } 2083 2084 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2085 { 2086 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2087 } 2088 2089 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2090 { 2091 rtl8125_set_eee_txidle_timer(tp); 2092 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2093 } 2094 2095 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2096 { 2097 const u16 w[] = { 2098 addr[0] | (addr[1] << 8), 2099 addr[2] | (addr[3] << 8), 2100 addr[4] | (addr[5] << 8) 2101 }; 2102 2103 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2104 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2105 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2106 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2107 } 2108 2109 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2110 { 2111 u16 data1, data2, ioffset; 2112 2113 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2114 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2115 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2116 2117 ioffset = (data2 >> 1) & 0x7ff8; 2118 ioffset |= data2 & 0x0007; 2119 if (data1 & BIT(7)) 2120 ioffset |= BIT(15); 2121 2122 return ioffset; 2123 } 2124 2125 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2126 { 2127 set_bit(flag, tp->wk.flags); 2128 schedule_work(&tp->wk.work); 2129 } 2130 2131 static void rtl8169_init_phy(struct rtl8169_private *tp) 2132 { 2133 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2134 2135 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2136 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2137 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2138 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2139 RTL_W8(tp, 0x82, 0x01); 2140 } 2141 2142 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2143 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2144 tp->pci_dev->subsystem_device == 0xe000) 2145 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2146 2147 /* We may have called phy_speed_down before */ 2148 phy_speed_up(tp->phydev); 2149 2150 if (rtl_supports_eee(tp)) 2151 rtl_enable_eee(tp); 2152 2153 genphy_soft_reset(tp->phydev); 2154 } 2155 2156 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2157 { 2158 rtl_unlock_config_regs(tp); 2159 2160 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2161 rtl_pci_commit(tp); 2162 2163 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2164 rtl_pci_commit(tp); 2165 2166 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2167 rtl_rar_exgmac_set(tp, addr); 2168 2169 rtl_lock_config_regs(tp); 2170 } 2171 2172 static int rtl_set_mac_address(struct net_device *dev, void *p) 2173 { 2174 struct rtl8169_private *tp = netdev_priv(dev); 2175 int ret; 2176 2177 ret = eth_mac_addr(dev, p); 2178 if (ret) 2179 return ret; 2180 2181 rtl_rar_set(tp, dev->dev_addr); 2182 2183 return 0; 2184 } 2185 2186 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2187 { 2188 switch (tp->mac_version) { 2189 case RTL_GIGA_MAC_VER_25: 2190 case RTL_GIGA_MAC_VER_26: 2191 case RTL_GIGA_MAC_VER_29: 2192 case RTL_GIGA_MAC_VER_30: 2193 case RTL_GIGA_MAC_VER_32: 2194 case RTL_GIGA_MAC_VER_33: 2195 case RTL_GIGA_MAC_VER_34: 2196 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63: 2197 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2198 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2199 break; 2200 default: 2201 break; 2202 } 2203 } 2204 2205 static void rtl_pll_power_down(struct rtl8169_private *tp) 2206 { 2207 if (r8168_check_dash(tp)) 2208 return; 2209 2210 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2211 tp->mac_version == RTL_GIGA_MAC_VER_33) 2212 rtl_ephy_write(tp, 0x19, 0xff64); 2213 2214 if (device_may_wakeup(tp_to_dev(tp))) { 2215 phy_speed_down(tp->phydev, false); 2216 rtl_wol_suspend_quirk(tp); 2217 return; 2218 } 2219 2220 switch (tp->mac_version) { 2221 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2222 case RTL_GIGA_MAC_VER_37: 2223 case RTL_GIGA_MAC_VER_39: 2224 case RTL_GIGA_MAC_VER_43: 2225 case RTL_GIGA_MAC_VER_44: 2226 case RTL_GIGA_MAC_VER_45: 2227 case RTL_GIGA_MAC_VER_46: 2228 case RTL_GIGA_MAC_VER_47: 2229 case RTL_GIGA_MAC_VER_48: 2230 case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63: 2231 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2232 break; 2233 case RTL_GIGA_MAC_VER_40: 2234 case RTL_GIGA_MAC_VER_41: 2235 case RTL_GIGA_MAC_VER_49: 2236 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 2237 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2238 break; 2239 default: 2240 break; 2241 } 2242 2243 clk_disable_unprepare(tp->clk); 2244 } 2245 2246 static void rtl_pll_power_up(struct rtl8169_private *tp) 2247 { 2248 clk_prepare_enable(tp->clk); 2249 2250 switch (tp->mac_version) { 2251 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2252 case RTL_GIGA_MAC_VER_37: 2253 case RTL_GIGA_MAC_VER_39: 2254 case RTL_GIGA_MAC_VER_43: 2255 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2256 break; 2257 case RTL_GIGA_MAC_VER_44: 2258 case RTL_GIGA_MAC_VER_45: 2259 case RTL_GIGA_MAC_VER_46: 2260 case RTL_GIGA_MAC_VER_47: 2261 case RTL_GIGA_MAC_VER_48: 2262 case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63: 2263 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2264 break; 2265 case RTL_GIGA_MAC_VER_40: 2266 case RTL_GIGA_MAC_VER_41: 2267 case RTL_GIGA_MAC_VER_49: 2268 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2269 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 2270 break; 2271 default: 2272 break; 2273 } 2274 2275 phy_resume(tp->phydev); 2276 } 2277 2278 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2279 { 2280 switch (tp->mac_version) { 2281 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2282 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2283 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2284 break; 2285 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2286 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2287 case RTL_GIGA_MAC_VER_38: 2288 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2289 break; 2290 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2291 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2292 break; 2293 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2294 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2295 break; 2296 default: 2297 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2298 break; 2299 } 2300 } 2301 2302 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2303 { 2304 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2305 } 2306 2307 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2308 { 2309 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2310 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2311 } 2312 2313 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2314 { 2315 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2316 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2317 } 2318 2319 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2320 { 2321 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2322 } 2323 2324 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2325 { 2326 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2327 } 2328 2329 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2330 { 2331 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2332 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2333 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2334 } 2335 2336 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2337 { 2338 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2339 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2340 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2341 } 2342 2343 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2344 { 2345 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2346 } 2347 2348 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2349 { 2350 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2351 } 2352 2353 static void rtl_jumbo_config(struct rtl8169_private *tp) 2354 { 2355 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2356 2357 rtl_unlock_config_regs(tp); 2358 switch (tp->mac_version) { 2359 case RTL_GIGA_MAC_VER_12: 2360 case RTL_GIGA_MAC_VER_17: 2361 if (jumbo) { 2362 pcie_set_readrq(tp->pci_dev, 512); 2363 r8168b_1_hw_jumbo_enable(tp); 2364 } else { 2365 r8168b_1_hw_jumbo_disable(tp); 2366 } 2367 break; 2368 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2369 if (jumbo) { 2370 pcie_set_readrq(tp->pci_dev, 512); 2371 r8168c_hw_jumbo_enable(tp); 2372 } else { 2373 r8168c_hw_jumbo_disable(tp); 2374 } 2375 break; 2376 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2377 if (jumbo) 2378 r8168dp_hw_jumbo_enable(tp); 2379 else 2380 r8168dp_hw_jumbo_disable(tp); 2381 break; 2382 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2383 if (jumbo) { 2384 pcie_set_readrq(tp->pci_dev, 512); 2385 r8168e_hw_jumbo_enable(tp); 2386 } else { 2387 r8168e_hw_jumbo_disable(tp); 2388 } 2389 break; 2390 default: 2391 break; 2392 } 2393 rtl_lock_config_regs(tp); 2394 2395 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2396 pcie_set_readrq(tp->pci_dev, 4096); 2397 } 2398 2399 DECLARE_RTL_COND(rtl_chipcmd_cond) 2400 { 2401 return RTL_R8(tp, ChipCmd) & CmdReset; 2402 } 2403 2404 static void rtl_hw_reset(struct rtl8169_private *tp) 2405 { 2406 RTL_W8(tp, ChipCmd, CmdReset); 2407 2408 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2409 } 2410 2411 static void rtl_request_firmware(struct rtl8169_private *tp) 2412 { 2413 struct rtl_fw *rtl_fw; 2414 2415 /* firmware loaded already or no firmware available */ 2416 if (tp->rtl_fw || !tp->fw_name) 2417 return; 2418 2419 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2420 if (!rtl_fw) 2421 return; 2422 2423 rtl_fw->phy_write = rtl_writephy; 2424 rtl_fw->phy_read = rtl_readphy; 2425 rtl_fw->mac_mcu_write = mac_mcu_write; 2426 rtl_fw->mac_mcu_read = mac_mcu_read; 2427 rtl_fw->fw_name = tp->fw_name; 2428 rtl_fw->dev = tp_to_dev(tp); 2429 2430 if (rtl_fw_request_firmware(rtl_fw)) 2431 kfree(rtl_fw); 2432 else 2433 tp->rtl_fw = rtl_fw; 2434 } 2435 2436 static void rtl_rx_close(struct rtl8169_private *tp) 2437 { 2438 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2439 } 2440 2441 DECLARE_RTL_COND(rtl_npq_cond) 2442 { 2443 return RTL_R8(tp, TxPoll) & NPQ; 2444 } 2445 2446 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2447 { 2448 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2449 } 2450 2451 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2452 { 2453 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2454 } 2455 2456 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2457 { 2458 /* IntrMitigate has new functionality on RTL8125 */ 2459 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2460 } 2461 2462 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2463 { 2464 switch (tp->mac_version) { 2465 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2466 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2467 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2468 break; 2469 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2470 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2471 break; 2472 case RTL_GIGA_MAC_VER_63: 2473 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2474 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2475 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2476 break; 2477 default: 2478 break; 2479 } 2480 } 2481 2482 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2483 { 2484 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2485 fsleep(2000); 2486 rtl_wait_txrx_fifo_empty(tp); 2487 } 2488 2489 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2490 { 2491 u32 val = TX_DMA_BURST << TxDMAShift | 2492 InterFrameGap << TxInterFrameGapShift; 2493 2494 if (rtl_is_8168evl_up(tp)) 2495 val |= TXCFG_AUTO_FIFO; 2496 2497 RTL_W32(tp, TxConfig, val); 2498 } 2499 2500 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2501 { 2502 /* Low hurts. Let's disable the filtering. */ 2503 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2504 } 2505 2506 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2507 { 2508 /* 2509 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2510 * register to be written before TxDescAddrLow to work. 2511 * Switching from MMIO to I/O access fixes the issue as well. 2512 */ 2513 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2514 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2515 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2516 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2517 } 2518 2519 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2520 { 2521 u32 val; 2522 2523 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2524 val = 0x000fff00; 2525 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2526 val = 0x00ffff00; 2527 else 2528 return; 2529 2530 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2531 val |= 0xff; 2532 2533 RTL_W32(tp, 0x7c, val); 2534 } 2535 2536 static void rtl_set_rx_mode(struct net_device *dev) 2537 { 2538 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2539 /* Multicast hash filter */ 2540 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2541 struct rtl8169_private *tp = netdev_priv(dev); 2542 u32 tmp; 2543 2544 if (dev->flags & IFF_PROMISC) { 2545 rx_mode |= AcceptAllPhys; 2546 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2547 dev->flags & IFF_ALLMULTI || 2548 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2549 /* accept all multicasts */ 2550 } else if (netdev_mc_empty(dev)) { 2551 rx_mode &= ~AcceptMulticast; 2552 } else { 2553 struct netdev_hw_addr *ha; 2554 2555 mc_filter[1] = mc_filter[0] = 0; 2556 netdev_for_each_mc_addr(ha, dev) { 2557 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2558 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2559 } 2560 2561 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2562 tmp = mc_filter[0]; 2563 mc_filter[0] = swab32(mc_filter[1]); 2564 mc_filter[1] = swab32(tmp); 2565 } 2566 } 2567 2568 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2569 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2570 2571 tmp = RTL_R32(tp, RxConfig); 2572 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2573 } 2574 2575 DECLARE_RTL_COND(rtl_csiar_cond) 2576 { 2577 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2578 } 2579 2580 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2581 { 2582 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2583 2584 RTL_W32(tp, CSIDR, value); 2585 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2586 CSIAR_BYTE_ENABLE | func << 16); 2587 2588 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2589 } 2590 2591 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2592 { 2593 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2594 2595 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2596 CSIAR_BYTE_ENABLE); 2597 2598 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2599 RTL_R32(tp, CSIDR) : ~0; 2600 } 2601 2602 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2603 { 2604 struct pci_dev *pdev = tp->pci_dev; 2605 u32 csi; 2606 2607 /* According to Realtek the value at config space address 0x070f 2608 * controls the L0s/L1 entrance latency. We try standard ECAM access 2609 * first and if it fails fall back to CSI. 2610 */ 2611 if (pdev->cfg_size > 0x070f && 2612 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2613 return; 2614 2615 netdev_notice_once(tp->dev, 2616 "No native access to PCI extended config space, falling back to CSI\n"); 2617 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2618 rtl_csi_write(tp, 0x070c, csi | val << 24); 2619 } 2620 2621 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2622 { 2623 rtl_csi_access_enable(tp, 0x27); 2624 } 2625 2626 struct ephy_info { 2627 unsigned int offset; 2628 u16 mask; 2629 u16 bits; 2630 }; 2631 2632 static void __rtl_ephy_init(struct rtl8169_private *tp, 2633 const struct ephy_info *e, int len) 2634 { 2635 u16 w; 2636 2637 while (len-- > 0) { 2638 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2639 rtl_ephy_write(tp, e->offset, w); 2640 e++; 2641 } 2642 } 2643 2644 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2645 2646 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2647 { 2648 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2649 PCI_EXP_LNKCTL_CLKREQ_EN); 2650 } 2651 2652 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2653 { 2654 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2655 PCI_EXP_LNKCTL_CLKREQ_EN); 2656 } 2657 2658 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2659 { 2660 /* work around an issue when PCI reset occurs during L2/L3 state */ 2661 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2662 } 2663 2664 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2665 { 2666 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2667 if (enable && tp->aspm_manageable) { 2668 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2669 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2670 } else { 2671 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2672 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2673 } 2674 2675 udelay(10); 2676 } 2677 2678 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2679 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2680 { 2681 /* Usage of dynamic vs. static FIFO is controlled by bit 2682 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2683 */ 2684 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2685 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2686 } 2687 2688 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2689 u8 low, u8 high) 2690 { 2691 /* FIFO thresholds for pause flow control */ 2692 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2693 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2694 } 2695 2696 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2697 { 2698 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2699 } 2700 2701 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2702 { 2703 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2704 2705 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2706 2707 rtl_disable_clock_request(tp); 2708 } 2709 2710 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2711 { 2712 static const struct ephy_info e_info_8168cp[] = { 2713 { 0x01, 0, 0x0001 }, 2714 { 0x02, 0x0800, 0x1000 }, 2715 { 0x03, 0, 0x0042 }, 2716 { 0x06, 0x0080, 0x0000 }, 2717 { 0x07, 0, 0x2000 } 2718 }; 2719 2720 rtl_set_def_aspm_entry_latency(tp); 2721 2722 rtl_ephy_init(tp, e_info_8168cp); 2723 2724 __rtl_hw_start_8168cp(tp); 2725 } 2726 2727 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2728 { 2729 rtl_set_def_aspm_entry_latency(tp); 2730 2731 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2732 } 2733 2734 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2735 { 2736 rtl_set_def_aspm_entry_latency(tp); 2737 2738 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2739 2740 /* Magic. */ 2741 RTL_W8(tp, DBG_REG, 0x20); 2742 } 2743 2744 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2745 { 2746 static const struct ephy_info e_info_8168c_1[] = { 2747 { 0x02, 0x0800, 0x1000 }, 2748 { 0x03, 0, 0x0002 }, 2749 { 0x06, 0x0080, 0x0000 } 2750 }; 2751 2752 rtl_set_def_aspm_entry_latency(tp); 2753 2754 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2755 2756 rtl_ephy_init(tp, e_info_8168c_1); 2757 2758 __rtl_hw_start_8168cp(tp); 2759 } 2760 2761 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2762 { 2763 static const struct ephy_info e_info_8168c_2[] = { 2764 { 0x01, 0, 0x0001 }, 2765 { 0x03, 0x0400, 0x0020 } 2766 }; 2767 2768 rtl_set_def_aspm_entry_latency(tp); 2769 2770 rtl_ephy_init(tp, e_info_8168c_2); 2771 2772 __rtl_hw_start_8168cp(tp); 2773 } 2774 2775 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2776 { 2777 rtl_hw_start_8168c_2(tp); 2778 } 2779 2780 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2781 { 2782 rtl_set_def_aspm_entry_latency(tp); 2783 2784 __rtl_hw_start_8168cp(tp); 2785 } 2786 2787 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2788 { 2789 rtl_set_def_aspm_entry_latency(tp); 2790 2791 rtl_disable_clock_request(tp); 2792 } 2793 2794 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2795 { 2796 static const struct ephy_info e_info_8168d_4[] = { 2797 { 0x0b, 0x0000, 0x0048 }, 2798 { 0x19, 0x0020, 0x0050 }, 2799 { 0x0c, 0x0100, 0x0020 }, 2800 { 0x10, 0x0004, 0x0000 }, 2801 }; 2802 2803 rtl_set_def_aspm_entry_latency(tp); 2804 2805 rtl_ephy_init(tp, e_info_8168d_4); 2806 2807 rtl_enable_clock_request(tp); 2808 } 2809 2810 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2811 { 2812 static const struct ephy_info e_info_8168e_1[] = { 2813 { 0x00, 0x0200, 0x0100 }, 2814 { 0x00, 0x0000, 0x0004 }, 2815 { 0x06, 0x0002, 0x0001 }, 2816 { 0x06, 0x0000, 0x0030 }, 2817 { 0x07, 0x0000, 0x2000 }, 2818 { 0x00, 0x0000, 0x0020 }, 2819 { 0x03, 0x5800, 0x2000 }, 2820 { 0x03, 0x0000, 0x0001 }, 2821 { 0x01, 0x0800, 0x1000 }, 2822 { 0x07, 0x0000, 0x4000 }, 2823 { 0x1e, 0x0000, 0x2000 }, 2824 { 0x19, 0xffff, 0xfe6c }, 2825 { 0x0a, 0x0000, 0x0040 } 2826 }; 2827 2828 rtl_set_def_aspm_entry_latency(tp); 2829 2830 rtl_ephy_init(tp, e_info_8168e_1); 2831 2832 rtl_disable_clock_request(tp); 2833 2834 /* Reset tx FIFO pointer */ 2835 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2836 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2837 2838 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2839 } 2840 2841 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2842 { 2843 static const struct ephy_info e_info_8168e_2[] = { 2844 { 0x09, 0x0000, 0x0080 }, 2845 { 0x19, 0x0000, 0x0224 }, 2846 { 0x00, 0x0000, 0x0004 }, 2847 { 0x0c, 0x3df0, 0x0200 }, 2848 }; 2849 2850 rtl_set_def_aspm_entry_latency(tp); 2851 2852 rtl_ephy_init(tp, e_info_8168e_2); 2853 2854 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2855 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2856 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2857 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2858 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2859 rtl_reset_packet_filter(tp); 2860 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2861 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2862 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2863 2864 rtl_disable_clock_request(tp); 2865 2866 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2867 2868 rtl8168_config_eee_mac(tp); 2869 2870 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2871 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2872 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2873 2874 rtl_hw_aspm_clkreq_enable(tp, true); 2875 } 2876 2877 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2878 { 2879 rtl_set_def_aspm_entry_latency(tp); 2880 2881 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2882 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2883 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2884 rtl_reset_packet_filter(tp); 2885 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2886 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2887 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2888 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2889 2890 rtl_disable_clock_request(tp); 2891 2892 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2893 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2894 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2895 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2896 2897 rtl8168_config_eee_mac(tp); 2898 } 2899 2900 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2901 { 2902 static const struct ephy_info e_info_8168f_1[] = { 2903 { 0x06, 0x00c0, 0x0020 }, 2904 { 0x08, 0x0001, 0x0002 }, 2905 { 0x09, 0x0000, 0x0080 }, 2906 { 0x19, 0x0000, 0x0224 }, 2907 { 0x00, 0x0000, 0x0004 }, 2908 { 0x0c, 0x3df0, 0x0200 }, 2909 }; 2910 2911 rtl_hw_start_8168f(tp); 2912 2913 rtl_ephy_init(tp, e_info_8168f_1); 2914 2915 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2916 } 2917 2918 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2919 { 2920 static const struct ephy_info e_info_8168f_1[] = { 2921 { 0x06, 0x00c0, 0x0020 }, 2922 { 0x0f, 0xffff, 0x5200 }, 2923 { 0x19, 0x0000, 0x0224 }, 2924 { 0x00, 0x0000, 0x0004 }, 2925 { 0x0c, 0x3df0, 0x0200 }, 2926 }; 2927 2928 rtl_hw_start_8168f(tp); 2929 rtl_pcie_state_l2l3_disable(tp); 2930 2931 rtl_ephy_init(tp, e_info_8168f_1); 2932 2933 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2934 } 2935 2936 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2937 { 2938 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2939 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2940 2941 rtl_set_def_aspm_entry_latency(tp); 2942 2943 rtl_reset_packet_filter(tp); 2944 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2945 2946 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2947 2948 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2949 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2950 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2951 2952 rtl8168_config_eee_mac(tp); 2953 2954 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2955 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2956 2957 rtl_pcie_state_l2l3_disable(tp); 2958 } 2959 2960 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2961 { 2962 static const struct ephy_info e_info_8168g_1[] = { 2963 { 0x00, 0x0008, 0x0000 }, 2964 { 0x0c, 0x3ff0, 0x0820 }, 2965 { 0x1e, 0x0000, 0x0001 }, 2966 { 0x19, 0x8000, 0x0000 } 2967 }; 2968 2969 rtl_hw_start_8168g(tp); 2970 2971 /* disable aspm and clock request before access ephy */ 2972 rtl_hw_aspm_clkreq_enable(tp, false); 2973 rtl_ephy_init(tp, e_info_8168g_1); 2974 rtl_hw_aspm_clkreq_enable(tp, true); 2975 } 2976 2977 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 2978 { 2979 static const struct ephy_info e_info_8168g_2[] = { 2980 { 0x00, 0x0008, 0x0000 }, 2981 { 0x0c, 0x3ff0, 0x0820 }, 2982 { 0x19, 0xffff, 0x7c00 }, 2983 { 0x1e, 0xffff, 0x20eb }, 2984 { 0x0d, 0xffff, 0x1666 }, 2985 { 0x00, 0xffff, 0x10a3 }, 2986 { 0x06, 0xffff, 0xf050 }, 2987 { 0x04, 0x0000, 0x0010 }, 2988 { 0x1d, 0x4000, 0x0000 }, 2989 }; 2990 2991 rtl_hw_start_8168g(tp); 2992 2993 /* disable aspm and clock request before access ephy */ 2994 rtl_hw_aspm_clkreq_enable(tp, false); 2995 rtl_ephy_init(tp, e_info_8168g_2); 2996 } 2997 2998 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 2999 { 3000 static const struct ephy_info e_info_8411_2[] = { 3001 { 0x00, 0x0008, 0x0000 }, 3002 { 0x0c, 0x37d0, 0x0820 }, 3003 { 0x1e, 0x0000, 0x0001 }, 3004 { 0x19, 0x8021, 0x0000 }, 3005 { 0x1e, 0x0000, 0x2000 }, 3006 { 0x0d, 0x0100, 0x0200 }, 3007 { 0x00, 0x0000, 0x0080 }, 3008 { 0x06, 0x0000, 0x0010 }, 3009 { 0x04, 0x0000, 0x0010 }, 3010 { 0x1d, 0x0000, 0x4000 }, 3011 }; 3012 3013 rtl_hw_start_8168g(tp); 3014 3015 /* disable aspm and clock request before access ephy */ 3016 rtl_hw_aspm_clkreq_enable(tp, false); 3017 rtl_ephy_init(tp, e_info_8411_2); 3018 3019 /* The following Realtek-provided magic fixes an issue with the RX unit 3020 * getting confused after the PHY having been powered-down. 3021 */ 3022 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3023 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3024 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3025 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3026 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3027 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3028 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3029 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3030 mdelay(3); 3031 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3032 3033 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3034 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3035 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3036 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3037 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3038 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3039 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3040 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3041 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3042 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3043 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3044 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3045 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3046 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3047 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3048 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3049 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3050 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3051 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3052 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3053 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3054 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3055 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3056 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3057 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3058 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3059 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3060 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3061 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3062 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3063 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3064 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3065 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3066 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3067 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3068 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3069 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3070 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3071 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3072 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3073 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3074 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3075 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3076 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3077 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3078 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3079 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3080 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3081 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3082 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3083 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3084 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3085 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3086 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3087 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3088 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3089 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3090 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3091 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3092 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3093 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3094 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3095 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3096 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3097 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3098 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3099 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3100 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3101 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3102 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3103 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3104 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3105 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3106 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3107 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3108 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3109 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3110 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3111 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3112 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3113 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3114 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3115 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3116 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3117 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3118 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3119 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3120 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3121 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3122 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3123 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3124 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3125 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3126 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3127 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3128 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3129 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3130 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3131 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3132 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3133 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3134 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3135 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3136 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3137 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3138 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3139 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3140 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3141 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3142 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3143 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3144 3145 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3146 3147 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3148 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3149 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3150 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3151 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3152 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3153 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3154 3155 rtl_hw_aspm_clkreq_enable(tp, true); 3156 } 3157 3158 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3159 { 3160 static const struct ephy_info e_info_8168h_1[] = { 3161 { 0x1e, 0x0800, 0x0001 }, 3162 { 0x1d, 0x0000, 0x0800 }, 3163 { 0x05, 0xffff, 0x2089 }, 3164 { 0x06, 0xffff, 0x5881 }, 3165 { 0x04, 0xffff, 0x854a }, 3166 { 0x01, 0xffff, 0x068b } 3167 }; 3168 int rg_saw_cnt; 3169 3170 /* disable aspm and clock request before access ephy */ 3171 rtl_hw_aspm_clkreq_enable(tp, false); 3172 rtl_ephy_init(tp, e_info_8168h_1); 3173 3174 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3175 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3176 3177 rtl_set_def_aspm_entry_latency(tp); 3178 3179 rtl_reset_packet_filter(tp); 3180 3181 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3182 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3183 3184 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3185 3186 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3187 3188 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3189 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3190 3191 rtl8168_config_eee_mac(tp); 3192 3193 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3194 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3195 3196 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3197 3198 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3199 3200 rtl_pcie_state_l2l3_disable(tp); 3201 3202 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3203 if (rg_saw_cnt > 0) { 3204 u16 sw_cnt_1ms_ini; 3205 3206 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3207 sw_cnt_1ms_ini &= 0x0fff; 3208 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3209 } 3210 3211 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3212 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3213 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3214 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3215 3216 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3217 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3218 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3219 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3220 3221 rtl_hw_aspm_clkreq_enable(tp, true); 3222 } 3223 3224 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3225 { 3226 rtl8168ep_stop_cmac(tp); 3227 3228 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3229 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3230 3231 rtl_set_def_aspm_entry_latency(tp); 3232 3233 rtl_reset_packet_filter(tp); 3234 3235 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3236 3237 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3238 3239 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3240 3241 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3242 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3243 3244 rtl8168_config_eee_mac(tp); 3245 3246 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3247 3248 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3249 3250 rtl_pcie_state_l2l3_disable(tp); 3251 } 3252 3253 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3254 { 3255 static const struct ephy_info e_info_8168ep_1[] = { 3256 { 0x00, 0xffff, 0x10ab }, 3257 { 0x06, 0xffff, 0xf030 }, 3258 { 0x08, 0xffff, 0x2006 }, 3259 { 0x0d, 0xffff, 0x1666 }, 3260 { 0x0c, 0x3ff0, 0x0000 } 3261 }; 3262 3263 /* disable aspm and clock request before access ephy */ 3264 rtl_hw_aspm_clkreq_enable(tp, false); 3265 rtl_ephy_init(tp, e_info_8168ep_1); 3266 3267 rtl_hw_start_8168ep(tp); 3268 3269 rtl_hw_aspm_clkreq_enable(tp, true); 3270 } 3271 3272 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3273 { 3274 static const struct ephy_info e_info_8168ep_2[] = { 3275 { 0x00, 0xffff, 0x10a3 }, 3276 { 0x19, 0xffff, 0xfc00 }, 3277 { 0x1e, 0xffff, 0x20ea } 3278 }; 3279 3280 /* disable aspm and clock request before access ephy */ 3281 rtl_hw_aspm_clkreq_enable(tp, false); 3282 rtl_ephy_init(tp, e_info_8168ep_2); 3283 3284 rtl_hw_start_8168ep(tp); 3285 3286 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3287 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3288 3289 rtl_hw_aspm_clkreq_enable(tp, true); 3290 } 3291 3292 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3293 { 3294 static const struct ephy_info e_info_8168ep_3[] = { 3295 { 0x00, 0x0000, 0x0080 }, 3296 { 0x0d, 0x0100, 0x0200 }, 3297 { 0x19, 0x8021, 0x0000 }, 3298 { 0x1e, 0x0000, 0x2000 }, 3299 }; 3300 3301 /* disable aspm and clock request before access ephy */ 3302 rtl_hw_aspm_clkreq_enable(tp, false); 3303 rtl_ephy_init(tp, e_info_8168ep_3); 3304 3305 rtl_hw_start_8168ep(tp); 3306 3307 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3308 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3309 3310 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3311 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3312 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3313 3314 rtl_hw_aspm_clkreq_enable(tp, true); 3315 } 3316 3317 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3318 { 3319 static const struct ephy_info e_info_8117[] = { 3320 { 0x19, 0x0040, 0x1100 }, 3321 { 0x59, 0x0040, 0x1100 }, 3322 }; 3323 int rg_saw_cnt; 3324 3325 rtl8168ep_stop_cmac(tp); 3326 3327 /* disable aspm and clock request before access ephy */ 3328 rtl_hw_aspm_clkreq_enable(tp, false); 3329 rtl_ephy_init(tp, e_info_8117); 3330 3331 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3332 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3333 3334 rtl_set_def_aspm_entry_latency(tp); 3335 3336 rtl_reset_packet_filter(tp); 3337 3338 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3339 3340 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3341 3342 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3343 3344 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3345 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3346 3347 rtl8168_config_eee_mac(tp); 3348 3349 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3350 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3351 3352 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3353 3354 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3355 3356 rtl_pcie_state_l2l3_disable(tp); 3357 3358 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3359 if (rg_saw_cnt > 0) { 3360 u16 sw_cnt_1ms_ini; 3361 3362 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3363 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3364 } 3365 3366 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3367 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3368 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3369 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3370 3371 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3372 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3373 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3374 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3375 3376 /* firmware is for MAC only */ 3377 r8169_apply_firmware(tp); 3378 3379 rtl_hw_aspm_clkreq_enable(tp, true); 3380 } 3381 3382 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3383 { 3384 static const struct ephy_info e_info_8102e_1[] = { 3385 { 0x01, 0, 0x6e65 }, 3386 { 0x02, 0, 0x091f }, 3387 { 0x03, 0, 0xc2f9 }, 3388 { 0x06, 0, 0xafb5 }, 3389 { 0x07, 0, 0x0e00 }, 3390 { 0x19, 0, 0xec80 }, 3391 { 0x01, 0, 0x2e65 }, 3392 { 0x01, 0, 0x6e65 } 3393 }; 3394 u8 cfg1; 3395 3396 rtl_set_def_aspm_entry_latency(tp); 3397 3398 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3399 3400 RTL_W8(tp, Config1, 3401 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3402 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3403 3404 cfg1 = RTL_R8(tp, Config1); 3405 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3406 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3407 3408 rtl_ephy_init(tp, e_info_8102e_1); 3409 } 3410 3411 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3412 { 3413 rtl_set_def_aspm_entry_latency(tp); 3414 3415 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3416 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3417 } 3418 3419 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3420 { 3421 rtl_hw_start_8102e_2(tp); 3422 3423 rtl_ephy_write(tp, 0x03, 0xc2f9); 3424 } 3425 3426 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3427 { 3428 static const struct ephy_info e_info_8401[] = { 3429 { 0x01, 0xffff, 0x6fe5 }, 3430 { 0x03, 0xffff, 0x0599 }, 3431 { 0x06, 0xffff, 0xaf25 }, 3432 { 0x07, 0xffff, 0x8e68 }, 3433 }; 3434 3435 rtl_ephy_init(tp, e_info_8401); 3436 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3437 } 3438 3439 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3440 { 3441 static const struct ephy_info e_info_8105e_1[] = { 3442 { 0x07, 0, 0x4000 }, 3443 { 0x19, 0, 0x0200 }, 3444 { 0x19, 0, 0x0020 }, 3445 { 0x1e, 0, 0x2000 }, 3446 { 0x03, 0, 0x0001 }, 3447 { 0x19, 0, 0x0100 }, 3448 { 0x19, 0, 0x0004 }, 3449 { 0x0a, 0, 0x0020 } 3450 }; 3451 3452 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3453 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3454 3455 /* Disable Early Tally Counter */ 3456 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3457 3458 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3459 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3460 3461 rtl_ephy_init(tp, e_info_8105e_1); 3462 3463 rtl_pcie_state_l2l3_disable(tp); 3464 } 3465 3466 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3467 { 3468 rtl_hw_start_8105e_1(tp); 3469 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3470 } 3471 3472 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3473 { 3474 static const struct ephy_info e_info_8402[] = { 3475 { 0x19, 0xffff, 0xff64 }, 3476 { 0x1e, 0, 0x4000 } 3477 }; 3478 3479 rtl_set_def_aspm_entry_latency(tp); 3480 3481 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3482 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3483 3484 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3485 3486 rtl_ephy_init(tp, e_info_8402); 3487 3488 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3489 rtl_reset_packet_filter(tp); 3490 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3491 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3492 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3493 3494 /* disable EEE */ 3495 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3496 3497 rtl_pcie_state_l2l3_disable(tp); 3498 } 3499 3500 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3501 { 3502 rtl_hw_aspm_clkreq_enable(tp, false); 3503 3504 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3505 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3506 3507 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3508 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3509 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3510 3511 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3512 3513 /* disable EEE */ 3514 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3515 3516 rtl_pcie_state_l2l3_disable(tp); 3517 rtl_hw_aspm_clkreq_enable(tp, true); 3518 } 3519 3520 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3521 { 3522 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3523 } 3524 3525 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3526 { 3527 rtl_pcie_state_l2l3_disable(tp); 3528 3529 RTL_W16(tp, 0x382, 0x221b); 3530 RTL_W8(tp, 0x4500, 0); 3531 RTL_W16(tp, 0x4800, 0); 3532 3533 /* disable UPS */ 3534 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3535 3536 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3537 3538 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3539 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3540 3541 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3542 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3543 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3544 3545 /* disable new tx descriptor format */ 3546 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3547 3548 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3549 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3550 else 3551 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3552 3553 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3554 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3555 else 3556 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3557 3558 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3559 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3560 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3561 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3562 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3563 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3564 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3565 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3566 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3567 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3568 3569 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3570 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3571 udelay(1); 3572 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3573 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3574 3575 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3576 3577 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3578 3579 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3580 rtl8125b_config_eee_mac(tp); 3581 else 3582 rtl8125a_config_eee_mac(tp); 3583 3584 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3585 udelay(10); 3586 } 3587 3588 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3589 { 3590 static const struct ephy_info e_info_8125a_1[] = { 3591 { 0x01, 0xffff, 0xa812 }, 3592 { 0x09, 0xffff, 0x520c }, 3593 { 0x04, 0xffff, 0xd000 }, 3594 { 0x0d, 0xffff, 0xf702 }, 3595 { 0x0a, 0xffff, 0x8653 }, 3596 { 0x06, 0xffff, 0x001e }, 3597 { 0x08, 0xffff, 0x3595 }, 3598 { 0x20, 0xffff, 0x9455 }, 3599 { 0x21, 0xffff, 0x99ff }, 3600 { 0x02, 0xffff, 0x6046 }, 3601 { 0x29, 0xffff, 0xfe00 }, 3602 { 0x23, 0xffff, 0xab62 }, 3603 3604 { 0x41, 0xffff, 0xa80c }, 3605 { 0x49, 0xffff, 0x520c }, 3606 { 0x44, 0xffff, 0xd000 }, 3607 { 0x4d, 0xffff, 0xf702 }, 3608 { 0x4a, 0xffff, 0x8653 }, 3609 { 0x46, 0xffff, 0x001e }, 3610 { 0x48, 0xffff, 0x3595 }, 3611 { 0x60, 0xffff, 0x9455 }, 3612 { 0x61, 0xffff, 0x99ff }, 3613 { 0x42, 0xffff, 0x6046 }, 3614 { 0x69, 0xffff, 0xfe00 }, 3615 { 0x63, 0xffff, 0xab62 }, 3616 }; 3617 3618 rtl_set_def_aspm_entry_latency(tp); 3619 3620 /* disable aspm and clock request before access ephy */ 3621 rtl_hw_aspm_clkreq_enable(tp, false); 3622 rtl_ephy_init(tp, e_info_8125a_1); 3623 3624 rtl_hw_start_8125_common(tp); 3625 rtl_hw_aspm_clkreq_enable(tp, true); 3626 } 3627 3628 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3629 { 3630 static const struct ephy_info e_info_8125a_2[] = { 3631 { 0x04, 0xffff, 0xd000 }, 3632 { 0x0a, 0xffff, 0x8653 }, 3633 { 0x23, 0xffff, 0xab66 }, 3634 { 0x20, 0xffff, 0x9455 }, 3635 { 0x21, 0xffff, 0x99ff }, 3636 { 0x29, 0xffff, 0xfe04 }, 3637 3638 { 0x44, 0xffff, 0xd000 }, 3639 { 0x4a, 0xffff, 0x8653 }, 3640 { 0x63, 0xffff, 0xab66 }, 3641 { 0x60, 0xffff, 0x9455 }, 3642 { 0x61, 0xffff, 0x99ff }, 3643 { 0x69, 0xffff, 0xfe04 }, 3644 }; 3645 3646 rtl_set_def_aspm_entry_latency(tp); 3647 3648 /* disable aspm and clock request before access ephy */ 3649 rtl_hw_aspm_clkreq_enable(tp, false); 3650 rtl_ephy_init(tp, e_info_8125a_2); 3651 3652 rtl_hw_start_8125_common(tp); 3653 rtl_hw_aspm_clkreq_enable(tp, true); 3654 } 3655 3656 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3657 { 3658 static const struct ephy_info e_info_8125b[] = { 3659 { 0x0b, 0xffff, 0xa908 }, 3660 { 0x1e, 0xffff, 0x20eb }, 3661 { 0x4b, 0xffff, 0xa908 }, 3662 { 0x5e, 0xffff, 0x20eb }, 3663 { 0x22, 0x0030, 0x0020 }, 3664 { 0x62, 0x0030, 0x0020 }, 3665 }; 3666 3667 rtl_set_def_aspm_entry_latency(tp); 3668 rtl_hw_aspm_clkreq_enable(tp, false); 3669 3670 rtl_ephy_init(tp, e_info_8125b); 3671 rtl_hw_start_8125_common(tp); 3672 3673 rtl_hw_aspm_clkreq_enable(tp, true); 3674 } 3675 3676 static void rtl_hw_config(struct rtl8169_private *tp) 3677 { 3678 static const rtl_generic_fct hw_configs[] = { 3679 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3680 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3681 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3682 [RTL_GIGA_MAC_VER_10] = NULL, 3683 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3684 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3685 [RTL_GIGA_MAC_VER_13] = NULL, 3686 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3687 [RTL_GIGA_MAC_VER_16] = NULL, 3688 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3689 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3690 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3691 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3692 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3693 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3694 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3695 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3696 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3697 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3698 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3699 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3700 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3701 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3702 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3703 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3704 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3705 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3706 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3707 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3708 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3709 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3710 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3711 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3712 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3713 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3714 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3715 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3716 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3717 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3718 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3719 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3720 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3721 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3722 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3723 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3724 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3725 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3726 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3727 }; 3728 3729 if (hw_configs[tp->mac_version]) 3730 hw_configs[tp->mac_version](tp); 3731 } 3732 3733 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3734 { 3735 int i; 3736 3737 /* disable interrupt coalescing */ 3738 for (i = 0xa00; i < 0xb00; i += 4) 3739 RTL_W32(tp, i, 0); 3740 3741 rtl_hw_config(tp); 3742 } 3743 3744 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3745 { 3746 if (rtl_is_8168evl_up(tp)) 3747 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3748 else 3749 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3750 3751 rtl_hw_config(tp); 3752 3753 /* disable interrupt coalescing */ 3754 RTL_W16(tp, IntrMitigate, 0x0000); 3755 } 3756 3757 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3758 { 3759 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3760 3761 tp->cp_cmd |= PCIMulRW; 3762 3763 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3764 tp->mac_version == RTL_GIGA_MAC_VER_03) 3765 tp->cp_cmd |= EnAnaPLL; 3766 3767 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3768 3769 rtl8169_set_magic_reg(tp); 3770 3771 /* disable interrupt coalescing */ 3772 RTL_W16(tp, IntrMitigate, 0x0000); 3773 } 3774 3775 static void rtl_hw_start(struct rtl8169_private *tp) 3776 { 3777 rtl_unlock_config_regs(tp); 3778 3779 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3780 3781 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3782 rtl_hw_start_8169(tp); 3783 else if (rtl_is_8125(tp)) 3784 rtl_hw_start_8125(tp); 3785 else 3786 rtl_hw_start_8168(tp); 3787 3788 rtl_set_rx_max_size(tp); 3789 rtl_set_rx_tx_desc_registers(tp); 3790 rtl_lock_config_regs(tp); 3791 3792 rtl_jumbo_config(tp); 3793 3794 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3795 rtl_pci_commit(tp); 3796 3797 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3798 rtl_init_rxcfg(tp); 3799 rtl_set_tx_config_registers(tp); 3800 rtl_set_rx_config_features(tp, tp->dev->features); 3801 rtl_set_rx_mode(tp->dev); 3802 rtl_irq_enable(tp); 3803 } 3804 3805 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3806 { 3807 struct rtl8169_private *tp = netdev_priv(dev); 3808 3809 dev->mtu = new_mtu; 3810 netdev_update_features(dev); 3811 rtl_jumbo_config(tp); 3812 3813 switch (tp->mac_version) { 3814 case RTL_GIGA_MAC_VER_61: 3815 case RTL_GIGA_MAC_VER_63: 3816 rtl8125_set_eee_txidle_timer(tp); 3817 break; 3818 default: 3819 break; 3820 } 3821 3822 return 0; 3823 } 3824 3825 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3826 { 3827 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3828 3829 desc->opts2 = 0; 3830 /* Force memory writes to complete before releasing descriptor */ 3831 dma_wmb(); 3832 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3833 } 3834 3835 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3836 struct RxDesc *desc) 3837 { 3838 struct device *d = tp_to_dev(tp); 3839 int node = dev_to_node(d); 3840 dma_addr_t mapping; 3841 struct page *data; 3842 3843 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3844 if (!data) 3845 return NULL; 3846 3847 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3848 if (unlikely(dma_mapping_error(d, mapping))) { 3849 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3850 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3851 return NULL; 3852 } 3853 3854 desc->addr = cpu_to_le64(mapping); 3855 rtl8169_mark_to_asic(desc); 3856 3857 return data; 3858 } 3859 3860 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3861 { 3862 unsigned int i; 3863 3864 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3865 dma_unmap_page(tp_to_dev(tp), 3866 le64_to_cpu(tp->RxDescArray[i].addr), 3867 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3868 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3869 tp->Rx_databuff[i] = NULL; 3870 tp->RxDescArray[i].addr = 0; 3871 tp->RxDescArray[i].opts1 = 0; 3872 } 3873 } 3874 3875 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3876 { 3877 unsigned int i; 3878 3879 for (i = 0; i < NUM_RX_DESC; i++) { 3880 struct page *data; 3881 3882 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3883 if (!data) { 3884 rtl8169_rx_clear(tp); 3885 return -ENOMEM; 3886 } 3887 tp->Rx_databuff[i] = data; 3888 } 3889 3890 /* mark as last descriptor in the ring */ 3891 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3892 3893 return 0; 3894 } 3895 3896 static int rtl8169_init_ring(struct rtl8169_private *tp) 3897 { 3898 rtl8169_init_ring_indexes(tp); 3899 3900 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3901 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3902 3903 return rtl8169_rx_fill(tp); 3904 } 3905 3906 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3907 { 3908 struct ring_info *tx_skb = tp->tx_skb + entry; 3909 struct TxDesc *desc = tp->TxDescArray + entry; 3910 3911 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3912 DMA_TO_DEVICE); 3913 memset(desc, 0, sizeof(*desc)); 3914 memset(tx_skb, 0, sizeof(*tx_skb)); 3915 } 3916 3917 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3918 unsigned int n) 3919 { 3920 unsigned int i; 3921 3922 for (i = 0; i < n; i++) { 3923 unsigned int entry = (start + i) % NUM_TX_DESC; 3924 struct ring_info *tx_skb = tp->tx_skb + entry; 3925 unsigned int len = tx_skb->len; 3926 3927 if (len) { 3928 struct sk_buff *skb = tx_skb->skb; 3929 3930 rtl8169_unmap_tx_skb(tp, entry); 3931 if (skb) 3932 dev_consume_skb_any(skb); 3933 } 3934 } 3935 } 3936 3937 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3938 { 3939 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3940 netdev_reset_queue(tp->dev); 3941 } 3942 3943 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3944 { 3945 napi_disable(&tp->napi); 3946 3947 /* Give a racing hard_start_xmit a few cycles to complete. */ 3948 synchronize_net(); 3949 3950 /* Disable interrupts */ 3951 rtl8169_irq_mask_and_ack(tp); 3952 3953 rtl_rx_close(tp); 3954 3955 if (going_down && tp->dev->wol_enabled) 3956 goto no_reset; 3957 3958 switch (tp->mac_version) { 3959 case RTL_GIGA_MAC_VER_27: 3960 case RTL_GIGA_MAC_VER_28: 3961 case RTL_GIGA_MAC_VER_31: 3962 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3963 break; 3964 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3965 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3966 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3967 break; 3968 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3969 rtl_enable_rxdvgate(tp); 3970 fsleep(2000); 3971 break; 3972 default: 3973 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3974 fsleep(100); 3975 break; 3976 } 3977 3978 rtl_hw_reset(tp); 3979 no_reset: 3980 rtl8169_tx_clear(tp); 3981 rtl8169_init_ring_indexes(tp); 3982 } 3983 3984 static void rtl_reset_work(struct rtl8169_private *tp) 3985 { 3986 int i; 3987 3988 netif_stop_queue(tp->dev); 3989 3990 rtl8169_cleanup(tp, false); 3991 3992 for (i = 0; i < NUM_RX_DESC; i++) 3993 rtl8169_mark_to_asic(tp->RxDescArray + i); 3994 3995 napi_enable(&tp->napi); 3996 rtl_hw_start(tp); 3997 } 3998 3999 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4000 { 4001 struct rtl8169_private *tp = netdev_priv(dev); 4002 4003 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4004 } 4005 4006 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4007 void *addr, unsigned int entry, bool desc_own) 4008 { 4009 struct TxDesc *txd = tp->TxDescArray + entry; 4010 struct device *d = tp_to_dev(tp); 4011 dma_addr_t mapping; 4012 u32 opts1; 4013 int ret; 4014 4015 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4016 ret = dma_mapping_error(d, mapping); 4017 if (unlikely(ret)) { 4018 if (net_ratelimit()) 4019 netdev_err(tp->dev, "Failed to map TX data!\n"); 4020 return ret; 4021 } 4022 4023 txd->addr = cpu_to_le64(mapping); 4024 txd->opts2 = cpu_to_le32(opts[1]); 4025 4026 opts1 = opts[0] | len; 4027 if (entry == NUM_TX_DESC - 1) 4028 opts1 |= RingEnd; 4029 if (desc_own) 4030 opts1 |= DescOwn; 4031 txd->opts1 = cpu_to_le32(opts1); 4032 4033 tp->tx_skb[entry].len = len; 4034 4035 return 0; 4036 } 4037 4038 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4039 const u32 *opts, unsigned int entry) 4040 { 4041 struct skb_shared_info *info = skb_shinfo(skb); 4042 unsigned int cur_frag; 4043 4044 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4045 const skb_frag_t *frag = info->frags + cur_frag; 4046 void *addr = skb_frag_address(frag); 4047 u32 len = skb_frag_size(frag); 4048 4049 entry = (entry + 1) % NUM_TX_DESC; 4050 4051 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4052 goto err_out; 4053 } 4054 4055 return 0; 4056 4057 err_out: 4058 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4059 return -EIO; 4060 } 4061 4062 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 4063 { 4064 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 4065 } 4066 4067 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4068 { 4069 u32 mss = skb_shinfo(skb)->gso_size; 4070 4071 if (mss) { 4072 opts[0] |= TD_LSO; 4073 opts[0] |= mss << TD0_MSS_SHIFT; 4074 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4075 const struct iphdr *ip = ip_hdr(skb); 4076 4077 if (ip->protocol == IPPROTO_TCP) 4078 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4079 else if (ip->protocol == IPPROTO_UDP) 4080 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4081 else 4082 WARN_ON_ONCE(1); 4083 } 4084 } 4085 4086 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4087 struct sk_buff *skb, u32 *opts) 4088 { 4089 u32 transport_offset = (u32)skb_transport_offset(skb); 4090 struct skb_shared_info *shinfo = skb_shinfo(skb); 4091 u32 mss = shinfo->gso_size; 4092 4093 if (mss) { 4094 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4095 opts[0] |= TD1_GTSENV4; 4096 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4097 if (skb_cow_head(skb, 0)) 4098 return false; 4099 4100 tcp_v6_gso_csum_prep(skb); 4101 opts[0] |= TD1_GTSENV6; 4102 } else { 4103 WARN_ON_ONCE(1); 4104 } 4105 4106 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4107 opts[1] |= mss << TD1_MSS_SHIFT; 4108 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4109 u8 ip_protocol; 4110 4111 switch (vlan_get_protocol(skb)) { 4112 case htons(ETH_P_IP): 4113 opts[1] |= TD1_IPv4_CS; 4114 ip_protocol = ip_hdr(skb)->protocol; 4115 break; 4116 4117 case htons(ETH_P_IPV6): 4118 opts[1] |= TD1_IPv6_CS; 4119 ip_protocol = ipv6_hdr(skb)->nexthdr; 4120 break; 4121 4122 default: 4123 ip_protocol = IPPROTO_RAW; 4124 break; 4125 } 4126 4127 if (ip_protocol == IPPROTO_TCP) 4128 opts[1] |= TD1_TCP_CS; 4129 else if (ip_protocol == IPPROTO_UDP) 4130 opts[1] |= TD1_UDP_CS; 4131 else 4132 WARN_ON_ONCE(1); 4133 4134 opts[1] |= transport_offset << TCPHO_SHIFT; 4135 } else { 4136 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 4137 return !eth_skb_pad(skb); 4138 } 4139 4140 return true; 4141 } 4142 4143 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4144 unsigned int nr_frags) 4145 { 4146 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4147 4148 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4149 return slots_avail > nr_frags; 4150 } 4151 4152 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4153 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4154 { 4155 switch (tp->mac_version) { 4156 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4157 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4158 return false; 4159 default: 4160 return true; 4161 } 4162 } 4163 4164 static void rtl8169_doorbell(struct rtl8169_private *tp) 4165 { 4166 if (rtl_is_8125(tp)) 4167 RTL_W16(tp, TxPoll_8125, BIT(0)); 4168 else 4169 RTL_W8(tp, TxPoll, NPQ); 4170 } 4171 4172 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4173 struct net_device *dev) 4174 { 4175 unsigned int frags = skb_shinfo(skb)->nr_frags; 4176 struct rtl8169_private *tp = netdev_priv(dev); 4177 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4178 struct TxDesc *txd_first, *txd_last; 4179 bool stop_queue, door_bell; 4180 u32 opts[2]; 4181 4182 txd_first = tp->TxDescArray + entry; 4183 4184 if (unlikely(!rtl_tx_slots_avail(tp, frags))) { 4185 if (net_ratelimit()) 4186 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4187 goto err_stop_0; 4188 } 4189 4190 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn)) 4191 goto err_stop_0; 4192 4193 opts[1] = rtl8169_tx_vlan_tag(skb); 4194 opts[0] = 0; 4195 4196 if (!rtl_chip_supports_csum_v2(tp)) 4197 rtl8169_tso_csum_v1(skb, opts); 4198 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4199 goto err_dma_0; 4200 4201 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4202 entry, false))) 4203 goto err_dma_0; 4204 4205 if (frags) { 4206 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4207 goto err_dma_1; 4208 entry = (entry + frags) % NUM_TX_DESC; 4209 } 4210 4211 txd_last = tp->TxDescArray + entry; 4212 txd_last->opts1 |= cpu_to_le32(LastFrag); 4213 tp->tx_skb[entry].skb = skb; 4214 4215 skb_tx_timestamp(skb); 4216 4217 /* Force memory writes to complete before releasing descriptor */ 4218 dma_wmb(); 4219 4220 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4221 4222 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4223 4224 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4225 smp_wmb(); 4226 4227 tp->cur_tx += frags + 1; 4228 4229 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4230 if (unlikely(stop_queue)) { 4231 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4232 * not miss a ring update when it notices a stopped queue. 4233 */ 4234 smp_wmb(); 4235 netif_stop_queue(dev); 4236 door_bell = true; 4237 } 4238 4239 if (door_bell) 4240 rtl8169_doorbell(tp); 4241 4242 if (unlikely(stop_queue)) { 4243 /* Sync with rtl_tx: 4244 * - publish queue status and cur_tx ring index (write barrier) 4245 * - refresh dirty_tx ring index (read barrier). 4246 * May the current thread have a pessimistic view of the ring 4247 * status and forget to wake up queue, a racing rtl_tx thread 4248 * can't. 4249 */ 4250 smp_mb(); 4251 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4252 netif_start_queue(dev); 4253 } 4254 4255 return NETDEV_TX_OK; 4256 4257 err_dma_1: 4258 rtl8169_unmap_tx_skb(tp, entry); 4259 err_dma_0: 4260 dev_kfree_skb_any(skb); 4261 dev->stats.tx_dropped++; 4262 return NETDEV_TX_OK; 4263 4264 err_stop_0: 4265 netif_stop_queue(dev); 4266 dev->stats.tx_dropped++; 4267 return NETDEV_TX_BUSY; 4268 } 4269 4270 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4271 { 4272 struct skb_shared_info *info = skb_shinfo(skb); 4273 unsigned int nr_frags = info->nr_frags; 4274 4275 if (!nr_frags) 4276 return UINT_MAX; 4277 4278 return skb_frag_size(info->frags + nr_frags - 1); 4279 } 4280 4281 /* Workaround for hw issues with TSO on RTL8168evl */ 4282 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4283 netdev_features_t features) 4284 { 4285 /* IPv4 header has options field */ 4286 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4287 ip_hdrlen(skb) > sizeof(struct iphdr)) 4288 features &= ~NETIF_F_ALL_TSO; 4289 4290 /* IPv4 TCP header has options field */ 4291 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4292 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4293 features &= ~NETIF_F_ALL_TSO; 4294 4295 else if (rtl_last_frag_len(skb) <= 6) 4296 features &= ~NETIF_F_ALL_TSO; 4297 4298 return features; 4299 } 4300 4301 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4302 struct net_device *dev, 4303 netdev_features_t features) 4304 { 4305 int transport_offset = skb_transport_offset(skb); 4306 struct rtl8169_private *tp = netdev_priv(dev); 4307 4308 if (skb_is_gso(skb)) { 4309 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4310 features = rtl8168evl_fix_tso(skb, features); 4311 4312 if (transport_offset > GTTCPHO_MAX && 4313 rtl_chip_supports_csum_v2(tp)) 4314 features &= ~NETIF_F_ALL_TSO; 4315 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4316 if (skb->len < ETH_ZLEN) { 4317 switch (tp->mac_version) { 4318 case RTL_GIGA_MAC_VER_11: 4319 case RTL_GIGA_MAC_VER_12: 4320 case RTL_GIGA_MAC_VER_17: 4321 case RTL_GIGA_MAC_VER_34: 4322 features &= ~NETIF_F_CSUM_MASK; 4323 break; 4324 default: 4325 break; 4326 } 4327 } 4328 4329 if (transport_offset > TCPHO_MAX && 4330 rtl_chip_supports_csum_v2(tp)) 4331 features &= ~NETIF_F_CSUM_MASK; 4332 } 4333 4334 return vlan_features_check(skb, features); 4335 } 4336 4337 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4338 { 4339 struct rtl8169_private *tp = netdev_priv(dev); 4340 struct pci_dev *pdev = tp->pci_dev; 4341 int pci_status_errs; 4342 u16 pci_cmd; 4343 4344 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4345 4346 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4347 4348 if (net_ratelimit()) 4349 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4350 pci_cmd, pci_status_errs); 4351 /* 4352 * The recovery sequence below admits a very elaborated explanation: 4353 * - it seems to work; 4354 * - I did not see what else could be done; 4355 * - it makes iop3xx happy. 4356 * 4357 * Feel free to adjust to your needs. 4358 */ 4359 if (pdev->broken_parity_status) 4360 pci_cmd &= ~PCI_COMMAND_PARITY; 4361 else 4362 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4363 4364 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4365 4366 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4367 } 4368 4369 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4370 int budget) 4371 { 4372 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4373 4374 dirty_tx = tp->dirty_tx; 4375 smp_rmb(); 4376 4377 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) { 4378 unsigned int entry = dirty_tx % NUM_TX_DESC; 4379 struct sk_buff *skb = tp->tx_skb[entry].skb; 4380 u32 status; 4381 4382 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4383 if (status & DescOwn) 4384 break; 4385 4386 rtl8169_unmap_tx_skb(tp, entry); 4387 4388 if (skb) { 4389 pkts_compl++; 4390 bytes_compl += skb->len; 4391 napi_consume_skb(skb, budget); 4392 } 4393 dirty_tx++; 4394 } 4395 4396 if (tp->dirty_tx != dirty_tx) { 4397 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4398 4399 u64_stats_update_begin(&tp->tx_stats.syncp); 4400 tp->tx_stats.packets += pkts_compl; 4401 tp->tx_stats.bytes += bytes_compl; 4402 u64_stats_update_end(&tp->tx_stats.syncp); 4403 4404 tp->dirty_tx = dirty_tx; 4405 /* Sync with rtl8169_start_xmit: 4406 * - publish dirty_tx ring index (write barrier) 4407 * - refresh cur_tx ring index and queue status (read barrier) 4408 * May the current thread miss the stopped queue condition, 4409 * a racing xmit thread can only have a right view of the 4410 * ring status. 4411 */ 4412 smp_mb(); 4413 if (netif_queue_stopped(dev) && 4414 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4415 netif_wake_queue(dev); 4416 } 4417 /* 4418 * 8168 hack: TxPoll requests are lost when the Tx packets are 4419 * too close. Let's kick an extra TxPoll request when a burst 4420 * of start_xmit activity is detected (if it is not detected, 4421 * it is slow enough). -- FR 4422 */ 4423 if (tp->cur_tx != dirty_tx) 4424 rtl8169_doorbell(tp); 4425 } 4426 } 4427 4428 static inline int rtl8169_fragmented_frame(u32 status) 4429 { 4430 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4431 } 4432 4433 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4434 { 4435 u32 status = opts1 & RxProtoMask; 4436 4437 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4438 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4439 skb->ip_summed = CHECKSUM_UNNECESSARY; 4440 else 4441 skb_checksum_none_assert(skb); 4442 } 4443 4444 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4445 { 4446 unsigned int cur_rx, rx_left, count; 4447 struct device *d = tp_to_dev(tp); 4448 4449 cur_rx = tp->cur_rx; 4450 4451 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4452 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC; 4453 struct RxDesc *desc = tp->RxDescArray + entry; 4454 struct sk_buff *skb; 4455 const void *rx_buf; 4456 dma_addr_t addr; 4457 u32 status; 4458 4459 status = le32_to_cpu(desc->opts1); 4460 if (status & DescOwn) 4461 break; 4462 4463 /* This barrier is needed to keep us from reading 4464 * any other fields out of the Rx descriptor until 4465 * we know the status of DescOwn 4466 */ 4467 dma_rmb(); 4468 4469 if (unlikely(status & RxRES)) { 4470 if (net_ratelimit()) 4471 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4472 status); 4473 dev->stats.rx_errors++; 4474 if (status & (RxRWT | RxRUNT)) 4475 dev->stats.rx_length_errors++; 4476 if (status & RxCRC) 4477 dev->stats.rx_crc_errors++; 4478 4479 if (!(dev->features & NETIF_F_RXALL)) 4480 goto release_descriptor; 4481 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4482 goto release_descriptor; 4483 } 4484 4485 pkt_size = status & GENMASK(13, 0); 4486 if (likely(!(dev->features & NETIF_F_RXFCS))) 4487 pkt_size -= ETH_FCS_LEN; 4488 4489 /* The driver does not support incoming fragmented frames. 4490 * They are seen as a symptom of over-mtu sized frames. 4491 */ 4492 if (unlikely(rtl8169_fragmented_frame(status))) { 4493 dev->stats.rx_dropped++; 4494 dev->stats.rx_length_errors++; 4495 goto release_descriptor; 4496 } 4497 4498 skb = napi_alloc_skb(&tp->napi, pkt_size); 4499 if (unlikely(!skb)) { 4500 dev->stats.rx_dropped++; 4501 goto release_descriptor; 4502 } 4503 4504 addr = le64_to_cpu(desc->addr); 4505 rx_buf = page_address(tp->Rx_databuff[entry]); 4506 4507 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4508 prefetch(rx_buf); 4509 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4510 skb->tail += pkt_size; 4511 skb->len = pkt_size; 4512 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4513 4514 rtl8169_rx_csum(skb, status); 4515 skb->protocol = eth_type_trans(skb, dev); 4516 4517 rtl8169_rx_vlan_tag(desc, skb); 4518 4519 if (skb->pkt_type == PACKET_MULTICAST) 4520 dev->stats.multicast++; 4521 4522 napi_gro_receive(&tp->napi, skb); 4523 4524 u64_stats_update_begin(&tp->rx_stats.syncp); 4525 tp->rx_stats.packets++; 4526 tp->rx_stats.bytes += pkt_size; 4527 u64_stats_update_end(&tp->rx_stats.syncp); 4528 4529 release_descriptor: 4530 rtl8169_mark_to_asic(desc); 4531 } 4532 4533 count = cur_rx - tp->cur_rx; 4534 tp->cur_rx = cur_rx; 4535 4536 return count; 4537 } 4538 4539 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4540 { 4541 struct rtl8169_private *tp = dev_instance; 4542 u32 status = rtl_get_events(tp); 4543 4544 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 4545 !(status & tp->irq_mask)) 4546 return IRQ_NONE; 4547 4548 if (unlikely(status & SYSErr)) { 4549 rtl8169_pcierr_interrupt(tp->dev); 4550 goto out; 4551 } 4552 4553 if (status & LinkChg) 4554 phy_mac_interrupt(tp->phydev); 4555 4556 if (unlikely(status & RxFIFOOver && 4557 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4558 netif_stop_queue(tp->dev); 4559 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4560 } 4561 4562 rtl_irq_disable(tp); 4563 napi_schedule_irqoff(&tp->napi); 4564 out: 4565 rtl_ack_events(tp, status); 4566 4567 return IRQ_HANDLED; 4568 } 4569 4570 static void rtl_task(struct work_struct *work) 4571 { 4572 struct rtl8169_private *tp = 4573 container_of(work, struct rtl8169_private, wk.work); 4574 4575 rtnl_lock(); 4576 4577 if (!netif_running(tp->dev) || 4578 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4579 goto out_unlock; 4580 4581 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4582 rtl_reset_work(tp); 4583 netif_wake_queue(tp->dev); 4584 } 4585 out_unlock: 4586 rtnl_unlock(); 4587 } 4588 4589 static int rtl8169_poll(struct napi_struct *napi, int budget) 4590 { 4591 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4592 struct net_device *dev = tp->dev; 4593 int work_done; 4594 4595 work_done = rtl_rx(dev, tp, (u32) budget); 4596 4597 rtl_tx(dev, tp, budget); 4598 4599 if (work_done < budget) { 4600 napi_complete_done(napi, work_done); 4601 rtl_irq_enable(tp); 4602 } 4603 4604 return work_done; 4605 } 4606 4607 static void r8169_phylink_handler(struct net_device *ndev) 4608 { 4609 struct rtl8169_private *tp = netdev_priv(ndev); 4610 4611 if (netif_carrier_ok(ndev)) { 4612 rtl_link_chg_patch(tp); 4613 pm_request_resume(&tp->pci_dev->dev); 4614 } else { 4615 pm_runtime_idle(&tp->pci_dev->dev); 4616 } 4617 4618 if (net_ratelimit()) 4619 phy_print_status(tp->phydev); 4620 } 4621 4622 static int r8169_phy_connect(struct rtl8169_private *tp) 4623 { 4624 struct phy_device *phydev = tp->phydev; 4625 phy_interface_t phy_mode; 4626 int ret; 4627 4628 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4629 PHY_INTERFACE_MODE_MII; 4630 4631 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4632 phy_mode); 4633 if (ret) 4634 return ret; 4635 4636 if (!tp->supports_gmii) 4637 phy_set_max_speed(phydev, SPEED_100); 4638 4639 phy_support_asym_pause(phydev); 4640 4641 phy_attached_info(phydev); 4642 4643 return 0; 4644 } 4645 4646 static void rtl8169_down(struct rtl8169_private *tp) 4647 { 4648 /* Clear all task flags */ 4649 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4650 4651 phy_stop(tp->phydev); 4652 4653 rtl8169_update_counters(tp); 4654 4655 rtl8169_cleanup(tp, true); 4656 4657 rtl_pll_power_down(tp); 4658 } 4659 4660 static void rtl8169_up(struct rtl8169_private *tp) 4661 { 4662 rtl_pll_power_up(tp); 4663 rtl8169_init_phy(tp); 4664 napi_enable(&tp->napi); 4665 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4666 rtl_reset_work(tp); 4667 4668 phy_start(tp->phydev); 4669 } 4670 4671 static int rtl8169_close(struct net_device *dev) 4672 { 4673 struct rtl8169_private *tp = netdev_priv(dev); 4674 struct pci_dev *pdev = tp->pci_dev; 4675 4676 pm_runtime_get_sync(&pdev->dev); 4677 4678 netif_stop_queue(dev); 4679 rtl8169_down(tp); 4680 rtl8169_rx_clear(tp); 4681 4682 cancel_work_sync(&tp->wk.work); 4683 4684 phy_disconnect(tp->phydev); 4685 4686 pci_free_irq(pdev, 0, tp); 4687 4688 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4689 tp->RxPhyAddr); 4690 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4691 tp->TxPhyAddr); 4692 tp->TxDescArray = NULL; 4693 tp->RxDescArray = NULL; 4694 4695 pm_runtime_put_sync(&pdev->dev); 4696 4697 return 0; 4698 } 4699 4700 #ifdef CONFIG_NET_POLL_CONTROLLER 4701 static void rtl8169_netpoll(struct net_device *dev) 4702 { 4703 struct rtl8169_private *tp = netdev_priv(dev); 4704 4705 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4706 } 4707 #endif 4708 4709 static int rtl_open(struct net_device *dev) 4710 { 4711 struct rtl8169_private *tp = netdev_priv(dev); 4712 struct pci_dev *pdev = tp->pci_dev; 4713 int retval = -ENOMEM; 4714 4715 pm_runtime_get_sync(&pdev->dev); 4716 4717 /* 4718 * Rx and Tx descriptors needs 256 bytes alignment. 4719 * dma_alloc_coherent provides more. 4720 */ 4721 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4722 &tp->TxPhyAddr, GFP_KERNEL); 4723 if (!tp->TxDescArray) 4724 goto err_pm_runtime_put; 4725 4726 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4727 &tp->RxPhyAddr, GFP_KERNEL); 4728 if (!tp->RxDescArray) 4729 goto err_free_tx_0; 4730 4731 retval = rtl8169_init_ring(tp); 4732 if (retval < 0) 4733 goto err_free_rx_1; 4734 4735 rtl_request_firmware(tp); 4736 4737 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 4738 dev->name); 4739 if (retval < 0) 4740 goto err_release_fw_2; 4741 4742 retval = r8169_phy_connect(tp); 4743 if (retval) 4744 goto err_free_irq; 4745 4746 rtl8169_up(tp); 4747 rtl8169_init_counter_offsets(tp); 4748 netif_start_queue(dev); 4749 4750 pm_runtime_put_sync(&pdev->dev); 4751 out: 4752 return retval; 4753 4754 err_free_irq: 4755 pci_free_irq(pdev, 0, tp); 4756 err_release_fw_2: 4757 rtl_release_firmware(tp); 4758 rtl8169_rx_clear(tp); 4759 err_free_rx_1: 4760 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4761 tp->RxPhyAddr); 4762 tp->RxDescArray = NULL; 4763 err_free_tx_0: 4764 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4765 tp->TxPhyAddr); 4766 tp->TxDescArray = NULL; 4767 err_pm_runtime_put: 4768 pm_runtime_put_noidle(&pdev->dev); 4769 goto out; 4770 } 4771 4772 static void 4773 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4774 { 4775 struct rtl8169_private *tp = netdev_priv(dev); 4776 struct pci_dev *pdev = tp->pci_dev; 4777 struct rtl8169_counters *counters = tp->counters; 4778 unsigned int start; 4779 4780 pm_runtime_get_noresume(&pdev->dev); 4781 4782 netdev_stats_to_stats64(stats, &dev->stats); 4783 4784 do { 4785 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 4786 stats->rx_packets = tp->rx_stats.packets; 4787 stats->rx_bytes = tp->rx_stats.bytes; 4788 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 4789 4790 do { 4791 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 4792 stats->tx_packets = tp->tx_stats.packets; 4793 stats->tx_bytes = tp->tx_stats.bytes; 4794 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 4795 4796 /* 4797 * Fetch additional counter values missing in stats collected by driver 4798 * from tally counters. 4799 */ 4800 if (pm_runtime_active(&pdev->dev)) 4801 rtl8169_update_counters(tp); 4802 4803 /* 4804 * Subtract values fetched during initalization. 4805 * See rtl8169_init_counter_offsets for a description why we do that. 4806 */ 4807 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4808 le64_to_cpu(tp->tc_offset.tx_errors); 4809 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4810 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4811 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4812 le16_to_cpu(tp->tc_offset.tx_aborted); 4813 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4814 le16_to_cpu(tp->tc_offset.rx_missed); 4815 4816 pm_runtime_put_noidle(&pdev->dev); 4817 } 4818 4819 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4820 { 4821 netif_device_detach(tp->dev); 4822 4823 if (netif_running(tp->dev)) 4824 rtl8169_down(tp); 4825 } 4826 4827 #ifdef CONFIG_PM 4828 4829 static int __maybe_unused rtl8169_suspend(struct device *device) 4830 { 4831 struct rtl8169_private *tp = dev_get_drvdata(device); 4832 4833 rtnl_lock(); 4834 rtl8169_net_suspend(tp); 4835 rtnl_unlock(); 4836 4837 return 0; 4838 } 4839 4840 static int rtl8169_resume(struct device *device) 4841 { 4842 struct rtl8169_private *tp = dev_get_drvdata(device); 4843 4844 rtl_rar_set(tp, tp->dev->dev_addr); 4845 4846 if (tp->TxDescArray) 4847 rtl8169_up(tp); 4848 4849 netif_device_attach(tp->dev); 4850 4851 return 0; 4852 } 4853 4854 static int rtl8169_runtime_suspend(struct device *device) 4855 { 4856 struct rtl8169_private *tp = dev_get_drvdata(device); 4857 4858 if (!tp->TxDescArray) { 4859 netif_device_detach(tp->dev); 4860 return 0; 4861 } 4862 4863 rtnl_lock(); 4864 __rtl8169_set_wol(tp, WAKE_PHY); 4865 rtl8169_net_suspend(tp); 4866 rtnl_unlock(); 4867 4868 return 0; 4869 } 4870 4871 static int rtl8169_runtime_resume(struct device *device) 4872 { 4873 struct rtl8169_private *tp = dev_get_drvdata(device); 4874 4875 __rtl8169_set_wol(tp, tp->saved_wolopts); 4876 4877 return rtl8169_resume(device); 4878 } 4879 4880 static int rtl8169_runtime_idle(struct device *device) 4881 { 4882 struct rtl8169_private *tp = dev_get_drvdata(device); 4883 4884 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4885 pm_schedule_suspend(device, 10000); 4886 4887 return -EBUSY; 4888 } 4889 4890 static const struct dev_pm_ops rtl8169_pm_ops = { 4891 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4892 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4893 rtl8169_runtime_idle) 4894 }; 4895 4896 #endif /* CONFIG_PM */ 4897 4898 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4899 { 4900 /* WoL fails with 8168b when the receiver is disabled. */ 4901 switch (tp->mac_version) { 4902 case RTL_GIGA_MAC_VER_11: 4903 case RTL_GIGA_MAC_VER_12: 4904 case RTL_GIGA_MAC_VER_17: 4905 pci_clear_master(tp->pci_dev); 4906 4907 RTL_W8(tp, ChipCmd, CmdRxEnb); 4908 rtl_pci_commit(tp); 4909 break; 4910 default: 4911 break; 4912 } 4913 } 4914 4915 static void rtl_shutdown(struct pci_dev *pdev) 4916 { 4917 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4918 4919 rtnl_lock(); 4920 rtl8169_net_suspend(tp); 4921 rtnl_unlock(); 4922 4923 /* Restore original MAC address */ 4924 rtl_rar_set(tp, tp->dev->perm_addr); 4925 4926 if (system_state == SYSTEM_POWER_OFF) { 4927 if (tp->saved_wolopts) { 4928 rtl_wol_suspend_quirk(tp); 4929 rtl_wol_shutdown_quirk(tp); 4930 } 4931 4932 pci_wake_from_d3(pdev, true); 4933 pci_set_power_state(pdev, PCI_D3hot); 4934 } 4935 } 4936 4937 static void rtl_remove_one(struct pci_dev *pdev) 4938 { 4939 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4940 4941 if (pci_dev_run_wake(pdev)) 4942 pm_runtime_get_noresume(&pdev->dev); 4943 4944 unregister_netdev(tp->dev); 4945 4946 if (r8168_check_dash(tp)) 4947 rtl8168_driver_stop(tp); 4948 4949 rtl_release_firmware(tp); 4950 4951 /* restore original MAC address */ 4952 rtl_rar_set(tp, tp->dev->perm_addr); 4953 } 4954 4955 static const struct net_device_ops rtl_netdev_ops = { 4956 .ndo_open = rtl_open, 4957 .ndo_stop = rtl8169_close, 4958 .ndo_get_stats64 = rtl8169_get_stats64, 4959 .ndo_start_xmit = rtl8169_start_xmit, 4960 .ndo_features_check = rtl8169_features_check, 4961 .ndo_tx_timeout = rtl8169_tx_timeout, 4962 .ndo_validate_addr = eth_validate_addr, 4963 .ndo_change_mtu = rtl8169_change_mtu, 4964 .ndo_fix_features = rtl8169_fix_features, 4965 .ndo_set_features = rtl8169_set_features, 4966 .ndo_set_mac_address = rtl_set_mac_address, 4967 .ndo_do_ioctl = phy_do_ioctl_running, 4968 .ndo_set_rx_mode = rtl_set_rx_mode, 4969 #ifdef CONFIG_NET_POLL_CONTROLLER 4970 .ndo_poll_controller = rtl8169_netpoll, 4971 #endif 4972 4973 }; 4974 4975 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4976 { 4977 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4978 4979 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4980 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4981 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4982 /* special workaround needed */ 4983 tp->irq_mask |= RxFIFOOver; 4984 else 4985 tp->irq_mask |= RxOverflow; 4986 } 4987 4988 static int rtl_alloc_irq(struct rtl8169_private *tp) 4989 { 4990 unsigned int flags; 4991 4992 switch (tp->mac_version) { 4993 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4994 rtl_unlock_config_regs(tp); 4995 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4996 rtl_lock_config_regs(tp); 4997 /* fall through */ 4998 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4999 flags = PCI_IRQ_LEGACY; 5000 break; 5001 default: 5002 flags = PCI_IRQ_ALL_TYPES; 5003 break; 5004 } 5005 5006 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5007 } 5008 5009 static void rtl_read_mac_address(struct rtl8169_private *tp, 5010 u8 mac_addr[ETH_ALEN]) 5011 { 5012 /* Get MAC address */ 5013 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5014 u32 value = rtl_eri_read(tp, 0xe0); 5015 5016 mac_addr[0] = (value >> 0) & 0xff; 5017 mac_addr[1] = (value >> 8) & 0xff; 5018 mac_addr[2] = (value >> 16) & 0xff; 5019 mac_addr[3] = (value >> 24) & 0xff; 5020 5021 value = rtl_eri_read(tp, 0xe4); 5022 mac_addr[4] = (value >> 0) & 0xff; 5023 mac_addr[5] = (value >> 8) & 0xff; 5024 } else if (rtl_is_8125(tp)) { 5025 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5026 } 5027 } 5028 5029 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5030 { 5031 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5032 } 5033 5034 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5035 { 5036 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5037 } 5038 5039 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5040 { 5041 struct rtl8169_private *tp = mii_bus->priv; 5042 5043 if (phyaddr > 0) 5044 return -ENODEV; 5045 5046 return rtl_readphy(tp, phyreg); 5047 } 5048 5049 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5050 int phyreg, u16 val) 5051 { 5052 struct rtl8169_private *tp = mii_bus->priv; 5053 5054 if (phyaddr > 0) 5055 return -ENODEV; 5056 5057 rtl_writephy(tp, phyreg, val); 5058 5059 return 0; 5060 } 5061 5062 static int r8169_mdio_register(struct rtl8169_private *tp) 5063 { 5064 struct pci_dev *pdev = tp->pci_dev; 5065 struct mii_bus *new_bus; 5066 int ret; 5067 5068 new_bus = devm_mdiobus_alloc(&pdev->dev); 5069 if (!new_bus) 5070 return -ENOMEM; 5071 5072 new_bus->name = "r8169"; 5073 new_bus->priv = tp; 5074 new_bus->parent = &pdev->dev; 5075 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5076 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5077 5078 new_bus->read = r8169_mdio_read_reg; 5079 new_bus->write = r8169_mdio_write_reg; 5080 5081 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5082 if (ret) 5083 return ret; 5084 5085 tp->phydev = mdiobus_get_phy(new_bus, 0); 5086 if (!tp->phydev) { 5087 return -ENODEV; 5088 } else if (!tp->phydev->drv) { 5089 /* Most chip versions fail with the genphy driver. 5090 * Therefore ensure that the dedicated PHY driver is loaded. 5091 */ 5092 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5093 tp->phydev->phy_id); 5094 return -EUNATCH; 5095 } 5096 5097 /* PHY will be woken up in rtl_open() */ 5098 phy_suspend(tp->phydev); 5099 5100 return 0; 5101 } 5102 5103 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5104 { 5105 rtl_enable_rxdvgate(tp); 5106 5107 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5108 msleep(1); 5109 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5110 5111 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5112 r8168g_wait_ll_share_fifo_ready(tp); 5113 5114 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5115 r8168g_wait_ll_share_fifo_ready(tp); 5116 } 5117 5118 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5119 { 5120 rtl_enable_rxdvgate(tp); 5121 5122 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5123 msleep(1); 5124 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5125 5126 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5127 r8168g_wait_ll_share_fifo_ready(tp); 5128 5129 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5130 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5131 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5132 r8168g_wait_ll_share_fifo_ready(tp); 5133 } 5134 5135 static void rtl_hw_initialize(struct rtl8169_private *tp) 5136 { 5137 switch (tp->mac_version) { 5138 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5139 rtl8168ep_stop_cmac(tp); 5140 /* fall through */ 5141 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5142 rtl_hw_init_8168g(tp); 5143 break; 5144 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5145 rtl_hw_init_8125(tp); 5146 break; 5147 default: 5148 break; 5149 } 5150 } 5151 5152 static int rtl_jumbo_max(struct rtl8169_private *tp) 5153 { 5154 /* Non-GBit versions don't support jumbo frames */ 5155 if (!tp->supports_gmii) 5156 return 0; 5157 5158 switch (tp->mac_version) { 5159 /* RTL8169 */ 5160 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5161 return JUMBO_7K; 5162 /* RTL8168b */ 5163 case RTL_GIGA_MAC_VER_11: 5164 case RTL_GIGA_MAC_VER_12: 5165 case RTL_GIGA_MAC_VER_17: 5166 return JUMBO_4K; 5167 /* RTL8168c */ 5168 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5169 return JUMBO_6K; 5170 default: 5171 return JUMBO_9K; 5172 } 5173 } 5174 5175 static void rtl_disable_clk(void *data) 5176 { 5177 clk_disable_unprepare(data); 5178 } 5179 5180 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5181 { 5182 struct device *d = tp_to_dev(tp); 5183 struct clk *clk; 5184 int rc; 5185 5186 clk = devm_clk_get(d, "ether_clk"); 5187 if (IS_ERR(clk)) { 5188 rc = PTR_ERR(clk); 5189 if (rc == -ENOENT) 5190 /* clk-core allows NULL (for suspend / resume) */ 5191 rc = 0; 5192 else if (rc != -EPROBE_DEFER) 5193 dev_err(d, "failed to get clk: %d\n", rc); 5194 } else { 5195 tp->clk = clk; 5196 rc = clk_prepare_enable(clk); 5197 if (rc) 5198 dev_err(d, "failed to enable clk: %d\n", rc); 5199 else 5200 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5201 } 5202 5203 return rc; 5204 } 5205 5206 static void rtl_init_mac_address(struct rtl8169_private *tp) 5207 { 5208 struct net_device *dev = tp->dev; 5209 u8 *mac_addr = dev->dev_addr; 5210 int rc; 5211 5212 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5213 if (!rc) 5214 goto done; 5215 5216 rtl_read_mac_address(tp, mac_addr); 5217 if (is_valid_ether_addr(mac_addr)) 5218 goto done; 5219 5220 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5221 if (is_valid_ether_addr(mac_addr)) 5222 goto done; 5223 5224 eth_hw_addr_random(dev); 5225 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5226 done: 5227 rtl_rar_set(tp, mac_addr); 5228 } 5229 5230 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5231 { 5232 struct rtl8169_private *tp; 5233 int jumbo_max, region, rc; 5234 enum mac_version chipset; 5235 struct net_device *dev; 5236 u16 xid; 5237 5238 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5239 if (!dev) 5240 return -ENOMEM; 5241 5242 SET_NETDEV_DEV(dev, &pdev->dev); 5243 dev->netdev_ops = &rtl_netdev_ops; 5244 tp = netdev_priv(dev); 5245 tp->dev = dev; 5246 tp->pci_dev = pdev; 5247 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5248 tp->eee_adv = -1; 5249 tp->ocp_base = OCP_STD_PHY_BASE; 5250 5251 /* Get the *optional* external "ether_clk" used on some boards */ 5252 rc = rtl_get_ether_clk(tp); 5253 if (rc) 5254 return rc; 5255 5256 /* Disable ASPM completely as that cause random device stop working 5257 * problems as well as full system hangs for some PCIe devices users. 5258 */ 5259 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5260 PCIE_LINK_STATE_L1); 5261 tp->aspm_manageable = !rc; 5262 5263 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5264 rc = pcim_enable_device(pdev); 5265 if (rc < 0) { 5266 dev_err(&pdev->dev, "enable failure\n"); 5267 return rc; 5268 } 5269 5270 if (pcim_set_mwi(pdev) < 0) 5271 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5272 5273 /* use first MMIO region */ 5274 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5275 if (region < 0) { 5276 dev_err(&pdev->dev, "no MMIO resource found\n"); 5277 return -ENODEV; 5278 } 5279 5280 /* check for weird/broken PCI region reporting */ 5281 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5282 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5283 return -ENODEV; 5284 } 5285 5286 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5287 if (rc < 0) { 5288 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5289 return rc; 5290 } 5291 5292 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5293 5294 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5295 5296 /* Identify chip attached to board */ 5297 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5298 if (chipset == RTL_GIGA_MAC_NONE) { 5299 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid); 5300 return -ENODEV; 5301 } 5302 5303 tp->mac_version = chipset; 5304 5305 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5306 5307 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5308 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5309 dev->features |= NETIF_F_HIGHDMA; 5310 5311 rtl_init_rxcfg(tp); 5312 5313 rtl8169_irq_mask_and_ack(tp); 5314 5315 rtl_hw_initialize(tp); 5316 5317 rtl_hw_reset(tp); 5318 5319 pci_set_master(pdev); 5320 5321 rc = rtl_alloc_irq(tp); 5322 if (rc < 0) { 5323 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5324 return rc; 5325 } 5326 5327 INIT_WORK(&tp->wk.work, rtl_task); 5328 u64_stats_init(&tp->rx_stats.syncp); 5329 u64_stats_init(&tp->tx_stats.syncp); 5330 5331 rtl_init_mac_address(tp); 5332 5333 dev->ethtool_ops = &rtl8169_ethtool_ops; 5334 5335 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5336 5337 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5338 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5339 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5340 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5341 5342 /* 5343 * Pretend we are using VLANs; This bypasses a nasty bug where 5344 * Interrupts stop flowing on high load on 8110SCd controllers. 5345 */ 5346 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5347 /* Disallow toggling */ 5348 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5349 5350 if (rtl_chip_supports_csum_v2(tp)) 5351 dev->hw_features |= NETIF_F_IPV6_CSUM; 5352 5353 dev->features |= dev->hw_features; 5354 5355 /* There has been a number of reports that using SG/TSO results in 5356 * tx timeouts. However for a lot of people SG/TSO works fine. 5357 * Therefore disable both features by default, but allow users to 5358 * enable them. Use at own risk! 5359 */ 5360 if (rtl_chip_supports_csum_v2(tp)) { 5361 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5362 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5363 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5364 } else { 5365 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5366 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5367 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5368 } 5369 5370 dev->hw_features |= NETIF_F_RXALL; 5371 dev->hw_features |= NETIF_F_RXFCS; 5372 5373 /* configure chip for default features */ 5374 rtl8169_set_features(dev, dev->features); 5375 5376 jumbo_max = rtl_jumbo_max(tp); 5377 if (jumbo_max) 5378 dev->max_mtu = jumbo_max; 5379 5380 rtl_set_irq_mask(tp); 5381 5382 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5383 5384 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5385 &tp->counters_phys_addr, 5386 GFP_KERNEL); 5387 if (!tp->counters) 5388 return -ENOMEM; 5389 5390 pci_set_drvdata(pdev, tp); 5391 5392 rc = r8169_mdio_register(tp); 5393 if (rc) 5394 return rc; 5395 5396 /* chip gets powered up in rtl_open() */ 5397 rtl_pll_power_down(tp); 5398 5399 rc = register_netdev(dev); 5400 if (rc) 5401 return rc; 5402 5403 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5404 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5405 pci_irq_vector(pdev, 0)); 5406 5407 if (jumbo_max) 5408 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5409 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5410 "ok" : "ko"); 5411 5412 if (r8168_check_dash(tp)) { 5413 netdev_info(dev, "DASH enabled\n"); 5414 rtl8168_driver_start(tp); 5415 } 5416 5417 if (pci_dev_run_wake(pdev)) 5418 pm_runtime_put_sync(&pdev->dev); 5419 5420 return 0; 5421 } 5422 5423 static struct pci_driver rtl8169_pci_driver = { 5424 .name = MODULENAME, 5425 .id_table = rtl8169_pci_tbl, 5426 .probe = rtl_init_one, 5427 .remove = rtl_remove_one, 5428 .shutdown = rtl_shutdown, 5429 #ifdef CONFIG_PM 5430 .driver.pm = &rtl8169_pm_ops, 5431 #endif 5432 }; 5433 5434 module_pci_driver(rtl8169_pci_driver); 5435