1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/pci-aspm.h> 32 #include <linux/ipv6.h> 33 #include <net/ip6_checksum.h> 34 35 #include "r8169_firmware.h" 36 37 #define MODULENAME "r8169" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 58 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 59 60 #define R8169_MSG_DEFAULT \ 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 62 63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 65 #define MC_FILTER_LIMIT 32 66 67 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 69 70 #define R8169_REGS_SIZE 256 71 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 73 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 enum mac_version { 88 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */ 89 RTL_GIGA_MAC_VER_02, 90 RTL_GIGA_MAC_VER_03, 91 RTL_GIGA_MAC_VER_04, 92 RTL_GIGA_MAC_VER_05, 93 RTL_GIGA_MAC_VER_06, 94 RTL_GIGA_MAC_VER_07, 95 RTL_GIGA_MAC_VER_08, 96 RTL_GIGA_MAC_VER_09, 97 RTL_GIGA_MAC_VER_10, 98 RTL_GIGA_MAC_VER_11, 99 RTL_GIGA_MAC_VER_12, 100 RTL_GIGA_MAC_VER_13, 101 RTL_GIGA_MAC_VER_14, 102 RTL_GIGA_MAC_VER_15, 103 RTL_GIGA_MAC_VER_16, 104 RTL_GIGA_MAC_VER_17, 105 RTL_GIGA_MAC_VER_18, 106 RTL_GIGA_MAC_VER_19, 107 RTL_GIGA_MAC_VER_20, 108 RTL_GIGA_MAC_VER_21, 109 RTL_GIGA_MAC_VER_22, 110 RTL_GIGA_MAC_VER_23, 111 RTL_GIGA_MAC_VER_24, 112 RTL_GIGA_MAC_VER_25, 113 RTL_GIGA_MAC_VER_26, 114 RTL_GIGA_MAC_VER_27, 115 RTL_GIGA_MAC_VER_28, 116 RTL_GIGA_MAC_VER_29, 117 RTL_GIGA_MAC_VER_30, 118 RTL_GIGA_MAC_VER_31, 119 RTL_GIGA_MAC_VER_32, 120 RTL_GIGA_MAC_VER_33, 121 RTL_GIGA_MAC_VER_34, 122 RTL_GIGA_MAC_VER_35, 123 RTL_GIGA_MAC_VER_36, 124 RTL_GIGA_MAC_VER_37, 125 RTL_GIGA_MAC_VER_38, 126 RTL_GIGA_MAC_VER_39, 127 RTL_GIGA_MAC_VER_40, 128 RTL_GIGA_MAC_VER_41, 129 RTL_GIGA_MAC_VER_42, 130 RTL_GIGA_MAC_VER_43, 131 RTL_GIGA_MAC_VER_44, 132 RTL_GIGA_MAC_VER_45, 133 RTL_GIGA_MAC_VER_46, 134 RTL_GIGA_MAC_VER_47, 135 RTL_GIGA_MAC_VER_48, 136 RTL_GIGA_MAC_VER_49, 137 RTL_GIGA_MAC_VER_50, 138 RTL_GIGA_MAC_VER_51, 139 RTL_GIGA_MAC_VER_60, 140 RTL_GIGA_MAC_VER_61, 141 RTL_GIGA_MAC_NONE 142 }; 143 144 #define JUMBO_1K ETH_DATA_LEN 145 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 146 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 147 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 148 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 149 150 static const struct { 151 const char *name; 152 const char *fw_name; 153 } rtl_chip_infos[] = { 154 /* PCI devices. */ 155 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 156 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 157 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 158 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 159 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 160 /* PCI-E devices. */ 161 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 162 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 163 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 164 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 165 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 166 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 167 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 168 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 169 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 170 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 171 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 172 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 173 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 174 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 175 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 176 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 177 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 178 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 179 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 180 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 181 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 182 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 183 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 184 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 185 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 186 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 187 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 188 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 189 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 190 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 191 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 192 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 193 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 194 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 195 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 196 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 197 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 198 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 199 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 200 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 201 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 202 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 203 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 204 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 205 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 206 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 207 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 208 }; 209 210 static const struct pci_device_id rtl8169_pci_tbl[] = { 211 { PCI_VDEVICE(REALTEK, 0x2502) }, 212 { PCI_VDEVICE(REALTEK, 0x2600) }, 213 { PCI_VDEVICE(REALTEK, 0x8129) }, 214 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 215 { PCI_VDEVICE(REALTEK, 0x8161) }, 216 { PCI_VDEVICE(REALTEK, 0x8167) }, 217 { PCI_VDEVICE(REALTEK, 0x8168) }, 218 { PCI_VDEVICE(NCUBE, 0x8168) }, 219 { PCI_VDEVICE(REALTEK, 0x8169) }, 220 { PCI_VENDOR_ID_DLINK, 0x4300, 221 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 222 { PCI_VDEVICE(DLINK, 0x4300) }, 223 { PCI_VDEVICE(DLINK, 0x4302) }, 224 { PCI_VDEVICE(AT, 0xc107) }, 225 { PCI_VDEVICE(USR, 0x0116) }, 226 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 227 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 228 { PCI_VDEVICE(REALTEK, 0x8125) }, 229 { PCI_VDEVICE(REALTEK, 0x3000) }, 230 {} 231 }; 232 233 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 234 235 static struct { 236 u32 msg_enable; 237 } debug = { -1 }; 238 239 enum rtl_registers { 240 MAC0 = 0, /* Ethernet hardware address. */ 241 MAC4 = 4, 242 MAR0 = 8, /* Multicast filter. */ 243 CounterAddrLow = 0x10, 244 CounterAddrHigh = 0x14, 245 TxDescStartAddrLow = 0x20, 246 TxDescStartAddrHigh = 0x24, 247 TxHDescStartAddrLow = 0x28, 248 TxHDescStartAddrHigh = 0x2c, 249 FLASH = 0x30, 250 ERSR = 0x36, 251 ChipCmd = 0x37, 252 TxPoll = 0x38, 253 IntrMask = 0x3c, 254 IntrStatus = 0x3e, 255 256 TxConfig = 0x40, 257 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 258 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 259 260 RxConfig = 0x44, 261 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 262 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 263 #define RXCFG_FIFO_SHIFT 13 264 /* No threshold before first PCI xfer */ 265 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 266 #define RX_EARLY_OFF (1 << 11) 267 #define RXCFG_DMA_SHIFT 8 268 /* Unlimited maximum PCI burst. */ 269 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 270 271 RxMissed = 0x4c, 272 Cfg9346 = 0x50, 273 Config0 = 0x51, 274 Config1 = 0x52, 275 Config2 = 0x53, 276 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 277 278 Config3 = 0x54, 279 Config4 = 0x55, 280 Config5 = 0x56, 281 PHYAR = 0x60, 282 PHYstatus = 0x6c, 283 RxMaxSize = 0xda, 284 CPlusCmd = 0xe0, 285 IntrMitigate = 0xe2, 286 287 #define RTL_COALESCE_MASK 0x0f 288 #define RTL_COALESCE_SHIFT 4 289 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 290 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 291 292 RxDescAddrLow = 0xe4, 293 RxDescAddrHigh = 0xe8, 294 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 295 296 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 297 298 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 299 300 #define TxPacketMax (8064 >> 7) 301 #define EarlySize 0x27 302 303 FuncEvent = 0xf0, 304 FuncEventMask = 0xf4, 305 FuncPresetState = 0xf8, 306 IBCR0 = 0xf8, 307 IBCR2 = 0xf9, 308 IBIMR0 = 0xfa, 309 IBISR0 = 0xfb, 310 FuncForceEvent = 0xfc, 311 }; 312 313 enum rtl8168_8101_registers { 314 CSIDR = 0x64, 315 CSIAR = 0x68, 316 #define CSIAR_FLAG 0x80000000 317 #define CSIAR_WRITE_CMD 0x80000000 318 #define CSIAR_BYTE_ENABLE 0x0000f000 319 #define CSIAR_ADDR_MASK 0x00000fff 320 PMCH = 0x6f, 321 EPHYAR = 0x80, 322 #define EPHYAR_FLAG 0x80000000 323 #define EPHYAR_WRITE_CMD 0x80000000 324 #define EPHYAR_REG_MASK 0x1f 325 #define EPHYAR_REG_SHIFT 16 326 #define EPHYAR_DATA_MASK 0xffff 327 DLLPR = 0xd0, 328 #define PFM_EN (1 << 6) 329 #define TX_10M_PS_EN (1 << 7) 330 DBG_REG = 0xd1, 331 #define FIX_NAK_1 (1 << 4) 332 #define FIX_NAK_2 (1 << 3) 333 TWSI = 0xd2, 334 MCU = 0xd3, 335 #define NOW_IS_OOB (1 << 7) 336 #define TX_EMPTY (1 << 5) 337 #define RX_EMPTY (1 << 4) 338 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 339 #define EN_NDP (1 << 3) 340 #define EN_OOB_RESET (1 << 2) 341 #define LINK_LIST_RDY (1 << 1) 342 EFUSEAR = 0xdc, 343 #define EFUSEAR_FLAG 0x80000000 344 #define EFUSEAR_WRITE_CMD 0x80000000 345 #define EFUSEAR_READ_CMD 0x00000000 346 #define EFUSEAR_REG_MASK 0x03ff 347 #define EFUSEAR_REG_SHIFT 8 348 #define EFUSEAR_DATA_MASK 0xff 349 MISC_1 = 0xf2, 350 #define PFM_D3COLD_EN (1 << 6) 351 }; 352 353 enum rtl8168_registers { 354 LED_FREQ = 0x1a, 355 EEE_LED = 0x1b, 356 ERIDR = 0x70, 357 ERIAR = 0x74, 358 #define ERIAR_FLAG 0x80000000 359 #define ERIAR_WRITE_CMD 0x80000000 360 #define ERIAR_READ_CMD 0x00000000 361 #define ERIAR_ADDR_BYTE_ALIGN 4 362 #define ERIAR_TYPE_SHIFT 16 363 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 364 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 365 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 366 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 367 #define ERIAR_MASK_SHIFT 12 368 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 369 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 370 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 371 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 372 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 373 EPHY_RXER_NUM = 0x7c, 374 OCPDR = 0xb0, /* OCP GPHY access */ 375 #define OCPDR_WRITE_CMD 0x80000000 376 #define OCPDR_READ_CMD 0x00000000 377 #define OCPDR_REG_MASK 0x7f 378 #define OCPDR_GPHY_REG_SHIFT 16 379 #define OCPDR_DATA_MASK 0xffff 380 OCPAR = 0xb4, 381 #define OCPAR_FLAG 0x80000000 382 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 383 #define OCPAR_GPHY_READ_CMD 0x0000f060 384 GPHY_OCP = 0xb8, 385 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 386 MISC = 0xf0, /* 8168e only. */ 387 #define TXPLA_RST (1 << 29) 388 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 389 #define PWM_EN (1 << 22) 390 #define RXDV_GATED_EN (1 << 19) 391 #define EARLY_TALLY_EN (1 << 16) 392 }; 393 394 enum rtl8125_registers { 395 IntrMask_8125 = 0x38, 396 IntrStatus_8125 = 0x3c, 397 TxPoll_8125 = 0x90, 398 MAC0_BKP = 0x19e0, 399 }; 400 401 #define RX_VLAN_INNER_8125 BIT(22) 402 #define RX_VLAN_OUTER_8125 BIT(23) 403 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 404 405 #define RX_FETCH_DFLT_8125 (8 << 27) 406 407 enum rtl_register_content { 408 /* InterruptStatusBits */ 409 SYSErr = 0x8000, 410 PCSTimeout = 0x4000, 411 SWInt = 0x0100, 412 TxDescUnavail = 0x0080, 413 RxFIFOOver = 0x0040, 414 LinkChg = 0x0020, 415 RxOverflow = 0x0010, 416 TxErr = 0x0008, 417 TxOK = 0x0004, 418 RxErr = 0x0002, 419 RxOK = 0x0001, 420 421 /* RxStatusDesc */ 422 RxRWT = (1 << 22), 423 RxRES = (1 << 21), 424 RxRUNT = (1 << 20), 425 RxCRC = (1 << 19), 426 427 /* ChipCmdBits */ 428 StopReq = 0x80, 429 CmdReset = 0x10, 430 CmdRxEnb = 0x08, 431 CmdTxEnb = 0x04, 432 RxBufEmpty = 0x01, 433 434 /* TXPoll register p.5 */ 435 HPQ = 0x80, /* Poll cmd on the high prio queue */ 436 NPQ = 0x40, /* Poll cmd on the low prio queue */ 437 FSWInt = 0x01, /* Forced software interrupt */ 438 439 /* Cfg9346Bits */ 440 Cfg9346_Lock = 0x00, 441 Cfg9346_Unlock = 0xc0, 442 443 /* rx_mode_bits */ 444 AcceptErr = 0x20, 445 AcceptRunt = 0x10, 446 AcceptBroadcast = 0x08, 447 AcceptMulticast = 0x04, 448 AcceptMyPhys = 0x02, 449 AcceptAllPhys = 0x01, 450 #define RX_CONFIG_ACCEPT_MASK 0x3f 451 452 /* TxConfigBits */ 453 TxInterFrameGapShift = 24, 454 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 455 456 /* Config1 register p.24 */ 457 LEDS1 = (1 << 7), 458 LEDS0 = (1 << 6), 459 Speed_down = (1 << 4), 460 MEMMAP = (1 << 3), 461 IOMAP = (1 << 2), 462 VPD = (1 << 1), 463 PMEnable = (1 << 0), /* Power Management Enable */ 464 465 /* Config2 register p. 25 */ 466 ClkReqEn = (1 << 7), /* Clock Request Enable */ 467 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 468 PCI_Clock_66MHz = 0x01, 469 PCI_Clock_33MHz = 0x00, 470 471 /* Config3 register p.25 */ 472 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 473 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 474 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 475 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 476 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 477 478 /* Config4 register */ 479 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 480 481 /* Config5 register p.27 */ 482 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 483 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 484 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 485 Spi_en = (1 << 3), 486 LanWake = (1 << 1), /* LanWake enable/disable */ 487 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 488 ASPM_en = (1 << 0), /* ASPM enable */ 489 490 /* CPlusCmd p.31 */ 491 EnableBist = (1 << 15), // 8168 8101 492 Mac_dbgo_oe = (1 << 14), // 8168 8101 493 Normal_mode = (1 << 13), // unused 494 Force_half_dup = (1 << 12), // 8168 8101 495 Force_rxflow_en = (1 << 11), // 8168 8101 496 Force_txflow_en = (1 << 10), // 8168 8101 497 Cxpl_dbg_sel = (1 << 9), // 8168 8101 498 ASF = (1 << 8), // 8168 8101 499 PktCntrDisable = (1 << 7), // 8168 8101 500 Mac_dbgo_sel = 0x001c, // 8168 501 RxVlan = (1 << 6), 502 RxChkSum = (1 << 5), 503 PCIDAC = (1 << 4), 504 PCIMulRW = (1 << 3), 505 #define INTT_MASK GENMASK(1, 0) 506 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 507 508 /* rtl8169_PHYstatus */ 509 TBI_Enable = 0x80, 510 TxFlowCtrl = 0x40, 511 RxFlowCtrl = 0x20, 512 _1000bpsF = 0x10, 513 _100bps = 0x08, 514 _10bps = 0x04, 515 LinkStatus = 0x02, 516 FullDup = 0x01, 517 518 /* ResetCounterCommand */ 519 CounterReset = 0x1, 520 521 /* DumpCounterCommand */ 522 CounterDump = 0x8, 523 524 /* magic enable v2 */ 525 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 526 }; 527 528 enum rtl_desc_bit { 529 /* First doubleword. */ 530 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 531 RingEnd = (1 << 30), /* End of descriptor ring */ 532 FirstFrag = (1 << 29), /* First segment of a packet */ 533 LastFrag = (1 << 28), /* Final segment of a packet */ 534 }; 535 536 /* Generic case. */ 537 enum rtl_tx_desc_bit { 538 /* First doubleword. */ 539 TD_LSO = (1 << 27), /* Large Send Offload */ 540 #define TD_MSS_MAX 0x07ffu /* MSS value */ 541 542 /* Second doubleword. */ 543 TxVlanTag = (1 << 17), /* Add VLAN tag */ 544 }; 545 546 /* 8169, 8168b and 810x except 8102e. */ 547 enum rtl_tx_desc_bit_0 { 548 /* First doubleword. */ 549 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 550 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 551 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 552 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 553 }; 554 555 /* 8102e, 8168c and beyond. */ 556 enum rtl_tx_desc_bit_1 { 557 /* First doubleword. */ 558 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 559 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 560 #define GTTCPHO_SHIFT 18 561 #define GTTCPHO_MAX 0x7f 562 563 /* Second doubleword. */ 564 #define TCPHO_SHIFT 18 565 #define TCPHO_MAX 0x3ff 566 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 567 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 568 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 569 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 570 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 571 }; 572 573 enum rtl_rx_desc_bit { 574 /* Rx private */ 575 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 576 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 577 578 #define RxProtoUDP (PID1) 579 #define RxProtoTCP (PID0) 580 #define RxProtoIP (PID1 | PID0) 581 #define RxProtoMask RxProtoIP 582 583 IPFail = (1 << 16), /* IP checksum failed */ 584 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 585 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 586 RxVlanTag = (1 << 16), /* VLAN tag available */ 587 }; 588 589 #define RsvdMask 0x3fffc000 590 591 #define RTL_GSO_MAX_SIZE_V1 32000 592 #define RTL_GSO_MAX_SEGS_V1 24 593 #define RTL_GSO_MAX_SIZE_V2 64000 594 #define RTL_GSO_MAX_SEGS_V2 64 595 596 struct TxDesc { 597 __le32 opts1; 598 __le32 opts2; 599 __le64 addr; 600 }; 601 602 struct RxDesc { 603 __le32 opts1; 604 __le32 opts2; 605 __le64 addr; 606 }; 607 608 struct ring_info { 609 struct sk_buff *skb; 610 u32 len; 611 }; 612 613 struct rtl8169_counters { 614 __le64 tx_packets; 615 __le64 rx_packets; 616 __le64 tx_errors; 617 __le32 rx_errors; 618 __le16 rx_missed; 619 __le16 align_errors; 620 __le32 tx_one_collision; 621 __le32 tx_multi_collision; 622 __le64 rx_unicast; 623 __le64 rx_broadcast; 624 __le32 rx_multicast; 625 __le16 tx_aborted; 626 __le16 tx_underun; 627 }; 628 629 struct rtl8169_tc_offsets { 630 bool inited; 631 __le64 tx_errors; 632 __le32 tx_multi_collision; 633 __le16 tx_aborted; 634 }; 635 636 enum rtl_flag { 637 RTL_FLAG_TASK_ENABLED = 0, 638 RTL_FLAG_TASK_RESET_PENDING, 639 RTL_FLAG_MAX 640 }; 641 642 struct rtl8169_stats { 643 u64 packets; 644 u64 bytes; 645 struct u64_stats_sync syncp; 646 }; 647 648 struct rtl8169_private { 649 void __iomem *mmio_addr; /* memory map physical address */ 650 struct pci_dev *pci_dev; 651 struct net_device *dev; 652 struct phy_device *phydev; 653 struct napi_struct napi; 654 u32 msg_enable; 655 enum mac_version mac_version; 656 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 657 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 658 u32 dirty_tx; 659 struct rtl8169_stats rx_stats; 660 struct rtl8169_stats tx_stats; 661 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 662 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 663 dma_addr_t TxPhyAddr; 664 dma_addr_t RxPhyAddr; 665 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 666 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 667 u16 cp_cmd; 668 u32 irq_mask; 669 struct clk *clk; 670 671 struct { 672 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 673 struct mutex mutex; 674 struct work_struct work; 675 } wk; 676 677 unsigned irq_enabled:1; 678 unsigned supports_gmii:1; 679 unsigned aspm_manageable:1; 680 dma_addr_t counters_phys_addr; 681 struct rtl8169_counters *counters; 682 struct rtl8169_tc_offsets tc_offset; 683 u32 saved_wolopts; 684 685 const char *fw_name; 686 struct rtl_fw *rtl_fw; 687 688 u32 ocp_base; 689 }; 690 691 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 692 693 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 694 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 695 module_param_named(debug, debug.msg_enable, int, 0); 696 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 697 MODULE_SOFTDEP("pre: realtek"); 698 MODULE_LICENSE("GPL"); 699 MODULE_FIRMWARE(FIRMWARE_8168D_1); 700 MODULE_FIRMWARE(FIRMWARE_8168D_2); 701 MODULE_FIRMWARE(FIRMWARE_8168E_1); 702 MODULE_FIRMWARE(FIRMWARE_8168E_2); 703 MODULE_FIRMWARE(FIRMWARE_8168E_3); 704 MODULE_FIRMWARE(FIRMWARE_8105E_1); 705 MODULE_FIRMWARE(FIRMWARE_8168F_1); 706 MODULE_FIRMWARE(FIRMWARE_8168F_2); 707 MODULE_FIRMWARE(FIRMWARE_8402_1); 708 MODULE_FIRMWARE(FIRMWARE_8411_1); 709 MODULE_FIRMWARE(FIRMWARE_8411_2); 710 MODULE_FIRMWARE(FIRMWARE_8106E_1); 711 MODULE_FIRMWARE(FIRMWARE_8106E_2); 712 MODULE_FIRMWARE(FIRMWARE_8168G_2); 713 MODULE_FIRMWARE(FIRMWARE_8168G_3); 714 MODULE_FIRMWARE(FIRMWARE_8168H_1); 715 MODULE_FIRMWARE(FIRMWARE_8168H_2); 716 MODULE_FIRMWARE(FIRMWARE_8107E_1); 717 MODULE_FIRMWARE(FIRMWARE_8107E_2); 718 MODULE_FIRMWARE(FIRMWARE_8125A_3); 719 720 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 721 { 722 return &tp->pci_dev->dev; 723 } 724 725 static void rtl_lock_work(struct rtl8169_private *tp) 726 { 727 mutex_lock(&tp->wk.mutex); 728 } 729 730 static void rtl_unlock_work(struct rtl8169_private *tp) 731 { 732 mutex_unlock(&tp->wk.mutex); 733 } 734 735 static void rtl_lock_config_regs(struct rtl8169_private *tp) 736 { 737 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 738 } 739 740 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 741 { 742 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 743 } 744 745 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force) 746 { 747 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL, 748 PCI_EXP_DEVCTL_READRQ, force); 749 } 750 751 static bool rtl_is_8125(struct rtl8169_private *tp) 752 { 753 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 754 } 755 756 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 757 { 758 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 759 tp->mac_version != RTL_GIGA_MAC_VER_39 && 760 tp->mac_version <= RTL_GIGA_MAC_VER_51; 761 } 762 763 static bool rtl_supports_eee(struct rtl8169_private *tp) 764 { 765 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 766 tp->mac_version != RTL_GIGA_MAC_VER_37 && 767 tp->mac_version != RTL_GIGA_MAC_VER_39; 768 } 769 770 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 771 { 772 int i; 773 774 for (i = 0; i < ETH_ALEN; i++) 775 mac[i] = RTL_R8(tp, reg + i); 776 } 777 778 struct rtl_cond { 779 bool (*check)(struct rtl8169_private *); 780 const char *msg; 781 }; 782 783 static void rtl_udelay(unsigned int d) 784 { 785 udelay(d); 786 } 787 788 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 789 void (*delay)(unsigned int), unsigned int d, int n, 790 bool high) 791 { 792 int i; 793 794 for (i = 0; i < n; i++) { 795 if (c->check(tp) == high) 796 return true; 797 delay(d); 798 } 799 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 800 c->msg, !high, n, d); 801 return false; 802 } 803 804 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 805 const struct rtl_cond *c, 806 unsigned int d, int n) 807 { 808 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 809 } 810 811 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 812 const struct rtl_cond *c, 813 unsigned int d, int n) 814 { 815 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 816 } 817 818 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 819 const struct rtl_cond *c, 820 unsigned int d, int n) 821 { 822 return rtl_loop_wait(tp, c, msleep, d, n, true); 823 } 824 825 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 826 const struct rtl_cond *c, 827 unsigned int d, int n) 828 { 829 return rtl_loop_wait(tp, c, msleep, d, n, false); 830 } 831 832 #define DECLARE_RTL_COND(name) \ 833 static bool name ## _check(struct rtl8169_private *); \ 834 \ 835 static const struct rtl_cond name = { \ 836 .check = name ## _check, \ 837 .msg = #name \ 838 }; \ 839 \ 840 static bool name ## _check(struct rtl8169_private *tp) 841 842 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 843 { 844 if (reg & 0xffff0001) { 845 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 846 return true; 847 } 848 return false; 849 } 850 851 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 852 { 853 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 854 } 855 856 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 857 { 858 if (rtl_ocp_reg_failure(tp, reg)) 859 return; 860 861 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 862 863 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 864 } 865 866 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 867 { 868 if (rtl_ocp_reg_failure(tp, reg)) 869 return 0; 870 871 RTL_W32(tp, GPHY_OCP, reg << 15); 872 873 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 874 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 875 } 876 877 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 878 { 879 if (rtl_ocp_reg_failure(tp, reg)) 880 return; 881 882 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 883 } 884 885 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 886 { 887 if (rtl_ocp_reg_failure(tp, reg)) 888 return 0; 889 890 RTL_W32(tp, OCPDR, reg << 15); 891 892 return RTL_R32(tp, OCPDR); 893 } 894 895 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 896 u16 set) 897 { 898 u16 data = r8168_mac_ocp_read(tp, reg); 899 900 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 901 } 902 903 #define OCP_STD_PHY_BASE 0xa400 904 905 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 906 { 907 if (reg == 0x1f) { 908 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 909 return; 910 } 911 912 if (tp->ocp_base != OCP_STD_PHY_BASE) 913 reg -= 0x10; 914 915 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 916 } 917 918 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 919 { 920 if (tp->ocp_base != OCP_STD_PHY_BASE) 921 reg -= 0x10; 922 923 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 924 } 925 926 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 927 { 928 if (reg == 0x1f) { 929 tp->ocp_base = value << 4; 930 return; 931 } 932 933 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 934 } 935 936 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 937 { 938 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 939 } 940 941 DECLARE_RTL_COND(rtl_phyar_cond) 942 { 943 return RTL_R32(tp, PHYAR) & 0x80000000; 944 } 945 946 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 947 { 948 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 949 950 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 951 /* 952 * According to hardware specs a 20us delay is required after write 953 * complete indication, but before sending next command. 954 */ 955 udelay(20); 956 } 957 958 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 959 { 960 int value; 961 962 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 963 964 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 965 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 966 967 /* 968 * According to hardware specs a 20us delay is required after read 969 * complete indication, but before sending next command. 970 */ 971 udelay(20); 972 973 return value; 974 } 975 976 DECLARE_RTL_COND(rtl_ocpar_cond) 977 { 978 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 979 } 980 981 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 982 { 983 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 984 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 985 RTL_W32(tp, EPHY_RXER_NUM, 0); 986 987 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 988 } 989 990 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 991 { 992 r8168dp_1_mdio_access(tp, reg, 993 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 994 } 995 996 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 997 { 998 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 999 1000 mdelay(1); 1001 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1002 RTL_W32(tp, EPHY_RXER_NUM, 0); 1003 1004 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1005 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1006 } 1007 1008 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1009 1010 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1011 { 1012 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1013 } 1014 1015 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1016 { 1017 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1018 } 1019 1020 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1021 { 1022 r8168dp_2_mdio_start(tp); 1023 1024 r8169_mdio_write(tp, reg, value); 1025 1026 r8168dp_2_mdio_stop(tp); 1027 } 1028 1029 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1030 { 1031 int value; 1032 1033 r8168dp_2_mdio_start(tp); 1034 1035 value = r8169_mdio_read(tp, reg); 1036 1037 r8168dp_2_mdio_stop(tp); 1038 1039 return value; 1040 } 1041 1042 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1043 { 1044 switch (tp->mac_version) { 1045 case RTL_GIGA_MAC_VER_27: 1046 r8168dp_1_mdio_write(tp, location, val); 1047 break; 1048 case RTL_GIGA_MAC_VER_28: 1049 case RTL_GIGA_MAC_VER_31: 1050 r8168dp_2_mdio_write(tp, location, val); 1051 break; 1052 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1053 r8168g_mdio_write(tp, location, val); 1054 break; 1055 default: 1056 r8169_mdio_write(tp, location, val); 1057 break; 1058 } 1059 } 1060 1061 static int rtl_readphy(struct rtl8169_private *tp, int location) 1062 { 1063 switch (tp->mac_version) { 1064 case RTL_GIGA_MAC_VER_27: 1065 return r8168dp_1_mdio_read(tp, location); 1066 case RTL_GIGA_MAC_VER_28: 1067 case RTL_GIGA_MAC_VER_31: 1068 return r8168dp_2_mdio_read(tp, location); 1069 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1070 return r8168g_mdio_read(tp, location); 1071 default: 1072 return r8169_mdio_read(tp, location); 1073 } 1074 } 1075 1076 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) 1077 { 1078 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); 1079 } 1080 1081 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) 1082 { 1083 int val; 1084 1085 val = rtl_readphy(tp, reg_addr); 1086 rtl_writephy(tp, reg_addr, (val & ~m) | p); 1087 } 1088 1089 DECLARE_RTL_COND(rtl_ephyar_cond) 1090 { 1091 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1092 } 1093 1094 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1095 { 1096 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1097 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1098 1099 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1100 1101 udelay(10); 1102 } 1103 1104 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1105 { 1106 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1107 1108 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1109 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1110 } 1111 1112 DECLARE_RTL_COND(rtl_eriar_cond) 1113 { 1114 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1115 } 1116 1117 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1118 u32 val, int type) 1119 { 1120 BUG_ON((addr & 3) || (mask == 0)); 1121 RTL_W32(tp, ERIDR, val); 1122 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1123 1124 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1125 } 1126 1127 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1128 u32 val) 1129 { 1130 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1131 } 1132 1133 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1134 { 1135 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1136 1137 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1138 RTL_R32(tp, ERIDR) : ~0; 1139 } 1140 1141 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1142 { 1143 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1144 } 1145 1146 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1147 u32 m) 1148 { 1149 u32 val; 1150 1151 val = rtl_eri_read(tp, addr); 1152 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1153 } 1154 1155 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1156 u32 p) 1157 { 1158 rtl_w0w1_eri(tp, addr, mask, p, 0); 1159 } 1160 1161 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1162 u32 m) 1163 { 1164 rtl_w0w1_eri(tp, addr, mask, 0, m); 1165 } 1166 1167 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1168 { 1169 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1170 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1171 RTL_R32(tp, OCPDR) : ~0; 1172 } 1173 1174 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1175 { 1176 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1177 } 1178 1179 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1180 u32 data) 1181 { 1182 RTL_W32(tp, OCPDR, data); 1183 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1184 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1185 } 1186 1187 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1188 u32 data) 1189 { 1190 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1191 data, ERIAR_OOB); 1192 } 1193 1194 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1195 { 1196 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1197 1198 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1199 } 1200 1201 #define OOB_CMD_RESET 0x00 1202 #define OOB_CMD_DRIVER_START 0x05 1203 #define OOB_CMD_DRIVER_STOP 0x06 1204 1205 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1206 { 1207 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1208 } 1209 1210 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1211 { 1212 u16 reg; 1213 1214 reg = rtl8168_get_ocp_reg(tp); 1215 1216 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1217 } 1218 1219 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1220 { 1221 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1222 } 1223 1224 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1225 { 1226 return RTL_R8(tp, IBISR0) & 0x20; 1227 } 1228 1229 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1230 { 1231 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1232 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1233 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1234 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1235 } 1236 1237 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1238 { 1239 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1240 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1241 } 1242 1243 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1244 { 1245 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1246 r8168ep_ocp_write(tp, 0x01, 0x30, 1247 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1248 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1249 } 1250 1251 static void rtl8168_driver_start(struct rtl8169_private *tp) 1252 { 1253 switch (tp->mac_version) { 1254 case RTL_GIGA_MAC_VER_27: 1255 case RTL_GIGA_MAC_VER_28: 1256 case RTL_GIGA_MAC_VER_31: 1257 rtl8168dp_driver_start(tp); 1258 break; 1259 case RTL_GIGA_MAC_VER_49: 1260 case RTL_GIGA_MAC_VER_50: 1261 case RTL_GIGA_MAC_VER_51: 1262 rtl8168ep_driver_start(tp); 1263 break; 1264 default: 1265 BUG(); 1266 break; 1267 } 1268 } 1269 1270 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1271 { 1272 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1273 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1274 } 1275 1276 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1277 { 1278 rtl8168ep_stop_cmac(tp); 1279 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1280 r8168ep_ocp_write(tp, 0x01, 0x30, 1281 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1282 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1283 } 1284 1285 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1286 { 1287 switch (tp->mac_version) { 1288 case RTL_GIGA_MAC_VER_27: 1289 case RTL_GIGA_MAC_VER_28: 1290 case RTL_GIGA_MAC_VER_31: 1291 rtl8168dp_driver_stop(tp); 1292 break; 1293 case RTL_GIGA_MAC_VER_49: 1294 case RTL_GIGA_MAC_VER_50: 1295 case RTL_GIGA_MAC_VER_51: 1296 rtl8168ep_driver_stop(tp); 1297 break; 1298 default: 1299 BUG(); 1300 break; 1301 } 1302 } 1303 1304 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1305 { 1306 u16 reg = rtl8168_get_ocp_reg(tp); 1307 1308 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1309 } 1310 1311 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1312 { 1313 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1314 } 1315 1316 static bool r8168_check_dash(struct rtl8169_private *tp) 1317 { 1318 switch (tp->mac_version) { 1319 case RTL_GIGA_MAC_VER_27: 1320 case RTL_GIGA_MAC_VER_28: 1321 case RTL_GIGA_MAC_VER_31: 1322 return r8168dp_check_dash(tp); 1323 case RTL_GIGA_MAC_VER_49: 1324 case RTL_GIGA_MAC_VER_50: 1325 case RTL_GIGA_MAC_VER_51: 1326 return r8168ep_check_dash(tp); 1327 default: 1328 return false; 1329 } 1330 } 1331 1332 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1333 { 1334 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1335 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1336 } 1337 1338 DECLARE_RTL_COND(rtl_efusear_cond) 1339 { 1340 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1341 } 1342 1343 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1344 { 1345 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1346 1347 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1348 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1349 } 1350 1351 static u32 rtl_get_events(struct rtl8169_private *tp) 1352 { 1353 if (rtl_is_8125(tp)) 1354 return RTL_R32(tp, IntrStatus_8125); 1355 else 1356 return RTL_R16(tp, IntrStatus); 1357 } 1358 1359 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1360 { 1361 if (rtl_is_8125(tp)) 1362 RTL_W32(tp, IntrStatus_8125, bits); 1363 else 1364 RTL_W16(tp, IntrStatus, bits); 1365 } 1366 1367 static void rtl_irq_disable(struct rtl8169_private *tp) 1368 { 1369 if (rtl_is_8125(tp)) 1370 RTL_W32(tp, IntrMask_8125, 0); 1371 else 1372 RTL_W16(tp, IntrMask, 0); 1373 tp->irq_enabled = 0; 1374 } 1375 1376 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) 1377 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) 1378 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) 1379 1380 static void rtl_irq_enable(struct rtl8169_private *tp) 1381 { 1382 tp->irq_enabled = 1; 1383 if (rtl_is_8125(tp)) 1384 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1385 else 1386 RTL_W16(tp, IntrMask, tp->irq_mask); 1387 } 1388 1389 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1390 { 1391 rtl_irq_disable(tp); 1392 rtl_ack_events(tp, 0xffffffff); 1393 /* PCI commit */ 1394 RTL_R8(tp, ChipCmd); 1395 } 1396 1397 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1398 { 1399 struct net_device *dev = tp->dev; 1400 struct phy_device *phydev = tp->phydev; 1401 1402 if (!netif_running(dev)) 1403 return; 1404 1405 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1406 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1407 if (phydev->speed == SPEED_1000) { 1408 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1409 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1410 } else if (phydev->speed == SPEED_100) { 1411 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1412 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1413 } else { 1414 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1415 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1416 } 1417 rtl_reset_packet_filter(tp); 1418 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1419 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1420 if (phydev->speed == SPEED_1000) { 1421 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1422 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1423 } else { 1424 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1425 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1426 } 1427 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1428 if (phydev->speed == SPEED_10) { 1429 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1430 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1431 } else { 1432 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1433 } 1434 } 1435 } 1436 1437 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1438 1439 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1440 { 1441 struct rtl8169_private *tp = netdev_priv(dev); 1442 1443 rtl_lock_work(tp); 1444 wol->supported = WAKE_ANY; 1445 wol->wolopts = tp->saved_wolopts; 1446 rtl_unlock_work(tp); 1447 } 1448 1449 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1450 { 1451 static const struct { 1452 u32 opt; 1453 u16 reg; 1454 u8 mask; 1455 } cfg[] = { 1456 { WAKE_PHY, Config3, LinkUp }, 1457 { WAKE_UCAST, Config5, UWF }, 1458 { WAKE_BCAST, Config5, BWF }, 1459 { WAKE_MCAST, Config5, MWF }, 1460 { WAKE_ANY, Config5, LanWake }, 1461 { WAKE_MAGIC, Config3, MagicPacket } 1462 }; 1463 unsigned int i, tmp = ARRAY_SIZE(cfg); 1464 u8 options; 1465 1466 rtl_unlock_config_regs(tp); 1467 1468 if (rtl_is_8168evl_up(tp)) { 1469 tmp--; 1470 if (wolopts & WAKE_MAGIC) 1471 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1472 MagicPacket_v2); 1473 else 1474 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1475 MagicPacket_v2); 1476 } else if (rtl_is_8125(tp)) { 1477 tmp--; 1478 if (wolopts & WAKE_MAGIC) 1479 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1480 else 1481 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1482 } 1483 1484 for (i = 0; i < tmp; i++) { 1485 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1486 if (wolopts & cfg[i].opt) 1487 options |= cfg[i].mask; 1488 RTL_W8(tp, cfg[i].reg, options); 1489 } 1490 1491 switch (tp->mac_version) { 1492 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1493 options = RTL_R8(tp, Config1) & ~PMEnable; 1494 if (wolopts) 1495 options |= PMEnable; 1496 RTL_W8(tp, Config1, options); 1497 break; 1498 case RTL_GIGA_MAC_VER_34: 1499 case RTL_GIGA_MAC_VER_37: 1500 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51: 1501 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1502 if (wolopts) 1503 options |= PME_SIGNAL; 1504 RTL_W8(tp, Config2, options); 1505 break; 1506 default: 1507 break; 1508 } 1509 1510 rtl_lock_config_regs(tp); 1511 1512 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1513 } 1514 1515 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1516 { 1517 struct rtl8169_private *tp = netdev_priv(dev); 1518 struct device *d = tp_to_dev(tp); 1519 1520 if (wol->wolopts & ~WAKE_ANY) 1521 return -EINVAL; 1522 1523 pm_runtime_get_noresume(d); 1524 1525 rtl_lock_work(tp); 1526 1527 tp->saved_wolopts = wol->wolopts; 1528 1529 if (pm_runtime_active(d)) 1530 __rtl8169_set_wol(tp, tp->saved_wolopts); 1531 1532 rtl_unlock_work(tp); 1533 1534 pm_runtime_put_noidle(d); 1535 1536 return 0; 1537 } 1538 1539 static void rtl8169_get_drvinfo(struct net_device *dev, 1540 struct ethtool_drvinfo *info) 1541 { 1542 struct rtl8169_private *tp = netdev_priv(dev); 1543 struct rtl_fw *rtl_fw = tp->rtl_fw; 1544 1545 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1546 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1547 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1548 if (rtl_fw) 1549 strlcpy(info->fw_version, rtl_fw->version, 1550 sizeof(info->fw_version)); 1551 } 1552 1553 static int rtl8169_get_regs_len(struct net_device *dev) 1554 { 1555 return R8169_REGS_SIZE; 1556 } 1557 1558 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1559 netdev_features_t features) 1560 { 1561 struct rtl8169_private *tp = netdev_priv(dev); 1562 1563 if (dev->mtu > TD_MSS_MAX) 1564 features &= ~NETIF_F_ALL_TSO; 1565 1566 if (dev->mtu > JUMBO_1K && 1567 tp->mac_version > RTL_GIGA_MAC_VER_06) 1568 features &= ~NETIF_F_IP_CSUM; 1569 1570 return features; 1571 } 1572 1573 static int rtl8169_set_features(struct net_device *dev, 1574 netdev_features_t features) 1575 { 1576 struct rtl8169_private *tp = netdev_priv(dev); 1577 u32 rx_config; 1578 1579 rtl_lock_work(tp); 1580 1581 rx_config = RTL_R32(tp, RxConfig); 1582 if (features & NETIF_F_RXALL) 1583 rx_config |= (AcceptErr | AcceptRunt); 1584 else 1585 rx_config &= ~(AcceptErr | AcceptRunt); 1586 1587 if (rtl_is_8125(tp)) { 1588 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1589 rx_config |= RX_VLAN_8125; 1590 else 1591 rx_config &= ~RX_VLAN_8125; 1592 } 1593 1594 RTL_W32(tp, RxConfig, rx_config); 1595 1596 if (features & NETIF_F_RXCSUM) 1597 tp->cp_cmd |= RxChkSum; 1598 else 1599 tp->cp_cmd &= ~RxChkSum; 1600 1601 if (!rtl_is_8125(tp)) { 1602 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1603 tp->cp_cmd |= RxVlan; 1604 else 1605 tp->cp_cmd &= ~RxVlan; 1606 } 1607 1608 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1609 RTL_R16(tp, CPlusCmd); 1610 1611 rtl_unlock_work(tp); 1612 1613 return 0; 1614 } 1615 1616 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1617 { 1618 return (skb_vlan_tag_present(skb)) ? 1619 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1620 } 1621 1622 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1623 { 1624 u32 opts2 = le32_to_cpu(desc->opts2); 1625 1626 if (opts2 & RxVlanTag) 1627 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1628 } 1629 1630 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1631 void *p) 1632 { 1633 struct rtl8169_private *tp = netdev_priv(dev); 1634 u32 __iomem *data = tp->mmio_addr; 1635 u32 *dw = p; 1636 int i; 1637 1638 rtl_lock_work(tp); 1639 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1640 memcpy_fromio(dw++, data++, 4); 1641 rtl_unlock_work(tp); 1642 } 1643 1644 static u32 rtl8169_get_msglevel(struct net_device *dev) 1645 { 1646 struct rtl8169_private *tp = netdev_priv(dev); 1647 1648 return tp->msg_enable; 1649 } 1650 1651 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1652 { 1653 struct rtl8169_private *tp = netdev_priv(dev); 1654 1655 tp->msg_enable = value; 1656 } 1657 1658 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1659 "tx_packets", 1660 "rx_packets", 1661 "tx_errors", 1662 "rx_errors", 1663 "rx_missed", 1664 "align_errors", 1665 "tx_single_collisions", 1666 "tx_multi_collisions", 1667 "unicast", 1668 "broadcast", 1669 "multicast", 1670 "tx_aborted", 1671 "tx_underrun", 1672 }; 1673 1674 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1675 { 1676 switch (sset) { 1677 case ETH_SS_STATS: 1678 return ARRAY_SIZE(rtl8169_gstrings); 1679 default: 1680 return -EOPNOTSUPP; 1681 } 1682 } 1683 1684 DECLARE_RTL_COND(rtl_counters_cond) 1685 { 1686 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1687 } 1688 1689 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1690 { 1691 dma_addr_t paddr = tp->counters_phys_addr; 1692 u32 cmd; 1693 1694 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1695 RTL_R32(tp, CounterAddrHigh); 1696 cmd = (u64)paddr & DMA_BIT_MASK(32); 1697 RTL_W32(tp, CounterAddrLow, cmd); 1698 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1699 1700 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1701 } 1702 1703 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1704 { 1705 /* 1706 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1707 * tally counters. 1708 */ 1709 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1710 return true; 1711 1712 return rtl8169_do_counters(tp, CounterReset); 1713 } 1714 1715 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1716 { 1717 u8 val = RTL_R8(tp, ChipCmd); 1718 1719 /* 1720 * Some chips are unable to dump tally counters when the receiver 1721 * is disabled. If 0xff chip may be in a PCI power-save state. 1722 */ 1723 if (!(val & CmdRxEnb) || val == 0xff) 1724 return true; 1725 1726 return rtl8169_do_counters(tp, CounterDump); 1727 } 1728 1729 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1730 { 1731 struct rtl8169_counters *counters = tp->counters; 1732 bool ret = false; 1733 1734 /* 1735 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1736 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1737 * reset by a power cycle, while the counter values collected by the 1738 * driver are reset at every driver unload/load cycle. 1739 * 1740 * To make sure the HW values returned by @get_stats64 match the SW 1741 * values, we collect the initial values at first open(*) and use them 1742 * as offsets to normalize the values returned by @get_stats64. 1743 * 1744 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1745 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1746 * set at open time by rtl_hw_start. 1747 */ 1748 1749 if (tp->tc_offset.inited) 1750 return true; 1751 1752 /* If both, reset and update fail, propagate to caller. */ 1753 if (rtl8169_reset_counters(tp)) 1754 ret = true; 1755 1756 if (rtl8169_update_counters(tp)) 1757 ret = true; 1758 1759 tp->tc_offset.tx_errors = counters->tx_errors; 1760 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1761 tp->tc_offset.tx_aborted = counters->tx_aborted; 1762 tp->tc_offset.inited = true; 1763 1764 return ret; 1765 } 1766 1767 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1768 struct ethtool_stats *stats, u64 *data) 1769 { 1770 struct rtl8169_private *tp = netdev_priv(dev); 1771 struct device *d = tp_to_dev(tp); 1772 struct rtl8169_counters *counters = tp->counters; 1773 1774 ASSERT_RTNL(); 1775 1776 pm_runtime_get_noresume(d); 1777 1778 if (pm_runtime_active(d)) 1779 rtl8169_update_counters(tp); 1780 1781 pm_runtime_put_noidle(d); 1782 1783 data[0] = le64_to_cpu(counters->tx_packets); 1784 data[1] = le64_to_cpu(counters->rx_packets); 1785 data[2] = le64_to_cpu(counters->tx_errors); 1786 data[3] = le32_to_cpu(counters->rx_errors); 1787 data[4] = le16_to_cpu(counters->rx_missed); 1788 data[5] = le16_to_cpu(counters->align_errors); 1789 data[6] = le32_to_cpu(counters->tx_one_collision); 1790 data[7] = le32_to_cpu(counters->tx_multi_collision); 1791 data[8] = le64_to_cpu(counters->rx_unicast); 1792 data[9] = le64_to_cpu(counters->rx_broadcast); 1793 data[10] = le32_to_cpu(counters->rx_multicast); 1794 data[11] = le16_to_cpu(counters->tx_aborted); 1795 data[12] = le16_to_cpu(counters->tx_underun); 1796 } 1797 1798 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1799 { 1800 switch(stringset) { 1801 case ETH_SS_STATS: 1802 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1803 break; 1804 } 1805 } 1806 1807 /* 1808 * Interrupt coalescing 1809 * 1810 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1811 * > 8169, 8168 and 810x line of chipsets 1812 * 1813 * 8169, 8168, and 8136(810x) serial chipsets support it. 1814 * 1815 * > 2 - the Tx timer unit at gigabit speed 1816 * 1817 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1818 * (0xe0) bit 1 and bit 0. 1819 * 1820 * For 8169 1821 * bit[1:0] \ speed 1000M 100M 10M 1822 * 0 0 320ns 2.56us 40.96us 1823 * 0 1 2.56us 20.48us 327.7us 1824 * 1 0 5.12us 40.96us 655.4us 1825 * 1 1 10.24us 81.92us 1.31ms 1826 * 1827 * For the other 1828 * bit[1:0] \ speed 1000M 100M 10M 1829 * 0 0 5us 2.56us 40.96us 1830 * 0 1 40us 20.48us 327.7us 1831 * 1 0 80us 40.96us 655.4us 1832 * 1 1 160us 81.92us 1.31ms 1833 */ 1834 1835 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1836 struct rtl_coalesce_scale { 1837 /* Rx / Tx */ 1838 u32 nsecs[2]; 1839 }; 1840 1841 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1842 struct rtl_coalesce_info { 1843 u32 speed; 1844 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1845 }; 1846 1847 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1848 #define rxtx_x1822(r, t) { \ 1849 {{(r), (t)}}, \ 1850 {{(r)*8, (t)*8}}, \ 1851 {{(r)*8*2, (t)*8*2}}, \ 1852 {{(r)*8*2*2, (t)*8*2*2}}, \ 1853 } 1854 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1855 /* speed delays: rx00 tx00 */ 1856 { SPEED_10, rxtx_x1822(40960, 40960) }, 1857 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1858 { SPEED_1000, rxtx_x1822( 320, 320) }, 1859 { 0 }, 1860 }; 1861 1862 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1863 /* speed delays: rx00 tx00 */ 1864 { SPEED_10, rxtx_x1822(40960, 40960) }, 1865 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1866 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1867 { 0 }, 1868 }; 1869 #undef rxtx_x1822 1870 1871 /* get rx/tx scale vector corresponding to current speed */ 1872 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1873 { 1874 struct rtl8169_private *tp = netdev_priv(dev); 1875 const struct rtl_coalesce_info *ci; 1876 1877 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1878 ci = rtl_coalesce_info_8169; 1879 else 1880 ci = rtl_coalesce_info_8168_8136; 1881 1882 for (; ci->speed; ci++) { 1883 if (tp->phydev->speed == ci->speed) 1884 return ci; 1885 } 1886 1887 return ERR_PTR(-ELNRNG); 1888 } 1889 1890 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1891 { 1892 struct rtl8169_private *tp = netdev_priv(dev); 1893 const struct rtl_coalesce_info *ci; 1894 const struct rtl_coalesce_scale *scale; 1895 struct { 1896 u32 *max_frames; 1897 u32 *usecs; 1898 } coal_settings [] = { 1899 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1900 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1901 }, *p = coal_settings; 1902 int i; 1903 u16 w; 1904 1905 if (rtl_is_8125(tp)) 1906 return -EOPNOTSUPP; 1907 1908 memset(ec, 0, sizeof(*ec)); 1909 1910 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1911 ci = rtl_coalesce_info(dev); 1912 if (IS_ERR(ci)) 1913 return PTR_ERR(ci); 1914 1915 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1916 1917 /* read IntrMitigate and adjust according to scale */ 1918 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1919 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1920 w >>= RTL_COALESCE_SHIFT; 1921 *p->usecs = w & RTL_COALESCE_MASK; 1922 } 1923 1924 for (i = 0; i < 2; i++) { 1925 p = coal_settings + i; 1926 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1927 1928 /* 1929 * ethtool_coalesce says it is illegal to set both usecs and 1930 * max_frames to 0. 1931 */ 1932 if (!*p->usecs && !*p->max_frames) 1933 *p->max_frames = 1; 1934 } 1935 1936 return 0; 1937 } 1938 1939 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1940 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1941 struct net_device *dev, u32 nsec, u16 *cp01) 1942 { 1943 const struct rtl_coalesce_info *ci; 1944 u16 i; 1945 1946 ci = rtl_coalesce_info(dev); 1947 if (IS_ERR(ci)) 1948 return ERR_CAST(ci); 1949 1950 for (i = 0; i < 4; i++) { 1951 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1952 ci->scalev[i].nsecs[1]); 1953 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1954 *cp01 = i; 1955 return &ci->scalev[i]; 1956 } 1957 } 1958 1959 return ERR_PTR(-EINVAL); 1960 } 1961 1962 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1963 { 1964 struct rtl8169_private *tp = netdev_priv(dev); 1965 const struct rtl_coalesce_scale *scale; 1966 struct { 1967 u32 frames; 1968 u32 usecs; 1969 } coal_settings [] = { 1970 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 1971 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 1972 }, *p = coal_settings; 1973 u16 w = 0, cp01; 1974 int i; 1975 1976 if (rtl_is_8125(tp)) 1977 return -EOPNOTSUPP; 1978 1979 scale = rtl_coalesce_choose_scale(dev, 1980 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 1981 if (IS_ERR(scale)) 1982 return PTR_ERR(scale); 1983 1984 for (i = 0; i < 2; i++, p++) { 1985 u32 units; 1986 1987 /* 1988 * accept max_frames=1 we returned in rtl_get_coalesce. 1989 * accept it not only when usecs=0 because of e.g. the following scenario: 1990 * 1991 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1992 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1993 * - then user does `ethtool -C eth0 rx-usecs 100` 1994 * 1995 * since ethtool sends to kernel whole ethtool_coalesce 1996 * settings, if we do not handle rx_usecs=!0, rx_frames=1 1997 * we'll reject it below in `frames % 4 != 0`. 1998 */ 1999 if (p->frames == 1) { 2000 p->frames = 0; 2001 } 2002 2003 units = p->usecs * 1000 / scale->nsecs[i]; 2004 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 2005 return -EINVAL; 2006 2007 w <<= RTL_COALESCE_SHIFT; 2008 w |= units; 2009 w <<= RTL_COALESCE_SHIFT; 2010 w |= p->frames >> 2; 2011 } 2012 2013 rtl_lock_work(tp); 2014 2015 RTL_W16(tp, IntrMitigate, swab16(w)); 2016 2017 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2018 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2019 RTL_R16(tp, CPlusCmd); 2020 2021 rtl_unlock_work(tp); 2022 2023 return 0; 2024 } 2025 2026 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 2027 { 2028 struct rtl8169_private *tp = netdev_priv(dev); 2029 struct device *d = tp_to_dev(tp); 2030 int ret; 2031 2032 if (!rtl_supports_eee(tp)) 2033 return -EOPNOTSUPP; 2034 2035 pm_runtime_get_noresume(d); 2036 2037 if (!pm_runtime_active(d)) { 2038 ret = -EOPNOTSUPP; 2039 } else { 2040 ret = phy_ethtool_get_eee(tp->phydev, data); 2041 } 2042 2043 pm_runtime_put_noidle(d); 2044 2045 return ret; 2046 } 2047 2048 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 2049 { 2050 struct rtl8169_private *tp = netdev_priv(dev); 2051 struct device *d = tp_to_dev(tp); 2052 int ret; 2053 2054 if (!rtl_supports_eee(tp)) 2055 return -EOPNOTSUPP; 2056 2057 pm_runtime_get_noresume(d); 2058 2059 if (!pm_runtime_active(d)) { 2060 ret = -EOPNOTSUPP; 2061 goto out; 2062 } 2063 2064 if (dev->phydev->autoneg == AUTONEG_DISABLE || 2065 dev->phydev->duplex != DUPLEX_FULL) { 2066 ret = -EPROTONOSUPPORT; 2067 goto out; 2068 } 2069 2070 ret = phy_ethtool_set_eee(tp->phydev, data); 2071 out: 2072 pm_runtime_put_noidle(d); 2073 return ret; 2074 } 2075 2076 static const struct ethtool_ops rtl8169_ethtool_ops = { 2077 .get_drvinfo = rtl8169_get_drvinfo, 2078 .get_regs_len = rtl8169_get_regs_len, 2079 .get_link = ethtool_op_get_link, 2080 .get_coalesce = rtl_get_coalesce, 2081 .set_coalesce = rtl_set_coalesce, 2082 .get_msglevel = rtl8169_get_msglevel, 2083 .set_msglevel = rtl8169_set_msglevel, 2084 .get_regs = rtl8169_get_regs, 2085 .get_wol = rtl8169_get_wol, 2086 .set_wol = rtl8169_set_wol, 2087 .get_strings = rtl8169_get_strings, 2088 .get_sset_count = rtl8169_get_sset_count, 2089 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2090 .get_ts_info = ethtool_op_get_ts_info, 2091 .nway_reset = phy_ethtool_nway_reset, 2092 .get_eee = rtl8169_get_eee, 2093 .set_eee = rtl8169_set_eee, 2094 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2095 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2096 }; 2097 2098 static void rtl_enable_eee(struct rtl8169_private *tp) 2099 { 2100 struct phy_device *phydev = tp->phydev; 2101 int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2102 2103 if (supported > 0) 2104 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported); 2105 } 2106 2107 static void rtl8169_get_mac_version(struct rtl8169_private *tp) 2108 { 2109 /* 2110 * The driver currently handles the 8168Bf and the 8168Be identically 2111 * but they can be identified more specifically through the test below 2112 * if needed: 2113 * 2114 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2115 * 2116 * Same thing for the 8101Eb and the 8101Ec: 2117 * 2118 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2119 */ 2120 static const struct rtl_mac_info { 2121 u16 mask; 2122 u16 val; 2123 u16 mac_version; 2124 } mac_info[] = { 2125 /* 8125 family. */ 2126 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2127 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2128 2129 /* 8168EP family. */ 2130 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2131 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2132 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2133 2134 /* 8168H family. */ 2135 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2136 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2137 2138 /* 8168G family. */ 2139 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2140 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2141 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2142 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2143 2144 /* 8168F family. */ 2145 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2146 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2147 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2148 2149 /* 8168E family. */ 2150 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2151 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2152 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2153 2154 /* 8168D family. */ 2155 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2156 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2157 2158 /* 8168DP family. */ 2159 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2160 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2161 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2162 2163 /* 8168C family. */ 2164 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2165 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2166 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2167 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2168 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2169 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2170 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2171 2172 /* 8168B family. */ 2173 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2174 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2175 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2176 2177 /* 8101 family. */ 2178 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2179 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2180 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2181 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2182 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2183 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2184 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2185 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2186 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2187 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2188 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2189 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2190 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2191 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2192 /* FIXME: where did these entries come from ? -- FR */ 2193 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2194 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2195 2196 /* 8110 family. */ 2197 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2198 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2199 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2200 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2201 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2202 2203 /* Catch-all */ 2204 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2205 }; 2206 const struct rtl_mac_info *p = mac_info; 2207 u16 reg = RTL_R32(tp, TxConfig) >> 20; 2208 2209 while ((reg & p->mask) != p->val) 2210 p++; 2211 tp->mac_version = p->mac_version; 2212 2213 if (tp->mac_version == RTL_GIGA_MAC_NONE) { 2214 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf); 2215 } else if (!tp->supports_gmii) { 2216 if (tp->mac_version == RTL_GIGA_MAC_VER_42) 2217 tp->mac_version = RTL_GIGA_MAC_VER_43; 2218 else if (tp->mac_version == RTL_GIGA_MAC_VER_45) 2219 tp->mac_version = RTL_GIGA_MAC_VER_47; 2220 else if (tp->mac_version == RTL_GIGA_MAC_VER_46) 2221 tp->mac_version = RTL_GIGA_MAC_VER_48; 2222 } 2223 } 2224 2225 struct phy_reg { 2226 u16 reg; 2227 u16 val; 2228 }; 2229 2230 static void __rtl_writephy_batch(struct rtl8169_private *tp, 2231 const struct phy_reg *regs, int len) 2232 { 2233 while (len-- > 0) { 2234 rtl_writephy(tp, regs->reg, regs->val); 2235 regs++; 2236 } 2237 } 2238 2239 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a)) 2240 2241 static void rtl_release_firmware(struct rtl8169_private *tp) 2242 { 2243 if (tp->rtl_fw) { 2244 rtl_fw_release_firmware(tp->rtl_fw); 2245 kfree(tp->rtl_fw); 2246 tp->rtl_fw = NULL; 2247 } 2248 } 2249 2250 static void rtl_apply_firmware(struct rtl8169_private *tp) 2251 { 2252 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2253 if (tp->rtl_fw) 2254 rtl_fw_write_firmware(tp, tp->rtl_fw); 2255 } 2256 2257 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) 2258 { 2259 if (rtl_readphy(tp, reg) != val) 2260 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); 2261 else 2262 rtl_apply_firmware(tp); 2263 } 2264 2265 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2266 { 2267 /* Adjust EEE LED frequency */ 2268 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2269 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2270 2271 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2272 } 2273 2274 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2275 { 2276 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2277 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2278 } 2279 2280 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp) 2281 { 2282 struct phy_device *phydev = tp->phydev; 2283 2284 phy_write(phydev, 0x1f, 0x0007); 2285 phy_write(phydev, 0x1e, 0x0020); 2286 phy_set_bits(phydev, 0x15, BIT(8)); 2287 2288 phy_write(phydev, 0x1f, 0x0005); 2289 phy_write(phydev, 0x05, 0x8b85); 2290 phy_set_bits(phydev, 0x06, BIT(13)); 2291 2292 phy_write(phydev, 0x1f, 0x0000); 2293 } 2294 2295 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp) 2296 { 2297 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4)); 2298 } 2299 2300 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp) 2301 { 2302 struct phy_device *phydev = tp->phydev; 2303 2304 rtl8168g_config_eee_phy(tp); 2305 2306 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 2307 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 2308 } 2309 2310 static void rtl8125_config_eee_phy(struct rtl8169_private *tp) 2311 { 2312 struct phy_device *phydev = tp->phydev; 2313 2314 rtl8168h_config_eee_phy(tp); 2315 2316 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 2317 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 2318 } 2319 2320 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) 2321 { 2322 static const struct phy_reg phy_reg_init[] = { 2323 { 0x1f, 0x0001 }, 2324 { 0x06, 0x006e }, 2325 { 0x08, 0x0708 }, 2326 { 0x15, 0x4000 }, 2327 { 0x18, 0x65c7 }, 2328 2329 { 0x1f, 0x0001 }, 2330 { 0x03, 0x00a1 }, 2331 { 0x02, 0x0008 }, 2332 { 0x01, 0x0120 }, 2333 { 0x00, 0x1000 }, 2334 { 0x04, 0x0800 }, 2335 { 0x04, 0x0000 }, 2336 2337 { 0x03, 0xff41 }, 2338 { 0x02, 0xdf60 }, 2339 { 0x01, 0x0140 }, 2340 { 0x00, 0x0077 }, 2341 { 0x04, 0x7800 }, 2342 { 0x04, 0x7000 }, 2343 2344 { 0x03, 0x802f }, 2345 { 0x02, 0x4f02 }, 2346 { 0x01, 0x0409 }, 2347 { 0x00, 0xf0f9 }, 2348 { 0x04, 0x9800 }, 2349 { 0x04, 0x9000 }, 2350 2351 { 0x03, 0xdf01 }, 2352 { 0x02, 0xdf20 }, 2353 { 0x01, 0xff95 }, 2354 { 0x00, 0xba00 }, 2355 { 0x04, 0xa800 }, 2356 { 0x04, 0xa000 }, 2357 2358 { 0x03, 0xff41 }, 2359 { 0x02, 0xdf20 }, 2360 { 0x01, 0x0140 }, 2361 { 0x00, 0x00bb }, 2362 { 0x04, 0xb800 }, 2363 { 0x04, 0xb000 }, 2364 2365 { 0x03, 0xdf41 }, 2366 { 0x02, 0xdc60 }, 2367 { 0x01, 0x6340 }, 2368 { 0x00, 0x007d }, 2369 { 0x04, 0xd800 }, 2370 { 0x04, 0xd000 }, 2371 2372 { 0x03, 0xdf01 }, 2373 { 0x02, 0xdf20 }, 2374 { 0x01, 0x100a }, 2375 { 0x00, 0xa0ff }, 2376 { 0x04, 0xf800 }, 2377 { 0x04, 0xf000 }, 2378 2379 { 0x1f, 0x0000 }, 2380 { 0x0b, 0x0000 }, 2381 { 0x00, 0x9200 } 2382 }; 2383 2384 rtl_writephy_batch(tp, phy_reg_init); 2385 } 2386 2387 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) 2388 { 2389 static const struct phy_reg phy_reg_init[] = { 2390 { 0x1f, 0x0002 }, 2391 { 0x01, 0x90d0 }, 2392 { 0x1f, 0x0000 } 2393 }; 2394 2395 rtl_writephy_batch(tp, phy_reg_init); 2396 } 2397 2398 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) 2399 { 2400 struct pci_dev *pdev = tp->pci_dev; 2401 2402 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || 2403 (pdev->subsystem_device != 0xe000)) 2404 return; 2405 2406 rtl_writephy(tp, 0x1f, 0x0001); 2407 rtl_writephy(tp, 0x10, 0xf01b); 2408 rtl_writephy(tp, 0x1f, 0x0000); 2409 } 2410 2411 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) 2412 { 2413 static const struct phy_reg phy_reg_init[] = { 2414 { 0x1f, 0x0001 }, 2415 { 0x04, 0x0000 }, 2416 { 0x03, 0x00a1 }, 2417 { 0x02, 0x0008 }, 2418 { 0x01, 0x0120 }, 2419 { 0x00, 0x1000 }, 2420 { 0x04, 0x0800 }, 2421 { 0x04, 0x9000 }, 2422 { 0x03, 0x802f }, 2423 { 0x02, 0x4f02 }, 2424 { 0x01, 0x0409 }, 2425 { 0x00, 0xf099 }, 2426 { 0x04, 0x9800 }, 2427 { 0x04, 0xa000 }, 2428 { 0x03, 0xdf01 }, 2429 { 0x02, 0xdf20 }, 2430 { 0x01, 0xff95 }, 2431 { 0x00, 0xba00 }, 2432 { 0x04, 0xa800 }, 2433 { 0x04, 0xf000 }, 2434 { 0x03, 0xdf01 }, 2435 { 0x02, 0xdf20 }, 2436 { 0x01, 0x101a }, 2437 { 0x00, 0xa0ff }, 2438 { 0x04, 0xf800 }, 2439 { 0x04, 0x0000 }, 2440 { 0x1f, 0x0000 }, 2441 2442 { 0x1f, 0x0001 }, 2443 { 0x10, 0xf41b }, 2444 { 0x14, 0xfb54 }, 2445 { 0x18, 0xf5c7 }, 2446 { 0x1f, 0x0000 }, 2447 2448 { 0x1f, 0x0001 }, 2449 { 0x17, 0x0cc0 }, 2450 { 0x1f, 0x0000 } 2451 }; 2452 2453 rtl_writephy_batch(tp, phy_reg_init); 2454 2455 rtl8169scd_hw_phy_config_quirk(tp); 2456 } 2457 2458 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) 2459 { 2460 static const struct phy_reg phy_reg_init[] = { 2461 { 0x1f, 0x0001 }, 2462 { 0x04, 0x0000 }, 2463 { 0x03, 0x00a1 }, 2464 { 0x02, 0x0008 }, 2465 { 0x01, 0x0120 }, 2466 { 0x00, 0x1000 }, 2467 { 0x04, 0x0800 }, 2468 { 0x04, 0x9000 }, 2469 { 0x03, 0x802f }, 2470 { 0x02, 0x4f02 }, 2471 { 0x01, 0x0409 }, 2472 { 0x00, 0xf099 }, 2473 { 0x04, 0x9800 }, 2474 { 0x04, 0xa000 }, 2475 { 0x03, 0xdf01 }, 2476 { 0x02, 0xdf20 }, 2477 { 0x01, 0xff95 }, 2478 { 0x00, 0xba00 }, 2479 { 0x04, 0xa800 }, 2480 { 0x04, 0xf000 }, 2481 { 0x03, 0xdf01 }, 2482 { 0x02, 0xdf20 }, 2483 { 0x01, 0x101a }, 2484 { 0x00, 0xa0ff }, 2485 { 0x04, 0xf800 }, 2486 { 0x04, 0x0000 }, 2487 { 0x1f, 0x0000 }, 2488 2489 { 0x1f, 0x0001 }, 2490 { 0x0b, 0x8480 }, 2491 { 0x1f, 0x0000 }, 2492 2493 { 0x1f, 0x0001 }, 2494 { 0x18, 0x67c7 }, 2495 { 0x04, 0x2000 }, 2496 { 0x03, 0x002f }, 2497 { 0x02, 0x4360 }, 2498 { 0x01, 0x0109 }, 2499 { 0x00, 0x3022 }, 2500 { 0x04, 0x2800 }, 2501 { 0x1f, 0x0000 }, 2502 2503 { 0x1f, 0x0001 }, 2504 { 0x17, 0x0cc0 }, 2505 { 0x1f, 0x0000 } 2506 }; 2507 2508 rtl_writephy_batch(tp, phy_reg_init); 2509 } 2510 2511 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) 2512 { 2513 static const struct phy_reg phy_reg_init[] = { 2514 { 0x10, 0xf41b }, 2515 { 0x1f, 0x0000 } 2516 }; 2517 2518 rtl_writephy(tp, 0x1f, 0x0001); 2519 rtl_patchphy(tp, 0x16, 1 << 0); 2520 2521 rtl_writephy_batch(tp, phy_reg_init); 2522 } 2523 2524 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) 2525 { 2526 static const struct phy_reg phy_reg_init[] = { 2527 { 0x1f, 0x0001 }, 2528 { 0x10, 0xf41b }, 2529 { 0x1f, 0x0000 } 2530 }; 2531 2532 rtl_writephy_batch(tp, phy_reg_init); 2533 } 2534 2535 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) 2536 { 2537 static const struct phy_reg phy_reg_init[] = { 2538 { 0x1f, 0x0000 }, 2539 { 0x1d, 0x0f00 }, 2540 { 0x1f, 0x0002 }, 2541 { 0x0c, 0x1ec8 }, 2542 { 0x1f, 0x0000 } 2543 }; 2544 2545 rtl_writephy_batch(tp, phy_reg_init); 2546 } 2547 2548 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) 2549 { 2550 static const struct phy_reg phy_reg_init[] = { 2551 { 0x1f, 0x0001 }, 2552 { 0x1d, 0x3d98 }, 2553 { 0x1f, 0x0000 } 2554 }; 2555 2556 rtl_writephy(tp, 0x1f, 0x0000); 2557 rtl_patchphy(tp, 0x14, 1 << 5); 2558 rtl_patchphy(tp, 0x0d, 1 << 5); 2559 2560 rtl_writephy_batch(tp, phy_reg_init); 2561 } 2562 2563 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) 2564 { 2565 static const struct phy_reg phy_reg_init[] = { 2566 { 0x1f, 0x0001 }, 2567 { 0x12, 0x2300 }, 2568 { 0x1f, 0x0002 }, 2569 { 0x00, 0x88d4 }, 2570 { 0x01, 0x82b1 }, 2571 { 0x03, 0x7002 }, 2572 { 0x08, 0x9e30 }, 2573 { 0x09, 0x01f0 }, 2574 { 0x0a, 0x5500 }, 2575 { 0x0c, 0x00c8 }, 2576 { 0x1f, 0x0003 }, 2577 { 0x12, 0xc096 }, 2578 { 0x16, 0x000a }, 2579 { 0x1f, 0x0000 }, 2580 { 0x1f, 0x0000 }, 2581 { 0x09, 0x2000 }, 2582 { 0x09, 0x0000 } 2583 }; 2584 2585 rtl_writephy_batch(tp, phy_reg_init); 2586 2587 rtl_patchphy(tp, 0x14, 1 << 5); 2588 rtl_patchphy(tp, 0x0d, 1 << 5); 2589 rtl_writephy(tp, 0x1f, 0x0000); 2590 } 2591 2592 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) 2593 { 2594 static const struct phy_reg phy_reg_init[] = { 2595 { 0x1f, 0x0001 }, 2596 { 0x12, 0x2300 }, 2597 { 0x03, 0x802f }, 2598 { 0x02, 0x4f02 }, 2599 { 0x01, 0x0409 }, 2600 { 0x00, 0xf099 }, 2601 { 0x04, 0x9800 }, 2602 { 0x04, 0x9000 }, 2603 { 0x1d, 0x3d98 }, 2604 { 0x1f, 0x0002 }, 2605 { 0x0c, 0x7eb8 }, 2606 { 0x06, 0x0761 }, 2607 { 0x1f, 0x0003 }, 2608 { 0x16, 0x0f0a }, 2609 { 0x1f, 0x0000 } 2610 }; 2611 2612 rtl_writephy_batch(tp, phy_reg_init); 2613 2614 rtl_patchphy(tp, 0x16, 1 << 0); 2615 rtl_patchphy(tp, 0x14, 1 << 5); 2616 rtl_patchphy(tp, 0x0d, 1 << 5); 2617 rtl_writephy(tp, 0x1f, 0x0000); 2618 } 2619 2620 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) 2621 { 2622 static const struct phy_reg phy_reg_init[] = { 2623 { 0x1f, 0x0001 }, 2624 { 0x12, 0x2300 }, 2625 { 0x1d, 0x3d98 }, 2626 { 0x1f, 0x0002 }, 2627 { 0x0c, 0x7eb8 }, 2628 { 0x06, 0x5461 }, 2629 { 0x1f, 0x0003 }, 2630 { 0x16, 0x0f0a }, 2631 { 0x1f, 0x0000 } 2632 }; 2633 2634 rtl_writephy_batch(tp, phy_reg_init); 2635 2636 rtl_patchphy(tp, 0x16, 1 << 0); 2637 rtl_patchphy(tp, 0x14, 1 << 5); 2638 rtl_patchphy(tp, 0x0d, 1 << 5); 2639 rtl_writephy(tp, 0x1f, 0x0000); 2640 } 2641 2642 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) 2643 { 2644 rtl8168c_3_hw_phy_config(tp); 2645 } 2646 2647 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 2648 /* Channel Estimation */ 2649 { 0x1f, 0x0001 }, 2650 { 0x06, 0x4064 }, 2651 { 0x07, 0x2863 }, 2652 { 0x08, 0x059c }, 2653 { 0x09, 0x26b4 }, 2654 { 0x0a, 0x6a19 }, 2655 { 0x0b, 0xdcc8 }, 2656 { 0x10, 0xf06d }, 2657 { 0x14, 0x7f68 }, 2658 { 0x18, 0x7fd9 }, 2659 { 0x1c, 0xf0ff }, 2660 { 0x1d, 0x3d9c }, 2661 { 0x1f, 0x0003 }, 2662 { 0x12, 0xf49f }, 2663 { 0x13, 0x070b }, 2664 { 0x1a, 0x05ad }, 2665 { 0x14, 0x94c0 }, 2666 2667 /* 2668 * Tx Error Issue 2669 * Enhance line driver power 2670 */ 2671 { 0x1f, 0x0002 }, 2672 { 0x06, 0x5561 }, 2673 { 0x1f, 0x0005 }, 2674 { 0x05, 0x8332 }, 2675 { 0x06, 0x5561 }, 2676 2677 /* 2678 * Can not link to 1Gbps with bad cable 2679 * Decrease SNR threshold form 21.07dB to 19.04dB 2680 */ 2681 { 0x1f, 0x0001 }, 2682 { 0x17, 0x0cc0 }, 2683 2684 { 0x1f, 0x0000 }, 2685 { 0x0d, 0xf880 } 2686 }; 2687 2688 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 2689 { 0x1f, 0x0002 }, 2690 { 0x05, 0x669a }, 2691 { 0x1f, 0x0005 }, 2692 { 0x05, 0x8330 }, 2693 { 0x06, 0x669a }, 2694 { 0x1f, 0x0002 } 2695 }; 2696 2697 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) 2698 { 2699 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2700 2701 /* 2702 * Rx Error Issue 2703 * Fine Tune Switching regulator parameter 2704 */ 2705 rtl_writephy(tp, 0x1f, 0x0002); 2706 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); 2707 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); 2708 2709 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2710 int val; 2711 2712 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2713 2714 val = rtl_readphy(tp, 0x0d); 2715 2716 if ((val & 0x00ff) != 0x006c) { 2717 static const u32 set[] = { 2718 0x0065, 0x0066, 0x0067, 0x0068, 2719 0x0069, 0x006a, 0x006b, 0x006c 2720 }; 2721 int i; 2722 2723 rtl_writephy(tp, 0x1f, 0x0002); 2724 2725 val &= 0xff00; 2726 for (i = 0; i < ARRAY_SIZE(set); i++) 2727 rtl_writephy(tp, 0x0d, val | set[i]); 2728 } 2729 } else { 2730 static const struct phy_reg phy_reg_init[] = { 2731 { 0x1f, 0x0002 }, 2732 { 0x05, 0x6662 }, 2733 { 0x1f, 0x0005 }, 2734 { 0x05, 0x8330 }, 2735 { 0x06, 0x6662 } 2736 }; 2737 2738 rtl_writephy_batch(tp, phy_reg_init); 2739 } 2740 2741 /* RSET couple improve */ 2742 rtl_writephy(tp, 0x1f, 0x0002); 2743 rtl_patchphy(tp, 0x0d, 0x0300); 2744 rtl_patchphy(tp, 0x0f, 0x0010); 2745 2746 /* Fine tune PLL performance */ 2747 rtl_writephy(tp, 0x1f, 0x0002); 2748 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2749 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2750 2751 rtl_writephy(tp, 0x1f, 0x0005); 2752 rtl_writephy(tp, 0x05, 0x001b); 2753 2754 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); 2755 2756 rtl_writephy(tp, 0x1f, 0x0000); 2757 } 2758 2759 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) 2760 { 2761 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2762 2763 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2764 int val; 2765 2766 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2767 2768 val = rtl_readphy(tp, 0x0d); 2769 if ((val & 0x00ff) != 0x006c) { 2770 static const u32 set[] = { 2771 0x0065, 0x0066, 0x0067, 0x0068, 2772 0x0069, 0x006a, 0x006b, 0x006c 2773 }; 2774 int i; 2775 2776 rtl_writephy(tp, 0x1f, 0x0002); 2777 2778 val &= 0xff00; 2779 for (i = 0; i < ARRAY_SIZE(set); i++) 2780 rtl_writephy(tp, 0x0d, val | set[i]); 2781 } 2782 } else { 2783 static const struct phy_reg phy_reg_init[] = { 2784 { 0x1f, 0x0002 }, 2785 { 0x05, 0x2642 }, 2786 { 0x1f, 0x0005 }, 2787 { 0x05, 0x8330 }, 2788 { 0x06, 0x2642 } 2789 }; 2790 2791 rtl_writephy_batch(tp, phy_reg_init); 2792 } 2793 2794 /* Fine tune PLL performance */ 2795 rtl_writephy(tp, 0x1f, 0x0002); 2796 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2797 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2798 2799 /* Switching regulator Slew rate */ 2800 rtl_writephy(tp, 0x1f, 0x0002); 2801 rtl_patchphy(tp, 0x0f, 0x0017); 2802 2803 rtl_writephy(tp, 0x1f, 0x0005); 2804 rtl_writephy(tp, 0x05, 0x001b); 2805 2806 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); 2807 2808 rtl_writephy(tp, 0x1f, 0x0000); 2809 } 2810 2811 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) 2812 { 2813 static const struct phy_reg phy_reg_init[] = { 2814 { 0x1f, 0x0002 }, 2815 { 0x10, 0x0008 }, 2816 { 0x0d, 0x006c }, 2817 2818 { 0x1f, 0x0000 }, 2819 { 0x0d, 0xf880 }, 2820 2821 { 0x1f, 0x0001 }, 2822 { 0x17, 0x0cc0 }, 2823 2824 { 0x1f, 0x0001 }, 2825 { 0x0b, 0xa4d8 }, 2826 { 0x09, 0x281c }, 2827 { 0x07, 0x2883 }, 2828 { 0x0a, 0x6b35 }, 2829 { 0x1d, 0x3da4 }, 2830 { 0x1c, 0xeffd }, 2831 { 0x14, 0x7f52 }, 2832 { 0x18, 0x7fc6 }, 2833 { 0x08, 0x0601 }, 2834 { 0x06, 0x4063 }, 2835 { 0x10, 0xf074 }, 2836 { 0x1f, 0x0003 }, 2837 { 0x13, 0x0789 }, 2838 { 0x12, 0xf4bd }, 2839 { 0x1a, 0x04fd }, 2840 { 0x14, 0x84b0 }, 2841 { 0x1f, 0x0000 }, 2842 { 0x00, 0x9200 }, 2843 2844 { 0x1f, 0x0005 }, 2845 { 0x01, 0x0340 }, 2846 { 0x1f, 0x0001 }, 2847 { 0x04, 0x4000 }, 2848 { 0x03, 0x1d21 }, 2849 { 0x02, 0x0c32 }, 2850 { 0x01, 0x0200 }, 2851 { 0x00, 0x5554 }, 2852 { 0x04, 0x4800 }, 2853 { 0x04, 0x4000 }, 2854 { 0x04, 0xf000 }, 2855 { 0x03, 0xdf01 }, 2856 { 0x02, 0xdf20 }, 2857 { 0x01, 0x101a }, 2858 { 0x00, 0xa0ff }, 2859 { 0x04, 0xf800 }, 2860 { 0x04, 0xf000 }, 2861 { 0x1f, 0x0000 }, 2862 2863 { 0x1f, 0x0007 }, 2864 { 0x1e, 0x0023 }, 2865 { 0x16, 0x0000 }, 2866 { 0x1f, 0x0000 } 2867 }; 2868 2869 rtl_writephy_batch(tp, phy_reg_init); 2870 } 2871 2872 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) 2873 { 2874 static const struct phy_reg phy_reg_init[] = { 2875 { 0x1f, 0x0001 }, 2876 { 0x17, 0x0cc0 }, 2877 2878 { 0x1f, 0x0007 }, 2879 { 0x1e, 0x002d }, 2880 { 0x18, 0x0040 }, 2881 { 0x1f, 0x0000 } 2882 }; 2883 2884 rtl_writephy_batch(tp, phy_reg_init); 2885 rtl_patchphy(tp, 0x0d, 1 << 5); 2886 } 2887 2888 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) 2889 { 2890 static const struct phy_reg phy_reg_init[] = { 2891 /* Enable Delay cap */ 2892 { 0x1f, 0x0005 }, 2893 { 0x05, 0x8b80 }, 2894 { 0x06, 0xc896 }, 2895 { 0x1f, 0x0000 }, 2896 2897 /* Channel estimation fine tune */ 2898 { 0x1f, 0x0001 }, 2899 { 0x0b, 0x6c20 }, 2900 { 0x07, 0x2872 }, 2901 { 0x1c, 0xefff }, 2902 { 0x1f, 0x0003 }, 2903 { 0x14, 0x6420 }, 2904 { 0x1f, 0x0000 }, 2905 2906 /* Update PFM & 10M TX idle timer */ 2907 { 0x1f, 0x0007 }, 2908 { 0x1e, 0x002f }, 2909 { 0x15, 0x1919 }, 2910 { 0x1f, 0x0000 }, 2911 2912 { 0x1f, 0x0007 }, 2913 { 0x1e, 0x00ac }, 2914 { 0x18, 0x0006 }, 2915 { 0x1f, 0x0000 } 2916 }; 2917 2918 rtl_apply_firmware(tp); 2919 2920 rtl_writephy_batch(tp, phy_reg_init); 2921 2922 /* DCO enable for 10M IDLE Power */ 2923 rtl_writephy(tp, 0x1f, 0x0007); 2924 rtl_writephy(tp, 0x1e, 0x0023); 2925 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 2926 rtl_writephy(tp, 0x1f, 0x0000); 2927 2928 /* For impedance matching */ 2929 rtl_writephy(tp, 0x1f, 0x0002); 2930 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00); 2931 rtl_writephy(tp, 0x1f, 0x0000); 2932 2933 /* PHY auto speed down */ 2934 rtl_writephy(tp, 0x1f, 0x0007); 2935 rtl_writephy(tp, 0x1e, 0x002d); 2936 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000); 2937 rtl_writephy(tp, 0x1f, 0x0000); 2938 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 2939 2940 rtl_writephy(tp, 0x1f, 0x0005); 2941 rtl_writephy(tp, 0x05, 0x8b86); 2942 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 2943 rtl_writephy(tp, 0x1f, 0x0000); 2944 2945 rtl_writephy(tp, 0x1f, 0x0005); 2946 rtl_writephy(tp, 0x05, 0x8b85); 2947 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); 2948 rtl_writephy(tp, 0x1f, 0x0007); 2949 rtl_writephy(tp, 0x1e, 0x0020); 2950 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100); 2951 rtl_writephy(tp, 0x1f, 0x0006); 2952 rtl_writephy(tp, 0x00, 0x5a00); 2953 rtl_writephy(tp, 0x1f, 0x0000); 2954 rtl_writephy(tp, 0x0d, 0x0007); 2955 rtl_writephy(tp, 0x0e, 0x003c); 2956 rtl_writephy(tp, 0x0d, 0x4007); 2957 rtl_writephy(tp, 0x0e, 0x0000); 2958 rtl_writephy(tp, 0x0d, 0x0000); 2959 } 2960 2961 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2962 { 2963 const u16 w[] = { 2964 addr[0] | (addr[1] << 8), 2965 addr[2] | (addr[3] << 8), 2966 addr[4] | (addr[5] << 8) 2967 }; 2968 2969 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2970 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2971 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2972 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2973 } 2974 2975 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) 2976 { 2977 static const struct phy_reg phy_reg_init[] = { 2978 /* Enable Delay cap */ 2979 { 0x1f, 0x0004 }, 2980 { 0x1f, 0x0007 }, 2981 { 0x1e, 0x00ac }, 2982 { 0x18, 0x0006 }, 2983 { 0x1f, 0x0002 }, 2984 { 0x1f, 0x0000 }, 2985 { 0x1f, 0x0000 }, 2986 2987 /* Channel estimation fine tune */ 2988 { 0x1f, 0x0003 }, 2989 { 0x09, 0xa20f }, 2990 { 0x1f, 0x0000 }, 2991 { 0x1f, 0x0000 }, 2992 2993 /* Green Setting */ 2994 { 0x1f, 0x0005 }, 2995 { 0x05, 0x8b5b }, 2996 { 0x06, 0x9222 }, 2997 { 0x05, 0x8b6d }, 2998 { 0x06, 0x8000 }, 2999 { 0x05, 0x8b76 }, 3000 { 0x06, 0x8000 }, 3001 { 0x1f, 0x0000 } 3002 }; 3003 3004 rtl_apply_firmware(tp); 3005 3006 rtl_writephy_batch(tp, phy_reg_init); 3007 3008 /* For 4-corner performance improve */ 3009 rtl_writephy(tp, 0x1f, 0x0005); 3010 rtl_writephy(tp, 0x05, 0x8b80); 3011 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 3012 rtl_writephy(tp, 0x1f, 0x0000); 3013 3014 /* PHY auto speed down */ 3015 rtl_writephy(tp, 0x1f, 0x0004); 3016 rtl_writephy(tp, 0x1f, 0x0007); 3017 rtl_writephy(tp, 0x1e, 0x002d); 3018 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3019 rtl_writephy(tp, 0x1f, 0x0002); 3020 rtl_writephy(tp, 0x1f, 0x0000); 3021 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3022 3023 /* improve 10M EEE waveform */ 3024 rtl_writephy(tp, 0x1f, 0x0005); 3025 rtl_writephy(tp, 0x05, 0x8b86); 3026 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3027 rtl_writephy(tp, 0x1f, 0x0000); 3028 3029 /* Improve 2-pair detection performance */ 3030 rtl_writephy(tp, 0x1f, 0x0005); 3031 rtl_writephy(tp, 0x05, 0x8b85); 3032 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3033 rtl_writephy(tp, 0x1f, 0x0000); 3034 3035 rtl8168f_config_eee_phy(tp); 3036 rtl_enable_eee(tp); 3037 3038 /* Green feature */ 3039 rtl_writephy(tp, 0x1f, 0x0003); 3040 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000); 3041 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000); 3042 rtl_writephy(tp, 0x1f, 0x0000); 3043 rtl_writephy(tp, 0x1f, 0x0005); 3044 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000); 3045 rtl_writephy(tp, 0x1f, 0x0000); 3046 3047 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ 3048 rtl_rar_exgmac_set(tp, tp->dev->dev_addr); 3049 } 3050 3051 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) 3052 { 3053 /* For 4-corner performance improve */ 3054 rtl_writephy(tp, 0x1f, 0x0005); 3055 rtl_writephy(tp, 0x05, 0x8b80); 3056 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000); 3057 rtl_writephy(tp, 0x1f, 0x0000); 3058 3059 /* PHY auto speed down */ 3060 rtl_writephy(tp, 0x1f, 0x0007); 3061 rtl_writephy(tp, 0x1e, 0x002d); 3062 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3063 rtl_writephy(tp, 0x1f, 0x0000); 3064 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3065 3066 /* Improve 10M EEE waveform */ 3067 rtl_writephy(tp, 0x1f, 0x0005); 3068 rtl_writephy(tp, 0x05, 0x8b86); 3069 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3070 rtl_writephy(tp, 0x1f, 0x0000); 3071 3072 rtl8168f_config_eee_phy(tp); 3073 rtl_enable_eee(tp); 3074 } 3075 3076 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) 3077 { 3078 static const struct phy_reg phy_reg_init[] = { 3079 /* Channel estimation fine tune */ 3080 { 0x1f, 0x0003 }, 3081 { 0x09, 0xa20f }, 3082 { 0x1f, 0x0000 }, 3083 3084 /* Modify green table for giga & fnet */ 3085 { 0x1f, 0x0005 }, 3086 { 0x05, 0x8b55 }, 3087 { 0x06, 0x0000 }, 3088 { 0x05, 0x8b5e }, 3089 { 0x06, 0x0000 }, 3090 { 0x05, 0x8b67 }, 3091 { 0x06, 0x0000 }, 3092 { 0x05, 0x8b70 }, 3093 { 0x06, 0x0000 }, 3094 { 0x1f, 0x0000 }, 3095 { 0x1f, 0x0007 }, 3096 { 0x1e, 0x0078 }, 3097 { 0x17, 0x0000 }, 3098 { 0x19, 0x00fb }, 3099 { 0x1f, 0x0000 }, 3100 3101 /* Modify green table for 10M */ 3102 { 0x1f, 0x0005 }, 3103 { 0x05, 0x8b79 }, 3104 { 0x06, 0xaa00 }, 3105 { 0x1f, 0x0000 }, 3106 3107 /* Disable hiimpedance detection (RTCT) */ 3108 { 0x1f, 0x0003 }, 3109 { 0x01, 0x328a }, 3110 { 0x1f, 0x0000 } 3111 }; 3112 3113 rtl_apply_firmware(tp); 3114 3115 rtl_writephy_batch(tp, phy_reg_init); 3116 3117 rtl8168f_hw_phy_config(tp); 3118 3119 /* Improve 2-pair detection performance */ 3120 rtl_writephy(tp, 0x1f, 0x0005); 3121 rtl_writephy(tp, 0x05, 0x8b85); 3122 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3123 rtl_writephy(tp, 0x1f, 0x0000); 3124 } 3125 3126 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) 3127 { 3128 rtl_apply_firmware(tp); 3129 3130 rtl8168f_hw_phy_config(tp); 3131 } 3132 3133 static void rtl8411_hw_phy_config(struct rtl8169_private *tp) 3134 { 3135 static const struct phy_reg phy_reg_init[] = { 3136 /* Channel estimation fine tune */ 3137 { 0x1f, 0x0003 }, 3138 { 0x09, 0xa20f }, 3139 { 0x1f, 0x0000 }, 3140 3141 /* Modify green table for giga & fnet */ 3142 { 0x1f, 0x0005 }, 3143 { 0x05, 0x8b55 }, 3144 { 0x06, 0x0000 }, 3145 { 0x05, 0x8b5e }, 3146 { 0x06, 0x0000 }, 3147 { 0x05, 0x8b67 }, 3148 { 0x06, 0x0000 }, 3149 { 0x05, 0x8b70 }, 3150 { 0x06, 0x0000 }, 3151 { 0x1f, 0x0000 }, 3152 { 0x1f, 0x0007 }, 3153 { 0x1e, 0x0078 }, 3154 { 0x17, 0x0000 }, 3155 { 0x19, 0x00aa }, 3156 { 0x1f, 0x0000 }, 3157 3158 /* Modify green table for 10M */ 3159 { 0x1f, 0x0005 }, 3160 { 0x05, 0x8b79 }, 3161 { 0x06, 0xaa00 }, 3162 { 0x1f, 0x0000 }, 3163 3164 /* Disable hiimpedance detection (RTCT) */ 3165 { 0x1f, 0x0003 }, 3166 { 0x01, 0x328a }, 3167 { 0x1f, 0x0000 } 3168 }; 3169 3170 3171 rtl_apply_firmware(tp); 3172 3173 rtl8168f_hw_phy_config(tp); 3174 3175 /* Improve 2-pair detection performance */ 3176 rtl_writephy(tp, 0x1f, 0x0005); 3177 rtl_writephy(tp, 0x05, 0x8b85); 3178 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3179 rtl_writephy(tp, 0x1f, 0x0000); 3180 3181 rtl_writephy_batch(tp, phy_reg_init); 3182 3183 /* Modify green table for giga */ 3184 rtl_writephy(tp, 0x1f, 0x0005); 3185 rtl_writephy(tp, 0x05, 0x8b54); 3186 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3187 rtl_writephy(tp, 0x05, 0x8b5d); 3188 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3189 rtl_writephy(tp, 0x05, 0x8a7c); 3190 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3191 rtl_writephy(tp, 0x05, 0x8a7f); 3192 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000); 3193 rtl_writephy(tp, 0x05, 0x8a82); 3194 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3195 rtl_writephy(tp, 0x05, 0x8a85); 3196 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3197 rtl_writephy(tp, 0x05, 0x8a88); 3198 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3199 rtl_writephy(tp, 0x1f, 0x0000); 3200 3201 /* uc same-seed solution */ 3202 rtl_writephy(tp, 0x1f, 0x0005); 3203 rtl_writephy(tp, 0x05, 0x8b85); 3204 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000); 3205 rtl_writephy(tp, 0x1f, 0x0000); 3206 3207 /* Green feature */ 3208 rtl_writephy(tp, 0x1f, 0x0003); 3209 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); 3210 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); 3211 rtl_writephy(tp, 0x1f, 0x0000); 3212 } 3213 3214 static void rtl8168g_disable_aldps(struct rtl8169_private *tp) 3215 { 3216 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0); 3217 } 3218 3219 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp) 3220 { 3221 struct phy_device *phydev = tp->phydev; 3222 3223 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 3224 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 3225 phy_write(phydev, 0x1f, 0x0a43); 3226 phy_write(phydev, 0x13, 0x8084); 3227 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13)); 3228 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0)); 3229 3230 phy_write(phydev, 0x1f, 0x0000); 3231 } 3232 3233 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) 3234 { 3235 int ret; 3236 3237 rtl_apply_firmware(tp); 3238 3239 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10); 3240 if (ret & BIT(8)) 3241 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0); 3242 else 3243 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15)); 3244 3245 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13); 3246 if (ret & BIT(8)) 3247 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1)); 3248 else 3249 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0); 3250 3251 /* Enable PHY auto speed down */ 3252 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3253 3254 rtl8168g_phy_adjust_10m_aldps(tp); 3255 3256 /* EEE auto-fallback function */ 3257 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3258 3259 /* Enable UC LPF tune function */ 3260 rtl_writephy(tp, 0x1f, 0x0a43); 3261 rtl_writephy(tp, 0x13, 0x8012); 3262 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3263 3264 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3265 3266 /* Improve SWR Efficiency */ 3267 rtl_writephy(tp, 0x1f, 0x0bcd); 3268 rtl_writephy(tp, 0x14, 0x5065); 3269 rtl_writephy(tp, 0x14, 0xd065); 3270 rtl_writephy(tp, 0x1f, 0x0bc8); 3271 rtl_writephy(tp, 0x11, 0x5655); 3272 rtl_writephy(tp, 0x1f, 0x0bcd); 3273 rtl_writephy(tp, 0x14, 0x1065); 3274 rtl_writephy(tp, 0x14, 0x9065); 3275 rtl_writephy(tp, 0x14, 0x1065); 3276 rtl_writephy(tp, 0x1f, 0x0000); 3277 3278 rtl8168g_disable_aldps(tp); 3279 rtl8168g_config_eee_phy(tp); 3280 rtl_enable_eee(tp); 3281 } 3282 3283 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) 3284 { 3285 rtl_apply_firmware(tp); 3286 rtl8168g_config_eee_phy(tp); 3287 rtl_enable_eee(tp); 3288 } 3289 3290 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) 3291 { 3292 u16 dout_tapbin; 3293 u32 data; 3294 3295 rtl_apply_firmware(tp); 3296 3297 /* CHN EST parameters adjust - giga master */ 3298 rtl_writephy(tp, 0x1f, 0x0a43); 3299 rtl_writephy(tp, 0x13, 0x809b); 3300 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800); 3301 rtl_writephy(tp, 0x13, 0x80a2); 3302 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00); 3303 rtl_writephy(tp, 0x13, 0x80a4); 3304 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00); 3305 rtl_writephy(tp, 0x13, 0x809c); 3306 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00); 3307 rtl_writephy(tp, 0x1f, 0x0000); 3308 3309 /* CHN EST parameters adjust - giga slave */ 3310 rtl_writephy(tp, 0x1f, 0x0a43); 3311 rtl_writephy(tp, 0x13, 0x80ad); 3312 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800); 3313 rtl_writephy(tp, 0x13, 0x80b4); 3314 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00); 3315 rtl_writephy(tp, 0x13, 0x80ac); 3316 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00); 3317 rtl_writephy(tp, 0x1f, 0x0000); 3318 3319 /* CHN EST parameters adjust - fnet */ 3320 rtl_writephy(tp, 0x1f, 0x0a43); 3321 rtl_writephy(tp, 0x13, 0x808e); 3322 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00); 3323 rtl_writephy(tp, 0x13, 0x8090); 3324 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00); 3325 rtl_writephy(tp, 0x13, 0x8092); 3326 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00); 3327 rtl_writephy(tp, 0x1f, 0x0000); 3328 3329 /* enable R-tune & PGA-retune function */ 3330 dout_tapbin = 0; 3331 rtl_writephy(tp, 0x1f, 0x0a46); 3332 data = rtl_readphy(tp, 0x13); 3333 data &= 3; 3334 data <<= 2; 3335 dout_tapbin |= data; 3336 data = rtl_readphy(tp, 0x12); 3337 data &= 0xc000; 3338 data >>= 14; 3339 dout_tapbin |= data; 3340 dout_tapbin = ~(dout_tapbin^0x08); 3341 dout_tapbin <<= 12; 3342 dout_tapbin &= 0xf000; 3343 rtl_writephy(tp, 0x1f, 0x0a43); 3344 rtl_writephy(tp, 0x13, 0x827a); 3345 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3346 rtl_writephy(tp, 0x13, 0x827b); 3347 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3348 rtl_writephy(tp, 0x13, 0x827c); 3349 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3350 rtl_writephy(tp, 0x13, 0x827d); 3351 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3352 3353 rtl_writephy(tp, 0x1f, 0x0a43); 3354 rtl_writephy(tp, 0x13, 0x0811); 3355 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3356 rtl_writephy(tp, 0x1f, 0x0a42); 3357 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3358 rtl_writephy(tp, 0x1f, 0x0000); 3359 3360 /* enable GPHY 10M */ 3361 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3362 3363 /* SAR ADC performance */ 3364 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 3365 3366 rtl_writephy(tp, 0x1f, 0x0a43); 3367 rtl_writephy(tp, 0x13, 0x803f); 3368 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3369 rtl_writephy(tp, 0x13, 0x8047); 3370 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3371 rtl_writephy(tp, 0x13, 0x804f); 3372 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3373 rtl_writephy(tp, 0x13, 0x8057); 3374 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3375 rtl_writephy(tp, 0x13, 0x805f); 3376 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3377 rtl_writephy(tp, 0x13, 0x8067); 3378 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3379 rtl_writephy(tp, 0x13, 0x806f); 3380 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3381 rtl_writephy(tp, 0x1f, 0x0000); 3382 3383 /* disable phy pfm mode */ 3384 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3385 3386 rtl8168g_disable_aldps(tp); 3387 rtl8168h_config_eee_phy(tp); 3388 rtl_enable_eee(tp); 3389 } 3390 3391 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) 3392 { 3393 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; 3394 u16 rlen; 3395 u32 data; 3396 3397 rtl_apply_firmware(tp); 3398 3399 /* CHIN EST parameter update */ 3400 rtl_writephy(tp, 0x1f, 0x0a43); 3401 rtl_writephy(tp, 0x13, 0x808a); 3402 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f); 3403 rtl_writephy(tp, 0x1f, 0x0000); 3404 3405 /* enable R-tune & PGA-retune function */ 3406 rtl_writephy(tp, 0x1f, 0x0a43); 3407 rtl_writephy(tp, 0x13, 0x0811); 3408 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3409 rtl_writephy(tp, 0x1f, 0x0a42); 3410 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3411 rtl_writephy(tp, 0x1f, 0x0000); 3412 3413 /* enable GPHY 10M */ 3414 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3415 3416 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 3417 data = r8168_mac_ocp_read(tp, 0xdd02); 3418 ioffset_p3 = ((data & 0x80)>>7); 3419 ioffset_p3 <<= 3; 3420 3421 data = r8168_mac_ocp_read(tp, 0xdd00); 3422 ioffset_p3 |= ((data & (0xe000))>>13); 3423 ioffset_p2 = ((data & (0x1e00))>>9); 3424 ioffset_p1 = ((data & (0x01e0))>>5); 3425 ioffset_p0 = ((data & 0x0010)>>4); 3426 ioffset_p0 <<= 3; 3427 ioffset_p0 |= (data & (0x07)); 3428 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); 3429 3430 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || 3431 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) { 3432 rtl_writephy(tp, 0x1f, 0x0bcf); 3433 rtl_writephy(tp, 0x16, data); 3434 rtl_writephy(tp, 0x1f, 0x0000); 3435 } 3436 3437 /* Modify rlen (TX LPF corner frequency) level */ 3438 rtl_writephy(tp, 0x1f, 0x0bcd); 3439 data = rtl_readphy(tp, 0x16); 3440 data &= 0x000f; 3441 rlen = 0; 3442 if (data > 3) 3443 rlen = data - 3; 3444 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); 3445 rtl_writephy(tp, 0x17, data); 3446 rtl_writephy(tp, 0x1f, 0x0bcd); 3447 rtl_writephy(tp, 0x1f, 0x0000); 3448 3449 /* disable phy pfm mode */ 3450 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3451 3452 rtl8168g_disable_aldps(tp); 3453 rtl8168g_config_eee_phy(tp); 3454 rtl_enable_eee(tp); 3455 } 3456 3457 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) 3458 { 3459 /* Enable PHY auto speed down */ 3460 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3461 3462 rtl8168g_phy_adjust_10m_aldps(tp); 3463 3464 /* Enable EEE auto-fallback function */ 3465 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3466 3467 /* Enable UC LPF tune function */ 3468 rtl_writephy(tp, 0x1f, 0x0a43); 3469 rtl_writephy(tp, 0x13, 0x8012); 3470 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3471 rtl_writephy(tp, 0x1f, 0x0000); 3472 3473 /* set rg_sel_sdm_rate */ 3474 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3475 3476 rtl8168g_disable_aldps(tp); 3477 rtl8168g_config_eee_phy(tp); 3478 rtl_enable_eee(tp); 3479 } 3480 3481 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) 3482 { 3483 rtl8168g_phy_adjust_10m_aldps(tp); 3484 3485 /* Enable UC LPF tune function */ 3486 rtl_writephy(tp, 0x1f, 0x0a43); 3487 rtl_writephy(tp, 0x13, 0x8012); 3488 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3489 rtl_writephy(tp, 0x1f, 0x0000); 3490 3491 /* Set rg_sel_sdm_rate */ 3492 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3493 3494 /* Channel estimation parameters */ 3495 rtl_writephy(tp, 0x1f, 0x0a43); 3496 rtl_writephy(tp, 0x13, 0x80f3); 3497 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff); 3498 rtl_writephy(tp, 0x13, 0x80f0); 3499 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff); 3500 rtl_writephy(tp, 0x13, 0x80ef); 3501 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff); 3502 rtl_writephy(tp, 0x13, 0x80f6); 3503 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff); 3504 rtl_writephy(tp, 0x13, 0x80ec); 3505 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff); 3506 rtl_writephy(tp, 0x13, 0x80ed); 3507 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3508 rtl_writephy(tp, 0x13, 0x80f2); 3509 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff); 3510 rtl_writephy(tp, 0x13, 0x80f4); 3511 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff); 3512 rtl_writephy(tp, 0x1f, 0x0a43); 3513 rtl_writephy(tp, 0x13, 0x8110); 3514 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff); 3515 rtl_writephy(tp, 0x13, 0x810f); 3516 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff); 3517 rtl_writephy(tp, 0x13, 0x8111); 3518 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff); 3519 rtl_writephy(tp, 0x13, 0x8113); 3520 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff); 3521 rtl_writephy(tp, 0x13, 0x8115); 3522 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff); 3523 rtl_writephy(tp, 0x13, 0x810e); 3524 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff); 3525 rtl_writephy(tp, 0x13, 0x810c); 3526 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3527 rtl_writephy(tp, 0x13, 0x810b); 3528 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff); 3529 rtl_writephy(tp, 0x1f, 0x0a43); 3530 rtl_writephy(tp, 0x13, 0x80d1); 3531 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff); 3532 rtl_writephy(tp, 0x13, 0x80cd); 3533 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff); 3534 rtl_writephy(tp, 0x13, 0x80d3); 3535 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff); 3536 rtl_writephy(tp, 0x13, 0x80d5); 3537 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff); 3538 rtl_writephy(tp, 0x13, 0x80d7); 3539 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff); 3540 3541 /* Force PWM-mode */ 3542 rtl_writephy(tp, 0x1f, 0x0bcd); 3543 rtl_writephy(tp, 0x14, 0x5065); 3544 rtl_writephy(tp, 0x14, 0xd065); 3545 rtl_writephy(tp, 0x1f, 0x0bc8); 3546 rtl_writephy(tp, 0x12, 0x00ed); 3547 rtl_writephy(tp, 0x1f, 0x0bcd); 3548 rtl_writephy(tp, 0x14, 0x1065); 3549 rtl_writephy(tp, 0x14, 0x9065); 3550 rtl_writephy(tp, 0x14, 0x1065); 3551 rtl_writephy(tp, 0x1f, 0x0000); 3552 3553 rtl8168g_disable_aldps(tp); 3554 rtl8168g_config_eee_phy(tp); 3555 rtl_enable_eee(tp); 3556 } 3557 3558 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) 3559 { 3560 static const struct phy_reg phy_reg_init[] = { 3561 { 0x1f, 0x0003 }, 3562 { 0x08, 0x441d }, 3563 { 0x01, 0x9100 }, 3564 { 0x1f, 0x0000 } 3565 }; 3566 3567 rtl_writephy(tp, 0x1f, 0x0000); 3568 rtl_patchphy(tp, 0x11, 1 << 12); 3569 rtl_patchphy(tp, 0x19, 1 << 13); 3570 rtl_patchphy(tp, 0x10, 1 << 15); 3571 3572 rtl_writephy_batch(tp, phy_reg_init); 3573 } 3574 3575 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) 3576 { 3577 static const struct phy_reg phy_reg_init[] = { 3578 { 0x1f, 0x0005 }, 3579 { 0x1a, 0x0000 }, 3580 { 0x1f, 0x0000 }, 3581 3582 { 0x1f, 0x0004 }, 3583 { 0x1c, 0x0000 }, 3584 { 0x1f, 0x0000 }, 3585 3586 { 0x1f, 0x0001 }, 3587 { 0x15, 0x7701 }, 3588 { 0x1f, 0x0000 } 3589 }; 3590 3591 /* Disable ALDPS before ram code */ 3592 rtl_writephy(tp, 0x1f, 0x0000); 3593 rtl_writephy(tp, 0x18, 0x0310); 3594 msleep(100); 3595 3596 rtl_apply_firmware(tp); 3597 3598 rtl_writephy_batch(tp, phy_reg_init); 3599 } 3600 3601 static void rtl8402_hw_phy_config(struct rtl8169_private *tp) 3602 { 3603 /* Disable ALDPS before setting firmware */ 3604 rtl_writephy(tp, 0x1f, 0x0000); 3605 rtl_writephy(tp, 0x18, 0x0310); 3606 msleep(20); 3607 3608 rtl_apply_firmware(tp); 3609 3610 /* EEE setting */ 3611 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3612 rtl_writephy(tp, 0x1f, 0x0004); 3613 rtl_writephy(tp, 0x10, 0x401f); 3614 rtl_writephy(tp, 0x19, 0x7030); 3615 rtl_writephy(tp, 0x1f, 0x0000); 3616 } 3617 3618 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) 3619 { 3620 static const struct phy_reg phy_reg_init[] = { 3621 { 0x1f, 0x0004 }, 3622 { 0x10, 0xc07f }, 3623 { 0x19, 0x7030 }, 3624 { 0x1f, 0x0000 } 3625 }; 3626 3627 /* Disable ALDPS before ram code */ 3628 rtl_writephy(tp, 0x1f, 0x0000); 3629 rtl_writephy(tp, 0x18, 0x0310); 3630 msleep(100); 3631 3632 rtl_apply_firmware(tp); 3633 3634 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3635 rtl_writephy_batch(tp, phy_reg_init); 3636 3637 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3638 } 3639 3640 static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp) 3641 { 3642 struct phy_device *phydev = tp->phydev; 3643 3644 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084); 3645 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3646 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006); 3647 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3648 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100); 3649 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000); 3650 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400); 3651 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff); 3652 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff); 3653 3654 phy_write(phydev, 0x1f, 0x0a43); 3655 phy_write(phydev, 0x13, 0x80ea); 3656 phy_modify(phydev, 0x14, 0xff00, 0xc400); 3657 phy_write(phydev, 0x13, 0x80eb); 3658 phy_modify(phydev, 0x14, 0x0700, 0x0300); 3659 phy_write(phydev, 0x13, 0x80f8); 3660 phy_modify(phydev, 0x14, 0xff00, 0x1c00); 3661 phy_write(phydev, 0x13, 0x80f1); 3662 phy_modify(phydev, 0x14, 0xff00, 0x3000); 3663 phy_write(phydev, 0x13, 0x80fe); 3664 phy_modify(phydev, 0x14, 0xff00, 0xa500); 3665 phy_write(phydev, 0x13, 0x8102); 3666 phy_modify(phydev, 0x14, 0xff00, 0x5000); 3667 phy_write(phydev, 0x13, 0x8105); 3668 phy_modify(phydev, 0x14, 0xff00, 0x3300); 3669 phy_write(phydev, 0x13, 0x8100); 3670 phy_modify(phydev, 0x14, 0xff00, 0x7000); 3671 phy_write(phydev, 0x13, 0x8104); 3672 phy_modify(phydev, 0x14, 0xff00, 0xf000); 3673 phy_write(phydev, 0x13, 0x8106); 3674 phy_modify(phydev, 0x14, 0xff00, 0x6500); 3675 phy_write(phydev, 0x13, 0x80dc); 3676 phy_modify(phydev, 0x14, 0xff00, 0xed00); 3677 phy_write(phydev, 0x13, 0x80df); 3678 phy_set_bits(phydev, 0x14, BIT(8)); 3679 phy_write(phydev, 0x13, 0x80e1); 3680 phy_clear_bits(phydev, 0x14, BIT(8)); 3681 phy_write(phydev, 0x1f, 0x0000); 3682 3683 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038); 3684 phy_write_paged(phydev, 0xa43, 0x13, 0x819f); 3685 phy_write_paged(phydev, 0xa43, 0x14, 0xd0b6); 3686 3687 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555); 3688 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00); 3689 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000); 3690 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3691 3692 rtl8125_config_eee_phy(tp); 3693 rtl_enable_eee(tp); 3694 } 3695 3696 static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp) 3697 { 3698 struct phy_device *phydev = tp->phydev; 3699 int i; 3700 3701 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3702 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 3703 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3704 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 3705 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 3706 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 3707 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 3708 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 3709 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 3710 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 3711 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 3712 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 3713 3714 phy_write(phydev, 0x1f, 0x0b87); 3715 phy_write(phydev, 0x16, 0x80a2); 3716 phy_write(phydev, 0x17, 0x0153); 3717 phy_write(phydev, 0x16, 0x809c); 3718 phy_write(phydev, 0x17, 0x0153); 3719 phy_write(phydev, 0x1f, 0x0000); 3720 3721 phy_write(phydev, 0x1f, 0x0a43); 3722 phy_write(phydev, 0x13, 0x81B3); 3723 phy_write(phydev, 0x14, 0x0043); 3724 phy_write(phydev, 0x14, 0x00A7); 3725 phy_write(phydev, 0x14, 0x00D6); 3726 phy_write(phydev, 0x14, 0x00EC); 3727 phy_write(phydev, 0x14, 0x00F6); 3728 phy_write(phydev, 0x14, 0x00FB); 3729 phy_write(phydev, 0x14, 0x00FD); 3730 phy_write(phydev, 0x14, 0x00FF); 3731 phy_write(phydev, 0x14, 0x00BB); 3732 phy_write(phydev, 0x14, 0x0058); 3733 phy_write(phydev, 0x14, 0x0029); 3734 phy_write(phydev, 0x14, 0x0013); 3735 phy_write(phydev, 0x14, 0x0009); 3736 phy_write(phydev, 0x14, 0x0004); 3737 phy_write(phydev, 0x14, 0x0002); 3738 for (i = 0; i < 25; i++) 3739 phy_write(phydev, 0x14, 0x0000); 3740 3741 phy_write(phydev, 0x13, 0x8257); 3742 phy_write(phydev, 0x14, 0x020F); 3743 3744 phy_write(phydev, 0x13, 0x80EA); 3745 phy_write(phydev, 0x14, 0x7843); 3746 phy_write(phydev, 0x1f, 0x0000); 3747 3748 rtl_apply_firmware(tp); 3749 3750 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 3751 3752 phy_write(phydev, 0x1f, 0x0a43); 3753 phy_write(phydev, 0x13, 0x81a2); 3754 phy_set_bits(phydev, 0x14, BIT(8)); 3755 phy_write(phydev, 0x1f, 0x0000); 3756 3757 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 3758 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 3759 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 3760 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 3761 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 3762 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3763 3764 rtl8125_config_eee_phy(tp); 3765 rtl_enable_eee(tp); 3766 } 3767 3768 static void rtl_hw_phy_config(struct net_device *dev) 3769 { 3770 static const rtl_generic_fct phy_configs[] = { 3771 /* PCI devices. */ 3772 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 3773 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 3774 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 3775 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 3776 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 3777 /* PCI-E devices. */ 3778 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 3779 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 3780 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 3781 [RTL_GIGA_MAC_VER_10] = NULL, 3782 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 3783 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 3784 [RTL_GIGA_MAC_VER_13] = NULL, 3785 [RTL_GIGA_MAC_VER_14] = NULL, 3786 [RTL_GIGA_MAC_VER_15] = NULL, 3787 [RTL_GIGA_MAC_VER_16] = NULL, 3788 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 3789 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 3790 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 3791 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 3792 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 3793 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config, 3794 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 3795 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 3796 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 3797 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 3798 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 3799 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 3800 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 3801 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 3802 [RTL_GIGA_MAC_VER_31] = NULL, 3803 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 3804 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 3805 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 3806 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 3807 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 3808 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 3809 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 3810 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 3811 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 3812 [RTL_GIGA_MAC_VER_41] = NULL, 3813 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 3814 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 3815 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 3816 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 3817 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 3818 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 3819 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 3820 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 3821 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 3822 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 3823 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config, 3824 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config, 3825 }; 3826 struct rtl8169_private *tp = netdev_priv(dev); 3827 3828 if (phy_configs[tp->mac_version]) 3829 phy_configs[tp->mac_version](tp); 3830 } 3831 3832 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 3833 { 3834 if (!test_and_set_bit(flag, tp->wk.flags)) 3835 schedule_work(&tp->wk.work); 3836 } 3837 3838 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 3839 { 3840 rtl_hw_phy_config(dev); 3841 3842 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 3843 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 3844 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 3845 netif_dbg(tp, drv, dev, 3846 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 3847 RTL_W8(tp, 0x82, 0x01); 3848 } 3849 3850 /* We may have called phy_speed_down before */ 3851 phy_speed_up(tp->phydev); 3852 3853 genphy_soft_reset(tp->phydev); 3854 } 3855 3856 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 3857 { 3858 rtl_lock_work(tp); 3859 3860 rtl_unlock_config_regs(tp); 3861 3862 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 3863 RTL_R32(tp, MAC4); 3864 3865 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3866 RTL_R32(tp, MAC0); 3867 3868 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 3869 rtl_rar_exgmac_set(tp, addr); 3870 3871 rtl_lock_config_regs(tp); 3872 3873 rtl_unlock_work(tp); 3874 } 3875 3876 static int rtl_set_mac_address(struct net_device *dev, void *p) 3877 { 3878 struct rtl8169_private *tp = netdev_priv(dev); 3879 struct device *d = tp_to_dev(tp); 3880 int ret; 3881 3882 ret = eth_mac_addr(dev, p); 3883 if (ret) 3884 return ret; 3885 3886 pm_runtime_get_noresume(d); 3887 3888 if (pm_runtime_active(d)) 3889 rtl_rar_set(tp, dev->dev_addr); 3890 3891 pm_runtime_put_noidle(d); 3892 3893 return 0; 3894 } 3895 3896 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3897 { 3898 struct rtl8169_private *tp = netdev_priv(dev); 3899 3900 if (!netif_running(dev)) 3901 return -ENODEV; 3902 3903 return phy_mii_ioctl(tp->phydev, ifr, cmd); 3904 } 3905 3906 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 3907 { 3908 switch (tp->mac_version) { 3909 case RTL_GIGA_MAC_VER_25: 3910 case RTL_GIGA_MAC_VER_26: 3911 case RTL_GIGA_MAC_VER_29: 3912 case RTL_GIGA_MAC_VER_30: 3913 case RTL_GIGA_MAC_VER_32: 3914 case RTL_GIGA_MAC_VER_33: 3915 case RTL_GIGA_MAC_VER_34: 3916 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51: 3917 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 3918 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 3919 break; 3920 default: 3921 break; 3922 } 3923 } 3924 3925 static void rtl_pll_power_down(struct rtl8169_private *tp) 3926 { 3927 if (r8168_check_dash(tp)) 3928 return; 3929 3930 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 3931 tp->mac_version == RTL_GIGA_MAC_VER_33) 3932 rtl_ephy_write(tp, 0x19, 0xff64); 3933 3934 if (device_may_wakeup(tp_to_dev(tp))) { 3935 phy_speed_down(tp->phydev, false); 3936 rtl_wol_suspend_quirk(tp); 3937 return; 3938 } 3939 3940 switch (tp->mac_version) { 3941 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3942 case RTL_GIGA_MAC_VER_37: 3943 case RTL_GIGA_MAC_VER_39: 3944 case RTL_GIGA_MAC_VER_43: 3945 case RTL_GIGA_MAC_VER_44: 3946 case RTL_GIGA_MAC_VER_45: 3947 case RTL_GIGA_MAC_VER_46: 3948 case RTL_GIGA_MAC_VER_47: 3949 case RTL_GIGA_MAC_VER_48: 3950 case RTL_GIGA_MAC_VER_50: 3951 case RTL_GIGA_MAC_VER_51: 3952 case RTL_GIGA_MAC_VER_60: 3953 case RTL_GIGA_MAC_VER_61: 3954 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3955 break; 3956 case RTL_GIGA_MAC_VER_40: 3957 case RTL_GIGA_MAC_VER_41: 3958 case RTL_GIGA_MAC_VER_49: 3959 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3960 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3961 break; 3962 default: 3963 break; 3964 } 3965 } 3966 3967 static void rtl_pll_power_up(struct rtl8169_private *tp) 3968 { 3969 switch (tp->mac_version) { 3970 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3971 case RTL_GIGA_MAC_VER_37: 3972 case RTL_GIGA_MAC_VER_39: 3973 case RTL_GIGA_MAC_VER_43: 3974 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 3975 break; 3976 case RTL_GIGA_MAC_VER_44: 3977 case RTL_GIGA_MAC_VER_45: 3978 case RTL_GIGA_MAC_VER_46: 3979 case RTL_GIGA_MAC_VER_47: 3980 case RTL_GIGA_MAC_VER_48: 3981 case RTL_GIGA_MAC_VER_50: 3982 case RTL_GIGA_MAC_VER_51: 3983 case RTL_GIGA_MAC_VER_60: 3984 case RTL_GIGA_MAC_VER_61: 3985 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3986 break; 3987 case RTL_GIGA_MAC_VER_40: 3988 case RTL_GIGA_MAC_VER_41: 3989 case RTL_GIGA_MAC_VER_49: 3990 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3991 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3992 break; 3993 default: 3994 break; 3995 } 3996 3997 phy_resume(tp->phydev); 3998 /* give MAC/PHY some time to resume */ 3999 msleep(20); 4000 } 4001 4002 static void rtl_init_rxcfg(struct rtl8169_private *tp) 4003 { 4004 switch (tp->mac_version) { 4005 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4006 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4007 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 4008 break; 4009 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 4010 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 4011 case RTL_GIGA_MAC_VER_38: 4012 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 4013 break; 4014 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 4015 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 4016 break; 4017 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 4018 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 | 4019 RX_DMA_BURST); 4020 break; 4021 default: 4022 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 4023 break; 4024 } 4025 } 4026 4027 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 4028 { 4029 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 4030 } 4031 4032 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 4033 { 4034 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4035 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 4036 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); 4037 } 4038 4039 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 4040 { 4041 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4042 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 4043 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4044 } 4045 4046 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 4047 { 4048 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4049 } 4050 4051 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 4052 { 4053 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4054 } 4055 4056 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 4057 { 4058 RTL_W8(tp, MaxTxPacketSize, 0x3f); 4059 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4060 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 4061 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); 4062 } 4063 4064 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 4065 { 4066 RTL_W8(tp, MaxTxPacketSize, 0x0c); 4067 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4068 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 4069 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4070 } 4071 4072 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) 4073 { 4074 rtl_tx_performance_tweak(tp, 4075 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN); 4076 } 4077 4078 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) 4079 { 4080 rtl_tx_performance_tweak(tp, 4081 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN); 4082 } 4083 4084 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 4085 { 4086 r8168b_0_hw_jumbo_enable(tp); 4087 4088 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 4089 } 4090 4091 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 4092 { 4093 r8168b_0_hw_jumbo_disable(tp); 4094 4095 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 4096 } 4097 4098 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) 4099 { 4100 rtl_unlock_config_regs(tp); 4101 switch (tp->mac_version) { 4102 case RTL_GIGA_MAC_VER_11: 4103 r8168b_0_hw_jumbo_enable(tp); 4104 break; 4105 case RTL_GIGA_MAC_VER_12: 4106 case RTL_GIGA_MAC_VER_17: 4107 r8168b_1_hw_jumbo_enable(tp); 4108 break; 4109 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 4110 r8168c_hw_jumbo_enable(tp); 4111 break; 4112 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 4113 r8168dp_hw_jumbo_enable(tp); 4114 break; 4115 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4116 r8168e_hw_jumbo_enable(tp); 4117 break; 4118 default: 4119 break; 4120 } 4121 rtl_lock_config_regs(tp); 4122 } 4123 4124 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) 4125 { 4126 rtl_unlock_config_regs(tp); 4127 switch (tp->mac_version) { 4128 case RTL_GIGA_MAC_VER_11: 4129 r8168b_0_hw_jumbo_disable(tp); 4130 break; 4131 case RTL_GIGA_MAC_VER_12: 4132 case RTL_GIGA_MAC_VER_17: 4133 r8168b_1_hw_jumbo_disable(tp); 4134 break; 4135 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 4136 r8168c_hw_jumbo_disable(tp); 4137 break; 4138 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 4139 r8168dp_hw_jumbo_disable(tp); 4140 break; 4141 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4142 r8168e_hw_jumbo_disable(tp); 4143 break; 4144 default: 4145 break; 4146 } 4147 rtl_lock_config_regs(tp); 4148 } 4149 4150 DECLARE_RTL_COND(rtl_chipcmd_cond) 4151 { 4152 return RTL_R8(tp, ChipCmd) & CmdReset; 4153 } 4154 4155 static void rtl_hw_reset(struct rtl8169_private *tp) 4156 { 4157 RTL_W8(tp, ChipCmd, CmdReset); 4158 4159 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 4160 } 4161 4162 static void rtl_request_firmware(struct rtl8169_private *tp) 4163 { 4164 struct rtl_fw *rtl_fw; 4165 4166 /* firmware loaded already or no firmware available */ 4167 if (tp->rtl_fw || !tp->fw_name) 4168 return; 4169 4170 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 4171 if (!rtl_fw) { 4172 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 4173 return; 4174 } 4175 4176 rtl_fw->phy_write = rtl_writephy; 4177 rtl_fw->phy_read = rtl_readphy; 4178 rtl_fw->mac_mcu_write = mac_mcu_write; 4179 rtl_fw->mac_mcu_read = mac_mcu_read; 4180 rtl_fw->fw_name = tp->fw_name; 4181 rtl_fw->dev = tp_to_dev(tp); 4182 4183 if (rtl_fw_request_firmware(rtl_fw)) 4184 kfree(rtl_fw); 4185 else 4186 tp->rtl_fw = rtl_fw; 4187 } 4188 4189 static void rtl_rx_close(struct rtl8169_private *tp) 4190 { 4191 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 4192 } 4193 4194 DECLARE_RTL_COND(rtl_npq_cond) 4195 { 4196 return RTL_R8(tp, TxPoll) & NPQ; 4197 } 4198 4199 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 4200 { 4201 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 4202 } 4203 4204 static void rtl8169_hw_reset(struct rtl8169_private *tp) 4205 { 4206 /* Disable interrupts */ 4207 rtl8169_irq_mask_and_ack(tp); 4208 4209 rtl_rx_close(tp); 4210 4211 switch (tp->mac_version) { 4212 case RTL_GIGA_MAC_VER_27: 4213 case RTL_GIGA_MAC_VER_28: 4214 case RTL_GIGA_MAC_VER_31: 4215 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 4216 break; 4217 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4218 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 4219 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4220 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4221 break; 4222 default: 4223 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4224 udelay(100); 4225 break; 4226 } 4227 4228 rtl_hw_reset(tp); 4229 } 4230 4231 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 4232 { 4233 u32 val = TX_DMA_BURST << TxDMAShift | 4234 InterFrameGap << TxInterFrameGapShift; 4235 4236 if (rtl_is_8168evl_up(tp)) 4237 val |= TXCFG_AUTO_FIFO; 4238 4239 RTL_W32(tp, TxConfig, val); 4240 } 4241 4242 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 4243 { 4244 /* Low hurts. Let's disable the filtering. */ 4245 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 4246 } 4247 4248 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 4249 { 4250 /* 4251 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 4252 * register to be written before TxDescAddrLow to work. 4253 * Switching from MMIO to I/O access fixes the issue as well. 4254 */ 4255 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 4256 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 4257 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 4258 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 4259 } 4260 4261 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 4262 { 4263 u32 val; 4264 4265 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 4266 val = 0x000fff00; 4267 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 4268 val = 0x00ffff00; 4269 else 4270 return; 4271 4272 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 4273 val |= 0xff; 4274 4275 RTL_W32(tp, 0x7c, val); 4276 } 4277 4278 static void rtl_set_rx_mode(struct net_device *dev) 4279 { 4280 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 4281 /* Multicast hash filter */ 4282 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 4283 struct rtl8169_private *tp = netdev_priv(dev); 4284 u32 tmp; 4285 4286 if (dev->flags & IFF_PROMISC) { 4287 /* Unconditionally log net taps. */ 4288 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 4289 rx_mode |= AcceptAllPhys; 4290 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 4291 dev->flags & IFF_ALLMULTI || 4292 tp->mac_version == RTL_GIGA_MAC_VER_35) { 4293 /* accept all multicasts */ 4294 } else if (netdev_mc_empty(dev)) { 4295 rx_mode &= ~AcceptMulticast; 4296 } else { 4297 struct netdev_hw_addr *ha; 4298 4299 mc_filter[1] = mc_filter[0] = 0; 4300 netdev_for_each_mc_addr(ha, dev) { 4301 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 4302 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 4303 } 4304 4305 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 4306 tmp = mc_filter[0]; 4307 mc_filter[0] = swab32(mc_filter[1]); 4308 mc_filter[1] = swab32(tmp); 4309 } 4310 } 4311 4312 if (dev->features & NETIF_F_RXALL) 4313 rx_mode |= (AcceptErr | AcceptRunt); 4314 4315 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 4316 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 4317 4318 tmp = RTL_R32(tp, RxConfig); 4319 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); 4320 } 4321 4322 DECLARE_RTL_COND(rtl_csiar_cond) 4323 { 4324 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 4325 } 4326 4327 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 4328 { 4329 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4330 4331 RTL_W32(tp, CSIDR, value); 4332 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 4333 CSIAR_BYTE_ENABLE | func << 16); 4334 4335 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 4336 } 4337 4338 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 4339 { 4340 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4341 4342 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 4343 CSIAR_BYTE_ENABLE); 4344 4345 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 4346 RTL_R32(tp, CSIDR) : ~0; 4347 } 4348 4349 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 4350 { 4351 struct pci_dev *pdev = tp->pci_dev; 4352 u32 csi; 4353 4354 /* According to Realtek the value at config space address 0x070f 4355 * controls the L0s/L1 entrance latency. We try standard ECAM access 4356 * first and if it fails fall back to CSI. 4357 */ 4358 if (pdev->cfg_size > 0x070f && 4359 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 4360 return; 4361 4362 netdev_notice_once(tp->dev, 4363 "No native access to PCI extended config space, falling back to CSI\n"); 4364 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 4365 rtl_csi_write(tp, 0x070c, csi | val << 24); 4366 } 4367 4368 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 4369 { 4370 rtl_csi_access_enable(tp, 0x27); 4371 } 4372 4373 struct ephy_info { 4374 unsigned int offset; 4375 u16 mask; 4376 u16 bits; 4377 }; 4378 4379 static void __rtl_ephy_init(struct rtl8169_private *tp, 4380 const struct ephy_info *e, int len) 4381 { 4382 u16 w; 4383 4384 while (len-- > 0) { 4385 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 4386 rtl_ephy_write(tp, e->offset, w); 4387 e++; 4388 } 4389 } 4390 4391 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 4392 4393 static void rtl_disable_clock_request(struct rtl8169_private *tp) 4394 { 4395 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 4396 PCI_EXP_LNKCTL_CLKREQ_EN); 4397 } 4398 4399 static void rtl_enable_clock_request(struct rtl8169_private *tp) 4400 { 4401 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 4402 PCI_EXP_LNKCTL_CLKREQ_EN); 4403 } 4404 4405 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 4406 { 4407 /* work around an issue when PCI reset occurs during L2/L3 state */ 4408 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 4409 } 4410 4411 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 4412 { 4413 /* Don't enable ASPM in the chip if OS can't control ASPM */ 4414 if (enable && tp->aspm_manageable) { 4415 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 4416 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 4417 } else { 4418 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4419 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4420 } 4421 4422 udelay(10); 4423 } 4424 4425 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 4426 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 4427 { 4428 /* Usage of dynamic vs. static FIFO is controlled by bit 4429 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 4430 */ 4431 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 4432 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 4433 } 4434 4435 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 4436 u8 low, u8 high) 4437 { 4438 /* FIFO thresholds for pause flow control */ 4439 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 4440 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 4441 } 4442 4443 static void rtl_hw_start_8168bb(struct rtl8169_private *tp) 4444 { 4445 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4446 4447 if (tp->dev->mtu <= ETH_DATA_LEN) { 4448 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B | 4449 PCI_EXP_DEVCTL_NOSNOOP_EN); 4450 } 4451 } 4452 4453 static void rtl_hw_start_8168bef(struct rtl8169_private *tp) 4454 { 4455 rtl_hw_start_8168bb(tp); 4456 4457 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 4458 } 4459 4460 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 4461 { 4462 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 4463 4464 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4465 4466 if (tp->dev->mtu <= ETH_DATA_LEN) 4467 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4468 4469 rtl_disable_clock_request(tp); 4470 } 4471 4472 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 4473 { 4474 static const struct ephy_info e_info_8168cp[] = { 4475 { 0x01, 0, 0x0001 }, 4476 { 0x02, 0x0800, 0x1000 }, 4477 { 0x03, 0, 0x0042 }, 4478 { 0x06, 0x0080, 0x0000 }, 4479 { 0x07, 0, 0x2000 } 4480 }; 4481 4482 rtl_set_def_aspm_entry_latency(tp); 4483 4484 rtl_ephy_init(tp, e_info_8168cp); 4485 4486 __rtl_hw_start_8168cp(tp); 4487 } 4488 4489 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 4490 { 4491 rtl_set_def_aspm_entry_latency(tp); 4492 4493 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4494 4495 if (tp->dev->mtu <= ETH_DATA_LEN) 4496 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4497 } 4498 4499 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 4500 { 4501 rtl_set_def_aspm_entry_latency(tp); 4502 4503 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4504 4505 /* Magic. */ 4506 RTL_W8(tp, DBG_REG, 0x20); 4507 4508 if (tp->dev->mtu <= ETH_DATA_LEN) 4509 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4510 } 4511 4512 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 4513 { 4514 static const struct ephy_info e_info_8168c_1[] = { 4515 { 0x02, 0x0800, 0x1000 }, 4516 { 0x03, 0, 0x0002 }, 4517 { 0x06, 0x0080, 0x0000 } 4518 }; 4519 4520 rtl_set_def_aspm_entry_latency(tp); 4521 4522 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 4523 4524 rtl_ephy_init(tp, e_info_8168c_1); 4525 4526 __rtl_hw_start_8168cp(tp); 4527 } 4528 4529 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 4530 { 4531 static const struct ephy_info e_info_8168c_2[] = { 4532 { 0x01, 0, 0x0001 }, 4533 { 0x03, 0x0400, 0x0020 } 4534 }; 4535 4536 rtl_set_def_aspm_entry_latency(tp); 4537 4538 rtl_ephy_init(tp, e_info_8168c_2); 4539 4540 __rtl_hw_start_8168cp(tp); 4541 } 4542 4543 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 4544 { 4545 rtl_hw_start_8168c_2(tp); 4546 } 4547 4548 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 4549 { 4550 rtl_set_def_aspm_entry_latency(tp); 4551 4552 __rtl_hw_start_8168cp(tp); 4553 } 4554 4555 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 4556 { 4557 rtl_set_def_aspm_entry_latency(tp); 4558 4559 rtl_disable_clock_request(tp); 4560 4561 if (tp->dev->mtu <= ETH_DATA_LEN) 4562 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4563 } 4564 4565 static void rtl_hw_start_8168dp(struct rtl8169_private *tp) 4566 { 4567 rtl_set_def_aspm_entry_latency(tp); 4568 4569 if (tp->dev->mtu <= ETH_DATA_LEN) 4570 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4571 4572 rtl_disable_clock_request(tp); 4573 } 4574 4575 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 4576 { 4577 static const struct ephy_info e_info_8168d_4[] = { 4578 { 0x0b, 0x0000, 0x0048 }, 4579 { 0x19, 0x0020, 0x0050 }, 4580 { 0x0c, 0x0100, 0x0020 }, 4581 { 0x10, 0x0004, 0x0000 }, 4582 }; 4583 4584 rtl_set_def_aspm_entry_latency(tp); 4585 4586 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4587 4588 rtl_ephy_init(tp, e_info_8168d_4); 4589 4590 rtl_enable_clock_request(tp); 4591 } 4592 4593 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 4594 { 4595 static const struct ephy_info e_info_8168e_1[] = { 4596 { 0x00, 0x0200, 0x0100 }, 4597 { 0x00, 0x0000, 0x0004 }, 4598 { 0x06, 0x0002, 0x0001 }, 4599 { 0x06, 0x0000, 0x0030 }, 4600 { 0x07, 0x0000, 0x2000 }, 4601 { 0x00, 0x0000, 0x0020 }, 4602 { 0x03, 0x5800, 0x2000 }, 4603 { 0x03, 0x0000, 0x0001 }, 4604 { 0x01, 0x0800, 0x1000 }, 4605 { 0x07, 0x0000, 0x4000 }, 4606 { 0x1e, 0x0000, 0x2000 }, 4607 { 0x19, 0xffff, 0xfe6c }, 4608 { 0x0a, 0x0000, 0x0040 } 4609 }; 4610 4611 rtl_set_def_aspm_entry_latency(tp); 4612 4613 rtl_ephy_init(tp, e_info_8168e_1); 4614 4615 if (tp->dev->mtu <= ETH_DATA_LEN) 4616 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4617 4618 rtl_disable_clock_request(tp); 4619 4620 /* Reset tx FIFO pointer */ 4621 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 4622 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 4623 4624 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4625 } 4626 4627 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 4628 { 4629 static const struct ephy_info e_info_8168e_2[] = { 4630 { 0x09, 0x0000, 0x0080 }, 4631 { 0x19, 0x0000, 0x0224 }, 4632 { 0x00, 0x0000, 0x0004 }, 4633 { 0x0c, 0x3df0, 0x0200 }, 4634 }; 4635 4636 rtl_set_def_aspm_entry_latency(tp); 4637 4638 rtl_ephy_init(tp, e_info_8168e_2); 4639 4640 if (tp->dev->mtu <= ETH_DATA_LEN) 4641 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4642 4643 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4644 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4645 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4646 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4647 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 4648 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4649 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4650 4651 rtl_disable_clock_request(tp); 4652 4653 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4654 4655 rtl8168_config_eee_mac(tp); 4656 4657 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4658 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4659 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4660 4661 rtl_hw_aspm_clkreq_enable(tp, true); 4662 } 4663 4664 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 4665 { 4666 rtl_set_def_aspm_entry_latency(tp); 4667 4668 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4669 4670 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4671 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4672 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4673 rtl_reset_packet_filter(tp); 4674 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4675 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 4676 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4677 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 4678 4679 rtl_disable_clock_request(tp); 4680 4681 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4682 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4683 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4684 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4685 4686 rtl8168_config_eee_mac(tp); 4687 } 4688 4689 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 4690 { 4691 static const struct ephy_info e_info_8168f_1[] = { 4692 { 0x06, 0x00c0, 0x0020 }, 4693 { 0x08, 0x0001, 0x0002 }, 4694 { 0x09, 0x0000, 0x0080 }, 4695 { 0x19, 0x0000, 0x0224 }, 4696 { 0x00, 0x0000, 0x0004 }, 4697 { 0x0c, 0x3df0, 0x0200 }, 4698 }; 4699 4700 rtl_hw_start_8168f(tp); 4701 4702 rtl_ephy_init(tp, e_info_8168f_1); 4703 4704 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4705 } 4706 4707 static void rtl_hw_start_8411(struct rtl8169_private *tp) 4708 { 4709 static const struct ephy_info e_info_8168f_1[] = { 4710 { 0x06, 0x00c0, 0x0020 }, 4711 { 0x0f, 0xffff, 0x5200 }, 4712 { 0x19, 0x0000, 0x0224 }, 4713 { 0x00, 0x0000, 0x0004 }, 4714 { 0x0c, 0x3df0, 0x0200 }, 4715 }; 4716 4717 rtl_hw_start_8168f(tp); 4718 rtl_pcie_state_l2l3_disable(tp); 4719 4720 rtl_ephy_init(tp, e_info_8168f_1); 4721 4722 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 4723 } 4724 4725 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 4726 { 4727 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4728 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4729 4730 rtl_set_def_aspm_entry_latency(tp); 4731 4732 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4733 4734 rtl_reset_packet_filter(tp); 4735 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 4736 4737 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4738 4739 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4740 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4741 4742 rtl8168_config_eee_mac(tp); 4743 4744 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4745 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4746 4747 rtl_pcie_state_l2l3_disable(tp); 4748 } 4749 4750 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 4751 { 4752 static const struct ephy_info e_info_8168g_1[] = { 4753 { 0x00, 0x0008, 0x0000 }, 4754 { 0x0c, 0x3ff0, 0x0820 }, 4755 { 0x1e, 0x0000, 0x0001 }, 4756 { 0x19, 0x8000, 0x0000 } 4757 }; 4758 4759 rtl_hw_start_8168g(tp); 4760 4761 /* disable aspm and clock request before access ephy */ 4762 rtl_hw_aspm_clkreq_enable(tp, false); 4763 rtl_ephy_init(tp, e_info_8168g_1); 4764 rtl_hw_aspm_clkreq_enable(tp, true); 4765 } 4766 4767 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 4768 { 4769 static const struct ephy_info e_info_8168g_2[] = { 4770 { 0x00, 0x0008, 0x0000 }, 4771 { 0x0c, 0x3ff0, 0x0820 }, 4772 { 0x19, 0xffff, 0x7c00 }, 4773 { 0x1e, 0xffff, 0x20eb }, 4774 { 0x0d, 0xffff, 0x1666 }, 4775 { 0x00, 0xffff, 0x10a3 }, 4776 { 0x06, 0xffff, 0xf050 }, 4777 { 0x04, 0x0000, 0x0010 }, 4778 { 0x1d, 0x4000, 0x0000 }, 4779 }; 4780 4781 rtl_hw_start_8168g(tp); 4782 4783 /* disable aspm and clock request before access ephy */ 4784 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4785 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4786 rtl_ephy_init(tp, e_info_8168g_2); 4787 } 4788 4789 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 4790 { 4791 static const struct ephy_info e_info_8411_2[] = { 4792 { 0x00, 0x0008, 0x0000 }, 4793 { 0x0c, 0x37d0, 0x0820 }, 4794 { 0x1e, 0x0000, 0x0001 }, 4795 { 0x19, 0x8021, 0x0000 }, 4796 { 0x1e, 0x0000, 0x2000 }, 4797 { 0x0d, 0x0100, 0x0200 }, 4798 { 0x00, 0x0000, 0x0080 }, 4799 { 0x06, 0x0000, 0x0010 }, 4800 { 0x04, 0x0000, 0x0010 }, 4801 { 0x1d, 0x0000, 0x4000 }, 4802 }; 4803 4804 rtl_hw_start_8168g(tp); 4805 4806 /* disable aspm and clock request before access ephy */ 4807 rtl_hw_aspm_clkreq_enable(tp, false); 4808 rtl_ephy_init(tp, e_info_8411_2); 4809 4810 /* The following Realtek-provided magic fixes an issue with the RX unit 4811 * getting confused after the PHY having been powered-down. 4812 */ 4813 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 4814 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 4815 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 4816 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 4817 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 4818 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 4819 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 4820 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 4821 mdelay(3); 4822 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 4823 4824 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 4825 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 4826 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 4827 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 4828 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 4829 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 4830 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 4831 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 4832 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 4833 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 4834 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 4835 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 4836 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 4837 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 4838 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 4839 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 4840 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 4841 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 4842 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 4843 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 4844 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 4845 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 4846 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 4847 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 4848 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 4849 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 4850 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 4851 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 4852 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 4853 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 4854 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 4855 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 4856 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 4857 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 4858 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 4859 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 4860 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 4861 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 4862 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 4863 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 4864 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 4865 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 4866 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 4867 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 4868 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 4869 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 4870 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 4871 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 4872 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 4873 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 4874 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 4875 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 4876 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 4877 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 4878 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 4879 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 4880 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 4881 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 4882 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 4883 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 4884 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 4885 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 4886 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 4887 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 4888 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 4889 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 4890 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 4891 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 4892 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 4893 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 4894 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 4895 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 4896 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 4897 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 4898 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 4899 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 4900 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 4901 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 4902 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 4903 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 4904 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 4905 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 4906 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 4907 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 4908 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 4909 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 4910 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 4911 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 4912 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 4913 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 4914 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 4915 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 4916 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 4917 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 4918 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 4919 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 4920 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 4921 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 4922 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 4923 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 4924 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 4925 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 4926 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 4927 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 4928 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 4929 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 4930 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 4931 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 4932 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 4933 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 4934 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 4935 4936 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 4937 4938 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 4939 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 4940 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 4941 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 4942 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 4943 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 4944 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 4945 4946 rtl_hw_aspm_clkreq_enable(tp, true); 4947 } 4948 4949 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 4950 { 4951 static const struct ephy_info e_info_8168h_1[] = { 4952 { 0x1e, 0x0800, 0x0001 }, 4953 { 0x1d, 0x0000, 0x0800 }, 4954 { 0x05, 0xffff, 0x2089 }, 4955 { 0x06, 0xffff, 0x5881 }, 4956 { 0x04, 0xffff, 0x854a }, 4957 { 0x01, 0xffff, 0x068b } 4958 }; 4959 int rg_saw_cnt; 4960 4961 /* disable aspm and clock request before access ephy */ 4962 rtl_hw_aspm_clkreq_enable(tp, false); 4963 rtl_ephy_init(tp, e_info_8168h_1); 4964 4965 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4966 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4967 4968 rtl_set_def_aspm_entry_latency(tp); 4969 4970 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4971 4972 rtl_reset_packet_filter(tp); 4973 4974 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 4975 4976 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 4977 4978 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4979 4980 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4981 4982 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4983 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4984 4985 rtl8168_config_eee_mac(tp); 4986 4987 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4988 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4989 4990 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4991 4992 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4993 4994 rtl_pcie_state_l2l3_disable(tp); 4995 4996 rtl_writephy(tp, 0x1f, 0x0c42); 4997 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff); 4998 rtl_writephy(tp, 0x1f, 0x0000); 4999 if (rg_saw_cnt > 0) { 5000 u16 sw_cnt_1ms_ini; 5001 5002 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 5003 sw_cnt_1ms_ini &= 0x0fff; 5004 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 5005 } 5006 5007 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 5008 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 5009 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 5010 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 5011 5012 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 5013 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 5014 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 5015 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 5016 5017 rtl_hw_aspm_clkreq_enable(tp, true); 5018 } 5019 5020 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 5021 { 5022 rtl8168ep_stop_cmac(tp); 5023 5024 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 5025 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 5026 5027 rtl_set_def_aspm_entry_latency(tp); 5028 5029 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5030 5031 rtl_reset_packet_filter(tp); 5032 5033 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 5034 5035 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 5036 5037 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 5038 5039 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 5040 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 5041 5042 rtl8168_config_eee_mac(tp); 5043 5044 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 5045 5046 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 5047 5048 rtl_pcie_state_l2l3_disable(tp); 5049 } 5050 5051 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 5052 { 5053 static const struct ephy_info e_info_8168ep_1[] = { 5054 { 0x00, 0xffff, 0x10ab }, 5055 { 0x06, 0xffff, 0xf030 }, 5056 { 0x08, 0xffff, 0x2006 }, 5057 { 0x0d, 0xffff, 0x1666 }, 5058 { 0x0c, 0x3ff0, 0x0000 } 5059 }; 5060 5061 /* disable aspm and clock request before access ephy */ 5062 rtl_hw_aspm_clkreq_enable(tp, false); 5063 rtl_ephy_init(tp, e_info_8168ep_1); 5064 5065 rtl_hw_start_8168ep(tp); 5066 5067 rtl_hw_aspm_clkreq_enable(tp, true); 5068 } 5069 5070 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 5071 { 5072 static const struct ephy_info e_info_8168ep_2[] = { 5073 { 0x00, 0xffff, 0x10a3 }, 5074 { 0x19, 0xffff, 0xfc00 }, 5075 { 0x1e, 0xffff, 0x20ea } 5076 }; 5077 5078 /* disable aspm and clock request before access ephy */ 5079 rtl_hw_aspm_clkreq_enable(tp, false); 5080 rtl_ephy_init(tp, e_info_8168ep_2); 5081 5082 rtl_hw_start_8168ep(tp); 5083 5084 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5085 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 5086 5087 rtl_hw_aspm_clkreq_enable(tp, true); 5088 } 5089 5090 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 5091 { 5092 static const struct ephy_info e_info_8168ep_3[] = { 5093 { 0x00, 0x0000, 0x0080 }, 5094 { 0x0d, 0x0100, 0x0200 }, 5095 { 0x19, 0x8021, 0x0000 }, 5096 { 0x1e, 0x0000, 0x2000 }, 5097 }; 5098 5099 /* disable aspm and clock request before access ephy */ 5100 rtl_hw_aspm_clkreq_enable(tp, false); 5101 rtl_ephy_init(tp, e_info_8168ep_3); 5102 5103 rtl_hw_start_8168ep(tp); 5104 5105 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5106 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 5107 5108 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 5109 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5110 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5111 5112 rtl_hw_aspm_clkreq_enable(tp, true); 5113 } 5114 5115 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 5116 { 5117 static const struct ephy_info e_info_8102e_1[] = { 5118 { 0x01, 0, 0x6e65 }, 5119 { 0x02, 0, 0x091f }, 5120 { 0x03, 0, 0xc2f9 }, 5121 { 0x06, 0, 0xafb5 }, 5122 { 0x07, 0, 0x0e00 }, 5123 { 0x19, 0, 0xec80 }, 5124 { 0x01, 0, 0x2e65 }, 5125 { 0x01, 0, 0x6e65 } 5126 }; 5127 u8 cfg1; 5128 5129 rtl_set_def_aspm_entry_latency(tp); 5130 5131 RTL_W8(tp, DBG_REG, FIX_NAK_1); 5132 5133 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5134 5135 RTL_W8(tp, Config1, 5136 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 5137 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5138 5139 cfg1 = RTL_R8(tp, Config1); 5140 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 5141 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 5142 5143 rtl_ephy_init(tp, e_info_8102e_1); 5144 } 5145 5146 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 5147 { 5148 rtl_set_def_aspm_entry_latency(tp); 5149 5150 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5151 5152 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 5153 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5154 } 5155 5156 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 5157 { 5158 rtl_hw_start_8102e_2(tp); 5159 5160 rtl_ephy_write(tp, 0x03, 0xc2f9); 5161 } 5162 5163 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 5164 { 5165 static const struct ephy_info e_info_8105e_1[] = { 5166 { 0x07, 0, 0x4000 }, 5167 { 0x19, 0, 0x0200 }, 5168 { 0x19, 0, 0x0020 }, 5169 { 0x1e, 0, 0x2000 }, 5170 { 0x03, 0, 0x0001 }, 5171 { 0x19, 0, 0x0100 }, 5172 { 0x19, 0, 0x0004 }, 5173 { 0x0a, 0, 0x0020 } 5174 }; 5175 5176 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5177 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5178 5179 /* Disable Early Tally Counter */ 5180 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 5181 5182 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5183 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 5184 5185 rtl_ephy_init(tp, e_info_8105e_1); 5186 5187 rtl_pcie_state_l2l3_disable(tp); 5188 } 5189 5190 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 5191 { 5192 rtl_hw_start_8105e_1(tp); 5193 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 5194 } 5195 5196 static void rtl_hw_start_8402(struct rtl8169_private *tp) 5197 { 5198 static const struct ephy_info e_info_8402[] = { 5199 { 0x19, 0xffff, 0xff64 }, 5200 { 0x1e, 0, 0x4000 } 5201 }; 5202 5203 rtl_set_def_aspm_entry_latency(tp); 5204 5205 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5206 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5207 5208 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5209 5210 rtl_ephy_init(tp, e_info_8402); 5211 5212 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5213 5214 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 5215 rtl_reset_packet_filter(tp); 5216 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 5217 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 5218 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 5219 5220 rtl_pcie_state_l2l3_disable(tp); 5221 } 5222 5223 static void rtl_hw_start_8106(struct rtl8169_private *tp) 5224 { 5225 rtl_hw_aspm_clkreq_enable(tp, false); 5226 5227 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5228 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5229 5230 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 5231 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5232 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5233 5234 rtl_pcie_state_l2l3_disable(tp); 5235 rtl_hw_aspm_clkreq_enable(tp, true); 5236 } 5237 5238 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 5239 { 5240 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 5241 } 5242 5243 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 5244 { 5245 rtl_pcie_state_l2l3_disable(tp); 5246 5247 RTL_W16(tp, 0x382, 0x221b); 5248 RTL_W8(tp, 0x4500, 0); 5249 RTL_W16(tp, 0x4800, 0); 5250 5251 /* disable UPS */ 5252 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 5253 5254 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 5255 5256 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 5257 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 5258 5259 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 5260 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5261 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5262 5263 /* disable new tx descriptor format */ 5264 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 5265 5266 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 5267 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 5268 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 5269 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 5270 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 5271 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 5272 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 5273 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 5274 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 5275 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 5276 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 5277 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 5278 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 5279 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 5280 udelay(1); 5281 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 5282 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 5283 5284 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 5285 5286 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 5287 5288 rtl8125_config_eee_mac(tp); 5289 5290 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 5291 udelay(10); 5292 } 5293 5294 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 5295 { 5296 static const struct ephy_info e_info_8125_1[] = { 5297 { 0x01, 0xffff, 0xa812 }, 5298 { 0x09, 0xffff, 0x520c }, 5299 { 0x04, 0xffff, 0xd000 }, 5300 { 0x0d, 0xffff, 0xf702 }, 5301 { 0x0a, 0xffff, 0x8653 }, 5302 { 0x06, 0xffff, 0x001e }, 5303 { 0x08, 0xffff, 0x3595 }, 5304 { 0x20, 0xffff, 0x9455 }, 5305 { 0x21, 0xffff, 0x99ff }, 5306 { 0x02, 0xffff, 0x6046 }, 5307 { 0x29, 0xffff, 0xfe00 }, 5308 { 0x23, 0xffff, 0xab62 }, 5309 5310 { 0x41, 0xffff, 0xa80c }, 5311 { 0x49, 0xffff, 0x520c }, 5312 { 0x44, 0xffff, 0xd000 }, 5313 { 0x4d, 0xffff, 0xf702 }, 5314 { 0x4a, 0xffff, 0x8653 }, 5315 { 0x46, 0xffff, 0x001e }, 5316 { 0x48, 0xffff, 0x3595 }, 5317 { 0x60, 0xffff, 0x9455 }, 5318 { 0x61, 0xffff, 0x99ff }, 5319 { 0x42, 0xffff, 0x6046 }, 5320 { 0x69, 0xffff, 0xfe00 }, 5321 { 0x63, 0xffff, 0xab62 }, 5322 }; 5323 5324 rtl_set_def_aspm_entry_latency(tp); 5325 5326 /* disable aspm and clock request before access ephy */ 5327 rtl_hw_aspm_clkreq_enable(tp, false); 5328 rtl_ephy_init(tp, e_info_8125_1); 5329 5330 rtl_hw_start_8125_common(tp); 5331 } 5332 5333 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 5334 { 5335 static const struct ephy_info e_info_8125_2[] = { 5336 { 0x04, 0xffff, 0xd000 }, 5337 { 0x0a, 0xffff, 0x8653 }, 5338 { 0x23, 0xffff, 0xab66 }, 5339 { 0x20, 0xffff, 0x9455 }, 5340 { 0x21, 0xffff, 0x99ff }, 5341 { 0x29, 0xffff, 0xfe04 }, 5342 5343 { 0x44, 0xffff, 0xd000 }, 5344 { 0x4a, 0xffff, 0x8653 }, 5345 { 0x63, 0xffff, 0xab66 }, 5346 { 0x60, 0xffff, 0x9455 }, 5347 { 0x61, 0xffff, 0x99ff }, 5348 { 0x69, 0xffff, 0xfe04 }, 5349 }; 5350 5351 rtl_set_def_aspm_entry_latency(tp); 5352 5353 /* disable aspm and clock request before access ephy */ 5354 rtl_hw_aspm_clkreq_enable(tp, false); 5355 rtl_ephy_init(tp, e_info_8125_2); 5356 5357 rtl_hw_start_8125_common(tp); 5358 } 5359 5360 static void rtl_hw_config(struct rtl8169_private *tp) 5361 { 5362 static const rtl_generic_fct hw_configs[] = { 5363 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 5364 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 5365 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 5366 [RTL_GIGA_MAC_VER_10] = NULL, 5367 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb, 5368 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef, 5369 [RTL_GIGA_MAC_VER_13] = NULL, 5370 [RTL_GIGA_MAC_VER_14] = NULL, 5371 [RTL_GIGA_MAC_VER_15] = NULL, 5372 [RTL_GIGA_MAC_VER_16] = NULL, 5373 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef, 5374 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 5375 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 5376 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 5377 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 5378 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 5379 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 5380 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 5381 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 5382 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 5383 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 5384 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 5385 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 5386 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 5387 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp, 5388 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 5389 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 5390 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 5391 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 5392 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 5393 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 5394 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 5395 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 5396 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 5397 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 5398 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 5399 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 5400 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 5401 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 5402 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 5403 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 5404 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 5405 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 5406 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 5407 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 5408 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 5409 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 5410 }; 5411 5412 if (hw_configs[tp->mac_version]) 5413 hw_configs[tp->mac_version](tp); 5414 } 5415 5416 static void rtl_hw_start_8125(struct rtl8169_private *tp) 5417 { 5418 int i; 5419 5420 /* disable interrupt coalescing */ 5421 for (i = 0xa00; i < 0xb00; i += 4) 5422 RTL_W32(tp, i, 0); 5423 5424 rtl_hw_config(tp); 5425 } 5426 5427 static void rtl_hw_start_8168(struct rtl8169_private *tp) 5428 { 5429 if (tp->mac_version == RTL_GIGA_MAC_VER_13 || 5430 tp->mac_version == RTL_GIGA_MAC_VER_16) 5431 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, 5432 PCI_EXP_DEVCTL_NOSNOOP_EN); 5433 5434 if (rtl_is_8168evl_up(tp)) 5435 RTL_W8(tp, MaxTxPacketSize, EarlySize); 5436 else 5437 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5438 5439 rtl_hw_config(tp); 5440 5441 /* disable interrupt coalescing */ 5442 RTL_W16(tp, IntrMitigate, 0x0000); 5443 } 5444 5445 static void rtl_hw_start_8169(struct rtl8169_private *tp) 5446 { 5447 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5448 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 5449 5450 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 5451 5452 tp->cp_cmd |= PCIMulRW; 5453 5454 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 5455 tp->mac_version == RTL_GIGA_MAC_VER_03) { 5456 netif_dbg(tp, drv, tp->dev, 5457 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n"); 5458 tp->cp_cmd |= (1 << 14); 5459 } 5460 5461 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5462 5463 rtl8169_set_magic_reg(tp, tp->mac_version); 5464 5465 RTL_W32(tp, RxMissed, 0); 5466 5467 /* disable interrupt coalescing */ 5468 RTL_W16(tp, IntrMitigate, 0x0000); 5469 } 5470 5471 static void rtl_hw_start(struct rtl8169_private *tp) 5472 { 5473 rtl_unlock_config_regs(tp); 5474 5475 tp->cp_cmd &= CPCMD_MASK; 5476 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5477 5478 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5479 rtl_hw_start_8169(tp); 5480 else if (rtl_is_8125(tp)) 5481 rtl_hw_start_8125(tp); 5482 else 5483 rtl_hw_start_8168(tp); 5484 5485 rtl_set_rx_max_size(tp); 5486 rtl_set_rx_tx_desc_registers(tp); 5487 rtl_lock_config_regs(tp); 5488 5489 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 5490 RTL_R16(tp, CPlusCmd); 5491 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 5492 rtl_init_rxcfg(tp); 5493 rtl_set_tx_config_registers(tp); 5494 rtl_set_rx_mode(tp->dev); 5495 rtl_irq_enable(tp); 5496 } 5497 5498 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 5499 { 5500 struct rtl8169_private *tp = netdev_priv(dev); 5501 5502 if (new_mtu > ETH_DATA_LEN) 5503 rtl_hw_jumbo_enable(tp); 5504 else 5505 rtl_hw_jumbo_disable(tp); 5506 5507 dev->mtu = new_mtu; 5508 netdev_update_features(dev); 5509 5510 return 0; 5511 } 5512 5513 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 5514 { 5515 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); 5516 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 5517 } 5518 5519 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 5520 { 5521 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 5522 5523 /* Force memory writes to complete before releasing descriptor */ 5524 dma_wmb(); 5525 5526 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 5527 } 5528 5529 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 5530 struct RxDesc *desc) 5531 { 5532 struct device *d = tp_to_dev(tp); 5533 int node = dev_to_node(d); 5534 dma_addr_t mapping; 5535 struct page *data; 5536 5537 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 5538 if (!data) 5539 return NULL; 5540 5541 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5542 if (unlikely(dma_mapping_error(d, mapping))) { 5543 if (net_ratelimit()) 5544 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 5545 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 5546 return NULL; 5547 } 5548 5549 desc->addr = cpu_to_le64(mapping); 5550 rtl8169_mark_to_asic(desc); 5551 5552 return data; 5553 } 5554 5555 static void rtl8169_rx_clear(struct rtl8169_private *tp) 5556 { 5557 unsigned int i; 5558 5559 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 5560 dma_unmap_page(tp_to_dev(tp), 5561 le64_to_cpu(tp->RxDescArray[i].addr), 5562 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5563 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 5564 tp->Rx_databuff[i] = NULL; 5565 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5566 } 5567 } 5568 5569 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 5570 { 5571 desc->opts1 |= cpu_to_le32(RingEnd); 5572 } 5573 5574 static int rtl8169_rx_fill(struct rtl8169_private *tp) 5575 { 5576 unsigned int i; 5577 5578 for (i = 0; i < NUM_RX_DESC; i++) { 5579 struct page *data; 5580 5581 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 5582 if (!data) { 5583 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5584 goto err_out; 5585 } 5586 tp->Rx_databuff[i] = data; 5587 } 5588 5589 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 5590 return 0; 5591 5592 err_out: 5593 rtl8169_rx_clear(tp); 5594 return -ENOMEM; 5595 } 5596 5597 static int rtl8169_init_ring(struct rtl8169_private *tp) 5598 { 5599 rtl8169_init_ring_indexes(tp); 5600 5601 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 5602 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 5603 5604 return rtl8169_rx_fill(tp); 5605 } 5606 5607 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, 5608 struct TxDesc *desc) 5609 { 5610 unsigned int len = tx_skb->len; 5611 5612 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); 5613 5614 desc->opts1 = 0x00; 5615 desc->opts2 = 0x00; 5616 desc->addr = 0x00; 5617 tx_skb->len = 0; 5618 } 5619 5620 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 5621 unsigned int n) 5622 { 5623 unsigned int i; 5624 5625 for (i = 0; i < n; i++) { 5626 unsigned int entry = (start + i) % NUM_TX_DESC; 5627 struct ring_info *tx_skb = tp->tx_skb + entry; 5628 unsigned int len = tx_skb->len; 5629 5630 if (len) { 5631 struct sk_buff *skb = tx_skb->skb; 5632 5633 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5634 tp->TxDescArray + entry); 5635 if (skb) { 5636 dev_consume_skb_any(skb); 5637 tx_skb->skb = NULL; 5638 } 5639 } 5640 } 5641 } 5642 5643 static void rtl8169_tx_clear(struct rtl8169_private *tp) 5644 { 5645 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 5646 tp->cur_tx = tp->dirty_tx = 0; 5647 netdev_reset_queue(tp->dev); 5648 } 5649 5650 static void rtl_reset_work(struct rtl8169_private *tp) 5651 { 5652 struct net_device *dev = tp->dev; 5653 int i; 5654 5655 napi_disable(&tp->napi); 5656 netif_stop_queue(dev); 5657 synchronize_rcu(); 5658 5659 rtl8169_hw_reset(tp); 5660 5661 for (i = 0; i < NUM_RX_DESC; i++) 5662 rtl8169_mark_to_asic(tp->RxDescArray + i); 5663 5664 rtl8169_tx_clear(tp); 5665 rtl8169_init_ring_indexes(tp); 5666 5667 napi_enable(&tp->napi); 5668 rtl_hw_start(tp); 5669 netif_wake_queue(dev); 5670 } 5671 5672 static void rtl8169_tx_timeout(struct net_device *dev) 5673 { 5674 struct rtl8169_private *tp = netdev_priv(dev); 5675 5676 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5677 } 5678 5679 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry) 5680 { 5681 u32 status = opts0 | len; 5682 5683 if (entry == NUM_TX_DESC - 1) 5684 status |= RingEnd; 5685 5686 return cpu_to_le32(status); 5687 } 5688 5689 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 5690 u32 *opts) 5691 { 5692 struct skb_shared_info *info = skb_shinfo(skb); 5693 unsigned int cur_frag, entry; 5694 struct TxDesc *uninitialized_var(txd); 5695 struct device *d = tp_to_dev(tp); 5696 5697 entry = tp->cur_tx; 5698 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 5699 const skb_frag_t *frag = info->frags + cur_frag; 5700 dma_addr_t mapping; 5701 u32 len; 5702 void *addr; 5703 5704 entry = (entry + 1) % NUM_TX_DESC; 5705 5706 txd = tp->TxDescArray + entry; 5707 len = skb_frag_size(frag); 5708 addr = skb_frag_address(frag); 5709 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 5710 if (unlikely(dma_mapping_error(d, mapping))) { 5711 if (net_ratelimit()) 5712 netif_err(tp, drv, tp->dev, 5713 "Failed to map TX fragments DMA!\n"); 5714 goto err_out; 5715 } 5716 5717 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5718 txd->opts2 = cpu_to_le32(opts[1]); 5719 txd->addr = cpu_to_le64(mapping); 5720 5721 tp->tx_skb[entry].len = len; 5722 } 5723 5724 if (cur_frag) { 5725 tp->tx_skb[entry].skb = skb; 5726 txd->opts1 |= cpu_to_le32(LastFrag); 5727 } 5728 5729 return cur_frag; 5730 5731 err_out: 5732 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 5733 return -EIO; 5734 } 5735 5736 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 5737 { 5738 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 5739 } 5740 5741 /* msdn_giant_send_check() 5742 * According to the document of microsoft, the TCP Pseudo Header excludes the 5743 * packet length for IPv6 TCP large packets. 5744 */ 5745 static int msdn_giant_send_check(struct sk_buff *skb) 5746 { 5747 const struct ipv6hdr *ipv6h; 5748 struct tcphdr *th; 5749 int ret; 5750 5751 ret = skb_cow_head(skb, 0); 5752 if (ret) 5753 return ret; 5754 5755 ipv6h = ipv6_hdr(skb); 5756 th = tcp_hdr(skb); 5757 5758 th->check = 0; 5759 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 5760 5761 return ret; 5762 } 5763 5764 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 5765 { 5766 u32 mss = skb_shinfo(skb)->gso_size; 5767 5768 if (mss) { 5769 opts[0] |= TD_LSO; 5770 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; 5771 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5772 const struct iphdr *ip = ip_hdr(skb); 5773 5774 if (ip->protocol == IPPROTO_TCP) 5775 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 5776 else if (ip->protocol == IPPROTO_UDP) 5777 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 5778 else 5779 WARN_ON_ONCE(1); 5780 } 5781 } 5782 5783 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 5784 struct sk_buff *skb, u32 *opts) 5785 { 5786 u32 transport_offset = (u32)skb_transport_offset(skb); 5787 u32 mss = skb_shinfo(skb)->gso_size; 5788 5789 if (mss) { 5790 switch (vlan_get_protocol(skb)) { 5791 case htons(ETH_P_IP): 5792 opts[0] |= TD1_GTSENV4; 5793 break; 5794 5795 case htons(ETH_P_IPV6): 5796 if (msdn_giant_send_check(skb)) 5797 return false; 5798 5799 opts[0] |= TD1_GTSENV6; 5800 break; 5801 5802 default: 5803 WARN_ON_ONCE(1); 5804 break; 5805 } 5806 5807 opts[0] |= transport_offset << GTTCPHO_SHIFT; 5808 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; 5809 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5810 u8 ip_protocol; 5811 5812 switch (vlan_get_protocol(skb)) { 5813 case htons(ETH_P_IP): 5814 opts[1] |= TD1_IPv4_CS; 5815 ip_protocol = ip_hdr(skb)->protocol; 5816 break; 5817 5818 case htons(ETH_P_IPV6): 5819 opts[1] |= TD1_IPv6_CS; 5820 ip_protocol = ipv6_hdr(skb)->nexthdr; 5821 break; 5822 5823 default: 5824 ip_protocol = IPPROTO_RAW; 5825 break; 5826 } 5827 5828 if (ip_protocol == IPPROTO_TCP) 5829 opts[1] |= TD1_TCP_CS; 5830 else if (ip_protocol == IPPROTO_UDP) 5831 opts[1] |= TD1_UDP_CS; 5832 else 5833 WARN_ON_ONCE(1); 5834 5835 opts[1] |= transport_offset << TCPHO_SHIFT; 5836 } else { 5837 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 5838 return !eth_skb_pad(skb); 5839 } 5840 5841 return true; 5842 } 5843 5844 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 5845 unsigned int nr_frags) 5846 { 5847 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 5848 5849 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 5850 return slots_avail > nr_frags; 5851 } 5852 5853 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 5854 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 5855 { 5856 switch (tp->mac_version) { 5857 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5858 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 5859 return false; 5860 default: 5861 return true; 5862 } 5863 } 5864 5865 static void rtl8169_doorbell(struct rtl8169_private *tp) 5866 { 5867 if (rtl_is_8125(tp)) 5868 RTL_W16(tp, TxPoll_8125, BIT(0)); 5869 else 5870 RTL_W8(tp, TxPoll, NPQ); 5871 } 5872 5873 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 5874 struct net_device *dev) 5875 { 5876 struct rtl8169_private *tp = netdev_priv(dev); 5877 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 5878 struct TxDesc *txd = tp->TxDescArray + entry; 5879 struct device *d = tp_to_dev(tp); 5880 dma_addr_t mapping; 5881 u32 opts[2], len; 5882 bool stop_queue; 5883 bool door_bell; 5884 int frags; 5885 5886 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) { 5887 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 5888 goto err_stop_0; 5889 } 5890 5891 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 5892 goto err_stop_0; 5893 5894 opts[1] = rtl8169_tx_vlan_tag(skb); 5895 opts[0] = DescOwn; 5896 5897 if (rtl_chip_supports_csum_v2(tp)) { 5898 if (!rtl8169_tso_csum_v2(tp, skb, opts)) 5899 goto err_dma_0; 5900 } else { 5901 rtl8169_tso_csum_v1(skb, opts); 5902 } 5903 5904 len = skb_headlen(skb); 5905 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); 5906 if (unlikely(dma_mapping_error(d, mapping))) { 5907 if (net_ratelimit()) 5908 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); 5909 goto err_dma_0; 5910 } 5911 5912 tp->tx_skb[entry].len = len; 5913 txd->addr = cpu_to_le64(mapping); 5914 5915 frags = rtl8169_xmit_frags(tp, skb, opts); 5916 if (frags < 0) 5917 goto err_dma_1; 5918 else if (frags) 5919 opts[0] |= FirstFrag; 5920 else { 5921 opts[0] |= FirstFrag | LastFrag; 5922 tp->tx_skb[entry].skb = skb; 5923 } 5924 5925 txd->opts2 = cpu_to_le32(opts[1]); 5926 5927 skb_tx_timestamp(skb); 5928 5929 /* Force memory writes to complete before releasing descriptor */ 5930 dma_wmb(); 5931 5932 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 5933 5934 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5935 5936 /* Force all memory writes to complete before notifying device */ 5937 wmb(); 5938 5939 tp->cur_tx += frags + 1; 5940 5941 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 5942 if (unlikely(stop_queue)) { 5943 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 5944 * not miss a ring update when it notices a stopped queue. 5945 */ 5946 smp_wmb(); 5947 netif_stop_queue(dev); 5948 door_bell = true; 5949 } 5950 5951 if (door_bell) 5952 rtl8169_doorbell(tp); 5953 5954 if (unlikely(stop_queue)) { 5955 /* Sync with rtl_tx: 5956 * - publish queue status and cur_tx ring index (write barrier) 5957 * - refresh dirty_tx ring index (read barrier). 5958 * May the current thread have a pessimistic view of the ring 5959 * status and forget to wake up queue, a racing rtl_tx thread 5960 * can't. 5961 */ 5962 smp_mb(); 5963 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 5964 netif_start_queue(dev); 5965 } 5966 5967 return NETDEV_TX_OK; 5968 5969 err_dma_1: 5970 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); 5971 err_dma_0: 5972 dev_kfree_skb_any(skb); 5973 dev->stats.tx_dropped++; 5974 return NETDEV_TX_OK; 5975 5976 err_stop_0: 5977 netif_stop_queue(dev); 5978 dev->stats.tx_dropped++; 5979 return NETDEV_TX_BUSY; 5980 } 5981 5982 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 5983 struct net_device *dev, 5984 netdev_features_t features) 5985 { 5986 int transport_offset = skb_transport_offset(skb); 5987 struct rtl8169_private *tp = netdev_priv(dev); 5988 5989 if (skb_is_gso(skb)) { 5990 if (transport_offset > GTTCPHO_MAX && 5991 rtl_chip_supports_csum_v2(tp)) 5992 features &= ~NETIF_F_ALL_TSO; 5993 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5994 if (skb->len < ETH_ZLEN) { 5995 switch (tp->mac_version) { 5996 case RTL_GIGA_MAC_VER_11: 5997 case RTL_GIGA_MAC_VER_12: 5998 case RTL_GIGA_MAC_VER_17: 5999 case RTL_GIGA_MAC_VER_34: 6000 features &= ~NETIF_F_CSUM_MASK; 6001 break; 6002 default: 6003 break; 6004 } 6005 } 6006 6007 if (transport_offset > TCPHO_MAX && 6008 rtl_chip_supports_csum_v2(tp)) 6009 features &= ~NETIF_F_CSUM_MASK; 6010 } 6011 6012 return vlan_features_check(skb, features); 6013 } 6014 6015 static void rtl8169_pcierr_interrupt(struct net_device *dev) 6016 { 6017 struct rtl8169_private *tp = netdev_priv(dev); 6018 struct pci_dev *pdev = tp->pci_dev; 6019 u16 pci_status, pci_cmd; 6020 6021 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 6022 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 6023 6024 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", 6025 pci_cmd, pci_status); 6026 6027 /* 6028 * The recovery sequence below admits a very elaborated explanation: 6029 * - it seems to work; 6030 * - I did not see what else could be done; 6031 * - it makes iop3xx happy. 6032 * 6033 * Feel free to adjust to your needs. 6034 */ 6035 if (pdev->broken_parity_status) 6036 pci_cmd &= ~PCI_COMMAND_PARITY; 6037 else 6038 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 6039 6040 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 6041 6042 pci_write_config_word(pdev, PCI_STATUS, 6043 pci_status & (PCI_STATUS_DETECTED_PARITY | 6044 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | 6045 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); 6046 6047 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 6048 } 6049 6050 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 6051 int budget) 6052 { 6053 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 6054 6055 dirty_tx = tp->dirty_tx; 6056 smp_rmb(); 6057 tx_left = tp->cur_tx - dirty_tx; 6058 6059 while (tx_left > 0) { 6060 unsigned int entry = dirty_tx % NUM_TX_DESC; 6061 struct ring_info *tx_skb = tp->tx_skb + entry; 6062 u32 status; 6063 6064 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 6065 if (status & DescOwn) 6066 break; 6067 6068 /* This barrier is needed to keep us from reading 6069 * any other fields out of the Tx descriptor until 6070 * we know the status of DescOwn 6071 */ 6072 dma_rmb(); 6073 6074 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 6075 tp->TxDescArray + entry); 6076 if (tx_skb->skb) { 6077 pkts_compl++; 6078 bytes_compl += tx_skb->skb->len; 6079 napi_consume_skb(tx_skb->skb, budget); 6080 tx_skb->skb = NULL; 6081 } 6082 dirty_tx++; 6083 tx_left--; 6084 } 6085 6086 if (tp->dirty_tx != dirty_tx) { 6087 netdev_completed_queue(dev, pkts_compl, bytes_compl); 6088 6089 u64_stats_update_begin(&tp->tx_stats.syncp); 6090 tp->tx_stats.packets += pkts_compl; 6091 tp->tx_stats.bytes += bytes_compl; 6092 u64_stats_update_end(&tp->tx_stats.syncp); 6093 6094 tp->dirty_tx = dirty_tx; 6095 /* Sync with rtl8169_start_xmit: 6096 * - publish dirty_tx ring index (write barrier) 6097 * - refresh cur_tx ring index and queue status (read barrier) 6098 * May the current thread miss the stopped queue condition, 6099 * a racing xmit thread can only have a right view of the 6100 * ring status. 6101 */ 6102 smp_mb(); 6103 if (netif_queue_stopped(dev) && 6104 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 6105 netif_wake_queue(dev); 6106 } 6107 /* 6108 * 8168 hack: TxPoll requests are lost when the Tx packets are 6109 * too close. Let's kick an extra TxPoll request when a burst 6110 * of start_xmit activity is detected (if it is not detected, 6111 * it is slow enough). -- FR 6112 */ 6113 if (tp->cur_tx != dirty_tx) 6114 rtl8169_doorbell(tp); 6115 } 6116 } 6117 6118 static inline int rtl8169_fragmented_frame(u32 status) 6119 { 6120 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 6121 } 6122 6123 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 6124 { 6125 u32 status = opts1 & RxProtoMask; 6126 6127 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 6128 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 6129 skb->ip_summed = CHECKSUM_UNNECESSARY; 6130 else 6131 skb_checksum_none_assert(skb); 6132 } 6133 6134 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 6135 { 6136 unsigned int cur_rx, rx_left; 6137 unsigned int count; 6138 6139 cur_rx = tp->cur_rx; 6140 6141 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 6142 unsigned int entry = cur_rx % NUM_RX_DESC; 6143 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 6144 struct RxDesc *desc = tp->RxDescArray + entry; 6145 u32 status; 6146 6147 status = le32_to_cpu(desc->opts1); 6148 if (status & DescOwn) 6149 break; 6150 6151 /* This barrier is needed to keep us from reading 6152 * any other fields out of the Rx descriptor until 6153 * we know the status of DescOwn 6154 */ 6155 dma_rmb(); 6156 6157 if (unlikely(status & RxRES)) { 6158 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 6159 status); 6160 dev->stats.rx_errors++; 6161 if (status & (RxRWT | RxRUNT)) 6162 dev->stats.rx_length_errors++; 6163 if (status & RxCRC) 6164 dev->stats.rx_crc_errors++; 6165 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 6166 dev->features & NETIF_F_RXALL) { 6167 goto process_pkt; 6168 } 6169 } else { 6170 unsigned int pkt_size; 6171 struct sk_buff *skb; 6172 6173 process_pkt: 6174 pkt_size = status & GENMASK(13, 0); 6175 if (likely(!(dev->features & NETIF_F_RXFCS))) 6176 pkt_size -= ETH_FCS_LEN; 6177 /* 6178 * The driver does not support incoming fragmented 6179 * frames. They are seen as a symptom of over-mtu 6180 * sized frames. 6181 */ 6182 if (unlikely(rtl8169_fragmented_frame(status))) { 6183 dev->stats.rx_dropped++; 6184 dev->stats.rx_length_errors++; 6185 goto release_descriptor; 6186 } 6187 6188 skb = napi_alloc_skb(&tp->napi, pkt_size); 6189 if (unlikely(!skb)) { 6190 dev->stats.rx_dropped++; 6191 goto release_descriptor; 6192 } 6193 6194 dma_sync_single_for_cpu(tp_to_dev(tp), 6195 le64_to_cpu(desc->addr), 6196 pkt_size, DMA_FROM_DEVICE); 6197 prefetch(rx_buf); 6198 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 6199 skb->tail += pkt_size; 6200 skb->len = pkt_size; 6201 6202 dma_sync_single_for_device(tp_to_dev(tp), 6203 le64_to_cpu(desc->addr), 6204 pkt_size, DMA_FROM_DEVICE); 6205 6206 rtl8169_rx_csum(skb, status); 6207 skb->protocol = eth_type_trans(skb, dev); 6208 6209 rtl8169_rx_vlan_tag(desc, skb); 6210 6211 if (skb->pkt_type == PACKET_MULTICAST) 6212 dev->stats.multicast++; 6213 6214 napi_gro_receive(&tp->napi, skb); 6215 6216 u64_stats_update_begin(&tp->rx_stats.syncp); 6217 tp->rx_stats.packets++; 6218 tp->rx_stats.bytes += pkt_size; 6219 u64_stats_update_end(&tp->rx_stats.syncp); 6220 } 6221 release_descriptor: 6222 desc->opts2 = 0; 6223 rtl8169_mark_to_asic(desc); 6224 } 6225 6226 count = cur_rx - tp->cur_rx; 6227 tp->cur_rx = cur_rx; 6228 6229 return count; 6230 } 6231 6232 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 6233 { 6234 struct rtl8169_private *tp = dev_instance; 6235 u32 status = rtl_get_events(tp); 6236 6237 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 6238 !(status & tp->irq_mask)) 6239 return IRQ_NONE; 6240 6241 if (unlikely(status & SYSErr)) { 6242 rtl8169_pcierr_interrupt(tp->dev); 6243 goto out; 6244 } 6245 6246 if (status & LinkChg) 6247 phy_mac_interrupt(tp->phydev); 6248 6249 if (unlikely(status & RxFIFOOver && 6250 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 6251 netif_stop_queue(tp->dev); 6252 /* XXX - Hack alert. See rtl_task(). */ 6253 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); 6254 } 6255 6256 rtl_irq_disable(tp); 6257 napi_schedule_irqoff(&tp->napi); 6258 out: 6259 rtl_ack_events(tp, status); 6260 6261 return IRQ_HANDLED; 6262 } 6263 6264 static void rtl_task(struct work_struct *work) 6265 { 6266 static const struct { 6267 int bitnr; 6268 void (*action)(struct rtl8169_private *); 6269 } rtl_work[] = { 6270 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, 6271 }; 6272 struct rtl8169_private *tp = 6273 container_of(work, struct rtl8169_private, wk.work); 6274 struct net_device *dev = tp->dev; 6275 int i; 6276 6277 rtl_lock_work(tp); 6278 6279 if (!netif_running(dev) || 6280 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 6281 goto out_unlock; 6282 6283 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { 6284 bool pending; 6285 6286 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); 6287 if (pending) 6288 rtl_work[i].action(tp); 6289 } 6290 6291 out_unlock: 6292 rtl_unlock_work(tp); 6293 } 6294 6295 static int rtl8169_poll(struct napi_struct *napi, int budget) 6296 { 6297 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 6298 struct net_device *dev = tp->dev; 6299 int work_done; 6300 6301 work_done = rtl_rx(dev, tp, (u32) budget); 6302 6303 rtl_tx(dev, tp, budget); 6304 6305 if (work_done < budget) { 6306 napi_complete_done(napi, work_done); 6307 rtl_irq_enable(tp); 6308 } 6309 6310 return work_done; 6311 } 6312 6313 static void rtl8169_rx_missed(struct net_device *dev) 6314 { 6315 struct rtl8169_private *tp = netdev_priv(dev); 6316 6317 if (tp->mac_version > RTL_GIGA_MAC_VER_06) 6318 return; 6319 6320 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff; 6321 RTL_W32(tp, RxMissed, 0); 6322 } 6323 6324 static void r8169_phylink_handler(struct net_device *ndev) 6325 { 6326 struct rtl8169_private *tp = netdev_priv(ndev); 6327 6328 if (netif_carrier_ok(ndev)) { 6329 rtl_link_chg_patch(tp); 6330 pm_request_resume(&tp->pci_dev->dev); 6331 } else { 6332 pm_runtime_idle(&tp->pci_dev->dev); 6333 } 6334 6335 if (net_ratelimit()) 6336 phy_print_status(tp->phydev); 6337 } 6338 6339 static int r8169_phy_connect(struct rtl8169_private *tp) 6340 { 6341 struct phy_device *phydev = tp->phydev; 6342 phy_interface_t phy_mode; 6343 int ret; 6344 6345 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 6346 PHY_INTERFACE_MODE_MII; 6347 6348 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 6349 phy_mode); 6350 if (ret) 6351 return ret; 6352 6353 if (!tp->supports_gmii) 6354 phy_set_max_speed(phydev, SPEED_100); 6355 6356 phy_support_asym_pause(phydev); 6357 6358 phy_attached_info(phydev); 6359 6360 return 0; 6361 } 6362 6363 static void rtl8169_down(struct net_device *dev) 6364 { 6365 struct rtl8169_private *tp = netdev_priv(dev); 6366 6367 phy_stop(tp->phydev); 6368 6369 napi_disable(&tp->napi); 6370 netif_stop_queue(dev); 6371 6372 rtl8169_hw_reset(tp); 6373 /* 6374 * At this point device interrupts can not be enabled in any function, 6375 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) 6376 * and napi is disabled (rtl8169_poll). 6377 */ 6378 rtl8169_rx_missed(dev); 6379 6380 /* Give a racing hard_start_xmit a few cycles to complete. */ 6381 synchronize_rcu(); 6382 6383 rtl8169_tx_clear(tp); 6384 6385 rtl8169_rx_clear(tp); 6386 6387 rtl_pll_power_down(tp); 6388 } 6389 6390 static int rtl8169_close(struct net_device *dev) 6391 { 6392 struct rtl8169_private *tp = netdev_priv(dev); 6393 struct pci_dev *pdev = tp->pci_dev; 6394 6395 pm_runtime_get_sync(&pdev->dev); 6396 6397 /* Update counters before going down */ 6398 rtl8169_update_counters(tp); 6399 6400 rtl_lock_work(tp); 6401 /* Clear all task flags */ 6402 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6403 6404 rtl8169_down(dev); 6405 rtl_unlock_work(tp); 6406 6407 cancel_work_sync(&tp->wk.work); 6408 6409 phy_disconnect(tp->phydev); 6410 6411 pci_free_irq(pdev, 0, tp); 6412 6413 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6414 tp->RxPhyAddr); 6415 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6416 tp->TxPhyAddr); 6417 tp->TxDescArray = NULL; 6418 tp->RxDescArray = NULL; 6419 6420 pm_runtime_put_sync(&pdev->dev); 6421 6422 return 0; 6423 } 6424 6425 #ifdef CONFIG_NET_POLL_CONTROLLER 6426 static void rtl8169_netpoll(struct net_device *dev) 6427 { 6428 struct rtl8169_private *tp = netdev_priv(dev); 6429 6430 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 6431 } 6432 #endif 6433 6434 static int rtl_open(struct net_device *dev) 6435 { 6436 struct rtl8169_private *tp = netdev_priv(dev); 6437 struct pci_dev *pdev = tp->pci_dev; 6438 int retval = -ENOMEM; 6439 6440 pm_runtime_get_sync(&pdev->dev); 6441 6442 /* 6443 * Rx and Tx descriptors needs 256 bytes alignment. 6444 * dma_alloc_coherent provides more. 6445 */ 6446 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 6447 &tp->TxPhyAddr, GFP_KERNEL); 6448 if (!tp->TxDescArray) 6449 goto err_pm_runtime_put; 6450 6451 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 6452 &tp->RxPhyAddr, GFP_KERNEL); 6453 if (!tp->RxDescArray) 6454 goto err_free_tx_0; 6455 6456 retval = rtl8169_init_ring(tp); 6457 if (retval < 0) 6458 goto err_free_rx_1; 6459 6460 rtl_request_firmware(tp); 6461 6462 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 6463 dev->name); 6464 if (retval < 0) 6465 goto err_release_fw_2; 6466 6467 retval = r8169_phy_connect(tp); 6468 if (retval) 6469 goto err_free_irq; 6470 6471 rtl_lock_work(tp); 6472 6473 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6474 6475 napi_enable(&tp->napi); 6476 6477 rtl8169_init_phy(dev, tp); 6478 6479 rtl_pll_power_up(tp); 6480 6481 rtl_hw_start(tp); 6482 6483 if (!rtl8169_init_counter_offsets(tp)) 6484 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 6485 6486 phy_start(tp->phydev); 6487 netif_start_queue(dev); 6488 6489 rtl_unlock_work(tp); 6490 6491 pm_runtime_put_sync(&pdev->dev); 6492 out: 6493 return retval; 6494 6495 err_free_irq: 6496 pci_free_irq(pdev, 0, tp); 6497 err_release_fw_2: 6498 rtl_release_firmware(tp); 6499 rtl8169_rx_clear(tp); 6500 err_free_rx_1: 6501 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6502 tp->RxPhyAddr); 6503 tp->RxDescArray = NULL; 6504 err_free_tx_0: 6505 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6506 tp->TxPhyAddr); 6507 tp->TxDescArray = NULL; 6508 err_pm_runtime_put: 6509 pm_runtime_put_noidle(&pdev->dev); 6510 goto out; 6511 } 6512 6513 static void 6514 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6515 { 6516 struct rtl8169_private *tp = netdev_priv(dev); 6517 struct pci_dev *pdev = tp->pci_dev; 6518 struct rtl8169_counters *counters = tp->counters; 6519 unsigned int start; 6520 6521 pm_runtime_get_noresume(&pdev->dev); 6522 6523 if (netif_running(dev) && pm_runtime_active(&pdev->dev)) 6524 rtl8169_rx_missed(dev); 6525 6526 do { 6527 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 6528 stats->rx_packets = tp->rx_stats.packets; 6529 stats->rx_bytes = tp->rx_stats.bytes; 6530 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 6531 6532 do { 6533 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 6534 stats->tx_packets = tp->tx_stats.packets; 6535 stats->tx_bytes = tp->tx_stats.bytes; 6536 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 6537 6538 stats->rx_dropped = dev->stats.rx_dropped; 6539 stats->tx_dropped = dev->stats.tx_dropped; 6540 stats->rx_length_errors = dev->stats.rx_length_errors; 6541 stats->rx_errors = dev->stats.rx_errors; 6542 stats->rx_crc_errors = dev->stats.rx_crc_errors; 6543 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 6544 stats->rx_missed_errors = dev->stats.rx_missed_errors; 6545 stats->multicast = dev->stats.multicast; 6546 6547 /* 6548 * Fetch additional counter values missing in stats collected by driver 6549 * from tally counters. 6550 */ 6551 if (pm_runtime_active(&pdev->dev)) 6552 rtl8169_update_counters(tp); 6553 6554 /* 6555 * Subtract values fetched during initalization. 6556 * See rtl8169_init_counter_offsets for a description why we do that. 6557 */ 6558 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 6559 le64_to_cpu(tp->tc_offset.tx_errors); 6560 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 6561 le32_to_cpu(tp->tc_offset.tx_multi_collision); 6562 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 6563 le16_to_cpu(tp->tc_offset.tx_aborted); 6564 6565 pm_runtime_put_noidle(&pdev->dev); 6566 } 6567 6568 static void rtl8169_net_suspend(struct net_device *dev) 6569 { 6570 struct rtl8169_private *tp = netdev_priv(dev); 6571 6572 if (!netif_running(dev)) 6573 return; 6574 6575 phy_stop(tp->phydev); 6576 netif_device_detach(dev); 6577 6578 rtl_lock_work(tp); 6579 napi_disable(&tp->napi); 6580 /* Clear all task flags */ 6581 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6582 6583 rtl_unlock_work(tp); 6584 6585 rtl_pll_power_down(tp); 6586 } 6587 6588 #ifdef CONFIG_PM 6589 6590 static int rtl8169_suspend(struct device *device) 6591 { 6592 struct net_device *dev = dev_get_drvdata(device); 6593 struct rtl8169_private *tp = netdev_priv(dev); 6594 6595 rtl8169_net_suspend(dev); 6596 clk_disable_unprepare(tp->clk); 6597 6598 return 0; 6599 } 6600 6601 static void __rtl8169_resume(struct net_device *dev) 6602 { 6603 struct rtl8169_private *tp = netdev_priv(dev); 6604 6605 netif_device_attach(dev); 6606 6607 rtl_pll_power_up(tp); 6608 rtl8169_init_phy(dev, tp); 6609 6610 phy_start(tp->phydev); 6611 6612 rtl_lock_work(tp); 6613 napi_enable(&tp->napi); 6614 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6615 rtl_reset_work(tp); 6616 rtl_unlock_work(tp); 6617 } 6618 6619 static int rtl8169_resume(struct device *device) 6620 { 6621 struct net_device *dev = dev_get_drvdata(device); 6622 struct rtl8169_private *tp = netdev_priv(dev); 6623 6624 rtl_rar_set(tp, dev->dev_addr); 6625 6626 clk_prepare_enable(tp->clk); 6627 6628 if (netif_running(dev)) 6629 __rtl8169_resume(dev); 6630 6631 return 0; 6632 } 6633 6634 static int rtl8169_runtime_suspend(struct device *device) 6635 { 6636 struct net_device *dev = dev_get_drvdata(device); 6637 struct rtl8169_private *tp = netdev_priv(dev); 6638 6639 if (!tp->TxDescArray) 6640 return 0; 6641 6642 rtl_lock_work(tp); 6643 __rtl8169_set_wol(tp, WAKE_ANY); 6644 rtl_unlock_work(tp); 6645 6646 rtl8169_net_suspend(dev); 6647 6648 /* Update counters before going runtime suspend */ 6649 rtl8169_rx_missed(dev); 6650 rtl8169_update_counters(tp); 6651 6652 return 0; 6653 } 6654 6655 static int rtl8169_runtime_resume(struct device *device) 6656 { 6657 struct net_device *dev = dev_get_drvdata(device); 6658 struct rtl8169_private *tp = netdev_priv(dev); 6659 6660 rtl_rar_set(tp, dev->dev_addr); 6661 6662 if (!tp->TxDescArray) 6663 return 0; 6664 6665 rtl_lock_work(tp); 6666 __rtl8169_set_wol(tp, tp->saved_wolopts); 6667 rtl_unlock_work(tp); 6668 6669 __rtl8169_resume(dev); 6670 6671 return 0; 6672 } 6673 6674 static int rtl8169_runtime_idle(struct device *device) 6675 { 6676 struct net_device *dev = dev_get_drvdata(device); 6677 6678 if (!netif_running(dev) || !netif_carrier_ok(dev)) 6679 pm_schedule_suspend(device, 10000); 6680 6681 return -EBUSY; 6682 } 6683 6684 static const struct dev_pm_ops rtl8169_pm_ops = { 6685 .suspend = rtl8169_suspend, 6686 .resume = rtl8169_resume, 6687 .freeze = rtl8169_suspend, 6688 .thaw = rtl8169_resume, 6689 .poweroff = rtl8169_suspend, 6690 .restore = rtl8169_resume, 6691 .runtime_suspend = rtl8169_runtime_suspend, 6692 .runtime_resume = rtl8169_runtime_resume, 6693 .runtime_idle = rtl8169_runtime_idle, 6694 }; 6695 6696 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 6697 6698 #else /* !CONFIG_PM */ 6699 6700 #define RTL8169_PM_OPS NULL 6701 6702 #endif /* !CONFIG_PM */ 6703 6704 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 6705 { 6706 /* WoL fails with 8168b when the receiver is disabled. */ 6707 switch (tp->mac_version) { 6708 case RTL_GIGA_MAC_VER_11: 6709 case RTL_GIGA_MAC_VER_12: 6710 case RTL_GIGA_MAC_VER_17: 6711 pci_clear_master(tp->pci_dev); 6712 6713 RTL_W8(tp, ChipCmd, CmdRxEnb); 6714 /* PCI commit */ 6715 RTL_R8(tp, ChipCmd); 6716 break; 6717 default: 6718 break; 6719 } 6720 } 6721 6722 static void rtl_shutdown(struct pci_dev *pdev) 6723 { 6724 struct net_device *dev = pci_get_drvdata(pdev); 6725 struct rtl8169_private *tp = netdev_priv(dev); 6726 6727 rtl8169_net_suspend(dev); 6728 6729 /* Restore original MAC address */ 6730 rtl_rar_set(tp, dev->perm_addr); 6731 6732 rtl8169_hw_reset(tp); 6733 6734 if (system_state == SYSTEM_POWER_OFF) { 6735 if (tp->saved_wolopts) { 6736 rtl_wol_suspend_quirk(tp); 6737 rtl_wol_shutdown_quirk(tp); 6738 } 6739 6740 pci_wake_from_d3(pdev, true); 6741 pci_set_power_state(pdev, PCI_D3hot); 6742 } 6743 } 6744 6745 static void rtl_remove_one(struct pci_dev *pdev) 6746 { 6747 struct net_device *dev = pci_get_drvdata(pdev); 6748 struct rtl8169_private *tp = netdev_priv(dev); 6749 6750 if (r8168_check_dash(tp)) 6751 rtl8168_driver_stop(tp); 6752 6753 netif_napi_del(&tp->napi); 6754 6755 unregister_netdev(dev); 6756 mdiobus_unregister(tp->phydev->mdio.bus); 6757 6758 rtl_release_firmware(tp); 6759 6760 if (pci_dev_run_wake(pdev)) 6761 pm_runtime_get_noresume(&pdev->dev); 6762 6763 /* restore original MAC address */ 6764 rtl_rar_set(tp, dev->perm_addr); 6765 } 6766 6767 static const struct net_device_ops rtl_netdev_ops = { 6768 .ndo_open = rtl_open, 6769 .ndo_stop = rtl8169_close, 6770 .ndo_get_stats64 = rtl8169_get_stats64, 6771 .ndo_start_xmit = rtl8169_start_xmit, 6772 .ndo_features_check = rtl8169_features_check, 6773 .ndo_tx_timeout = rtl8169_tx_timeout, 6774 .ndo_validate_addr = eth_validate_addr, 6775 .ndo_change_mtu = rtl8169_change_mtu, 6776 .ndo_fix_features = rtl8169_fix_features, 6777 .ndo_set_features = rtl8169_set_features, 6778 .ndo_set_mac_address = rtl_set_mac_address, 6779 .ndo_do_ioctl = rtl8169_ioctl, 6780 .ndo_set_rx_mode = rtl_set_rx_mode, 6781 #ifdef CONFIG_NET_POLL_CONTROLLER 6782 .ndo_poll_controller = rtl8169_netpoll, 6783 #endif 6784 6785 }; 6786 6787 static void rtl_set_irq_mask(struct rtl8169_private *tp) 6788 { 6789 tp->irq_mask = RTL_EVENT_NAPI | LinkChg; 6790 6791 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 6792 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 6793 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 6794 /* special workaround needed */ 6795 tp->irq_mask |= RxFIFOOver; 6796 else 6797 tp->irq_mask |= RxOverflow; 6798 } 6799 6800 static int rtl_alloc_irq(struct rtl8169_private *tp) 6801 { 6802 unsigned int flags; 6803 6804 switch (tp->mac_version) { 6805 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6806 rtl_unlock_config_regs(tp); 6807 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 6808 rtl_lock_config_regs(tp); 6809 /* fall through */ 6810 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24: 6811 flags = PCI_IRQ_LEGACY; 6812 break; 6813 default: 6814 flags = PCI_IRQ_ALL_TYPES; 6815 break; 6816 } 6817 6818 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 6819 } 6820 6821 static void rtl_read_mac_address(struct rtl8169_private *tp, 6822 u8 mac_addr[ETH_ALEN]) 6823 { 6824 /* Get MAC address */ 6825 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 6826 u32 value = rtl_eri_read(tp, 0xe0); 6827 6828 mac_addr[0] = (value >> 0) & 0xff; 6829 mac_addr[1] = (value >> 8) & 0xff; 6830 mac_addr[2] = (value >> 16) & 0xff; 6831 mac_addr[3] = (value >> 24) & 0xff; 6832 6833 value = rtl_eri_read(tp, 0xe4); 6834 mac_addr[4] = (value >> 0) & 0xff; 6835 mac_addr[5] = (value >> 8) & 0xff; 6836 } else if (rtl_is_8125(tp)) { 6837 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 6838 } 6839 } 6840 6841 DECLARE_RTL_COND(rtl_link_list_ready_cond) 6842 { 6843 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 6844 } 6845 6846 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 6847 { 6848 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 6849 } 6850 6851 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 6852 { 6853 struct rtl8169_private *tp = mii_bus->priv; 6854 6855 if (phyaddr > 0) 6856 return -ENODEV; 6857 6858 return rtl_readphy(tp, phyreg); 6859 } 6860 6861 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 6862 int phyreg, u16 val) 6863 { 6864 struct rtl8169_private *tp = mii_bus->priv; 6865 6866 if (phyaddr > 0) 6867 return -ENODEV; 6868 6869 rtl_writephy(tp, phyreg, val); 6870 6871 return 0; 6872 } 6873 6874 static int r8169_mdio_register(struct rtl8169_private *tp) 6875 { 6876 struct pci_dev *pdev = tp->pci_dev; 6877 struct mii_bus *new_bus; 6878 int ret; 6879 6880 new_bus = devm_mdiobus_alloc(&pdev->dev); 6881 if (!new_bus) 6882 return -ENOMEM; 6883 6884 new_bus->name = "r8169"; 6885 new_bus->priv = tp; 6886 new_bus->parent = &pdev->dev; 6887 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 6888 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 6889 6890 new_bus->read = r8169_mdio_read_reg; 6891 new_bus->write = r8169_mdio_write_reg; 6892 6893 ret = mdiobus_register(new_bus); 6894 if (ret) 6895 return ret; 6896 6897 tp->phydev = mdiobus_get_phy(new_bus, 0); 6898 if (!tp->phydev) { 6899 mdiobus_unregister(new_bus); 6900 return -ENODEV; 6901 } 6902 6903 /* PHY will be woken up in rtl_open() */ 6904 phy_suspend(tp->phydev); 6905 6906 return 0; 6907 } 6908 6909 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 6910 { 6911 tp->ocp_base = OCP_STD_PHY_BASE; 6912 6913 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6914 6915 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 6916 return; 6917 6918 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6919 return; 6920 6921 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6922 msleep(1); 6923 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6924 6925 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6926 6927 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6928 return; 6929 6930 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 6931 6932 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6933 } 6934 6935 static void rtl_hw_init_8125(struct rtl8169_private *tp) 6936 { 6937 tp->ocp_base = OCP_STD_PHY_BASE; 6938 6939 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6940 6941 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6942 return; 6943 6944 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6945 msleep(1); 6946 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6947 6948 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6949 6950 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6951 return; 6952 6953 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 6954 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 6955 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 6956 6957 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6958 } 6959 6960 static void rtl_hw_initialize(struct rtl8169_private *tp) 6961 { 6962 switch (tp->mac_version) { 6963 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51: 6964 rtl8168ep_stop_cmac(tp); 6965 /* fall through */ 6966 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 6967 rtl_hw_init_8168g(tp); 6968 break; 6969 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 6970 rtl_hw_init_8125(tp); 6971 break; 6972 default: 6973 break; 6974 } 6975 } 6976 6977 static int rtl_jumbo_max(struct rtl8169_private *tp) 6978 { 6979 /* Non-GBit versions don't support jumbo frames */ 6980 if (!tp->supports_gmii) 6981 return JUMBO_1K; 6982 6983 switch (tp->mac_version) { 6984 /* RTL8169 */ 6985 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6986 return JUMBO_7K; 6987 /* RTL8168b */ 6988 case RTL_GIGA_MAC_VER_11: 6989 case RTL_GIGA_MAC_VER_12: 6990 case RTL_GIGA_MAC_VER_17: 6991 return JUMBO_4K; 6992 /* RTL8168c */ 6993 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 6994 return JUMBO_6K; 6995 default: 6996 return JUMBO_9K; 6997 } 6998 } 6999 7000 static void rtl_disable_clk(void *data) 7001 { 7002 clk_disable_unprepare(data); 7003 } 7004 7005 static int rtl_get_ether_clk(struct rtl8169_private *tp) 7006 { 7007 struct device *d = tp_to_dev(tp); 7008 struct clk *clk; 7009 int rc; 7010 7011 clk = devm_clk_get(d, "ether_clk"); 7012 if (IS_ERR(clk)) { 7013 rc = PTR_ERR(clk); 7014 if (rc == -ENOENT) 7015 /* clk-core allows NULL (for suspend / resume) */ 7016 rc = 0; 7017 else if (rc != -EPROBE_DEFER) 7018 dev_err(d, "failed to get clk: %d\n", rc); 7019 } else { 7020 tp->clk = clk; 7021 rc = clk_prepare_enable(clk); 7022 if (rc) 7023 dev_err(d, "failed to enable clk: %d\n", rc); 7024 else 7025 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 7026 } 7027 7028 return rc; 7029 } 7030 7031 static void rtl_init_mac_address(struct rtl8169_private *tp) 7032 { 7033 struct net_device *dev = tp->dev; 7034 u8 *mac_addr = dev->dev_addr; 7035 int rc; 7036 7037 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 7038 if (!rc) 7039 goto done; 7040 7041 rtl_read_mac_address(tp, mac_addr); 7042 if (is_valid_ether_addr(mac_addr)) 7043 goto done; 7044 7045 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 7046 if (is_valid_ether_addr(mac_addr)) 7047 goto done; 7048 7049 eth_hw_addr_random(dev); 7050 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 7051 done: 7052 rtl_rar_set(tp, mac_addr); 7053 } 7054 7055 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 7056 { 7057 struct rtl8169_private *tp; 7058 struct net_device *dev; 7059 int chipset, region; 7060 int jumbo_max, rc; 7061 7062 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 7063 if (!dev) 7064 return -ENOMEM; 7065 7066 SET_NETDEV_DEV(dev, &pdev->dev); 7067 dev->netdev_ops = &rtl_netdev_ops; 7068 tp = netdev_priv(dev); 7069 tp->dev = dev; 7070 tp->pci_dev = pdev; 7071 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 7072 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 7073 7074 /* Get the *optional* external "ether_clk" used on some boards */ 7075 rc = rtl_get_ether_clk(tp); 7076 if (rc) 7077 return rc; 7078 7079 /* Disable ASPM completely as that cause random device stop working 7080 * problems as well as full system hangs for some PCIe devices users. 7081 */ 7082 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 7083 PCIE_LINK_STATE_L1); 7084 tp->aspm_manageable = !rc; 7085 7086 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 7087 rc = pcim_enable_device(pdev); 7088 if (rc < 0) { 7089 dev_err(&pdev->dev, "enable failure\n"); 7090 return rc; 7091 } 7092 7093 if (pcim_set_mwi(pdev) < 0) 7094 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 7095 7096 /* use first MMIO region */ 7097 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 7098 if (region < 0) { 7099 dev_err(&pdev->dev, "no MMIO resource found\n"); 7100 return -ENODEV; 7101 } 7102 7103 /* check for weird/broken PCI region reporting */ 7104 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 7105 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 7106 return -ENODEV; 7107 } 7108 7109 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 7110 if (rc < 0) { 7111 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 7112 return rc; 7113 } 7114 7115 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 7116 7117 /* Identify chip attached to board */ 7118 rtl8169_get_mac_version(tp); 7119 if (tp->mac_version == RTL_GIGA_MAC_NONE) 7120 return -ENODEV; 7121 7122 tp->cp_cmd = RTL_R16(tp, CPlusCmd); 7123 7124 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 7125 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 7126 dev->features |= NETIF_F_HIGHDMA; 7127 7128 rtl_init_rxcfg(tp); 7129 7130 rtl8169_irq_mask_and_ack(tp); 7131 7132 rtl_hw_initialize(tp); 7133 7134 rtl_hw_reset(tp); 7135 7136 pci_set_master(pdev); 7137 7138 chipset = tp->mac_version; 7139 7140 rc = rtl_alloc_irq(tp); 7141 if (rc < 0) { 7142 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 7143 return rc; 7144 } 7145 7146 mutex_init(&tp->wk.mutex); 7147 INIT_WORK(&tp->wk.work, rtl_task); 7148 u64_stats_init(&tp->rx_stats.syncp); 7149 u64_stats_init(&tp->tx_stats.syncp); 7150 7151 rtl_init_mac_address(tp); 7152 7153 dev->ethtool_ops = &rtl8169_ethtool_ops; 7154 7155 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 7156 7157 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7158 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 7159 NETIF_F_HW_VLAN_CTAG_RX; 7160 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7161 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 7162 NETIF_F_HW_VLAN_CTAG_RX; 7163 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7164 NETIF_F_HIGHDMA; 7165 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 7166 7167 tp->cp_cmd |= RxChkSum; 7168 /* RTL8125 uses register RxConfig for VLAN offloading config */ 7169 if (!rtl_is_8125(tp)) 7170 tp->cp_cmd |= RxVlan; 7171 /* 7172 * Pretend we are using VLANs; This bypasses a nasty bug where 7173 * Interrupts stop flowing on high load on 8110SCd controllers. 7174 */ 7175 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 7176 /* Disallow toggling */ 7177 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 7178 7179 if (rtl_chip_supports_csum_v2(tp)) { 7180 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 7181 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 7182 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 7183 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 7184 } else { 7185 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 7186 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 7187 } 7188 7189 /* RTL8168e-vl has a HW issue with TSO */ 7190 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { 7191 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7192 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7193 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7194 } 7195 7196 dev->hw_features |= NETIF_F_RXALL; 7197 dev->hw_features |= NETIF_F_RXFCS; 7198 7199 /* MTU range: 60 - hw-specific max */ 7200 dev->min_mtu = ETH_ZLEN; 7201 jumbo_max = rtl_jumbo_max(tp); 7202 dev->max_mtu = jumbo_max; 7203 7204 rtl_set_irq_mask(tp); 7205 7206 tp->fw_name = rtl_chip_infos[chipset].fw_name; 7207 7208 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 7209 &tp->counters_phys_addr, 7210 GFP_KERNEL); 7211 if (!tp->counters) 7212 return -ENOMEM; 7213 7214 pci_set_drvdata(pdev, dev); 7215 7216 rc = r8169_mdio_register(tp); 7217 if (rc) 7218 return rc; 7219 7220 /* chip gets powered up in rtl_open() */ 7221 rtl_pll_power_down(tp); 7222 7223 rc = register_netdev(dev); 7224 if (rc) 7225 goto err_mdio_unregister; 7226 7227 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 7228 rtl_chip_infos[chipset].name, dev->dev_addr, 7229 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf, 7230 pci_irq_vector(pdev, 0)); 7231 7232 if (jumbo_max > JUMBO_1K) 7233 netif_info(tp, probe, dev, 7234 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 7235 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 7236 "ok" : "ko"); 7237 7238 if (r8168_check_dash(tp)) 7239 rtl8168_driver_start(tp); 7240 7241 if (pci_dev_run_wake(pdev)) 7242 pm_runtime_put_sync(&pdev->dev); 7243 7244 return 0; 7245 7246 err_mdio_unregister: 7247 mdiobus_unregister(tp->phydev->mdio.bus); 7248 return rc; 7249 } 7250 7251 static struct pci_driver rtl8169_pci_driver = { 7252 .name = MODULENAME, 7253 .id_table = rtl8169_pci_tbl, 7254 .probe = rtl_init_one, 7255 .remove = rtl_remove_one, 7256 .shutdown = rtl_shutdown, 7257 .driver.pm = RTL8169_PM_OPS, 7258 }; 7259 7260 module_pci_driver(rtl8169_pci_driver); 7261