1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 61 #define MC_FILTER_LIMIT 32 62 63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 65 66 #define R8169_REGS_SIZE 256 67 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 68 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 69 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 72 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 73 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 74 75 #define OCP_STD_PHY_BASE 0xa400 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92 static const struct { 93 const char *name; 94 const char *fw_name; 95 } rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 143 }; 144 145 static const struct pci_device_id rtl8169_pci_tbl[] = { 146 { PCI_VDEVICE(REALTEK, 0x2502) }, 147 { PCI_VDEVICE(REALTEK, 0x2600) }, 148 { PCI_VDEVICE(REALTEK, 0x8129) }, 149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 150 { PCI_VDEVICE(REALTEK, 0x8161) }, 151 { PCI_VDEVICE(REALTEK, 0x8162) }, 152 { PCI_VDEVICE(REALTEK, 0x8167) }, 153 { PCI_VDEVICE(REALTEK, 0x8168) }, 154 { PCI_VDEVICE(NCUBE, 0x8168) }, 155 { PCI_VDEVICE(REALTEK, 0x8169) }, 156 { PCI_VENDOR_ID_DLINK, 0x4300, 157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 158 { PCI_VDEVICE(DLINK, 0x4300) }, 159 { PCI_VDEVICE(DLINK, 0x4302) }, 160 { PCI_VDEVICE(AT, 0xc107) }, 161 { PCI_VDEVICE(USR, 0x0116) }, 162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 164 { PCI_VDEVICE(REALTEK, 0x8125) }, 165 { PCI_VDEVICE(REALTEK, 0x3000) }, 166 {} 167 }; 168 169 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 170 171 enum rtl_registers { 172 MAC0 = 0, /* Ethernet hardware address. */ 173 MAC4 = 4, 174 MAR0 = 8, /* Multicast filter. */ 175 CounterAddrLow = 0x10, 176 CounterAddrHigh = 0x14, 177 TxDescStartAddrLow = 0x20, 178 TxDescStartAddrHigh = 0x24, 179 TxHDescStartAddrLow = 0x28, 180 TxHDescStartAddrHigh = 0x2c, 181 FLASH = 0x30, 182 ERSR = 0x36, 183 ChipCmd = 0x37, 184 TxPoll = 0x38, 185 IntrMask = 0x3c, 186 IntrStatus = 0x3e, 187 188 TxConfig = 0x40, 189 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 190 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 191 192 RxConfig = 0x44, 193 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 194 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 195 #define RXCFG_FIFO_SHIFT 13 196 /* No threshold before first PCI xfer */ 197 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 198 #define RX_EARLY_OFF (1 << 11) 199 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 200 #define RXCFG_DMA_SHIFT 8 201 /* Unlimited maximum PCI burst. */ 202 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 203 204 Cfg9346 = 0x50, 205 Config0 = 0x51, 206 Config1 = 0x52, 207 Config2 = 0x53, 208 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 209 210 Config3 = 0x54, 211 Config4 = 0x55, 212 Config5 = 0x56, 213 PHYAR = 0x60, 214 PHYstatus = 0x6c, 215 RxMaxSize = 0xda, 216 CPlusCmd = 0xe0, 217 IntrMitigate = 0xe2, 218 219 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 220 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 221 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 222 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 223 224 #define RTL_COALESCE_T_MAX 0x0fU 225 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 226 227 RxDescAddrLow = 0xe4, 228 RxDescAddrHigh = 0xe8, 229 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 230 231 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 232 233 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 234 235 #define TxPacketMax (8064 >> 7) 236 #define EarlySize 0x27 237 238 FuncEvent = 0xf0, 239 FuncEventMask = 0xf4, 240 FuncPresetState = 0xf8, 241 IBCR0 = 0xf8, 242 IBCR2 = 0xf9, 243 IBIMR0 = 0xfa, 244 IBISR0 = 0xfb, 245 FuncForceEvent = 0xfc, 246 }; 247 248 enum rtl8168_8101_registers { 249 CSIDR = 0x64, 250 CSIAR = 0x68, 251 #define CSIAR_FLAG 0x80000000 252 #define CSIAR_WRITE_CMD 0x80000000 253 #define CSIAR_BYTE_ENABLE 0x0000f000 254 #define CSIAR_ADDR_MASK 0x00000fff 255 PMCH = 0x6f, 256 #define D3COLD_NO_PLL_DOWN BIT(7) 257 #define D3HOT_NO_PLL_DOWN BIT(6) 258 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 259 EPHYAR = 0x80, 260 #define EPHYAR_FLAG 0x80000000 261 #define EPHYAR_WRITE_CMD 0x80000000 262 #define EPHYAR_REG_MASK 0x1f 263 #define EPHYAR_REG_SHIFT 16 264 #define EPHYAR_DATA_MASK 0xffff 265 DLLPR = 0xd0, 266 #define PFM_EN (1 << 6) 267 #define TX_10M_PS_EN (1 << 7) 268 DBG_REG = 0xd1, 269 #define FIX_NAK_1 (1 << 4) 270 #define FIX_NAK_2 (1 << 3) 271 TWSI = 0xd2, 272 MCU = 0xd3, 273 #define NOW_IS_OOB (1 << 7) 274 #define TX_EMPTY (1 << 5) 275 #define RX_EMPTY (1 << 4) 276 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 277 #define EN_NDP (1 << 3) 278 #define EN_OOB_RESET (1 << 2) 279 #define LINK_LIST_RDY (1 << 1) 280 EFUSEAR = 0xdc, 281 #define EFUSEAR_FLAG 0x80000000 282 #define EFUSEAR_WRITE_CMD 0x80000000 283 #define EFUSEAR_READ_CMD 0x00000000 284 #define EFUSEAR_REG_MASK 0x03ff 285 #define EFUSEAR_REG_SHIFT 8 286 #define EFUSEAR_DATA_MASK 0xff 287 MISC_1 = 0xf2, 288 #define PFM_D3COLD_EN (1 << 6) 289 }; 290 291 enum rtl8168_registers { 292 LED_FREQ = 0x1a, 293 EEE_LED = 0x1b, 294 ERIDR = 0x70, 295 ERIAR = 0x74, 296 #define ERIAR_FLAG 0x80000000 297 #define ERIAR_WRITE_CMD 0x80000000 298 #define ERIAR_READ_CMD 0x00000000 299 #define ERIAR_ADDR_BYTE_ALIGN 4 300 #define ERIAR_TYPE_SHIFT 16 301 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_MASK_SHIFT 12 306 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 311 EPHY_RXER_NUM = 0x7c, 312 OCPDR = 0xb0, /* OCP GPHY access */ 313 #define OCPDR_WRITE_CMD 0x80000000 314 #define OCPDR_READ_CMD 0x00000000 315 #define OCPDR_REG_MASK 0x7f 316 #define OCPDR_GPHY_REG_SHIFT 16 317 #define OCPDR_DATA_MASK 0xffff 318 OCPAR = 0xb4, 319 #define OCPAR_FLAG 0x80000000 320 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 321 #define OCPAR_GPHY_READ_CMD 0x0000f060 322 GPHY_OCP = 0xb8, 323 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 324 MISC = 0xf0, /* 8168e only. */ 325 #define TXPLA_RST (1 << 29) 326 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 327 #define PWM_EN (1 << 22) 328 #define RXDV_GATED_EN (1 << 19) 329 #define EARLY_TALLY_EN (1 << 16) 330 }; 331 332 enum rtl8125_registers { 333 IntrMask_8125 = 0x38, 334 IntrStatus_8125 = 0x3c, 335 TxPoll_8125 = 0x90, 336 MAC0_BKP = 0x19e0, 337 EEE_TXIDLE_TIMER_8125 = 0x6048, 338 }; 339 340 #define RX_VLAN_INNER_8125 BIT(22) 341 #define RX_VLAN_OUTER_8125 BIT(23) 342 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 343 344 #define RX_FETCH_DFLT_8125 (8 << 27) 345 346 enum rtl_register_content { 347 /* InterruptStatusBits */ 348 SYSErr = 0x8000, 349 PCSTimeout = 0x4000, 350 SWInt = 0x0100, 351 TxDescUnavail = 0x0080, 352 RxFIFOOver = 0x0040, 353 LinkChg = 0x0020, 354 RxOverflow = 0x0010, 355 TxErr = 0x0008, 356 TxOK = 0x0004, 357 RxErr = 0x0002, 358 RxOK = 0x0001, 359 360 /* RxStatusDesc */ 361 RxRWT = (1 << 22), 362 RxRES = (1 << 21), 363 RxRUNT = (1 << 20), 364 RxCRC = (1 << 19), 365 366 /* ChipCmdBits */ 367 StopReq = 0x80, 368 CmdReset = 0x10, 369 CmdRxEnb = 0x08, 370 CmdTxEnb = 0x04, 371 RxBufEmpty = 0x01, 372 373 /* TXPoll register p.5 */ 374 HPQ = 0x80, /* Poll cmd on the high prio queue */ 375 NPQ = 0x40, /* Poll cmd on the low prio queue */ 376 FSWInt = 0x01, /* Forced software interrupt */ 377 378 /* Cfg9346Bits */ 379 Cfg9346_Lock = 0x00, 380 Cfg9346_Unlock = 0xc0, 381 382 /* rx_mode_bits */ 383 AcceptErr = 0x20, 384 AcceptRunt = 0x10, 385 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 386 AcceptBroadcast = 0x08, 387 AcceptMulticast = 0x04, 388 AcceptMyPhys = 0x02, 389 AcceptAllPhys = 0x01, 390 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 391 #define RX_CONFIG_ACCEPT_MASK 0x3f 392 393 /* TxConfigBits */ 394 TxInterFrameGapShift = 24, 395 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 396 397 /* Config1 register p.24 */ 398 LEDS1 = (1 << 7), 399 LEDS0 = (1 << 6), 400 Speed_down = (1 << 4), 401 MEMMAP = (1 << 3), 402 IOMAP = (1 << 2), 403 VPD = (1 << 1), 404 PMEnable = (1 << 0), /* Power Management Enable */ 405 406 /* Config2 register p. 25 */ 407 ClkReqEn = (1 << 7), /* Clock Request Enable */ 408 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 409 PCI_Clock_66MHz = 0x01, 410 PCI_Clock_33MHz = 0x00, 411 412 /* Config3 register p.25 */ 413 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 414 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 415 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 416 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 417 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 418 419 /* Config4 register */ 420 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 421 422 /* Config5 register p.27 */ 423 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 424 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 425 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 426 Spi_en = (1 << 3), 427 LanWake = (1 << 1), /* LanWake enable/disable */ 428 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 429 ASPM_en = (1 << 0), /* ASPM enable */ 430 431 /* CPlusCmd p.31 */ 432 EnableBist = (1 << 15), // 8168 8101 433 Mac_dbgo_oe = (1 << 14), // 8168 8101 434 EnAnaPLL = (1 << 14), // 8169 435 Normal_mode = (1 << 13), // unused 436 Force_half_dup = (1 << 12), // 8168 8101 437 Force_rxflow_en = (1 << 11), // 8168 8101 438 Force_txflow_en = (1 << 10), // 8168 8101 439 Cxpl_dbg_sel = (1 << 9), // 8168 8101 440 ASF = (1 << 8), // 8168 8101 441 PktCntrDisable = (1 << 7), // 8168 8101 442 Mac_dbgo_sel = 0x001c, // 8168 443 RxVlan = (1 << 6), 444 RxChkSum = (1 << 5), 445 PCIDAC = (1 << 4), 446 PCIMulRW = (1 << 3), 447 #define INTT_MASK GENMASK(1, 0) 448 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 449 450 /* rtl8169_PHYstatus */ 451 TBI_Enable = 0x80, 452 TxFlowCtrl = 0x40, 453 RxFlowCtrl = 0x20, 454 _1000bpsF = 0x10, 455 _100bps = 0x08, 456 _10bps = 0x04, 457 LinkStatus = 0x02, 458 FullDup = 0x01, 459 460 /* ResetCounterCommand */ 461 CounterReset = 0x1, 462 463 /* DumpCounterCommand */ 464 CounterDump = 0x8, 465 466 /* magic enable v2 */ 467 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 468 }; 469 470 enum rtl_desc_bit { 471 /* First doubleword. */ 472 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 473 RingEnd = (1 << 30), /* End of descriptor ring */ 474 FirstFrag = (1 << 29), /* First segment of a packet */ 475 LastFrag = (1 << 28), /* Final segment of a packet */ 476 }; 477 478 /* Generic case. */ 479 enum rtl_tx_desc_bit { 480 /* First doubleword. */ 481 TD_LSO = (1 << 27), /* Large Send Offload */ 482 #define TD_MSS_MAX 0x07ffu /* MSS value */ 483 484 /* Second doubleword. */ 485 TxVlanTag = (1 << 17), /* Add VLAN tag */ 486 }; 487 488 /* 8169, 8168b and 810x except 8102e. */ 489 enum rtl_tx_desc_bit_0 { 490 /* First doubleword. */ 491 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 492 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 493 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 494 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 495 }; 496 497 /* 8102e, 8168c and beyond. */ 498 enum rtl_tx_desc_bit_1 { 499 /* First doubleword. */ 500 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 501 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 502 #define GTTCPHO_SHIFT 18 503 #define GTTCPHO_MAX 0x7f 504 505 /* Second doubleword. */ 506 #define TCPHO_SHIFT 18 507 #define TCPHO_MAX 0x3ff 508 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 509 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 510 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 511 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 512 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 513 }; 514 515 enum rtl_rx_desc_bit { 516 /* Rx private */ 517 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 518 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 519 520 #define RxProtoUDP (PID1) 521 #define RxProtoTCP (PID0) 522 #define RxProtoIP (PID1 | PID0) 523 #define RxProtoMask RxProtoIP 524 525 IPFail = (1 << 16), /* IP checksum failed */ 526 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 527 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 528 529 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 530 531 RxVlanTag = (1 << 16), /* VLAN tag available */ 532 }; 533 534 #define RTL_GSO_MAX_SIZE_V1 32000 535 #define RTL_GSO_MAX_SEGS_V1 24 536 #define RTL_GSO_MAX_SIZE_V2 64000 537 #define RTL_GSO_MAX_SEGS_V2 64 538 539 struct TxDesc { 540 __le32 opts1; 541 __le32 opts2; 542 __le64 addr; 543 }; 544 545 struct RxDesc { 546 __le32 opts1; 547 __le32 opts2; 548 __le64 addr; 549 }; 550 551 struct ring_info { 552 struct sk_buff *skb; 553 u32 len; 554 }; 555 556 struct rtl8169_counters { 557 __le64 tx_packets; 558 __le64 rx_packets; 559 __le64 tx_errors; 560 __le32 rx_errors; 561 __le16 rx_missed; 562 __le16 align_errors; 563 __le32 tx_one_collision; 564 __le32 tx_multi_collision; 565 __le64 rx_unicast; 566 __le64 rx_broadcast; 567 __le32 rx_multicast; 568 __le16 tx_aborted; 569 __le16 tx_underrun; 570 /* new since RTL8125 */ 571 __le64 tx_octets; 572 __le64 rx_octets; 573 __le64 rx_multicast64; 574 __le64 tx_unicast64; 575 __le64 tx_broadcast64; 576 __le64 tx_multicast64; 577 __le32 tx_pause_on; 578 __le32 tx_pause_off; 579 __le32 tx_pause_all; 580 __le32 tx_deferred; 581 __le32 tx_late_collision; 582 __le32 tx_all_collision; 583 __le32 tx_aborted32; 584 __le32 align_errors32; 585 __le32 rx_frame_too_long; 586 __le32 rx_runt; 587 __le32 rx_pause_on; 588 __le32 rx_pause_off; 589 __le32 rx_pause_all; 590 __le32 rx_unknown_opcode; 591 __le32 rx_mac_error; 592 __le32 tx_underrun32; 593 __le32 rx_mac_missed; 594 __le32 rx_tcam_dropped; 595 __le32 tdu; 596 __le32 rdu; 597 }; 598 599 struct rtl8169_tc_offsets { 600 bool inited; 601 __le64 tx_errors; 602 __le32 tx_multi_collision; 603 __le16 tx_aborted; 604 __le16 rx_missed; 605 }; 606 607 enum rtl_flag { 608 RTL_FLAG_TASK_ENABLED = 0, 609 RTL_FLAG_TASK_RESET_PENDING, 610 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 611 RTL_FLAG_TASK_TX_TIMEOUT, 612 RTL_FLAG_MAX 613 }; 614 615 enum rtl_dash_type { 616 RTL_DASH_NONE, 617 RTL_DASH_DP, 618 RTL_DASH_EP, 619 }; 620 621 struct rtl8169_private { 622 void __iomem *mmio_addr; /* memory map physical address */ 623 struct pci_dev *pci_dev; 624 struct net_device *dev; 625 struct phy_device *phydev; 626 struct napi_struct napi; 627 enum mac_version mac_version; 628 enum rtl_dash_type dash_type; 629 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 630 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 631 u32 dirty_tx; 632 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 633 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 634 dma_addr_t TxPhyAddr; 635 dma_addr_t RxPhyAddr; 636 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 637 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 638 u16 cp_cmd; 639 u32 irq_mask; 640 int irq; 641 struct clk *clk; 642 643 struct { 644 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 645 struct work_struct work; 646 } wk; 647 648 raw_spinlock_t config25_lock; 649 raw_spinlock_t mac_ocp_lock; 650 651 raw_spinlock_t cfg9346_usage_lock; 652 int cfg9346_usage_count; 653 654 unsigned supports_gmii:1; 655 unsigned aspm_manageable:1; 656 unsigned dash_enabled:1; 657 dma_addr_t counters_phys_addr; 658 struct rtl8169_counters *counters; 659 struct rtl8169_tc_offsets tc_offset; 660 u32 saved_wolopts; 661 int eee_adv; 662 663 const char *fw_name; 664 struct rtl_fw *rtl_fw; 665 666 u32 ocp_base; 667 }; 668 669 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 670 671 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 672 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 673 MODULE_SOFTDEP("pre: realtek"); 674 MODULE_LICENSE("GPL"); 675 MODULE_FIRMWARE(FIRMWARE_8168D_1); 676 MODULE_FIRMWARE(FIRMWARE_8168D_2); 677 MODULE_FIRMWARE(FIRMWARE_8168E_1); 678 MODULE_FIRMWARE(FIRMWARE_8168E_2); 679 MODULE_FIRMWARE(FIRMWARE_8168E_3); 680 MODULE_FIRMWARE(FIRMWARE_8105E_1); 681 MODULE_FIRMWARE(FIRMWARE_8168F_1); 682 MODULE_FIRMWARE(FIRMWARE_8168F_2); 683 MODULE_FIRMWARE(FIRMWARE_8402_1); 684 MODULE_FIRMWARE(FIRMWARE_8411_1); 685 MODULE_FIRMWARE(FIRMWARE_8411_2); 686 MODULE_FIRMWARE(FIRMWARE_8106E_1); 687 MODULE_FIRMWARE(FIRMWARE_8106E_2); 688 MODULE_FIRMWARE(FIRMWARE_8168G_2); 689 MODULE_FIRMWARE(FIRMWARE_8168G_3); 690 MODULE_FIRMWARE(FIRMWARE_8168H_2); 691 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 692 MODULE_FIRMWARE(FIRMWARE_8107E_2); 693 MODULE_FIRMWARE(FIRMWARE_8125A_3); 694 MODULE_FIRMWARE(FIRMWARE_8125B_2); 695 696 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 697 { 698 return &tp->pci_dev->dev; 699 } 700 701 static void rtl_lock_config_regs(struct rtl8169_private *tp) 702 { 703 unsigned long flags; 704 705 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 706 if (!--tp->cfg9346_usage_count) 707 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 708 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 709 } 710 711 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 712 { 713 unsigned long flags; 714 715 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 716 if (!tp->cfg9346_usage_count++) 717 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 718 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 719 } 720 721 static void rtl_pci_commit(struct rtl8169_private *tp) 722 { 723 /* Read an arbitrary register to commit a preceding PCI write */ 724 RTL_R8(tp, ChipCmd); 725 } 726 727 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 728 { 729 unsigned long flags; 730 u8 val; 731 732 raw_spin_lock_irqsave(&tp->config25_lock, flags); 733 val = RTL_R8(tp, Config2); 734 RTL_W8(tp, Config2, (val & ~clear) | set); 735 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 736 } 737 738 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 739 { 740 unsigned long flags; 741 u8 val; 742 743 raw_spin_lock_irqsave(&tp->config25_lock, flags); 744 val = RTL_R8(tp, Config5); 745 RTL_W8(tp, Config5, (val & ~clear) | set); 746 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 747 } 748 749 static bool rtl_is_8125(struct rtl8169_private *tp) 750 { 751 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 752 } 753 754 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 755 { 756 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 757 tp->mac_version != RTL_GIGA_MAC_VER_39 && 758 tp->mac_version <= RTL_GIGA_MAC_VER_53; 759 } 760 761 static bool rtl_supports_eee(struct rtl8169_private *tp) 762 { 763 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 764 tp->mac_version != RTL_GIGA_MAC_VER_37 && 765 tp->mac_version != RTL_GIGA_MAC_VER_39; 766 } 767 768 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 769 { 770 int i; 771 772 for (i = 0; i < ETH_ALEN; i++) 773 mac[i] = RTL_R8(tp, reg + i); 774 } 775 776 struct rtl_cond { 777 bool (*check)(struct rtl8169_private *); 778 const char *msg; 779 }; 780 781 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 782 unsigned long usecs, int n, bool high) 783 { 784 int i; 785 786 for (i = 0; i < n; i++) { 787 if (c->check(tp) == high) 788 return true; 789 fsleep(usecs); 790 } 791 792 if (net_ratelimit()) 793 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 794 c->msg, !high, n, usecs); 795 return false; 796 } 797 798 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 799 const struct rtl_cond *c, 800 unsigned long d, int n) 801 { 802 return rtl_loop_wait(tp, c, d, n, true); 803 } 804 805 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 806 const struct rtl_cond *c, 807 unsigned long d, int n) 808 { 809 return rtl_loop_wait(tp, c, d, n, false); 810 } 811 812 #define DECLARE_RTL_COND(name) \ 813 static bool name ## _check(struct rtl8169_private *); \ 814 \ 815 static const struct rtl_cond name = { \ 816 .check = name ## _check, \ 817 .msg = #name \ 818 }; \ 819 \ 820 static bool name ## _check(struct rtl8169_private *tp) 821 822 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 823 { 824 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 825 if (type == ERIAR_OOB && 826 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 827 tp->mac_version == RTL_GIGA_MAC_VER_53)) 828 *cmd |= 0xf70 << 18; 829 } 830 831 DECLARE_RTL_COND(rtl_eriar_cond) 832 { 833 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 834 } 835 836 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 837 u32 val, int type) 838 { 839 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 840 841 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 842 return; 843 844 RTL_W32(tp, ERIDR, val); 845 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 846 RTL_W32(tp, ERIAR, cmd); 847 848 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 849 } 850 851 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 852 u32 val) 853 { 854 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 855 } 856 857 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 858 { 859 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 860 861 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 862 RTL_W32(tp, ERIAR, cmd); 863 864 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 865 RTL_R32(tp, ERIDR) : ~0; 866 } 867 868 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 869 { 870 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 871 } 872 873 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 874 { 875 u32 val = rtl_eri_read(tp, addr); 876 877 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 878 } 879 880 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 881 { 882 rtl_w0w1_eri(tp, addr, p, 0); 883 } 884 885 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 886 { 887 rtl_w0w1_eri(tp, addr, 0, m); 888 } 889 890 static bool rtl_ocp_reg_failure(u32 reg) 891 { 892 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 893 } 894 895 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 896 { 897 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 898 } 899 900 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 901 { 902 if (rtl_ocp_reg_failure(reg)) 903 return; 904 905 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 906 907 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 908 } 909 910 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 911 { 912 if (rtl_ocp_reg_failure(reg)) 913 return 0; 914 915 RTL_W32(tp, GPHY_OCP, reg << 15); 916 917 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 918 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 919 } 920 921 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 922 { 923 if (rtl_ocp_reg_failure(reg)) 924 return; 925 926 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 927 } 928 929 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 930 { 931 unsigned long flags; 932 933 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 934 __r8168_mac_ocp_write(tp, reg, data); 935 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 936 } 937 938 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 939 { 940 if (rtl_ocp_reg_failure(reg)) 941 return 0; 942 943 RTL_W32(tp, OCPDR, reg << 15); 944 945 return RTL_R32(tp, OCPDR); 946 } 947 948 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 949 { 950 unsigned long flags; 951 u16 val; 952 953 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 954 val = __r8168_mac_ocp_read(tp, reg); 955 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 956 957 return val; 958 } 959 960 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 961 u16 set) 962 { 963 unsigned long flags; 964 u16 data; 965 966 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 967 data = __r8168_mac_ocp_read(tp, reg); 968 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 969 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 970 } 971 972 /* Work around a hw issue with RTL8168g PHY, the quirk disables 973 * PHY MCU interrupts before PHY power-down. 974 */ 975 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 976 { 977 switch (tp->mac_version) { 978 case RTL_GIGA_MAC_VER_40: 979 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 980 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 981 else 982 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 983 break; 984 default: 985 break; 986 } 987 }; 988 989 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 990 { 991 if (reg == 0x1f) { 992 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 993 return; 994 } 995 996 if (tp->ocp_base != OCP_STD_PHY_BASE) 997 reg -= 0x10; 998 999 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1000 rtl8168g_phy_suspend_quirk(tp, value); 1001 1002 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1003 } 1004 1005 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1006 { 1007 if (reg == 0x1f) 1008 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1009 1010 if (tp->ocp_base != OCP_STD_PHY_BASE) 1011 reg -= 0x10; 1012 1013 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1014 } 1015 1016 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1017 { 1018 if (reg == 0x1f) { 1019 tp->ocp_base = value << 4; 1020 return; 1021 } 1022 1023 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1024 } 1025 1026 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1027 { 1028 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1029 } 1030 1031 DECLARE_RTL_COND(rtl_phyar_cond) 1032 { 1033 return RTL_R32(tp, PHYAR) & 0x80000000; 1034 } 1035 1036 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1037 { 1038 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1039 1040 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1041 /* 1042 * According to hardware specs a 20us delay is required after write 1043 * complete indication, but before sending next command. 1044 */ 1045 udelay(20); 1046 } 1047 1048 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1049 { 1050 int value; 1051 1052 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1053 1054 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1055 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1056 1057 /* 1058 * According to hardware specs a 20us delay is required after read 1059 * complete indication, but before sending next command. 1060 */ 1061 udelay(20); 1062 1063 return value; 1064 } 1065 1066 DECLARE_RTL_COND(rtl_ocpar_cond) 1067 { 1068 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1069 } 1070 1071 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1072 1073 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1074 { 1075 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1076 } 1077 1078 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1079 { 1080 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1081 } 1082 1083 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1084 { 1085 r8168dp_2_mdio_start(tp); 1086 1087 r8169_mdio_write(tp, reg, value); 1088 1089 r8168dp_2_mdio_stop(tp); 1090 } 1091 1092 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1093 { 1094 int value; 1095 1096 /* Work around issue with chip reporting wrong PHY ID */ 1097 if (reg == MII_PHYSID2) 1098 return 0xc912; 1099 1100 r8168dp_2_mdio_start(tp); 1101 1102 value = r8169_mdio_read(tp, reg); 1103 1104 r8168dp_2_mdio_stop(tp); 1105 1106 return value; 1107 } 1108 1109 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1110 { 1111 switch (tp->mac_version) { 1112 case RTL_GIGA_MAC_VER_28: 1113 case RTL_GIGA_MAC_VER_31: 1114 r8168dp_2_mdio_write(tp, location, val); 1115 break; 1116 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1117 r8168g_mdio_write(tp, location, val); 1118 break; 1119 default: 1120 r8169_mdio_write(tp, location, val); 1121 break; 1122 } 1123 } 1124 1125 static int rtl_readphy(struct rtl8169_private *tp, int location) 1126 { 1127 switch (tp->mac_version) { 1128 case RTL_GIGA_MAC_VER_28: 1129 case RTL_GIGA_MAC_VER_31: 1130 return r8168dp_2_mdio_read(tp, location); 1131 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1132 return r8168g_mdio_read(tp, location); 1133 default: 1134 return r8169_mdio_read(tp, location); 1135 } 1136 } 1137 1138 DECLARE_RTL_COND(rtl_ephyar_cond) 1139 { 1140 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1141 } 1142 1143 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1144 { 1145 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1146 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1147 1148 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1149 1150 udelay(10); 1151 } 1152 1153 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1154 { 1155 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1156 1157 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1158 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1159 } 1160 1161 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1162 { 1163 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1164 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1165 RTL_R32(tp, OCPDR) : ~0; 1166 } 1167 1168 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1169 { 1170 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1171 } 1172 1173 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1174 u32 data) 1175 { 1176 RTL_W32(tp, OCPDR, data); 1177 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1178 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1179 } 1180 1181 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1182 u32 data) 1183 { 1184 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1185 data, ERIAR_OOB); 1186 } 1187 1188 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1189 { 1190 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1191 1192 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1193 } 1194 1195 #define OOB_CMD_RESET 0x00 1196 #define OOB_CMD_DRIVER_START 0x05 1197 #define OOB_CMD_DRIVER_STOP 0x06 1198 1199 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1200 { 1201 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1202 } 1203 1204 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1205 { 1206 u16 reg; 1207 1208 reg = rtl8168_get_ocp_reg(tp); 1209 1210 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1211 } 1212 1213 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1214 { 1215 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1216 } 1217 1218 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1219 { 1220 return RTL_R8(tp, IBISR0) & 0x20; 1221 } 1222 1223 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1224 { 1225 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1226 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1227 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1228 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1229 } 1230 1231 static void rtl_dash_loop_wait(struct rtl8169_private *tp, 1232 const struct rtl_cond *c, 1233 unsigned long usecs, int n, bool high) 1234 { 1235 if (!tp->dash_enabled) 1236 return; 1237 rtl_loop_wait(tp, c, usecs, n, high); 1238 } 1239 1240 static void rtl_dash_loop_wait_high(struct rtl8169_private *tp, 1241 const struct rtl_cond *c, 1242 unsigned long d, int n) 1243 { 1244 rtl_dash_loop_wait(tp, c, d, n, true); 1245 } 1246 1247 static void rtl_dash_loop_wait_low(struct rtl8169_private *tp, 1248 const struct rtl_cond *c, 1249 unsigned long d, int n) 1250 { 1251 rtl_dash_loop_wait(tp, c, d, n, false); 1252 } 1253 1254 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1255 { 1256 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1257 rtl_dash_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1258 } 1259 1260 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1261 { 1262 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1263 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1264 rtl_dash_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1265 } 1266 1267 static void rtl8168_driver_start(struct rtl8169_private *tp) 1268 { 1269 if (tp->dash_type == RTL_DASH_DP) 1270 rtl8168dp_driver_start(tp); 1271 else 1272 rtl8168ep_driver_start(tp); 1273 } 1274 1275 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1276 { 1277 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1278 rtl_dash_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1279 } 1280 1281 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1282 { 1283 rtl8168ep_stop_cmac(tp); 1284 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1285 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1286 rtl_dash_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1287 } 1288 1289 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1290 { 1291 if (tp->dash_type == RTL_DASH_DP) 1292 rtl8168dp_driver_stop(tp); 1293 else 1294 rtl8168ep_driver_stop(tp); 1295 } 1296 1297 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1298 { 1299 u16 reg = rtl8168_get_ocp_reg(tp); 1300 1301 return r8168dp_ocp_read(tp, reg) & BIT(15); 1302 } 1303 1304 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1305 { 1306 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1307 } 1308 1309 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1310 { 1311 switch (tp->dash_type) { 1312 case RTL_DASH_DP: 1313 return r8168dp_check_dash(tp); 1314 case RTL_DASH_EP: 1315 return r8168ep_check_dash(tp); 1316 default: 1317 return false; 1318 } 1319 } 1320 1321 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1322 { 1323 switch (tp->mac_version) { 1324 case RTL_GIGA_MAC_VER_28: 1325 case RTL_GIGA_MAC_VER_31: 1326 return RTL_DASH_DP; 1327 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1328 return RTL_DASH_EP; 1329 default: 1330 return RTL_DASH_NONE; 1331 } 1332 } 1333 1334 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1335 { 1336 switch (tp->mac_version) { 1337 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1338 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1339 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1340 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1341 if (enable) 1342 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1343 else 1344 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1345 break; 1346 default: 1347 break; 1348 } 1349 } 1350 1351 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1352 { 1353 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1354 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1355 } 1356 1357 DECLARE_RTL_COND(rtl_efusear_cond) 1358 { 1359 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1360 } 1361 1362 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1363 { 1364 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1365 1366 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1367 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1368 } 1369 1370 static u32 rtl_get_events(struct rtl8169_private *tp) 1371 { 1372 if (rtl_is_8125(tp)) 1373 return RTL_R32(tp, IntrStatus_8125); 1374 else 1375 return RTL_R16(tp, IntrStatus); 1376 } 1377 1378 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1379 { 1380 if (rtl_is_8125(tp)) 1381 RTL_W32(tp, IntrStatus_8125, bits); 1382 else 1383 RTL_W16(tp, IntrStatus, bits); 1384 } 1385 1386 static void rtl_irq_disable(struct rtl8169_private *tp) 1387 { 1388 if (rtl_is_8125(tp)) 1389 RTL_W32(tp, IntrMask_8125, 0); 1390 else 1391 RTL_W16(tp, IntrMask, 0); 1392 } 1393 1394 static void rtl_irq_enable(struct rtl8169_private *tp) 1395 { 1396 if (rtl_is_8125(tp)) 1397 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1398 else 1399 RTL_W16(tp, IntrMask, tp->irq_mask); 1400 } 1401 1402 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1403 { 1404 rtl_irq_disable(tp); 1405 rtl_ack_events(tp, 0xffffffff); 1406 rtl_pci_commit(tp); 1407 } 1408 1409 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1410 { 1411 struct phy_device *phydev = tp->phydev; 1412 1413 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1414 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1415 if (phydev->speed == SPEED_1000) { 1416 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1417 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1418 } else if (phydev->speed == SPEED_100) { 1419 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1420 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1421 } else { 1422 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1423 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1424 } 1425 rtl_reset_packet_filter(tp); 1426 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1427 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1428 if (phydev->speed == SPEED_1000) { 1429 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1430 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1431 } else { 1432 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1433 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1434 } 1435 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1436 if (phydev->speed == SPEED_10) { 1437 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1438 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1439 } else { 1440 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1441 } 1442 } 1443 } 1444 1445 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1446 1447 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1448 { 1449 struct rtl8169_private *tp = netdev_priv(dev); 1450 1451 wol->supported = WAKE_ANY; 1452 wol->wolopts = tp->saved_wolopts; 1453 } 1454 1455 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1456 { 1457 static const struct { 1458 u32 opt; 1459 u16 reg; 1460 u8 mask; 1461 } cfg[] = { 1462 { WAKE_PHY, Config3, LinkUp }, 1463 { WAKE_UCAST, Config5, UWF }, 1464 { WAKE_BCAST, Config5, BWF }, 1465 { WAKE_MCAST, Config5, MWF }, 1466 { WAKE_ANY, Config5, LanWake }, 1467 { WAKE_MAGIC, Config3, MagicPacket } 1468 }; 1469 unsigned int i, tmp = ARRAY_SIZE(cfg); 1470 unsigned long flags; 1471 u8 options; 1472 1473 rtl_unlock_config_regs(tp); 1474 1475 if (rtl_is_8168evl_up(tp)) { 1476 tmp--; 1477 if (wolopts & WAKE_MAGIC) 1478 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1479 else 1480 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1481 } else if (rtl_is_8125(tp)) { 1482 tmp--; 1483 if (wolopts & WAKE_MAGIC) 1484 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1485 else 1486 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1487 } 1488 1489 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1490 for (i = 0; i < tmp; i++) { 1491 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1492 if (wolopts & cfg[i].opt) 1493 options |= cfg[i].mask; 1494 RTL_W8(tp, cfg[i].reg, options); 1495 } 1496 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1497 1498 switch (tp->mac_version) { 1499 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1500 options = RTL_R8(tp, Config1) & ~PMEnable; 1501 if (wolopts) 1502 options |= PMEnable; 1503 RTL_W8(tp, Config1, options); 1504 break; 1505 case RTL_GIGA_MAC_VER_34: 1506 case RTL_GIGA_MAC_VER_37: 1507 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1508 if (wolopts) 1509 rtl_mod_config2(tp, 0, PME_SIGNAL); 1510 else 1511 rtl_mod_config2(tp, PME_SIGNAL, 0); 1512 break; 1513 default: 1514 break; 1515 } 1516 1517 rtl_lock_config_regs(tp); 1518 1519 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1520 1521 if (!tp->dash_enabled) { 1522 rtl_set_d3_pll_down(tp, !wolopts); 1523 tp->dev->wol_enabled = wolopts ? 1 : 0; 1524 } 1525 } 1526 1527 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1528 { 1529 struct rtl8169_private *tp = netdev_priv(dev); 1530 1531 if (wol->wolopts & ~WAKE_ANY) 1532 return -EINVAL; 1533 1534 tp->saved_wolopts = wol->wolopts; 1535 __rtl8169_set_wol(tp, tp->saved_wolopts); 1536 1537 return 0; 1538 } 1539 1540 static void rtl8169_get_drvinfo(struct net_device *dev, 1541 struct ethtool_drvinfo *info) 1542 { 1543 struct rtl8169_private *tp = netdev_priv(dev); 1544 struct rtl_fw *rtl_fw = tp->rtl_fw; 1545 1546 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1547 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1548 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1549 if (rtl_fw) 1550 strscpy(info->fw_version, rtl_fw->version, 1551 sizeof(info->fw_version)); 1552 } 1553 1554 static int rtl8169_get_regs_len(struct net_device *dev) 1555 { 1556 return R8169_REGS_SIZE; 1557 } 1558 1559 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1560 netdev_features_t features) 1561 { 1562 struct rtl8169_private *tp = netdev_priv(dev); 1563 1564 if (dev->mtu > TD_MSS_MAX) 1565 features &= ~NETIF_F_ALL_TSO; 1566 1567 if (dev->mtu > ETH_DATA_LEN && 1568 tp->mac_version > RTL_GIGA_MAC_VER_06) 1569 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1570 1571 return features; 1572 } 1573 1574 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1575 netdev_features_t features) 1576 { 1577 u32 rx_config = RTL_R32(tp, RxConfig); 1578 1579 if (features & NETIF_F_RXALL) 1580 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1581 else 1582 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1583 1584 if (rtl_is_8125(tp)) { 1585 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1586 rx_config |= RX_VLAN_8125; 1587 else 1588 rx_config &= ~RX_VLAN_8125; 1589 } 1590 1591 RTL_W32(tp, RxConfig, rx_config); 1592 } 1593 1594 static int rtl8169_set_features(struct net_device *dev, 1595 netdev_features_t features) 1596 { 1597 struct rtl8169_private *tp = netdev_priv(dev); 1598 1599 rtl_set_rx_config_features(tp, features); 1600 1601 if (features & NETIF_F_RXCSUM) 1602 tp->cp_cmd |= RxChkSum; 1603 else 1604 tp->cp_cmd &= ~RxChkSum; 1605 1606 if (!rtl_is_8125(tp)) { 1607 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1608 tp->cp_cmd |= RxVlan; 1609 else 1610 tp->cp_cmd &= ~RxVlan; 1611 } 1612 1613 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1614 rtl_pci_commit(tp); 1615 1616 return 0; 1617 } 1618 1619 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1620 { 1621 return (skb_vlan_tag_present(skb)) ? 1622 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1623 } 1624 1625 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1626 { 1627 u32 opts2 = le32_to_cpu(desc->opts2); 1628 1629 if (opts2 & RxVlanTag) 1630 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1631 } 1632 1633 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1634 void *p) 1635 { 1636 struct rtl8169_private *tp = netdev_priv(dev); 1637 u32 __iomem *data = tp->mmio_addr; 1638 u32 *dw = p; 1639 int i; 1640 1641 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1642 memcpy_fromio(dw++, data++, 4); 1643 } 1644 1645 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1646 "tx_packets", 1647 "rx_packets", 1648 "tx_errors", 1649 "rx_errors", 1650 "rx_missed", 1651 "align_errors", 1652 "tx_single_collisions", 1653 "tx_multi_collisions", 1654 "unicast", 1655 "broadcast", 1656 "multicast", 1657 "tx_aborted", 1658 "tx_underrun", 1659 }; 1660 1661 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1662 { 1663 switch (sset) { 1664 case ETH_SS_STATS: 1665 return ARRAY_SIZE(rtl8169_gstrings); 1666 default: 1667 return -EOPNOTSUPP; 1668 } 1669 } 1670 1671 DECLARE_RTL_COND(rtl_counters_cond) 1672 { 1673 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1674 } 1675 1676 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1677 { 1678 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1679 1680 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1681 rtl_pci_commit(tp); 1682 RTL_W32(tp, CounterAddrLow, cmd); 1683 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1684 1685 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1686 } 1687 1688 static void rtl8169_update_counters(struct rtl8169_private *tp) 1689 { 1690 u8 val = RTL_R8(tp, ChipCmd); 1691 1692 /* 1693 * Some chips are unable to dump tally counters when the receiver 1694 * is disabled. If 0xff chip may be in a PCI power-save state. 1695 */ 1696 if (val & CmdRxEnb && val != 0xff) 1697 rtl8169_do_counters(tp, CounterDump); 1698 } 1699 1700 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1701 { 1702 struct rtl8169_counters *counters = tp->counters; 1703 1704 /* 1705 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1706 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1707 * reset by a power cycle, while the counter values collected by the 1708 * driver are reset at every driver unload/load cycle. 1709 * 1710 * To make sure the HW values returned by @get_stats64 match the SW 1711 * values, we collect the initial values at first open(*) and use them 1712 * as offsets to normalize the values returned by @get_stats64. 1713 * 1714 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1715 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1716 * set at open time by rtl_hw_start. 1717 */ 1718 1719 if (tp->tc_offset.inited) 1720 return; 1721 1722 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1723 rtl8169_do_counters(tp, CounterReset); 1724 } else { 1725 rtl8169_update_counters(tp); 1726 tp->tc_offset.tx_errors = counters->tx_errors; 1727 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1728 tp->tc_offset.tx_aborted = counters->tx_aborted; 1729 tp->tc_offset.rx_missed = counters->rx_missed; 1730 } 1731 1732 tp->tc_offset.inited = true; 1733 } 1734 1735 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1736 struct ethtool_stats *stats, u64 *data) 1737 { 1738 struct rtl8169_private *tp = netdev_priv(dev); 1739 struct rtl8169_counters *counters; 1740 1741 counters = tp->counters; 1742 rtl8169_update_counters(tp); 1743 1744 data[0] = le64_to_cpu(counters->tx_packets); 1745 data[1] = le64_to_cpu(counters->rx_packets); 1746 data[2] = le64_to_cpu(counters->tx_errors); 1747 data[3] = le32_to_cpu(counters->rx_errors); 1748 data[4] = le16_to_cpu(counters->rx_missed); 1749 data[5] = le16_to_cpu(counters->align_errors); 1750 data[6] = le32_to_cpu(counters->tx_one_collision); 1751 data[7] = le32_to_cpu(counters->tx_multi_collision); 1752 data[8] = le64_to_cpu(counters->rx_unicast); 1753 data[9] = le64_to_cpu(counters->rx_broadcast); 1754 data[10] = le32_to_cpu(counters->rx_multicast); 1755 data[11] = le16_to_cpu(counters->tx_aborted); 1756 data[12] = le16_to_cpu(counters->tx_underrun); 1757 } 1758 1759 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1760 { 1761 switch(stringset) { 1762 case ETH_SS_STATS: 1763 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1764 break; 1765 } 1766 } 1767 1768 /* 1769 * Interrupt coalescing 1770 * 1771 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1772 * > 8169, 8168 and 810x line of chipsets 1773 * 1774 * 8169, 8168, and 8136(810x) serial chipsets support it. 1775 * 1776 * > 2 - the Tx timer unit at gigabit speed 1777 * 1778 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1779 * (0xe0) bit 1 and bit 0. 1780 * 1781 * For 8169 1782 * bit[1:0] \ speed 1000M 100M 10M 1783 * 0 0 320ns 2.56us 40.96us 1784 * 0 1 2.56us 20.48us 327.7us 1785 * 1 0 5.12us 40.96us 655.4us 1786 * 1 1 10.24us 81.92us 1.31ms 1787 * 1788 * For the other 1789 * bit[1:0] \ speed 1000M 100M 10M 1790 * 0 0 5us 2.56us 40.96us 1791 * 0 1 40us 20.48us 327.7us 1792 * 1 0 80us 40.96us 655.4us 1793 * 1 1 160us 81.92us 1.31ms 1794 */ 1795 1796 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1797 struct rtl_coalesce_info { 1798 u32 speed; 1799 u32 scale_nsecs[4]; 1800 }; 1801 1802 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1803 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1804 1805 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1806 { SPEED_1000, COALESCE_DELAY(320) }, 1807 { SPEED_100, COALESCE_DELAY(2560) }, 1808 { SPEED_10, COALESCE_DELAY(40960) }, 1809 { 0 }, 1810 }; 1811 1812 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1813 { SPEED_1000, COALESCE_DELAY(5000) }, 1814 { SPEED_100, COALESCE_DELAY(2560) }, 1815 { SPEED_10, COALESCE_DELAY(40960) }, 1816 { 0 }, 1817 }; 1818 #undef COALESCE_DELAY 1819 1820 /* get rx/tx scale vector corresponding to current speed */ 1821 static const struct rtl_coalesce_info * 1822 rtl_coalesce_info(struct rtl8169_private *tp) 1823 { 1824 const struct rtl_coalesce_info *ci; 1825 1826 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1827 ci = rtl_coalesce_info_8169; 1828 else 1829 ci = rtl_coalesce_info_8168_8136; 1830 1831 /* if speed is unknown assume highest one */ 1832 if (tp->phydev->speed == SPEED_UNKNOWN) 1833 return ci; 1834 1835 for (; ci->speed; ci++) { 1836 if (tp->phydev->speed == ci->speed) 1837 return ci; 1838 } 1839 1840 return ERR_PTR(-ELNRNG); 1841 } 1842 1843 static int rtl_get_coalesce(struct net_device *dev, 1844 struct ethtool_coalesce *ec, 1845 struct kernel_ethtool_coalesce *kernel_coal, 1846 struct netlink_ext_ack *extack) 1847 { 1848 struct rtl8169_private *tp = netdev_priv(dev); 1849 const struct rtl_coalesce_info *ci; 1850 u32 scale, c_us, c_fr; 1851 u16 intrmit; 1852 1853 if (rtl_is_8125(tp)) 1854 return -EOPNOTSUPP; 1855 1856 memset(ec, 0, sizeof(*ec)); 1857 1858 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1859 ci = rtl_coalesce_info(tp); 1860 if (IS_ERR(ci)) 1861 return PTR_ERR(ci); 1862 1863 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1864 1865 intrmit = RTL_R16(tp, IntrMitigate); 1866 1867 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1868 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1869 1870 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1871 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1872 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1873 1874 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1875 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1876 1877 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1878 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1879 1880 return 0; 1881 } 1882 1883 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1884 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1885 u16 *cp01) 1886 { 1887 const struct rtl_coalesce_info *ci; 1888 u16 i; 1889 1890 ci = rtl_coalesce_info(tp); 1891 if (IS_ERR(ci)) 1892 return PTR_ERR(ci); 1893 1894 for (i = 0; i < 4; i++) { 1895 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1896 *cp01 = i; 1897 return ci->scale_nsecs[i]; 1898 } 1899 } 1900 1901 return -ERANGE; 1902 } 1903 1904 static int rtl_set_coalesce(struct net_device *dev, 1905 struct ethtool_coalesce *ec, 1906 struct kernel_ethtool_coalesce *kernel_coal, 1907 struct netlink_ext_ack *extack) 1908 { 1909 struct rtl8169_private *tp = netdev_priv(dev); 1910 u32 tx_fr = ec->tx_max_coalesced_frames; 1911 u32 rx_fr = ec->rx_max_coalesced_frames; 1912 u32 coal_usec_max, units; 1913 u16 w = 0, cp01 = 0; 1914 int scale; 1915 1916 if (rtl_is_8125(tp)) 1917 return -EOPNOTSUPP; 1918 1919 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1920 return -ERANGE; 1921 1922 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1923 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1924 if (scale < 0) 1925 return scale; 1926 1927 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1928 * not only when usecs=0 because of e.g. the following scenario: 1929 * 1930 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1931 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1932 * - then user does `ethtool -C eth0 rx-usecs 100` 1933 * 1934 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1935 * if we want to ignore rx_frames then it has to be set to 0. 1936 */ 1937 if (rx_fr == 1) 1938 rx_fr = 0; 1939 if (tx_fr == 1) 1940 tx_fr = 0; 1941 1942 /* HW requires time limit to be set if frame limit is set */ 1943 if ((tx_fr && !ec->tx_coalesce_usecs) || 1944 (rx_fr && !ec->rx_coalesce_usecs)) 1945 return -EINVAL; 1946 1947 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1948 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1949 1950 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1951 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1952 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1953 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1954 1955 RTL_W16(tp, IntrMitigate, w); 1956 1957 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1958 if (rtl_is_8168evl_up(tp)) { 1959 if (!rx_fr && !tx_fr) 1960 /* disable packet counter */ 1961 tp->cp_cmd |= PktCntrDisable; 1962 else 1963 tp->cp_cmd &= ~PktCntrDisable; 1964 } 1965 1966 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1967 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1968 rtl_pci_commit(tp); 1969 1970 return 0; 1971 } 1972 1973 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1974 { 1975 struct rtl8169_private *tp = netdev_priv(dev); 1976 1977 if (!rtl_supports_eee(tp)) 1978 return -EOPNOTSUPP; 1979 1980 return phy_ethtool_get_eee(tp->phydev, data); 1981 } 1982 1983 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1984 { 1985 struct rtl8169_private *tp = netdev_priv(dev); 1986 int ret; 1987 1988 if (!rtl_supports_eee(tp)) 1989 return -EOPNOTSUPP; 1990 1991 ret = phy_ethtool_set_eee(tp->phydev, data); 1992 1993 if (!ret) 1994 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1995 MDIO_AN_EEE_ADV); 1996 return ret; 1997 } 1998 1999 static void rtl8169_get_ringparam(struct net_device *dev, 2000 struct ethtool_ringparam *data, 2001 struct kernel_ethtool_ringparam *kernel_data, 2002 struct netlink_ext_ack *extack) 2003 { 2004 data->rx_max_pending = NUM_RX_DESC; 2005 data->rx_pending = NUM_RX_DESC; 2006 data->tx_max_pending = NUM_TX_DESC; 2007 data->tx_pending = NUM_TX_DESC; 2008 } 2009 2010 static void rtl8169_get_pauseparam(struct net_device *dev, 2011 struct ethtool_pauseparam *data) 2012 { 2013 struct rtl8169_private *tp = netdev_priv(dev); 2014 bool tx_pause, rx_pause; 2015 2016 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2017 2018 data->autoneg = tp->phydev->autoneg; 2019 data->tx_pause = tx_pause ? 1 : 0; 2020 data->rx_pause = rx_pause ? 1 : 0; 2021 } 2022 2023 static int rtl8169_set_pauseparam(struct net_device *dev, 2024 struct ethtool_pauseparam *data) 2025 { 2026 struct rtl8169_private *tp = netdev_priv(dev); 2027 2028 if (dev->mtu > ETH_DATA_LEN) 2029 return -EOPNOTSUPP; 2030 2031 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2032 2033 return 0; 2034 } 2035 2036 static const struct ethtool_ops rtl8169_ethtool_ops = { 2037 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2038 ETHTOOL_COALESCE_MAX_FRAMES, 2039 .get_drvinfo = rtl8169_get_drvinfo, 2040 .get_regs_len = rtl8169_get_regs_len, 2041 .get_link = ethtool_op_get_link, 2042 .get_coalesce = rtl_get_coalesce, 2043 .set_coalesce = rtl_set_coalesce, 2044 .get_regs = rtl8169_get_regs, 2045 .get_wol = rtl8169_get_wol, 2046 .set_wol = rtl8169_set_wol, 2047 .get_strings = rtl8169_get_strings, 2048 .get_sset_count = rtl8169_get_sset_count, 2049 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2050 .get_ts_info = ethtool_op_get_ts_info, 2051 .nway_reset = phy_ethtool_nway_reset, 2052 .get_eee = rtl8169_get_eee, 2053 .set_eee = rtl8169_set_eee, 2054 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2055 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2056 .get_ringparam = rtl8169_get_ringparam, 2057 .get_pauseparam = rtl8169_get_pauseparam, 2058 .set_pauseparam = rtl8169_set_pauseparam, 2059 }; 2060 2061 static void rtl_enable_eee(struct rtl8169_private *tp) 2062 { 2063 struct phy_device *phydev = tp->phydev; 2064 int adv; 2065 2066 /* respect EEE advertisement the user may have set */ 2067 if (tp->eee_adv >= 0) 2068 adv = tp->eee_adv; 2069 else 2070 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2071 2072 if (adv >= 0) 2073 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2074 } 2075 2076 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2077 { 2078 /* 2079 * The driver currently handles the 8168Bf and the 8168Be identically 2080 * but they can be identified more specifically through the test below 2081 * if needed: 2082 * 2083 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2084 * 2085 * Same thing for the 8101Eb and the 8101Ec: 2086 * 2087 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2088 */ 2089 static const struct rtl_mac_info { 2090 u16 mask; 2091 u16 val; 2092 enum mac_version ver; 2093 } mac_info[] = { 2094 /* 8125B family. */ 2095 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2096 2097 /* 8125A family. */ 2098 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2099 /* It seems only XID 609 made it to the mass market. 2100 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2101 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2102 */ 2103 2104 /* RTL8117 */ 2105 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2106 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2107 2108 /* 8168EP family. */ 2109 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2110 /* It seems this chip version never made it to 2111 * the wild. Let's disable detection. 2112 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2113 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2114 */ 2115 2116 /* 8168H family. */ 2117 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2118 /* It seems this chip version never made it to 2119 * the wild. Let's disable detection. 2120 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2121 */ 2122 2123 /* 8168G family. */ 2124 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2125 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2126 /* It seems this chip version never made it to 2127 * the wild. Let's disable detection. 2128 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2129 */ 2130 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2131 2132 /* 8168F family. */ 2133 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2134 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2135 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2136 2137 /* 8168E family. */ 2138 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2139 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2140 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2141 2142 /* 8168D family. */ 2143 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2144 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2145 2146 /* 8168DP family. */ 2147 /* It seems this early RTL8168dp version never made it to 2148 * the wild. Support has been removed. 2149 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2150 */ 2151 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2152 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2153 2154 /* 8168C family. */ 2155 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2156 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2157 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2158 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2159 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2160 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2161 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2162 2163 /* 8168B family. */ 2164 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2165 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2166 2167 /* 8101 family. */ 2168 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2169 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2170 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2171 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2172 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2173 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2174 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2175 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2176 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2177 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2178 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2179 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2180 2181 /* 8110 family. */ 2182 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2183 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2184 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2185 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2186 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2187 2188 /* Catch-all */ 2189 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2190 }; 2191 const struct rtl_mac_info *p = mac_info; 2192 enum mac_version ver; 2193 2194 while ((xid & p->mask) != p->val) 2195 p++; 2196 ver = p->ver; 2197 2198 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2199 if (ver == RTL_GIGA_MAC_VER_42) 2200 ver = RTL_GIGA_MAC_VER_43; 2201 else if (ver == RTL_GIGA_MAC_VER_46) 2202 ver = RTL_GIGA_MAC_VER_48; 2203 } 2204 2205 return ver; 2206 } 2207 2208 static void rtl_release_firmware(struct rtl8169_private *tp) 2209 { 2210 if (tp->rtl_fw) { 2211 rtl_fw_release_firmware(tp->rtl_fw); 2212 kfree(tp->rtl_fw); 2213 tp->rtl_fw = NULL; 2214 } 2215 } 2216 2217 void r8169_apply_firmware(struct rtl8169_private *tp) 2218 { 2219 int val; 2220 2221 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2222 if (tp->rtl_fw) { 2223 rtl_fw_write_firmware(tp, tp->rtl_fw); 2224 /* At least one firmware doesn't reset tp->ocp_base. */ 2225 tp->ocp_base = OCP_STD_PHY_BASE; 2226 2227 /* PHY soft reset may still be in progress */ 2228 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2229 !(val & BMCR_RESET), 2230 50000, 600000, true); 2231 } 2232 } 2233 2234 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2235 { 2236 /* Adjust EEE LED frequency */ 2237 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2238 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2239 2240 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2241 } 2242 2243 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2244 { 2245 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2246 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2247 } 2248 2249 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2250 { 2251 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2252 } 2253 2254 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2255 { 2256 rtl8125_set_eee_txidle_timer(tp); 2257 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2258 } 2259 2260 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2261 { 2262 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2263 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2264 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2265 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2266 } 2267 2268 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2269 { 2270 u16 data1, data2, ioffset; 2271 2272 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2273 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2274 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2275 2276 ioffset = (data2 >> 1) & 0x7ff8; 2277 ioffset |= data2 & 0x0007; 2278 if (data1 & BIT(7)) 2279 ioffset |= BIT(15); 2280 2281 return ioffset; 2282 } 2283 2284 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2285 { 2286 set_bit(flag, tp->wk.flags); 2287 schedule_work(&tp->wk.work); 2288 } 2289 2290 static void rtl8169_init_phy(struct rtl8169_private *tp) 2291 { 2292 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2293 2294 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2295 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2296 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2297 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2298 RTL_W8(tp, 0x82, 0x01); 2299 } 2300 2301 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2302 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2303 tp->pci_dev->subsystem_device == 0xe000) 2304 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2305 2306 /* We may have called phy_speed_down before */ 2307 phy_speed_up(tp->phydev); 2308 2309 if (rtl_supports_eee(tp)) 2310 rtl_enable_eee(tp); 2311 2312 genphy_soft_reset(tp->phydev); 2313 } 2314 2315 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2316 { 2317 rtl_unlock_config_regs(tp); 2318 2319 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2320 rtl_pci_commit(tp); 2321 2322 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2323 rtl_pci_commit(tp); 2324 2325 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2326 rtl_rar_exgmac_set(tp, addr); 2327 2328 rtl_lock_config_regs(tp); 2329 } 2330 2331 static int rtl_set_mac_address(struct net_device *dev, void *p) 2332 { 2333 struct rtl8169_private *tp = netdev_priv(dev); 2334 int ret; 2335 2336 ret = eth_mac_addr(dev, p); 2337 if (ret) 2338 return ret; 2339 2340 rtl_rar_set(tp, dev->dev_addr); 2341 2342 return 0; 2343 } 2344 2345 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2346 { 2347 switch (tp->mac_version) { 2348 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2349 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2350 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2351 break; 2352 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2353 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2354 case RTL_GIGA_MAC_VER_38: 2355 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2356 break; 2357 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2358 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2359 break; 2360 case RTL_GIGA_MAC_VER_61: 2361 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2362 break; 2363 case RTL_GIGA_MAC_VER_63: 2364 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2365 RX_PAUSE_SLOT_ON); 2366 break; 2367 default: 2368 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2369 break; 2370 } 2371 } 2372 2373 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2374 { 2375 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2376 } 2377 2378 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2379 { 2380 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2381 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2382 } 2383 2384 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2385 { 2386 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2387 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2388 } 2389 2390 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2391 { 2392 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2393 } 2394 2395 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2396 { 2397 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2398 } 2399 2400 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2401 { 2402 RTL_W8(tp, MaxTxPacketSize, 0x24); 2403 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2404 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2405 } 2406 2407 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2408 { 2409 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2410 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2411 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2412 } 2413 2414 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2415 { 2416 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2417 } 2418 2419 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2420 { 2421 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2422 } 2423 2424 static void rtl_jumbo_config(struct rtl8169_private *tp) 2425 { 2426 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2427 int readrq = 4096; 2428 2429 rtl_unlock_config_regs(tp); 2430 switch (tp->mac_version) { 2431 case RTL_GIGA_MAC_VER_17: 2432 if (jumbo) { 2433 readrq = 512; 2434 r8168b_1_hw_jumbo_enable(tp); 2435 } else { 2436 r8168b_1_hw_jumbo_disable(tp); 2437 } 2438 break; 2439 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2440 if (jumbo) { 2441 readrq = 512; 2442 r8168c_hw_jumbo_enable(tp); 2443 } else { 2444 r8168c_hw_jumbo_disable(tp); 2445 } 2446 break; 2447 case RTL_GIGA_MAC_VER_28: 2448 if (jumbo) 2449 r8168dp_hw_jumbo_enable(tp); 2450 else 2451 r8168dp_hw_jumbo_disable(tp); 2452 break; 2453 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2454 if (jumbo) 2455 r8168e_hw_jumbo_enable(tp); 2456 else 2457 r8168e_hw_jumbo_disable(tp); 2458 break; 2459 default: 2460 break; 2461 } 2462 rtl_lock_config_regs(tp); 2463 2464 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2465 pcie_set_readrq(tp->pci_dev, readrq); 2466 2467 /* Chip doesn't support pause in jumbo mode */ 2468 if (jumbo) { 2469 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2470 tp->phydev->advertising); 2471 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2472 tp->phydev->advertising); 2473 phy_start_aneg(tp->phydev); 2474 } 2475 } 2476 2477 DECLARE_RTL_COND(rtl_chipcmd_cond) 2478 { 2479 return RTL_R8(tp, ChipCmd) & CmdReset; 2480 } 2481 2482 static void rtl_hw_reset(struct rtl8169_private *tp) 2483 { 2484 RTL_W8(tp, ChipCmd, CmdReset); 2485 2486 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2487 } 2488 2489 static void rtl_request_firmware(struct rtl8169_private *tp) 2490 { 2491 struct rtl_fw *rtl_fw; 2492 2493 /* firmware loaded already or no firmware available */ 2494 if (tp->rtl_fw || !tp->fw_name) 2495 return; 2496 2497 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2498 if (!rtl_fw) 2499 return; 2500 2501 rtl_fw->phy_write = rtl_writephy; 2502 rtl_fw->phy_read = rtl_readphy; 2503 rtl_fw->mac_mcu_write = mac_mcu_write; 2504 rtl_fw->mac_mcu_read = mac_mcu_read; 2505 rtl_fw->fw_name = tp->fw_name; 2506 rtl_fw->dev = tp_to_dev(tp); 2507 2508 if (rtl_fw_request_firmware(rtl_fw)) 2509 kfree(rtl_fw); 2510 else 2511 tp->rtl_fw = rtl_fw; 2512 } 2513 2514 static void rtl_rx_close(struct rtl8169_private *tp) 2515 { 2516 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2517 } 2518 2519 DECLARE_RTL_COND(rtl_npq_cond) 2520 { 2521 return RTL_R8(tp, TxPoll) & NPQ; 2522 } 2523 2524 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2525 { 2526 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2527 } 2528 2529 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2530 { 2531 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2532 } 2533 2534 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2535 { 2536 /* IntrMitigate has new functionality on RTL8125 */ 2537 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2538 } 2539 2540 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2541 { 2542 switch (tp->mac_version) { 2543 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2544 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2545 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2546 break; 2547 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2548 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2549 break; 2550 case RTL_GIGA_MAC_VER_63: 2551 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2552 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2553 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2554 break; 2555 default: 2556 break; 2557 } 2558 } 2559 2560 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2561 { 2562 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2563 } 2564 2565 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2566 { 2567 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2568 fsleep(2000); 2569 rtl_wait_txrx_fifo_empty(tp); 2570 } 2571 2572 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2573 { 2574 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2575 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2576 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2577 2578 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2579 rtl_disable_rxdvgate(tp); 2580 } 2581 2582 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2583 { 2584 if (tp->dash_enabled) 2585 return; 2586 2587 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2588 tp->mac_version == RTL_GIGA_MAC_VER_33) 2589 rtl_ephy_write(tp, 0x19, 0xff64); 2590 2591 if (device_may_wakeup(tp_to_dev(tp))) { 2592 phy_speed_down(tp->phydev, false); 2593 rtl_wol_enable_rx(tp); 2594 } 2595 } 2596 2597 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2598 { 2599 u32 val = TX_DMA_BURST << TxDMAShift | 2600 InterFrameGap << TxInterFrameGapShift; 2601 2602 if (rtl_is_8168evl_up(tp)) 2603 val |= TXCFG_AUTO_FIFO; 2604 2605 RTL_W32(tp, TxConfig, val); 2606 } 2607 2608 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2609 { 2610 /* Low hurts. Let's disable the filtering. */ 2611 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2612 } 2613 2614 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2615 { 2616 /* 2617 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2618 * register to be written before TxDescAddrLow to work. 2619 * Switching from MMIO to I/O access fixes the issue as well. 2620 */ 2621 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2622 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2623 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2624 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2625 } 2626 2627 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2628 { 2629 u32 val; 2630 2631 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2632 val = 0x000fff00; 2633 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2634 val = 0x00ffff00; 2635 else 2636 return; 2637 2638 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2639 val |= 0xff; 2640 2641 RTL_W32(tp, 0x7c, val); 2642 } 2643 2644 static void rtl_set_rx_mode(struct net_device *dev) 2645 { 2646 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2647 /* Multicast hash filter */ 2648 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2649 struct rtl8169_private *tp = netdev_priv(dev); 2650 u32 tmp; 2651 2652 if (dev->flags & IFF_PROMISC) { 2653 rx_mode |= AcceptAllPhys; 2654 } else if (!(dev->flags & IFF_MULTICAST)) { 2655 rx_mode &= ~AcceptMulticast; 2656 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2657 dev->flags & IFF_ALLMULTI || 2658 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2659 /* accept all multicasts */ 2660 } else if (netdev_mc_empty(dev)) { 2661 rx_mode &= ~AcceptMulticast; 2662 } else { 2663 struct netdev_hw_addr *ha; 2664 2665 mc_filter[1] = mc_filter[0] = 0; 2666 netdev_for_each_mc_addr(ha, dev) { 2667 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2668 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2669 } 2670 2671 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2672 tmp = mc_filter[0]; 2673 mc_filter[0] = swab32(mc_filter[1]); 2674 mc_filter[1] = swab32(tmp); 2675 } 2676 } 2677 2678 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2679 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2680 2681 tmp = RTL_R32(tp, RxConfig); 2682 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2683 } 2684 2685 DECLARE_RTL_COND(rtl_csiar_cond) 2686 { 2687 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2688 } 2689 2690 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2691 { 2692 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2693 2694 RTL_W32(tp, CSIDR, value); 2695 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2696 CSIAR_BYTE_ENABLE | func << 16); 2697 2698 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2699 } 2700 2701 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2702 { 2703 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2704 2705 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2706 CSIAR_BYTE_ENABLE); 2707 2708 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2709 RTL_R32(tp, CSIDR) : ~0; 2710 } 2711 2712 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2713 { 2714 struct pci_dev *pdev = tp->pci_dev; 2715 u32 csi; 2716 2717 /* According to Realtek the value at config space address 0x070f 2718 * controls the L0s/L1 entrance latency. We try standard ECAM access 2719 * first and if it fails fall back to CSI. 2720 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2721 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2722 */ 2723 if (pdev->cfg_size > 0x070f && 2724 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2725 return; 2726 2727 netdev_notice_once(tp->dev, 2728 "No native access to PCI extended config space, falling back to CSI\n"); 2729 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2730 rtl_csi_write(tp, 0x070c, csi | val << 24); 2731 } 2732 2733 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2734 { 2735 /* L0 7us, L1 16us */ 2736 rtl_set_aspm_entry_latency(tp, 0x27); 2737 } 2738 2739 struct ephy_info { 2740 unsigned int offset; 2741 u16 mask; 2742 u16 bits; 2743 }; 2744 2745 static void __rtl_ephy_init(struct rtl8169_private *tp, 2746 const struct ephy_info *e, int len) 2747 { 2748 u16 w; 2749 2750 while (len-- > 0) { 2751 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2752 rtl_ephy_write(tp, e->offset, w); 2753 e++; 2754 } 2755 } 2756 2757 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2758 2759 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2760 { 2761 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2762 PCI_EXP_LNKCTL_CLKREQ_EN); 2763 } 2764 2765 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2766 { 2767 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2768 PCI_EXP_LNKCTL_CLKREQ_EN); 2769 } 2770 2771 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2772 { 2773 /* work around an issue when PCI reset occurs during L2/L3 state */ 2774 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2775 } 2776 2777 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2778 { 2779 /* Bits control which events trigger ASPM L1 exit: 2780 * Bit 12: rxdv 2781 * Bit 11: ltr_msg 2782 * Bit 10: txdma_poll 2783 * Bit 9: xadm 2784 * Bit 8: pktavi 2785 * Bit 7: txpla 2786 */ 2787 switch (tp->mac_version) { 2788 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2789 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2790 break; 2791 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2792 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2793 break; 2794 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2795 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2796 break; 2797 default: 2798 break; 2799 } 2800 } 2801 2802 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2803 { 2804 switch (tp->mac_version) { 2805 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2806 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2807 break; 2808 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2809 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2810 break; 2811 default: 2812 break; 2813 } 2814 } 2815 2816 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2817 { 2818 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2819 return; 2820 2821 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2822 if (enable && tp->aspm_manageable) { 2823 /* On these chip versions ASPM can even harm 2824 * bus communication of other PCI devices. 2825 */ 2826 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2827 tp->mac_version == RTL_GIGA_MAC_VER_43) 2828 return; 2829 2830 rtl_mod_config5(tp, 0, ASPM_en); 2831 rtl_mod_config2(tp, 0, ClkReqEn); 2832 2833 switch (tp->mac_version) { 2834 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2835 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2836 /* reset ephy tx/rx disable timer */ 2837 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2838 /* chip can trigger L1.2 */ 2839 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2840 break; 2841 default: 2842 break; 2843 } 2844 } else { 2845 switch (tp->mac_version) { 2846 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2847 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2848 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2849 break; 2850 default: 2851 break; 2852 } 2853 2854 rtl_mod_config2(tp, ClkReqEn, 0); 2855 rtl_mod_config5(tp, ASPM_en, 0); 2856 } 2857 } 2858 2859 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2860 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2861 { 2862 /* Usage of dynamic vs. static FIFO is controlled by bit 2863 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2864 */ 2865 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2866 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2867 } 2868 2869 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2870 u8 low, u8 high) 2871 { 2872 /* FIFO thresholds for pause flow control */ 2873 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2874 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2875 } 2876 2877 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2878 { 2879 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2880 } 2881 2882 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2883 { 2884 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2885 2886 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2887 2888 rtl_disable_clock_request(tp); 2889 } 2890 2891 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2892 { 2893 static const struct ephy_info e_info_8168cp[] = { 2894 { 0x01, 0, 0x0001 }, 2895 { 0x02, 0x0800, 0x1000 }, 2896 { 0x03, 0, 0x0042 }, 2897 { 0x06, 0x0080, 0x0000 }, 2898 { 0x07, 0, 0x2000 } 2899 }; 2900 2901 rtl_set_def_aspm_entry_latency(tp); 2902 2903 rtl_ephy_init(tp, e_info_8168cp); 2904 2905 __rtl_hw_start_8168cp(tp); 2906 } 2907 2908 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2909 { 2910 rtl_set_def_aspm_entry_latency(tp); 2911 2912 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2913 } 2914 2915 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2916 { 2917 rtl_set_def_aspm_entry_latency(tp); 2918 2919 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2920 2921 /* Magic. */ 2922 RTL_W8(tp, DBG_REG, 0x20); 2923 } 2924 2925 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2926 { 2927 static const struct ephy_info e_info_8168c_1[] = { 2928 { 0x02, 0x0800, 0x1000 }, 2929 { 0x03, 0, 0x0002 }, 2930 { 0x06, 0x0080, 0x0000 } 2931 }; 2932 2933 rtl_set_def_aspm_entry_latency(tp); 2934 2935 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2936 2937 rtl_ephy_init(tp, e_info_8168c_1); 2938 2939 __rtl_hw_start_8168cp(tp); 2940 } 2941 2942 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2943 { 2944 static const struct ephy_info e_info_8168c_2[] = { 2945 { 0x01, 0, 0x0001 }, 2946 { 0x03, 0x0400, 0x0020 } 2947 }; 2948 2949 rtl_set_def_aspm_entry_latency(tp); 2950 2951 rtl_ephy_init(tp, e_info_8168c_2); 2952 2953 __rtl_hw_start_8168cp(tp); 2954 } 2955 2956 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2957 { 2958 rtl_set_def_aspm_entry_latency(tp); 2959 2960 __rtl_hw_start_8168cp(tp); 2961 } 2962 2963 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2964 { 2965 rtl_set_def_aspm_entry_latency(tp); 2966 2967 rtl_disable_clock_request(tp); 2968 } 2969 2970 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2971 { 2972 static const struct ephy_info e_info_8168d_4[] = { 2973 { 0x0b, 0x0000, 0x0048 }, 2974 { 0x19, 0x0020, 0x0050 }, 2975 { 0x0c, 0x0100, 0x0020 }, 2976 { 0x10, 0x0004, 0x0000 }, 2977 }; 2978 2979 rtl_set_def_aspm_entry_latency(tp); 2980 2981 rtl_ephy_init(tp, e_info_8168d_4); 2982 2983 rtl_enable_clock_request(tp); 2984 } 2985 2986 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2987 { 2988 static const struct ephy_info e_info_8168e_1[] = { 2989 { 0x00, 0x0200, 0x0100 }, 2990 { 0x00, 0x0000, 0x0004 }, 2991 { 0x06, 0x0002, 0x0001 }, 2992 { 0x06, 0x0000, 0x0030 }, 2993 { 0x07, 0x0000, 0x2000 }, 2994 { 0x00, 0x0000, 0x0020 }, 2995 { 0x03, 0x5800, 0x2000 }, 2996 { 0x03, 0x0000, 0x0001 }, 2997 { 0x01, 0x0800, 0x1000 }, 2998 { 0x07, 0x0000, 0x4000 }, 2999 { 0x1e, 0x0000, 0x2000 }, 3000 { 0x19, 0xffff, 0xfe6c }, 3001 { 0x0a, 0x0000, 0x0040 } 3002 }; 3003 3004 rtl_set_def_aspm_entry_latency(tp); 3005 3006 rtl_ephy_init(tp, e_info_8168e_1); 3007 3008 rtl_disable_clock_request(tp); 3009 3010 /* Reset tx FIFO pointer */ 3011 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3012 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3013 3014 rtl_mod_config5(tp, Spi_en, 0); 3015 } 3016 3017 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3018 { 3019 static const struct ephy_info e_info_8168e_2[] = { 3020 { 0x09, 0x0000, 0x0080 }, 3021 { 0x19, 0x0000, 0x0224 }, 3022 { 0x00, 0x0000, 0x0004 }, 3023 { 0x0c, 0x3df0, 0x0200 }, 3024 }; 3025 3026 rtl_set_def_aspm_entry_latency(tp); 3027 3028 rtl_ephy_init(tp, e_info_8168e_2); 3029 3030 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3031 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3032 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3033 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3034 rtl_reset_packet_filter(tp); 3035 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3036 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3037 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3038 3039 rtl_disable_clock_request(tp); 3040 3041 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3042 3043 rtl8168_config_eee_mac(tp); 3044 3045 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3046 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3047 rtl_mod_config5(tp, Spi_en, 0); 3048 } 3049 3050 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3051 { 3052 rtl_set_def_aspm_entry_latency(tp); 3053 3054 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3055 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3056 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3057 rtl_reset_packet_filter(tp); 3058 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3059 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3060 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3061 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3062 3063 rtl_disable_clock_request(tp); 3064 3065 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3066 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3067 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3068 rtl_mod_config5(tp, Spi_en, 0); 3069 3070 rtl8168_config_eee_mac(tp); 3071 } 3072 3073 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3074 { 3075 static const struct ephy_info e_info_8168f_1[] = { 3076 { 0x06, 0x00c0, 0x0020 }, 3077 { 0x08, 0x0001, 0x0002 }, 3078 { 0x09, 0x0000, 0x0080 }, 3079 { 0x19, 0x0000, 0x0224 }, 3080 { 0x00, 0x0000, 0x0008 }, 3081 { 0x0c, 0x3df0, 0x0200 }, 3082 }; 3083 3084 rtl_hw_start_8168f(tp); 3085 3086 rtl_ephy_init(tp, e_info_8168f_1); 3087 } 3088 3089 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3090 { 3091 static const struct ephy_info e_info_8168f_1[] = { 3092 { 0x06, 0x00c0, 0x0020 }, 3093 { 0x0f, 0xffff, 0x5200 }, 3094 { 0x19, 0x0000, 0x0224 }, 3095 { 0x00, 0x0000, 0x0008 }, 3096 { 0x0c, 0x3df0, 0x0200 }, 3097 }; 3098 3099 rtl_hw_start_8168f(tp); 3100 rtl_pcie_state_l2l3_disable(tp); 3101 3102 rtl_ephy_init(tp, e_info_8168f_1); 3103 } 3104 3105 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3106 { 3107 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3108 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3109 3110 rtl_set_def_aspm_entry_latency(tp); 3111 3112 rtl_reset_packet_filter(tp); 3113 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3114 3115 rtl_disable_rxdvgate(tp); 3116 3117 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3118 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3119 3120 rtl8168_config_eee_mac(tp); 3121 3122 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3123 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3124 3125 rtl_pcie_state_l2l3_disable(tp); 3126 } 3127 3128 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3129 { 3130 static const struct ephy_info e_info_8168g_1[] = { 3131 { 0x00, 0x0008, 0x0000 }, 3132 { 0x0c, 0x3ff0, 0x0820 }, 3133 { 0x1e, 0x0000, 0x0001 }, 3134 { 0x19, 0x8000, 0x0000 } 3135 }; 3136 3137 rtl_hw_start_8168g(tp); 3138 rtl_ephy_init(tp, e_info_8168g_1); 3139 } 3140 3141 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3142 { 3143 static const struct ephy_info e_info_8168g_2[] = { 3144 { 0x00, 0x0008, 0x0000 }, 3145 { 0x0c, 0x3ff0, 0x0820 }, 3146 { 0x19, 0xffff, 0x7c00 }, 3147 { 0x1e, 0xffff, 0x20eb }, 3148 { 0x0d, 0xffff, 0x1666 }, 3149 { 0x00, 0xffff, 0x10a3 }, 3150 { 0x06, 0xffff, 0xf050 }, 3151 { 0x04, 0x0000, 0x0010 }, 3152 { 0x1d, 0x4000, 0x0000 }, 3153 }; 3154 3155 rtl_hw_start_8168g(tp); 3156 rtl_ephy_init(tp, e_info_8168g_2); 3157 } 3158 3159 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3160 { 3161 static const struct ephy_info e_info_8411_2[] = { 3162 { 0x00, 0x0008, 0x0000 }, 3163 { 0x0c, 0x37d0, 0x0820 }, 3164 { 0x1e, 0x0000, 0x0001 }, 3165 { 0x19, 0x8021, 0x0000 }, 3166 { 0x1e, 0x0000, 0x2000 }, 3167 { 0x0d, 0x0100, 0x0200 }, 3168 { 0x00, 0x0000, 0x0080 }, 3169 { 0x06, 0x0000, 0x0010 }, 3170 { 0x04, 0x0000, 0x0010 }, 3171 { 0x1d, 0x0000, 0x4000 }, 3172 }; 3173 3174 rtl_hw_start_8168g(tp); 3175 3176 rtl_ephy_init(tp, e_info_8411_2); 3177 3178 /* The following Realtek-provided magic fixes an issue with the RX unit 3179 * getting confused after the PHY having been powered-down. 3180 */ 3181 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3182 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3183 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3184 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3185 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3186 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3187 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3188 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3189 mdelay(3); 3190 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3191 3192 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3193 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3194 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3195 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3196 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3197 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3198 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3199 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3200 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3201 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3202 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3203 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3204 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3205 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3206 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3207 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3208 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3209 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3210 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3211 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3212 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3213 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3214 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3215 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3216 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3217 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3218 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3219 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3220 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3221 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3222 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3223 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3224 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3225 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3226 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3227 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3228 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3229 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3230 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3231 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3232 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3233 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3234 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3235 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3236 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3237 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3238 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3239 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3240 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3241 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3242 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3243 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3244 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3245 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3246 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3247 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3248 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3249 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3250 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3251 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3252 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3253 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3254 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3255 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3256 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3257 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3258 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3259 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3260 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3261 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3262 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3263 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3264 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3265 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3266 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3267 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3268 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3269 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3270 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3271 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3272 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3273 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3274 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3275 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3276 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3277 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3278 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3279 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3280 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3281 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3282 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3283 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3284 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3285 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3286 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3287 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3288 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3289 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3290 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3291 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3292 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3293 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3294 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3295 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3296 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3297 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3298 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3299 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3300 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3301 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3302 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3303 3304 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3305 3306 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3307 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3308 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3309 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3310 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3311 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3312 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3313 } 3314 3315 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3316 { 3317 static const struct ephy_info e_info_8168h_1[] = { 3318 { 0x1e, 0x0800, 0x0001 }, 3319 { 0x1d, 0x0000, 0x0800 }, 3320 { 0x05, 0xffff, 0x2089 }, 3321 { 0x06, 0xffff, 0x5881 }, 3322 { 0x04, 0xffff, 0x854a }, 3323 { 0x01, 0xffff, 0x068b } 3324 }; 3325 int rg_saw_cnt; 3326 3327 rtl_ephy_init(tp, e_info_8168h_1); 3328 3329 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3330 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3331 3332 rtl_set_def_aspm_entry_latency(tp); 3333 3334 rtl_reset_packet_filter(tp); 3335 3336 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3337 3338 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3339 3340 rtl_disable_rxdvgate(tp); 3341 3342 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3343 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3344 3345 rtl8168_config_eee_mac(tp); 3346 3347 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3348 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3349 3350 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3351 3352 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3353 3354 rtl_pcie_state_l2l3_disable(tp); 3355 3356 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3357 if (rg_saw_cnt > 0) { 3358 u16 sw_cnt_1ms_ini; 3359 3360 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3361 sw_cnt_1ms_ini &= 0x0fff; 3362 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3363 } 3364 3365 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3366 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3367 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3368 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3369 3370 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3371 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3372 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3373 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3374 } 3375 3376 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3377 { 3378 rtl8168ep_stop_cmac(tp); 3379 3380 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3381 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3382 3383 rtl_set_def_aspm_entry_latency(tp); 3384 3385 rtl_reset_packet_filter(tp); 3386 3387 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3388 3389 rtl_disable_rxdvgate(tp); 3390 3391 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3392 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3393 3394 rtl8168_config_eee_mac(tp); 3395 3396 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3397 3398 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3399 3400 rtl_pcie_state_l2l3_disable(tp); 3401 } 3402 3403 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3404 { 3405 static const struct ephy_info e_info_8168ep_3[] = { 3406 { 0x00, 0x0000, 0x0080 }, 3407 { 0x0d, 0x0100, 0x0200 }, 3408 { 0x19, 0x8021, 0x0000 }, 3409 { 0x1e, 0x0000, 0x2000 }, 3410 }; 3411 3412 rtl_ephy_init(tp, e_info_8168ep_3); 3413 3414 rtl_hw_start_8168ep(tp); 3415 3416 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3417 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3418 3419 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3420 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3421 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3422 } 3423 3424 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3425 { 3426 static const struct ephy_info e_info_8117[] = { 3427 { 0x19, 0x0040, 0x1100 }, 3428 { 0x59, 0x0040, 0x1100 }, 3429 }; 3430 int rg_saw_cnt; 3431 3432 rtl8168ep_stop_cmac(tp); 3433 rtl_ephy_init(tp, e_info_8117); 3434 3435 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3436 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3437 3438 rtl_set_def_aspm_entry_latency(tp); 3439 3440 rtl_reset_packet_filter(tp); 3441 3442 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3443 3444 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3445 3446 rtl_disable_rxdvgate(tp); 3447 3448 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3449 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3450 3451 rtl8168_config_eee_mac(tp); 3452 3453 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3454 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3455 3456 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3457 3458 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3459 3460 rtl_pcie_state_l2l3_disable(tp); 3461 3462 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3463 if (rg_saw_cnt > 0) { 3464 u16 sw_cnt_1ms_ini; 3465 3466 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3467 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3468 } 3469 3470 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3471 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3472 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3473 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3474 3475 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3476 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3477 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3478 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3479 3480 /* firmware is for MAC only */ 3481 r8169_apply_firmware(tp); 3482 } 3483 3484 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3485 { 3486 static const struct ephy_info e_info_8102e_1[] = { 3487 { 0x01, 0, 0x6e65 }, 3488 { 0x02, 0, 0x091f }, 3489 { 0x03, 0, 0xc2f9 }, 3490 { 0x06, 0, 0xafb5 }, 3491 { 0x07, 0, 0x0e00 }, 3492 { 0x19, 0, 0xec80 }, 3493 { 0x01, 0, 0x2e65 }, 3494 { 0x01, 0, 0x6e65 } 3495 }; 3496 u8 cfg1; 3497 3498 rtl_set_def_aspm_entry_latency(tp); 3499 3500 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3501 3502 RTL_W8(tp, Config1, 3503 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3504 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3505 3506 cfg1 = RTL_R8(tp, Config1); 3507 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3508 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3509 3510 rtl_ephy_init(tp, e_info_8102e_1); 3511 } 3512 3513 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3514 { 3515 rtl_set_def_aspm_entry_latency(tp); 3516 3517 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3518 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3519 } 3520 3521 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3522 { 3523 rtl_hw_start_8102e_2(tp); 3524 3525 rtl_ephy_write(tp, 0x03, 0xc2f9); 3526 } 3527 3528 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3529 { 3530 static const struct ephy_info e_info_8401[] = { 3531 { 0x01, 0xffff, 0x6fe5 }, 3532 { 0x03, 0xffff, 0x0599 }, 3533 { 0x06, 0xffff, 0xaf25 }, 3534 { 0x07, 0xffff, 0x8e68 }, 3535 }; 3536 3537 rtl_ephy_init(tp, e_info_8401); 3538 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3539 } 3540 3541 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3542 { 3543 static const struct ephy_info e_info_8105e_1[] = { 3544 { 0x07, 0, 0x4000 }, 3545 { 0x19, 0, 0x0200 }, 3546 { 0x19, 0, 0x0020 }, 3547 { 0x1e, 0, 0x2000 }, 3548 { 0x03, 0, 0x0001 }, 3549 { 0x19, 0, 0x0100 }, 3550 { 0x19, 0, 0x0004 }, 3551 { 0x0a, 0, 0x0020 } 3552 }; 3553 3554 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3555 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3556 3557 /* Disable Early Tally Counter */ 3558 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3559 3560 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3561 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3562 3563 rtl_ephy_init(tp, e_info_8105e_1); 3564 3565 rtl_pcie_state_l2l3_disable(tp); 3566 } 3567 3568 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3569 { 3570 rtl_hw_start_8105e_1(tp); 3571 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3572 } 3573 3574 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3575 { 3576 static const struct ephy_info e_info_8402[] = { 3577 { 0x19, 0xffff, 0xff64 }, 3578 { 0x1e, 0, 0x4000 } 3579 }; 3580 3581 rtl_set_def_aspm_entry_latency(tp); 3582 3583 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3584 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3585 3586 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3587 3588 rtl_ephy_init(tp, e_info_8402); 3589 3590 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3591 rtl_reset_packet_filter(tp); 3592 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3593 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3594 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3595 3596 /* disable EEE */ 3597 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3598 3599 rtl_pcie_state_l2l3_disable(tp); 3600 } 3601 3602 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3603 { 3604 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3605 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3606 3607 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3608 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3609 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3610 3611 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3612 rtl_set_aspm_entry_latency(tp, 0x2f); 3613 3614 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3615 3616 /* disable EEE */ 3617 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3618 3619 rtl_pcie_state_l2l3_disable(tp); 3620 } 3621 3622 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3623 { 3624 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3625 } 3626 3627 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3628 { 3629 rtl_pcie_state_l2l3_disable(tp); 3630 3631 RTL_W16(tp, 0x382, 0x221b); 3632 RTL_W8(tp, 0x4500, 0); 3633 RTL_W16(tp, 0x4800, 0); 3634 3635 /* disable UPS */ 3636 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3637 3638 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3639 3640 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3641 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3642 3643 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3644 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3645 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3646 3647 /* disable new tx descriptor format */ 3648 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3649 3650 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3651 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3652 else 3653 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3654 3655 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3656 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3657 else 3658 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3659 3660 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3661 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3662 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3663 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3664 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3665 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3666 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3667 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3668 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3669 3670 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3671 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3672 udelay(1); 3673 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3674 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3675 3676 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3677 3678 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3679 3680 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3681 rtl8125b_config_eee_mac(tp); 3682 else 3683 rtl8125a_config_eee_mac(tp); 3684 3685 rtl_disable_rxdvgate(tp); 3686 } 3687 3688 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3689 { 3690 static const struct ephy_info e_info_8125a_2[] = { 3691 { 0x04, 0xffff, 0xd000 }, 3692 { 0x0a, 0xffff, 0x8653 }, 3693 { 0x23, 0xffff, 0xab66 }, 3694 { 0x20, 0xffff, 0x9455 }, 3695 { 0x21, 0xffff, 0x99ff }, 3696 { 0x29, 0xffff, 0xfe04 }, 3697 3698 { 0x44, 0xffff, 0xd000 }, 3699 { 0x4a, 0xffff, 0x8653 }, 3700 { 0x63, 0xffff, 0xab66 }, 3701 { 0x60, 0xffff, 0x9455 }, 3702 { 0x61, 0xffff, 0x99ff }, 3703 { 0x69, 0xffff, 0xfe04 }, 3704 }; 3705 3706 rtl_set_def_aspm_entry_latency(tp); 3707 rtl_ephy_init(tp, e_info_8125a_2); 3708 rtl_hw_start_8125_common(tp); 3709 } 3710 3711 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3712 { 3713 static const struct ephy_info e_info_8125b[] = { 3714 { 0x0b, 0xffff, 0xa908 }, 3715 { 0x1e, 0xffff, 0x20eb }, 3716 { 0x4b, 0xffff, 0xa908 }, 3717 { 0x5e, 0xffff, 0x20eb }, 3718 { 0x22, 0x0030, 0x0020 }, 3719 { 0x62, 0x0030, 0x0020 }, 3720 }; 3721 3722 rtl_set_def_aspm_entry_latency(tp); 3723 rtl_ephy_init(tp, e_info_8125b); 3724 rtl_hw_start_8125_common(tp); 3725 } 3726 3727 static void rtl_hw_config(struct rtl8169_private *tp) 3728 { 3729 static const rtl_generic_fct hw_configs[] = { 3730 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3731 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3732 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3733 [RTL_GIGA_MAC_VER_10] = NULL, 3734 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3735 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3736 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3737 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3738 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3739 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3740 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3741 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3742 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3743 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3744 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3745 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3746 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3747 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3748 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3749 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3750 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3751 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3752 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3753 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3754 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3755 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3756 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3757 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3758 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3759 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3760 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3761 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3762 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3763 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3764 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3765 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3766 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3767 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3768 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3769 }; 3770 3771 if (hw_configs[tp->mac_version]) 3772 hw_configs[tp->mac_version](tp); 3773 } 3774 3775 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3776 { 3777 int i; 3778 3779 /* disable interrupt coalescing */ 3780 for (i = 0xa00; i < 0xb00; i += 4) 3781 RTL_W32(tp, i, 0); 3782 3783 rtl_hw_config(tp); 3784 } 3785 3786 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3787 { 3788 if (rtl_is_8168evl_up(tp)) 3789 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3790 else 3791 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3792 3793 rtl_hw_config(tp); 3794 3795 /* disable interrupt coalescing */ 3796 RTL_W16(tp, IntrMitigate, 0x0000); 3797 } 3798 3799 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3800 { 3801 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3802 3803 tp->cp_cmd |= PCIMulRW; 3804 3805 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3806 tp->mac_version == RTL_GIGA_MAC_VER_03) 3807 tp->cp_cmd |= EnAnaPLL; 3808 3809 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3810 3811 rtl8169_set_magic_reg(tp); 3812 3813 /* disable interrupt coalescing */ 3814 RTL_W16(tp, IntrMitigate, 0x0000); 3815 } 3816 3817 static void rtl_hw_start(struct rtl8169_private *tp) 3818 { 3819 rtl_unlock_config_regs(tp); 3820 /* disable aspm and clock request before ephy access */ 3821 rtl_hw_aspm_clkreq_enable(tp, false); 3822 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3823 3824 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3825 rtl_hw_start_8169(tp); 3826 else if (rtl_is_8125(tp)) 3827 rtl_hw_start_8125(tp); 3828 else 3829 rtl_hw_start_8168(tp); 3830 3831 rtl_enable_exit_l1(tp); 3832 rtl_hw_aspm_clkreq_enable(tp, true); 3833 rtl_set_rx_max_size(tp); 3834 rtl_set_rx_tx_desc_registers(tp); 3835 rtl_lock_config_regs(tp); 3836 3837 rtl_jumbo_config(tp); 3838 3839 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3840 rtl_pci_commit(tp); 3841 3842 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3843 rtl_init_rxcfg(tp); 3844 rtl_set_tx_config_registers(tp); 3845 rtl_set_rx_config_features(tp, tp->dev->features); 3846 rtl_set_rx_mode(tp->dev); 3847 rtl_irq_enable(tp); 3848 } 3849 3850 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3851 { 3852 struct rtl8169_private *tp = netdev_priv(dev); 3853 3854 dev->mtu = new_mtu; 3855 netdev_update_features(dev); 3856 rtl_jumbo_config(tp); 3857 3858 switch (tp->mac_version) { 3859 case RTL_GIGA_MAC_VER_61: 3860 case RTL_GIGA_MAC_VER_63: 3861 rtl8125_set_eee_txidle_timer(tp); 3862 break; 3863 default: 3864 break; 3865 } 3866 3867 return 0; 3868 } 3869 3870 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3871 { 3872 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3873 3874 desc->opts2 = 0; 3875 /* Force memory writes to complete before releasing descriptor */ 3876 dma_wmb(); 3877 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3878 } 3879 3880 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3881 struct RxDesc *desc) 3882 { 3883 struct device *d = tp_to_dev(tp); 3884 int node = dev_to_node(d); 3885 dma_addr_t mapping; 3886 struct page *data; 3887 3888 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3889 if (!data) 3890 return NULL; 3891 3892 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3893 if (unlikely(dma_mapping_error(d, mapping))) { 3894 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3895 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3896 return NULL; 3897 } 3898 3899 desc->addr = cpu_to_le64(mapping); 3900 rtl8169_mark_to_asic(desc); 3901 3902 return data; 3903 } 3904 3905 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3906 { 3907 int i; 3908 3909 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3910 dma_unmap_page(tp_to_dev(tp), 3911 le64_to_cpu(tp->RxDescArray[i].addr), 3912 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3913 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3914 tp->Rx_databuff[i] = NULL; 3915 tp->RxDescArray[i].addr = 0; 3916 tp->RxDescArray[i].opts1 = 0; 3917 } 3918 } 3919 3920 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3921 { 3922 int i; 3923 3924 for (i = 0; i < NUM_RX_DESC; i++) { 3925 struct page *data; 3926 3927 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3928 if (!data) { 3929 rtl8169_rx_clear(tp); 3930 return -ENOMEM; 3931 } 3932 tp->Rx_databuff[i] = data; 3933 } 3934 3935 /* mark as last descriptor in the ring */ 3936 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3937 3938 return 0; 3939 } 3940 3941 static int rtl8169_init_ring(struct rtl8169_private *tp) 3942 { 3943 rtl8169_init_ring_indexes(tp); 3944 3945 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3946 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3947 3948 return rtl8169_rx_fill(tp); 3949 } 3950 3951 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3952 { 3953 struct ring_info *tx_skb = tp->tx_skb + entry; 3954 struct TxDesc *desc = tp->TxDescArray + entry; 3955 3956 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3957 DMA_TO_DEVICE); 3958 memset(desc, 0, sizeof(*desc)); 3959 memset(tx_skb, 0, sizeof(*tx_skb)); 3960 } 3961 3962 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3963 unsigned int n) 3964 { 3965 unsigned int i; 3966 3967 for (i = 0; i < n; i++) { 3968 unsigned int entry = (start + i) % NUM_TX_DESC; 3969 struct ring_info *tx_skb = tp->tx_skb + entry; 3970 unsigned int len = tx_skb->len; 3971 3972 if (len) { 3973 struct sk_buff *skb = tx_skb->skb; 3974 3975 rtl8169_unmap_tx_skb(tp, entry); 3976 if (skb) 3977 dev_consume_skb_any(skb); 3978 } 3979 } 3980 } 3981 3982 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3983 { 3984 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3985 netdev_reset_queue(tp->dev); 3986 } 3987 3988 static void rtl8169_cleanup(struct rtl8169_private *tp) 3989 { 3990 napi_disable(&tp->napi); 3991 3992 /* Give a racing hard_start_xmit a few cycles to complete. */ 3993 synchronize_net(); 3994 3995 /* Disable interrupts */ 3996 rtl8169_irq_mask_and_ack(tp); 3997 3998 rtl_rx_close(tp); 3999 4000 switch (tp->mac_version) { 4001 case RTL_GIGA_MAC_VER_28: 4002 case RTL_GIGA_MAC_VER_31: 4003 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4004 break; 4005 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4006 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4007 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4008 break; 4009 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 4010 rtl_enable_rxdvgate(tp); 4011 fsleep(2000); 4012 break; 4013 default: 4014 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4015 fsleep(100); 4016 break; 4017 } 4018 4019 rtl_hw_reset(tp); 4020 4021 rtl8169_tx_clear(tp); 4022 rtl8169_init_ring_indexes(tp); 4023 } 4024 4025 static void rtl_reset_work(struct rtl8169_private *tp) 4026 { 4027 int i; 4028 4029 netif_stop_queue(tp->dev); 4030 4031 rtl8169_cleanup(tp); 4032 4033 for (i = 0; i < NUM_RX_DESC; i++) 4034 rtl8169_mark_to_asic(tp->RxDescArray + i); 4035 4036 napi_enable(&tp->napi); 4037 rtl_hw_start(tp); 4038 } 4039 4040 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4041 { 4042 struct rtl8169_private *tp = netdev_priv(dev); 4043 4044 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4045 } 4046 4047 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4048 void *addr, unsigned int entry, bool desc_own) 4049 { 4050 struct TxDesc *txd = tp->TxDescArray + entry; 4051 struct device *d = tp_to_dev(tp); 4052 dma_addr_t mapping; 4053 u32 opts1; 4054 int ret; 4055 4056 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4057 ret = dma_mapping_error(d, mapping); 4058 if (unlikely(ret)) { 4059 if (net_ratelimit()) 4060 netdev_err(tp->dev, "Failed to map TX data!\n"); 4061 return ret; 4062 } 4063 4064 txd->addr = cpu_to_le64(mapping); 4065 txd->opts2 = cpu_to_le32(opts[1]); 4066 4067 opts1 = opts[0] | len; 4068 if (entry == NUM_TX_DESC - 1) 4069 opts1 |= RingEnd; 4070 if (desc_own) 4071 opts1 |= DescOwn; 4072 txd->opts1 = cpu_to_le32(opts1); 4073 4074 tp->tx_skb[entry].len = len; 4075 4076 return 0; 4077 } 4078 4079 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4080 const u32 *opts, unsigned int entry) 4081 { 4082 struct skb_shared_info *info = skb_shinfo(skb); 4083 unsigned int cur_frag; 4084 4085 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4086 const skb_frag_t *frag = info->frags + cur_frag; 4087 void *addr = skb_frag_address(frag); 4088 u32 len = skb_frag_size(frag); 4089 4090 entry = (entry + 1) % NUM_TX_DESC; 4091 4092 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4093 goto err_out; 4094 } 4095 4096 return 0; 4097 4098 err_out: 4099 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4100 return -EIO; 4101 } 4102 4103 static bool rtl_skb_is_udp(struct sk_buff *skb) 4104 { 4105 int no = skb_network_offset(skb); 4106 struct ipv6hdr *i6h, _i6h; 4107 struct iphdr *ih, _ih; 4108 4109 switch (vlan_get_protocol(skb)) { 4110 case htons(ETH_P_IP): 4111 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4112 return ih && ih->protocol == IPPROTO_UDP; 4113 case htons(ETH_P_IPV6): 4114 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4115 return i6h && i6h->nexthdr == IPPROTO_UDP; 4116 default: 4117 return false; 4118 } 4119 } 4120 4121 #define RTL_MIN_PATCH_LEN 47 4122 4123 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4124 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4125 struct sk_buff *skb) 4126 { 4127 unsigned int padto = 0, len = skb->len; 4128 4129 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4130 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4131 unsigned int trans_data_len = skb_tail_pointer(skb) - 4132 skb_transport_header(skb); 4133 4134 if (trans_data_len >= offsetof(struct udphdr, len) && 4135 trans_data_len < RTL_MIN_PATCH_LEN) { 4136 u16 dest = ntohs(udp_hdr(skb)->dest); 4137 4138 /* dest is a standard PTP port */ 4139 if (dest == 319 || dest == 320) 4140 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4141 } 4142 4143 if (trans_data_len < sizeof(struct udphdr)) 4144 padto = max_t(unsigned int, padto, 4145 len + sizeof(struct udphdr) - trans_data_len); 4146 } 4147 4148 return padto; 4149 } 4150 4151 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4152 struct sk_buff *skb) 4153 { 4154 unsigned int padto; 4155 4156 padto = rtl8125_quirk_udp_padto(tp, skb); 4157 4158 switch (tp->mac_version) { 4159 case RTL_GIGA_MAC_VER_34: 4160 case RTL_GIGA_MAC_VER_61: 4161 case RTL_GIGA_MAC_VER_63: 4162 padto = max_t(unsigned int, padto, ETH_ZLEN); 4163 break; 4164 default: 4165 break; 4166 } 4167 4168 return padto; 4169 } 4170 4171 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4172 { 4173 u32 mss = skb_shinfo(skb)->gso_size; 4174 4175 if (mss) { 4176 opts[0] |= TD_LSO; 4177 opts[0] |= mss << TD0_MSS_SHIFT; 4178 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4179 const struct iphdr *ip = ip_hdr(skb); 4180 4181 if (ip->protocol == IPPROTO_TCP) 4182 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4183 else if (ip->protocol == IPPROTO_UDP) 4184 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4185 else 4186 WARN_ON_ONCE(1); 4187 } 4188 } 4189 4190 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4191 struct sk_buff *skb, u32 *opts) 4192 { 4193 struct skb_shared_info *shinfo = skb_shinfo(skb); 4194 u32 mss = shinfo->gso_size; 4195 4196 if (mss) { 4197 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4198 opts[0] |= TD1_GTSENV4; 4199 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4200 if (skb_cow_head(skb, 0)) 4201 return false; 4202 4203 tcp_v6_gso_csum_prep(skb); 4204 opts[0] |= TD1_GTSENV6; 4205 } else { 4206 WARN_ON_ONCE(1); 4207 } 4208 4209 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4210 opts[1] |= mss << TD1_MSS_SHIFT; 4211 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4212 u8 ip_protocol; 4213 4214 switch (vlan_get_protocol(skb)) { 4215 case htons(ETH_P_IP): 4216 opts[1] |= TD1_IPv4_CS; 4217 ip_protocol = ip_hdr(skb)->protocol; 4218 break; 4219 4220 case htons(ETH_P_IPV6): 4221 opts[1] |= TD1_IPv6_CS; 4222 ip_protocol = ipv6_hdr(skb)->nexthdr; 4223 break; 4224 4225 default: 4226 ip_protocol = IPPROTO_RAW; 4227 break; 4228 } 4229 4230 if (ip_protocol == IPPROTO_TCP) 4231 opts[1] |= TD1_TCP_CS; 4232 else if (ip_protocol == IPPROTO_UDP) 4233 opts[1] |= TD1_UDP_CS; 4234 else 4235 WARN_ON_ONCE(1); 4236 4237 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4238 } else { 4239 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4240 4241 /* skb_padto would free the skb on error */ 4242 return !__skb_put_padto(skb, padto, false); 4243 } 4244 4245 return true; 4246 } 4247 4248 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4249 { 4250 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4251 } 4252 4253 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4254 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4255 { 4256 switch (tp->mac_version) { 4257 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4258 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4259 return false; 4260 default: 4261 return true; 4262 } 4263 } 4264 4265 static void rtl8169_doorbell(struct rtl8169_private *tp) 4266 { 4267 if (rtl_is_8125(tp)) 4268 RTL_W16(tp, TxPoll_8125, BIT(0)); 4269 else 4270 RTL_W8(tp, TxPoll, NPQ); 4271 } 4272 4273 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4274 struct net_device *dev) 4275 { 4276 struct rtl8169_private *tp = netdev_priv(dev); 4277 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4278 struct TxDesc *txd_first, *txd_last; 4279 bool stop_queue, door_bell; 4280 unsigned int frags; 4281 u32 opts[2]; 4282 4283 if (unlikely(!rtl_tx_slots_avail(tp))) { 4284 if (net_ratelimit()) 4285 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4286 netif_stop_queue(dev); 4287 return NETDEV_TX_BUSY; 4288 } 4289 4290 opts[1] = rtl8169_tx_vlan_tag(skb); 4291 opts[0] = 0; 4292 4293 if (!rtl_chip_supports_csum_v2(tp)) 4294 rtl8169_tso_csum_v1(skb, opts); 4295 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4296 goto err_dma_0; 4297 4298 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4299 entry, false))) 4300 goto err_dma_0; 4301 4302 txd_first = tp->TxDescArray + entry; 4303 4304 frags = skb_shinfo(skb)->nr_frags; 4305 if (frags) { 4306 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4307 goto err_dma_1; 4308 entry = (entry + frags) % NUM_TX_DESC; 4309 } 4310 4311 txd_last = tp->TxDescArray + entry; 4312 txd_last->opts1 |= cpu_to_le32(LastFrag); 4313 tp->tx_skb[entry].skb = skb; 4314 4315 skb_tx_timestamp(skb); 4316 4317 /* Force memory writes to complete before releasing descriptor */ 4318 dma_wmb(); 4319 4320 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4321 4322 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4323 4324 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4325 smp_wmb(); 4326 4327 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4328 4329 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4330 R8169_TX_STOP_THRS, 4331 R8169_TX_START_THRS); 4332 if (door_bell || stop_queue) 4333 rtl8169_doorbell(tp); 4334 4335 return NETDEV_TX_OK; 4336 4337 err_dma_1: 4338 rtl8169_unmap_tx_skb(tp, entry); 4339 err_dma_0: 4340 dev_kfree_skb_any(skb); 4341 dev->stats.tx_dropped++; 4342 return NETDEV_TX_OK; 4343 } 4344 4345 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4346 { 4347 struct skb_shared_info *info = skb_shinfo(skb); 4348 unsigned int nr_frags = info->nr_frags; 4349 4350 if (!nr_frags) 4351 return UINT_MAX; 4352 4353 return skb_frag_size(info->frags + nr_frags - 1); 4354 } 4355 4356 /* Workaround for hw issues with TSO on RTL8168evl */ 4357 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4358 netdev_features_t features) 4359 { 4360 /* IPv4 header has options field */ 4361 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4362 ip_hdrlen(skb) > sizeof(struct iphdr)) 4363 features &= ~NETIF_F_ALL_TSO; 4364 4365 /* IPv4 TCP header has options field */ 4366 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4367 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4368 features &= ~NETIF_F_ALL_TSO; 4369 4370 else if (rtl_last_frag_len(skb) <= 6) 4371 features &= ~NETIF_F_ALL_TSO; 4372 4373 return features; 4374 } 4375 4376 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4377 struct net_device *dev, 4378 netdev_features_t features) 4379 { 4380 struct rtl8169_private *tp = netdev_priv(dev); 4381 4382 if (skb_is_gso(skb)) { 4383 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4384 features = rtl8168evl_fix_tso(skb, features); 4385 4386 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4387 rtl_chip_supports_csum_v2(tp)) 4388 features &= ~NETIF_F_ALL_TSO; 4389 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4390 /* work around hw bug on some chip versions */ 4391 if (skb->len < ETH_ZLEN) 4392 features &= ~NETIF_F_CSUM_MASK; 4393 4394 if (rtl_quirk_packet_padto(tp, skb)) 4395 features &= ~NETIF_F_CSUM_MASK; 4396 4397 if (skb_transport_offset(skb) > TCPHO_MAX && 4398 rtl_chip_supports_csum_v2(tp)) 4399 features &= ~NETIF_F_CSUM_MASK; 4400 } 4401 4402 return vlan_features_check(skb, features); 4403 } 4404 4405 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4406 { 4407 struct rtl8169_private *tp = netdev_priv(dev); 4408 struct pci_dev *pdev = tp->pci_dev; 4409 int pci_status_errs; 4410 u16 pci_cmd; 4411 4412 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4413 4414 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4415 4416 if (net_ratelimit()) 4417 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4418 pci_cmd, pci_status_errs); 4419 4420 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4421 } 4422 4423 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4424 int budget) 4425 { 4426 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4427 struct sk_buff *skb; 4428 4429 dirty_tx = tp->dirty_tx; 4430 4431 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4432 unsigned int entry = dirty_tx % NUM_TX_DESC; 4433 u32 status; 4434 4435 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4436 if (status & DescOwn) 4437 break; 4438 4439 skb = tp->tx_skb[entry].skb; 4440 rtl8169_unmap_tx_skb(tp, entry); 4441 4442 if (skb) { 4443 pkts_compl++; 4444 bytes_compl += skb->len; 4445 napi_consume_skb(skb, budget); 4446 } 4447 dirty_tx++; 4448 } 4449 4450 if (tp->dirty_tx != dirty_tx) { 4451 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4452 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4453 4454 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4455 rtl_tx_slots_avail(tp), 4456 R8169_TX_START_THRS); 4457 /* 4458 * 8168 hack: TxPoll requests are lost when the Tx packets are 4459 * too close. Let's kick an extra TxPoll request when a burst 4460 * of start_xmit activity is detected (if it is not detected, 4461 * it is slow enough). -- FR 4462 * If skb is NULL then we come here again once a tx irq is 4463 * triggered after the last fragment is marked transmitted. 4464 */ 4465 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4466 rtl8169_doorbell(tp); 4467 } 4468 } 4469 4470 static inline int rtl8169_fragmented_frame(u32 status) 4471 { 4472 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4473 } 4474 4475 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4476 { 4477 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4478 4479 if (status == RxProtoTCP || status == RxProtoUDP) 4480 skb->ip_summed = CHECKSUM_UNNECESSARY; 4481 else 4482 skb_checksum_none_assert(skb); 4483 } 4484 4485 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4486 { 4487 struct device *d = tp_to_dev(tp); 4488 int count; 4489 4490 for (count = 0; count < budget; count++, tp->cur_rx++) { 4491 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4492 struct RxDesc *desc = tp->RxDescArray + entry; 4493 struct sk_buff *skb; 4494 const void *rx_buf; 4495 dma_addr_t addr; 4496 u32 status; 4497 4498 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4499 if (status & DescOwn) 4500 break; 4501 4502 /* This barrier is needed to keep us from reading 4503 * any other fields out of the Rx descriptor until 4504 * we know the status of DescOwn 4505 */ 4506 dma_rmb(); 4507 4508 if (unlikely(status & RxRES)) { 4509 if (net_ratelimit()) 4510 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4511 status); 4512 dev->stats.rx_errors++; 4513 if (status & (RxRWT | RxRUNT)) 4514 dev->stats.rx_length_errors++; 4515 if (status & RxCRC) 4516 dev->stats.rx_crc_errors++; 4517 4518 if (!(dev->features & NETIF_F_RXALL)) 4519 goto release_descriptor; 4520 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4521 goto release_descriptor; 4522 } 4523 4524 pkt_size = status & GENMASK(13, 0); 4525 if (likely(!(dev->features & NETIF_F_RXFCS))) 4526 pkt_size -= ETH_FCS_LEN; 4527 4528 /* The driver does not support incoming fragmented frames. 4529 * They are seen as a symptom of over-mtu sized frames. 4530 */ 4531 if (unlikely(rtl8169_fragmented_frame(status))) { 4532 dev->stats.rx_dropped++; 4533 dev->stats.rx_length_errors++; 4534 goto release_descriptor; 4535 } 4536 4537 skb = napi_alloc_skb(&tp->napi, pkt_size); 4538 if (unlikely(!skb)) { 4539 dev->stats.rx_dropped++; 4540 goto release_descriptor; 4541 } 4542 4543 addr = le64_to_cpu(desc->addr); 4544 rx_buf = page_address(tp->Rx_databuff[entry]); 4545 4546 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4547 prefetch(rx_buf); 4548 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4549 skb->tail += pkt_size; 4550 skb->len = pkt_size; 4551 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4552 4553 rtl8169_rx_csum(skb, status); 4554 skb->protocol = eth_type_trans(skb, dev); 4555 4556 rtl8169_rx_vlan_tag(desc, skb); 4557 4558 if (skb->pkt_type == PACKET_MULTICAST) 4559 dev->stats.multicast++; 4560 4561 napi_gro_receive(&tp->napi, skb); 4562 4563 dev_sw_netstats_rx_add(dev, pkt_size); 4564 release_descriptor: 4565 rtl8169_mark_to_asic(desc); 4566 } 4567 4568 return count; 4569 } 4570 4571 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4572 { 4573 struct rtl8169_private *tp = dev_instance; 4574 u32 status = rtl_get_events(tp); 4575 4576 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4577 return IRQ_NONE; 4578 4579 if (unlikely(status & SYSErr)) { 4580 rtl8169_pcierr_interrupt(tp->dev); 4581 goto out; 4582 } 4583 4584 if (status & LinkChg) 4585 phy_mac_interrupt(tp->phydev); 4586 4587 if (unlikely(status & RxFIFOOver && 4588 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4589 netif_stop_queue(tp->dev); 4590 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4591 } 4592 4593 rtl_irq_disable(tp); 4594 napi_schedule(&tp->napi); 4595 out: 4596 rtl_ack_events(tp, status); 4597 4598 return IRQ_HANDLED; 4599 } 4600 4601 static void rtl_task(struct work_struct *work) 4602 { 4603 struct rtl8169_private *tp = 4604 container_of(work, struct rtl8169_private, wk.work); 4605 int ret; 4606 4607 rtnl_lock(); 4608 4609 if (!netif_running(tp->dev) || 4610 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4611 goto out_unlock; 4612 4613 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4614 /* if chip isn't accessible, reset bus to revive it */ 4615 if (RTL_R32(tp, TxConfig) == ~0) { 4616 ret = pci_reset_bus(tp->pci_dev); 4617 if (ret < 0) { 4618 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4619 netif_device_detach(tp->dev); 4620 goto out_unlock; 4621 } 4622 } 4623 4624 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4625 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4626 PCIE_LINK_STATE_L0S); 4627 if (!ret) 4628 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4629 goto reset; 4630 } 4631 4632 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4633 reset: 4634 rtl_reset_work(tp); 4635 netif_wake_queue(tp->dev); 4636 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4637 rtl_reset_work(tp); 4638 } 4639 out_unlock: 4640 rtnl_unlock(); 4641 } 4642 4643 static int rtl8169_poll(struct napi_struct *napi, int budget) 4644 { 4645 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4646 struct net_device *dev = tp->dev; 4647 int work_done; 4648 4649 rtl_tx(dev, tp, budget); 4650 4651 work_done = rtl_rx(dev, tp, budget); 4652 4653 if (work_done < budget && napi_complete_done(napi, work_done)) 4654 rtl_irq_enable(tp); 4655 4656 return work_done; 4657 } 4658 4659 static void r8169_phylink_handler(struct net_device *ndev) 4660 { 4661 struct rtl8169_private *tp = netdev_priv(ndev); 4662 struct device *d = tp_to_dev(tp); 4663 4664 if (netif_carrier_ok(ndev)) { 4665 rtl_link_chg_patch(tp); 4666 pm_request_resume(d); 4667 netif_wake_queue(tp->dev); 4668 } else { 4669 /* In few cases rx is broken after link-down otherwise */ 4670 if (rtl_is_8125(tp)) 4671 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4672 pm_runtime_idle(d); 4673 } 4674 4675 phy_print_status(tp->phydev); 4676 } 4677 4678 static int r8169_phy_connect(struct rtl8169_private *tp) 4679 { 4680 struct phy_device *phydev = tp->phydev; 4681 phy_interface_t phy_mode; 4682 int ret; 4683 4684 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4685 PHY_INTERFACE_MODE_MII; 4686 4687 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4688 phy_mode); 4689 if (ret) 4690 return ret; 4691 4692 if (!tp->supports_gmii) 4693 phy_set_max_speed(phydev, SPEED_100); 4694 4695 phy_attached_info(phydev); 4696 4697 return 0; 4698 } 4699 4700 static void rtl8169_down(struct rtl8169_private *tp) 4701 { 4702 /* Clear all task flags */ 4703 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4704 4705 phy_stop(tp->phydev); 4706 4707 rtl8169_update_counters(tp); 4708 4709 pci_clear_master(tp->pci_dev); 4710 rtl_pci_commit(tp); 4711 4712 rtl8169_cleanup(tp); 4713 rtl_disable_exit_l1(tp); 4714 rtl_prepare_power_down(tp); 4715 4716 if (tp->dash_type != RTL_DASH_NONE) 4717 rtl8168_driver_stop(tp); 4718 } 4719 4720 static void rtl8169_up(struct rtl8169_private *tp) 4721 { 4722 if (tp->dash_type != RTL_DASH_NONE) 4723 rtl8168_driver_start(tp); 4724 4725 pci_set_master(tp->pci_dev); 4726 phy_init_hw(tp->phydev); 4727 phy_resume(tp->phydev); 4728 rtl8169_init_phy(tp); 4729 napi_enable(&tp->napi); 4730 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4731 rtl_reset_work(tp); 4732 4733 phy_start(tp->phydev); 4734 } 4735 4736 static int rtl8169_close(struct net_device *dev) 4737 { 4738 struct rtl8169_private *tp = netdev_priv(dev); 4739 struct pci_dev *pdev = tp->pci_dev; 4740 4741 pm_runtime_get_sync(&pdev->dev); 4742 4743 netif_stop_queue(dev); 4744 rtl8169_down(tp); 4745 rtl8169_rx_clear(tp); 4746 4747 cancel_work(&tp->wk.work); 4748 4749 free_irq(tp->irq, tp); 4750 4751 phy_disconnect(tp->phydev); 4752 4753 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4754 tp->RxPhyAddr); 4755 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4756 tp->TxPhyAddr); 4757 tp->TxDescArray = NULL; 4758 tp->RxDescArray = NULL; 4759 4760 pm_runtime_put_sync(&pdev->dev); 4761 4762 return 0; 4763 } 4764 4765 #ifdef CONFIG_NET_POLL_CONTROLLER 4766 static void rtl8169_netpoll(struct net_device *dev) 4767 { 4768 struct rtl8169_private *tp = netdev_priv(dev); 4769 4770 rtl8169_interrupt(tp->irq, tp); 4771 } 4772 #endif 4773 4774 static int rtl_open(struct net_device *dev) 4775 { 4776 struct rtl8169_private *tp = netdev_priv(dev); 4777 struct pci_dev *pdev = tp->pci_dev; 4778 unsigned long irqflags; 4779 int retval = -ENOMEM; 4780 4781 pm_runtime_get_sync(&pdev->dev); 4782 4783 /* 4784 * Rx and Tx descriptors needs 256 bytes alignment. 4785 * dma_alloc_coherent provides more. 4786 */ 4787 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4788 &tp->TxPhyAddr, GFP_KERNEL); 4789 if (!tp->TxDescArray) 4790 goto out; 4791 4792 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4793 &tp->RxPhyAddr, GFP_KERNEL); 4794 if (!tp->RxDescArray) 4795 goto err_free_tx_0; 4796 4797 retval = rtl8169_init_ring(tp); 4798 if (retval < 0) 4799 goto err_free_rx_1; 4800 4801 rtl_request_firmware(tp); 4802 4803 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4804 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4805 if (retval < 0) 4806 goto err_release_fw_2; 4807 4808 retval = r8169_phy_connect(tp); 4809 if (retval) 4810 goto err_free_irq; 4811 4812 rtl8169_up(tp); 4813 rtl8169_init_counter_offsets(tp); 4814 netif_start_queue(dev); 4815 out: 4816 pm_runtime_put_sync(&pdev->dev); 4817 4818 return retval; 4819 4820 err_free_irq: 4821 free_irq(tp->irq, tp); 4822 err_release_fw_2: 4823 rtl_release_firmware(tp); 4824 rtl8169_rx_clear(tp); 4825 err_free_rx_1: 4826 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4827 tp->RxPhyAddr); 4828 tp->RxDescArray = NULL; 4829 err_free_tx_0: 4830 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4831 tp->TxPhyAddr); 4832 tp->TxDescArray = NULL; 4833 goto out; 4834 } 4835 4836 static void 4837 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4838 { 4839 struct rtl8169_private *tp = netdev_priv(dev); 4840 struct pci_dev *pdev = tp->pci_dev; 4841 struct rtl8169_counters *counters = tp->counters; 4842 4843 pm_runtime_get_noresume(&pdev->dev); 4844 4845 netdev_stats_to_stats64(stats, &dev->stats); 4846 dev_fetch_sw_netstats(stats, dev->tstats); 4847 4848 /* 4849 * Fetch additional counter values missing in stats collected by driver 4850 * from tally counters. 4851 */ 4852 if (pm_runtime_active(&pdev->dev)) 4853 rtl8169_update_counters(tp); 4854 4855 /* 4856 * Subtract values fetched during initalization. 4857 * See rtl8169_init_counter_offsets for a description why we do that. 4858 */ 4859 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4860 le64_to_cpu(tp->tc_offset.tx_errors); 4861 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4862 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4863 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4864 le16_to_cpu(tp->tc_offset.tx_aborted); 4865 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4866 le16_to_cpu(tp->tc_offset.rx_missed); 4867 4868 pm_runtime_put_noidle(&pdev->dev); 4869 } 4870 4871 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4872 { 4873 netif_device_detach(tp->dev); 4874 4875 if (netif_running(tp->dev)) 4876 rtl8169_down(tp); 4877 } 4878 4879 static int rtl8169_runtime_resume(struct device *dev) 4880 { 4881 struct rtl8169_private *tp = dev_get_drvdata(dev); 4882 4883 rtl_rar_set(tp, tp->dev->dev_addr); 4884 __rtl8169_set_wol(tp, tp->saved_wolopts); 4885 4886 if (tp->TxDescArray) 4887 rtl8169_up(tp); 4888 4889 netif_device_attach(tp->dev); 4890 4891 return 0; 4892 } 4893 4894 static int rtl8169_suspend(struct device *device) 4895 { 4896 struct rtl8169_private *tp = dev_get_drvdata(device); 4897 4898 rtnl_lock(); 4899 rtl8169_net_suspend(tp); 4900 if (!device_may_wakeup(tp_to_dev(tp))) 4901 clk_disable_unprepare(tp->clk); 4902 rtnl_unlock(); 4903 4904 return 0; 4905 } 4906 4907 static int rtl8169_resume(struct device *device) 4908 { 4909 struct rtl8169_private *tp = dev_get_drvdata(device); 4910 4911 if (!device_may_wakeup(tp_to_dev(tp))) 4912 clk_prepare_enable(tp->clk); 4913 4914 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4915 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4916 rtl_init_rxcfg(tp); 4917 4918 return rtl8169_runtime_resume(device); 4919 } 4920 4921 static int rtl8169_runtime_suspend(struct device *device) 4922 { 4923 struct rtl8169_private *tp = dev_get_drvdata(device); 4924 4925 if (!tp->TxDescArray) { 4926 netif_device_detach(tp->dev); 4927 return 0; 4928 } 4929 4930 rtnl_lock(); 4931 __rtl8169_set_wol(tp, WAKE_PHY); 4932 rtl8169_net_suspend(tp); 4933 rtnl_unlock(); 4934 4935 return 0; 4936 } 4937 4938 static int rtl8169_runtime_idle(struct device *device) 4939 { 4940 struct rtl8169_private *tp = dev_get_drvdata(device); 4941 4942 if (tp->dash_enabled) 4943 return -EBUSY; 4944 4945 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4946 pm_schedule_suspend(device, 10000); 4947 4948 return -EBUSY; 4949 } 4950 4951 static const struct dev_pm_ops rtl8169_pm_ops = { 4952 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4953 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4954 rtl8169_runtime_idle) 4955 }; 4956 4957 static void rtl_shutdown(struct pci_dev *pdev) 4958 { 4959 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4960 4961 rtnl_lock(); 4962 rtl8169_net_suspend(tp); 4963 rtnl_unlock(); 4964 4965 /* Restore original MAC address */ 4966 rtl_rar_set(tp, tp->dev->perm_addr); 4967 4968 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 4969 pci_wake_from_d3(pdev, tp->saved_wolopts); 4970 pci_set_power_state(pdev, PCI_D3hot); 4971 } 4972 } 4973 4974 static void rtl_remove_one(struct pci_dev *pdev) 4975 { 4976 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4977 4978 if (pci_dev_run_wake(pdev)) 4979 pm_runtime_get_noresume(&pdev->dev); 4980 4981 cancel_work_sync(&tp->wk.work); 4982 4983 unregister_netdev(tp->dev); 4984 4985 if (tp->dash_type != RTL_DASH_NONE) 4986 rtl8168_driver_stop(tp); 4987 4988 rtl_release_firmware(tp); 4989 4990 /* restore original MAC address */ 4991 rtl_rar_set(tp, tp->dev->perm_addr); 4992 } 4993 4994 static const struct net_device_ops rtl_netdev_ops = { 4995 .ndo_open = rtl_open, 4996 .ndo_stop = rtl8169_close, 4997 .ndo_get_stats64 = rtl8169_get_stats64, 4998 .ndo_start_xmit = rtl8169_start_xmit, 4999 .ndo_features_check = rtl8169_features_check, 5000 .ndo_tx_timeout = rtl8169_tx_timeout, 5001 .ndo_validate_addr = eth_validate_addr, 5002 .ndo_change_mtu = rtl8169_change_mtu, 5003 .ndo_fix_features = rtl8169_fix_features, 5004 .ndo_set_features = rtl8169_set_features, 5005 .ndo_set_mac_address = rtl_set_mac_address, 5006 .ndo_eth_ioctl = phy_do_ioctl_running, 5007 .ndo_set_rx_mode = rtl_set_rx_mode, 5008 #ifdef CONFIG_NET_POLL_CONTROLLER 5009 .ndo_poll_controller = rtl8169_netpoll, 5010 #endif 5011 5012 }; 5013 5014 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5015 { 5016 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5017 5018 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5019 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5020 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5021 /* special workaround needed */ 5022 tp->irq_mask |= RxFIFOOver; 5023 else 5024 tp->irq_mask |= RxOverflow; 5025 } 5026 5027 static int rtl_alloc_irq(struct rtl8169_private *tp) 5028 { 5029 unsigned int flags; 5030 5031 switch (tp->mac_version) { 5032 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5033 rtl_unlock_config_regs(tp); 5034 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5035 rtl_lock_config_regs(tp); 5036 fallthrough; 5037 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5038 flags = PCI_IRQ_LEGACY; 5039 break; 5040 default: 5041 flags = PCI_IRQ_ALL_TYPES; 5042 break; 5043 } 5044 5045 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5046 } 5047 5048 static void rtl_read_mac_address(struct rtl8169_private *tp, 5049 u8 mac_addr[ETH_ALEN]) 5050 { 5051 /* Get MAC address */ 5052 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5053 u32 value; 5054 5055 value = rtl_eri_read(tp, 0xe0); 5056 put_unaligned_le32(value, mac_addr); 5057 value = rtl_eri_read(tp, 0xe4); 5058 put_unaligned_le16(value, mac_addr + 4); 5059 } else if (rtl_is_8125(tp)) { 5060 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5061 } 5062 } 5063 5064 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5065 { 5066 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5067 } 5068 5069 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5070 { 5071 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5072 } 5073 5074 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5075 { 5076 struct rtl8169_private *tp = mii_bus->priv; 5077 5078 if (phyaddr > 0) 5079 return -ENODEV; 5080 5081 return rtl_readphy(tp, phyreg); 5082 } 5083 5084 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5085 int phyreg, u16 val) 5086 { 5087 struct rtl8169_private *tp = mii_bus->priv; 5088 5089 if (phyaddr > 0) 5090 return -ENODEV; 5091 5092 rtl_writephy(tp, phyreg, val); 5093 5094 return 0; 5095 } 5096 5097 static int r8169_mdio_register(struct rtl8169_private *tp) 5098 { 5099 struct pci_dev *pdev = tp->pci_dev; 5100 struct mii_bus *new_bus; 5101 int ret; 5102 5103 /* On some boards with this chip version the BIOS is buggy and misses 5104 * to reset the PHY page selector. This results in the PHY ID read 5105 * accessing registers on a different page, returning a more or 5106 * less random value. Fix this by resetting the page selector first. 5107 */ 5108 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5109 tp->mac_version == RTL_GIGA_MAC_VER_26) 5110 r8169_mdio_write(tp, 0x1f, 0); 5111 5112 new_bus = devm_mdiobus_alloc(&pdev->dev); 5113 if (!new_bus) 5114 return -ENOMEM; 5115 5116 new_bus->name = "r8169"; 5117 new_bus->priv = tp; 5118 new_bus->parent = &pdev->dev; 5119 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5120 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5121 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5122 5123 new_bus->read = r8169_mdio_read_reg; 5124 new_bus->write = r8169_mdio_write_reg; 5125 5126 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5127 if (ret) 5128 return ret; 5129 5130 tp->phydev = mdiobus_get_phy(new_bus, 0); 5131 if (!tp->phydev) { 5132 return -ENODEV; 5133 } else if (!tp->phydev->drv) { 5134 /* Most chip versions fail with the genphy driver. 5135 * Therefore ensure that the dedicated PHY driver is loaded. 5136 */ 5137 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5138 tp->phydev->phy_id); 5139 return -EUNATCH; 5140 } 5141 5142 tp->phydev->mac_managed_pm = true; 5143 5144 phy_support_asym_pause(tp->phydev); 5145 5146 /* PHY will be woken up in rtl_open() */ 5147 phy_suspend(tp->phydev); 5148 5149 return 0; 5150 } 5151 5152 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5153 { 5154 rtl_enable_rxdvgate(tp); 5155 5156 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5157 msleep(1); 5158 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5159 5160 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5161 r8168g_wait_ll_share_fifo_ready(tp); 5162 5163 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5164 r8168g_wait_ll_share_fifo_ready(tp); 5165 } 5166 5167 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5168 { 5169 rtl_enable_rxdvgate(tp); 5170 5171 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5172 msleep(1); 5173 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5174 5175 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5176 r8168g_wait_ll_share_fifo_ready(tp); 5177 5178 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5179 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5180 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5181 r8168g_wait_ll_share_fifo_ready(tp); 5182 } 5183 5184 static void rtl_hw_initialize(struct rtl8169_private *tp) 5185 { 5186 switch (tp->mac_version) { 5187 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5188 rtl8168ep_stop_cmac(tp); 5189 fallthrough; 5190 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5191 rtl_hw_init_8168g(tp); 5192 break; 5193 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5194 rtl_hw_init_8125(tp); 5195 break; 5196 default: 5197 break; 5198 } 5199 } 5200 5201 static int rtl_jumbo_max(struct rtl8169_private *tp) 5202 { 5203 /* Non-GBit versions don't support jumbo frames */ 5204 if (!tp->supports_gmii) 5205 return 0; 5206 5207 switch (tp->mac_version) { 5208 /* RTL8169 */ 5209 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5210 return JUMBO_7K; 5211 /* RTL8168b */ 5212 case RTL_GIGA_MAC_VER_11: 5213 case RTL_GIGA_MAC_VER_17: 5214 return JUMBO_4K; 5215 /* RTL8168c */ 5216 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5217 return JUMBO_6K; 5218 default: 5219 return JUMBO_9K; 5220 } 5221 } 5222 5223 static void rtl_init_mac_address(struct rtl8169_private *tp) 5224 { 5225 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5226 struct net_device *dev = tp->dev; 5227 int rc; 5228 5229 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5230 if (!rc) 5231 goto done; 5232 5233 rtl_read_mac_address(tp, mac_addr); 5234 if (is_valid_ether_addr(mac_addr)) 5235 goto done; 5236 5237 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5238 if (is_valid_ether_addr(mac_addr)) 5239 goto done; 5240 5241 eth_random_addr(mac_addr); 5242 dev->addr_assign_type = NET_ADDR_RANDOM; 5243 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5244 done: 5245 eth_hw_addr_set(dev, mac_addr); 5246 rtl_rar_set(tp, mac_addr); 5247 } 5248 5249 /* register is set if system vendor successfully tested ASPM 1.2 */ 5250 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5251 { 5252 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5253 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5254 return true; 5255 5256 return false; 5257 } 5258 5259 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5260 { 5261 struct rtl8169_private *tp; 5262 int jumbo_max, region, rc; 5263 enum mac_version chipset; 5264 struct net_device *dev; 5265 u32 txconfig; 5266 u16 xid; 5267 5268 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5269 if (!dev) 5270 return -ENOMEM; 5271 5272 SET_NETDEV_DEV(dev, &pdev->dev); 5273 dev->netdev_ops = &rtl_netdev_ops; 5274 tp = netdev_priv(dev); 5275 tp->dev = dev; 5276 tp->pci_dev = pdev; 5277 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5278 tp->eee_adv = -1; 5279 tp->ocp_base = OCP_STD_PHY_BASE; 5280 5281 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5282 raw_spin_lock_init(&tp->config25_lock); 5283 raw_spin_lock_init(&tp->mac_ocp_lock); 5284 5285 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5286 struct pcpu_sw_netstats); 5287 if (!dev->tstats) 5288 return -ENOMEM; 5289 5290 /* Get the *optional* external "ether_clk" used on some boards */ 5291 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5292 if (IS_ERR(tp->clk)) 5293 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5294 5295 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5296 rc = pcim_enable_device(pdev); 5297 if (rc < 0) 5298 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5299 5300 if (pcim_set_mwi(pdev) < 0) 5301 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5302 5303 /* use first MMIO region */ 5304 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5305 if (region < 0) 5306 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5307 5308 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5309 if (rc < 0) 5310 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5311 5312 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5313 5314 txconfig = RTL_R32(tp, TxConfig); 5315 if (txconfig == ~0U) 5316 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5317 5318 xid = (txconfig >> 20) & 0xfcf; 5319 5320 /* Identify chip attached to board */ 5321 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5322 if (chipset == RTL_GIGA_MAC_NONE) 5323 return dev_err_probe(&pdev->dev, -ENODEV, 5324 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5325 xid); 5326 tp->mac_version = chipset; 5327 5328 /* Disable ASPM L1 as that cause random device stop working 5329 * problems as well as full system hangs for some PCIe devices users. 5330 */ 5331 if (rtl_aspm_is_safe(tp)) 5332 rc = 0; 5333 else 5334 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5335 tp->aspm_manageable = !rc; 5336 5337 tp->dash_type = rtl_get_dash_type(tp); 5338 tp->dash_enabled = rtl_dash_is_enabled(tp); 5339 5340 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5341 5342 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5343 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5344 dev->features |= NETIF_F_HIGHDMA; 5345 5346 rtl_init_rxcfg(tp); 5347 5348 rtl8169_irq_mask_and_ack(tp); 5349 5350 rtl_hw_initialize(tp); 5351 5352 rtl_hw_reset(tp); 5353 5354 rc = rtl_alloc_irq(tp); 5355 if (rc < 0) 5356 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5357 5358 tp->irq = pci_irq_vector(pdev, 0); 5359 5360 INIT_WORK(&tp->wk.work, rtl_task); 5361 5362 rtl_init_mac_address(tp); 5363 5364 dev->ethtool_ops = &rtl8169_ethtool_ops; 5365 5366 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5367 5368 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5369 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5370 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5371 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5372 5373 /* 5374 * Pretend we are using VLANs; This bypasses a nasty bug where 5375 * Interrupts stop flowing on high load on 8110SCd controllers. 5376 */ 5377 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5378 /* Disallow toggling */ 5379 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5380 5381 if (rtl_chip_supports_csum_v2(tp)) 5382 dev->hw_features |= NETIF_F_IPV6_CSUM; 5383 5384 dev->features |= dev->hw_features; 5385 5386 /* There has been a number of reports that using SG/TSO results in 5387 * tx timeouts. However for a lot of people SG/TSO works fine. 5388 * Therefore disable both features by default, but allow users to 5389 * enable them. Use at own risk! 5390 */ 5391 if (rtl_chip_supports_csum_v2(tp)) { 5392 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5393 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5394 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5395 } else { 5396 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5397 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5398 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5399 } 5400 5401 dev->hw_features |= NETIF_F_RXALL; 5402 dev->hw_features |= NETIF_F_RXFCS; 5403 5404 netdev_sw_irq_coalesce_default_on(dev); 5405 5406 /* configure chip for default features */ 5407 rtl8169_set_features(dev, dev->features); 5408 5409 if (!tp->dash_enabled) { 5410 rtl_set_d3_pll_down(tp, true); 5411 } else { 5412 rtl_set_d3_pll_down(tp, false); 5413 dev->wol_enabled = 1; 5414 } 5415 5416 jumbo_max = rtl_jumbo_max(tp); 5417 if (jumbo_max) 5418 dev->max_mtu = jumbo_max; 5419 5420 rtl_set_irq_mask(tp); 5421 5422 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5423 5424 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5425 &tp->counters_phys_addr, 5426 GFP_KERNEL); 5427 if (!tp->counters) 5428 return -ENOMEM; 5429 5430 pci_set_drvdata(pdev, tp); 5431 5432 rc = r8169_mdio_register(tp); 5433 if (rc) 5434 return rc; 5435 5436 rc = register_netdev(dev); 5437 if (rc) 5438 return rc; 5439 5440 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5441 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5442 5443 if (jumbo_max) 5444 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5445 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5446 "ok" : "ko"); 5447 5448 if (tp->dash_type != RTL_DASH_NONE) { 5449 netdev_info(dev, "DASH %s\n", 5450 tp->dash_enabled ? "enabled" : "disabled"); 5451 rtl8168_driver_start(tp); 5452 } 5453 5454 if (pci_dev_run_wake(pdev)) 5455 pm_runtime_put_sync(&pdev->dev); 5456 5457 return 0; 5458 } 5459 5460 static struct pci_driver rtl8169_pci_driver = { 5461 .name = KBUILD_MODNAME, 5462 .id_table = rtl8169_pci_tbl, 5463 .probe = rtl_init_one, 5464 .remove = rtl_remove_one, 5465 .shutdown = rtl_shutdown, 5466 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5467 }; 5468 5469 module_pci_driver(rtl8169_pci_driver); 5470