1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define MODULENAME "r8169" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 56 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 59 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 60 61 #define R8169_MSG_DEFAULT \ 62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 63 64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 65 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 66 #define MC_FILTER_LIMIT 32 67 68 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 69 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 70 71 #define R8169_REGS_SIZE 256 72 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 73 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 74 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 77 78 #define RTL_CFG_NO_GBIT 1 79 80 /* write/read MMIO register */ 81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 87 88 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 89 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 90 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 91 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 92 93 static const struct { 94 const char *name; 95 const char *fw_name; 96 } rtl_chip_infos[] = { 97 /* PCI devices. */ 98 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 99 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 100 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 101 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 102 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 103 /* PCI-E devices. */ 104 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 106 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 107 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 108 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 111 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 112 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 113 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 114 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 115 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 119 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 120 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 121 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 122 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 123 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 124 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 125 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 126 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 127 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 128 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 129 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 130 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 131 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 132 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 133 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 134 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 135 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 136 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 137 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 138 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 139 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 140 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 141 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 142 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 143 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 144 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 145 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 146 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 148 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 149 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 150 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 151 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 152 }; 153 154 static const struct pci_device_id rtl8169_pci_tbl[] = { 155 { PCI_VDEVICE(REALTEK, 0x2502) }, 156 { PCI_VDEVICE(REALTEK, 0x2600) }, 157 { PCI_VDEVICE(REALTEK, 0x8129) }, 158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 159 { PCI_VDEVICE(REALTEK, 0x8161) }, 160 { PCI_VDEVICE(REALTEK, 0x8167) }, 161 { PCI_VDEVICE(REALTEK, 0x8168) }, 162 { PCI_VDEVICE(NCUBE, 0x8168) }, 163 { PCI_VDEVICE(REALTEK, 0x8169) }, 164 { PCI_VENDOR_ID_DLINK, 0x4300, 165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 166 { PCI_VDEVICE(DLINK, 0x4300) }, 167 { PCI_VDEVICE(DLINK, 0x4302) }, 168 { PCI_VDEVICE(AT, 0xc107) }, 169 { PCI_VDEVICE(USR, 0x0116) }, 170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 172 { PCI_VDEVICE(REALTEK, 0x8125) }, 173 { PCI_VDEVICE(REALTEK, 0x3000) }, 174 {} 175 }; 176 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 178 179 static struct { 180 u32 msg_enable; 181 } debug = { -1 }; 182 183 enum rtl_registers { 184 MAC0 = 0, /* Ethernet hardware address. */ 185 MAC4 = 4, 186 MAR0 = 8, /* Multicast filter. */ 187 CounterAddrLow = 0x10, 188 CounterAddrHigh = 0x14, 189 TxDescStartAddrLow = 0x20, 190 TxDescStartAddrHigh = 0x24, 191 TxHDescStartAddrLow = 0x28, 192 TxHDescStartAddrHigh = 0x2c, 193 FLASH = 0x30, 194 ERSR = 0x36, 195 ChipCmd = 0x37, 196 TxPoll = 0x38, 197 IntrMask = 0x3c, 198 IntrStatus = 0x3e, 199 200 TxConfig = 0x40, 201 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 202 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 203 204 RxConfig = 0x44, 205 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 206 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 207 #define RXCFG_FIFO_SHIFT 13 208 /* No threshold before first PCI xfer */ 209 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 210 #define RX_EARLY_OFF (1 << 11) 211 #define RXCFG_DMA_SHIFT 8 212 /* Unlimited maximum PCI burst. */ 213 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 214 215 RxMissed = 0x4c, 216 Cfg9346 = 0x50, 217 Config0 = 0x51, 218 Config1 = 0x52, 219 Config2 = 0x53, 220 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 221 222 Config3 = 0x54, 223 Config4 = 0x55, 224 Config5 = 0x56, 225 PHYAR = 0x60, 226 PHYstatus = 0x6c, 227 RxMaxSize = 0xda, 228 CPlusCmd = 0xe0, 229 IntrMitigate = 0xe2, 230 231 #define RTL_COALESCE_MASK 0x0f 232 #define RTL_COALESCE_SHIFT 4 233 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 234 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 235 236 RxDescAddrLow = 0xe4, 237 RxDescAddrHigh = 0xe8, 238 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 239 240 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 241 242 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 243 244 #define TxPacketMax (8064 >> 7) 245 #define EarlySize 0x27 246 247 FuncEvent = 0xf0, 248 FuncEventMask = 0xf4, 249 FuncPresetState = 0xf8, 250 IBCR0 = 0xf8, 251 IBCR2 = 0xf9, 252 IBIMR0 = 0xfa, 253 IBISR0 = 0xfb, 254 FuncForceEvent = 0xfc, 255 }; 256 257 enum rtl8168_8101_registers { 258 CSIDR = 0x64, 259 CSIAR = 0x68, 260 #define CSIAR_FLAG 0x80000000 261 #define CSIAR_WRITE_CMD 0x80000000 262 #define CSIAR_BYTE_ENABLE 0x0000f000 263 #define CSIAR_ADDR_MASK 0x00000fff 264 PMCH = 0x6f, 265 EPHYAR = 0x80, 266 #define EPHYAR_FLAG 0x80000000 267 #define EPHYAR_WRITE_CMD 0x80000000 268 #define EPHYAR_REG_MASK 0x1f 269 #define EPHYAR_REG_SHIFT 16 270 #define EPHYAR_DATA_MASK 0xffff 271 DLLPR = 0xd0, 272 #define PFM_EN (1 << 6) 273 #define TX_10M_PS_EN (1 << 7) 274 DBG_REG = 0xd1, 275 #define FIX_NAK_1 (1 << 4) 276 #define FIX_NAK_2 (1 << 3) 277 TWSI = 0xd2, 278 MCU = 0xd3, 279 #define NOW_IS_OOB (1 << 7) 280 #define TX_EMPTY (1 << 5) 281 #define RX_EMPTY (1 << 4) 282 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 283 #define EN_NDP (1 << 3) 284 #define EN_OOB_RESET (1 << 2) 285 #define LINK_LIST_RDY (1 << 1) 286 EFUSEAR = 0xdc, 287 #define EFUSEAR_FLAG 0x80000000 288 #define EFUSEAR_WRITE_CMD 0x80000000 289 #define EFUSEAR_READ_CMD 0x00000000 290 #define EFUSEAR_REG_MASK 0x03ff 291 #define EFUSEAR_REG_SHIFT 8 292 #define EFUSEAR_DATA_MASK 0xff 293 MISC_1 = 0xf2, 294 #define PFM_D3COLD_EN (1 << 6) 295 }; 296 297 enum rtl8168_registers { 298 LED_FREQ = 0x1a, 299 EEE_LED = 0x1b, 300 ERIDR = 0x70, 301 ERIAR = 0x74, 302 #define ERIAR_FLAG 0x80000000 303 #define ERIAR_WRITE_CMD 0x80000000 304 #define ERIAR_READ_CMD 0x00000000 305 #define ERIAR_ADDR_BYTE_ALIGN 4 306 #define ERIAR_TYPE_SHIFT 16 307 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 310 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_MASK_SHIFT 12 312 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 315 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 317 EPHY_RXER_NUM = 0x7c, 318 OCPDR = 0xb0, /* OCP GPHY access */ 319 #define OCPDR_WRITE_CMD 0x80000000 320 #define OCPDR_READ_CMD 0x00000000 321 #define OCPDR_REG_MASK 0x7f 322 #define OCPDR_GPHY_REG_SHIFT 16 323 #define OCPDR_DATA_MASK 0xffff 324 OCPAR = 0xb4, 325 #define OCPAR_FLAG 0x80000000 326 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 327 #define OCPAR_GPHY_READ_CMD 0x0000f060 328 GPHY_OCP = 0xb8, 329 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 330 MISC = 0xf0, /* 8168e only. */ 331 #define TXPLA_RST (1 << 29) 332 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 333 #define PWM_EN (1 << 22) 334 #define RXDV_GATED_EN (1 << 19) 335 #define EARLY_TALLY_EN (1 << 16) 336 }; 337 338 enum rtl8125_registers { 339 IntrMask_8125 = 0x38, 340 IntrStatus_8125 = 0x3c, 341 TxPoll_8125 = 0x90, 342 MAC0_BKP = 0x19e0, 343 }; 344 345 #define RX_VLAN_INNER_8125 BIT(22) 346 #define RX_VLAN_OUTER_8125 BIT(23) 347 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 348 349 #define RX_FETCH_DFLT_8125 (8 << 27) 350 351 enum rtl_register_content { 352 /* InterruptStatusBits */ 353 SYSErr = 0x8000, 354 PCSTimeout = 0x4000, 355 SWInt = 0x0100, 356 TxDescUnavail = 0x0080, 357 RxFIFOOver = 0x0040, 358 LinkChg = 0x0020, 359 RxOverflow = 0x0010, 360 TxErr = 0x0008, 361 TxOK = 0x0004, 362 RxErr = 0x0002, 363 RxOK = 0x0001, 364 365 /* RxStatusDesc */ 366 RxRWT = (1 << 22), 367 RxRES = (1 << 21), 368 RxRUNT = (1 << 20), 369 RxCRC = (1 << 19), 370 371 /* ChipCmdBits */ 372 StopReq = 0x80, 373 CmdReset = 0x10, 374 CmdRxEnb = 0x08, 375 CmdTxEnb = 0x04, 376 RxBufEmpty = 0x01, 377 378 /* TXPoll register p.5 */ 379 HPQ = 0x80, /* Poll cmd on the high prio queue */ 380 NPQ = 0x40, /* Poll cmd on the low prio queue */ 381 FSWInt = 0x01, /* Forced software interrupt */ 382 383 /* Cfg9346Bits */ 384 Cfg9346_Lock = 0x00, 385 Cfg9346_Unlock = 0xc0, 386 387 /* rx_mode_bits */ 388 AcceptErr = 0x20, 389 AcceptRunt = 0x10, 390 AcceptBroadcast = 0x08, 391 AcceptMulticast = 0x04, 392 AcceptMyPhys = 0x02, 393 AcceptAllPhys = 0x01, 394 #define RX_CONFIG_ACCEPT_MASK 0x3f 395 396 /* TxConfigBits */ 397 TxInterFrameGapShift = 24, 398 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 399 400 /* Config1 register p.24 */ 401 LEDS1 = (1 << 7), 402 LEDS0 = (1 << 6), 403 Speed_down = (1 << 4), 404 MEMMAP = (1 << 3), 405 IOMAP = (1 << 2), 406 VPD = (1 << 1), 407 PMEnable = (1 << 0), /* Power Management Enable */ 408 409 /* Config2 register p. 25 */ 410 ClkReqEn = (1 << 7), /* Clock Request Enable */ 411 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 412 PCI_Clock_66MHz = 0x01, 413 PCI_Clock_33MHz = 0x00, 414 415 /* Config3 register p.25 */ 416 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 417 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 418 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 419 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 420 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 421 422 /* Config4 register */ 423 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 424 425 /* Config5 register p.27 */ 426 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 427 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 428 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 429 Spi_en = (1 << 3), 430 LanWake = (1 << 1), /* LanWake enable/disable */ 431 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 432 ASPM_en = (1 << 0), /* ASPM enable */ 433 434 /* CPlusCmd p.31 */ 435 EnableBist = (1 << 15), // 8168 8101 436 Mac_dbgo_oe = (1 << 14), // 8168 8101 437 EnAnaPLL = (1 << 14), // 8169 438 Normal_mode = (1 << 13), // unused 439 Force_half_dup = (1 << 12), // 8168 8101 440 Force_rxflow_en = (1 << 11), // 8168 8101 441 Force_txflow_en = (1 << 10), // 8168 8101 442 Cxpl_dbg_sel = (1 << 9), // 8168 8101 443 ASF = (1 << 8), // 8168 8101 444 PktCntrDisable = (1 << 7), // 8168 8101 445 Mac_dbgo_sel = 0x001c, // 8168 446 RxVlan = (1 << 6), 447 RxChkSum = (1 << 5), 448 PCIDAC = (1 << 4), 449 PCIMulRW = (1 << 3), 450 #define INTT_MASK GENMASK(1, 0) 451 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 452 453 /* rtl8169_PHYstatus */ 454 TBI_Enable = 0x80, 455 TxFlowCtrl = 0x40, 456 RxFlowCtrl = 0x20, 457 _1000bpsF = 0x10, 458 _100bps = 0x08, 459 _10bps = 0x04, 460 LinkStatus = 0x02, 461 FullDup = 0x01, 462 463 /* ResetCounterCommand */ 464 CounterReset = 0x1, 465 466 /* DumpCounterCommand */ 467 CounterDump = 0x8, 468 469 /* magic enable v2 */ 470 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 471 }; 472 473 enum rtl_desc_bit { 474 /* First doubleword. */ 475 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 476 RingEnd = (1 << 30), /* End of descriptor ring */ 477 FirstFrag = (1 << 29), /* First segment of a packet */ 478 LastFrag = (1 << 28), /* Final segment of a packet */ 479 }; 480 481 /* Generic case. */ 482 enum rtl_tx_desc_bit { 483 /* First doubleword. */ 484 TD_LSO = (1 << 27), /* Large Send Offload */ 485 #define TD_MSS_MAX 0x07ffu /* MSS value */ 486 487 /* Second doubleword. */ 488 TxVlanTag = (1 << 17), /* Add VLAN tag */ 489 }; 490 491 /* 8169, 8168b and 810x except 8102e. */ 492 enum rtl_tx_desc_bit_0 { 493 /* First doubleword. */ 494 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 495 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 496 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 497 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 498 }; 499 500 /* 8102e, 8168c and beyond. */ 501 enum rtl_tx_desc_bit_1 { 502 /* First doubleword. */ 503 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 504 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 505 #define GTTCPHO_SHIFT 18 506 #define GTTCPHO_MAX 0x7f 507 508 /* Second doubleword. */ 509 #define TCPHO_SHIFT 18 510 #define TCPHO_MAX 0x3ff 511 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 512 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 513 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 514 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 515 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 516 }; 517 518 enum rtl_rx_desc_bit { 519 /* Rx private */ 520 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 521 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 522 523 #define RxProtoUDP (PID1) 524 #define RxProtoTCP (PID0) 525 #define RxProtoIP (PID1 | PID0) 526 #define RxProtoMask RxProtoIP 527 528 IPFail = (1 << 16), /* IP checksum failed */ 529 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 530 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 531 RxVlanTag = (1 << 16), /* VLAN tag available */ 532 }; 533 534 #define RsvdMask 0x3fffc000 535 536 #define RTL_GSO_MAX_SIZE_V1 32000 537 #define RTL_GSO_MAX_SEGS_V1 24 538 #define RTL_GSO_MAX_SIZE_V2 64000 539 #define RTL_GSO_MAX_SEGS_V2 64 540 541 struct TxDesc { 542 __le32 opts1; 543 __le32 opts2; 544 __le64 addr; 545 }; 546 547 struct RxDesc { 548 __le32 opts1; 549 __le32 opts2; 550 __le64 addr; 551 }; 552 553 struct ring_info { 554 struct sk_buff *skb; 555 u32 len; 556 }; 557 558 struct rtl8169_counters { 559 __le64 tx_packets; 560 __le64 rx_packets; 561 __le64 tx_errors; 562 __le32 rx_errors; 563 __le16 rx_missed; 564 __le16 align_errors; 565 __le32 tx_one_collision; 566 __le32 tx_multi_collision; 567 __le64 rx_unicast; 568 __le64 rx_broadcast; 569 __le32 rx_multicast; 570 __le16 tx_aborted; 571 __le16 tx_underun; 572 }; 573 574 struct rtl8169_tc_offsets { 575 bool inited; 576 __le64 tx_errors; 577 __le32 tx_multi_collision; 578 __le16 tx_aborted; 579 }; 580 581 enum rtl_flag { 582 RTL_FLAG_TASK_ENABLED = 0, 583 RTL_FLAG_TASK_RESET_PENDING, 584 RTL_FLAG_MAX 585 }; 586 587 struct rtl8169_stats { 588 u64 packets; 589 u64 bytes; 590 struct u64_stats_sync syncp; 591 }; 592 593 struct rtl8169_private { 594 void __iomem *mmio_addr; /* memory map physical address */ 595 struct pci_dev *pci_dev; 596 struct net_device *dev; 597 struct phy_device *phydev; 598 struct napi_struct napi; 599 u32 msg_enable; 600 enum mac_version mac_version; 601 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 602 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 603 u32 dirty_tx; 604 struct rtl8169_stats rx_stats; 605 struct rtl8169_stats tx_stats; 606 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 607 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 608 dma_addr_t TxPhyAddr; 609 dma_addr_t RxPhyAddr; 610 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 611 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 612 u16 cp_cmd; 613 u32 irq_mask; 614 struct clk *clk; 615 616 struct { 617 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 618 struct mutex mutex; 619 struct work_struct work; 620 } wk; 621 622 unsigned irq_enabled:1; 623 unsigned supports_gmii:1; 624 unsigned aspm_manageable:1; 625 dma_addr_t counters_phys_addr; 626 struct rtl8169_counters *counters; 627 struct rtl8169_tc_offsets tc_offset; 628 u32 saved_wolopts; 629 int eee_adv; 630 631 const char *fw_name; 632 struct rtl_fw *rtl_fw; 633 634 u32 ocp_base; 635 }; 636 637 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 638 639 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 640 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 641 module_param_named(debug, debug.msg_enable, int, 0); 642 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 643 MODULE_SOFTDEP("pre: realtek"); 644 MODULE_LICENSE("GPL"); 645 MODULE_FIRMWARE(FIRMWARE_8168D_1); 646 MODULE_FIRMWARE(FIRMWARE_8168D_2); 647 MODULE_FIRMWARE(FIRMWARE_8168E_1); 648 MODULE_FIRMWARE(FIRMWARE_8168E_2); 649 MODULE_FIRMWARE(FIRMWARE_8168E_3); 650 MODULE_FIRMWARE(FIRMWARE_8105E_1); 651 MODULE_FIRMWARE(FIRMWARE_8168F_1); 652 MODULE_FIRMWARE(FIRMWARE_8168F_2); 653 MODULE_FIRMWARE(FIRMWARE_8402_1); 654 MODULE_FIRMWARE(FIRMWARE_8411_1); 655 MODULE_FIRMWARE(FIRMWARE_8411_2); 656 MODULE_FIRMWARE(FIRMWARE_8106E_1); 657 MODULE_FIRMWARE(FIRMWARE_8106E_2); 658 MODULE_FIRMWARE(FIRMWARE_8168G_2); 659 MODULE_FIRMWARE(FIRMWARE_8168G_3); 660 MODULE_FIRMWARE(FIRMWARE_8168H_1); 661 MODULE_FIRMWARE(FIRMWARE_8168H_2); 662 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 663 MODULE_FIRMWARE(FIRMWARE_8107E_1); 664 MODULE_FIRMWARE(FIRMWARE_8107E_2); 665 MODULE_FIRMWARE(FIRMWARE_8125A_3); 666 667 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 668 { 669 return &tp->pci_dev->dev; 670 } 671 672 static void rtl_lock_work(struct rtl8169_private *tp) 673 { 674 mutex_lock(&tp->wk.mutex); 675 } 676 677 static void rtl_unlock_work(struct rtl8169_private *tp) 678 { 679 mutex_unlock(&tp->wk.mutex); 680 } 681 682 static void rtl_lock_config_regs(struct rtl8169_private *tp) 683 { 684 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 685 } 686 687 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 688 { 689 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 690 } 691 692 static bool rtl_is_8125(struct rtl8169_private *tp) 693 { 694 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 695 } 696 697 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 698 { 699 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 700 tp->mac_version != RTL_GIGA_MAC_VER_39 && 701 tp->mac_version <= RTL_GIGA_MAC_VER_52; 702 } 703 704 static bool rtl_supports_eee(struct rtl8169_private *tp) 705 { 706 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 707 tp->mac_version != RTL_GIGA_MAC_VER_37 && 708 tp->mac_version != RTL_GIGA_MAC_VER_39; 709 } 710 711 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 712 { 713 int i; 714 715 for (i = 0; i < ETH_ALEN; i++) 716 mac[i] = RTL_R8(tp, reg + i); 717 } 718 719 struct rtl_cond { 720 bool (*check)(struct rtl8169_private *); 721 const char *msg; 722 }; 723 724 static void rtl_udelay(unsigned int d) 725 { 726 udelay(d); 727 } 728 729 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 730 void (*delay)(unsigned int), unsigned int d, int n, 731 bool high) 732 { 733 int i; 734 735 for (i = 0; i < n; i++) { 736 if (c->check(tp) == high) 737 return true; 738 delay(d); 739 } 740 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 741 c->msg, !high, n, d); 742 return false; 743 } 744 745 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 746 const struct rtl_cond *c, 747 unsigned int d, int n) 748 { 749 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 750 } 751 752 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 753 const struct rtl_cond *c, 754 unsigned int d, int n) 755 { 756 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 757 } 758 759 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 760 const struct rtl_cond *c, 761 unsigned int d, int n) 762 { 763 return rtl_loop_wait(tp, c, msleep, d, n, true); 764 } 765 766 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 767 const struct rtl_cond *c, 768 unsigned int d, int n) 769 { 770 return rtl_loop_wait(tp, c, msleep, d, n, false); 771 } 772 773 #define DECLARE_RTL_COND(name) \ 774 static bool name ## _check(struct rtl8169_private *); \ 775 \ 776 static const struct rtl_cond name = { \ 777 .check = name ## _check, \ 778 .msg = #name \ 779 }; \ 780 \ 781 static bool name ## _check(struct rtl8169_private *tp) 782 783 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 784 { 785 if (reg & 0xffff0001) { 786 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 787 return true; 788 } 789 return false; 790 } 791 792 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 793 { 794 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 795 } 796 797 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 798 { 799 if (rtl_ocp_reg_failure(tp, reg)) 800 return; 801 802 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 803 804 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 805 } 806 807 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 808 { 809 if (rtl_ocp_reg_failure(tp, reg)) 810 return 0; 811 812 RTL_W32(tp, GPHY_OCP, reg << 15); 813 814 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 815 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 816 } 817 818 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 819 { 820 if (rtl_ocp_reg_failure(tp, reg)) 821 return; 822 823 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 824 } 825 826 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 827 { 828 if (rtl_ocp_reg_failure(tp, reg)) 829 return 0; 830 831 RTL_W32(tp, OCPDR, reg << 15); 832 833 return RTL_R32(tp, OCPDR); 834 } 835 836 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 837 u16 set) 838 { 839 u16 data = r8168_mac_ocp_read(tp, reg); 840 841 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 842 } 843 844 #define OCP_STD_PHY_BASE 0xa400 845 846 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 847 { 848 if (reg == 0x1f) { 849 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 850 return; 851 } 852 853 if (tp->ocp_base != OCP_STD_PHY_BASE) 854 reg -= 0x10; 855 856 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 857 } 858 859 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 860 { 861 if (reg == 0x1f) 862 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 863 864 if (tp->ocp_base != OCP_STD_PHY_BASE) 865 reg -= 0x10; 866 867 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 868 } 869 870 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 871 { 872 if (reg == 0x1f) { 873 tp->ocp_base = value << 4; 874 return; 875 } 876 877 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 878 } 879 880 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 881 { 882 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 883 } 884 885 DECLARE_RTL_COND(rtl_phyar_cond) 886 { 887 return RTL_R32(tp, PHYAR) & 0x80000000; 888 } 889 890 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 891 { 892 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 893 894 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 895 /* 896 * According to hardware specs a 20us delay is required after write 897 * complete indication, but before sending next command. 898 */ 899 udelay(20); 900 } 901 902 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 903 { 904 int value; 905 906 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 907 908 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 909 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 910 911 /* 912 * According to hardware specs a 20us delay is required after read 913 * complete indication, but before sending next command. 914 */ 915 udelay(20); 916 917 return value; 918 } 919 920 DECLARE_RTL_COND(rtl_ocpar_cond) 921 { 922 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 923 } 924 925 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 926 { 927 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 928 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 929 RTL_W32(tp, EPHY_RXER_NUM, 0); 930 931 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 932 } 933 934 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 935 { 936 r8168dp_1_mdio_access(tp, reg, 937 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 938 } 939 940 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 941 { 942 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 943 944 mdelay(1); 945 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 946 RTL_W32(tp, EPHY_RXER_NUM, 0); 947 948 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 949 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 950 } 951 952 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 953 954 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 955 { 956 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 957 } 958 959 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 960 { 961 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 962 } 963 964 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 965 { 966 r8168dp_2_mdio_start(tp); 967 968 r8169_mdio_write(tp, reg, value); 969 970 r8168dp_2_mdio_stop(tp); 971 } 972 973 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 974 { 975 int value; 976 977 /* Work around issue with chip reporting wrong PHY ID */ 978 if (reg == MII_PHYSID2) 979 return 0xc912; 980 981 r8168dp_2_mdio_start(tp); 982 983 value = r8169_mdio_read(tp, reg); 984 985 r8168dp_2_mdio_stop(tp); 986 987 return value; 988 } 989 990 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 991 { 992 switch (tp->mac_version) { 993 case RTL_GIGA_MAC_VER_27: 994 r8168dp_1_mdio_write(tp, location, val); 995 break; 996 case RTL_GIGA_MAC_VER_28: 997 case RTL_GIGA_MAC_VER_31: 998 r8168dp_2_mdio_write(tp, location, val); 999 break; 1000 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1001 r8168g_mdio_write(tp, location, val); 1002 break; 1003 default: 1004 r8169_mdio_write(tp, location, val); 1005 break; 1006 } 1007 } 1008 1009 static int rtl_readphy(struct rtl8169_private *tp, int location) 1010 { 1011 switch (tp->mac_version) { 1012 case RTL_GIGA_MAC_VER_27: 1013 return r8168dp_1_mdio_read(tp, location); 1014 case RTL_GIGA_MAC_VER_28: 1015 case RTL_GIGA_MAC_VER_31: 1016 return r8168dp_2_mdio_read(tp, location); 1017 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1018 return r8168g_mdio_read(tp, location); 1019 default: 1020 return r8169_mdio_read(tp, location); 1021 } 1022 } 1023 1024 DECLARE_RTL_COND(rtl_ephyar_cond) 1025 { 1026 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1027 } 1028 1029 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1030 { 1031 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1032 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1033 1034 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1035 1036 udelay(10); 1037 } 1038 1039 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1040 { 1041 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1042 1043 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1044 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1045 } 1046 1047 DECLARE_RTL_COND(rtl_eriar_cond) 1048 { 1049 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1050 } 1051 1052 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1053 u32 val, int type) 1054 { 1055 BUG_ON((addr & 3) || (mask == 0)); 1056 RTL_W32(tp, ERIDR, val); 1057 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1058 1059 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1060 } 1061 1062 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1063 u32 val) 1064 { 1065 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1066 } 1067 1068 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1069 { 1070 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1071 1072 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1073 RTL_R32(tp, ERIDR) : ~0; 1074 } 1075 1076 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1077 { 1078 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1079 } 1080 1081 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1082 u32 m) 1083 { 1084 u32 val; 1085 1086 val = rtl_eri_read(tp, addr); 1087 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1088 } 1089 1090 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1091 u32 p) 1092 { 1093 rtl_w0w1_eri(tp, addr, mask, p, 0); 1094 } 1095 1096 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1097 u32 m) 1098 { 1099 rtl_w0w1_eri(tp, addr, mask, 0, m); 1100 } 1101 1102 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1103 { 1104 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1105 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1106 RTL_R32(tp, OCPDR) : ~0; 1107 } 1108 1109 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1110 { 1111 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1112 } 1113 1114 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1115 u32 data) 1116 { 1117 RTL_W32(tp, OCPDR, data); 1118 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1119 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1120 } 1121 1122 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1123 u32 data) 1124 { 1125 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1126 data, ERIAR_OOB); 1127 } 1128 1129 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1130 { 1131 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1132 1133 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1134 } 1135 1136 #define OOB_CMD_RESET 0x00 1137 #define OOB_CMD_DRIVER_START 0x05 1138 #define OOB_CMD_DRIVER_STOP 0x06 1139 1140 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1141 { 1142 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1143 } 1144 1145 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1146 { 1147 u16 reg; 1148 1149 reg = rtl8168_get_ocp_reg(tp); 1150 1151 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1152 } 1153 1154 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1155 { 1156 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1157 } 1158 1159 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1160 { 1161 return RTL_R8(tp, IBISR0) & 0x20; 1162 } 1163 1164 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1165 { 1166 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1167 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1168 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1169 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1170 } 1171 1172 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1173 { 1174 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1175 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1176 } 1177 1178 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1179 { 1180 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1181 r8168ep_ocp_write(tp, 0x01, 0x30, 1182 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1183 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1184 } 1185 1186 static void rtl8168_driver_start(struct rtl8169_private *tp) 1187 { 1188 switch (tp->mac_version) { 1189 case RTL_GIGA_MAC_VER_27: 1190 case RTL_GIGA_MAC_VER_28: 1191 case RTL_GIGA_MAC_VER_31: 1192 rtl8168dp_driver_start(tp); 1193 break; 1194 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1195 rtl8168ep_driver_start(tp); 1196 break; 1197 default: 1198 BUG(); 1199 break; 1200 } 1201 } 1202 1203 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1204 { 1205 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1206 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1207 } 1208 1209 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1210 { 1211 rtl8168ep_stop_cmac(tp); 1212 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1213 r8168ep_ocp_write(tp, 0x01, 0x30, 1214 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1215 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1216 } 1217 1218 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1219 { 1220 switch (tp->mac_version) { 1221 case RTL_GIGA_MAC_VER_27: 1222 case RTL_GIGA_MAC_VER_28: 1223 case RTL_GIGA_MAC_VER_31: 1224 rtl8168dp_driver_stop(tp); 1225 break; 1226 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1227 rtl8168ep_driver_stop(tp); 1228 break; 1229 default: 1230 BUG(); 1231 break; 1232 } 1233 } 1234 1235 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1236 { 1237 u16 reg = rtl8168_get_ocp_reg(tp); 1238 1239 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1240 } 1241 1242 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1243 { 1244 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1245 } 1246 1247 static bool r8168_check_dash(struct rtl8169_private *tp) 1248 { 1249 switch (tp->mac_version) { 1250 case RTL_GIGA_MAC_VER_27: 1251 case RTL_GIGA_MAC_VER_28: 1252 case RTL_GIGA_MAC_VER_31: 1253 return r8168dp_check_dash(tp); 1254 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1255 return r8168ep_check_dash(tp); 1256 default: 1257 return false; 1258 } 1259 } 1260 1261 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1262 { 1263 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1264 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1265 } 1266 1267 DECLARE_RTL_COND(rtl_efusear_cond) 1268 { 1269 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1270 } 1271 1272 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1273 { 1274 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1275 1276 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1277 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1278 } 1279 1280 static u32 rtl_get_events(struct rtl8169_private *tp) 1281 { 1282 if (rtl_is_8125(tp)) 1283 return RTL_R32(tp, IntrStatus_8125); 1284 else 1285 return RTL_R16(tp, IntrStatus); 1286 } 1287 1288 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1289 { 1290 if (rtl_is_8125(tp)) 1291 RTL_W32(tp, IntrStatus_8125, bits); 1292 else 1293 RTL_W16(tp, IntrStatus, bits); 1294 } 1295 1296 static void rtl_irq_disable(struct rtl8169_private *tp) 1297 { 1298 if (rtl_is_8125(tp)) 1299 RTL_W32(tp, IntrMask_8125, 0); 1300 else 1301 RTL_W16(tp, IntrMask, 0); 1302 tp->irq_enabled = 0; 1303 } 1304 1305 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) 1306 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) 1307 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) 1308 1309 static void rtl_irq_enable(struct rtl8169_private *tp) 1310 { 1311 tp->irq_enabled = 1; 1312 if (rtl_is_8125(tp)) 1313 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1314 else 1315 RTL_W16(tp, IntrMask, tp->irq_mask); 1316 } 1317 1318 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1319 { 1320 rtl_irq_disable(tp); 1321 rtl_ack_events(tp, 0xffffffff); 1322 /* PCI commit */ 1323 RTL_R8(tp, ChipCmd); 1324 } 1325 1326 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1327 { 1328 struct net_device *dev = tp->dev; 1329 struct phy_device *phydev = tp->phydev; 1330 1331 if (!netif_running(dev)) 1332 return; 1333 1334 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1335 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1336 if (phydev->speed == SPEED_1000) { 1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1339 } else if (phydev->speed == SPEED_100) { 1340 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1341 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1342 } else { 1343 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1344 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1345 } 1346 rtl_reset_packet_filter(tp); 1347 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1348 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1349 if (phydev->speed == SPEED_1000) { 1350 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1351 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1352 } else { 1353 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1354 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1355 } 1356 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1357 if (phydev->speed == SPEED_10) { 1358 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1359 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1360 } else { 1361 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1362 } 1363 } 1364 } 1365 1366 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1367 1368 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1369 { 1370 struct rtl8169_private *tp = netdev_priv(dev); 1371 1372 rtl_lock_work(tp); 1373 wol->supported = WAKE_ANY; 1374 wol->wolopts = tp->saved_wolopts; 1375 rtl_unlock_work(tp); 1376 } 1377 1378 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1379 { 1380 static const struct { 1381 u32 opt; 1382 u16 reg; 1383 u8 mask; 1384 } cfg[] = { 1385 { WAKE_PHY, Config3, LinkUp }, 1386 { WAKE_UCAST, Config5, UWF }, 1387 { WAKE_BCAST, Config5, BWF }, 1388 { WAKE_MCAST, Config5, MWF }, 1389 { WAKE_ANY, Config5, LanWake }, 1390 { WAKE_MAGIC, Config3, MagicPacket } 1391 }; 1392 unsigned int i, tmp = ARRAY_SIZE(cfg); 1393 u8 options; 1394 1395 rtl_unlock_config_regs(tp); 1396 1397 if (rtl_is_8168evl_up(tp)) { 1398 tmp--; 1399 if (wolopts & WAKE_MAGIC) 1400 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1401 MagicPacket_v2); 1402 else 1403 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1404 MagicPacket_v2); 1405 } else if (rtl_is_8125(tp)) { 1406 tmp--; 1407 if (wolopts & WAKE_MAGIC) 1408 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1409 else 1410 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1411 } 1412 1413 for (i = 0; i < tmp; i++) { 1414 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1415 if (wolopts & cfg[i].opt) 1416 options |= cfg[i].mask; 1417 RTL_W8(tp, cfg[i].reg, options); 1418 } 1419 1420 switch (tp->mac_version) { 1421 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1422 options = RTL_R8(tp, Config1) & ~PMEnable; 1423 if (wolopts) 1424 options |= PMEnable; 1425 RTL_W8(tp, Config1, options); 1426 break; 1427 case RTL_GIGA_MAC_VER_34: 1428 case RTL_GIGA_MAC_VER_37: 1429 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52: 1430 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1431 if (wolopts) 1432 options |= PME_SIGNAL; 1433 RTL_W8(tp, Config2, options); 1434 break; 1435 default: 1436 break; 1437 } 1438 1439 rtl_lock_config_regs(tp); 1440 1441 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1442 tp->dev->wol_enabled = wolopts ? 1 : 0; 1443 } 1444 1445 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1446 { 1447 struct rtl8169_private *tp = netdev_priv(dev); 1448 struct device *d = tp_to_dev(tp); 1449 1450 if (wol->wolopts & ~WAKE_ANY) 1451 return -EINVAL; 1452 1453 pm_runtime_get_noresume(d); 1454 1455 rtl_lock_work(tp); 1456 1457 tp->saved_wolopts = wol->wolopts; 1458 1459 if (pm_runtime_active(d)) 1460 __rtl8169_set_wol(tp, tp->saved_wolopts); 1461 1462 rtl_unlock_work(tp); 1463 1464 pm_runtime_put_noidle(d); 1465 1466 return 0; 1467 } 1468 1469 static void rtl8169_get_drvinfo(struct net_device *dev, 1470 struct ethtool_drvinfo *info) 1471 { 1472 struct rtl8169_private *tp = netdev_priv(dev); 1473 struct rtl_fw *rtl_fw = tp->rtl_fw; 1474 1475 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1476 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1477 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1478 if (rtl_fw) 1479 strlcpy(info->fw_version, rtl_fw->version, 1480 sizeof(info->fw_version)); 1481 } 1482 1483 static int rtl8169_get_regs_len(struct net_device *dev) 1484 { 1485 return R8169_REGS_SIZE; 1486 } 1487 1488 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1489 netdev_features_t features) 1490 { 1491 struct rtl8169_private *tp = netdev_priv(dev); 1492 1493 if (dev->mtu > TD_MSS_MAX) 1494 features &= ~NETIF_F_ALL_TSO; 1495 1496 if (dev->mtu > ETH_DATA_LEN && 1497 tp->mac_version > RTL_GIGA_MAC_VER_06) 1498 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1499 1500 return features; 1501 } 1502 1503 static int rtl8169_set_features(struct net_device *dev, 1504 netdev_features_t features) 1505 { 1506 struct rtl8169_private *tp = netdev_priv(dev); 1507 u32 rx_config; 1508 1509 rtl_lock_work(tp); 1510 1511 rx_config = RTL_R32(tp, RxConfig); 1512 if (features & NETIF_F_RXALL) 1513 rx_config |= (AcceptErr | AcceptRunt); 1514 else 1515 rx_config &= ~(AcceptErr | AcceptRunt); 1516 1517 if (rtl_is_8125(tp)) { 1518 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1519 rx_config |= RX_VLAN_8125; 1520 else 1521 rx_config &= ~RX_VLAN_8125; 1522 } 1523 1524 RTL_W32(tp, RxConfig, rx_config); 1525 1526 if (features & NETIF_F_RXCSUM) 1527 tp->cp_cmd |= RxChkSum; 1528 else 1529 tp->cp_cmd &= ~RxChkSum; 1530 1531 if (!rtl_is_8125(tp)) { 1532 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1533 tp->cp_cmd |= RxVlan; 1534 else 1535 tp->cp_cmd &= ~RxVlan; 1536 } 1537 1538 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1539 RTL_R16(tp, CPlusCmd); 1540 1541 rtl_unlock_work(tp); 1542 1543 return 0; 1544 } 1545 1546 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1547 { 1548 return (skb_vlan_tag_present(skb)) ? 1549 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1550 } 1551 1552 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1553 { 1554 u32 opts2 = le32_to_cpu(desc->opts2); 1555 1556 if (opts2 & RxVlanTag) 1557 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1558 } 1559 1560 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1561 void *p) 1562 { 1563 struct rtl8169_private *tp = netdev_priv(dev); 1564 u32 __iomem *data = tp->mmio_addr; 1565 u32 *dw = p; 1566 int i; 1567 1568 rtl_lock_work(tp); 1569 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1570 memcpy_fromio(dw++, data++, 4); 1571 rtl_unlock_work(tp); 1572 } 1573 1574 static u32 rtl8169_get_msglevel(struct net_device *dev) 1575 { 1576 struct rtl8169_private *tp = netdev_priv(dev); 1577 1578 return tp->msg_enable; 1579 } 1580 1581 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1582 { 1583 struct rtl8169_private *tp = netdev_priv(dev); 1584 1585 tp->msg_enable = value; 1586 } 1587 1588 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1589 "tx_packets", 1590 "rx_packets", 1591 "tx_errors", 1592 "rx_errors", 1593 "rx_missed", 1594 "align_errors", 1595 "tx_single_collisions", 1596 "tx_multi_collisions", 1597 "unicast", 1598 "broadcast", 1599 "multicast", 1600 "tx_aborted", 1601 "tx_underrun", 1602 }; 1603 1604 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1605 { 1606 switch (sset) { 1607 case ETH_SS_STATS: 1608 return ARRAY_SIZE(rtl8169_gstrings); 1609 default: 1610 return -EOPNOTSUPP; 1611 } 1612 } 1613 1614 DECLARE_RTL_COND(rtl_counters_cond) 1615 { 1616 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1617 } 1618 1619 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1620 { 1621 dma_addr_t paddr = tp->counters_phys_addr; 1622 u32 cmd; 1623 1624 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1625 RTL_R32(tp, CounterAddrHigh); 1626 cmd = (u64)paddr & DMA_BIT_MASK(32); 1627 RTL_W32(tp, CounterAddrLow, cmd); 1628 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1629 1630 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1631 } 1632 1633 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1634 { 1635 /* 1636 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1637 * tally counters. 1638 */ 1639 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1640 return true; 1641 1642 return rtl8169_do_counters(tp, CounterReset); 1643 } 1644 1645 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1646 { 1647 u8 val = RTL_R8(tp, ChipCmd); 1648 1649 /* 1650 * Some chips are unable to dump tally counters when the receiver 1651 * is disabled. If 0xff chip may be in a PCI power-save state. 1652 */ 1653 if (!(val & CmdRxEnb) || val == 0xff) 1654 return true; 1655 1656 return rtl8169_do_counters(tp, CounterDump); 1657 } 1658 1659 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1660 { 1661 struct rtl8169_counters *counters = tp->counters; 1662 bool ret = false; 1663 1664 /* 1665 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1666 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1667 * reset by a power cycle, while the counter values collected by the 1668 * driver are reset at every driver unload/load cycle. 1669 * 1670 * To make sure the HW values returned by @get_stats64 match the SW 1671 * values, we collect the initial values at first open(*) and use them 1672 * as offsets to normalize the values returned by @get_stats64. 1673 * 1674 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1675 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1676 * set at open time by rtl_hw_start. 1677 */ 1678 1679 if (tp->tc_offset.inited) 1680 return true; 1681 1682 /* If both, reset and update fail, propagate to caller. */ 1683 if (rtl8169_reset_counters(tp)) 1684 ret = true; 1685 1686 if (rtl8169_update_counters(tp)) 1687 ret = true; 1688 1689 tp->tc_offset.tx_errors = counters->tx_errors; 1690 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1691 tp->tc_offset.tx_aborted = counters->tx_aborted; 1692 tp->tc_offset.inited = true; 1693 1694 return ret; 1695 } 1696 1697 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1698 struct ethtool_stats *stats, u64 *data) 1699 { 1700 struct rtl8169_private *tp = netdev_priv(dev); 1701 struct device *d = tp_to_dev(tp); 1702 struct rtl8169_counters *counters = tp->counters; 1703 1704 ASSERT_RTNL(); 1705 1706 pm_runtime_get_noresume(d); 1707 1708 if (pm_runtime_active(d)) 1709 rtl8169_update_counters(tp); 1710 1711 pm_runtime_put_noidle(d); 1712 1713 data[0] = le64_to_cpu(counters->tx_packets); 1714 data[1] = le64_to_cpu(counters->rx_packets); 1715 data[2] = le64_to_cpu(counters->tx_errors); 1716 data[3] = le32_to_cpu(counters->rx_errors); 1717 data[4] = le16_to_cpu(counters->rx_missed); 1718 data[5] = le16_to_cpu(counters->align_errors); 1719 data[6] = le32_to_cpu(counters->tx_one_collision); 1720 data[7] = le32_to_cpu(counters->tx_multi_collision); 1721 data[8] = le64_to_cpu(counters->rx_unicast); 1722 data[9] = le64_to_cpu(counters->rx_broadcast); 1723 data[10] = le32_to_cpu(counters->rx_multicast); 1724 data[11] = le16_to_cpu(counters->tx_aborted); 1725 data[12] = le16_to_cpu(counters->tx_underun); 1726 } 1727 1728 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1729 { 1730 switch(stringset) { 1731 case ETH_SS_STATS: 1732 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1733 break; 1734 } 1735 } 1736 1737 /* 1738 * Interrupt coalescing 1739 * 1740 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1741 * > 8169, 8168 and 810x line of chipsets 1742 * 1743 * 8169, 8168, and 8136(810x) serial chipsets support it. 1744 * 1745 * > 2 - the Tx timer unit at gigabit speed 1746 * 1747 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1748 * (0xe0) bit 1 and bit 0. 1749 * 1750 * For 8169 1751 * bit[1:0] \ speed 1000M 100M 10M 1752 * 0 0 320ns 2.56us 40.96us 1753 * 0 1 2.56us 20.48us 327.7us 1754 * 1 0 5.12us 40.96us 655.4us 1755 * 1 1 10.24us 81.92us 1.31ms 1756 * 1757 * For the other 1758 * bit[1:0] \ speed 1000M 100M 10M 1759 * 0 0 5us 2.56us 40.96us 1760 * 0 1 40us 20.48us 327.7us 1761 * 1 0 80us 40.96us 655.4us 1762 * 1 1 160us 81.92us 1.31ms 1763 */ 1764 1765 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1766 struct rtl_coalesce_scale { 1767 /* Rx / Tx */ 1768 u32 nsecs[2]; 1769 }; 1770 1771 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1772 struct rtl_coalesce_info { 1773 u32 speed; 1774 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1775 }; 1776 1777 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1778 #define rxtx_x1822(r, t) { \ 1779 {{(r), (t)}}, \ 1780 {{(r)*8, (t)*8}}, \ 1781 {{(r)*8*2, (t)*8*2}}, \ 1782 {{(r)*8*2*2, (t)*8*2*2}}, \ 1783 } 1784 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1785 /* speed delays: rx00 tx00 */ 1786 { SPEED_10, rxtx_x1822(40960, 40960) }, 1787 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1788 { SPEED_1000, rxtx_x1822( 320, 320) }, 1789 { 0 }, 1790 }; 1791 1792 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1793 /* speed delays: rx00 tx00 */ 1794 { SPEED_10, rxtx_x1822(40960, 40960) }, 1795 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1796 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1797 { 0 }, 1798 }; 1799 #undef rxtx_x1822 1800 1801 /* get rx/tx scale vector corresponding to current speed */ 1802 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1803 { 1804 struct rtl8169_private *tp = netdev_priv(dev); 1805 const struct rtl_coalesce_info *ci; 1806 1807 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1808 ci = rtl_coalesce_info_8169; 1809 else 1810 ci = rtl_coalesce_info_8168_8136; 1811 1812 for (; ci->speed; ci++) { 1813 if (tp->phydev->speed == ci->speed) 1814 return ci; 1815 } 1816 1817 return ERR_PTR(-ELNRNG); 1818 } 1819 1820 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1821 { 1822 struct rtl8169_private *tp = netdev_priv(dev); 1823 const struct rtl_coalesce_info *ci; 1824 const struct rtl_coalesce_scale *scale; 1825 struct { 1826 u32 *max_frames; 1827 u32 *usecs; 1828 } coal_settings [] = { 1829 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1830 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1831 }, *p = coal_settings; 1832 int i; 1833 u16 w; 1834 1835 if (rtl_is_8125(tp)) 1836 return -EOPNOTSUPP; 1837 1838 memset(ec, 0, sizeof(*ec)); 1839 1840 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1841 ci = rtl_coalesce_info(dev); 1842 if (IS_ERR(ci)) 1843 return PTR_ERR(ci); 1844 1845 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1846 1847 /* read IntrMitigate and adjust according to scale */ 1848 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1849 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1850 w >>= RTL_COALESCE_SHIFT; 1851 *p->usecs = w & RTL_COALESCE_MASK; 1852 } 1853 1854 for (i = 0; i < 2; i++) { 1855 p = coal_settings + i; 1856 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1857 1858 /* 1859 * ethtool_coalesce says it is illegal to set both usecs and 1860 * max_frames to 0. 1861 */ 1862 if (!*p->usecs && !*p->max_frames) 1863 *p->max_frames = 1; 1864 } 1865 1866 return 0; 1867 } 1868 1869 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1870 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1871 struct net_device *dev, u32 nsec, u16 *cp01) 1872 { 1873 const struct rtl_coalesce_info *ci; 1874 u16 i; 1875 1876 ci = rtl_coalesce_info(dev); 1877 if (IS_ERR(ci)) 1878 return ERR_CAST(ci); 1879 1880 for (i = 0; i < 4; i++) { 1881 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1882 ci->scalev[i].nsecs[1]); 1883 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1884 *cp01 = i; 1885 return &ci->scalev[i]; 1886 } 1887 } 1888 1889 return ERR_PTR(-EINVAL); 1890 } 1891 1892 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1893 { 1894 struct rtl8169_private *tp = netdev_priv(dev); 1895 const struct rtl_coalesce_scale *scale; 1896 struct { 1897 u32 frames; 1898 u32 usecs; 1899 } coal_settings [] = { 1900 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 1901 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 1902 }, *p = coal_settings; 1903 u16 w = 0, cp01; 1904 int i; 1905 1906 if (rtl_is_8125(tp)) 1907 return -EOPNOTSUPP; 1908 1909 scale = rtl_coalesce_choose_scale(dev, 1910 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 1911 if (IS_ERR(scale)) 1912 return PTR_ERR(scale); 1913 1914 for (i = 0; i < 2; i++, p++) { 1915 u32 units; 1916 1917 /* 1918 * accept max_frames=1 we returned in rtl_get_coalesce. 1919 * accept it not only when usecs=0 because of e.g. the following scenario: 1920 * 1921 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1922 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1923 * - then user does `ethtool -C eth0 rx-usecs 100` 1924 * 1925 * since ethtool sends to kernel whole ethtool_coalesce 1926 * settings, if we do not handle rx_usecs=!0, rx_frames=1 1927 * we'll reject it below in `frames % 4 != 0`. 1928 */ 1929 if (p->frames == 1) { 1930 p->frames = 0; 1931 } 1932 1933 units = p->usecs * 1000 / scale->nsecs[i]; 1934 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 1935 return -EINVAL; 1936 1937 w <<= RTL_COALESCE_SHIFT; 1938 w |= units; 1939 w <<= RTL_COALESCE_SHIFT; 1940 w |= p->frames >> 2; 1941 } 1942 1943 rtl_lock_work(tp); 1944 1945 RTL_W16(tp, IntrMitigate, swab16(w)); 1946 1947 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1948 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1949 RTL_R16(tp, CPlusCmd); 1950 1951 rtl_unlock_work(tp); 1952 1953 return 0; 1954 } 1955 1956 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1957 { 1958 struct rtl8169_private *tp = netdev_priv(dev); 1959 struct device *d = tp_to_dev(tp); 1960 int ret; 1961 1962 if (!rtl_supports_eee(tp)) 1963 return -EOPNOTSUPP; 1964 1965 pm_runtime_get_noresume(d); 1966 1967 if (!pm_runtime_active(d)) { 1968 ret = -EOPNOTSUPP; 1969 } else { 1970 ret = phy_ethtool_get_eee(tp->phydev, data); 1971 } 1972 1973 pm_runtime_put_noidle(d); 1974 1975 return ret; 1976 } 1977 1978 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1979 { 1980 struct rtl8169_private *tp = netdev_priv(dev); 1981 struct device *d = tp_to_dev(tp); 1982 int ret; 1983 1984 if (!rtl_supports_eee(tp)) 1985 return -EOPNOTSUPP; 1986 1987 pm_runtime_get_noresume(d); 1988 1989 if (!pm_runtime_active(d)) { 1990 ret = -EOPNOTSUPP; 1991 goto out; 1992 } 1993 1994 if (dev->phydev->autoneg == AUTONEG_DISABLE || 1995 dev->phydev->duplex != DUPLEX_FULL) { 1996 ret = -EPROTONOSUPPORT; 1997 goto out; 1998 } 1999 2000 ret = phy_ethtool_set_eee(tp->phydev, data); 2001 2002 if (!ret) 2003 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 2004 MDIO_AN_EEE_ADV); 2005 out: 2006 pm_runtime_put_noidle(d); 2007 return ret; 2008 } 2009 2010 static const struct ethtool_ops rtl8169_ethtool_ops = { 2011 .get_drvinfo = rtl8169_get_drvinfo, 2012 .get_regs_len = rtl8169_get_regs_len, 2013 .get_link = ethtool_op_get_link, 2014 .get_coalesce = rtl_get_coalesce, 2015 .set_coalesce = rtl_set_coalesce, 2016 .get_msglevel = rtl8169_get_msglevel, 2017 .set_msglevel = rtl8169_set_msglevel, 2018 .get_regs = rtl8169_get_regs, 2019 .get_wol = rtl8169_get_wol, 2020 .set_wol = rtl8169_set_wol, 2021 .get_strings = rtl8169_get_strings, 2022 .get_sset_count = rtl8169_get_sset_count, 2023 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2024 .get_ts_info = ethtool_op_get_ts_info, 2025 .nway_reset = phy_ethtool_nway_reset, 2026 .get_eee = rtl8169_get_eee, 2027 .set_eee = rtl8169_set_eee, 2028 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2029 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2030 }; 2031 2032 static void rtl_enable_eee(struct rtl8169_private *tp) 2033 { 2034 struct phy_device *phydev = tp->phydev; 2035 int adv; 2036 2037 /* respect EEE advertisement the user may have set */ 2038 if (tp->eee_adv >= 0) 2039 adv = tp->eee_adv; 2040 else 2041 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2042 2043 if (adv >= 0) 2044 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2045 } 2046 2047 static void rtl8169_get_mac_version(struct rtl8169_private *tp) 2048 { 2049 /* 2050 * The driver currently handles the 8168Bf and the 8168Be identically 2051 * but they can be identified more specifically through the test below 2052 * if needed: 2053 * 2054 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2055 * 2056 * Same thing for the 8101Eb and the 8101Ec: 2057 * 2058 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2059 */ 2060 static const struct rtl_mac_info { 2061 u16 mask; 2062 u16 val; 2063 u16 mac_version; 2064 } mac_info[] = { 2065 /* 8125 family. */ 2066 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2067 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2068 2069 /* RTL8117 */ 2070 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2071 2072 /* 8168EP family. */ 2073 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2074 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2075 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2076 2077 /* 8168H family. */ 2078 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2079 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2080 2081 /* 8168G family. */ 2082 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2083 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2084 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2085 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2086 2087 /* 8168F family. */ 2088 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2089 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2090 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2091 2092 /* 8168E family. */ 2093 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2094 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2095 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2096 2097 /* 8168D family. */ 2098 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2099 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2100 2101 /* 8168DP family. */ 2102 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2103 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2104 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2105 2106 /* 8168C family. */ 2107 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2108 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2109 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2110 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2111 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2112 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2113 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2114 2115 /* 8168B family. */ 2116 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2117 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2118 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2119 2120 /* 8101 family. */ 2121 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2122 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2123 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2124 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2125 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2126 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2127 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2128 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2129 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2130 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2131 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2132 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2133 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2134 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2135 /* FIXME: where did these entries come from ? -- FR */ 2136 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2137 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2138 2139 /* 8110 family. */ 2140 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2141 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2142 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2143 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2144 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2145 2146 /* Catch-all */ 2147 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2148 }; 2149 const struct rtl_mac_info *p = mac_info; 2150 u16 reg = RTL_R32(tp, TxConfig) >> 20; 2151 2152 while ((reg & p->mask) != p->val) 2153 p++; 2154 tp->mac_version = p->mac_version; 2155 2156 if (tp->mac_version == RTL_GIGA_MAC_NONE) { 2157 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf); 2158 } else if (!tp->supports_gmii) { 2159 if (tp->mac_version == RTL_GIGA_MAC_VER_42) 2160 tp->mac_version = RTL_GIGA_MAC_VER_43; 2161 else if (tp->mac_version == RTL_GIGA_MAC_VER_45) 2162 tp->mac_version = RTL_GIGA_MAC_VER_47; 2163 else if (tp->mac_version == RTL_GIGA_MAC_VER_46) 2164 tp->mac_version = RTL_GIGA_MAC_VER_48; 2165 } 2166 } 2167 2168 static void rtl_release_firmware(struct rtl8169_private *tp) 2169 { 2170 if (tp->rtl_fw) { 2171 rtl_fw_release_firmware(tp->rtl_fw); 2172 kfree(tp->rtl_fw); 2173 tp->rtl_fw = NULL; 2174 } 2175 } 2176 2177 void r8169_apply_firmware(struct rtl8169_private *tp) 2178 { 2179 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2180 if (tp->rtl_fw) 2181 rtl_fw_write_firmware(tp, tp->rtl_fw); 2182 } 2183 2184 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2185 { 2186 /* Adjust EEE LED frequency */ 2187 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2188 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2189 2190 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2191 } 2192 2193 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2194 { 2195 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2196 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2197 } 2198 2199 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2200 { 2201 const u16 w[] = { 2202 addr[0] | (addr[1] << 8), 2203 addr[2] | (addr[3] << 8), 2204 addr[4] | (addr[5] << 8) 2205 }; 2206 2207 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2208 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2209 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2210 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2211 } 2212 2213 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2214 { 2215 u16 data1, data2, ioffset; 2216 2217 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2218 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2219 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2220 2221 ioffset = (data2 >> 1) & 0x7ff8; 2222 ioffset |= data2 & 0x0007; 2223 if (data1 & BIT(7)) 2224 ioffset |= BIT(15); 2225 2226 return ioffset; 2227 } 2228 2229 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2230 { 2231 if (!test_and_set_bit(flag, tp->wk.flags)) 2232 schedule_work(&tp->wk.work); 2233 } 2234 2235 static void rtl8169_init_phy(struct rtl8169_private *tp) 2236 { 2237 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2238 2239 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2240 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2241 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2242 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2243 RTL_W8(tp, 0x82, 0x01); 2244 } 2245 2246 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2247 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2248 tp->pci_dev->subsystem_device == 0xe000) 2249 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2250 2251 /* We may have called phy_speed_down before */ 2252 phy_speed_up(tp->phydev); 2253 2254 if (rtl_supports_eee(tp)) 2255 rtl_enable_eee(tp); 2256 2257 genphy_soft_reset(tp->phydev); 2258 } 2259 2260 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2261 { 2262 rtl_lock_work(tp); 2263 2264 rtl_unlock_config_regs(tp); 2265 2266 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2267 RTL_R32(tp, MAC4); 2268 2269 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2270 RTL_R32(tp, MAC0); 2271 2272 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2273 rtl_rar_exgmac_set(tp, addr); 2274 2275 rtl_lock_config_regs(tp); 2276 2277 rtl_unlock_work(tp); 2278 } 2279 2280 static int rtl_set_mac_address(struct net_device *dev, void *p) 2281 { 2282 struct rtl8169_private *tp = netdev_priv(dev); 2283 struct device *d = tp_to_dev(tp); 2284 int ret; 2285 2286 ret = eth_mac_addr(dev, p); 2287 if (ret) 2288 return ret; 2289 2290 pm_runtime_get_noresume(d); 2291 2292 if (pm_runtime_active(d)) 2293 rtl_rar_set(tp, dev->dev_addr); 2294 2295 pm_runtime_put_noidle(d); 2296 2297 return 0; 2298 } 2299 2300 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2301 { 2302 switch (tp->mac_version) { 2303 case RTL_GIGA_MAC_VER_25: 2304 case RTL_GIGA_MAC_VER_26: 2305 case RTL_GIGA_MAC_VER_29: 2306 case RTL_GIGA_MAC_VER_30: 2307 case RTL_GIGA_MAC_VER_32: 2308 case RTL_GIGA_MAC_VER_33: 2309 case RTL_GIGA_MAC_VER_34: 2310 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61: 2311 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2312 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2313 break; 2314 default: 2315 break; 2316 } 2317 } 2318 2319 static void rtl_pll_power_down(struct rtl8169_private *tp) 2320 { 2321 if (r8168_check_dash(tp)) 2322 return; 2323 2324 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2325 tp->mac_version == RTL_GIGA_MAC_VER_33) 2326 rtl_ephy_write(tp, 0x19, 0xff64); 2327 2328 if (device_may_wakeup(tp_to_dev(tp))) { 2329 phy_speed_down(tp->phydev, false); 2330 rtl_wol_suspend_quirk(tp); 2331 return; 2332 } 2333 2334 switch (tp->mac_version) { 2335 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2336 case RTL_GIGA_MAC_VER_37: 2337 case RTL_GIGA_MAC_VER_39: 2338 case RTL_GIGA_MAC_VER_43: 2339 case RTL_GIGA_MAC_VER_44: 2340 case RTL_GIGA_MAC_VER_45: 2341 case RTL_GIGA_MAC_VER_46: 2342 case RTL_GIGA_MAC_VER_47: 2343 case RTL_GIGA_MAC_VER_48: 2344 case RTL_GIGA_MAC_VER_50: 2345 case RTL_GIGA_MAC_VER_51: 2346 case RTL_GIGA_MAC_VER_52: 2347 case RTL_GIGA_MAC_VER_60: 2348 case RTL_GIGA_MAC_VER_61: 2349 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2350 break; 2351 case RTL_GIGA_MAC_VER_40: 2352 case RTL_GIGA_MAC_VER_41: 2353 case RTL_GIGA_MAC_VER_49: 2354 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2355 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2356 break; 2357 default: 2358 break; 2359 } 2360 } 2361 2362 static void rtl_pll_power_up(struct rtl8169_private *tp) 2363 { 2364 switch (tp->mac_version) { 2365 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2366 case RTL_GIGA_MAC_VER_37: 2367 case RTL_GIGA_MAC_VER_39: 2368 case RTL_GIGA_MAC_VER_43: 2369 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2370 break; 2371 case RTL_GIGA_MAC_VER_44: 2372 case RTL_GIGA_MAC_VER_45: 2373 case RTL_GIGA_MAC_VER_46: 2374 case RTL_GIGA_MAC_VER_47: 2375 case RTL_GIGA_MAC_VER_48: 2376 case RTL_GIGA_MAC_VER_50: 2377 case RTL_GIGA_MAC_VER_51: 2378 case RTL_GIGA_MAC_VER_52: 2379 case RTL_GIGA_MAC_VER_60: 2380 case RTL_GIGA_MAC_VER_61: 2381 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2382 break; 2383 case RTL_GIGA_MAC_VER_40: 2384 case RTL_GIGA_MAC_VER_41: 2385 case RTL_GIGA_MAC_VER_49: 2386 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2387 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2388 break; 2389 default: 2390 break; 2391 } 2392 2393 phy_resume(tp->phydev); 2394 /* give MAC/PHY some time to resume */ 2395 msleep(20); 2396 } 2397 2398 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2399 { 2400 switch (tp->mac_version) { 2401 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2402 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2403 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2404 break; 2405 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2406 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2407 case RTL_GIGA_MAC_VER_38: 2408 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2409 break; 2410 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2411 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2412 break; 2413 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2414 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 | 2415 RX_DMA_BURST); 2416 break; 2417 default: 2418 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2419 break; 2420 } 2421 } 2422 2423 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2424 { 2425 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2426 } 2427 2428 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2429 { 2430 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2431 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2432 } 2433 2434 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2435 { 2436 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2437 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2438 } 2439 2440 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2441 { 2442 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2443 } 2444 2445 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2446 { 2447 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2448 } 2449 2450 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2451 { 2452 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2453 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2454 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2455 } 2456 2457 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2458 { 2459 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2460 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2461 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2462 } 2463 2464 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2465 { 2466 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2467 } 2468 2469 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2470 { 2471 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2472 } 2473 2474 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) 2475 { 2476 rtl_unlock_config_regs(tp); 2477 switch (tp->mac_version) { 2478 case RTL_GIGA_MAC_VER_12: 2479 case RTL_GIGA_MAC_VER_17: 2480 pcie_set_readrq(tp->pci_dev, 512); 2481 r8168b_1_hw_jumbo_enable(tp); 2482 break; 2483 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2484 pcie_set_readrq(tp->pci_dev, 512); 2485 r8168c_hw_jumbo_enable(tp); 2486 break; 2487 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2488 r8168dp_hw_jumbo_enable(tp); 2489 break; 2490 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2491 pcie_set_readrq(tp->pci_dev, 512); 2492 r8168e_hw_jumbo_enable(tp); 2493 break; 2494 default: 2495 break; 2496 } 2497 rtl_lock_config_regs(tp); 2498 } 2499 2500 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) 2501 { 2502 rtl_unlock_config_regs(tp); 2503 switch (tp->mac_version) { 2504 case RTL_GIGA_MAC_VER_12: 2505 case RTL_GIGA_MAC_VER_17: 2506 r8168b_1_hw_jumbo_disable(tp); 2507 break; 2508 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2509 r8168c_hw_jumbo_disable(tp); 2510 break; 2511 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2512 r8168dp_hw_jumbo_disable(tp); 2513 break; 2514 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2515 r8168e_hw_jumbo_disable(tp); 2516 break; 2517 default: 2518 break; 2519 } 2520 rtl_lock_config_regs(tp); 2521 2522 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2523 pcie_set_readrq(tp->pci_dev, 4096); 2524 } 2525 2526 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu) 2527 { 2528 if (mtu > ETH_DATA_LEN) 2529 rtl_hw_jumbo_enable(tp); 2530 else 2531 rtl_hw_jumbo_disable(tp); 2532 } 2533 2534 DECLARE_RTL_COND(rtl_chipcmd_cond) 2535 { 2536 return RTL_R8(tp, ChipCmd) & CmdReset; 2537 } 2538 2539 static void rtl_hw_reset(struct rtl8169_private *tp) 2540 { 2541 RTL_W8(tp, ChipCmd, CmdReset); 2542 2543 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2544 } 2545 2546 static void rtl_request_firmware(struct rtl8169_private *tp) 2547 { 2548 struct rtl_fw *rtl_fw; 2549 2550 /* firmware loaded already or no firmware available */ 2551 if (tp->rtl_fw || !tp->fw_name) 2552 return; 2553 2554 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2555 if (!rtl_fw) { 2556 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 2557 return; 2558 } 2559 2560 rtl_fw->phy_write = rtl_writephy; 2561 rtl_fw->phy_read = rtl_readphy; 2562 rtl_fw->mac_mcu_write = mac_mcu_write; 2563 rtl_fw->mac_mcu_read = mac_mcu_read; 2564 rtl_fw->fw_name = tp->fw_name; 2565 rtl_fw->dev = tp_to_dev(tp); 2566 2567 if (rtl_fw_request_firmware(rtl_fw)) 2568 kfree(rtl_fw); 2569 else 2570 tp->rtl_fw = rtl_fw; 2571 } 2572 2573 static void rtl_rx_close(struct rtl8169_private *tp) 2574 { 2575 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2576 } 2577 2578 DECLARE_RTL_COND(rtl_npq_cond) 2579 { 2580 return RTL_R8(tp, TxPoll) & NPQ; 2581 } 2582 2583 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2584 { 2585 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2586 } 2587 2588 static void rtl8169_hw_reset(struct rtl8169_private *tp) 2589 { 2590 /* Disable interrupts */ 2591 rtl8169_irq_mask_and_ack(tp); 2592 2593 rtl_rx_close(tp); 2594 2595 switch (tp->mac_version) { 2596 case RTL_GIGA_MAC_VER_27: 2597 case RTL_GIGA_MAC_VER_28: 2598 case RTL_GIGA_MAC_VER_31: 2599 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 2600 break; 2601 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2602 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2603 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2604 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 2605 break; 2606 default: 2607 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2608 udelay(100); 2609 break; 2610 } 2611 2612 rtl_hw_reset(tp); 2613 } 2614 2615 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2616 { 2617 u32 val = TX_DMA_BURST << TxDMAShift | 2618 InterFrameGap << TxInterFrameGapShift; 2619 2620 if (rtl_is_8168evl_up(tp)) 2621 val |= TXCFG_AUTO_FIFO; 2622 2623 RTL_W32(tp, TxConfig, val); 2624 } 2625 2626 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2627 { 2628 /* Low hurts. Let's disable the filtering. */ 2629 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2630 } 2631 2632 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2633 { 2634 /* 2635 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2636 * register to be written before TxDescAddrLow to work. 2637 * Switching from MMIO to I/O access fixes the issue as well. 2638 */ 2639 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2640 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2641 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2642 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2643 } 2644 2645 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 2646 { 2647 u32 val; 2648 2649 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2650 val = 0x000fff00; 2651 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2652 val = 0x00ffff00; 2653 else 2654 return; 2655 2656 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2657 val |= 0xff; 2658 2659 RTL_W32(tp, 0x7c, val); 2660 } 2661 2662 static void rtl_set_rx_mode(struct net_device *dev) 2663 { 2664 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2665 /* Multicast hash filter */ 2666 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2667 struct rtl8169_private *tp = netdev_priv(dev); 2668 u32 tmp; 2669 2670 if (dev->flags & IFF_PROMISC) { 2671 /* Unconditionally log net taps. */ 2672 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 2673 rx_mode |= AcceptAllPhys; 2674 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2675 dev->flags & IFF_ALLMULTI || 2676 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2677 /* accept all multicasts */ 2678 } else if (netdev_mc_empty(dev)) { 2679 rx_mode &= ~AcceptMulticast; 2680 } else { 2681 struct netdev_hw_addr *ha; 2682 2683 mc_filter[1] = mc_filter[0] = 0; 2684 netdev_for_each_mc_addr(ha, dev) { 2685 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2686 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2687 } 2688 2689 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2690 tmp = mc_filter[0]; 2691 mc_filter[0] = swab32(mc_filter[1]); 2692 mc_filter[1] = swab32(tmp); 2693 } 2694 } 2695 2696 if (dev->features & NETIF_F_RXALL) 2697 rx_mode |= (AcceptErr | AcceptRunt); 2698 2699 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2700 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2701 2702 tmp = RTL_R32(tp, RxConfig); 2703 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); 2704 } 2705 2706 DECLARE_RTL_COND(rtl_csiar_cond) 2707 { 2708 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2709 } 2710 2711 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2712 { 2713 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2714 2715 RTL_W32(tp, CSIDR, value); 2716 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2717 CSIAR_BYTE_ENABLE | func << 16); 2718 2719 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2720 } 2721 2722 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2723 { 2724 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2725 2726 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2727 CSIAR_BYTE_ENABLE); 2728 2729 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2730 RTL_R32(tp, CSIDR) : ~0; 2731 } 2732 2733 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2734 { 2735 struct pci_dev *pdev = tp->pci_dev; 2736 u32 csi; 2737 2738 /* According to Realtek the value at config space address 0x070f 2739 * controls the L0s/L1 entrance latency. We try standard ECAM access 2740 * first and if it fails fall back to CSI. 2741 */ 2742 if (pdev->cfg_size > 0x070f && 2743 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2744 return; 2745 2746 netdev_notice_once(tp->dev, 2747 "No native access to PCI extended config space, falling back to CSI\n"); 2748 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2749 rtl_csi_write(tp, 0x070c, csi | val << 24); 2750 } 2751 2752 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2753 { 2754 rtl_csi_access_enable(tp, 0x27); 2755 } 2756 2757 struct ephy_info { 2758 unsigned int offset; 2759 u16 mask; 2760 u16 bits; 2761 }; 2762 2763 static void __rtl_ephy_init(struct rtl8169_private *tp, 2764 const struct ephy_info *e, int len) 2765 { 2766 u16 w; 2767 2768 while (len-- > 0) { 2769 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2770 rtl_ephy_write(tp, e->offset, w); 2771 e++; 2772 } 2773 } 2774 2775 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2776 2777 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2778 { 2779 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2780 PCI_EXP_LNKCTL_CLKREQ_EN); 2781 } 2782 2783 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2784 { 2785 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2786 PCI_EXP_LNKCTL_CLKREQ_EN); 2787 } 2788 2789 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2790 { 2791 /* work around an issue when PCI reset occurs during L2/L3 state */ 2792 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2793 } 2794 2795 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2796 { 2797 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2798 if (enable && tp->aspm_manageable) { 2799 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2800 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2801 } else { 2802 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2803 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2804 } 2805 2806 udelay(10); 2807 } 2808 2809 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2810 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2811 { 2812 /* Usage of dynamic vs. static FIFO is controlled by bit 2813 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2814 */ 2815 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2816 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2817 } 2818 2819 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2820 u8 low, u8 high) 2821 { 2822 /* FIFO thresholds for pause flow control */ 2823 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2824 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2825 } 2826 2827 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2828 { 2829 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2830 } 2831 2832 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2833 { 2834 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2835 2836 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2837 2838 rtl_disable_clock_request(tp); 2839 } 2840 2841 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2842 { 2843 static const struct ephy_info e_info_8168cp[] = { 2844 { 0x01, 0, 0x0001 }, 2845 { 0x02, 0x0800, 0x1000 }, 2846 { 0x03, 0, 0x0042 }, 2847 { 0x06, 0x0080, 0x0000 }, 2848 { 0x07, 0, 0x2000 } 2849 }; 2850 2851 rtl_set_def_aspm_entry_latency(tp); 2852 2853 rtl_ephy_init(tp, e_info_8168cp); 2854 2855 __rtl_hw_start_8168cp(tp); 2856 } 2857 2858 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2859 { 2860 rtl_set_def_aspm_entry_latency(tp); 2861 2862 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2863 } 2864 2865 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2866 { 2867 rtl_set_def_aspm_entry_latency(tp); 2868 2869 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2870 2871 /* Magic. */ 2872 RTL_W8(tp, DBG_REG, 0x20); 2873 } 2874 2875 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2876 { 2877 static const struct ephy_info e_info_8168c_1[] = { 2878 { 0x02, 0x0800, 0x1000 }, 2879 { 0x03, 0, 0x0002 }, 2880 { 0x06, 0x0080, 0x0000 } 2881 }; 2882 2883 rtl_set_def_aspm_entry_latency(tp); 2884 2885 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2886 2887 rtl_ephy_init(tp, e_info_8168c_1); 2888 2889 __rtl_hw_start_8168cp(tp); 2890 } 2891 2892 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2893 { 2894 static const struct ephy_info e_info_8168c_2[] = { 2895 { 0x01, 0, 0x0001 }, 2896 { 0x03, 0x0400, 0x0020 } 2897 }; 2898 2899 rtl_set_def_aspm_entry_latency(tp); 2900 2901 rtl_ephy_init(tp, e_info_8168c_2); 2902 2903 __rtl_hw_start_8168cp(tp); 2904 } 2905 2906 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2907 { 2908 rtl_hw_start_8168c_2(tp); 2909 } 2910 2911 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2912 { 2913 rtl_set_def_aspm_entry_latency(tp); 2914 2915 __rtl_hw_start_8168cp(tp); 2916 } 2917 2918 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2919 { 2920 rtl_set_def_aspm_entry_latency(tp); 2921 2922 rtl_disable_clock_request(tp); 2923 } 2924 2925 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2926 { 2927 static const struct ephy_info e_info_8168d_4[] = { 2928 { 0x0b, 0x0000, 0x0048 }, 2929 { 0x19, 0x0020, 0x0050 }, 2930 { 0x0c, 0x0100, 0x0020 }, 2931 { 0x10, 0x0004, 0x0000 }, 2932 }; 2933 2934 rtl_set_def_aspm_entry_latency(tp); 2935 2936 rtl_ephy_init(tp, e_info_8168d_4); 2937 2938 rtl_enable_clock_request(tp); 2939 } 2940 2941 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2942 { 2943 static const struct ephy_info e_info_8168e_1[] = { 2944 { 0x00, 0x0200, 0x0100 }, 2945 { 0x00, 0x0000, 0x0004 }, 2946 { 0x06, 0x0002, 0x0001 }, 2947 { 0x06, 0x0000, 0x0030 }, 2948 { 0x07, 0x0000, 0x2000 }, 2949 { 0x00, 0x0000, 0x0020 }, 2950 { 0x03, 0x5800, 0x2000 }, 2951 { 0x03, 0x0000, 0x0001 }, 2952 { 0x01, 0x0800, 0x1000 }, 2953 { 0x07, 0x0000, 0x4000 }, 2954 { 0x1e, 0x0000, 0x2000 }, 2955 { 0x19, 0xffff, 0xfe6c }, 2956 { 0x0a, 0x0000, 0x0040 } 2957 }; 2958 2959 rtl_set_def_aspm_entry_latency(tp); 2960 2961 rtl_ephy_init(tp, e_info_8168e_1); 2962 2963 rtl_disable_clock_request(tp); 2964 2965 /* Reset tx FIFO pointer */ 2966 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2967 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2968 2969 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2970 } 2971 2972 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2973 { 2974 static const struct ephy_info e_info_8168e_2[] = { 2975 { 0x09, 0x0000, 0x0080 }, 2976 { 0x19, 0x0000, 0x0224 }, 2977 { 0x00, 0x0000, 0x0004 }, 2978 { 0x0c, 0x3df0, 0x0200 }, 2979 }; 2980 2981 rtl_set_def_aspm_entry_latency(tp); 2982 2983 rtl_ephy_init(tp, e_info_8168e_2); 2984 2985 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2986 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2987 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2988 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2989 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2990 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 2991 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 2992 2993 rtl_disable_clock_request(tp); 2994 2995 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2996 2997 rtl8168_config_eee_mac(tp); 2998 2999 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3000 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3001 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 3002 3003 rtl_hw_aspm_clkreq_enable(tp, true); 3004 } 3005 3006 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3007 { 3008 rtl_set_def_aspm_entry_latency(tp); 3009 3010 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3011 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3012 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3013 rtl_reset_packet_filter(tp); 3014 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 3015 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 3016 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3017 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3018 3019 rtl_disable_clock_request(tp); 3020 3021 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3022 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3023 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3024 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 3025 3026 rtl8168_config_eee_mac(tp); 3027 } 3028 3029 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3030 { 3031 static const struct ephy_info e_info_8168f_1[] = { 3032 { 0x06, 0x00c0, 0x0020 }, 3033 { 0x08, 0x0001, 0x0002 }, 3034 { 0x09, 0x0000, 0x0080 }, 3035 { 0x19, 0x0000, 0x0224 }, 3036 { 0x00, 0x0000, 0x0004 }, 3037 { 0x0c, 0x3df0, 0x0200 }, 3038 }; 3039 3040 rtl_hw_start_8168f(tp); 3041 3042 rtl_ephy_init(tp, e_info_8168f_1); 3043 3044 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 3045 } 3046 3047 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3048 { 3049 static const struct ephy_info e_info_8168f_1[] = { 3050 { 0x06, 0x00c0, 0x0020 }, 3051 { 0x0f, 0xffff, 0x5200 }, 3052 { 0x19, 0x0000, 0x0224 }, 3053 { 0x00, 0x0000, 0x0004 }, 3054 { 0x0c, 0x3df0, 0x0200 }, 3055 }; 3056 3057 rtl_hw_start_8168f(tp); 3058 rtl_pcie_state_l2l3_disable(tp); 3059 3060 rtl_ephy_init(tp, e_info_8168f_1); 3061 3062 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 3063 } 3064 3065 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3066 { 3067 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3068 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3069 3070 rtl_set_def_aspm_entry_latency(tp); 3071 3072 rtl_reset_packet_filter(tp); 3073 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3074 3075 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3076 3077 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3078 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3079 3080 rtl8168_config_eee_mac(tp); 3081 3082 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3083 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3084 3085 rtl_pcie_state_l2l3_disable(tp); 3086 } 3087 3088 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3089 { 3090 static const struct ephy_info e_info_8168g_1[] = { 3091 { 0x00, 0x0008, 0x0000 }, 3092 { 0x0c, 0x3ff0, 0x0820 }, 3093 { 0x1e, 0x0000, 0x0001 }, 3094 { 0x19, 0x8000, 0x0000 } 3095 }; 3096 3097 rtl_hw_start_8168g(tp); 3098 3099 /* disable aspm and clock request before access ephy */ 3100 rtl_hw_aspm_clkreq_enable(tp, false); 3101 rtl_ephy_init(tp, e_info_8168g_1); 3102 rtl_hw_aspm_clkreq_enable(tp, true); 3103 } 3104 3105 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3106 { 3107 static const struct ephy_info e_info_8168g_2[] = { 3108 { 0x00, 0x0008, 0x0000 }, 3109 { 0x0c, 0x3ff0, 0x0820 }, 3110 { 0x19, 0xffff, 0x7c00 }, 3111 { 0x1e, 0xffff, 0x20eb }, 3112 { 0x0d, 0xffff, 0x1666 }, 3113 { 0x00, 0xffff, 0x10a3 }, 3114 { 0x06, 0xffff, 0xf050 }, 3115 { 0x04, 0x0000, 0x0010 }, 3116 { 0x1d, 0x4000, 0x0000 }, 3117 }; 3118 3119 rtl_hw_start_8168g(tp); 3120 3121 /* disable aspm and clock request before access ephy */ 3122 rtl_hw_aspm_clkreq_enable(tp, false); 3123 rtl_ephy_init(tp, e_info_8168g_2); 3124 } 3125 3126 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3127 { 3128 static const struct ephy_info e_info_8411_2[] = { 3129 { 0x00, 0x0008, 0x0000 }, 3130 { 0x0c, 0x37d0, 0x0820 }, 3131 { 0x1e, 0x0000, 0x0001 }, 3132 { 0x19, 0x8021, 0x0000 }, 3133 { 0x1e, 0x0000, 0x2000 }, 3134 { 0x0d, 0x0100, 0x0200 }, 3135 { 0x00, 0x0000, 0x0080 }, 3136 { 0x06, 0x0000, 0x0010 }, 3137 { 0x04, 0x0000, 0x0010 }, 3138 { 0x1d, 0x0000, 0x4000 }, 3139 }; 3140 3141 rtl_hw_start_8168g(tp); 3142 3143 /* disable aspm and clock request before access ephy */ 3144 rtl_hw_aspm_clkreq_enable(tp, false); 3145 rtl_ephy_init(tp, e_info_8411_2); 3146 3147 /* The following Realtek-provided magic fixes an issue with the RX unit 3148 * getting confused after the PHY having been powered-down. 3149 */ 3150 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3151 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3152 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3153 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3154 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3155 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3156 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3157 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3158 mdelay(3); 3159 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3160 3161 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3162 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3163 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3164 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3165 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3166 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3167 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3168 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3169 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3170 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3171 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3172 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3173 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3174 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3175 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3176 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3177 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3178 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3179 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3180 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3181 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3182 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3183 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3184 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3185 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3186 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3187 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3188 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3189 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3190 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3191 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3192 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3193 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3194 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3195 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3196 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3197 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3198 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3199 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3200 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3201 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3202 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3203 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3204 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3205 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3206 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3207 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3208 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3209 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3210 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3211 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3212 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3213 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3214 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3215 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3216 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3217 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3218 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3219 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3220 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3221 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3222 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3223 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3224 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3225 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3226 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3227 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3228 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3229 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3230 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3231 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3232 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3233 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3234 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3235 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3236 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3237 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3238 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3239 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3240 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3241 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3242 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3243 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3244 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3245 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3246 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3247 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3248 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3249 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3250 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3251 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3252 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3253 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3254 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3255 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3256 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3257 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3258 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3259 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3260 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3261 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3262 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3263 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3264 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3265 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3266 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3267 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3268 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3269 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3270 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3271 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3272 3273 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3274 3275 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3276 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3277 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3278 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3279 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3280 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3281 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3282 3283 rtl_hw_aspm_clkreq_enable(tp, true); 3284 } 3285 3286 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3287 { 3288 static const struct ephy_info e_info_8168h_1[] = { 3289 { 0x1e, 0x0800, 0x0001 }, 3290 { 0x1d, 0x0000, 0x0800 }, 3291 { 0x05, 0xffff, 0x2089 }, 3292 { 0x06, 0xffff, 0x5881 }, 3293 { 0x04, 0xffff, 0x854a }, 3294 { 0x01, 0xffff, 0x068b } 3295 }; 3296 int rg_saw_cnt; 3297 3298 /* disable aspm and clock request before access ephy */ 3299 rtl_hw_aspm_clkreq_enable(tp, false); 3300 rtl_ephy_init(tp, e_info_8168h_1); 3301 3302 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3303 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3304 3305 rtl_set_def_aspm_entry_latency(tp); 3306 3307 rtl_reset_packet_filter(tp); 3308 3309 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 3310 3311 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 3312 3313 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3314 3315 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3316 3317 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3318 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3319 3320 rtl8168_config_eee_mac(tp); 3321 3322 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3323 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3324 3325 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3326 3327 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3328 3329 rtl_pcie_state_l2l3_disable(tp); 3330 3331 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3332 if (rg_saw_cnt > 0) { 3333 u16 sw_cnt_1ms_ini; 3334 3335 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3336 sw_cnt_1ms_ini &= 0x0fff; 3337 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3338 } 3339 3340 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3341 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3342 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3343 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3344 3345 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3346 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3347 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3348 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3349 3350 rtl_hw_aspm_clkreq_enable(tp, true); 3351 } 3352 3353 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3354 { 3355 rtl8168ep_stop_cmac(tp); 3356 3357 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3358 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3359 3360 rtl_set_def_aspm_entry_latency(tp); 3361 3362 rtl_reset_packet_filter(tp); 3363 3364 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 3365 3366 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3367 3368 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3369 3370 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3371 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3372 3373 rtl8168_config_eee_mac(tp); 3374 3375 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3376 3377 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3378 3379 rtl_pcie_state_l2l3_disable(tp); 3380 } 3381 3382 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3383 { 3384 static const struct ephy_info e_info_8168ep_1[] = { 3385 { 0x00, 0xffff, 0x10ab }, 3386 { 0x06, 0xffff, 0xf030 }, 3387 { 0x08, 0xffff, 0x2006 }, 3388 { 0x0d, 0xffff, 0x1666 }, 3389 { 0x0c, 0x3ff0, 0x0000 } 3390 }; 3391 3392 /* disable aspm and clock request before access ephy */ 3393 rtl_hw_aspm_clkreq_enable(tp, false); 3394 rtl_ephy_init(tp, e_info_8168ep_1); 3395 3396 rtl_hw_start_8168ep(tp); 3397 3398 rtl_hw_aspm_clkreq_enable(tp, true); 3399 } 3400 3401 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3402 { 3403 static const struct ephy_info e_info_8168ep_2[] = { 3404 { 0x00, 0xffff, 0x10a3 }, 3405 { 0x19, 0xffff, 0xfc00 }, 3406 { 0x1e, 0xffff, 0x20ea } 3407 }; 3408 3409 /* disable aspm and clock request before access ephy */ 3410 rtl_hw_aspm_clkreq_enable(tp, false); 3411 rtl_ephy_init(tp, e_info_8168ep_2); 3412 3413 rtl_hw_start_8168ep(tp); 3414 3415 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3416 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3417 3418 rtl_hw_aspm_clkreq_enable(tp, true); 3419 } 3420 3421 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3422 { 3423 static const struct ephy_info e_info_8168ep_3[] = { 3424 { 0x00, 0x0000, 0x0080 }, 3425 { 0x0d, 0x0100, 0x0200 }, 3426 { 0x19, 0x8021, 0x0000 }, 3427 { 0x1e, 0x0000, 0x2000 }, 3428 }; 3429 3430 /* disable aspm and clock request before access ephy */ 3431 rtl_hw_aspm_clkreq_enable(tp, false); 3432 rtl_ephy_init(tp, e_info_8168ep_3); 3433 3434 rtl_hw_start_8168ep(tp); 3435 3436 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3437 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3438 3439 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3440 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3441 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3442 3443 rtl_hw_aspm_clkreq_enable(tp, true); 3444 } 3445 3446 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3447 { 3448 static const struct ephy_info e_info_8117[] = { 3449 { 0x19, 0x0040, 0x1100 }, 3450 { 0x59, 0x0040, 0x1100 }, 3451 }; 3452 int rg_saw_cnt; 3453 3454 rtl8168ep_stop_cmac(tp); 3455 3456 /* disable aspm and clock request before access ephy */ 3457 rtl_hw_aspm_clkreq_enable(tp, false); 3458 rtl_ephy_init(tp, e_info_8117); 3459 3460 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3461 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3462 3463 rtl_set_def_aspm_entry_latency(tp); 3464 3465 rtl_reset_packet_filter(tp); 3466 3467 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90); 3468 3469 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3470 3471 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3472 3473 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3474 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3475 3476 rtl8168_config_eee_mac(tp); 3477 3478 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3479 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3480 3481 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3482 3483 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3484 3485 rtl_pcie_state_l2l3_disable(tp); 3486 3487 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3488 if (rg_saw_cnt > 0) { 3489 u16 sw_cnt_1ms_ini; 3490 3491 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3492 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3493 } 3494 3495 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3496 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3497 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3498 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3499 3500 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3501 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3502 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3503 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3504 3505 /* firmware is for MAC only */ 3506 r8169_apply_firmware(tp); 3507 3508 rtl_hw_aspm_clkreq_enable(tp, true); 3509 } 3510 3511 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3512 { 3513 static const struct ephy_info e_info_8102e_1[] = { 3514 { 0x01, 0, 0x6e65 }, 3515 { 0x02, 0, 0x091f }, 3516 { 0x03, 0, 0xc2f9 }, 3517 { 0x06, 0, 0xafb5 }, 3518 { 0x07, 0, 0x0e00 }, 3519 { 0x19, 0, 0xec80 }, 3520 { 0x01, 0, 0x2e65 }, 3521 { 0x01, 0, 0x6e65 } 3522 }; 3523 u8 cfg1; 3524 3525 rtl_set_def_aspm_entry_latency(tp); 3526 3527 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3528 3529 RTL_W8(tp, Config1, 3530 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3531 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3532 3533 cfg1 = RTL_R8(tp, Config1); 3534 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3535 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3536 3537 rtl_ephy_init(tp, e_info_8102e_1); 3538 } 3539 3540 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3541 { 3542 rtl_set_def_aspm_entry_latency(tp); 3543 3544 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3545 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3546 } 3547 3548 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3549 { 3550 rtl_hw_start_8102e_2(tp); 3551 3552 rtl_ephy_write(tp, 0x03, 0xc2f9); 3553 } 3554 3555 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3556 { 3557 static const struct ephy_info e_info_8105e_1[] = { 3558 { 0x07, 0, 0x4000 }, 3559 { 0x19, 0, 0x0200 }, 3560 { 0x19, 0, 0x0020 }, 3561 { 0x1e, 0, 0x2000 }, 3562 { 0x03, 0, 0x0001 }, 3563 { 0x19, 0, 0x0100 }, 3564 { 0x19, 0, 0x0004 }, 3565 { 0x0a, 0, 0x0020 } 3566 }; 3567 3568 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3569 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3570 3571 /* Disable Early Tally Counter */ 3572 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3573 3574 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3575 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3576 3577 rtl_ephy_init(tp, e_info_8105e_1); 3578 3579 rtl_pcie_state_l2l3_disable(tp); 3580 } 3581 3582 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3583 { 3584 rtl_hw_start_8105e_1(tp); 3585 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3586 } 3587 3588 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3589 { 3590 static const struct ephy_info e_info_8402[] = { 3591 { 0x19, 0xffff, 0xff64 }, 3592 { 0x1e, 0, 0x4000 } 3593 }; 3594 3595 rtl_set_def_aspm_entry_latency(tp); 3596 3597 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3598 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3599 3600 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3601 3602 rtl_ephy_init(tp, e_info_8402); 3603 3604 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3605 rtl_reset_packet_filter(tp); 3606 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3607 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3608 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 3609 3610 /* disable EEE */ 3611 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3612 3613 rtl_pcie_state_l2l3_disable(tp); 3614 } 3615 3616 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3617 { 3618 rtl_hw_aspm_clkreq_enable(tp, false); 3619 3620 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3621 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3622 3623 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3624 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3625 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3626 3627 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3628 3629 /* disable EEE */ 3630 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3631 3632 rtl_pcie_state_l2l3_disable(tp); 3633 rtl_hw_aspm_clkreq_enable(tp, true); 3634 } 3635 3636 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3637 { 3638 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3639 } 3640 3641 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3642 { 3643 rtl_pcie_state_l2l3_disable(tp); 3644 3645 RTL_W16(tp, 0x382, 0x221b); 3646 RTL_W8(tp, 0x4500, 0); 3647 RTL_W16(tp, 0x4800, 0); 3648 3649 /* disable UPS */ 3650 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3651 3652 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3653 3654 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3655 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3656 3657 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3658 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3659 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3660 3661 /* disable new tx descriptor format */ 3662 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3663 3664 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3665 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3666 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3667 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3668 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3669 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3670 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3671 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3672 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 3673 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3674 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3675 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 3676 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3677 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3678 udelay(1); 3679 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3680 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3681 3682 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3683 3684 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3685 3686 rtl8125_config_eee_mac(tp); 3687 3688 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3689 udelay(10); 3690 } 3691 3692 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 3693 { 3694 static const struct ephy_info e_info_8125_1[] = { 3695 { 0x01, 0xffff, 0xa812 }, 3696 { 0x09, 0xffff, 0x520c }, 3697 { 0x04, 0xffff, 0xd000 }, 3698 { 0x0d, 0xffff, 0xf702 }, 3699 { 0x0a, 0xffff, 0x8653 }, 3700 { 0x06, 0xffff, 0x001e }, 3701 { 0x08, 0xffff, 0x3595 }, 3702 { 0x20, 0xffff, 0x9455 }, 3703 { 0x21, 0xffff, 0x99ff }, 3704 { 0x02, 0xffff, 0x6046 }, 3705 { 0x29, 0xffff, 0xfe00 }, 3706 { 0x23, 0xffff, 0xab62 }, 3707 3708 { 0x41, 0xffff, 0xa80c }, 3709 { 0x49, 0xffff, 0x520c }, 3710 { 0x44, 0xffff, 0xd000 }, 3711 { 0x4d, 0xffff, 0xf702 }, 3712 { 0x4a, 0xffff, 0x8653 }, 3713 { 0x46, 0xffff, 0x001e }, 3714 { 0x48, 0xffff, 0x3595 }, 3715 { 0x60, 0xffff, 0x9455 }, 3716 { 0x61, 0xffff, 0x99ff }, 3717 { 0x42, 0xffff, 0x6046 }, 3718 { 0x69, 0xffff, 0xfe00 }, 3719 { 0x63, 0xffff, 0xab62 }, 3720 }; 3721 3722 rtl_set_def_aspm_entry_latency(tp); 3723 3724 /* disable aspm and clock request before access ephy */ 3725 rtl_hw_aspm_clkreq_enable(tp, false); 3726 rtl_ephy_init(tp, e_info_8125_1); 3727 3728 rtl_hw_start_8125_common(tp); 3729 } 3730 3731 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 3732 { 3733 static const struct ephy_info e_info_8125_2[] = { 3734 { 0x04, 0xffff, 0xd000 }, 3735 { 0x0a, 0xffff, 0x8653 }, 3736 { 0x23, 0xffff, 0xab66 }, 3737 { 0x20, 0xffff, 0x9455 }, 3738 { 0x21, 0xffff, 0x99ff }, 3739 { 0x29, 0xffff, 0xfe04 }, 3740 3741 { 0x44, 0xffff, 0xd000 }, 3742 { 0x4a, 0xffff, 0x8653 }, 3743 { 0x63, 0xffff, 0xab66 }, 3744 { 0x60, 0xffff, 0x9455 }, 3745 { 0x61, 0xffff, 0x99ff }, 3746 { 0x69, 0xffff, 0xfe04 }, 3747 }; 3748 3749 rtl_set_def_aspm_entry_latency(tp); 3750 3751 /* disable aspm and clock request before access ephy */ 3752 rtl_hw_aspm_clkreq_enable(tp, false); 3753 rtl_ephy_init(tp, e_info_8125_2); 3754 3755 rtl_hw_start_8125_common(tp); 3756 } 3757 3758 static void rtl_hw_config(struct rtl8169_private *tp) 3759 { 3760 static const rtl_generic_fct hw_configs[] = { 3761 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3762 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3763 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3764 [RTL_GIGA_MAC_VER_10] = NULL, 3765 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3766 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3767 [RTL_GIGA_MAC_VER_13] = NULL, 3768 [RTL_GIGA_MAC_VER_14] = NULL, 3769 [RTL_GIGA_MAC_VER_15] = NULL, 3770 [RTL_GIGA_MAC_VER_16] = NULL, 3771 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3772 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3773 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3774 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3775 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3776 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3777 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3778 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3779 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3780 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3781 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3782 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3783 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3784 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3785 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3786 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3787 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3788 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3789 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3790 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3791 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3792 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3793 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3794 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3795 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3796 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3797 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3798 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3799 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3800 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3801 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3802 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3803 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3804 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3805 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3806 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3807 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 3808 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 3809 }; 3810 3811 if (hw_configs[tp->mac_version]) 3812 hw_configs[tp->mac_version](tp); 3813 } 3814 3815 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3816 { 3817 int i; 3818 3819 /* disable interrupt coalescing */ 3820 for (i = 0xa00; i < 0xb00; i += 4) 3821 RTL_W32(tp, i, 0); 3822 3823 rtl_hw_config(tp); 3824 } 3825 3826 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3827 { 3828 if (rtl_is_8168evl_up(tp)) 3829 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3830 else 3831 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3832 3833 rtl_hw_config(tp); 3834 3835 /* disable interrupt coalescing */ 3836 RTL_W16(tp, IntrMitigate, 0x0000); 3837 } 3838 3839 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3840 { 3841 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 3842 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 3843 3844 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3845 3846 tp->cp_cmd |= PCIMulRW; 3847 3848 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3849 tp->mac_version == RTL_GIGA_MAC_VER_03) 3850 tp->cp_cmd |= EnAnaPLL; 3851 3852 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3853 3854 rtl8169_set_magic_reg(tp, tp->mac_version); 3855 3856 RTL_W32(tp, RxMissed, 0); 3857 3858 /* disable interrupt coalescing */ 3859 RTL_W16(tp, IntrMitigate, 0x0000); 3860 } 3861 3862 static void rtl_hw_start(struct rtl8169_private *tp) 3863 { 3864 rtl_unlock_config_regs(tp); 3865 3866 tp->cp_cmd &= CPCMD_MASK; 3867 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3868 3869 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3870 rtl_hw_start_8169(tp); 3871 else if (rtl_is_8125(tp)) 3872 rtl_hw_start_8125(tp); 3873 else 3874 rtl_hw_start_8168(tp); 3875 3876 rtl_set_rx_max_size(tp); 3877 rtl_set_rx_tx_desc_registers(tp); 3878 rtl_lock_config_regs(tp); 3879 3880 rtl_jumbo_config(tp, tp->dev->mtu); 3881 3882 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3883 RTL_R16(tp, CPlusCmd); 3884 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3885 rtl_init_rxcfg(tp); 3886 rtl_set_tx_config_registers(tp); 3887 rtl_set_rx_mode(tp->dev); 3888 rtl_irq_enable(tp); 3889 } 3890 3891 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3892 { 3893 struct rtl8169_private *tp = netdev_priv(dev); 3894 3895 rtl_jumbo_config(tp, new_mtu); 3896 3897 dev->mtu = new_mtu; 3898 netdev_update_features(dev); 3899 3900 return 0; 3901 } 3902 3903 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 3904 { 3905 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); 3906 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 3907 } 3908 3909 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 3910 { 3911 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3912 3913 /* Force memory writes to complete before releasing descriptor */ 3914 dma_wmb(); 3915 3916 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 3917 } 3918 3919 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3920 struct RxDesc *desc) 3921 { 3922 struct device *d = tp_to_dev(tp); 3923 int node = dev_to_node(d); 3924 dma_addr_t mapping; 3925 struct page *data; 3926 3927 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3928 if (!data) 3929 return NULL; 3930 3931 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3932 if (unlikely(dma_mapping_error(d, mapping))) { 3933 if (net_ratelimit()) 3934 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 3935 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3936 return NULL; 3937 } 3938 3939 desc->addr = cpu_to_le64(mapping); 3940 rtl8169_mark_to_asic(desc); 3941 3942 return data; 3943 } 3944 3945 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3946 { 3947 unsigned int i; 3948 3949 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3950 dma_unmap_page(tp_to_dev(tp), 3951 le64_to_cpu(tp->RxDescArray[i].addr), 3952 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3953 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3954 tp->Rx_databuff[i] = NULL; 3955 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 3956 } 3957 } 3958 3959 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 3960 { 3961 desc->opts1 |= cpu_to_le32(RingEnd); 3962 } 3963 3964 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3965 { 3966 unsigned int i; 3967 3968 for (i = 0; i < NUM_RX_DESC; i++) { 3969 struct page *data; 3970 3971 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3972 if (!data) { 3973 rtl8169_rx_clear(tp); 3974 return -ENOMEM; 3975 } 3976 tp->Rx_databuff[i] = data; 3977 } 3978 3979 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 3980 3981 return 0; 3982 } 3983 3984 static int rtl8169_init_ring(struct rtl8169_private *tp) 3985 { 3986 rtl8169_init_ring_indexes(tp); 3987 3988 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3989 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3990 3991 return rtl8169_rx_fill(tp); 3992 } 3993 3994 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, 3995 struct TxDesc *desc) 3996 { 3997 unsigned int len = tx_skb->len; 3998 3999 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); 4000 4001 desc->opts1 = 0x00; 4002 desc->opts2 = 0x00; 4003 desc->addr = 0x00; 4004 tx_skb->len = 0; 4005 } 4006 4007 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4008 unsigned int n) 4009 { 4010 unsigned int i; 4011 4012 for (i = 0; i < n; i++) { 4013 unsigned int entry = (start + i) % NUM_TX_DESC; 4014 struct ring_info *tx_skb = tp->tx_skb + entry; 4015 unsigned int len = tx_skb->len; 4016 4017 if (len) { 4018 struct sk_buff *skb = tx_skb->skb; 4019 4020 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 4021 tp->TxDescArray + entry); 4022 if (skb) { 4023 dev_consume_skb_any(skb); 4024 tx_skb->skb = NULL; 4025 } 4026 } 4027 } 4028 } 4029 4030 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4031 { 4032 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4033 tp->cur_tx = tp->dirty_tx = 0; 4034 netdev_reset_queue(tp->dev); 4035 } 4036 4037 static void rtl_reset_work(struct rtl8169_private *tp) 4038 { 4039 struct net_device *dev = tp->dev; 4040 int i; 4041 4042 napi_disable(&tp->napi); 4043 netif_stop_queue(dev); 4044 synchronize_rcu(); 4045 4046 rtl8169_hw_reset(tp); 4047 4048 for (i = 0; i < NUM_RX_DESC; i++) 4049 rtl8169_mark_to_asic(tp->RxDescArray + i); 4050 4051 rtl8169_tx_clear(tp); 4052 rtl8169_init_ring_indexes(tp); 4053 4054 napi_enable(&tp->napi); 4055 rtl_hw_start(tp); 4056 netif_wake_queue(dev); 4057 } 4058 4059 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4060 { 4061 struct rtl8169_private *tp = netdev_priv(dev); 4062 4063 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4064 } 4065 4066 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry) 4067 { 4068 u32 status = opts0 | len; 4069 4070 if (entry == NUM_TX_DESC - 1) 4071 status |= RingEnd; 4072 4073 return cpu_to_le32(status); 4074 } 4075 4076 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4077 u32 *opts) 4078 { 4079 struct skb_shared_info *info = skb_shinfo(skb); 4080 unsigned int cur_frag, entry; 4081 struct TxDesc *uninitialized_var(txd); 4082 struct device *d = tp_to_dev(tp); 4083 4084 entry = tp->cur_tx; 4085 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4086 const skb_frag_t *frag = info->frags + cur_frag; 4087 dma_addr_t mapping; 4088 u32 len; 4089 void *addr; 4090 4091 entry = (entry + 1) % NUM_TX_DESC; 4092 4093 txd = tp->TxDescArray + entry; 4094 len = skb_frag_size(frag); 4095 addr = skb_frag_address(frag); 4096 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4097 if (unlikely(dma_mapping_error(d, mapping))) { 4098 if (net_ratelimit()) 4099 netif_err(tp, drv, tp->dev, 4100 "Failed to map TX fragments DMA!\n"); 4101 goto err_out; 4102 } 4103 4104 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 4105 txd->opts2 = cpu_to_le32(opts[1]); 4106 txd->addr = cpu_to_le64(mapping); 4107 4108 tp->tx_skb[entry].len = len; 4109 } 4110 4111 if (cur_frag) { 4112 tp->tx_skb[entry].skb = skb; 4113 txd->opts1 |= cpu_to_le32(LastFrag); 4114 } 4115 4116 return cur_frag; 4117 4118 err_out: 4119 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4120 return -EIO; 4121 } 4122 4123 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 4124 { 4125 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 4126 } 4127 4128 /* msdn_giant_send_check() 4129 * According to the document of microsoft, the TCP Pseudo Header excludes the 4130 * packet length for IPv6 TCP large packets. 4131 */ 4132 static int msdn_giant_send_check(struct sk_buff *skb) 4133 { 4134 const struct ipv6hdr *ipv6h; 4135 struct tcphdr *th; 4136 int ret; 4137 4138 ret = skb_cow_head(skb, 0); 4139 if (ret) 4140 return ret; 4141 4142 ipv6h = ipv6_hdr(skb); 4143 th = tcp_hdr(skb); 4144 4145 th->check = 0; 4146 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 4147 4148 return ret; 4149 } 4150 4151 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4152 { 4153 u32 mss = skb_shinfo(skb)->gso_size; 4154 4155 if (mss) { 4156 opts[0] |= TD_LSO; 4157 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; 4158 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4159 const struct iphdr *ip = ip_hdr(skb); 4160 4161 if (ip->protocol == IPPROTO_TCP) 4162 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4163 else if (ip->protocol == IPPROTO_UDP) 4164 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4165 else 4166 WARN_ON_ONCE(1); 4167 } 4168 } 4169 4170 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4171 struct sk_buff *skb, u32 *opts) 4172 { 4173 u32 transport_offset = (u32)skb_transport_offset(skb); 4174 u32 mss = skb_shinfo(skb)->gso_size; 4175 4176 if (mss) { 4177 switch (vlan_get_protocol(skb)) { 4178 case htons(ETH_P_IP): 4179 opts[0] |= TD1_GTSENV4; 4180 break; 4181 4182 case htons(ETH_P_IPV6): 4183 if (msdn_giant_send_check(skb)) 4184 return false; 4185 4186 opts[0] |= TD1_GTSENV6; 4187 break; 4188 4189 default: 4190 WARN_ON_ONCE(1); 4191 break; 4192 } 4193 4194 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4195 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; 4196 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4197 u8 ip_protocol; 4198 4199 switch (vlan_get_protocol(skb)) { 4200 case htons(ETH_P_IP): 4201 opts[1] |= TD1_IPv4_CS; 4202 ip_protocol = ip_hdr(skb)->protocol; 4203 break; 4204 4205 case htons(ETH_P_IPV6): 4206 opts[1] |= TD1_IPv6_CS; 4207 ip_protocol = ipv6_hdr(skb)->nexthdr; 4208 break; 4209 4210 default: 4211 ip_protocol = IPPROTO_RAW; 4212 break; 4213 } 4214 4215 if (ip_protocol == IPPROTO_TCP) 4216 opts[1] |= TD1_TCP_CS; 4217 else if (ip_protocol == IPPROTO_UDP) 4218 opts[1] |= TD1_UDP_CS; 4219 else 4220 WARN_ON_ONCE(1); 4221 4222 opts[1] |= transport_offset << TCPHO_SHIFT; 4223 } else { 4224 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 4225 return !eth_skb_pad(skb); 4226 } 4227 4228 return true; 4229 } 4230 4231 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4232 unsigned int nr_frags) 4233 { 4234 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4235 4236 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4237 return slots_avail > nr_frags; 4238 } 4239 4240 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4241 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4242 { 4243 switch (tp->mac_version) { 4244 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4245 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4246 return false; 4247 default: 4248 return true; 4249 } 4250 } 4251 4252 static void rtl8169_doorbell(struct rtl8169_private *tp) 4253 { 4254 if (rtl_is_8125(tp)) 4255 RTL_W16(tp, TxPoll_8125, BIT(0)); 4256 else 4257 RTL_W8(tp, TxPoll, NPQ); 4258 } 4259 4260 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4261 struct net_device *dev) 4262 { 4263 struct rtl8169_private *tp = netdev_priv(dev); 4264 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4265 struct TxDesc *txd = tp->TxDescArray + entry; 4266 struct device *d = tp_to_dev(tp); 4267 dma_addr_t mapping; 4268 u32 opts[2], len; 4269 bool stop_queue; 4270 bool door_bell; 4271 int frags; 4272 4273 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) { 4274 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 4275 goto err_stop_0; 4276 } 4277 4278 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 4279 goto err_stop_0; 4280 4281 opts[1] = rtl8169_tx_vlan_tag(skb); 4282 opts[0] = DescOwn; 4283 4284 if (rtl_chip_supports_csum_v2(tp)) { 4285 if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4286 goto err_dma_0; 4287 } else { 4288 rtl8169_tso_csum_v1(skb, opts); 4289 } 4290 4291 len = skb_headlen(skb); 4292 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); 4293 if (unlikely(dma_mapping_error(d, mapping))) { 4294 if (net_ratelimit()) 4295 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); 4296 goto err_dma_0; 4297 } 4298 4299 tp->tx_skb[entry].len = len; 4300 txd->addr = cpu_to_le64(mapping); 4301 4302 frags = rtl8169_xmit_frags(tp, skb, opts); 4303 if (frags < 0) 4304 goto err_dma_1; 4305 else if (frags) 4306 opts[0] |= FirstFrag; 4307 else { 4308 opts[0] |= FirstFrag | LastFrag; 4309 tp->tx_skb[entry].skb = skb; 4310 } 4311 4312 txd->opts2 = cpu_to_le32(opts[1]); 4313 4314 skb_tx_timestamp(skb); 4315 4316 /* Force memory writes to complete before releasing descriptor */ 4317 dma_wmb(); 4318 4319 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4320 4321 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 4322 4323 /* Force all memory writes to complete before notifying device */ 4324 wmb(); 4325 4326 tp->cur_tx += frags + 1; 4327 4328 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4329 if (unlikely(stop_queue)) { 4330 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4331 * not miss a ring update when it notices a stopped queue. 4332 */ 4333 smp_wmb(); 4334 netif_stop_queue(dev); 4335 door_bell = true; 4336 } 4337 4338 if (door_bell) 4339 rtl8169_doorbell(tp); 4340 4341 if (unlikely(stop_queue)) { 4342 /* Sync with rtl_tx: 4343 * - publish queue status and cur_tx ring index (write barrier) 4344 * - refresh dirty_tx ring index (read barrier). 4345 * May the current thread have a pessimistic view of the ring 4346 * status and forget to wake up queue, a racing rtl_tx thread 4347 * can't. 4348 */ 4349 smp_mb(); 4350 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4351 netif_start_queue(dev); 4352 } 4353 4354 return NETDEV_TX_OK; 4355 4356 err_dma_1: 4357 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); 4358 err_dma_0: 4359 dev_kfree_skb_any(skb); 4360 dev->stats.tx_dropped++; 4361 return NETDEV_TX_OK; 4362 4363 err_stop_0: 4364 netif_stop_queue(dev); 4365 dev->stats.tx_dropped++; 4366 return NETDEV_TX_BUSY; 4367 } 4368 4369 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4370 struct net_device *dev, 4371 netdev_features_t features) 4372 { 4373 int transport_offset = skb_transport_offset(skb); 4374 struct rtl8169_private *tp = netdev_priv(dev); 4375 4376 if (skb_is_gso(skb)) { 4377 if (transport_offset > GTTCPHO_MAX && 4378 rtl_chip_supports_csum_v2(tp)) 4379 features &= ~NETIF_F_ALL_TSO; 4380 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4381 if (skb->len < ETH_ZLEN) { 4382 switch (tp->mac_version) { 4383 case RTL_GIGA_MAC_VER_11: 4384 case RTL_GIGA_MAC_VER_12: 4385 case RTL_GIGA_MAC_VER_17: 4386 case RTL_GIGA_MAC_VER_34: 4387 features &= ~NETIF_F_CSUM_MASK; 4388 break; 4389 default: 4390 break; 4391 } 4392 } 4393 4394 if (transport_offset > TCPHO_MAX && 4395 rtl_chip_supports_csum_v2(tp)) 4396 features &= ~NETIF_F_CSUM_MASK; 4397 } 4398 4399 return vlan_features_check(skb, features); 4400 } 4401 4402 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4403 { 4404 struct rtl8169_private *tp = netdev_priv(dev); 4405 struct pci_dev *pdev = tp->pci_dev; 4406 u16 pci_status, pci_cmd; 4407 4408 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4409 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 4410 4411 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", 4412 pci_cmd, pci_status); 4413 4414 /* 4415 * The recovery sequence below admits a very elaborated explanation: 4416 * - it seems to work; 4417 * - I did not see what else could be done; 4418 * - it makes iop3xx happy. 4419 * 4420 * Feel free to adjust to your needs. 4421 */ 4422 if (pdev->broken_parity_status) 4423 pci_cmd &= ~PCI_COMMAND_PARITY; 4424 else 4425 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4426 4427 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4428 4429 pci_write_config_word(pdev, PCI_STATUS, 4430 pci_status & (PCI_STATUS_DETECTED_PARITY | 4431 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | 4432 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); 4433 4434 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4435 } 4436 4437 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4438 int budget) 4439 { 4440 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4441 4442 dirty_tx = tp->dirty_tx; 4443 smp_rmb(); 4444 tx_left = tp->cur_tx - dirty_tx; 4445 4446 while (tx_left > 0) { 4447 unsigned int entry = dirty_tx % NUM_TX_DESC; 4448 struct ring_info *tx_skb = tp->tx_skb + entry; 4449 u32 status; 4450 4451 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4452 if (status & DescOwn) 4453 break; 4454 4455 /* This barrier is needed to keep us from reading 4456 * any other fields out of the Tx descriptor until 4457 * we know the status of DescOwn 4458 */ 4459 dma_rmb(); 4460 4461 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 4462 tp->TxDescArray + entry); 4463 if (tx_skb->skb) { 4464 pkts_compl++; 4465 bytes_compl += tx_skb->skb->len; 4466 napi_consume_skb(tx_skb->skb, budget); 4467 tx_skb->skb = NULL; 4468 } 4469 dirty_tx++; 4470 tx_left--; 4471 } 4472 4473 if (tp->dirty_tx != dirty_tx) { 4474 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4475 4476 u64_stats_update_begin(&tp->tx_stats.syncp); 4477 tp->tx_stats.packets += pkts_compl; 4478 tp->tx_stats.bytes += bytes_compl; 4479 u64_stats_update_end(&tp->tx_stats.syncp); 4480 4481 tp->dirty_tx = dirty_tx; 4482 /* Sync with rtl8169_start_xmit: 4483 * - publish dirty_tx ring index (write barrier) 4484 * - refresh cur_tx ring index and queue status (read barrier) 4485 * May the current thread miss the stopped queue condition, 4486 * a racing xmit thread can only have a right view of the 4487 * ring status. 4488 */ 4489 smp_mb(); 4490 if (netif_queue_stopped(dev) && 4491 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4492 netif_wake_queue(dev); 4493 } 4494 /* 4495 * 8168 hack: TxPoll requests are lost when the Tx packets are 4496 * too close. Let's kick an extra TxPoll request when a burst 4497 * of start_xmit activity is detected (if it is not detected, 4498 * it is slow enough). -- FR 4499 */ 4500 if (tp->cur_tx != dirty_tx) 4501 rtl8169_doorbell(tp); 4502 } 4503 } 4504 4505 static inline int rtl8169_fragmented_frame(u32 status) 4506 { 4507 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4508 } 4509 4510 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4511 { 4512 u32 status = opts1 & RxProtoMask; 4513 4514 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4515 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4516 skb->ip_summed = CHECKSUM_UNNECESSARY; 4517 else 4518 skb_checksum_none_assert(skb); 4519 } 4520 4521 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4522 { 4523 unsigned int cur_rx, rx_left; 4524 unsigned int count; 4525 4526 cur_rx = tp->cur_rx; 4527 4528 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4529 unsigned int entry = cur_rx % NUM_RX_DESC; 4530 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 4531 struct RxDesc *desc = tp->RxDescArray + entry; 4532 u32 status; 4533 4534 status = le32_to_cpu(desc->opts1); 4535 if (status & DescOwn) 4536 break; 4537 4538 /* This barrier is needed to keep us from reading 4539 * any other fields out of the Rx descriptor until 4540 * we know the status of DescOwn 4541 */ 4542 dma_rmb(); 4543 4544 if (unlikely(status & RxRES)) { 4545 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 4546 status); 4547 dev->stats.rx_errors++; 4548 if (status & (RxRWT | RxRUNT)) 4549 dev->stats.rx_length_errors++; 4550 if (status & RxCRC) 4551 dev->stats.rx_crc_errors++; 4552 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 4553 dev->features & NETIF_F_RXALL) { 4554 goto process_pkt; 4555 } 4556 } else { 4557 unsigned int pkt_size; 4558 struct sk_buff *skb; 4559 4560 process_pkt: 4561 pkt_size = status & GENMASK(13, 0); 4562 if (likely(!(dev->features & NETIF_F_RXFCS))) 4563 pkt_size -= ETH_FCS_LEN; 4564 /* 4565 * The driver does not support incoming fragmented 4566 * frames. They are seen as a symptom of over-mtu 4567 * sized frames. 4568 */ 4569 if (unlikely(rtl8169_fragmented_frame(status))) { 4570 dev->stats.rx_dropped++; 4571 dev->stats.rx_length_errors++; 4572 goto release_descriptor; 4573 } 4574 4575 skb = napi_alloc_skb(&tp->napi, pkt_size); 4576 if (unlikely(!skb)) { 4577 dev->stats.rx_dropped++; 4578 goto release_descriptor; 4579 } 4580 4581 dma_sync_single_for_cpu(tp_to_dev(tp), 4582 le64_to_cpu(desc->addr), 4583 pkt_size, DMA_FROM_DEVICE); 4584 prefetch(rx_buf); 4585 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4586 skb->tail += pkt_size; 4587 skb->len = pkt_size; 4588 4589 dma_sync_single_for_device(tp_to_dev(tp), 4590 le64_to_cpu(desc->addr), 4591 pkt_size, DMA_FROM_DEVICE); 4592 4593 rtl8169_rx_csum(skb, status); 4594 skb->protocol = eth_type_trans(skb, dev); 4595 4596 rtl8169_rx_vlan_tag(desc, skb); 4597 4598 if (skb->pkt_type == PACKET_MULTICAST) 4599 dev->stats.multicast++; 4600 4601 napi_gro_receive(&tp->napi, skb); 4602 4603 u64_stats_update_begin(&tp->rx_stats.syncp); 4604 tp->rx_stats.packets++; 4605 tp->rx_stats.bytes += pkt_size; 4606 u64_stats_update_end(&tp->rx_stats.syncp); 4607 } 4608 release_descriptor: 4609 desc->opts2 = 0; 4610 rtl8169_mark_to_asic(desc); 4611 } 4612 4613 count = cur_rx - tp->cur_rx; 4614 tp->cur_rx = cur_rx; 4615 4616 return count; 4617 } 4618 4619 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4620 { 4621 struct rtl8169_private *tp = dev_instance; 4622 u32 status = rtl_get_events(tp); 4623 4624 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 4625 !(status & tp->irq_mask)) 4626 return IRQ_NONE; 4627 4628 if (unlikely(status & SYSErr)) { 4629 rtl8169_pcierr_interrupt(tp->dev); 4630 goto out; 4631 } 4632 4633 if (status & LinkChg) 4634 phy_mac_interrupt(tp->phydev); 4635 4636 if (unlikely(status & RxFIFOOver && 4637 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4638 netif_stop_queue(tp->dev); 4639 /* XXX - Hack alert. See rtl_task(). */ 4640 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); 4641 } 4642 4643 rtl_irq_disable(tp); 4644 napi_schedule_irqoff(&tp->napi); 4645 out: 4646 rtl_ack_events(tp, status); 4647 4648 return IRQ_HANDLED; 4649 } 4650 4651 static void rtl_task(struct work_struct *work) 4652 { 4653 static const struct { 4654 int bitnr; 4655 void (*action)(struct rtl8169_private *); 4656 } rtl_work[] = { 4657 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, 4658 }; 4659 struct rtl8169_private *tp = 4660 container_of(work, struct rtl8169_private, wk.work); 4661 struct net_device *dev = tp->dev; 4662 int i; 4663 4664 rtl_lock_work(tp); 4665 4666 if (!netif_running(dev) || 4667 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4668 goto out_unlock; 4669 4670 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { 4671 bool pending; 4672 4673 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); 4674 if (pending) 4675 rtl_work[i].action(tp); 4676 } 4677 4678 out_unlock: 4679 rtl_unlock_work(tp); 4680 } 4681 4682 static int rtl8169_poll(struct napi_struct *napi, int budget) 4683 { 4684 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4685 struct net_device *dev = tp->dev; 4686 int work_done; 4687 4688 work_done = rtl_rx(dev, tp, (u32) budget); 4689 4690 rtl_tx(dev, tp, budget); 4691 4692 if (work_done < budget) { 4693 napi_complete_done(napi, work_done); 4694 rtl_irq_enable(tp); 4695 } 4696 4697 return work_done; 4698 } 4699 4700 static void rtl8169_rx_missed(struct net_device *dev) 4701 { 4702 struct rtl8169_private *tp = netdev_priv(dev); 4703 4704 if (tp->mac_version > RTL_GIGA_MAC_VER_06) 4705 return; 4706 4707 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff; 4708 RTL_W32(tp, RxMissed, 0); 4709 } 4710 4711 static void r8169_phylink_handler(struct net_device *ndev) 4712 { 4713 struct rtl8169_private *tp = netdev_priv(ndev); 4714 4715 if (netif_carrier_ok(ndev)) { 4716 rtl_link_chg_patch(tp); 4717 pm_request_resume(&tp->pci_dev->dev); 4718 } else { 4719 pm_runtime_idle(&tp->pci_dev->dev); 4720 } 4721 4722 if (net_ratelimit()) 4723 phy_print_status(tp->phydev); 4724 } 4725 4726 static int r8169_phy_connect(struct rtl8169_private *tp) 4727 { 4728 struct phy_device *phydev = tp->phydev; 4729 phy_interface_t phy_mode; 4730 int ret; 4731 4732 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4733 PHY_INTERFACE_MODE_MII; 4734 4735 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4736 phy_mode); 4737 if (ret) 4738 return ret; 4739 4740 if (!tp->supports_gmii) 4741 phy_set_max_speed(phydev, SPEED_100); 4742 4743 phy_support_asym_pause(phydev); 4744 4745 phy_attached_info(phydev); 4746 4747 return 0; 4748 } 4749 4750 static void rtl8169_down(struct net_device *dev) 4751 { 4752 struct rtl8169_private *tp = netdev_priv(dev); 4753 4754 phy_stop(tp->phydev); 4755 4756 napi_disable(&tp->napi); 4757 netif_stop_queue(dev); 4758 4759 rtl8169_hw_reset(tp); 4760 /* 4761 * At this point device interrupts can not be enabled in any function, 4762 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) 4763 * and napi is disabled (rtl8169_poll). 4764 */ 4765 rtl8169_rx_missed(dev); 4766 4767 /* Give a racing hard_start_xmit a few cycles to complete. */ 4768 synchronize_rcu(); 4769 4770 rtl8169_tx_clear(tp); 4771 4772 rtl8169_rx_clear(tp); 4773 4774 rtl_pll_power_down(tp); 4775 } 4776 4777 static int rtl8169_close(struct net_device *dev) 4778 { 4779 struct rtl8169_private *tp = netdev_priv(dev); 4780 struct pci_dev *pdev = tp->pci_dev; 4781 4782 pm_runtime_get_sync(&pdev->dev); 4783 4784 /* Update counters before going down */ 4785 rtl8169_update_counters(tp); 4786 4787 rtl_lock_work(tp); 4788 /* Clear all task flags */ 4789 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4790 4791 rtl8169_down(dev); 4792 rtl_unlock_work(tp); 4793 4794 cancel_work_sync(&tp->wk.work); 4795 4796 phy_disconnect(tp->phydev); 4797 4798 pci_free_irq(pdev, 0, tp); 4799 4800 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4801 tp->RxPhyAddr); 4802 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4803 tp->TxPhyAddr); 4804 tp->TxDescArray = NULL; 4805 tp->RxDescArray = NULL; 4806 4807 pm_runtime_put_sync(&pdev->dev); 4808 4809 return 0; 4810 } 4811 4812 #ifdef CONFIG_NET_POLL_CONTROLLER 4813 static void rtl8169_netpoll(struct net_device *dev) 4814 { 4815 struct rtl8169_private *tp = netdev_priv(dev); 4816 4817 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4818 } 4819 #endif 4820 4821 static int rtl_open(struct net_device *dev) 4822 { 4823 struct rtl8169_private *tp = netdev_priv(dev); 4824 struct pci_dev *pdev = tp->pci_dev; 4825 int retval = -ENOMEM; 4826 4827 pm_runtime_get_sync(&pdev->dev); 4828 4829 /* 4830 * Rx and Tx descriptors needs 256 bytes alignment. 4831 * dma_alloc_coherent provides more. 4832 */ 4833 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4834 &tp->TxPhyAddr, GFP_KERNEL); 4835 if (!tp->TxDescArray) 4836 goto err_pm_runtime_put; 4837 4838 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4839 &tp->RxPhyAddr, GFP_KERNEL); 4840 if (!tp->RxDescArray) 4841 goto err_free_tx_0; 4842 4843 retval = rtl8169_init_ring(tp); 4844 if (retval < 0) 4845 goto err_free_rx_1; 4846 4847 rtl_request_firmware(tp); 4848 4849 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 4850 dev->name); 4851 if (retval < 0) 4852 goto err_release_fw_2; 4853 4854 retval = r8169_phy_connect(tp); 4855 if (retval) 4856 goto err_free_irq; 4857 4858 rtl_lock_work(tp); 4859 4860 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4861 4862 napi_enable(&tp->napi); 4863 4864 rtl8169_init_phy(tp); 4865 4866 rtl_pll_power_up(tp); 4867 4868 rtl_hw_start(tp); 4869 4870 if (!rtl8169_init_counter_offsets(tp)) 4871 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 4872 4873 phy_start(tp->phydev); 4874 netif_start_queue(dev); 4875 4876 rtl_unlock_work(tp); 4877 4878 pm_runtime_put_sync(&pdev->dev); 4879 out: 4880 return retval; 4881 4882 err_free_irq: 4883 pci_free_irq(pdev, 0, tp); 4884 err_release_fw_2: 4885 rtl_release_firmware(tp); 4886 rtl8169_rx_clear(tp); 4887 err_free_rx_1: 4888 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4889 tp->RxPhyAddr); 4890 tp->RxDescArray = NULL; 4891 err_free_tx_0: 4892 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4893 tp->TxPhyAddr); 4894 tp->TxDescArray = NULL; 4895 err_pm_runtime_put: 4896 pm_runtime_put_noidle(&pdev->dev); 4897 goto out; 4898 } 4899 4900 static void 4901 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4902 { 4903 struct rtl8169_private *tp = netdev_priv(dev); 4904 struct pci_dev *pdev = tp->pci_dev; 4905 struct rtl8169_counters *counters = tp->counters; 4906 unsigned int start; 4907 4908 pm_runtime_get_noresume(&pdev->dev); 4909 4910 if (netif_running(dev) && pm_runtime_active(&pdev->dev)) 4911 rtl8169_rx_missed(dev); 4912 4913 do { 4914 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 4915 stats->rx_packets = tp->rx_stats.packets; 4916 stats->rx_bytes = tp->rx_stats.bytes; 4917 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 4918 4919 do { 4920 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 4921 stats->tx_packets = tp->tx_stats.packets; 4922 stats->tx_bytes = tp->tx_stats.bytes; 4923 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 4924 4925 stats->rx_dropped = dev->stats.rx_dropped; 4926 stats->tx_dropped = dev->stats.tx_dropped; 4927 stats->rx_length_errors = dev->stats.rx_length_errors; 4928 stats->rx_errors = dev->stats.rx_errors; 4929 stats->rx_crc_errors = dev->stats.rx_crc_errors; 4930 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 4931 stats->rx_missed_errors = dev->stats.rx_missed_errors; 4932 stats->multicast = dev->stats.multicast; 4933 4934 /* 4935 * Fetch additional counter values missing in stats collected by driver 4936 * from tally counters. 4937 */ 4938 if (pm_runtime_active(&pdev->dev)) 4939 rtl8169_update_counters(tp); 4940 4941 /* 4942 * Subtract values fetched during initalization. 4943 * See rtl8169_init_counter_offsets for a description why we do that. 4944 */ 4945 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4946 le64_to_cpu(tp->tc_offset.tx_errors); 4947 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4948 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4949 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4950 le16_to_cpu(tp->tc_offset.tx_aborted); 4951 4952 pm_runtime_put_noidle(&pdev->dev); 4953 } 4954 4955 static void rtl8169_net_suspend(struct net_device *dev) 4956 { 4957 struct rtl8169_private *tp = netdev_priv(dev); 4958 4959 if (!netif_running(dev)) 4960 return; 4961 4962 phy_stop(tp->phydev); 4963 netif_device_detach(dev); 4964 4965 rtl_lock_work(tp); 4966 napi_disable(&tp->napi); 4967 /* Clear all task flags */ 4968 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4969 4970 rtl_unlock_work(tp); 4971 4972 rtl_pll_power_down(tp); 4973 } 4974 4975 #ifdef CONFIG_PM 4976 4977 static int rtl8169_suspend(struct device *device) 4978 { 4979 struct net_device *dev = dev_get_drvdata(device); 4980 struct rtl8169_private *tp = netdev_priv(dev); 4981 4982 rtl8169_net_suspend(dev); 4983 clk_disable_unprepare(tp->clk); 4984 4985 return 0; 4986 } 4987 4988 static void __rtl8169_resume(struct net_device *dev) 4989 { 4990 struct rtl8169_private *tp = netdev_priv(dev); 4991 4992 netif_device_attach(dev); 4993 4994 rtl_pll_power_up(tp); 4995 rtl8169_init_phy(tp); 4996 4997 phy_start(tp->phydev); 4998 4999 rtl_lock_work(tp); 5000 napi_enable(&tp->napi); 5001 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 5002 rtl_reset_work(tp); 5003 rtl_unlock_work(tp); 5004 } 5005 5006 static int rtl8169_resume(struct device *device) 5007 { 5008 struct net_device *dev = dev_get_drvdata(device); 5009 struct rtl8169_private *tp = netdev_priv(dev); 5010 5011 rtl_rar_set(tp, dev->dev_addr); 5012 5013 clk_prepare_enable(tp->clk); 5014 5015 if (netif_running(dev)) 5016 __rtl8169_resume(dev); 5017 5018 return 0; 5019 } 5020 5021 static int rtl8169_runtime_suspend(struct device *device) 5022 { 5023 struct net_device *dev = dev_get_drvdata(device); 5024 struct rtl8169_private *tp = netdev_priv(dev); 5025 5026 if (!tp->TxDescArray) 5027 return 0; 5028 5029 rtl_lock_work(tp); 5030 __rtl8169_set_wol(tp, WAKE_ANY); 5031 rtl_unlock_work(tp); 5032 5033 rtl8169_net_suspend(dev); 5034 5035 /* Update counters before going runtime suspend */ 5036 rtl8169_rx_missed(dev); 5037 rtl8169_update_counters(tp); 5038 5039 return 0; 5040 } 5041 5042 static int rtl8169_runtime_resume(struct device *device) 5043 { 5044 struct net_device *dev = dev_get_drvdata(device); 5045 struct rtl8169_private *tp = netdev_priv(dev); 5046 5047 rtl_rar_set(tp, dev->dev_addr); 5048 5049 if (!tp->TxDescArray) 5050 return 0; 5051 5052 rtl_lock_work(tp); 5053 __rtl8169_set_wol(tp, tp->saved_wolopts); 5054 rtl_unlock_work(tp); 5055 5056 __rtl8169_resume(dev); 5057 5058 return 0; 5059 } 5060 5061 static int rtl8169_runtime_idle(struct device *device) 5062 { 5063 struct net_device *dev = dev_get_drvdata(device); 5064 5065 if (!netif_running(dev) || !netif_carrier_ok(dev)) 5066 pm_schedule_suspend(device, 10000); 5067 5068 return -EBUSY; 5069 } 5070 5071 static const struct dev_pm_ops rtl8169_pm_ops = { 5072 .suspend = rtl8169_suspend, 5073 .resume = rtl8169_resume, 5074 .freeze = rtl8169_suspend, 5075 .thaw = rtl8169_resume, 5076 .poweroff = rtl8169_suspend, 5077 .restore = rtl8169_resume, 5078 .runtime_suspend = rtl8169_runtime_suspend, 5079 .runtime_resume = rtl8169_runtime_resume, 5080 .runtime_idle = rtl8169_runtime_idle, 5081 }; 5082 5083 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 5084 5085 #else /* !CONFIG_PM */ 5086 5087 #define RTL8169_PM_OPS NULL 5088 5089 #endif /* !CONFIG_PM */ 5090 5091 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 5092 { 5093 /* WoL fails with 8168b when the receiver is disabled. */ 5094 switch (tp->mac_version) { 5095 case RTL_GIGA_MAC_VER_11: 5096 case RTL_GIGA_MAC_VER_12: 5097 case RTL_GIGA_MAC_VER_17: 5098 pci_clear_master(tp->pci_dev); 5099 5100 RTL_W8(tp, ChipCmd, CmdRxEnb); 5101 /* PCI commit */ 5102 RTL_R8(tp, ChipCmd); 5103 break; 5104 default: 5105 break; 5106 } 5107 } 5108 5109 static void rtl_shutdown(struct pci_dev *pdev) 5110 { 5111 struct net_device *dev = pci_get_drvdata(pdev); 5112 struct rtl8169_private *tp = netdev_priv(dev); 5113 5114 rtl8169_net_suspend(dev); 5115 5116 /* Restore original MAC address */ 5117 rtl_rar_set(tp, dev->perm_addr); 5118 5119 rtl8169_hw_reset(tp); 5120 5121 if (system_state == SYSTEM_POWER_OFF) { 5122 if (tp->saved_wolopts) { 5123 rtl_wol_suspend_quirk(tp); 5124 rtl_wol_shutdown_quirk(tp); 5125 } 5126 5127 pci_wake_from_d3(pdev, true); 5128 pci_set_power_state(pdev, PCI_D3hot); 5129 } 5130 } 5131 5132 static void rtl_remove_one(struct pci_dev *pdev) 5133 { 5134 struct net_device *dev = pci_get_drvdata(pdev); 5135 struct rtl8169_private *tp = netdev_priv(dev); 5136 5137 if (r8168_check_dash(tp)) 5138 rtl8168_driver_stop(tp); 5139 5140 netif_napi_del(&tp->napi); 5141 5142 unregister_netdev(dev); 5143 mdiobus_unregister(tp->phydev->mdio.bus); 5144 5145 rtl_release_firmware(tp); 5146 5147 if (pci_dev_run_wake(pdev)) 5148 pm_runtime_get_noresume(&pdev->dev); 5149 5150 /* restore original MAC address */ 5151 rtl_rar_set(tp, dev->perm_addr); 5152 } 5153 5154 static const struct net_device_ops rtl_netdev_ops = { 5155 .ndo_open = rtl_open, 5156 .ndo_stop = rtl8169_close, 5157 .ndo_get_stats64 = rtl8169_get_stats64, 5158 .ndo_start_xmit = rtl8169_start_xmit, 5159 .ndo_features_check = rtl8169_features_check, 5160 .ndo_tx_timeout = rtl8169_tx_timeout, 5161 .ndo_validate_addr = eth_validate_addr, 5162 .ndo_change_mtu = rtl8169_change_mtu, 5163 .ndo_fix_features = rtl8169_fix_features, 5164 .ndo_set_features = rtl8169_set_features, 5165 .ndo_set_mac_address = rtl_set_mac_address, 5166 .ndo_do_ioctl = phy_do_ioctl_running, 5167 .ndo_set_rx_mode = rtl_set_rx_mode, 5168 #ifdef CONFIG_NET_POLL_CONTROLLER 5169 .ndo_poll_controller = rtl8169_netpoll, 5170 #endif 5171 5172 }; 5173 5174 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5175 { 5176 tp->irq_mask = RTL_EVENT_NAPI | LinkChg; 5177 5178 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5179 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5180 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5181 /* special workaround needed */ 5182 tp->irq_mask |= RxFIFOOver; 5183 else 5184 tp->irq_mask |= RxOverflow; 5185 } 5186 5187 static int rtl_alloc_irq(struct rtl8169_private *tp) 5188 { 5189 unsigned int flags; 5190 5191 switch (tp->mac_version) { 5192 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5193 rtl_unlock_config_regs(tp); 5194 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5195 rtl_lock_config_regs(tp); 5196 /* fall through */ 5197 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5198 flags = PCI_IRQ_LEGACY; 5199 break; 5200 default: 5201 flags = PCI_IRQ_ALL_TYPES; 5202 break; 5203 } 5204 5205 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5206 } 5207 5208 static void rtl_read_mac_address(struct rtl8169_private *tp, 5209 u8 mac_addr[ETH_ALEN]) 5210 { 5211 /* Get MAC address */ 5212 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5213 u32 value = rtl_eri_read(tp, 0xe0); 5214 5215 mac_addr[0] = (value >> 0) & 0xff; 5216 mac_addr[1] = (value >> 8) & 0xff; 5217 mac_addr[2] = (value >> 16) & 0xff; 5218 mac_addr[3] = (value >> 24) & 0xff; 5219 5220 value = rtl_eri_read(tp, 0xe4); 5221 mac_addr[4] = (value >> 0) & 0xff; 5222 mac_addr[5] = (value >> 8) & 0xff; 5223 } else if (rtl_is_8125(tp)) { 5224 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5225 } 5226 } 5227 5228 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5229 { 5230 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5231 } 5232 5233 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 5234 { 5235 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 5236 } 5237 5238 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5239 { 5240 struct rtl8169_private *tp = mii_bus->priv; 5241 5242 if (phyaddr > 0) 5243 return -ENODEV; 5244 5245 return rtl_readphy(tp, phyreg); 5246 } 5247 5248 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5249 int phyreg, u16 val) 5250 { 5251 struct rtl8169_private *tp = mii_bus->priv; 5252 5253 if (phyaddr > 0) 5254 return -ENODEV; 5255 5256 rtl_writephy(tp, phyreg, val); 5257 5258 return 0; 5259 } 5260 5261 static int r8169_mdio_register(struct rtl8169_private *tp) 5262 { 5263 struct pci_dev *pdev = tp->pci_dev; 5264 struct mii_bus *new_bus; 5265 int ret; 5266 5267 new_bus = devm_mdiobus_alloc(&pdev->dev); 5268 if (!new_bus) 5269 return -ENOMEM; 5270 5271 new_bus->name = "r8169"; 5272 new_bus->priv = tp; 5273 new_bus->parent = &pdev->dev; 5274 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5275 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5276 5277 new_bus->read = r8169_mdio_read_reg; 5278 new_bus->write = r8169_mdio_write_reg; 5279 5280 ret = mdiobus_register(new_bus); 5281 if (ret) 5282 return ret; 5283 5284 tp->phydev = mdiobus_get_phy(new_bus, 0); 5285 if (!tp->phydev) { 5286 mdiobus_unregister(new_bus); 5287 return -ENODEV; 5288 } else if (!tp->phydev->drv) { 5289 /* Most chip versions fail with the genphy driver. 5290 * Therefore ensure that the dedicated PHY driver is loaded. 5291 */ 5292 dev_err(&pdev->dev, "realtek.ko not loaded, maybe it needs to be added to initramfs?\n"); 5293 mdiobus_unregister(new_bus); 5294 return -EUNATCH; 5295 } 5296 5297 /* PHY will be woken up in rtl_open() */ 5298 phy_suspend(tp->phydev); 5299 5300 return 0; 5301 } 5302 5303 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5304 { 5305 tp->ocp_base = OCP_STD_PHY_BASE; 5306 5307 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 5308 5309 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 5310 return; 5311 5312 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 5313 return; 5314 5315 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5316 msleep(1); 5317 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5318 5319 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5320 5321 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 5322 return; 5323 5324 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5325 5326 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5327 } 5328 5329 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5330 { 5331 tp->ocp_base = OCP_STD_PHY_BASE; 5332 5333 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 5334 5335 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 5336 return; 5337 5338 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5339 msleep(1); 5340 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5341 5342 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5343 5344 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 5345 return; 5346 5347 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5348 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5349 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5350 5351 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5352 } 5353 5354 static void rtl_hw_initialize(struct rtl8169_private *tp) 5355 { 5356 switch (tp->mac_version) { 5357 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5358 rtl8168ep_stop_cmac(tp); 5359 /* fall through */ 5360 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5361 rtl_hw_init_8168g(tp); 5362 break; 5363 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 5364 rtl_hw_init_8125(tp); 5365 break; 5366 default: 5367 break; 5368 } 5369 } 5370 5371 static int rtl_jumbo_max(struct rtl8169_private *tp) 5372 { 5373 /* Non-GBit versions don't support jumbo frames */ 5374 if (!tp->supports_gmii) 5375 return 0; 5376 5377 switch (tp->mac_version) { 5378 /* RTL8169 */ 5379 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5380 return JUMBO_7K; 5381 /* RTL8168b */ 5382 case RTL_GIGA_MAC_VER_11: 5383 case RTL_GIGA_MAC_VER_12: 5384 case RTL_GIGA_MAC_VER_17: 5385 return JUMBO_4K; 5386 /* RTL8168c */ 5387 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5388 return JUMBO_6K; 5389 default: 5390 return JUMBO_9K; 5391 } 5392 } 5393 5394 static void rtl_disable_clk(void *data) 5395 { 5396 clk_disable_unprepare(data); 5397 } 5398 5399 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5400 { 5401 struct device *d = tp_to_dev(tp); 5402 struct clk *clk; 5403 int rc; 5404 5405 clk = devm_clk_get(d, "ether_clk"); 5406 if (IS_ERR(clk)) { 5407 rc = PTR_ERR(clk); 5408 if (rc == -ENOENT) 5409 /* clk-core allows NULL (for suspend / resume) */ 5410 rc = 0; 5411 else if (rc != -EPROBE_DEFER) 5412 dev_err(d, "failed to get clk: %d\n", rc); 5413 } else { 5414 tp->clk = clk; 5415 rc = clk_prepare_enable(clk); 5416 if (rc) 5417 dev_err(d, "failed to enable clk: %d\n", rc); 5418 else 5419 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5420 } 5421 5422 return rc; 5423 } 5424 5425 static void rtl_init_mac_address(struct rtl8169_private *tp) 5426 { 5427 struct net_device *dev = tp->dev; 5428 u8 *mac_addr = dev->dev_addr; 5429 int rc; 5430 5431 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5432 if (!rc) 5433 goto done; 5434 5435 rtl_read_mac_address(tp, mac_addr); 5436 if (is_valid_ether_addr(mac_addr)) 5437 goto done; 5438 5439 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5440 if (is_valid_ether_addr(mac_addr)) 5441 goto done; 5442 5443 eth_hw_addr_random(dev); 5444 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5445 done: 5446 rtl_rar_set(tp, mac_addr); 5447 } 5448 5449 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5450 { 5451 struct rtl8169_private *tp; 5452 struct net_device *dev; 5453 int chipset, region; 5454 int jumbo_max, rc; 5455 5456 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5457 if (!dev) 5458 return -ENOMEM; 5459 5460 SET_NETDEV_DEV(dev, &pdev->dev); 5461 dev->netdev_ops = &rtl_netdev_ops; 5462 tp = netdev_priv(dev); 5463 tp->dev = dev; 5464 tp->pci_dev = pdev; 5465 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 5466 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5467 tp->eee_adv = -1; 5468 5469 /* Get the *optional* external "ether_clk" used on some boards */ 5470 rc = rtl_get_ether_clk(tp); 5471 if (rc) 5472 return rc; 5473 5474 /* Disable ASPM completely as that cause random device stop working 5475 * problems as well as full system hangs for some PCIe devices users. 5476 */ 5477 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5478 PCIE_LINK_STATE_L1); 5479 tp->aspm_manageable = !rc; 5480 5481 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5482 rc = pcim_enable_device(pdev); 5483 if (rc < 0) { 5484 dev_err(&pdev->dev, "enable failure\n"); 5485 return rc; 5486 } 5487 5488 if (pcim_set_mwi(pdev) < 0) 5489 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5490 5491 /* use first MMIO region */ 5492 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5493 if (region < 0) { 5494 dev_err(&pdev->dev, "no MMIO resource found\n"); 5495 return -ENODEV; 5496 } 5497 5498 /* check for weird/broken PCI region reporting */ 5499 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5500 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5501 return -ENODEV; 5502 } 5503 5504 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5505 if (rc < 0) { 5506 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5507 return rc; 5508 } 5509 5510 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5511 5512 /* Identify chip attached to board */ 5513 rtl8169_get_mac_version(tp); 5514 if (tp->mac_version == RTL_GIGA_MAC_NONE) 5515 return -ENODEV; 5516 5517 tp->cp_cmd = RTL_R16(tp, CPlusCmd); 5518 5519 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5520 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5521 dev->features |= NETIF_F_HIGHDMA; 5522 5523 rtl_init_rxcfg(tp); 5524 5525 rtl8169_irq_mask_and_ack(tp); 5526 5527 rtl_hw_initialize(tp); 5528 5529 rtl_hw_reset(tp); 5530 5531 pci_set_master(pdev); 5532 5533 chipset = tp->mac_version; 5534 5535 rc = rtl_alloc_irq(tp); 5536 if (rc < 0) { 5537 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5538 return rc; 5539 } 5540 5541 mutex_init(&tp->wk.mutex); 5542 INIT_WORK(&tp->wk.work, rtl_task); 5543 u64_stats_init(&tp->rx_stats.syncp); 5544 u64_stats_init(&tp->tx_stats.syncp); 5545 5546 rtl_init_mac_address(tp); 5547 5548 dev->ethtool_ops = &rtl8169_ethtool_ops; 5549 5550 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5551 5552 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5553 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 5554 NETIF_F_HW_VLAN_CTAG_RX; 5555 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5556 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 5557 NETIF_F_HW_VLAN_CTAG_RX; 5558 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 5559 NETIF_F_HIGHDMA; 5560 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5561 5562 tp->cp_cmd |= RxChkSum; 5563 /* RTL8125 uses register RxConfig for VLAN offloading config */ 5564 if (!rtl_is_8125(tp)) 5565 tp->cp_cmd |= RxVlan; 5566 /* 5567 * Pretend we are using VLANs; This bypasses a nasty bug where 5568 * Interrupts stop flowing on high load on 8110SCd controllers. 5569 */ 5570 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5571 /* Disallow toggling */ 5572 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5573 5574 if (rtl_chip_supports_csum_v2(tp)) { 5575 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5576 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 5577 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5578 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5579 } else { 5580 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5581 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5582 } 5583 5584 /* RTL8168e-vl and one RTL8168c variant are known to have a 5585 * HW issue with TSO. 5586 */ 5587 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 5588 tp->mac_version == RTL_GIGA_MAC_VER_22) { 5589 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 5590 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 5591 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 5592 } 5593 5594 dev->hw_features |= NETIF_F_RXALL; 5595 dev->hw_features |= NETIF_F_RXFCS; 5596 5597 jumbo_max = rtl_jumbo_max(tp); 5598 if (jumbo_max) 5599 dev->max_mtu = jumbo_max; 5600 5601 rtl_set_irq_mask(tp); 5602 5603 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5604 5605 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5606 &tp->counters_phys_addr, 5607 GFP_KERNEL); 5608 if (!tp->counters) 5609 return -ENOMEM; 5610 5611 pci_set_drvdata(pdev, dev); 5612 5613 rc = r8169_mdio_register(tp); 5614 if (rc) 5615 return rc; 5616 5617 /* chip gets powered up in rtl_open() */ 5618 rtl_pll_power_down(tp); 5619 5620 rc = register_netdev(dev); 5621 if (rc) 5622 goto err_mdio_unregister; 5623 5624 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 5625 rtl_chip_infos[chipset].name, dev->dev_addr, 5626 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf, 5627 pci_irq_vector(pdev, 0)); 5628 5629 if (jumbo_max) 5630 netif_info(tp, probe, dev, 5631 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5632 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5633 "ok" : "ko"); 5634 5635 if (r8168_check_dash(tp)) 5636 rtl8168_driver_start(tp); 5637 5638 if (pci_dev_run_wake(pdev)) 5639 pm_runtime_put_sync(&pdev->dev); 5640 5641 return 0; 5642 5643 err_mdio_unregister: 5644 mdiobus_unregister(tp->phydev->mdio.bus); 5645 return rc; 5646 } 5647 5648 static struct pci_driver rtl8169_pci_driver = { 5649 .name = MODULENAME, 5650 .id_table = rtl8169_pci_tbl, 5651 .probe = rtl_init_one, 5652 .remove = rtl_remove_one, 5653 .shutdown = rtl_shutdown, 5654 .driver.pm = RTL8169_PM_OPS, 5655 }; 5656 5657 module_pci_driver(rtl8169_pci_driver); 5658