1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 61 #define MC_FILTER_LIMIT 32 62 63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 65 66 #define R8169_REGS_SIZE 256 67 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 68 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 69 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 72 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 73 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 74 75 #define OCP_STD_PHY_BASE 0xa400 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92 static const struct { 93 const char *name; 94 const char *fw_name; 95 } rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 143 }; 144 145 static const struct pci_device_id rtl8169_pci_tbl[] = { 146 { PCI_VDEVICE(REALTEK, 0x2502) }, 147 { PCI_VDEVICE(REALTEK, 0x2600) }, 148 { PCI_VDEVICE(REALTEK, 0x8129) }, 149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 150 { PCI_VDEVICE(REALTEK, 0x8161) }, 151 { PCI_VDEVICE(REALTEK, 0x8162) }, 152 { PCI_VDEVICE(REALTEK, 0x8167) }, 153 { PCI_VDEVICE(REALTEK, 0x8168) }, 154 { PCI_VDEVICE(NCUBE, 0x8168) }, 155 { PCI_VDEVICE(REALTEK, 0x8169) }, 156 { PCI_VENDOR_ID_DLINK, 0x4300, 157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 158 { PCI_VDEVICE(DLINK, 0x4300) }, 159 { PCI_VDEVICE(DLINK, 0x4302) }, 160 { PCI_VDEVICE(AT, 0xc107) }, 161 { PCI_VDEVICE(USR, 0x0116) }, 162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 164 { PCI_VDEVICE(REALTEK, 0x8125) }, 165 { PCI_VDEVICE(REALTEK, 0x3000) }, 166 {} 167 }; 168 169 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 170 171 enum rtl_registers { 172 MAC0 = 0, /* Ethernet hardware address. */ 173 MAC4 = 4, 174 MAR0 = 8, /* Multicast filter. */ 175 CounterAddrLow = 0x10, 176 CounterAddrHigh = 0x14, 177 TxDescStartAddrLow = 0x20, 178 TxDescStartAddrHigh = 0x24, 179 TxHDescStartAddrLow = 0x28, 180 TxHDescStartAddrHigh = 0x2c, 181 FLASH = 0x30, 182 ERSR = 0x36, 183 ChipCmd = 0x37, 184 TxPoll = 0x38, 185 IntrMask = 0x3c, 186 IntrStatus = 0x3e, 187 188 TxConfig = 0x40, 189 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 190 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 191 192 RxConfig = 0x44, 193 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 194 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 195 #define RXCFG_FIFO_SHIFT 13 196 /* No threshold before first PCI xfer */ 197 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 198 #define RX_EARLY_OFF (1 << 11) 199 #define RXCFG_DMA_SHIFT 8 200 /* Unlimited maximum PCI burst. */ 201 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 202 203 Cfg9346 = 0x50, 204 Config0 = 0x51, 205 Config1 = 0x52, 206 Config2 = 0x53, 207 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 208 209 Config3 = 0x54, 210 Config4 = 0x55, 211 Config5 = 0x56, 212 PHYAR = 0x60, 213 PHYstatus = 0x6c, 214 RxMaxSize = 0xda, 215 CPlusCmd = 0xe0, 216 IntrMitigate = 0xe2, 217 218 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 219 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 220 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 221 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 222 223 #define RTL_COALESCE_T_MAX 0x0fU 224 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 225 226 RxDescAddrLow = 0xe4, 227 RxDescAddrHigh = 0xe8, 228 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 229 230 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 231 232 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 233 234 #define TxPacketMax (8064 >> 7) 235 #define EarlySize 0x27 236 237 FuncEvent = 0xf0, 238 FuncEventMask = 0xf4, 239 FuncPresetState = 0xf8, 240 IBCR0 = 0xf8, 241 IBCR2 = 0xf9, 242 IBIMR0 = 0xfa, 243 IBISR0 = 0xfb, 244 FuncForceEvent = 0xfc, 245 }; 246 247 enum rtl8168_8101_registers { 248 CSIDR = 0x64, 249 CSIAR = 0x68, 250 #define CSIAR_FLAG 0x80000000 251 #define CSIAR_WRITE_CMD 0x80000000 252 #define CSIAR_BYTE_ENABLE 0x0000f000 253 #define CSIAR_ADDR_MASK 0x00000fff 254 PMCH = 0x6f, 255 #define D3COLD_NO_PLL_DOWN BIT(7) 256 #define D3HOT_NO_PLL_DOWN BIT(6) 257 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 258 EPHYAR = 0x80, 259 #define EPHYAR_FLAG 0x80000000 260 #define EPHYAR_WRITE_CMD 0x80000000 261 #define EPHYAR_REG_MASK 0x1f 262 #define EPHYAR_REG_SHIFT 16 263 #define EPHYAR_DATA_MASK 0xffff 264 DLLPR = 0xd0, 265 #define PFM_EN (1 << 6) 266 #define TX_10M_PS_EN (1 << 7) 267 DBG_REG = 0xd1, 268 #define FIX_NAK_1 (1 << 4) 269 #define FIX_NAK_2 (1 << 3) 270 TWSI = 0xd2, 271 MCU = 0xd3, 272 #define NOW_IS_OOB (1 << 7) 273 #define TX_EMPTY (1 << 5) 274 #define RX_EMPTY (1 << 4) 275 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 276 #define EN_NDP (1 << 3) 277 #define EN_OOB_RESET (1 << 2) 278 #define LINK_LIST_RDY (1 << 1) 279 EFUSEAR = 0xdc, 280 #define EFUSEAR_FLAG 0x80000000 281 #define EFUSEAR_WRITE_CMD 0x80000000 282 #define EFUSEAR_READ_CMD 0x00000000 283 #define EFUSEAR_REG_MASK 0x03ff 284 #define EFUSEAR_REG_SHIFT 8 285 #define EFUSEAR_DATA_MASK 0xff 286 MISC_1 = 0xf2, 287 #define PFM_D3COLD_EN (1 << 6) 288 }; 289 290 enum rtl8168_registers { 291 LED_FREQ = 0x1a, 292 EEE_LED = 0x1b, 293 ERIDR = 0x70, 294 ERIAR = 0x74, 295 #define ERIAR_FLAG 0x80000000 296 #define ERIAR_WRITE_CMD 0x80000000 297 #define ERIAR_READ_CMD 0x00000000 298 #define ERIAR_ADDR_BYTE_ALIGN 4 299 #define ERIAR_TYPE_SHIFT 16 300 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 301 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_MASK_SHIFT 12 305 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 306 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 310 EPHY_RXER_NUM = 0x7c, 311 OCPDR = 0xb0, /* OCP GPHY access */ 312 #define OCPDR_WRITE_CMD 0x80000000 313 #define OCPDR_READ_CMD 0x00000000 314 #define OCPDR_REG_MASK 0x7f 315 #define OCPDR_GPHY_REG_SHIFT 16 316 #define OCPDR_DATA_MASK 0xffff 317 OCPAR = 0xb4, 318 #define OCPAR_FLAG 0x80000000 319 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 320 #define OCPAR_GPHY_READ_CMD 0x0000f060 321 GPHY_OCP = 0xb8, 322 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 323 MISC = 0xf0, /* 8168e only. */ 324 #define TXPLA_RST (1 << 29) 325 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 326 #define PWM_EN (1 << 22) 327 #define RXDV_GATED_EN (1 << 19) 328 #define EARLY_TALLY_EN (1 << 16) 329 }; 330 331 enum rtl8125_registers { 332 IntrMask_8125 = 0x38, 333 IntrStatus_8125 = 0x3c, 334 TxPoll_8125 = 0x90, 335 MAC0_BKP = 0x19e0, 336 EEE_TXIDLE_TIMER_8125 = 0x6048, 337 }; 338 339 #define RX_VLAN_INNER_8125 BIT(22) 340 #define RX_VLAN_OUTER_8125 BIT(23) 341 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 342 343 #define RX_FETCH_DFLT_8125 (8 << 27) 344 345 enum rtl_register_content { 346 /* InterruptStatusBits */ 347 SYSErr = 0x8000, 348 PCSTimeout = 0x4000, 349 SWInt = 0x0100, 350 TxDescUnavail = 0x0080, 351 RxFIFOOver = 0x0040, 352 LinkChg = 0x0020, 353 RxOverflow = 0x0010, 354 TxErr = 0x0008, 355 TxOK = 0x0004, 356 RxErr = 0x0002, 357 RxOK = 0x0001, 358 359 /* RxStatusDesc */ 360 RxRWT = (1 << 22), 361 RxRES = (1 << 21), 362 RxRUNT = (1 << 20), 363 RxCRC = (1 << 19), 364 365 /* ChipCmdBits */ 366 StopReq = 0x80, 367 CmdReset = 0x10, 368 CmdRxEnb = 0x08, 369 CmdTxEnb = 0x04, 370 RxBufEmpty = 0x01, 371 372 /* TXPoll register p.5 */ 373 HPQ = 0x80, /* Poll cmd on the high prio queue */ 374 NPQ = 0x40, /* Poll cmd on the low prio queue */ 375 FSWInt = 0x01, /* Forced software interrupt */ 376 377 /* Cfg9346Bits */ 378 Cfg9346_Lock = 0x00, 379 Cfg9346_Unlock = 0xc0, 380 381 /* rx_mode_bits */ 382 AcceptErr = 0x20, 383 AcceptRunt = 0x10, 384 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 385 AcceptBroadcast = 0x08, 386 AcceptMulticast = 0x04, 387 AcceptMyPhys = 0x02, 388 AcceptAllPhys = 0x01, 389 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 390 #define RX_CONFIG_ACCEPT_MASK 0x3f 391 392 /* TxConfigBits */ 393 TxInterFrameGapShift = 24, 394 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 395 396 /* Config1 register p.24 */ 397 LEDS1 = (1 << 7), 398 LEDS0 = (1 << 6), 399 Speed_down = (1 << 4), 400 MEMMAP = (1 << 3), 401 IOMAP = (1 << 2), 402 VPD = (1 << 1), 403 PMEnable = (1 << 0), /* Power Management Enable */ 404 405 /* Config2 register p. 25 */ 406 ClkReqEn = (1 << 7), /* Clock Request Enable */ 407 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 408 PCI_Clock_66MHz = 0x01, 409 PCI_Clock_33MHz = 0x00, 410 411 /* Config3 register p.25 */ 412 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 413 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 414 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 415 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 416 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 417 418 /* Config4 register */ 419 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 420 421 /* Config5 register p.27 */ 422 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 423 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 424 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 425 Spi_en = (1 << 3), 426 LanWake = (1 << 1), /* LanWake enable/disable */ 427 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 428 ASPM_en = (1 << 0), /* ASPM enable */ 429 430 /* CPlusCmd p.31 */ 431 EnableBist = (1 << 15), // 8168 8101 432 Mac_dbgo_oe = (1 << 14), // 8168 8101 433 EnAnaPLL = (1 << 14), // 8169 434 Normal_mode = (1 << 13), // unused 435 Force_half_dup = (1 << 12), // 8168 8101 436 Force_rxflow_en = (1 << 11), // 8168 8101 437 Force_txflow_en = (1 << 10), // 8168 8101 438 Cxpl_dbg_sel = (1 << 9), // 8168 8101 439 ASF = (1 << 8), // 8168 8101 440 PktCntrDisable = (1 << 7), // 8168 8101 441 Mac_dbgo_sel = 0x001c, // 8168 442 RxVlan = (1 << 6), 443 RxChkSum = (1 << 5), 444 PCIDAC = (1 << 4), 445 PCIMulRW = (1 << 3), 446 #define INTT_MASK GENMASK(1, 0) 447 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 448 449 /* rtl8169_PHYstatus */ 450 TBI_Enable = 0x80, 451 TxFlowCtrl = 0x40, 452 RxFlowCtrl = 0x20, 453 _1000bpsF = 0x10, 454 _100bps = 0x08, 455 _10bps = 0x04, 456 LinkStatus = 0x02, 457 FullDup = 0x01, 458 459 /* ResetCounterCommand */ 460 CounterReset = 0x1, 461 462 /* DumpCounterCommand */ 463 CounterDump = 0x8, 464 465 /* magic enable v2 */ 466 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 467 }; 468 469 enum rtl_desc_bit { 470 /* First doubleword. */ 471 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 472 RingEnd = (1 << 30), /* End of descriptor ring */ 473 FirstFrag = (1 << 29), /* First segment of a packet */ 474 LastFrag = (1 << 28), /* Final segment of a packet */ 475 }; 476 477 /* Generic case. */ 478 enum rtl_tx_desc_bit { 479 /* First doubleword. */ 480 TD_LSO = (1 << 27), /* Large Send Offload */ 481 #define TD_MSS_MAX 0x07ffu /* MSS value */ 482 483 /* Second doubleword. */ 484 TxVlanTag = (1 << 17), /* Add VLAN tag */ 485 }; 486 487 /* 8169, 8168b and 810x except 8102e. */ 488 enum rtl_tx_desc_bit_0 { 489 /* First doubleword. */ 490 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 491 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 492 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 493 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 494 }; 495 496 /* 8102e, 8168c and beyond. */ 497 enum rtl_tx_desc_bit_1 { 498 /* First doubleword. */ 499 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 500 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 501 #define GTTCPHO_SHIFT 18 502 #define GTTCPHO_MAX 0x7f 503 504 /* Second doubleword. */ 505 #define TCPHO_SHIFT 18 506 #define TCPHO_MAX 0x3ff 507 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 508 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 509 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 510 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 511 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 512 }; 513 514 enum rtl_rx_desc_bit { 515 /* Rx private */ 516 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 517 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 518 519 #define RxProtoUDP (PID1) 520 #define RxProtoTCP (PID0) 521 #define RxProtoIP (PID1 | PID0) 522 #define RxProtoMask RxProtoIP 523 524 IPFail = (1 << 16), /* IP checksum failed */ 525 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 526 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 527 528 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 529 530 RxVlanTag = (1 << 16), /* VLAN tag available */ 531 }; 532 533 #define RTL_GSO_MAX_SIZE_V1 32000 534 #define RTL_GSO_MAX_SEGS_V1 24 535 #define RTL_GSO_MAX_SIZE_V2 64000 536 #define RTL_GSO_MAX_SEGS_V2 64 537 538 struct TxDesc { 539 __le32 opts1; 540 __le32 opts2; 541 __le64 addr; 542 }; 543 544 struct RxDesc { 545 __le32 opts1; 546 __le32 opts2; 547 __le64 addr; 548 }; 549 550 struct ring_info { 551 struct sk_buff *skb; 552 u32 len; 553 }; 554 555 struct rtl8169_counters { 556 __le64 tx_packets; 557 __le64 rx_packets; 558 __le64 tx_errors; 559 __le32 rx_errors; 560 __le16 rx_missed; 561 __le16 align_errors; 562 __le32 tx_one_collision; 563 __le32 tx_multi_collision; 564 __le64 rx_unicast; 565 __le64 rx_broadcast; 566 __le32 rx_multicast; 567 __le16 tx_aborted; 568 __le16 tx_underun; 569 }; 570 571 struct rtl8169_tc_offsets { 572 bool inited; 573 __le64 tx_errors; 574 __le32 tx_multi_collision; 575 __le16 tx_aborted; 576 __le16 rx_missed; 577 }; 578 579 enum rtl_flag { 580 RTL_FLAG_TASK_ENABLED = 0, 581 RTL_FLAG_TASK_RESET_PENDING, 582 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 583 RTL_FLAG_TASK_TX_TIMEOUT, 584 RTL_FLAG_MAX 585 }; 586 587 enum rtl_dash_type { 588 RTL_DASH_NONE, 589 RTL_DASH_DP, 590 RTL_DASH_EP, 591 }; 592 593 struct rtl8169_private { 594 void __iomem *mmio_addr; /* memory map physical address */ 595 struct pci_dev *pci_dev; 596 struct net_device *dev; 597 struct phy_device *phydev; 598 struct napi_struct napi; 599 enum mac_version mac_version; 600 enum rtl_dash_type dash_type; 601 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 602 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 603 u32 dirty_tx; 604 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 605 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 606 dma_addr_t TxPhyAddr; 607 dma_addr_t RxPhyAddr; 608 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 609 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 610 u16 cp_cmd; 611 u32 irq_mask; 612 int irq; 613 struct clk *clk; 614 615 struct { 616 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 617 struct work_struct work; 618 } wk; 619 620 raw_spinlock_t config25_lock; 621 raw_spinlock_t mac_ocp_lock; 622 623 raw_spinlock_t cfg9346_usage_lock; 624 int cfg9346_usage_count; 625 626 unsigned supports_gmii:1; 627 unsigned aspm_manageable:1; 628 unsigned dash_enabled:1; 629 dma_addr_t counters_phys_addr; 630 struct rtl8169_counters *counters; 631 struct rtl8169_tc_offsets tc_offset; 632 u32 saved_wolopts; 633 int eee_adv; 634 635 const char *fw_name; 636 struct rtl_fw *rtl_fw; 637 638 u32 ocp_base; 639 }; 640 641 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 642 643 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 644 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 645 MODULE_SOFTDEP("pre: realtek"); 646 MODULE_LICENSE("GPL"); 647 MODULE_FIRMWARE(FIRMWARE_8168D_1); 648 MODULE_FIRMWARE(FIRMWARE_8168D_2); 649 MODULE_FIRMWARE(FIRMWARE_8168E_1); 650 MODULE_FIRMWARE(FIRMWARE_8168E_2); 651 MODULE_FIRMWARE(FIRMWARE_8168E_3); 652 MODULE_FIRMWARE(FIRMWARE_8105E_1); 653 MODULE_FIRMWARE(FIRMWARE_8168F_1); 654 MODULE_FIRMWARE(FIRMWARE_8168F_2); 655 MODULE_FIRMWARE(FIRMWARE_8402_1); 656 MODULE_FIRMWARE(FIRMWARE_8411_1); 657 MODULE_FIRMWARE(FIRMWARE_8411_2); 658 MODULE_FIRMWARE(FIRMWARE_8106E_1); 659 MODULE_FIRMWARE(FIRMWARE_8106E_2); 660 MODULE_FIRMWARE(FIRMWARE_8168G_2); 661 MODULE_FIRMWARE(FIRMWARE_8168G_3); 662 MODULE_FIRMWARE(FIRMWARE_8168H_2); 663 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 664 MODULE_FIRMWARE(FIRMWARE_8107E_2); 665 MODULE_FIRMWARE(FIRMWARE_8125A_3); 666 MODULE_FIRMWARE(FIRMWARE_8125B_2); 667 668 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 669 { 670 return &tp->pci_dev->dev; 671 } 672 673 static void rtl_lock_config_regs(struct rtl8169_private *tp) 674 { 675 unsigned long flags; 676 677 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 678 if (!--tp->cfg9346_usage_count) 679 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 680 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 681 } 682 683 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 684 { 685 unsigned long flags; 686 687 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 688 if (!tp->cfg9346_usage_count++) 689 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 690 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 691 } 692 693 static void rtl_pci_commit(struct rtl8169_private *tp) 694 { 695 /* Read an arbitrary register to commit a preceding PCI write */ 696 RTL_R8(tp, ChipCmd); 697 } 698 699 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 700 { 701 unsigned long flags; 702 u8 val; 703 704 raw_spin_lock_irqsave(&tp->config25_lock, flags); 705 val = RTL_R8(tp, Config2); 706 RTL_W8(tp, Config2, (val & ~clear) | set); 707 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 708 } 709 710 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 711 { 712 unsigned long flags; 713 u8 val; 714 715 raw_spin_lock_irqsave(&tp->config25_lock, flags); 716 val = RTL_R8(tp, Config5); 717 RTL_W8(tp, Config5, (val & ~clear) | set); 718 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 719 } 720 721 static bool rtl_is_8125(struct rtl8169_private *tp) 722 { 723 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 724 } 725 726 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 727 { 728 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 729 tp->mac_version != RTL_GIGA_MAC_VER_39 && 730 tp->mac_version <= RTL_GIGA_MAC_VER_53; 731 } 732 733 static bool rtl_supports_eee(struct rtl8169_private *tp) 734 { 735 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 736 tp->mac_version != RTL_GIGA_MAC_VER_37 && 737 tp->mac_version != RTL_GIGA_MAC_VER_39; 738 } 739 740 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 741 { 742 int i; 743 744 for (i = 0; i < ETH_ALEN; i++) 745 mac[i] = RTL_R8(tp, reg + i); 746 } 747 748 struct rtl_cond { 749 bool (*check)(struct rtl8169_private *); 750 const char *msg; 751 }; 752 753 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 754 unsigned long usecs, int n, bool high) 755 { 756 int i; 757 758 for (i = 0; i < n; i++) { 759 if (c->check(tp) == high) 760 return true; 761 fsleep(usecs); 762 } 763 764 if (net_ratelimit()) 765 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 766 c->msg, !high, n, usecs); 767 return false; 768 } 769 770 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 771 const struct rtl_cond *c, 772 unsigned long d, int n) 773 { 774 return rtl_loop_wait(tp, c, d, n, true); 775 } 776 777 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 778 const struct rtl_cond *c, 779 unsigned long d, int n) 780 { 781 return rtl_loop_wait(tp, c, d, n, false); 782 } 783 784 #define DECLARE_RTL_COND(name) \ 785 static bool name ## _check(struct rtl8169_private *); \ 786 \ 787 static const struct rtl_cond name = { \ 788 .check = name ## _check, \ 789 .msg = #name \ 790 }; \ 791 \ 792 static bool name ## _check(struct rtl8169_private *tp) 793 794 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 795 { 796 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 797 if (type == ERIAR_OOB && 798 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 799 tp->mac_version == RTL_GIGA_MAC_VER_53)) 800 *cmd |= 0xf70 << 18; 801 } 802 803 DECLARE_RTL_COND(rtl_eriar_cond) 804 { 805 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 806 } 807 808 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 809 u32 val, int type) 810 { 811 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 812 813 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 814 return; 815 816 RTL_W32(tp, ERIDR, val); 817 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 818 RTL_W32(tp, ERIAR, cmd); 819 820 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 821 } 822 823 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 824 u32 val) 825 { 826 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 827 } 828 829 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 830 { 831 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 832 833 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 834 RTL_W32(tp, ERIAR, cmd); 835 836 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 837 RTL_R32(tp, ERIDR) : ~0; 838 } 839 840 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 841 { 842 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 843 } 844 845 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 846 { 847 u32 val = rtl_eri_read(tp, addr); 848 849 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 850 } 851 852 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 853 { 854 rtl_w0w1_eri(tp, addr, p, 0); 855 } 856 857 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 858 { 859 rtl_w0w1_eri(tp, addr, 0, m); 860 } 861 862 static bool rtl_ocp_reg_failure(u32 reg) 863 { 864 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 865 } 866 867 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 868 { 869 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 870 } 871 872 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 873 { 874 if (rtl_ocp_reg_failure(reg)) 875 return; 876 877 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 878 879 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 880 } 881 882 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 883 { 884 if (rtl_ocp_reg_failure(reg)) 885 return 0; 886 887 RTL_W32(tp, GPHY_OCP, reg << 15); 888 889 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 890 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 891 } 892 893 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 894 { 895 if (rtl_ocp_reg_failure(reg)) 896 return; 897 898 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 899 } 900 901 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 902 { 903 unsigned long flags; 904 905 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 906 __r8168_mac_ocp_write(tp, reg, data); 907 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 908 } 909 910 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 911 { 912 if (rtl_ocp_reg_failure(reg)) 913 return 0; 914 915 RTL_W32(tp, OCPDR, reg << 15); 916 917 return RTL_R32(tp, OCPDR); 918 } 919 920 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 921 { 922 unsigned long flags; 923 u16 val; 924 925 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 926 val = __r8168_mac_ocp_read(tp, reg); 927 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 928 929 return val; 930 } 931 932 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 933 u16 set) 934 { 935 unsigned long flags; 936 u16 data; 937 938 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 939 data = __r8168_mac_ocp_read(tp, reg); 940 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 941 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 942 } 943 944 /* Work around a hw issue with RTL8168g PHY, the quirk disables 945 * PHY MCU interrupts before PHY power-down. 946 */ 947 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 948 { 949 switch (tp->mac_version) { 950 case RTL_GIGA_MAC_VER_40: 951 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 952 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 953 else 954 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 955 break; 956 default: 957 break; 958 } 959 }; 960 961 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 962 { 963 if (reg == 0x1f) { 964 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 965 return; 966 } 967 968 if (tp->ocp_base != OCP_STD_PHY_BASE) 969 reg -= 0x10; 970 971 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 972 rtl8168g_phy_suspend_quirk(tp, value); 973 974 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 975 } 976 977 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 978 { 979 if (reg == 0x1f) 980 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 981 982 if (tp->ocp_base != OCP_STD_PHY_BASE) 983 reg -= 0x10; 984 985 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 986 } 987 988 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 989 { 990 if (reg == 0x1f) { 991 tp->ocp_base = value << 4; 992 return; 993 } 994 995 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 996 } 997 998 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 999 { 1000 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1001 } 1002 1003 DECLARE_RTL_COND(rtl_phyar_cond) 1004 { 1005 return RTL_R32(tp, PHYAR) & 0x80000000; 1006 } 1007 1008 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1009 { 1010 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1011 1012 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1013 /* 1014 * According to hardware specs a 20us delay is required after write 1015 * complete indication, but before sending next command. 1016 */ 1017 udelay(20); 1018 } 1019 1020 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1021 { 1022 int value; 1023 1024 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1025 1026 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1027 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1028 1029 /* 1030 * According to hardware specs a 20us delay is required after read 1031 * complete indication, but before sending next command. 1032 */ 1033 udelay(20); 1034 1035 return value; 1036 } 1037 1038 DECLARE_RTL_COND(rtl_ocpar_cond) 1039 { 1040 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1041 } 1042 1043 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1044 1045 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1046 { 1047 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1048 } 1049 1050 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1051 { 1052 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1053 } 1054 1055 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1056 { 1057 r8168dp_2_mdio_start(tp); 1058 1059 r8169_mdio_write(tp, reg, value); 1060 1061 r8168dp_2_mdio_stop(tp); 1062 } 1063 1064 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1065 { 1066 int value; 1067 1068 /* Work around issue with chip reporting wrong PHY ID */ 1069 if (reg == MII_PHYSID2) 1070 return 0xc912; 1071 1072 r8168dp_2_mdio_start(tp); 1073 1074 value = r8169_mdio_read(tp, reg); 1075 1076 r8168dp_2_mdio_stop(tp); 1077 1078 return value; 1079 } 1080 1081 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1082 { 1083 switch (tp->mac_version) { 1084 case RTL_GIGA_MAC_VER_28: 1085 case RTL_GIGA_MAC_VER_31: 1086 r8168dp_2_mdio_write(tp, location, val); 1087 break; 1088 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1089 r8168g_mdio_write(tp, location, val); 1090 break; 1091 default: 1092 r8169_mdio_write(tp, location, val); 1093 break; 1094 } 1095 } 1096 1097 static int rtl_readphy(struct rtl8169_private *tp, int location) 1098 { 1099 switch (tp->mac_version) { 1100 case RTL_GIGA_MAC_VER_28: 1101 case RTL_GIGA_MAC_VER_31: 1102 return r8168dp_2_mdio_read(tp, location); 1103 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1104 return r8168g_mdio_read(tp, location); 1105 default: 1106 return r8169_mdio_read(tp, location); 1107 } 1108 } 1109 1110 DECLARE_RTL_COND(rtl_ephyar_cond) 1111 { 1112 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1113 } 1114 1115 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1116 { 1117 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1118 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1119 1120 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1121 1122 udelay(10); 1123 } 1124 1125 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1126 { 1127 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1128 1129 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1130 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1131 } 1132 1133 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1134 { 1135 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1136 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1137 RTL_R32(tp, OCPDR) : ~0; 1138 } 1139 1140 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1141 { 1142 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1143 } 1144 1145 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1146 u32 data) 1147 { 1148 RTL_W32(tp, OCPDR, data); 1149 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1150 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1151 } 1152 1153 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1154 u32 data) 1155 { 1156 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1157 data, ERIAR_OOB); 1158 } 1159 1160 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1161 { 1162 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1163 1164 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1165 } 1166 1167 #define OOB_CMD_RESET 0x00 1168 #define OOB_CMD_DRIVER_START 0x05 1169 #define OOB_CMD_DRIVER_STOP 0x06 1170 1171 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1172 { 1173 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1174 } 1175 1176 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1177 { 1178 u16 reg; 1179 1180 reg = rtl8168_get_ocp_reg(tp); 1181 1182 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1183 } 1184 1185 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1186 { 1187 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1188 } 1189 1190 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1191 { 1192 return RTL_R8(tp, IBISR0) & 0x20; 1193 } 1194 1195 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1196 { 1197 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1198 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1199 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1200 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1201 } 1202 1203 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1204 { 1205 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1206 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1207 } 1208 1209 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1210 { 1211 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1212 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1213 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1214 } 1215 1216 static void rtl8168_driver_start(struct rtl8169_private *tp) 1217 { 1218 if (tp->dash_type == RTL_DASH_DP) 1219 rtl8168dp_driver_start(tp); 1220 else 1221 rtl8168ep_driver_start(tp); 1222 } 1223 1224 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1225 { 1226 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1227 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1228 } 1229 1230 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1231 { 1232 rtl8168ep_stop_cmac(tp); 1233 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1234 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1235 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1236 } 1237 1238 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1239 { 1240 if (tp->dash_type == RTL_DASH_DP) 1241 rtl8168dp_driver_stop(tp); 1242 else 1243 rtl8168ep_driver_stop(tp); 1244 } 1245 1246 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1247 { 1248 u16 reg = rtl8168_get_ocp_reg(tp); 1249 1250 return r8168dp_ocp_read(tp, reg) & BIT(15); 1251 } 1252 1253 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1254 { 1255 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1256 } 1257 1258 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1259 { 1260 switch (tp->dash_type) { 1261 case RTL_DASH_DP: 1262 return r8168dp_check_dash(tp); 1263 case RTL_DASH_EP: 1264 return r8168ep_check_dash(tp); 1265 default: 1266 return false; 1267 } 1268 } 1269 1270 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1271 { 1272 switch (tp->mac_version) { 1273 case RTL_GIGA_MAC_VER_28: 1274 case RTL_GIGA_MAC_VER_31: 1275 return RTL_DASH_DP; 1276 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1277 return RTL_DASH_EP; 1278 default: 1279 return RTL_DASH_NONE; 1280 } 1281 } 1282 1283 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1284 { 1285 switch (tp->mac_version) { 1286 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1287 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1288 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1289 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1290 if (enable) 1291 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1292 else 1293 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1294 break; 1295 default: 1296 break; 1297 } 1298 } 1299 1300 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1301 { 1302 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1303 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1304 } 1305 1306 DECLARE_RTL_COND(rtl_efusear_cond) 1307 { 1308 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1309 } 1310 1311 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1312 { 1313 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1314 1315 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1316 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1317 } 1318 1319 static u32 rtl_get_events(struct rtl8169_private *tp) 1320 { 1321 if (rtl_is_8125(tp)) 1322 return RTL_R32(tp, IntrStatus_8125); 1323 else 1324 return RTL_R16(tp, IntrStatus); 1325 } 1326 1327 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1328 { 1329 if (rtl_is_8125(tp)) 1330 RTL_W32(tp, IntrStatus_8125, bits); 1331 else 1332 RTL_W16(tp, IntrStatus, bits); 1333 } 1334 1335 static void rtl_irq_disable(struct rtl8169_private *tp) 1336 { 1337 if (rtl_is_8125(tp)) 1338 RTL_W32(tp, IntrMask_8125, 0); 1339 else 1340 RTL_W16(tp, IntrMask, 0); 1341 } 1342 1343 static void rtl_irq_enable(struct rtl8169_private *tp) 1344 { 1345 if (rtl_is_8125(tp)) 1346 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1347 else 1348 RTL_W16(tp, IntrMask, tp->irq_mask); 1349 } 1350 1351 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1352 { 1353 rtl_irq_disable(tp); 1354 rtl_ack_events(tp, 0xffffffff); 1355 rtl_pci_commit(tp); 1356 } 1357 1358 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1359 { 1360 struct phy_device *phydev = tp->phydev; 1361 1362 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1363 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1364 if (phydev->speed == SPEED_1000) { 1365 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1366 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1367 } else if (phydev->speed == SPEED_100) { 1368 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1369 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1370 } else { 1371 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1372 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1373 } 1374 rtl_reset_packet_filter(tp); 1375 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1376 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1377 if (phydev->speed == SPEED_1000) { 1378 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1379 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1380 } else { 1381 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1382 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1383 } 1384 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1385 if (phydev->speed == SPEED_10) { 1386 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1387 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1388 } else { 1389 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1390 } 1391 } 1392 } 1393 1394 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1395 1396 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1397 { 1398 struct rtl8169_private *tp = netdev_priv(dev); 1399 1400 wol->supported = WAKE_ANY; 1401 wol->wolopts = tp->saved_wolopts; 1402 } 1403 1404 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1405 { 1406 static const struct { 1407 u32 opt; 1408 u16 reg; 1409 u8 mask; 1410 } cfg[] = { 1411 { WAKE_PHY, Config3, LinkUp }, 1412 { WAKE_UCAST, Config5, UWF }, 1413 { WAKE_BCAST, Config5, BWF }, 1414 { WAKE_MCAST, Config5, MWF }, 1415 { WAKE_ANY, Config5, LanWake }, 1416 { WAKE_MAGIC, Config3, MagicPacket } 1417 }; 1418 unsigned int i, tmp = ARRAY_SIZE(cfg); 1419 unsigned long flags; 1420 u8 options; 1421 1422 rtl_unlock_config_regs(tp); 1423 1424 if (rtl_is_8168evl_up(tp)) { 1425 tmp--; 1426 if (wolopts & WAKE_MAGIC) 1427 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1428 else 1429 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1430 } else if (rtl_is_8125(tp)) { 1431 tmp--; 1432 if (wolopts & WAKE_MAGIC) 1433 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1434 else 1435 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1436 } 1437 1438 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1439 for (i = 0; i < tmp; i++) { 1440 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1441 if (wolopts & cfg[i].opt) 1442 options |= cfg[i].mask; 1443 RTL_W8(tp, cfg[i].reg, options); 1444 } 1445 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1446 1447 switch (tp->mac_version) { 1448 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1449 options = RTL_R8(tp, Config1) & ~PMEnable; 1450 if (wolopts) 1451 options |= PMEnable; 1452 RTL_W8(tp, Config1, options); 1453 break; 1454 case RTL_GIGA_MAC_VER_34: 1455 case RTL_GIGA_MAC_VER_37: 1456 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1457 if (wolopts) 1458 rtl_mod_config2(tp, 0, PME_SIGNAL); 1459 else 1460 rtl_mod_config2(tp, PME_SIGNAL, 0); 1461 break; 1462 default: 1463 break; 1464 } 1465 1466 rtl_lock_config_regs(tp); 1467 1468 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1469 1470 if (!tp->dash_enabled) { 1471 rtl_set_d3_pll_down(tp, !wolopts); 1472 tp->dev->wol_enabled = wolopts ? 1 : 0; 1473 } 1474 } 1475 1476 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1477 { 1478 struct rtl8169_private *tp = netdev_priv(dev); 1479 1480 if (wol->wolopts & ~WAKE_ANY) 1481 return -EINVAL; 1482 1483 tp->saved_wolopts = wol->wolopts; 1484 __rtl8169_set_wol(tp, tp->saved_wolopts); 1485 1486 return 0; 1487 } 1488 1489 static void rtl8169_get_drvinfo(struct net_device *dev, 1490 struct ethtool_drvinfo *info) 1491 { 1492 struct rtl8169_private *tp = netdev_priv(dev); 1493 struct rtl_fw *rtl_fw = tp->rtl_fw; 1494 1495 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1496 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1497 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1498 if (rtl_fw) 1499 strscpy(info->fw_version, rtl_fw->version, 1500 sizeof(info->fw_version)); 1501 } 1502 1503 static int rtl8169_get_regs_len(struct net_device *dev) 1504 { 1505 return R8169_REGS_SIZE; 1506 } 1507 1508 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1509 netdev_features_t features) 1510 { 1511 struct rtl8169_private *tp = netdev_priv(dev); 1512 1513 if (dev->mtu > TD_MSS_MAX) 1514 features &= ~NETIF_F_ALL_TSO; 1515 1516 if (dev->mtu > ETH_DATA_LEN && 1517 tp->mac_version > RTL_GIGA_MAC_VER_06) 1518 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1519 1520 return features; 1521 } 1522 1523 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1524 netdev_features_t features) 1525 { 1526 u32 rx_config = RTL_R32(tp, RxConfig); 1527 1528 if (features & NETIF_F_RXALL) 1529 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1530 else 1531 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1532 1533 if (rtl_is_8125(tp)) { 1534 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1535 rx_config |= RX_VLAN_8125; 1536 else 1537 rx_config &= ~RX_VLAN_8125; 1538 } 1539 1540 RTL_W32(tp, RxConfig, rx_config); 1541 } 1542 1543 static int rtl8169_set_features(struct net_device *dev, 1544 netdev_features_t features) 1545 { 1546 struct rtl8169_private *tp = netdev_priv(dev); 1547 1548 rtl_set_rx_config_features(tp, features); 1549 1550 if (features & NETIF_F_RXCSUM) 1551 tp->cp_cmd |= RxChkSum; 1552 else 1553 tp->cp_cmd &= ~RxChkSum; 1554 1555 if (!rtl_is_8125(tp)) { 1556 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1557 tp->cp_cmd |= RxVlan; 1558 else 1559 tp->cp_cmd &= ~RxVlan; 1560 } 1561 1562 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1563 rtl_pci_commit(tp); 1564 1565 return 0; 1566 } 1567 1568 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1569 { 1570 return (skb_vlan_tag_present(skb)) ? 1571 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1572 } 1573 1574 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1575 { 1576 u32 opts2 = le32_to_cpu(desc->opts2); 1577 1578 if (opts2 & RxVlanTag) 1579 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1580 } 1581 1582 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1583 void *p) 1584 { 1585 struct rtl8169_private *tp = netdev_priv(dev); 1586 u32 __iomem *data = tp->mmio_addr; 1587 u32 *dw = p; 1588 int i; 1589 1590 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1591 memcpy_fromio(dw++, data++, 4); 1592 } 1593 1594 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1595 "tx_packets", 1596 "rx_packets", 1597 "tx_errors", 1598 "rx_errors", 1599 "rx_missed", 1600 "align_errors", 1601 "tx_single_collisions", 1602 "tx_multi_collisions", 1603 "unicast", 1604 "broadcast", 1605 "multicast", 1606 "tx_aborted", 1607 "tx_underrun", 1608 }; 1609 1610 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1611 { 1612 switch (sset) { 1613 case ETH_SS_STATS: 1614 return ARRAY_SIZE(rtl8169_gstrings); 1615 default: 1616 return -EOPNOTSUPP; 1617 } 1618 } 1619 1620 DECLARE_RTL_COND(rtl_counters_cond) 1621 { 1622 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1623 } 1624 1625 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1626 { 1627 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1628 1629 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1630 rtl_pci_commit(tp); 1631 RTL_W32(tp, CounterAddrLow, cmd); 1632 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1633 1634 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1635 } 1636 1637 static void rtl8169_update_counters(struct rtl8169_private *tp) 1638 { 1639 u8 val = RTL_R8(tp, ChipCmd); 1640 1641 /* 1642 * Some chips are unable to dump tally counters when the receiver 1643 * is disabled. If 0xff chip may be in a PCI power-save state. 1644 */ 1645 if (val & CmdRxEnb && val != 0xff) 1646 rtl8169_do_counters(tp, CounterDump); 1647 } 1648 1649 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1650 { 1651 struct rtl8169_counters *counters = tp->counters; 1652 1653 /* 1654 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1655 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1656 * reset by a power cycle, while the counter values collected by the 1657 * driver are reset at every driver unload/load cycle. 1658 * 1659 * To make sure the HW values returned by @get_stats64 match the SW 1660 * values, we collect the initial values at first open(*) and use them 1661 * as offsets to normalize the values returned by @get_stats64. 1662 * 1663 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1664 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1665 * set at open time by rtl_hw_start. 1666 */ 1667 1668 if (tp->tc_offset.inited) 1669 return; 1670 1671 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1672 rtl8169_do_counters(tp, CounterReset); 1673 } else { 1674 rtl8169_update_counters(tp); 1675 tp->tc_offset.tx_errors = counters->tx_errors; 1676 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1677 tp->tc_offset.tx_aborted = counters->tx_aborted; 1678 tp->tc_offset.rx_missed = counters->rx_missed; 1679 } 1680 1681 tp->tc_offset.inited = true; 1682 } 1683 1684 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1685 struct ethtool_stats *stats, u64 *data) 1686 { 1687 struct rtl8169_private *tp = netdev_priv(dev); 1688 struct rtl8169_counters *counters; 1689 1690 counters = tp->counters; 1691 rtl8169_update_counters(tp); 1692 1693 data[0] = le64_to_cpu(counters->tx_packets); 1694 data[1] = le64_to_cpu(counters->rx_packets); 1695 data[2] = le64_to_cpu(counters->tx_errors); 1696 data[3] = le32_to_cpu(counters->rx_errors); 1697 data[4] = le16_to_cpu(counters->rx_missed); 1698 data[5] = le16_to_cpu(counters->align_errors); 1699 data[6] = le32_to_cpu(counters->tx_one_collision); 1700 data[7] = le32_to_cpu(counters->tx_multi_collision); 1701 data[8] = le64_to_cpu(counters->rx_unicast); 1702 data[9] = le64_to_cpu(counters->rx_broadcast); 1703 data[10] = le32_to_cpu(counters->rx_multicast); 1704 data[11] = le16_to_cpu(counters->tx_aborted); 1705 data[12] = le16_to_cpu(counters->tx_underun); 1706 } 1707 1708 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1709 { 1710 switch(stringset) { 1711 case ETH_SS_STATS: 1712 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1713 break; 1714 } 1715 } 1716 1717 /* 1718 * Interrupt coalescing 1719 * 1720 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1721 * > 8169, 8168 and 810x line of chipsets 1722 * 1723 * 8169, 8168, and 8136(810x) serial chipsets support it. 1724 * 1725 * > 2 - the Tx timer unit at gigabit speed 1726 * 1727 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1728 * (0xe0) bit 1 and bit 0. 1729 * 1730 * For 8169 1731 * bit[1:0] \ speed 1000M 100M 10M 1732 * 0 0 320ns 2.56us 40.96us 1733 * 0 1 2.56us 20.48us 327.7us 1734 * 1 0 5.12us 40.96us 655.4us 1735 * 1 1 10.24us 81.92us 1.31ms 1736 * 1737 * For the other 1738 * bit[1:0] \ speed 1000M 100M 10M 1739 * 0 0 5us 2.56us 40.96us 1740 * 0 1 40us 20.48us 327.7us 1741 * 1 0 80us 40.96us 655.4us 1742 * 1 1 160us 81.92us 1.31ms 1743 */ 1744 1745 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1746 struct rtl_coalesce_info { 1747 u32 speed; 1748 u32 scale_nsecs[4]; 1749 }; 1750 1751 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1752 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1753 1754 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1755 { SPEED_1000, COALESCE_DELAY(320) }, 1756 { SPEED_100, COALESCE_DELAY(2560) }, 1757 { SPEED_10, COALESCE_DELAY(40960) }, 1758 { 0 }, 1759 }; 1760 1761 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1762 { SPEED_1000, COALESCE_DELAY(5000) }, 1763 { SPEED_100, COALESCE_DELAY(2560) }, 1764 { SPEED_10, COALESCE_DELAY(40960) }, 1765 { 0 }, 1766 }; 1767 #undef COALESCE_DELAY 1768 1769 /* get rx/tx scale vector corresponding to current speed */ 1770 static const struct rtl_coalesce_info * 1771 rtl_coalesce_info(struct rtl8169_private *tp) 1772 { 1773 const struct rtl_coalesce_info *ci; 1774 1775 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1776 ci = rtl_coalesce_info_8169; 1777 else 1778 ci = rtl_coalesce_info_8168_8136; 1779 1780 /* if speed is unknown assume highest one */ 1781 if (tp->phydev->speed == SPEED_UNKNOWN) 1782 return ci; 1783 1784 for (; ci->speed; ci++) { 1785 if (tp->phydev->speed == ci->speed) 1786 return ci; 1787 } 1788 1789 return ERR_PTR(-ELNRNG); 1790 } 1791 1792 static int rtl_get_coalesce(struct net_device *dev, 1793 struct ethtool_coalesce *ec, 1794 struct kernel_ethtool_coalesce *kernel_coal, 1795 struct netlink_ext_ack *extack) 1796 { 1797 struct rtl8169_private *tp = netdev_priv(dev); 1798 const struct rtl_coalesce_info *ci; 1799 u32 scale, c_us, c_fr; 1800 u16 intrmit; 1801 1802 if (rtl_is_8125(tp)) 1803 return -EOPNOTSUPP; 1804 1805 memset(ec, 0, sizeof(*ec)); 1806 1807 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1808 ci = rtl_coalesce_info(tp); 1809 if (IS_ERR(ci)) 1810 return PTR_ERR(ci); 1811 1812 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1813 1814 intrmit = RTL_R16(tp, IntrMitigate); 1815 1816 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1817 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1818 1819 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1820 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1821 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1822 1823 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1824 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1825 1826 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1827 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1828 1829 return 0; 1830 } 1831 1832 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1833 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1834 u16 *cp01) 1835 { 1836 const struct rtl_coalesce_info *ci; 1837 u16 i; 1838 1839 ci = rtl_coalesce_info(tp); 1840 if (IS_ERR(ci)) 1841 return PTR_ERR(ci); 1842 1843 for (i = 0; i < 4; i++) { 1844 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1845 *cp01 = i; 1846 return ci->scale_nsecs[i]; 1847 } 1848 } 1849 1850 return -ERANGE; 1851 } 1852 1853 static int rtl_set_coalesce(struct net_device *dev, 1854 struct ethtool_coalesce *ec, 1855 struct kernel_ethtool_coalesce *kernel_coal, 1856 struct netlink_ext_ack *extack) 1857 { 1858 struct rtl8169_private *tp = netdev_priv(dev); 1859 u32 tx_fr = ec->tx_max_coalesced_frames; 1860 u32 rx_fr = ec->rx_max_coalesced_frames; 1861 u32 coal_usec_max, units; 1862 u16 w = 0, cp01 = 0; 1863 int scale; 1864 1865 if (rtl_is_8125(tp)) 1866 return -EOPNOTSUPP; 1867 1868 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1869 return -ERANGE; 1870 1871 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1872 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1873 if (scale < 0) 1874 return scale; 1875 1876 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1877 * not only when usecs=0 because of e.g. the following scenario: 1878 * 1879 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1880 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1881 * - then user does `ethtool -C eth0 rx-usecs 100` 1882 * 1883 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1884 * if we want to ignore rx_frames then it has to be set to 0. 1885 */ 1886 if (rx_fr == 1) 1887 rx_fr = 0; 1888 if (tx_fr == 1) 1889 tx_fr = 0; 1890 1891 /* HW requires time limit to be set if frame limit is set */ 1892 if ((tx_fr && !ec->tx_coalesce_usecs) || 1893 (rx_fr && !ec->rx_coalesce_usecs)) 1894 return -EINVAL; 1895 1896 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1897 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1898 1899 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1900 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1901 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1902 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1903 1904 RTL_W16(tp, IntrMitigate, w); 1905 1906 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1907 if (rtl_is_8168evl_up(tp)) { 1908 if (!rx_fr && !tx_fr) 1909 /* disable packet counter */ 1910 tp->cp_cmd |= PktCntrDisable; 1911 else 1912 tp->cp_cmd &= ~PktCntrDisable; 1913 } 1914 1915 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1916 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1917 rtl_pci_commit(tp); 1918 1919 return 0; 1920 } 1921 1922 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1923 { 1924 struct rtl8169_private *tp = netdev_priv(dev); 1925 1926 if (!rtl_supports_eee(tp)) 1927 return -EOPNOTSUPP; 1928 1929 return phy_ethtool_get_eee(tp->phydev, data); 1930 } 1931 1932 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1933 { 1934 struct rtl8169_private *tp = netdev_priv(dev); 1935 int ret; 1936 1937 if (!rtl_supports_eee(tp)) 1938 return -EOPNOTSUPP; 1939 1940 ret = phy_ethtool_set_eee(tp->phydev, data); 1941 1942 if (!ret) 1943 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1944 MDIO_AN_EEE_ADV); 1945 return ret; 1946 } 1947 1948 static void rtl8169_get_ringparam(struct net_device *dev, 1949 struct ethtool_ringparam *data, 1950 struct kernel_ethtool_ringparam *kernel_data, 1951 struct netlink_ext_ack *extack) 1952 { 1953 data->rx_max_pending = NUM_RX_DESC; 1954 data->rx_pending = NUM_RX_DESC; 1955 data->tx_max_pending = NUM_TX_DESC; 1956 data->tx_pending = NUM_TX_DESC; 1957 } 1958 1959 static void rtl8169_get_pauseparam(struct net_device *dev, 1960 struct ethtool_pauseparam *data) 1961 { 1962 struct rtl8169_private *tp = netdev_priv(dev); 1963 bool tx_pause, rx_pause; 1964 1965 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1966 1967 data->autoneg = tp->phydev->autoneg; 1968 data->tx_pause = tx_pause ? 1 : 0; 1969 data->rx_pause = rx_pause ? 1 : 0; 1970 } 1971 1972 static int rtl8169_set_pauseparam(struct net_device *dev, 1973 struct ethtool_pauseparam *data) 1974 { 1975 struct rtl8169_private *tp = netdev_priv(dev); 1976 1977 if (dev->mtu > ETH_DATA_LEN) 1978 return -EOPNOTSUPP; 1979 1980 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1981 1982 return 0; 1983 } 1984 1985 static const struct ethtool_ops rtl8169_ethtool_ops = { 1986 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1987 ETHTOOL_COALESCE_MAX_FRAMES, 1988 .get_drvinfo = rtl8169_get_drvinfo, 1989 .get_regs_len = rtl8169_get_regs_len, 1990 .get_link = ethtool_op_get_link, 1991 .get_coalesce = rtl_get_coalesce, 1992 .set_coalesce = rtl_set_coalesce, 1993 .get_regs = rtl8169_get_regs, 1994 .get_wol = rtl8169_get_wol, 1995 .set_wol = rtl8169_set_wol, 1996 .get_strings = rtl8169_get_strings, 1997 .get_sset_count = rtl8169_get_sset_count, 1998 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1999 .get_ts_info = ethtool_op_get_ts_info, 2000 .nway_reset = phy_ethtool_nway_reset, 2001 .get_eee = rtl8169_get_eee, 2002 .set_eee = rtl8169_set_eee, 2003 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2004 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2005 .get_ringparam = rtl8169_get_ringparam, 2006 .get_pauseparam = rtl8169_get_pauseparam, 2007 .set_pauseparam = rtl8169_set_pauseparam, 2008 }; 2009 2010 static void rtl_enable_eee(struct rtl8169_private *tp) 2011 { 2012 struct phy_device *phydev = tp->phydev; 2013 int adv; 2014 2015 /* respect EEE advertisement the user may have set */ 2016 if (tp->eee_adv >= 0) 2017 adv = tp->eee_adv; 2018 else 2019 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2020 2021 if (adv >= 0) 2022 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2023 } 2024 2025 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2026 { 2027 /* 2028 * The driver currently handles the 8168Bf and the 8168Be identically 2029 * but they can be identified more specifically through the test below 2030 * if needed: 2031 * 2032 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2033 * 2034 * Same thing for the 8101Eb and the 8101Ec: 2035 * 2036 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2037 */ 2038 static const struct rtl_mac_info { 2039 u16 mask; 2040 u16 val; 2041 enum mac_version ver; 2042 } mac_info[] = { 2043 /* 8125B family. */ 2044 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2045 2046 /* 8125A family. */ 2047 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2048 /* It seems only XID 609 made it to the mass market. 2049 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2050 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2051 */ 2052 2053 /* RTL8117 */ 2054 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2055 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2056 2057 /* 8168EP family. */ 2058 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2059 /* It seems this chip version never made it to 2060 * the wild. Let's disable detection. 2061 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2062 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2063 */ 2064 2065 /* 8168H family. */ 2066 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2067 /* It seems this chip version never made it to 2068 * the wild. Let's disable detection. 2069 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2070 */ 2071 2072 /* 8168G family. */ 2073 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2074 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2075 /* It seems this chip version never made it to 2076 * the wild. Let's disable detection. 2077 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2078 */ 2079 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2080 2081 /* 8168F family. */ 2082 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2083 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2084 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2085 2086 /* 8168E family. */ 2087 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2088 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2089 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2090 2091 /* 8168D family. */ 2092 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2093 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2094 2095 /* 8168DP family. */ 2096 /* It seems this early RTL8168dp version never made it to 2097 * the wild. Support has been removed. 2098 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2099 */ 2100 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2101 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2102 2103 /* 8168C family. */ 2104 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2105 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2106 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2107 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2108 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2109 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2110 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2111 2112 /* 8168B family. */ 2113 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2114 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2115 2116 /* 8101 family. */ 2117 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2118 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2119 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2120 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2121 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2122 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2123 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2124 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2125 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2126 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2127 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2128 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2129 2130 /* 8110 family. */ 2131 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2132 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2133 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2134 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2135 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2136 2137 /* Catch-all */ 2138 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2139 }; 2140 const struct rtl_mac_info *p = mac_info; 2141 enum mac_version ver; 2142 2143 while ((xid & p->mask) != p->val) 2144 p++; 2145 ver = p->ver; 2146 2147 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2148 if (ver == RTL_GIGA_MAC_VER_42) 2149 ver = RTL_GIGA_MAC_VER_43; 2150 else if (ver == RTL_GIGA_MAC_VER_46) 2151 ver = RTL_GIGA_MAC_VER_48; 2152 } 2153 2154 return ver; 2155 } 2156 2157 static void rtl_release_firmware(struct rtl8169_private *tp) 2158 { 2159 if (tp->rtl_fw) { 2160 rtl_fw_release_firmware(tp->rtl_fw); 2161 kfree(tp->rtl_fw); 2162 tp->rtl_fw = NULL; 2163 } 2164 } 2165 2166 void r8169_apply_firmware(struct rtl8169_private *tp) 2167 { 2168 int val; 2169 2170 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2171 if (tp->rtl_fw) { 2172 rtl_fw_write_firmware(tp, tp->rtl_fw); 2173 /* At least one firmware doesn't reset tp->ocp_base. */ 2174 tp->ocp_base = OCP_STD_PHY_BASE; 2175 2176 /* PHY soft reset may still be in progress */ 2177 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2178 !(val & BMCR_RESET), 2179 50000, 600000, true); 2180 } 2181 } 2182 2183 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2184 { 2185 /* Adjust EEE LED frequency */ 2186 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2187 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2188 2189 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2190 } 2191 2192 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2193 { 2194 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2195 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2196 } 2197 2198 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2199 { 2200 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2201 } 2202 2203 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2204 { 2205 rtl8125_set_eee_txidle_timer(tp); 2206 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2207 } 2208 2209 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2210 { 2211 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2212 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2213 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2214 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2215 } 2216 2217 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2218 { 2219 u16 data1, data2, ioffset; 2220 2221 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2222 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2223 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2224 2225 ioffset = (data2 >> 1) & 0x7ff8; 2226 ioffset |= data2 & 0x0007; 2227 if (data1 & BIT(7)) 2228 ioffset |= BIT(15); 2229 2230 return ioffset; 2231 } 2232 2233 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2234 { 2235 set_bit(flag, tp->wk.flags); 2236 schedule_work(&tp->wk.work); 2237 } 2238 2239 static void rtl8169_init_phy(struct rtl8169_private *tp) 2240 { 2241 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2242 2243 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2244 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2245 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2246 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2247 RTL_W8(tp, 0x82, 0x01); 2248 } 2249 2250 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2251 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2252 tp->pci_dev->subsystem_device == 0xe000) 2253 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2254 2255 /* We may have called phy_speed_down before */ 2256 phy_speed_up(tp->phydev); 2257 2258 if (rtl_supports_eee(tp)) 2259 rtl_enable_eee(tp); 2260 2261 genphy_soft_reset(tp->phydev); 2262 } 2263 2264 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2265 { 2266 rtl_unlock_config_regs(tp); 2267 2268 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2269 rtl_pci_commit(tp); 2270 2271 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2272 rtl_pci_commit(tp); 2273 2274 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2275 rtl_rar_exgmac_set(tp, addr); 2276 2277 rtl_lock_config_regs(tp); 2278 } 2279 2280 static int rtl_set_mac_address(struct net_device *dev, void *p) 2281 { 2282 struct rtl8169_private *tp = netdev_priv(dev); 2283 int ret; 2284 2285 ret = eth_mac_addr(dev, p); 2286 if (ret) 2287 return ret; 2288 2289 rtl_rar_set(tp, dev->dev_addr); 2290 2291 return 0; 2292 } 2293 2294 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2295 { 2296 switch (tp->mac_version) { 2297 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2298 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2299 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2300 break; 2301 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2302 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2303 case RTL_GIGA_MAC_VER_38: 2304 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2305 break; 2306 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2307 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2308 break; 2309 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2310 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2311 break; 2312 default: 2313 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2314 break; 2315 } 2316 } 2317 2318 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2319 { 2320 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2321 } 2322 2323 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2324 { 2325 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2326 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2327 } 2328 2329 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2330 { 2331 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2332 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2333 } 2334 2335 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2336 { 2337 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2338 } 2339 2340 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2341 { 2342 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2343 } 2344 2345 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2346 { 2347 RTL_W8(tp, MaxTxPacketSize, 0x24); 2348 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2349 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2350 } 2351 2352 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2353 { 2354 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2355 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2356 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2357 } 2358 2359 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2360 { 2361 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2362 } 2363 2364 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2365 { 2366 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2367 } 2368 2369 static void rtl_jumbo_config(struct rtl8169_private *tp) 2370 { 2371 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2372 int readrq = 4096; 2373 2374 rtl_unlock_config_regs(tp); 2375 switch (tp->mac_version) { 2376 case RTL_GIGA_MAC_VER_17: 2377 if (jumbo) { 2378 readrq = 512; 2379 r8168b_1_hw_jumbo_enable(tp); 2380 } else { 2381 r8168b_1_hw_jumbo_disable(tp); 2382 } 2383 break; 2384 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2385 if (jumbo) { 2386 readrq = 512; 2387 r8168c_hw_jumbo_enable(tp); 2388 } else { 2389 r8168c_hw_jumbo_disable(tp); 2390 } 2391 break; 2392 case RTL_GIGA_MAC_VER_28: 2393 if (jumbo) 2394 r8168dp_hw_jumbo_enable(tp); 2395 else 2396 r8168dp_hw_jumbo_disable(tp); 2397 break; 2398 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2399 if (jumbo) 2400 r8168e_hw_jumbo_enable(tp); 2401 else 2402 r8168e_hw_jumbo_disable(tp); 2403 break; 2404 default: 2405 break; 2406 } 2407 rtl_lock_config_regs(tp); 2408 2409 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2410 pcie_set_readrq(tp->pci_dev, readrq); 2411 2412 /* Chip doesn't support pause in jumbo mode */ 2413 if (jumbo) { 2414 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2415 tp->phydev->advertising); 2416 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2417 tp->phydev->advertising); 2418 phy_start_aneg(tp->phydev); 2419 } 2420 } 2421 2422 DECLARE_RTL_COND(rtl_chipcmd_cond) 2423 { 2424 return RTL_R8(tp, ChipCmd) & CmdReset; 2425 } 2426 2427 static void rtl_hw_reset(struct rtl8169_private *tp) 2428 { 2429 RTL_W8(tp, ChipCmd, CmdReset); 2430 2431 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2432 } 2433 2434 static void rtl_request_firmware(struct rtl8169_private *tp) 2435 { 2436 struct rtl_fw *rtl_fw; 2437 2438 /* firmware loaded already or no firmware available */ 2439 if (tp->rtl_fw || !tp->fw_name) 2440 return; 2441 2442 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2443 if (!rtl_fw) 2444 return; 2445 2446 rtl_fw->phy_write = rtl_writephy; 2447 rtl_fw->phy_read = rtl_readphy; 2448 rtl_fw->mac_mcu_write = mac_mcu_write; 2449 rtl_fw->mac_mcu_read = mac_mcu_read; 2450 rtl_fw->fw_name = tp->fw_name; 2451 rtl_fw->dev = tp_to_dev(tp); 2452 2453 if (rtl_fw_request_firmware(rtl_fw)) 2454 kfree(rtl_fw); 2455 else 2456 tp->rtl_fw = rtl_fw; 2457 } 2458 2459 static void rtl_rx_close(struct rtl8169_private *tp) 2460 { 2461 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2462 } 2463 2464 DECLARE_RTL_COND(rtl_npq_cond) 2465 { 2466 return RTL_R8(tp, TxPoll) & NPQ; 2467 } 2468 2469 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2470 { 2471 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2472 } 2473 2474 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2475 { 2476 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2477 } 2478 2479 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2480 { 2481 /* IntrMitigate has new functionality on RTL8125 */ 2482 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2483 } 2484 2485 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2486 { 2487 switch (tp->mac_version) { 2488 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2489 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2490 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2491 break; 2492 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2493 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2494 break; 2495 case RTL_GIGA_MAC_VER_63: 2496 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2497 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2498 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2499 break; 2500 default: 2501 break; 2502 } 2503 } 2504 2505 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2506 { 2507 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2508 } 2509 2510 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2511 { 2512 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2513 fsleep(2000); 2514 rtl_wait_txrx_fifo_empty(tp); 2515 } 2516 2517 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2518 { 2519 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2520 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2521 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2522 2523 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2524 rtl_disable_rxdvgate(tp); 2525 } 2526 2527 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2528 { 2529 if (tp->dash_enabled) 2530 return; 2531 2532 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2533 tp->mac_version == RTL_GIGA_MAC_VER_33) 2534 rtl_ephy_write(tp, 0x19, 0xff64); 2535 2536 if (device_may_wakeup(tp_to_dev(tp))) { 2537 phy_speed_down(tp->phydev, false); 2538 rtl_wol_enable_rx(tp); 2539 } 2540 } 2541 2542 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2543 { 2544 u32 val = TX_DMA_BURST << TxDMAShift | 2545 InterFrameGap << TxInterFrameGapShift; 2546 2547 if (rtl_is_8168evl_up(tp)) 2548 val |= TXCFG_AUTO_FIFO; 2549 2550 RTL_W32(tp, TxConfig, val); 2551 } 2552 2553 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2554 { 2555 /* Low hurts. Let's disable the filtering. */ 2556 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2557 } 2558 2559 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2560 { 2561 /* 2562 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2563 * register to be written before TxDescAddrLow to work. 2564 * Switching from MMIO to I/O access fixes the issue as well. 2565 */ 2566 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2567 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2568 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2569 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2570 } 2571 2572 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2573 { 2574 u32 val; 2575 2576 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2577 val = 0x000fff00; 2578 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2579 val = 0x00ffff00; 2580 else 2581 return; 2582 2583 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2584 val |= 0xff; 2585 2586 RTL_W32(tp, 0x7c, val); 2587 } 2588 2589 static void rtl_set_rx_mode(struct net_device *dev) 2590 { 2591 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2592 /* Multicast hash filter */ 2593 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2594 struct rtl8169_private *tp = netdev_priv(dev); 2595 u32 tmp; 2596 2597 if (dev->flags & IFF_PROMISC) { 2598 rx_mode |= AcceptAllPhys; 2599 } else if (!(dev->flags & IFF_MULTICAST)) { 2600 rx_mode &= ~AcceptMulticast; 2601 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2602 dev->flags & IFF_ALLMULTI || 2603 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2604 /* accept all multicasts */ 2605 } else if (netdev_mc_empty(dev)) { 2606 rx_mode &= ~AcceptMulticast; 2607 } else { 2608 struct netdev_hw_addr *ha; 2609 2610 mc_filter[1] = mc_filter[0] = 0; 2611 netdev_for_each_mc_addr(ha, dev) { 2612 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2613 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2614 } 2615 2616 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2617 tmp = mc_filter[0]; 2618 mc_filter[0] = swab32(mc_filter[1]); 2619 mc_filter[1] = swab32(tmp); 2620 } 2621 } 2622 2623 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2624 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2625 2626 tmp = RTL_R32(tp, RxConfig); 2627 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2628 } 2629 2630 DECLARE_RTL_COND(rtl_csiar_cond) 2631 { 2632 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2633 } 2634 2635 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2636 { 2637 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2638 2639 RTL_W32(tp, CSIDR, value); 2640 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2641 CSIAR_BYTE_ENABLE | func << 16); 2642 2643 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2644 } 2645 2646 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2647 { 2648 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2649 2650 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2651 CSIAR_BYTE_ENABLE); 2652 2653 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2654 RTL_R32(tp, CSIDR) : ~0; 2655 } 2656 2657 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2658 { 2659 struct pci_dev *pdev = tp->pci_dev; 2660 u32 csi; 2661 2662 /* According to Realtek the value at config space address 0x070f 2663 * controls the L0s/L1 entrance latency. We try standard ECAM access 2664 * first and if it fails fall back to CSI. 2665 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2666 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2667 */ 2668 if (pdev->cfg_size > 0x070f && 2669 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2670 return; 2671 2672 netdev_notice_once(tp->dev, 2673 "No native access to PCI extended config space, falling back to CSI\n"); 2674 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2675 rtl_csi_write(tp, 0x070c, csi | val << 24); 2676 } 2677 2678 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2679 { 2680 /* L0 7us, L1 16us */ 2681 rtl_set_aspm_entry_latency(tp, 0x27); 2682 } 2683 2684 struct ephy_info { 2685 unsigned int offset; 2686 u16 mask; 2687 u16 bits; 2688 }; 2689 2690 static void __rtl_ephy_init(struct rtl8169_private *tp, 2691 const struct ephy_info *e, int len) 2692 { 2693 u16 w; 2694 2695 while (len-- > 0) { 2696 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2697 rtl_ephy_write(tp, e->offset, w); 2698 e++; 2699 } 2700 } 2701 2702 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2703 2704 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2705 { 2706 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2707 PCI_EXP_LNKCTL_CLKREQ_EN); 2708 } 2709 2710 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2711 { 2712 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2713 PCI_EXP_LNKCTL_CLKREQ_EN); 2714 } 2715 2716 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2717 { 2718 /* work around an issue when PCI reset occurs during L2/L3 state */ 2719 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2720 } 2721 2722 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2723 { 2724 /* Bits control which events trigger ASPM L1 exit: 2725 * Bit 12: rxdv 2726 * Bit 11: ltr_msg 2727 * Bit 10: txdma_poll 2728 * Bit 9: xadm 2729 * Bit 8: pktavi 2730 * Bit 7: txpla 2731 */ 2732 switch (tp->mac_version) { 2733 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2734 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2735 break; 2736 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2737 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2738 break; 2739 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2740 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2741 break; 2742 default: 2743 break; 2744 } 2745 } 2746 2747 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2748 { 2749 switch (tp->mac_version) { 2750 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2751 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2752 break; 2753 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2754 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2755 break; 2756 default: 2757 break; 2758 } 2759 } 2760 2761 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2762 { 2763 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2764 return; 2765 2766 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2767 if (enable && tp->aspm_manageable) { 2768 /* On these chip versions ASPM can even harm 2769 * bus communication of other PCI devices. 2770 */ 2771 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2772 tp->mac_version == RTL_GIGA_MAC_VER_43) 2773 return; 2774 2775 rtl_mod_config5(tp, 0, ASPM_en); 2776 rtl_mod_config2(tp, 0, ClkReqEn); 2777 2778 switch (tp->mac_version) { 2779 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2780 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2781 /* reset ephy tx/rx disable timer */ 2782 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2783 /* chip can trigger L1.2 */ 2784 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2785 break; 2786 default: 2787 break; 2788 } 2789 } else { 2790 switch (tp->mac_version) { 2791 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2792 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2793 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2794 break; 2795 default: 2796 break; 2797 } 2798 2799 rtl_mod_config2(tp, ClkReqEn, 0); 2800 rtl_mod_config5(tp, ASPM_en, 0); 2801 } 2802 } 2803 2804 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2805 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2806 { 2807 /* Usage of dynamic vs. static FIFO is controlled by bit 2808 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2809 */ 2810 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2811 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2812 } 2813 2814 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2815 u8 low, u8 high) 2816 { 2817 /* FIFO thresholds for pause flow control */ 2818 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2819 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2820 } 2821 2822 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2823 { 2824 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2825 } 2826 2827 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2828 { 2829 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2830 2831 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2832 2833 rtl_disable_clock_request(tp); 2834 } 2835 2836 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2837 { 2838 static const struct ephy_info e_info_8168cp[] = { 2839 { 0x01, 0, 0x0001 }, 2840 { 0x02, 0x0800, 0x1000 }, 2841 { 0x03, 0, 0x0042 }, 2842 { 0x06, 0x0080, 0x0000 }, 2843 { 0x07, 0, 0x2000 } 2844 }; 2845 2846 rtl_set_def_aspm_entry_latency(tp); 2847 2848 rtl_ephy_init(tp, e_info_8168cp); 2849 2850 __rtl_hw_start_8168cp(tp); 2851 } 2852 2853 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2854 { 2855 rtl_set_def_aspm_entry_latency(tp); 2856 2857 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2858 } 2859 2860 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2861 { 2862 rtl_set_def_aspm_entry_latency(tp); 2863 2864 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2865 2866 /* Magic. */ 2867 RTL_W8(tp, DBG_REG, 0x20); 2868 } 2869 2870 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2871 { 2872 static const struct ephy_info e_info_8168c_1[] = { 2873 { 0x02, 0x0800, 0x1000 }, 2874 { 0x03, 0, 0x0002 }, 2875 { 0x06, 0x0080, 0x0000 } 2876 }; 2877 2878 rtl_set_def_aspm_entry_latency(tp); 2879 2880 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2881 2882 rtl_ephy_init(tp, e_info_8168c_1); 2883 2884 __rtl_hw_start_8168cp(tp); 2885 } 2886 2887 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2888 { 2889 static const struct ephy_info e_info_8168c_2[] = { 2890 { 0x01, 0, 0x0001 }, 2891 { 0x03, 0x0400, 0x0020 } 2892 }; 2893 2894 rtl_set_def_aspm_entry_latency(tp); 2895 2896 rtl_ephy_init(tp, e_info_8168c_2); 2897 2898 __rtl_hw_start_8168cp(tp); 2899 } 2900 2901 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2902 { 2903 rtl_set_def_aspm_entry_latency(tp); 2904 2905 __rtl_hw_start_8168cp(tp); 2906 } 2907 2908 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2909 { 2910 rtl_set_def_aspm_entry_latency(tp); 2911 2912 rtl_disable_clock_request(tp); 2913 } 2914 2915 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2916 { 2917 static const struct ephy_info e_info_8168d_4[] = { 2918 { 0x0b, 0x0000, 0x0048 }, 2919 { 0x19, 0x0020, 0x0050 }, 2920 { 0x0c, 0x0100, 0x0020 }, 2921 { 0x10, 0x0004, 0x0000 }, 2922 }; 2923 2924 rtl_set_def_aspm_entry_latency(tp); 2925 2926 rtl_ephy_init(tp, e_info_8168d_4); 2927 2928 rtl_enable_clock_request(tp); 2929 } 2930 2931 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2932 { 2933 static const struct ephy_info e_info_8168e_1[] = { 2934 { 0x00, 0x0200, 0x0100 }, 2935 { 0x00, 0x0000, 0x0004 }, 2936 { 0x06, 0x0002, 0x0001 }, 2937 { 0x06, 0x0000, 0x0030 }, 2938 { 0x07, 0x0000, 0x2000 }, 2939 { 0x00, 0x0000, 0x0020 }, 2940 { 0x03, 0x5800, 0x2000 }, 2941 { 0x03, 0x0000, 0x0001 }, 2942 { 0x01, 0x0800, 0x1000 }, 2943 { 0x07, 0x0000, 0x4000 }, 2944 { 0x1e, 0x0000, 0x2000 }, 2945 { 0x19, 0xffff, 0xfe6c }, 2946 { 0x0a, 0x0000, 0x0040 } 2947 }; 2948 2949 rtl_set_def_aspm_entry_latency(tp); 2950 2951 rtl_ephy_init(tp, e_info_8168e_1); 2952 2953 rtl_disable_clock_request(tp); 2954 2955 /* Reset tx FIFO pointer */ 2956 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2957 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2958 2959 rtl_mod_config5(tp, Spi_en, 0); 2960 } 2961 2962 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2963 { 2964 static const struct ephy_info e_info_8168e_2[] = { 2965 { 0x09, 0x0000, 0x0080 }, 2966 { 0x19, 0x0000, 0x0224 }, 2967 { 0x00, 0x0000, 0x0004 }, 2968 { 0x0c, 0x3df0, 0x0200 }, 2969 }; 2970 2971 rtl_set_def_aspm_entry_latency(tp); 2972 2973 rtl_ephy_init(tp, e_info_8168e_2); 2974 2975 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2976 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2977 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2978 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2979 rtl_reset_packet_filter(tp); 2980 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2981 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2982 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2983 2984 rtl_disable_clock_request(tp); 2985 2986 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2987 2988 rtl8168_config_eee_mac(tp); 2989 2990 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2991 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2992 rtl_mod_config5(tp, Spi_en, 0); 2993 } 2994 2995 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2996 { 2997 rtl_set_def_aspm_entry_latency(tp); 2998 2999 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3000 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3001 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3002 rtl_reset_packet_filter(tp); 3003 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3004 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3005 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3006 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3007 3008 rtl_disable_clock_request(tp); 3009 3010 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3011 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3012 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3013 rtl_mod_config5(tp, Spi_en, 0); 3014 3015 rtl8168_config_eee_mac(tp); 3016 } 3017 3018 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3019 { 3020 static const struct ephy_info e_info_8168f_1[] = { 3021 { 0x06, 0x00c0, 0x0020 }, 3022 { 0x08, 0x0001, 0x0002 }, 3023 { 0x09, 0x0000, 0x0080 }, 3024 { 0x19, 0x0000, 0x0224 }, 3025 { 0x00, 0x0000, 0x0008 }, 3026 { 0x0c, 0x3df0, 0x0200 }, 3027 }; 3028 3029 rtl_hw_start_8168f(tp); 3030 3031 rtl_ephy_init(tp, e_info_8168f_1); 3032 } 3033 3034 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3035 { 3036 static const struct ephy_info e_info_8168f_1[] = { 3037 { 0x06, 0x00c0, 0x0020 }, 3038 { 0x0f, 0xffff, 0x5200 }, 3039 { 0x19, 0x0000, 0x0224 }, 3040 { 0x00, 0x0000, 0x0008 }, 3041 { 0x0c, 0x3df0, 0x0200 }, 3042 }; 3043 3044 rtl_hw_start_8168f(tp); 3045 rtl_pcie_state_l2l3_disable(tp); 3046 3047 rtl_ephy_init(tp, e_info_8168f_1); 3048 } 3049 3050 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3051 { 3052 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3053 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3054 3055 rtl_set_def_aspm_entry_latency(tp); 3056 3057 rtl_reset_packet_filter(tp); 3058 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3059 3060 rtl_disable_rxdvgate(tp); 3061 3062 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3063 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3064 3065 rtl8168_config_eee_mac(tp); 3066 3067 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3068 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3069 3070 rtl_pcie_state_l2l3_disable(tp); 3071 } 3072 3073 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3074 { 3075 static const struct ephy_info e_info_8168g_1[] = { 3076 { 0x00, 0x0008, 0x0000 }, 3077 { 0x0c, 0x3ff0, 0x0820 }, 3078 { 0x1e, 0x0000, 0x0001 }, 3079 { 0x19, 0x8000, 0x0000 } 3080 }; 3081 3082 rtl_hw_start_8168g(tp); 3083 rtl_ephy_init(tp, e_info_8168g_1); 3084 } 3085 3086 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3087 { 3088 static const struct ephy_info e_info_8168g_2[] = { 3089 { 0x00, 0x0008, 0x0000 }, 3090 { 0x0c, 0x3ff0, 0x0820 }, 3091 { 0x19, 0xffff, 0x7c00 }, 3092 { 0x1e, 0xffff, 0x20eb }, 3093 { 0x0d, 0xffff, 0x1666 }, 3094 { 0x00, 0xffff, 0x10a3 }, 3095 { 0x06, 0xffff, 0xf050 }, 3096 { 0x04, 0x0000, 0x0010 }, 3097 { 0x1d, 0x4000, 0x0000 }, 3098 }; 3099 3100 rtl_hw_start_8168g(tp); 3101 rtl_ephy_init(tp, e_info_8168g_2); 3102 } 3103 3104 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3105 { 3106 static const struct ephy_info e_info_8411_2[] = { 3107 { 0x00, 0x0008, 0x0000 }, 3108 { 0x0c, 0x37d0, 0x0820 }, 3109 { 0x1e, 0x0000, 0x0001 }, 3110 { 0x19, 0x8021, 0x0000 }, 3111 { 0x1e, 0x0000, 0x2000 }, 3112 { 0x0d, 0x0100, 0x0200 }, 3113 { 0x00, 0x0000, 0x0080 }, 3114 { 0x06, 0x0000, 0x0010 }, 3115 { 0x04, 0x0000, 0x0010 }, 3116 { 0x1d, 0x0000, 0x4000 }, 3117 }; 3118 3119 rtl_hw_start_8168g(tp); 3120 3121 rtl_ephy_init(tp, e_info_8411_2); 3122 3123 /* The following Realtek-provided magic fixes an issue with the RX unit 3124 * getting confused after the PHY having been powered-down. 3125 */ 3126 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3127 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3128 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3129 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3130 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3131 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3132 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3133 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3134 mdelay(3); 3135 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3136 3137 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3138 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3139 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3140 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3141 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3142 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3143 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3144 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3145 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3146 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3147 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3148 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3149 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3150 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3151 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3152 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3153 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3154 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3155 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3156 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3157 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3158 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3159 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3160 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3161 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3162 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3163 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3164 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3165 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3166 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3167 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3168 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3169 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3170 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3171 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3172 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3173 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3174 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3175 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3176 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3177 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3178 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3179 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3180 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3181 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3182 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3183 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3184 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3185 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3186 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3187 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3188 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3189 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3190 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3191 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3192 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3193 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3194 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3195 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3196 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3197 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3198 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3199 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3200 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3201 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3202 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3203 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3204 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3205 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3206 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3207 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3208 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3209 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3210 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3211 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3212 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3213 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3214 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3215 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3216 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3217 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3218 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3219 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3220 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3221 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3222 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3223 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3224 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3225 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3226 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3227 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3228 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3229 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3230 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3231 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3232 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3233 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3234 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3235 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3236 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3237 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3238 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3239 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3240 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3241 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3242 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3243 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3244 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3245 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3246 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3247 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3248 3249 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3250 3251 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3252 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3253 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3254 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3255 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3256 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3257 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3258 } 3259 3260 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3261 { 3262 static const struct ephy_info e_info_8168h_1[] = { 3263 { 0x1e, 0x0800, 0x0001 }, 3264 { 0x1d, 0x0000, 0x0800 }, 3265 { 0x05, 0xffff, 0x2089 }, 3266 { 0x06, 0xffff, 0x5881 }, 3267 { 0x04, 0xffff, 0x854a }, 3268 { 0x01, 0xffff, 0x068b } 3269 }; 3270 int rg_saw_cnt; 3271 3272 rtl_ephy_init(tp, e_info_8168h_1); 3273 3274 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3275 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3276 3277 rtl_set_def_aspm_entry_latency(tp); 3278 3279 rtl_reset_packet_filter(tp); 3280 3281 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3282 3283 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3284 3285 rtl_disable_rxdvgate(tp); 3286 3287 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3288 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3289 3290 rtl8168_config_eee_mac(tp); 3291 3292 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3293 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3294 3295 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3296 3297 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3298 3299 rtl_pcie_state_l2l3_disable(tp); 3300 3301 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3302 if (rg_saw_cnt > 0) { 3303 u16 sw_cnt_1ms_ini; 3304 3305 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3306 sw_cnt_1ms_ini &= 0x0fff; 3307 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3308 } 3309 3310 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3311 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3312 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3313 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3314 3315 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3316 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3317 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3318 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3319 } 3320 3321 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3322 { 3323 rtl8168ep_stop_cmac(tp); 3324 3325 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3326 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3327 3328 rtl_set_def_aspm_entry_latency(tp); 3329 3330 rtl_reset_packet_filter(tp); 3331 3332 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3333 3334 rtl_disable_rxdvgate(tp); 3335 3336 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3337 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3338 3339 rtl8168_config_eee_mac(tp); 3340 3341 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3342 3343 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3344 3345 rtl_pcie_state_l2l3_disable(tp); 3346 } 3347 3348 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3349 { 3350 static const struct ephy_info e_info_8168ep_3[] = { 3351 { 0x00, 0x0000, 0x0080 }, 3352 { 0x0d, 0x0100, 0x0200 }, 3353 { 0x19, 0x8021, 0x0000 }, 3354 { 0x1e, 0x0000, 0x2000 }, 3355 }; 3356 3357 rtl_ephy_init(tp, e_info_8168ep_3); 3358 3359 rtl_hw_start_8168ep(tp); 3360 3361 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3362 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3363 3364 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3365 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3366 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3367 } 3368 3369 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3370 { 3371 static const struct ephy_info e_info_8117[] = { 3372 { 0x19, 0x0040, 0x1100 }, 3373 { 0x59, 0x0040, 0x1100 }, 3374 }; 3375 int rg_saw_cnt; 3376 3377 rtl8168ep_stop_cmac(tp); 3378 rtl_ephy_init(tp, e_info_8117); 3379 3380 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3381 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3382 3383 rtl_set_def_aspm_entry_latency(tp); 3384 3385 rtl_reset_packet_filter(tp); 3386 3387 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3388 3389 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3390 3391 rtl_disable_rxdvgate(tp); 3392 3393 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3394 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3395 3396 rtl8168_config_eee_mac(tp); 3397 3398 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3399 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3400 3401 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3402 3403 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3404 3405 rtl_pcie_state_l2l3_disable(tp); 3406 3407 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3408 if (rg_saw_cnt > 0) { 3409 u16 sw_cnt_1ms_ini; 3410 3411 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3412 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3413 } 3414 3415 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3416 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3417 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3418 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3419 3420 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3421 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3422 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3423 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3424 3425 /* firmware is for MAC only */ 3426 r8169_apply_firmware(tp); 3427 } 3428 3429 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3430 { 3431 static const struct ephy_info e_info_8102e_1[] = { 3432 { 0x01, 0, 0x6e65 }, 3433 { 0x02, 0, 0x091f }, 3434 { 0x03, 0, 0xc2f9 }, 3435 { 0x06, 0, 0xafb5 }, 3436 { 0x07, 0, 0x0e00 }, 3437 { 0x19, 0, 0xec80 }, 3438 { 0x01, 0, 0x2e65 }, 3439 { 0x01, 0, 0x6e65 } 3440 }; 3441 u8 cfg1; 3442 3443 rtl_set_def_aspm_entry_latency(tp); 3444 3445 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3446 3447 RTL_W8(tp, Config1, 3448 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3449 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3450 3451 cfg1 = RTL_R8(tp, Config1); 3452 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3453 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3454 3455 rtl_ephy_init(tp, e_info_8102e_1); 3456 } 3457 3458 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3459 { 3460 rtl_set_def_aspm_entry_latency(tp); 3461 3462 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3463 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3464 } 3465 3466 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3467 { 3468 rtl_hw_start_8102e_2(tp); 3469 3470 rtl_ephy_write(tp, 0x03, 0xc2f9); 3471 } 3472 3473 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3474 { 3475 static const struct ephy_info e_info_8401[] = { 3476 { 0x01, 0xffff, 0x6fe5 }, 3477 { 0x03, 0xffff, 0x0599 }, 3478 { 0x06, 0xffff, 0xaf25 }, 3479 { 0x07, 0xffff, 0x8e68 }, 3480 }; 3481 3482 rtl_ephy_init(tp, e_info_8401); 3483 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3484 } 3485 3486 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3487 { 3488 static const struct ephy_info e_info_8105e_1[] = { 3489 { 0x07, 0, 0x4000 }, 3490 { 0x19, 0, 0x0200 }, 3491 { 0x19, 0, 0x0020 }, 3492 { 0x1e, 0, 0x2000 }, 3493 { 0x03, 0, 0x0001 }, 3494 { 0x19, 0, 0x0100 }, 3495 { 0x19, 0, 0x0004 }, 3496 { 0x0a, 0, 0x0020 } 3497 }; 3498 3499 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3500 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3501 3502 /* Disable Early Tally Counter */ 3503 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3504 3505 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3506 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3507 3508 rtl_ephy_init(tp, e_info_8105e_1); 3509 3510 rtl_pcie_state_l2l3_disable(tp); 3511 } 3512 3513 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3514 { 3515 rtl_hw_start_8105e_1(tp); 3516 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3517 } 3518 3519 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3520 { 3521 static const struct ephy_info e_info_8402[] = { 3522 { 0x19, 0xffff, 0xff64 }, 3523 { 0x1e, 0, 0x4000 } 3524 }; 3525 3526 rtl_set_def_aspm_entry_latency(tp); 3527 3528 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3529 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3530 3531 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3532 3533 rtl_ephy_init(tp, e_info_8402); 3534 3535 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3536 rtl_reset_packet_filter(tp); 3537 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3538 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3539 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3540 3541 /* disable EEE */ 3542 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3543 3544 rtl_pcie_state_l2l3_disable(tp); 3545 } 3546 3547 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3548 { 3549 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3550 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3551 3552 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3553 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3554 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3555 3556 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3557 rtl_set_aspm_entry_latency(tp, 0x2f); 3558 3559 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3560 3561 /* disable EEE */ 3562 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3563 3564 rtl_pcie_state_l2l3_disable(tp); 3565 } 3566 3567 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3568 { 3569 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3570 } 3571 3572 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3573 { 3574 rtl_pcie_state_l2l3_disable(tp); 3575 3576 RTL_W16(tp, 0x382, 0x221b); 3577 RTL_W8(tp, 0x4500, 0); 3578 RTL_W16(tp, 0x4800, 0); 3579 3580 /* disable UPS */ 3581 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3582 3583 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3584 3585 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3586 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3587 3588 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3589 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3590 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3591 3592 /* disable new tx descriptor format */ 3593 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3594 3595 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3596 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3597 else 3598 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3599 3600 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3601 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3602 else 3603 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3604 3605 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3606 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3607 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3608 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3609 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3610 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3611 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3612 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3613 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3614 3615 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3616 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3617 udelay(1); 3618 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3619 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3620 3621 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3622 3623 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3624 3625 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3626 rtl8125b_config_eee_mac(tp); 3627 else 3628 rtl8125a_config_eee_mac(tp); 3629 3630 rtl_disable_rxdvgate(tp); 3631 } 3632 3633 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3634 { 3635 static const struct ephy_info e_info_8125a_2[] = { 3636 { 0x04, 0xffff, 0xd000 }, 3637 { 0x0a, 0xffff, 0x8653 }, 3638 { 0x23, 0xffff, 0xab66 }, 3639 { 0x20, 0xffff, 0x9455 }, 3640 { 0x21, 0xffff, 0x99ff }, 3641 { 0x29, 0xffff, 0xfe04 }, 3642 3643 { 0x44, 0xffff, 0xd000 }, 3644 { 0x4a, 0xffff, 0x8653 }, 3645 { 0x63, 0xffff, 0xab66 }, 3646 { 0x60, 0xffff, 0x9455 }, 3647 { 0x61, 0xffff, 0x99ff }, 3648 { 0x69, 0xffff, 0xfe04 }, 3649 }; 3650 3651 rtl_set_def_aspm_entry_latency(tp); 3652 rtl_ephy_init(tp, e_info_8125a_2); 3653 rtl_hw_start_8125_common(tp); 3654 } 3655 3656 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3657 { 3658 static const struct ephy_info e_info_8125b[] = { 3659 { 0x0b, 0xffff, 0xa908 }, 3660 { 0x1e, 0xffff, 0x20eb }, 3661 { 0x4b, 0xffff, 0xa908 }, 3662 { 0x5e, 0xffff, 0x20eb }, 3663 { 0x22, 0x0030, 0x0020 }, 3664 { 0x62, 0x0030, 0x0020 }, 3665 }; 3666 3667 rtl_set_def_aspm_entry_latency(tp); 3668 rtl_ephy_init(tp, e_info_8125b); 3669 rtl_hw_start_8125_common(tp); 3670 } 3671 3672 static void rtl_hw_config(struct rtl8169_private *tp) 3673 { 3674 static const rtl_generic_fct hw_configs[] = { 3675 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3676 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3677 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3678 [RTL_GIGA_MAC_VER_10] = NULL, 3679 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3680 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3681 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3682 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3683 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3684 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3685 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3686 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3687 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3688 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3689 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3690 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3691 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3692 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3693 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3694 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3695 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3696 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3697 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3698 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3699 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3700 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3701 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3702 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3703 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3704 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3705 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3706 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3707 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3708 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3709 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3710 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3711 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3712 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3713 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3714 }; 3715 3716 if (hw_configs[tp->mac_version]) 3717 hw_configs[tp->mac_version](tp); 3718 } 3719 3720 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3721 { 3722 int i; 3723 3724 /* disable interrupt coalescing */ 3725 for (i = 0xa00; i < 0xb00; i += 4) 3726 RTL_W32(tp, i, 0); 3727 3728 rtl_hw_config(tp); 3729 } 3730 3731 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3732 { 3733 if (rtl_is_8168evl_up(tp)) 3734 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3735 else 3736 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3737 3738 rtl_hw_config(tp); 3739 3740 /* disable interrupt coalescing */ 3741 RTL_W16(tp, IntrMitigate, 0x0000); 3742 } 3743 3744 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3745 { 3746 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3747 3748 tp->cp_cmd |= PCIMulRW; 3749 3750 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3751 tp->mac_version == RTL_GIGA_MAC_VER_03) 3752 tp->cp_cmd |= EnAnaPLL; 3753 3754 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3755 3756 rtl8169_set_magic_reg(tp); 3757 3758 /* disable interrupt coalescing */ 3759 RTL_W16(tp, IntrMitigate, 0x0000); 3760 } 3761 3762 static void rtl_hw_start(struct rtl8169_private *tp) 3763 { 3764 rtl_unlock_config_regs(tp); 3765 /* disable aspm and clock request before ephy access */ 3766 rtl_hw_aspm_clkreq_enable(tp, false); 3767 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3768 3769 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3770 rtl_hw_start_8169(tp); 3771 else if (rtl_is_8125(tp)) 3772 rtl_hw_start_8125(tp); 3773 else 3774 rtl_hw_start_8168(tp); 3775 3776 rtl_enable_exit_l1(tp); 3777 rtl_hw_aspm_clkreq_enable(tp, true); 3778 rtl_set_rx_max_size(tp); 3779 rtl_set_rx_tx_desc_registers(tp); 3780 rtl_lock_config_regs(tp); 3781 3782 rtl_jumbo_config(tp); 3783 3784 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3785 rtl_pci_commit(tp); 3786 3787 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3788 rtl_init_rxcfg(tp); 3789 rtl_set_tx_config_registers(tp); 3790 rtl_set_rx_config_features(tp, tp->dev->features); 3791 rtl_set_rx_mode(tp->dev); 3792 rtl_irq_enable(tp); 3793 } 3794 3795 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3796 { 3797 struct rtl8169_private *tp = netdev_priv(dev); 3798 3799 dev->mtu = new_mtu; 3800 netdev_update_features(dev); 3801 rtl_jumbo_config(tp); 3802 3803 switch (tp->mac_version) { 3804 case RTL_GIGA_MAC_VER_61: 3805 case RTL_GIGA_MAC_VER_63: 3806 rtl8125_set_eee_txidle_timer(tp); 3807 break; 3808 default: 3809 break; 3810 } 3811 3812 return 0; 3813 } 3814 3815 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3816 { 3817 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3818 3819 desc->opts2 = 0; 3820 /* Force memory writes to complete before releasing descriptor */ 3821 dma_wmb(); 3822 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3823 } 3824 3825 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3826 struct RxDesc *desc) 3827 { 3828 struct device *d = tp_to_dev(tp); 3829 int node = dev_to_node(d); 3830 dma_addr_t mapping; 3831 struct page *data; 3832 3833 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3834 if (!data) 3835 return NULL; 3836 3837 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3838 if (unlikely(dma_mapping_error(d, mapping))) { 3839 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3840 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3841 return NULL; 3842 } 3843 3844 desc->addr = cpu_to_le64(mapping); 3845 rtl8169_mark_to_asic(desc); 3846 3847 return data; 3848 } 3849 3850 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3851 { 3852 int i; 3853 3854 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3855 dma_unmap_page(tp_to_dev(tp), 3856 le64_to_cpu(tp->RxDescArray[i].addr), 3857 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3858 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3859 tp->Rx_databuff[i] = NULL; 3860 tp->RxDescArray[i].addr = 0; 3861 tp->RxDescArray[i].opts1 = 0; 3862 } 3863 } 3864 3865 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3866 { 3867 int i; 3868 3869 for (i = 0; i < NUM_RX_DESC; i++) { 3870 struct page *data; 3871 3872 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3873 if (!data) { 3874 rtl8169_rx_clear(tp); 3875 return -ENOMEM; 3876 } 3877 tp->Rx_databuff[i] = data; 3878 } 3879 3880 /* mark as last descriptor in the ring */ 3881 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3882 3883 return 0; 3884 } 3885 3886 static int rtl8169_init_ring(struct rtl8169_private *tp) 3887 { 3888 rtl8169_init_ring_indexes(tp); 3889 3890 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3891 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3892 3893 return rtl8169_rx_fill(tp); 3894 } 3895 3896 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3897 { 3898 struct ring_info *tx_skb = tp->tx_skb + entry; 3899 struct TxDesc *desc = tp->TxDescArray + entry; 3900 3901 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3902 DMA_TO_DEVICE); 3903 memset(desc, 0, sizeof(*desc)); 3904 memset(tx_skb, 0, sizeof(*tx_skb)); 3905 } 3906 3907 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3908 unsigned int n) 3909 { 3910 unsigned int i; 3911 3912 for (i = 0; i < n; i++) { 3913 unsigned int entry = (start + i) % NUM_TX_DESC; 3914 struct ring_info *tx_skb = tp->tx_skb + entry; 3915 unsigned int len = tx_skb->len; 3916 3917 if (len) { 3918 struct sk_buff *skb = tx_skb->skb; 3919 3920 rtl8169_unmap_tx_skb(tp, entry); 3921 if (skb) 3922 dev_consume_skb_any(skb); 3923 } 3924 } 3925 } 3926 3927 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3928 { 3929 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3930 netdev_reset_queue(tp->dev); 3931 } 3932 3933 static void rtl8169_cleanup(struct rtl8169_private *tp) 3934 { 3935 napi_disable(&tp->napi); 3936 3937 /* Give a racing hard_start_xmit a few cycles to complete. */ 3938 synchronize_net(); 3939 3940 /* Disable interrupts */ 3941 rtl8169_irq_mask_and_ack(tp); 3942 3943 rtl_rx_close(tp); 3944 3945 switch (tp->mac_version) { 3946 case RTL_GIGA_MAC_VER_28: 3947 case RTL_GIGA_MAC_VER_31: 3948 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3949 break; 3950 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3951 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3952 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3953 break; 3954 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3955 rtl_enable_rxdvgate(tp); 3956 fsleep(2000); 3957 break; 3958 default: 3959 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3960 fsleep(100); 3961 break; 3962 } 3963 3964 rtl_hw_reset(tp); 3965 3966 rtl8169_tx_clear(tp); 3967 rtl8169_init_ring_indexes(tp); 3968 } 3969 3970 static void rtl_reset_work(struct rtl8169_private *tp) 3971 { 3972 int i; 3973 3974 netif_stop_queue(tp->dev); 3975 3976 rtl8169_cleanup(tp); 3977 3978 for (i = 0; i < NUM_RX_DESC; i++) 3979 rtl8169_mark_to_asic(tp->RxDescArray + i); 3980 3981 napi_enable(&tp->napi); 3982 rtl_hw_start(tp); 3983 } 3984 3985 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3986 { 3987 struct rtl8169_private *tp = netdev_priv(dev); 3988 3989 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 3990 } 3991 3992 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3993 void *addr, unsigned int entry, bool desc_own) 3994 { 3995 struct TxDesc *txd = tp->TxDescArray + entry; 3996 struct device *d = tp_to_dev(tp); 3997 dma_addr_t mapping; 3998 u32 opts1; 3999 int ret; 4000 4001 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4002 ret = dma_mapping_error(d, mapping); 4003 if (unlikely(ret)) { 4004 if (net_ratelimit()) 4005 netdev_err(tp->dev, "Failed to map TX data!\n"); 4006 return ret; 4007 } 4008 4009 txd->addr = cpu_to_le64(mapping); 4010 txd->opts2 = cpu_to_le32(opts[1]); 4011 4012 opts1 = opts[0] | len; 4013 if (entry == NUM_TX_DESC - 1) 4014 opts1 |= RingEnd; 4015 if (desc_own) 4016 opts1 |= DescOwn; 4017 txd->opts1 = cpu_to_le32(opts1); 4018 4019 tp->tx_skb[entry].len = len; 4020 4021 return 0; 4022 } 4023 4024 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4025 const u32 *opts, unsigned int entry) 4026 { 4027 struct skb_shared_info *info = skb_shinfo(skb); 4028 unsigned int cur_frag; 4029 4030 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4031 const skb_frag_t *frag = info->frags + cur_frag; 4032 void *addr = skb_frag_address(frag); 4033 u32 len = skb_frag_size(frag); 4034 4035 entry = (entry + 1) % NUM_TX_DESC; 4036 4037 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4038 goto err_out; 4039 } 4040 4041 return 0; 4042 4043 err_out: 4044 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4045 return -EIO; 4046 } 4047 4048 static bool rtl_skb_is_udp(struct sk_buff *skb) 4049 { 4050 int no = skb_network_offset(skb); 4051 struct ipv6hdr *i6h, _i6h; 4052 struct iphdr *ih, _ih; 4053 4054 switch (vlan_get_protocol(skb)) { 4055 case htons(ETH_P_IP): 4056 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4057 return ih && ih->protocol == IPPROTO_UDP; 4058 case htons(ETH_P_IPV6): 4059 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4060 return i6h && i6h->nexthdr == IPPROTO_UDP; 4061 default: 4062 return false; 4063 } 4064 } 4065 4066 #define RTL_MIN_PATCH_LEN 47 4067 4068 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4069 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4070 struct sk_buff *skb) 4071 { 4072 unsigned int padto = 0, len = skb->len; 4073 4074 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4075 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4076 unsigned int trans_data_len = skb_tail_pointer(skb) - 4077 skb_transport_header(skb); 4078 4079 if (trans_data_len >= offsetof(struct udphdr, len) && 4080 trans_data_len < RTL_MIN_PATCH_LEN) { 4081 u16 dest = ntohs(udp_hdr(skb)->dest); 4082 4083 /* dest is a standard PTP port */ 4084 if (dest == 319 || dest == 320) 4085 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4086 } 4087 4088 if (trans_data_len < sizeof(struct udphdr)) 4089 padto = max_t(unsigned int, padto, 4090 len + sizeof(struct udphdr) - trans_data_len); 4091 } 4092 4093 return padto; 4094 } 4095 4096 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4097 struct sk_buff *skb) 4098 { 4099 unsigned int padto; 4100 4101 padto = rtl8125_quirk_udp_padto(tp, skb); 4102 4103 switch (tp->mac_version) { 4104 case RTL_GIGA_MAC_VER_34: 4105 case RTL_GIGA_MAC_VER_61: 4106 case RTL_GIGA_MAC_VER_63: 4107 padto = max_t(unsigned int, padto, ETH_ZLEN); 4108 break; 4109 default: 4110 break; 4111 } 4112 4113 return padto; 4114 } 4115 4116 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4117 { 4118 u32 mss = skb_shinfo(skb)->gso_size; 4119 4120 if (mss) { 4121 opts[0] |= TD_LSO; 4122 opts[0] |= mss << TD0_MSS_SHIFT; 4123 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4124 const struct iphdr *ip = ip_hdr(skb); 4125 4126 if (ip->protocol == IPPROTO_TCP) 4127 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4128 else if (ip->protocol == IPPROTO_UDP) 4129 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4130 else 4131 WARN_ON_ONCE(1); 4132 } 4133 } 4134 4135 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4136 struct sk_buff *skb, u32 *opts) 4137 { 4138 struct skb_shared_info *shinfo = skb_shinfo(skb); 4139 u32 mss = shinfo->gso_size; 4140 4141 if (mss) { 4142 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4143 opts[0] |= TD1_GTSENV4; 4144 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4145 if (skb_cow_head(skb, 0)) 4146 return false; 4147 4148 tcp_v6_gso_csum_prep(skb); 4149 opts[0] |= TD1_GTSENV6; 4150 } else { 4151 WARN_ON_ONCE(1); 4152 } 4153 4154 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4155 opts[1] |= mss << TD1_MSS_SHIFT; 4156 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4157 u8 ip_protocol; 4158 4159 switch (vlan_get_protocol(skb)) { 4160 case htons(ETH_P_IP): 4161 opts[1] |= TD1_IPv4_CS; 4162 ip_protocol = ip_hdr(skb)->protocol; 4163 break; 4164 4165 case htons(ETH_P_IPV6): 4166 opts[1] |= TD1_IPv6_CS; 4167 ip_protocol = ipv6_hdr(skb)->nexthdr; 4168 break; 4169 4170 default: 4171 ip_protocol = IPPROTO_RAW; 4172 break; 4173 } 4174 4175 if (ip_protocol == IPPROTO_TCP) 4176 opts[1] |= TD1_TCP_CS; 4177 else if (ip_protocol == IPPROTO_UDP) 4178 opts[1] |= TD1_UDP_CS; 4179 else 4180 WARN_ON_ONCE(1); 4181 4182 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4183 } else { 4184 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4185 4186 /* skb_padto would free the skb on error */ 4187 return !__skb_put_padto(skb, padto, false); 4188 } 4189 4190 return true; 4191 } 4192 4193 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4194 { 4195 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4196 } 4197 4198 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4199 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4200 { 4201 switch (tp->mac_version) { 4202 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4203 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4204 return false; 4205 default: 4206 return true; 4207 } 4208 } 4209 4210 static void rtl8169_doorbell(struct rtl8169_private *tp) 4211 { 4212 if (rtl_is_8125(tp)) 4213 RTL_W16(tp, TxPoll_8125, BIT(0)); 4214 else 4215 RTL_W8(tp, TxPoll, NPQ); 4216 } 4217 4218 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4219 struct net_device *dev) 4220 { 4221 unsigned int frags = skb_shinfo(skb)->nr_frags; 4222 struct rtl8169_private *tp = netdev_priv(dev); 4223 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4224 struct TxDesc *txd_first, *txd_last; 4225 bool stop_queue, door_bell; 4226 u32 opts[2]; 4227 4228 if (unlikely(!rtl_tx_slots_avail(tp))) { 4229 if (net_ratelimit()) 4230 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4231 goto err_stop_0; 4232 } 4233 4234 opts[1] = rtl8169_tx_vlan_tag(skb); 4235 opts[0] = 0; 4236 4237 if (!rtl_chip_supports_csum_v2(tp)) 4238 rtl8169_tso_csum_v1(skb, opts); 4239 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4240 goto err_dma_0; 4241 4242 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4243 entry, false))) 4244 goto err_dma_0; 4245 4246 txd_first = tp->TxDescArray + entry; 4247 4248 if (frags) { 4249 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4250 goto err_dma_1; 4251 entry = (entry + frags) % NUM_TX_DESC; 4252 } 4253 4254 txd_last = tp->TxDescArray + entry; 4255 txd_last->opts1 |= cpu_to_le32(LastFrag); 4256 tp->tx_skb[entry].skb = skb; 4257 4258 skb_tx_timestamp(skb); 4259 4260 /* Force memory writes to complete before releasing descriptor */ 4261 dma_wmb(); 4262 4263 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4264 4265 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4266 4267 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4268 smp_wmb(); 4269 4270 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4271 4272 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4273 R8169_TX_STOP_THRS, 4274 R8169_TX_START_THRS); 4275 if (door_bell || stop_queue) 4276 rtl8169_doorbell(tp); 4277 4278 return NETDEV_TX_OK; 4279 4280 err_dma_1: 4281 rtl8169_unmap_tx_skb(tp, entry); 4282 err_dma_0: 4283 dev_kfree_skb_any(skb); 4284 dev->stats.tx_dropped++; 4285 return NETDEV_TX_OK; 4286 4287 err_stop_0: 4288 netif_stop_queue(dev); 4289 dev->stats.tx_dropped++; 4290 return NETDEV_TX_BUSY; 4291 } 4292 4293 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4294 { 4295 struct skb_shared_info *info = skb_shinfo(skb); 4296 unsigned int nr_frags = info->nr_frags; 4297 4298 if (!nr_frags) 4299 return UINT_MAX; 4300 4301 return skb_frag_size(info->frags + nr_frags - 1); 4302 } 4303 4304 /* Workaround for hw issues with TSO on RTL8168evl */ 4305 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4306 netdev_features_t features) 4307 { 4308 /* IPv4 header has options field */ 4309 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4310 ip_hdrlen(skb) > sizeof(struct iphdr)) 4311 features &= ~NETIF_F_ALL_TSO; 4312 4313 /* IPv4 TCP header has options field */ 4314 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4315 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4316 features &= ~NETIF_F_ALL_TSO; 4317 4318 else if (rtl_last_frag_len(skb) <= 6) 4319 features &= ~NETIF_F_ALL_TSO; 4320 4321 return features; 4322 } 4323 4324 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4325 struct net_device *dev, 4326 netdev_features_t features) 4327 { 4328 struct rtl8169_private *tp = netdev_priv(dev); 4329 4330 if (skb_is_gso(skb)) { 4331 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4332 features = rtl8168evl_fix_tso(skb, features); 4333 4334 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4335 rtl_chip_supports_csum_v2(tp)) 4336 features &= ~NETIF_F_ALL_TSO; 4337 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4338 /* work around hw bug on some chip versions */ 4339 if (skb->len < ETH_ZLEN) 4340 features &= ~NETIF_F_CSUM_MASK; 4341 4342 if (rtl_quirk_packet_padto(tp, skb)) 4343 features &= ~NETIF_F_CSUM_MASK; 4344 4345 if (skb_transport_offset(skb) > TCPHO_MAX && 4346 rtl_chip_supports_csum_v2(tp)) 4347 features &= ~NETIF_F_CSUM_MASK; 4348 } 4349 4350 return vlan_features_check(skb, features); 4351 } 4352 4353 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4354 { 4355 struct rtl8169_private *tp = netdev_priv(dev); 4356 struct pci_dev *pdev = tp->pci_dev; 4357 int pci_status_errs; 4358 u16 pci_cmd; 4359 4360 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4361 4362 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4363 4364 if (net_ratelimit()) 4365 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4366 pci_cmd, pci_status_errs); 4367 4368 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4369 } 4370 4371 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4372 int budget) 4373 { 4374 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4375 struct sk_buff *skb; 4376 4377 dirty_tx = tp->dirty_tx; 4378 4379 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4380 unsigned int entry = dirty_tx % NUM_TX_DESC; 4381 u32 status; 4382 4383 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4384 if (status & DescOwn) 4385 break; 4386 4387 skb = tp->tx_skb[entry].skb; 4388 rtl8169_unmap_tx_skb(tp, entry); 4389 4390 if (skb) { 4391 pkts_compl++; 4392 bytes_compl += skb->len; 4393 napi_consume_skb(skb, budget); 4394 } 4395 dirty_tx++; 4396 } 4397 4398 if (tp->dirty_tx != dirty_tx) { 4399 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4400 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4401 4402 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4403 rtl_tx_slots_avail(tp), 4404 R8169_TX_START_THRS); 4405 /* 4406 * 8168 hack: TxPoll requests are lost when the Tx packets are 4407 * too close. Let's kick an extra TxPoll request when a burst 4408 * of start_xmit activity is detected (if it is not detected, 4409 * it is slow enough). -- FR 4410 * If skb is NULL then we come here again once a tx irq is 4411 * triggered after the last fragment is marked transmitted. 4412 */ 4413 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4414 rtl8169_doorbell(tp); 4415 } 4416 } 4417 4418 static inline int rtl8169_fragmented_frame(u32 status) 4419 { 4420 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4421 } 4422 4423 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4424 { 4425 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4426 4427 if (status == RxProtoTCP || status == RxProtoUDP) 4428 skb->ip_summed = CHECKSUM_UNNECESSARY; 4429 else 4430 skb_checksum_none_assert(skb); 4431 } 4432 4433 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4434 { 4435 struct device *d = tp_to_dev(tp); 4436 int count; 4437 4438 for (count = 0; count < budget; count++, tp->cur_rx++) { 4439 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4440 struct RxDesc *desc = tp->RxDescArray + entry; 4441 struct sk_buff *skb; 4442 const void *rx_buf; 4443 dma_addr_t addr; 4444 u32 status; 4445 4446 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4447 if (status & DescOwn) 4448 break; 4449 4450 /* This barrier is needed to keep us from reading 4451 * any other fields out of the Rx descriptor until 4452 * we know the status of DescOwn 4453 */ 4454 dma_rmb(); 4455 4456 if (unlikely(status & RxRES)) { 4457 if (net_ratelimit()) 4458 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4459 status); 4460 dev->stats.rx_errors++; 4461 if (status & (RxRWT | RxRUNT)) 4462 dev->stats.rx_length_errors++; 4463 if (status & RxCRC) 4464 dev->stats.rx_crc_errors++; 4465 4466 if (!(dev->features & NETIF_F_RXALL)) 4467 goto release_descriptor; 4468 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4469 goto release_descriptor; 4470 } 4471 4472 pkt_size = status & GENMASK(13, 0); 4473 if (likely(!(dev->features & NETIF_F_RXFCS))) 4474 pkt_size -= ETH_FCS_LEN; 4475 4476 /* The driver does not support incoming fragmented frames. 4477 * They are seen as a symptom of over-mtu sized frames. 4478 */ 4479 if (unlikely(rtl8169_fragmented_frame(status))) { 4480 dev->stats.rx_dropped++; 4481 dev->stats.rx_length_errors++; 4482 goto release_descriptor; 4483 } 4484 4485 skb = napi_alloc_skb(&tp->napi, pkt_size); 4486 if (unlikely(!skb)) { 4487 dev->stats.rx_dropped++; 4488 goto release_descriptor; 4489 } 4490 4491 addr = le64_to_cpu(desc->addr); 4492 rx_buf = page_address(tp->Rx_databuff[entry]); 4493 4494 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4495 prefetch(rx_buf); 4496 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4497 skb->tail += pkt_size; 4498 skb->len = pkt_size; 4499 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4500 4501 rtl8169_rx_csum(skb, status); 4502 skb->protocol = eth_type_trans(skb, dev); 4503 4504 rtl8169_rx_vlan_tag(desc, skb); 4505 4506 if (skb->pkt_type == PACKET_MULTICAST) 4507 dev->stats.multicast++; 4508 4509 napi_gro_receive(&tp->napi, skb); 4510 4511 dev_sw_netstats_rx_add(dev, pkt_size); 4512 release_descriptor: 4513 rtl8169_mark_to_asic(desc); 4514 } 4515 4516 return count; 4517 } 4518 4519 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4520 { 4521 struct rtl8169_private *tp = dev_instance; 4522 u32 status = rtl_get_events(tp); 4523 4524 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4525 return IRQ_NONE; 4526 4527 if (unlikely(status & SYSErr)) { 4528 rtl8169_pcierr_interrupt(tp->dev); 4529 goto out; 4530 } 4531 4532 if (status & LinkChg) 4533 phy_mac_interrupt(tp->phydev); 4534 4535 if (unlikely(status & RxFIFOOver && 4536 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4537 netif_stop_queue(tp->dev); 4538 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4539 } 4540 4541 if (napi_schedule_prep(&tp->napi)) { 4542 rtl_irq_disable(tp); 4543 __napi_schedule(&tp->napi); 4544 } 4545 out: 4546 rtl_ack_events(tp, status); 4547 4548 return IRQ_HANDLED; 4549 } 4550 4551 static void rtl_task(struct work_struct *work) 4552 { 4553 struct rtl8169_private *tp = 4554 container_of(work, struct rtl8169_private, wk.work); 4555 int ret; 4556 4557 rtnl_lock(); 4558 4559 if (!netif_running(tp->dev) || 4560 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4561 goto out_unlock; 4562 4563 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4564 /* if chip isn't accessible, reset bus to revive it */ 4565 if (RTL_R32(tp, TxConfig) == ~0) { 4566 ret = pci_reset_bus(tp->pci_dev); 4567 if (ret < 0) { 4568 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4569 netif_device_detach(tp->dev); 4570 goto out_unlock; 4571 } 4572 } 4573 4574 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4575 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4576 PCIE_LINK_STATE_L0S); 4577 if (!ret) 4578 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4579 goto reset; 4580 } 4581 4582 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4583 reset: 4584 rtl_reset_work(tp); 4585 netif_wake_queue(tp->dev); 4586 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4587 rtl_reset_work(tp); 4588 } 4589 out_unlock: 4590 rtnl_unlock(); 4591 } 4592 4593 static int rtl8169_poll(struct napi_struct *napi, int budget) 4594 { 4595 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4596 struct net_device *dev = tp->dev; 4597 int work_done; 4598 4599 rtl_tx(dev, tp, budget); 4600 4601 work_done = rtl_rx(dev, tp, budget); 4602 4603 if (work_done < budget && napi_complete_done(napi, work_done)) 4604 rtl_irq_enable(tp); 4605 4606 return work_done; 4607 } 4608 4609 static void r8169_phylink_handler(struct net_device *ndev) 4610 { 4611 struct rtl8169_private *tp = netdev_priv(ndev); 4612 struct device *d = tp_to_dev(tp); 4613 4614 if (netif_carrier_ok(ndev)) { 4615 rtl_link_chg_patch(tp); 4616 pm_request_resume(d); 4617 netif_wake_queue(tp->dev); 4618 } else { 4619 /* In few cases rx is broken after link-down otherwise */ 4620 if (rtl_is_8125(tp)) 4621 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4622 pm_runtime_idle(d); 4623 } 4624 4625 phy_print_status(tp->phydev); 4626 } 4627 4628 static int r8169_phy_connect(struct rtl8169_private *tp) 4629 { 4630 struct phy_device *phydev = tp->phydev; 4631 phy_interface_t phy_mode; 4632 int ret; 4633 4634 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4635 PHY_INTERFACE_MODE_MII; 4636 4637 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4638 phy_mode); 4639 if (ret) 4640 return ret; 4641 4642 if (!tp->supports_gmii) 4643 phy_set_max_speed(phydev, SPEED_100); 4644 4645 phy_attached_info(phydev); 4646 4647 return 0; 4648 } 4649 4650 static void rtl8169_down(struct rtl8169_private *tp) 4651 { 4652 /* Clear all task flags */ 4653 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4654 4655 phy_stop(tp->phydev); 4656 4657 rtl8169_update_counters(tp); 4658 4659 pci_clear_master(tp->pci_dev); 4660 rtl_pci_commit(tp); 4661 4662 rtl8169_cleanup(tp); 4663 rtl_disable_exit_l1(tp); 4664 rtl_prepare_power_down(tp); 4665 4666 if (tp->dash_type != RTL_DASH_NONE) 4667 rtl8168_driver_stop(tp); 4668 } 4669 4670 static void rtl8169_up(struct rtl8169_private *tp) 4671 { 4672 if (tp->dash_type != RTL_DASH_NONE) 4673 rtl8168_driver_start(tp); 4674 4675 pci_set_master(tp->pci_dev); 4676 phy_init_hw(tp->phydev); 4677 phy_resume(tp->phydev); 4678 rtl8169_init_phy(tp); 4679 napi_enable(&tp->napi); 4680 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4681 rtl_reset_work(tp); 4682 4683 phy_start(tp->phydev); 4684 } 4685 4686 static int rtl8169_close(struct net_device *dev) 4687 { 4688 struct rtl8169_private *tp = netdev_priv(dev); 4689 struct pci_dev *pdev = tp->pci_dev; 4690 4691 pm_runtime_get_sync(&pdev->dev); 4692 4693 netif_stop_queue(dev); 4694 rtl8169_down(tp); 4695 rtl8169_rx_clear(tp); 4696 4697 cancel_work(&tp->wk.work); 4698 4699 free_irq(tp->irq, tp); 4700 4701 phy_disconnect(tp->phydev); 4702 4703 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4704 tp->RxPhyAddr); 4705 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4706 tp->TxPhyAddr); 4707 tp->TxDescArray = NULL; 4708 tp->RxDescArray = NULL; 4709 4710 pm_runtime_put_sync(&pdev->dev); 4711 4712 return 0; 4713 } 4714 4715 #ifdef CONFIG_NET_POLL_CONTROLLER 4716 static void rtl8169_netpoll(struct net_device *dev) 4717 { 4718 struct rtl8169_private *tp = netdev_priv(dev); 4719 4720 rtl8169_interrupt(tp->irq, tp); 4721 } 4722 #endif 4723 4724 static int rtl_open(struct net_device *dev) 4725 { 4726 struct rtl8169_private *tp = netdev_priv(dev); 4727 struct pci_dev *pdev = tp->pci_dev; 4728 unsigned long irqflags; 4729 int retval = -ENOMEM; 4730 4731 pm_runtime_get_sync(&pdev->dev); 4732 4733 /* 4734 * Rx and Tx descriptors needs 256 bytes alignment. 4735 * dma_alloc_coherent provides more. 4736 */ 4737 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4738 &tp->TxPhyAddr, GFP_KERNEL); 4739 if (!tp->TxDescArray) 4740 goto out; 4741 4742 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4743 &tp->RxPhyAddr, GFP_KERNEL); 4744 if (!tp->RxDescArray) 4745 goto err_free_tx_0; 4746 4747 retval = rtl8169_init_ring(tp); 4748 if (retval < 0) 4749 goto err_free_rx_1; 4750 4751 rtl_request_firmware(tp); 4752 4753 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4754 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4755 if (retval < 0) 4756 goto err_release_fw_2; 4757 4758 retval = r8169_phy_connect(tp); 4759 if (retval) 4760 goto err_free_irq; 4761 4762 rtl8169_up(tp); 4763 rtl8169_init_counter_offsets(tp); 4764 netif_start_queue(dev); 4765 out: 4766 pm_runtime_put_sync(&pdev->dev); 4767 4768 return retval; 4769 4770 err_free_irq: 4771 free_irq(tp->irq, tp); 4772 err_release_fw_2: 4773 rtl_release_firmware(tp); 4774 rtl8169_rx_clear(tp); 4775 err_free_rx_1: 4776 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4777 tp->RxPhyAddr); 4778 tp->RxDescArray = NULL; 4779 err_free_tx_0: 4780 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4781 tp->TxPhyAddr); 4782 tp->TxDescArray = NULL; 4783 goto out; 4784 } 4785 4786 static void 4787 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4788 { 4789 struct rtl8169_private *tp = netdev_priv(dev); 4790 struct pci_dev *pdev = tp->pci_dev; 4791 struct rtl8169_counters *counters = tp->counters; 4792 4793 pm_runtime_get_noresume(&pdev->dev); 4794 4795 netdev_stats_to_stats64(stats, &dev->stats); 4796 dev_fetch_sw_netstats(stats, dev->tstats); 4797 4798 /* 4799 * Fetch additional counter values missing in stats collected by driver 4800 * from tally counters. 4801 */ 4802 if (pm_runtime_active(&pdev->dev)) 4803 rtl8169_update_counters(tp); 4804 4805 /* 4806 * Subtract values fetched during initalization. 4807 * See rtl8169_init_counter_offsets for a description why we do that. 4808 */ 4809 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4810 le64_to_cpu(tp->tc_offset.tx_errors); 4811 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4812 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4813 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4814 le16_to_cpu(tp->tc_offset.tx_aborted); 4815 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4816 le16_to_cpu(tp->tc_offset.rx_missed); 4817 4818 pm_runtime_put_noidle(&pdev->dev); 4819 } 4820 4821 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4822 { 4823 netif_device_detach(tp->dev); 4824 4825 if (netif_running(tp->dev)) 4826 rtl8169_down(tp); 4827 } 4828 4829 static int rtl8169_runtime_resume(struct device *dev) 4830 { 4831 struct rtl8169_private *tp = dev_get_drvdata(dev); 4832 4833 rtl_rar_set(tp, tp->dev->dev_addr); 4834 __rtl8169_set_wol(tp, tp->saved_wolopts); 4835 4836 if (tp->TxDescArray) 4837 rtl8169_up(tp); 4838 4839 netif_device_attach(tp->dev); 4840 4841 return 0; 4842 } 4843 4844 static int rtl8169_suspend(struct device *device) 4845 { 4846 struct rtl8169_private *tp = dev_get_drvdata(device); 4847 4848 rtnl_lock(); 4849 rtl8169_net_suspend(tp); 4850 if (!device_may_wakeup(tp_to_dev(tp))) 4851 clk_disable_unprepare(tp->clk); 4852 rtnl_unlock(); 4853 4854 return 0; 4855 } 4856 4857 static int rtl8169_resume(struct device *device) 4858 { 4859 struct rtl8169_private *tp = dev_get_drvdata(device); 4860 4861 if (!device_may_wakeup(tp_to_dev(tp))) 4862 clk_prepare_enable(tp->clk); 4863 4864 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4865 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4866 rtl_init_rxcfg(tp); 4867 4868 return rtl8169_runtime_resume(device); 4869 } 4870 4871 static int rtl8169_runtime_suspend(struct device *device) 4872 { 4873 struct rtl8169_private *tp = dev_get_drvdata(device); 4874 4875 if (!tp->TxDescArray) { 4876 netif_device_detach(tp->dev); 4877 return 0; 4878 } 4879 4880 rtnl_lock(); 4881 __rtl8169_set_wol(tp, WAKE_PHY); 4882 rtl8169_net_suspend(tp); 4883 rtnl_unlock(); 4884 4885 return 0; 4886 } 4887 4888 static int rtl8169_runtime_idle(struct device *device) 4889 { 4890 struct rtl8169_private *tp = dev_get_drvdata(device); 4891 4892 if (tp->dash_enabled) 4893 return -EBUSY; 4894 4895 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4896 pm_schedule_suspend(device, 10000); 4897 4898 return -EBUSY; 4899 } 4900 4901 static const struct dev_pm_ops rtl8169_pm_ops = { 4902 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4903 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4904 rtl8169_runtime_idle) 4905 }; 4906 4907 static void rtl_shutdown(struct pci_dev *pdev) 4908 { 4909 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4910 4911 rtnl_lock(); 4912 rtl8169_net_suspend(tp); 4913 rtnl_unlock(); 4914 4915 /* Restore original MAC address */ 4916 rtl_rar_set(tp, tp->dev->perm_addr); 4917 4918 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 4919 pci_wake_from_d3(pdev, tp->saved_wolopts); 4920 pci_set_power_state(pdev, PCI_D3hot); 4921 } 4922 } 4923 4924 static void rtl_remove_one(struct pci_dev *pdev) 4925 { 4926 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4927 4928 if (pci_dev_run_wake(pdev)) 4929 pm_runtime_get_noresume(&pdev->dev); 4930 4931 cancel_work_sync(&tp->wk.work); 4932 4933 unregister_netdev(tp->dev); 4934 4935 if (tp->dash_type != RTL_DASH_NONE) 4936 rtl8168_driver_stop(tp); 4937 4938 rtl_release_firmware(tp); 4939 4940 /* restore original MAC address */ 4941 rtl_rar_set(tp, tp->dev->perm_addr); 4942 } 4943 4944 static const struct net_device_ops rtl_netdev_ops = { 4945 .ndo_open = rtl_open, 4946 .ndo_stop = rtl8169_close, 4947 .ndo_get_stats64 = rtl8169_get_stats64, 4948 .ndo_start_xmit = rtl8169_start_xmit, 4949 .ndo_features_check = rtl8169_features_check, 4950 .ndo_tx_timeout = rtl8169_tx_timeout, 4951 .ndo_validate_addr = eth_validate_addr, 4952 .ndo_change_mtu = rtl8169_change_mtu, 4953 .ndo_fix_features = rtl8169_fix_features, 4954 .ndo_set_features = rtl8169_set_features, 4955 .ndo_set_mac_address = rtl_set_mac_address, 4956 .ndo_eth_ioctl = phy_do_ioctl_running, 4957 .ndo_set_rx_mode = rtl_set_rx_mode, 4958 #ifdef CONFIG_NET_POLL_CONTROLLER 4959 .ndo_poll_controller = rtl8169_netpoll, 4960 #endif 4961 4962 }; 4963 4964 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4965 { 4966 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4967 4968 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4969 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4970 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4971 /* special workaround needed */ 4972 tp->irq_mask |= RxFIFOOver; 4973 else 4974 tp->irq_mask |= RxOverflow; 4975 } 4976 4977 static int rtl_alloc_irq(struct rtl8169_private *tp) 4978 { 4979 unsigned int flags; 4980 4981 switch (tp->mac_version) { 4982 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4983 rtl_unlock_config_regs(tp); 4984 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4985 rtl_lock_config_regs(tp); 4986 fallthrough; 4987 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4988 flags = PCI_IRQ_LEGACY; 4989 break; 4990 default: 4991 flags = PCI_IRQ_ALL_TYPES; 4992 break; 4993 } 4994 4995 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4996 } 4997 4998 static void rtl_read_mac_address(struct rtl8169_private *tp, 4999 u8 mac_addr[ETH_ALEN]) 5000 { 5001 /* Get MAC address */ 5002 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5003 u32 value; 5004 5005 value = rtl_eri_read(tp, 0xe0); 5006 put_unaligned_le32(value, mac_addr); 5007 value = rtl_eri_read(tp, 0xe4); 5008 put_unaligned_le16(value, mac_addr + 4); 5009 } else if (rtl_is_8125(tp)) { 5010 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5011 } 5012 } 5013 5014 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5015 { 5016 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5017 } 5018 5019 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5020 { 5021 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5022 } 5023 5024 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5025 { 5026 struct rtl8169_private *tp = mii_bus->priv; 5027 5028 if (phyaddr > 0) 5029 return -ENODEV; 5030 5031 return rtl_readphy(tp, phyreg); 5032 } 5033 5034 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5035 int phyreg, u16 val) 5036 { 5037 struct rtl8169_private *tp = mii_bus->priv; 5038 5039 if (phyaddr > 0) 5040 return -ENODEV; 5041 5042 rtl_writephy(tp, phyreg, val); 5043 5044 return 0; 5045 } 5046 5047 static int r8169_mdio_register(struct rtl8169_private *tp) 5048 { 5049 struct pci_dev *pdev = tp->pci_dev; 5050 struct mii_bus *new_bus; 5051 int ret; 5052 5053 new_bus = devm_mdiobus_alloc(&pdev->dev); 5054 if (!new_bus) 5055 return -ENOMEM; 5056 5057 new_bus->name = "r8169"; 5058 new_bus->priv = tp; 5059 new_bus->parent = &pdev->dev; 5060 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5061 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5062 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5063 5064 new_bus->read = r8169_mdio_read_reg; 5065 new_bus->write = r8169_mdio_write_reg; 5066 5067 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5068 if (ret) 5069 return ret; 5070 5071 tp->phydev = mdiobus_get_phy(new_bus, 0); 5072 if (!tp->phydev) { 5073 return -ENODEV; 5074 } else if (!tp->phydev->drv) { 5075 /* Most chip versions fail with the genphy driver. 5076 * Therefore ensure that the dedicated PHY driver is loaded. 5077 */ 5078 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5079 tp->phydev->phy_id); 5080 return -EUNATCH; 5081 } 5082 5083 tp->phydev->mac_managed_pm = true; 5084 5085 phy_support_asym_pause(tp->phydev); 5086 5087 /* PHY will be woken up in rtl_open() */ 5088 phy_suspend(tp->phydev); 5089 5090 return 0; 5091 } 5092 5093 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5094 { 5095 rtl_enable_rxdvgate(tp); 5096 5097 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5098 msleep(1); 5099 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5100 5101 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5102 r8168g_wait_ll_share_fifo_ready(tp); 5103 5104 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5105 r8168g_wait_ll_share_fifo_ready(tp); 5106 } 5107 5108 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5109 { 5110 rtl_enable_rxdvgate(tp); 5111 5112 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5113 msleep(1); 5114 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5115 5116 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5117 r8168g_wait_ll_share_fifo_ready(tp); 5118 5119 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5120 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5121 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5122 r8168g_wait_ll_share_fifo_ready(tp); 5123 } 5124 5125 static void rtl_hw_initialize(struct rtl8169_private *tp) 5126 { 5127 switch (tp->mac_version) { 5128 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5129 rtl8168ep_stop_cmac(tp); 5130 fallthrough; 5131 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5132 rtl_hw_init_8168g(tp); 5133 break; 5134 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5135 rtl_hw_init_8125(tp); 5136 break; 5137 default: 5138 break; 5139 } 5140 } 5141 5142 static int rtl_jumbo_max(struct rtl8169_private *tp) 5143 { 5144 /* Non-GBit versions don't support jumbo frames */ 5145 if (!tp->supports_gmii) 5146 return 0; 5147 5148 switch (tp->mac_version) { 5149 /* RTL8169 */ 5150 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5151 return JUMBO_7K; 5152 /* RTL8168b */ 5153 case RTL_GIGA_MAC_VER_11: 5154 case RTL_GIGA_MAC_VER_17: 5155 return JUMBO_4K; 5156 /* RTL8168c */ 5157 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5158 return JUMBO_6K; 5159 default: 5160 return JUMBO_9K; 5161 } 5162 } 5163 5164 static void rtl_init_mac_address(struct rtl8169_private *tp) 5165 { 5166 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5167 struct net_device *dev = tp->dev; 5168 int rc; 5169 5170 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5171 if (!rc) 5172 goto done; 5173 5174 rtl_read_mac_address(tp, mac_addr); 5175 if (is_valid_ether_addr(mac_addr)) 5176 goto done; 5177 5178 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5179 if (is_valid_ether_addr(mac_addr)) 5180 goto done; 5181 5182 eth_random_addr(mac_addr); 5183 dev->addr_assign_type = NET_ADDR_RANDOM; 5184 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5185 done: 5186 eth_hw_addr_set(dev, mac_addr); 5187 rtl_rar_set(tp, mac_addr); 5188 } 5189 5190 /* register is set if system vendor successfully tested ASPM 1.2 */ 5191 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5192 { 5193 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5194 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5195 return true; 5196 5197 return false; 5198 } 5199 5200 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5201 { 5202 struct rtl8169_private *tp; 5203 int jumbo_max, region, rc; 5204 enum mac_version chipset; 5205 struct net_device *dev; 5206 u32 txconfig; 5207 u16 xid; 5208 5209 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5210 if (!dev) 5211 return -ENOMEM; 5212 5213 SET_NETDEV_DEV(dev, &pdev->dev); 5214 dev->netdev_ops = &rtl_netdev_ops; 5215 tp = netdev_priv(dev); 5216 tp->dev = dev; 5217 tp->pci_dev = pdev; 5218 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5219 tp->eee_adv = -1; 5220 tp->ocp_base = OCP_STD_PHY_BASE; 5221 5222 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5223 raw_spin_lock_init(&tp->config25_lock); 5224 raw_spin_lock_init(&tp->mac_ocp_lock); 5225 5226 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5227 struct pcpu_sw_netstats); 5228 if (!dev->tstats) 5229 return -ENOMEM; 5230 5231 /* Get the *optional* external "ether_clk" used on some boards */ 5232 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5233 if (IS_ERR(tp->clk)) 5234 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5235 5236 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5237 rc = pcim_enable_device(pdev); 5238 if (rc < 0) 5239 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5240 5241 if (pcim_set_mwi(pdev) < 0) 5242 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5243 5244 /* use first MMIO region */ 5245 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5246 if (region < 0) 5247 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5248 5249 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5250 if (rc < 0) 5251 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5252 5253 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5254 5255 txconfig = RTL_R32(tp, TxConfig); 5256 if (txconfig == ~0U) 5257 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5258 5259 xid = (txconfig >> 20) & 0xfcf; 5260 5261 /* Identify chip attached to board */ 5262 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5263 if (chipset == RTL_GIGA_MAC_NONE) 5264 return dev_err_probe(&pdev->dev, -ENODEV, 5265 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5266 xid); 5267 tp->mac_version = chipset; 5268 5269 /* Disable ASPM L1 as that cause random device stop working 5270 * problems as well as full system hangs for some PCIe devices users. 5271 */ 5272 if (rtl_aspm_is_safe(tp)) 5273 rc = 0; 5274 else 5275 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5276 tp->aspm_manageable = !rc; 5277 5278 tp->dash_type = rtl_get_dash_type(tp); 5279 tp->dash_enabled = rtl_dash_is_enabled(tp); 5280 5281 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5282 5283 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5284 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5285 dev->features |= NETIF_F_HIGHDMA; 5286 5287 rtl_init_rxcfg(tp); 5288 5289 rtl8169_irq_mask_and_ack(tp); 5290 5291 rtl_hw_initialize(tp); 5292 5293 rtl_hw_reset(tp); 5294 5295 rc = rtl_alloc_irq(tp); 5296 if (rc < 0) 5297 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5298 5299 tp->irq = pci_irq_vector(pdev, 0); 5300 5301 INIT_WORK(&tp->wk.work, rtl_task); 5302 5303 rtl_init_mac_address(tp); 5304 5305 dev->ethtool_ops = &rtl8169_ethtool_ops; 5306 5307 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5308 5309 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5310 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5311 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5312 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5313 5314 /* 5315 * Pretend we are using VLANs; This bypasses a nasty bug where 5316 * Interrupts stop flowing on high load on 8110SCd controllers. 5317 */ 5318 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5319 /* Disallow toggling */ 5320 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5321 5322 if (rtl_chip_supports_csum_v2(tp)) 5323 dev->hw_features |= NETIF_F_IPV6_CSUM; 5324 5325 dev->features |= dev->hw_features; 5326 5327 /* There has been a number of reports that using SG/TSO results in 5328 * tx timeouts. However for a lot of people SG/TSO works fine. 5329 * Therefore disable both features by default, but allow users to 5330 * enable them. Use at own risk! 5331 */ 5332 if (rtl_chip_supports_csum_v2(tp)) { 5333 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5334 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5335 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5336 } else { 5337 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5338 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5339 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5340 } 5341 5342 dev->hw_features |= NETIF_F_RXALL; 5343 dev->hw_features |= NETIF_F_RXFCS; 5344 5345 netdev_sw_irq_coalesce_default_on(dev); 5346 5347 /* configure chip for default features */ 5348 rtl8169_set_features(dev, dev->features); 5349 5350 if (!tp->dash_enabled) { 5351 rtl_set_d3_pll_down(tp, true); 5352 } else { 5353 rtl_set_d3_pll_down(tp, false); 5354 dev->wol_enabled = 1; 5355 } 5356 5357 jumbo_max = rtl_jumbo_max(tp); 5358 if (jumbo_max) 5359 dev->max_mtu = jumbo_max; 5360 5361 rtl_set_irq_mask(tp); 5362 5363 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5364 5365 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5366 &tp->counters_phys_addr, 5367 GFP_KERNEL); 5368 if (!tp->counters) 5369 return -ENOMEM; 5370 5371 pci_set_drvdata(pdev, tp); 5372 5373 rc = r8169_mdio_register(tp); 5374 if (rc) 5375 return rc; 5376 5377 rc = register_netdev(dev); 5378 if (rc) 5379 return rc; 5380 5381 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5382 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5383 5384 if (jumbo_max) 5385 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5386 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5387 "ok" : "ko"); 5388 5389 if (tp->dash_type != RTL_DASH_NONE) { 5390 netdev_info(dev, "DASH %s\n", 5391 tp->dash_enabled ? "enabled" : "disabled"); 5392 rtl8168_driver_start(tp); 5393 } 5394 5395 if (pci_dev_run_wake(pdev)) 5396 pm_runtime_put_sync(&pdev->dev); 5397 5398 return 0; 5399 } 5400 5401 static struct pci_driver rtl8169_pci_driver = { 5402 .name = KBUILD_MODNAME, 5403 .id_table = rtl8169_pci_tbl, 5404 .probe = rtl_init_one, 5405 .remove = rtl_remove_one, 5406 .shutdown = rtl_shutdown, 5407 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5408 }; 5409 5410 module_pci_driver(rtl8169_pci_driver); 5411