1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <net/ip6_checksum.h> 32 33 #include "r8169.h" 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 58 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 59 60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 62 #define MC_FILTER_LIMIT 32 63 64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 66 67 #define R8169_REGS_SIZE 256 68 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 69 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 70 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 73 74 #define OCP_STD_PHY_BASE 0xa400 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 91 static const struct { 92 const char *name; 93 const char *fw_name; 94 } rtl_chip_infos[] = { 95 /* PCI devices. */ 96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 101 /* PCI-E devices. */ 102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 109 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 110 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 111 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 112 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 113 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 119 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 121 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 122 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 125 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 127 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 128 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 129 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 130 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 131 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 132 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 133 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 134 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 135 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 136 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 137 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 138 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 139 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 140 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 141 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 142 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 143 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 144 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 145 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 148 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 149 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 150 }; 151 152 static const struct pci_device_id rtl8169_pci_tbl[] = { 153 { PCI_VDEVICE(REALTEK, 0x2502) }, 154 { PCI_VDEVICE(REALTEK, 0x2600) }, 155 { PCI_VDEVICE(REALTEK, 0x8129) }, 156 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 157 { PCI_VDEVICE(REALTEK, 0x8161) }, 158 { PCI_VDEVICE(REALTEK, 0x8167) }, 159 { PCI_VDEVICE(REALTEK, 0x8168) }, 160 { PCI_VDEVICE(NCUBE, 0x8168) }, 161 { PCI_VDEVICE(REALTEK, 0x8169) }, 162 { PCI_VENDOR_ID_DLINK, 0x4300, 163 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 164 { PCI_VDEVICE(DLINK, 0x4300) }, 165 { PCI_VDEVICE(DLINK, 0x4302) }, 166 { PCI_VDEVICE(AT, 0xc107) }, 167 { PCI_VDEVICE(USR, 0x0116) }, 168 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 169 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 170 { PCI_VDEVICE(REALTEK, 0x8125) }, 171 { PCI_VDEVICE(REALTEK, 0x3000) }, 172 {} 173 }; 174 175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 176 177 enum rtl_registers { 178 MAC0 = 0, /* Ethernet hardware address. */ 179 MAC4 = 4, 180 MAR0 = 8, /* Multicast filter. */ 181 CounterAddrLow = 0x10, 182 CounterAddrHigh = 0x14, 183 TxDescStartAddrLow = 0x20, 184 TxDescStartAddrHigh = 0x24, 185 TxHDescStartAddrLow = 0x28, 186 TxHDescStartAddrHigh = 0x2c, 187 FLASH = 0x30, 188 ERSR = 0x36, 189 ChipCmd = 0x37, 190 TxPoll = 0x38, 191 IntrMask = 0x3c, 192 IntrStatus = 0x3e, 193 194 TxConfig = 0x40, 195 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 196 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 197 198 RxConfig = 0x44, 199 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 200 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 201 #define RXCFG_FIFO_SHIFT 13 202 /* No threshold before first PCI xfer */ 203 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 204 #define RX_EARLY_OFF (1 << 11) 205 #define RXCFG_DMA_SHIFT 8 206 /* Unlimited maximum PCI burst. */ 207 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 208 209 Cfg9346 = 0x50, 210 Config0 = 0x51, 211 Config1 = 0x52, 212 Config2 = 0x53, 213 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 214 215 Config3 = 0x54, 216 Config4 = 0x55, 217 Config5 = 0x56, 218 PHYAR = 0x60, 219 PHYstatus = 0x6c, 220 RxMaxSize = 0xda, 221 CPlusCmd = 0xe0, 222 IntrMitigate = 0xe2, 223 224 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 225 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 226 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 227 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 228 229 #define RTL_COALESCE_T_MAX 0x0fU 230 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 231 232 RxDescAddrLow = 0xe4, 233 RxDescAddrHigh = 0xe8, 234 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 235 236 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 237 238 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 239 240 #define TxPacketMax (8064 >> 7) 241 #define EarlySize 0x27 242 243 FuncEvent = 0xf0, 244 FuncEventMask = 0xf4, 245 FuncPresetState = 0xf8, 246 IBCR0 = 0xf8, 247 IBCR2 = 0xf9, 248 IBIMR0 = 0xfa, 249 IBISR0 = 0xfb, 250 FuncForceEvent = 0xfc, 251 }; 252 253 enum rtl8168_8101_registers { 254 CSIDR = 0x64, 255 CSIAR = 0x68, 256 #define CSIAR_FLAG 0x80000000 257 #define CSIAR_WRITE_CMD 0x80000000 258 #define CSIAR_BYTE_ENABLE 0x0000f000 259 #define CSIAR_ADDR_MASK 0x00000fff 260 PMCH = 0x6f, 261 EPHYAR = 0x80, 262 #define EPHYAR_FLAG 0x80000000 263 #define EPHYAR_WRITE_CMD 0x80000000 264 #define EPHYAR_REG_MASK 0x1f 265 #define EPHYAR_REG_SHIFT 16 266 #define EPHYAR_DATA_MASK 0xffff 267 DLLPR = 0xd0, 268 #define PFM_EN (1 << 6) 269 #define TX_10M_PS_EN (1 << 7) 270 DBG_REG = 0xd1, 271 #define FIX_NAK_1 (1 << 4) 272 #define FIX_NAK_2 (1 << 3) 273 TWSI = 0xd2, 274 MCU = 0xd3, 275 #define NOW_IS_OOB (1 << 7) 276 #define TX_EMPTY (1 << 5) 277 #define RX_EMPTY (1 << 4) 278 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 279 #define EN_NDP (1 << 3) 280 #define EN_OOB_RESET (1 << 2) 281 #define LINK_LIST_RDY (1 << 1) 282 EFUSEAR = 0xdc, 283 #define EFUSEAR_FLAG 0x80000000 284 #define EFUSEAR_WRITE_CMD 0x80000000 285 #define EFUSEAR_READ_CMD 0x00000000 286 #define EFUSEAR_REG_MASK 0x03ff 287 #define EFUSEAR_REG_SHIFT 8 288 #define EFUSEAR_DATA_MASK 0xff 289 MISC_1 = 0xf2, 290 #define PFM_D3COLD_EN (1 << 6) 291 }; 292 293 enum rtl8168_registers { 294 LED_FREQ = 0x1a, 295 EEE_LED = 0x1b, 296 ERIDR = 0x70, 297 ERIAR = 0x74, 298 #define ERIAR_FLAG 0x80000000 299 #define ERIAR_WRITE_CMD 0x80000000 300 #define ERIAR_READ_CMD 0x00000000 301 #define ERIAR_ADDR_BYTE_ALIGN 4 302 #define ERIAR_TYPE_SHIFT 16 303 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_MASK_SHIFT 12 308 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 313 EPHY_RXER_NUM = 0x7c, 314 OCPDR = 0xb0, /* OCP GPHY access */ 315 #define OCPDR_WRITE_CMD 0x80000000 316 #define OCPDR_READ_CMD 0x00000000 317 #define OCPDR_REG_MASK 0x7f 318 #define OCPDR_GPHY_REG_SHIFT 16 319 #define OCPDR_DATA_MASK 0xffff 320 OCPAR = 0xb4, 321 #define OCPAR_FLAG 0x80000000 322 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 323 #define OCPAR_GPHY_READ_CMD 0x0000f060 324 GPHY_OCP = 0xb8, 325 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 326 MISC = 0xf0, /* 8168e only. */ 327 #define TXPLA_RST (1 << 29) 328 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 329 #define PWM_EN (1 << 22) 330 #define RXDV_GATED_EN (1 << 19) 331 #define EARLY_TALLY_EN (1 << 16) 332 }; 333 334 enum rtl8125_registers { 335 IntrMask_8125 = 0x38, 336 IntrStatus_8125 = 0x3c, 337 TxPoll_8125 = 0x90, 338 MAC0_BKP = 0x19e0, 339 }; 340 341 #define RX_VLAN_INNER_8125 BIT(22) 342 #define RX_VLAN_OUTER_8125 BIT(23) 343 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 344 345 #define RX_FETCH_DFLT_8125 (8 << 27) 346 347 enum rtl_register_content { 348 /* InterruptStatusBits */ 349 SYSErr = 0x8000, 350 PCSTimeout = 0x4000, 351 SWInt = 0x0100, 352 TxDescUnavail = 0x0080, 353 RxFIFOOver = 0x0040, 354 LinkChg = 0x0020, 355 RxOverflow = 0x0010, 356 TxErr = 0x0008, 357 TxOK = 0x0004, 358 RxErr = 0x0002, 359 RxOK = 0x0001, 360 361 /* RxStatusDesc */ 362 RxRWT = (1 << 22), 363 RxRES = (1 << 21), 364 RxRUNT = (1 << 20), 365 RxCRC = (1 << 19), 366 367 /* ChipCmdBits */ 368 StopReq = 0x80, 369 CmdReset = 0x10, 370 CmdRxEnb = 0x08, 371 CmdTxEnb = 0x04, 372 RxBufEmpty = 0x01, 373 374 /* TXPoll register p.5 */ 375 HPQ = 0x80, /* Poll cmd on the high prio queue */ 376 NPQ = 0x40, /* Poll cmd on the low prio queue */ 377 FSWInt = 0x01, /* Forced software interrupt */ 378 379 /* Cfg9346Bits */ 380 Cfg9346_Lock = 0x00, 381 Cfg9346_Unlock = 0xc0, 382 383 /* rx_mode_bits */ 384 AcceptErr = 0x20, 385 AcceptRunt = 0x10, 386 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 387 AcceptBroadcast = 0x08, 388 AcceptMulticast = 0x04, 389 AcceptMyPhys = 0x02, 390 AcceptAllPhys = 0x01, 391 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 392 #define RX_CONFIG_ACCEPT_MASK 0x3f 393 394 /* TxConfigBits */ 395 TxInterFrameGapShift = 24, 396 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 397 398 /* Config1 register p.24 */ 399 LEDS1 = (1 << 7), 400 LEDS0 = (1 << 6), 401 Speed_down = (1 << 4), 402 MEMMAP = (1 << 3), 403 IOMAP = (1 << 2), 404 VPD = (1 << 1), 405 PMEnable = (1 << 0), /* Power Management Enable */ 406 407 /* Config2 register p. 25 */ 408 ClkReqEn = (1 << 7), /* Clock Request Enable */ 409 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 410 PCI_Clock_66MHz = 0x01, 411 PCI_Clock_33MHz = 0x00, 412 413 /* Config3 register p.25 */ 414 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 415 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 416 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 417 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 418 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 419 420 /* Config4 register */ 421 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 422 423 /* Config5 register p.27 */ 424 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 425 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 426 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 427 Spi_en = (1 << 3), 428 LanWake = (1 << 1), /* LanWake enable/disable */ 429 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 430 ASPM_en = (1 << 0), /* ASPM enable */ 431 432 /* CPlusCmd p.31 */ 433 EnableBist = (1 << 15), // 8168 8101 434 Mac_dbgo_oe = (1 << 14), // 8168 8101 435 EnAnaPLL = (1 << 14), // 8169 436 Normal_mode = (1 << 13), // unused 437 Force_half_dup = (1 << 12), // 8168 8101 438 Force_rxflow_en = (1 << 11), // 8168 8101 439 Force_txflow_en = (1 << 10), // 8168 8101 440 Cxpl_dbg_sel = (1 << 9), // 8168 8101 441 ASF = (1 << 8), // 8168 8101 442 PktCntrDisable = (1 << 7), // 8168 8101 443 Mac_dbgo_sel = 0x001c, // 8168 444 RxVlan = (1 << 6), 445 RxChkSum = (1 << 5), 446 PCIDAC = (1 << 4), 447 PCIMulRW = (1 << 3), 448 #define INTT_MASK GENMASK(1, 0) 449 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 450 451 /* rtl8169_PHYstatus */ 452 TBI_Enable = 0x80, 453 TxFlowCtrl = 0x40, 454 RxFlowCtrl = 0x20, 455 _1000bpsF = 0x10, 456 _100bps = 0x08, 457 _10bps = 0x04, 458 LinkStatus = 0x02, 459 FullDup = 0x01, 460 461 /* ResetCounterCommand */ 462 CounterReset = 0x1, 463 464 /* DumpCounterCommand */ 465 CounterDump = 0x8, 466 467 /* magic enable v2 */ 468 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 469 }; 470 471 enum rtl_desc_bit { 472 /* First doubleword. */ 473 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 474 RingEnd = (1 << 30), /* End of descriptor ring */ 475 FirstFrag = (1 << 29), /* First segment of a packet */ 476 LastFrag = (1 << 28), /* Final segment of a packet */ 477 }; 478 479 /* Generic case. */ 480 enum rtl_tx_desc_bit { 481 /* First doubleword. */ 482 TD_LSO = (1 << 27), /* Large Send Offload */ 483 #define TD_MSS_MAX 0x07ffu /* MSS value */ 484 485 /* Second doubleword. */ 486 TxVlanTag = (1 << 17), /* Add VLAN tag */ 487 }; 488 489 /* 8169, 8168b and 810x except 8102e. */ 490 enum rtl_tx_desc_bit_0 { 491 /* First doubleword. */ 492 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 493 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 494 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 495 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 496 }; 497 498 /* 8102e, 8168c and beyond. */ 499 enum rtl_tx_desc_bit_1 { 500 /* First doubleword. */ 501 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 502 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 503 #define GTTCPHO_SHIFT 18 504 #define GTTCPHO_MAX 0x7f 505 506 /* Second doubleword. */ 507 #define TCPHO_SHIFT 18 508 #define TCPHO_MAX 0x3ff 509 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 510 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 511 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 512 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 513 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 514 }; 515 516 enum rtl_rx_desc_bit { 517 /* Rx private */ 518 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 519 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 520 521 #define RxProtoUDP (PID1) 522 #define RxProtoTCP (PID0) 523 #define RxProtoIP (PID1 | PID0) 524 #define RxProtoMask RxProtoIP 525 526 IPFail = (1 << 16), /* IP checksum failed */ 527 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 528 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 529 RxVlanTag = (1 << 16), /* VLAN tag available */ 530 }; 531 532 #define RsvdMask 0x3fffc000 533 534 #define RTL_GSO_MAX_SIZE_V1 32000 535 #define RTL_GSO_MAX_SEGS_V1 24 536 #define RTL_GSO_MAX_SIZE_V2 64000 537 #define RTL_GSO_MAX_SEGS_V2 64 538 539 struct TxDesc { 540 __le32 opts1; 541 __le32 opts2; 542 __le64 addr; 543 }; 544 545 struct RxDesc { 546 __le32 opts1; 547 __le32 opts2; 548 __le64 addr; 549 }; 550 551 struct ring_info { 552 struct sk_buff *skb; 553 u32 len; 554 }; 555 556 struct rtl8169_counters { 557 __le64 tx_packets; 558 __le64 rx_packets; 559 __le64 tx_errors; 560 __le32 rx_errors; 561 __le16 rx_missed; 562 __le16 align_errors; 563 __le32 tx_one_collision; 564 __le32 tx_multi_collision; 565 __le64 rx_unicast; 566 __le64 rx_broadcast; 567 __le32 rx_multicast; 568 __le16 tx_aborted; 569 __le16 tx_underun; 570 }; 571 572 struct rtl8169_tc_offsets { 573 bool inited; 574 __le64 tx_errors; 575 __le32 tx_multi_collision; 576 __le16 tx_aborted; 577 __le16 rx_missed; 578 }; 579 580 enum rtl_flag { 581 RTL_FLAG_TASK_ENABLED = 0, 582 RTL_FLAG_TASK_RESET_PENDING, 583 RTL_FLAG_MAX 584 }; 585 586 struct rtl8169_stats { 587 u64 packets; 588 u64 bytes; 589 struct u64_stats_sync syncp; 590 }; 591 592 struct rtl8169_private { 593 void __iomem *mmio_addr; /* memory map physical address */ 594 struct pci_dev *pci_dev; 595 struct net_device *dev; 596 struct phy_device *phydev; 597 struct napi_struct napi; 598 enum mac_version mac_version; 599 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 600 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 601 u32 dirty_tx; 602 struct rtl8169_stats rx_stats; 603 struct rtl8169_stats tx_stats; 604 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 605 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 606 dma_addr_t TxPhyAddr; 607 dma_addr_t RxPhyAddr; 608 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 609 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 610 u16 cp_cmd; 611 u32 irq_mask; 612 struct clk *clk; 613 614 struct { 615 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 616 struct mutex mutex; 617 struct work_struct work; 618 } wk; 619 620 unsigned irq_enabled:1; 621 unsigned supports_gmii:1; 622 unsigned aspm_manageable:1; 623 dma_addr_t counters_phys_addr; 624 struct rtl8169_counters *counters; 625 struct rtl8169_tc_offsets tc_offset; 626 u32 saved_wolopts; 627 int eee_adv; 628 629 const char *fw_name; 630 struct rtl_fw *rtl_fw; 631 632 u32 ocp_base; 633 }; 634 635 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 636 637 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 638 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 639 MODULE_SOFTDEP("pre: realtek"); 640 MODULE_LICENSE("GPL"); 641 MODULE_FIRMWARE(FIRMWARE_8168D_1); 642 MODULE_FIRMWARE(FIRMWARE_8168D_2); 643 MODULE_FIRMWARE(FIRMWARE_8168E_1); 644 MODULE_FIRMWARE(FIRMWARE_8168E_2); 645 MODULE_FIRMWARE(FIRMWARE_8168E_3); 646 MODULE_FIRMWARE(FIRMWARE_8105E_1); 647 MODULE_FIRMWARE(FIRMWARE_8168F_1); 648 MODULE_FIRMWARE(FIRMWARE_8168F_2); 649 MODULE_FIRMWARE(FIRMWARE_8402_1); 650 MODULE_FIRMWARE(FIRMWARE_8411_1); 651 MODULE_FIRMWARE(FIRMWARE_8411_2); 652 MODULE_FIRMWARE(FIRMWARE_8106E_1); 653 MODULE_FIRMWARE(FIRMWARE_8106E_2); 654 MODULE_FIRMWARE(FIRMWARE_8168G_2); 655 MODULE_FIRMWARE(FIRMWARE_8168G_3); 656 MODULE_FIRMWARE(FIRMWARE_8168H_1); 657 MODULE_FIRMWARE(FIRMWARE_8168H_2); 658 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 659 MODULE_FIRMWARE(FIRMWARE_8107E_1); 660 MODULE_FIRMWARE(FIRMWARE_8107E_2); 661 MODULE_FIRMWARE(FIRMWARE_8125A_3); 662 663 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 664 { 665 return &tp->pci_dev->dev; 666 } 667 668 static void rtl_lock_work(struct rtl8169_private *tp) 669 { 670 mutex_lock(&tp->wk.mutex); 671 } 672 673 static void rtl_unlock_work(struct rtl8169_private *tp) 674 { 675 mutex_unlock(&tp->wk.mutex); 676 } 677 678 static void rtl_lock_config_regs(struct rtl8169_private *tp) 679 { 680 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 681 } 682 683 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 684 { 685 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 686 } 687 688 static void rtl_pci_commit(struct rtl8169_private *tp) 689 { 690 /* Read an arbitrary register to commit a preceding PCI write */ 691 RTL_R8(tp, ChipCmd); 692 } 693 694 static bool rtl_is_8125(struct rtl8169_private *tp) 695 { 696 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 697 } 698 699 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 700 { 701 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 702 tp->mac_version != RTL_GIGA_MAC_VER_39 && 703 tp->mac_version <= RTL_GIGA_MAC_VER_52; 704 } 705 706 static bool rtl_supports_eee(struct rtl8169_private *tp) 707 { 708 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 709 tp->mac_version != RTL_GIGA_MAC_VER_37 && 710 tp->mac_version != RTL_GIGA_MAC_VER_39; 711 } 712 713 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 714 { 715 int i; 716 717 for (i = 0; i < ETH_ALEN; i++) 718 mac[i] = RTL_R8(tp, reg + i); 719 } 720 721 struct rtl_cond { 722 bool (*check)(struct rtl8169_private *); 723 const char *msg; 724 }; 725 726 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 727 unsigned long usecs, int n, bool high) 728 { 729 int i; 730 731 for (i = 0; i < n; i++) { 732 if (c->check(tp) == high) 733 return true; 734 fsleep(usecs); 735 } 736 737 if (net_ratelimit()) 738 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 739 c->msg, !high, n, usecs); 740 return false; 741 } 742 743 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 744 const struct rtl_cond *c, 745 unsigned long d, int n) 746 { 747 return rtl_loop_wait(tp, c, d, n, true); 748 } 749 750 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 751 const struct rtl_cond *c, 752 unsigned long d, int n) 753 { 754 return rtl_loop_wait(tp, c, d, n, false); 755 } 756 757 #define DECLARE_RTL_COND(name) \ 758 static bool name ## _check(struct rtl8169_private *); \ 759 \ 760 static const struct rtl_cond name = { \ 761 .check = name ## _check, \ 762 .msg = #name \ 763 }; \ 764 \ 765 static bool name ## _check(struct rtl8169_private *tp) 766 767 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 768 { 769 if (reg & 0xffff0001) { 770 if (net_ratelimit()) 771 netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg); 772 return true; 773 } 774 return false; 775 } 776 777 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 778 { 779 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 780 } 781 782 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 783 { 784 if (rtl_ocp_reg_failure(tp, reg)) 785 return; 786 787 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 788 789 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 790 } 791 792 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 793 { 794 if (rtl_ocp_reg_failure(tp, reg)) 795 return 0; 796 797 RTL_W32(tp, GPHY_OCP, reg << 15); 798 799 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 800 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 801 } 802 803 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 804 { 805 if (rtl_ocp_reg_failure(tp, reg)) 806 return; 807 808 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 809 } 810 811 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 812 { 813 if (rtl_ocp_reg_failure(tp, reg)) 814 return 0; 815 816 RTL_W32(tp, OCPDR, reg << 15); 817 818 return RTL_R32(tp, OCPDR); 819 } 820 821 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 822 u16 set) 823 { 824 u16 data = r8168_mac_ocp_read(tp, reg); 825 826 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 827 } 828 829 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 830 { 831 if (reg == 0x1f) { 832 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 833 return; 834 } 835 836 if (tp->ocp_base != OCP_STD_PHY_BASE) 837 reg -= 0x10; 838 839 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 840 } 841 842 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 843 { 844 if (reg == 0x1f) 845 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 846 847 if (tp->ocp_base != OCP_STD_PHY_BASE) 848 reg -= 0x10; 849 850 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 851 } 852 853 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 854 { 855 if (reg == 0x1f) { 856 tp->ocp_base = value << 4; 857 return; 858 } 859 860 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 861 } 862 863 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 864 { 865 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 866 } 867 868 DECLARE_RTL_COND(rtl_phyar_cond) 869 { 870 return RTL_R32(tp, PHYAR) & 0x80000000; 871 } 872 873 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 874 { 875 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 876 877 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 878 /* 879 * According to hardware specs a 20us delay is required after write 880 * complete indication, but before sending next command. 881 */ 882 udelay(20); 883 } 884 885 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 886 { 887 int value; 888 889 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 890 891 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 892 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 893 894 /* 895 * According to hardware specs a 20us delay is required after read 896 * complete indication, but before sending next command. 897 */ 898 udelay(20); 899 900 return value; 901 } 902 903 DECLARE_RTL_COND(rtl_ocpar_cond) 904 { 905 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 906 } 907 908 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 909 { 910 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 911 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 912 RTL_W32(tp, EPHY_RXER_NUM, 0); 913 914 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 915 } 916 917 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 918 { 919 r8168dp_1_mdio_access(tp, reg, 920 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 921 } 922 923 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 924 { 925 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 926 927 mdelay(1); 928 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 929 RTL_W32(tp, EPHY_RXER_NUM, 0); 930 931 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 932 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 933 } 934 935 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 936 937 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 938 { 939 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 940 } 941 942 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 943 { 944 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 945 } 946 947 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 948 { 949 r8168dp_2_mdio_start(tp); 950 951 r8169_mdio_write(tp, reg, value); 952 953 r8168dp_2_mdio_stop(tp); 954 } 955 956 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 957 { 958 int value; 959 960 /* Work around issue with chip reporting wrong PHY ID */ 961 if (reg == MII_PHYSID2) 962 return 0xc912; 963 964 r8168dp_2_mdio_start(tp); 965 966 value = r8169_mdio_read(tp, reg); 967 968 r8168dp_2_mdio_stop(tp); 969 970 return value; 971 } 972 973 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 974 { 975 switch (tp->mac_version) { 976 case RTL_GIGA_MAC_VER_27: 977 r8168dp_1_mdio_write(tp, location, val); 978 break; 979 case RTL_GIGA_MAC_VER_28: 980 case RTL_GIGA_MAC_VER_31: 981 r8168dp_2_mdio_write(tp, location, val); 982 break; 983 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 984 r8168g_mdio_write(tp, location, val); 985 break; 986 default: 987 r8169_mdio_write(tp, location, val); 988 break; 989 } 990 } 991 992 static int rtl_readphy(struct rtl8169_private *tp, int location) 993 { 994 switch (tp->mac_version) { 995 case RTL_GIGA_MAC_VER_27: 996 return r8168dp_1_mdio_read(tp, location); 997 case RTL_GIGA_MAC_VER_28: 998 case RTL_GIGA_MAC_VER_31: 999 return r8168dp_2_mdio_read(tp, location); 1000 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1001 return r8168g_mdio_read(tp, location); 1002 default: 1003 return r8169_mdio_read(tp, location); 1004 } 1005 } 1006 1007 DECLARE_RTL_COND(rtl_ephyar_cond) 1008 { 1009 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1010 } 1011 1012 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1013 { 1014 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1015 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1016 1017 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1018 1019 udelay(10); 1020 } 1021 1022 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1023 { 1024 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1025 1026 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1027 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1028 } 1029 1030 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 1031 { 1032 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 1033 if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB) 1034 *cmd |= 0x7f0 << 18; 1035 } 1036 1037 DECLARE_RTL_COND(rtl_eriar_cond) 1038 { 1039 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1040 } 1041 1042 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1043 u32 val, int type) 1044 { 1045 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 1046 1047 BUG_ON((addr & 3) || (mask == 0)); 1048 RTL_W32(tp, ERIDR, val); 1049 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1050 RTL_W32(tp, ERIAR, cmd); 1051 1052 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1053 } 1054 1055 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1056 u32 val) 1057 { 1058 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1059 } 1060 1061 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1062 { 1063 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 1064 1065 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1066 RTL_W32(tp, ERIAR, cmd); 1067 1068 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1069 RTL_R32(tp, ERIDR) : ~0; 1070 } 1071 1072 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1073 { 1074 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1075 } 1076 1077 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 1078 { 1079 u32 val = rtl_eri_read(tp, addr); 1080 1081 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1082 } 1083 1084 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1085 { 1086 rtl_w0w1_eri(tp, addr, p, 0); 1087 } 1088 1089 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1090 { 1091 rtl_w0w1_eri(tp, addr, 0, m); 1092 } 1093 1094 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1095 { 1096 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1097 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1098 RTL_R32(tp, OCPDR) : ~0; 1099 } 1100 1101 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1102 { 1103 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1104 } 1105 1106 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1107 u32 data) 1108 { 1109 RTL_W32(tp, OCPDR, data); 1110 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1111 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1112 } 1113 1114 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1115 u32 data) 1116 { 1117 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1118 data, ERIAR_OOB); 1119 } 1120 1121 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1122 { 1123 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1124 1125 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1126 } 1127 1128 #define OOB_CMD_RESET 0x00 1129 #define OOB_CMD_DRIVER_START 0x05 1130 #define OOB_CMD_DRIVER_STOP 0x06 1131 1132 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1133 { 1134 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1135 } 1136 1137 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1138 { 1139 u16 reg; 1140 1141 reg = rtl8168_get_ocp_reg(tp); 1142 1143 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1144 } 1145 1146 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1147 { 1148 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1149 } 1150 1151 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1152 { 1153 return RTL_R8(tp, IBISR0) & 0x20; 1154 } 1155 1156 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1157 { 1158 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1159 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1160 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1161 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1162 } 1163 1164 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1165 { 1166 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1167 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1168 } 1169 1170 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1171 { 1172 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1173 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1174 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1175 } 1176 1177 static void rtl8168_driver_start(struct rtl8169_private *tp) 1178 { 1179 switch (tp->mac_version) { 1180 case RTL_GIGA_MAC_VER_27: 1181 case RTL_GIGA_MAC_VER_28: 1182 case RTL_GIGA_MAC_VER_31: 1183 rtl8168dp_driver_start(tp); 1184 break; 1185 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1186 rtl8168ep_driver_start(tp); 1187 break; 1188 default: 1189 BUG(); 1190 break; 1191 } 1192 } 1193 1194 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1195 { 1196 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1197 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1198 } 1199 1200 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1201 { 1202 rtl8168ep_stop_cmac(tp); 1203 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1204 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1205 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1206 } 1207 1208 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1209 { 1210 switch (tp->mac_version) { 1211 case RTL_GIGA_MAC_VER_27: 1212 case RTL_GIGA_MAC_VER_28: 1213 case RTL_GIGA_MAC_VER_31: 1214 rtl8168dp_driver_stop(tp); 1215 break; 1216 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1217 rtl8168ep_driver_stop(tp); 1218 break; 1219 default: 1220 BUG(); 1221 break; 1222 } 1223 } 1224 1225 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1226 { 1227 u16 reg = rtl8168_get_ocp_reg(tp); 1228 1229 return !!(r8168dp_ocp_read(tp, reg) & 0x00008000); 1230 } 1231 1232 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1233 { 1234 return r8168ep_ocp_read(tp, 0x128) & 0x00000001; 1235 } 1236 1237 static bool r8168_check_dash(struct rtl8169_private *tp) 1238 { 1239 switch (tp->mac_version) { 1240 case RTL_GIGA_MAC_VER_27: 1241 case RTL_GIGA_MAC_VER_28: 1242 case RTL_GIGA_MAC_VER_31: 1243 return r8168dp_check_dash(tp); 1244 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1245 return r8168ep_check_dash(tp); 1246 default: 1247 return false; 1248 } 1249 } 1250 1251 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1252 { 1253 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1254 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1255 } 1256 1257 DECLARE_RTL_COND(rtl_efusear_cond) 1258 { 1259 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1260 } 1261 1262 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1263 { 1264 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1265 1266 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1267 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1268 } 1269 1270 static u32 rtl_get_events(struct rtl8169_private *tp) 1271 { 1272 if (rtl_is_8125(tp)) 1273 return RTL_R32(tp, IntrStatus_8125); 1274 else 1275 return RTL_R16(tp, IntrStatus); 1276 } 1277 1278 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1279 { 1280 if (rtl_is_8125(tp)) 1281 RTL_W32(tp, IntrStatus_8125, bits); 1282 else 1283 RTL_W16(tp, IntrStatus, bits); 1284 } 1285 1286 static void rtl_irq_disable(struct rtl8169_private *tp) 1287 { 1288 if (rtl_is_8125(tp)) 1289 RTL_W32(tp, IntrMask_8125, 0); 1290 else 1291 RTL_W16(tp, IntrMask, 0); 1292 tp->irq_enabled = 0; 1293 } 1294 1295 static void rtl_irq_enable(struct rtl8169_private *tp) 1296 { 1297 tp->irq_enabled = 1; 1298 if (rtl_is_8125(tp)) 1299 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1300 else 1301 RTL_W16(tp, IntrMask, tp->irq_mask); 1302 } 1303 1304 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1305 { 1306 rtl_irq_disable(tp); 1307 rtl_ack_events(tp, 0xffffffff); 1308 rtl_pci_commit(tp); 1309 } 1310 1311 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1312 { 1313 struct phy_device *phydev = tp->phydev; 1314 1315 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1316 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1317 if (phydev->speed == SPEED_1000) { 1318 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1319 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1320 } else if (phydev->speed == SPEED_100) { 1321 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1322 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1323 } else { 1324 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1325 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1326 } 1327 rtl_reset_packet_filter(tp); 1328 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1329 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1330 if (phydev->speed == SPEED_1000) { 1331 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1332 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1333 } else { 1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1336 } 1337 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1338 if (phydev->speed == SPEED_10) { 1339 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1340 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1341 } else { 1342 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1343 } 1344 } 1345 } 1346 1347 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1348 1349 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1350 { 1351 struct rtl8169_private *tp = netdev_priv(dev); 1352 1353 rtl_lock_work(tp); 1354 wol->supported = WAKE_ANY; 1355 wol->wolopts = tp->saved_wolopts; 1356 rtl_unlock_work(tp); 1357 } 1358 1359 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1360 { 1361 static const struct { 1362 u32 opt; 1363 u16 reg; 1364 u8 mask; 1365 } cfg[] = { 1366 { WAKE_PHY, Config3, LinkUp }, 1367 { WAKE_UCAST, Config5, UWF }, 1368 { WAKE_BCAST, Config5, BWF }, 1369 { WAKE_MCAST, Config5, MWF }, 1370 { WAKE_ANY, Config5, LanWake }, 1371 { WAKE_MAGIC, Config3, MagicPacket } 1372 }; 1373 unsigned int i, tmp = ARRAY_SIZE(cfg); 1374 u8 options; 1375 1376 rtl_unlock_config_regs(tp); 1377 1378 if (rtl_is_8168evl_up(tp)) { 1379 tmp--; 1380 if (wolopts & WAKE_MAGIC) 1381 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1382 else 1383 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1384 } else if (rtl_is_8125(tp)) { 1385 tmp--; 1386 if (wolopts & WAKE_MAGIC) 1387 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1388 else 1389 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1390 } 1391 1392 for (i = 0; i < tmp; i++) { 1393 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1394 if (wolopts & cfg[i].opt) 1395 options |= cfg[i].mask; 1396 RTL_W8(tp, cfg[i].reg, options); 1397 } 1398 1399 switch (tp->mac_version) { 1400 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1401 options = RTL_R8(tp, Config1) & ~PMEnable; 1402 if (wolopts) 1403 options |= PMEnable; 1404 RTL_W8(tp, Config1, options); 1405 break; 1406 case RTL_GIGA_MAC_VER_34: 1407 case RTL_GIGA_MAC_VER_37: 1408 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_61: 1409 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1410 if (wolopts) 1411 options |= PME_SIGNAL; 1412 RTL_W8(tp, Config2, options); 1413 break; 1414 default: 1415 break; 1416 } 1417 1418 rtl_lock_config_regs(tp); 1419 1420 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1421 tp->dev->wol_enabled = wolopts ? 1 : 0; 1422 } 1423 1424 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1425 { 1426 struct rtl8169_private *tp = netdev_priv(dev); 1427 struct device *d = tp_to_dev(tp); 1428 1429 if (wol->wolopts & ~WAKE_ANY) 1430 return -EINVAL; 1431 1432 pm_runtime_get_noresume(d); 1433 1434 rtl_lock_work(tp); 1435 1436 tp->saved_wolopts = wol->wolopts; 1437 1438 if (pm_runtime_active(d)) 1439 __rtl8169_set_wol(tp, tp->saved_wolopts); 1440 1441 rtl_unlock_work(tp); 1442 1443 pm_runtime_put_noidle(d); 1444 1445 return 0; 1446 } 1447 1448 static void rtl8169_get_drvinfo(struct net_device *dev, 1449 struct ethtool_drvinfo *info) 1450 { 1451 struct rtl8169_private *tp = netdev_priv(dev); 1452 struct rtl_fw *rtl_fw = tp->rtl_fw; 1453 1454 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1455 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1456 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1457 if (rtl_fw) 1458 strlcpy(info->fw_version, rtl_fw->version, 1459 sizeof(info->fw_version)); 1460 } 1461 1462 static int rtl8169_get_regs_len(struct net_device *dev) 1463 { 1464 return R8169_REGS_SIZE; 1465 } 1466 1467 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1468 netdev_features_t features) 1469 { 1470 struct rtl8169_private *tp = netdev_priv(dev); 1471 1472 if (dev->mtu > TD_MSS_MAX) 1473 features &= ~NETIF_F_ALL_TSO; 1474 1475 if (dev->mtu > ETH_DATA_LEN && 1476 tp->mac_version > RTL_GIGA_MAC_VER_06) 1477 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1478 1479 return features; 1480 } 1481 1482 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1483 netdev_features_t features) 1484 { 1485 u32 rx_config = RTL_R32(tp, RxConfig); 1486 1487 if (features & NETIF_F_RXALL) 1488 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1489 else 1490 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1491 1492 if (rtl_is_8125(tp)) { 1493 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1494 rx_config |= RX_VLAN_8125; 1495 else 1496 rx_config &= ~RX_VLAN_8125; 1497 } 1498 1499 RTL_W32(tp, RxConfig, rx_config); 1500 } 1501 1502 static int rtl8169_set_features(struct net_device *dev, 1503 netdev_features_t features) 1504 { 1505 struct rtl8169_private *tp = netdev_priv(dev); 1506 1507 rtl_lock_work(tp); 1508 1509 rtl_set_rx_config_features(tp, features); 1510 1511 if (features & NETIF_F_RXCSUM) 1512 tp->cp_cmd |= RxChkSum; 1513 else 1514 tp->cp_cmd &= ~RxChkSum; 1515 1516 if (!rtl_is_8125(tp)) { 1517 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1518 tp->cp_cmd |= RxVlan; 1519 else 1520 tp->cp_cmd &= ~RxVlan; 1521 } 1522 1523 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1524 rtl_pci_commit(tp); 1525 1526 rtl_unlock_work(tp); 1527 1528 return 0; 1529 } 1530 1531 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1532 { 1533 return (skb_vlan_tag_present(skb)) ? 1534 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1535 } 1536 1537 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1538 { 1539 u32 opts2 = le32_to_cpu(desc->opts2); 1540 1541 if (opts2 & RxVlanTag) 1542 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1543 } 1544 1545 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1546 void *p) 1547 { 1548 struct rtl8169_private *tp = netdev_priv(dev); 1549 u32 __iomem *data = tp->mmio_addr; 1550 u32 *dw = p; 1551 int i; 1552 1553 rtl_lock_work(tp); 1554 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1555 memcpy_fromio(dw++, data++, 4); 1556 rtl_unlock_work(tp); 1557 } 1558 1559 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1560 "tx_packets", 1561 "rx_packets", 1562 "tx_errors", 1563 "rx_errors", 1564 "rx_missed", 1565 "align_errors", 1566 "tx_single_collisions", 1567 "tx_multi_collisions", 1568 "unicast", 1569 "broadcast", 1570 "multicast", 1571 "tx_aborted", 1572 "tx_underrun", 1573 }; 1574 1575 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1576 { 1577 switch (sset) { 1578 case ETH_SS_STATS: 1579 return ARRAY_SIZE(rtl8169_gstrings); 1580 default: 1581 return -EOPNOTSUPP; 1582 } 1583 } 1584 1585 DECLARE_RTL_COND(rtl_counters_cond) 1586 { 1587 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1588 } 1589 1590 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1591 { 1592 dma_addr_t paddr = tp->counters_phys_addr; 1593 u32 cmd; 1594 1595 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1596 rtl_pci_commit(tp); 1597 cmd = (u64)paddr & DMA_BIT_MASK(32); 1598 RTL_W32(tp, CounterAddrLow, cmd); 1599 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1600 1601 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1602 } 1603 1604 static void rtl8169_reset_counters(struct rtl8169_private *tp) 1605 { 1606 /* 1607 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1608 * tally counters. 1609 */ 1610 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) 1611 rtl8169_do_counters(tp, CounterReset); 1612 } 1613 1614 static void rtl8169_update_counters(struct rtl8169_private *tp) 1615 { 1616 u8 val = RTL_R8(tp, ChipCmd); 1617 1618 /* 1619 * Some chips are unable to dump tally counters when the receiver 1620 * is disabled. If 0xff chip may be in a PCI power-save state. 1621 */ 1622 if (val & CmdRxEnb && val != 0xff) 1623 rtl8169_do_counters(tp, CounterDump); 1624 } 1625 1626 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1627 { 1628 struct rtl8169_counters *counters = tp->counters; 1629 1630 /* 1631 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1632 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1633 * reset by a power cycle, while the counter values collected by the 1634 * driver are reset at every driver unload/load cycle. 1635 * 1636 * To make sure the HW values returned by @get_stats64 match the SW 1637 * values, we collect the initial values at first open(*) and use them 1638 * as offsets to normalize the values returned by @get_stats64. 1639 * 1640 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1641 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1642 * set at open time by rtl_hw_start. 1643 */ 1644 1645 if (tp->tc_offset.inited) 1646 return; 1647 1648 rtl8169_reset_counters(tp); 1649 rtl8169_update_counters(tp); 1650 1651 tp->tc_offset.tx_errors = counters->tx_errors; 1652 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1653 tp->tc_offset.tx_aborted = counters->tx_aborted; 1654 tp->tc_offset.rx_missed = counters->rx_missed; 1655 tp->tc_offset.inited = true; 1656 } 1657 1658 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1659 struct ethtool_stats *stats, u64 *data) 1660 { 1661 struct rtl8169_private *tp = netdev_priv(dev); 1662 struct device *d = tp_to_dev(tp); 1663 struct rtl8169_counters *counters = tp->counters; 1664 1665 ASSERT_RTNL(); 1666 1667 pm_runtime_get_noresume(d); 1668 1669 if (pm_runtime_active(d)) 1670 rtl8169_update_counters(tp); 1671 1672 pm_runtime_put_noidle(d); 1673 1674 data[0] = le64_to_cpu(counters->tx_packets); 1675 data[1] = le64_to_cpu(counters->rx_packets); 1676 data[2] = le64_to_cpu(counters->tx_errors); 1677 data[3] = le32_to_cpu(counters->rx_errors); 1678 data[4] = le16_to_cpu(counters->rx_missed); 1679 data[5] = le16_to_cpu(counters->align_errors); 1680 data[6] = le32_to_cpu(counters->tx_one_collision); 1681 data[7] = le32_to_cpu(counters->tx_multi_collision); 1682 data[8] = le64_to_cpu(counters->rx_unicast); 1683 data[9] = le64_to_cpu(counters->rx_broadcast); 1684 data[10] = le32_to_cpu(counters->rx_multicast); 1685 data[11] = le16_to_cpu(counters->tx_aborted); 1686 data[12] = le16_to_cpu(counters->tx_underun); 1687 } 1688 1689 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1690 { 1691 switch(stringset) { 1692 case ETH_SS_STATS: 1693 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1694 break; 1695 } 1696 } 1697 1698 /* 1699 * Interrupt coalescing 1700 * 1701 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1702 * > 8169, 8168 and 810x line of chipsets 1703 * 1704 * 8169, 8168, and 8136(810x) serial chipsets support it. 1705 * 1706 * > 2 - the Tx timer unit at gigabit speed 1707 * 1708 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1709 * (0xe0) bit 1 and bit 0. 1710 * 1711 * For 8169 1712 * bit[1:0] \ speed 1000M 100M 10M 1713 * 0 0 320ns 2.56us 40.96us 1714 * 0 1 2.56us 20.48us 327.7us 1715 * 1 0 5.12us 40.96us 655.4us 1716 * 1 1 10.24us 81.92us 1.31ms 1717 * 1718 * For the other 1719 * bit[1:0] \ speed 1000M 100M 10M 1720 * 0 0 5us 2.56us 40.96us 1721 * 0 1 40us 20.48us 327.7us 1722 * 1 0 80us 40.96us 655.4us 1723 * 1 1 160us 81.92us 1.31ms 1724 */ 1725 1726 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1727 struct rtl_coalesce_info { 1728 u32 speed; 1729 u32 scale_nsecs[4]; 1730 }; 1731 1732 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1733 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1734 1735 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1736 { SPEED_10, COALESCE_DELAY(40960) }, 1737 { SPEED_100, COALESCE_DELAY(2560) }, 1738 { SPEED_1000, COALESCE_DELAY(320) }, 1739 { 0 }, 1740 }; 1741 1742 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1743 { SPEED_10, COALESCE_DELAY(40960) }, 1744 { SPEED_100, COALESCE_DELAY(2560) }, 1745 { SPEED_1000, COALESCE_DELAY(5000) }, 1746 { 0 }, 1747 }; 1748 #undef COALESCE_DELAY 1749 1750 /* get rx/tx scale vector corresponding to current speed */ 1751 static const struct rtl_coalesce_info * 1752 rtl_coalesce_info(struct rtl8169_private *tp) 1753 { 1754 const struct rtl_coalesce_info *ci; 1755 1756 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1757 ci = rtl_coalesce_info_8169; 1758 else 1759 ci = rtl_coalesce_info_8168_8136; 1760 1761 for (; ci->speed; ci++) { 1762 if (tp->phydev->speed == ci->speed) 1763 return ci; 1764 } 1765 1766 return ERR_PTR(-ELNRNG); 1767 } 1768 1769 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1770 { 1771 struct rtl8169_private *tp = netdev_priv(dev); 1772 const struct rtl_coalesce_info *ci; 1773 u32 scale, c_us, c_fr; 1774 u16 intrmit; 1775 1776 if (rtl_is_8125(tp)) 1777 return -EOPNOTSUPP; 1778 1779 memset(ec, 0, sizeof(*ec)); 1780 1781 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1782 ci = rtl_coalesce_info(tp); 1783 if (IS_ERR(ci)) 1784 return PTR_ERR(ci); 1785 1786 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1787 1788 intrmit = RTL_R16(tp, IntrMitigate); 1789 1790 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1791 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1792 1793 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1794 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1795 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1796 1797 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1798 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1799 1800 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1801 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1802 1803 return 0; 1804 } 1805 1806 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1807 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1808 u16 *cp01) 1809 { 1810 const struct rtl_coalesce_info *ci; 1811 u16 i; 1812 1813 ci = rtl_coalesce_info(tp); 1814 if (IS_ERR(ci)) 1815 return PTR_ERR(ci); 1816 1817 for (i = 0; i < 4; i++) { 1818 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1819 *cp01 = i; 1820 return ci->scale_nsecs[i]; 1821 } 1822 } 1823 1824 return -ERANGE; 1825 } 1826 1827 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1828 { 1829 struct rtl8169_private *tp = netdev_priv(dev); 1830 u32 tx_fr = ec->tx_max_coalesced_frames; 1831 u32 rx_fr = ec->rx_max_coalesced_frames; 1832 u32 coal_usec_max, units; 1833 u16 w = 0, cp01 = 0; 1834 int scale; 1835 1836 if (rtl_is_8125(tp)) 1837 return -EOPNOTSUPP; 1838 1839 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1840 return -ERANGE; 1841 1842 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1843 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1844 if (scale < 0) 1845 return scale; 1846 1847 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1848 * not only when usecs=0 because of e.g. the following scenario: 1849 * 1850 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1851 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1852 * - then user does `ethtool -C eth0 rx-usecs 100` 1853 * 1854 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1855 * if we want to ignore rx_frames then it has to be set to 0. 1856 */ 1857 if (rx_fr == 1) 1858 rx_fr = 0; 1859 if (tx_fr == 1) 1860 tx_fr = 0; 1861 1862 /* HW requires time limit to be set if frame limit is set */ 1863 if ((tx_fr && !ec->tx_coalesce_usecs) || 1864 (rx_fr && !ec->rx_coalesce_usecs)) 1865 return -EINVAL; 1866 1867 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1868 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1869 1870 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1871 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1872 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1873 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1874 1875 rtl_lock_work(tp); 1876 1877 RTL_W16(tp, IntrMitigate, w); 1878 1879 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1880 if (rtl_is_8168evl_up(tp)) { 1881 if (!rx_fr && !tx_fr) 1882 /* disable packet counter */ 1883 tp->cp_cmd |= PktCntrDisable; 1884 else 1885 tp->cp_cmd &= ~PktCntrDisable; 1886 } 1887 1888 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1889 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1890 rtl_pci_commit(tp); 1891 1892 rtl_unlock_work(tp); 1893 1894 return 0; 1895 } 1896 1897 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1898 { 1899 struct rtl8169_private *tp = netdev_priv(dev); 1900 struct device *d = tp_to_dev(tp); 1901 int ret; 1902 1903 if (!rtl_supports_eee(tp)) 1904 return -EOPNOTSUPP; 1905 1906 pm_runtime_get_noresume(d); 1907 1908 if (!pm_runtime_active(d)) { 1909 ret = -EOPNOTSUPP; 1910 } else { 1911 ret = phy_ethtool_get_eee(tp->phydev, data); 1912 } 1913 1914 pm_runtime_put_noidle(d); 1915 1916 return ret; 1917 } 1918 1919 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1920 { 1921 struct rtl8169_private *tp = netdev_priv(dev); 1922 struct device *d = tp_to_dev(tp); 1923 int ret; 1924 1925 if (!rtl_supports_eee(tp)) 1926 return -EOPNOTSUPP; 1927 1928 pm_runtime_get_noresume(d); 1929 1930 if (!pm_runtime_active(d)) { 1931 ret = -EOPNOTSUPP; 1932 goto out; 1933 } 1934 1935 ret = phy_ethtool_set_eee(tp->phydev, data); 1936 1937 if (!ret) 1938 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1939 MDIO_AN_EEE_ADV); 1940 out: 1941 pm_runtime_put_noidle(d); 1942 return ret; 1943 } 1944 1945 static const struct ethtool_ops rtl8169_ethtool_ops = { 1946 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1947 ETHTOOL_COALESCE_MAX_FRAMES, 1948 .get_drvinfo = rtl8169_get_drvinfo, 1949 .get_regs_len = rtl8169_get_regs_len, 1950 .get_link = ethtool_op_get_link, 1951 .get_coalesce = rtl_get_coalesce, 1952 .set_coalesce = rtl_set_coalesce, 1953 .get_regs = rtl8169_get_regs, 1954 .get_wol = rtl8169_get_wol, 1955 .set_wol = rtl8169_set_wol, 1956 .get_strings = rtl8169_get_strings, 1957 .get_sset_count = rtl8169_get_sset_count, 1958 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1959 .get_ts_info = ethtool_op_get_ts_info, 1960 .nway_reset = phy_ethtool_nway_reset, 1961 .get_eee = rtl8169_get_eee, 1962 .set_eee = rtl8169_set_eee, 1963 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1964 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1965 }; 1966 1967 static void rtl_enable_eee(struct rtl8169_private *tp) 1968 { 1969 struct phy_device *phydev = tp->phydev; 1970 int adv; 1971 1972 /* respect EEE advertisement the user may have set */ 1973 if (tp->eee_adv >= 0) 1974 adv = tp->eee_adv; 1975 else 1976 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1977 1978 if (adv >= 0) 1979 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1980 } 1981 1982 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1983 { 1984 /* 1985 * The driver currently handles the 8168Bf and the 8168Be identically 1986 * but they can be identified more specifically through the test below 1987 * if needed: 1988 * 1989 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1990 * 1991 * Same thing for the 8101Eb and the 8101Ec: 1992 * 1993 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1994 */ 1995 static const struct rtl_mac_info { 1996 u16 mask; 1997 u16 val; 1998 enum mac_version ver; 1999 } mac_info[] = { 2000 /* 8125 family. */ 2001 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2002 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2003 2004 /* RTL8117 */ 2005 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2006 2007 /* 8168EP family. */ 2008 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2009 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2010 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2011 2012 /* 8168H family. */ 2013 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2014 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2015 2016 /* 8168G family. */ 2017 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2018 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2019 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2020 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2021 2022 /* 8168F family. */ 2023 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2024 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2025 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2026 2027 /* 8168E family. */ 2028 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2029 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2030 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2031 2032 /* 8168D family. */ 2033 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2034 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2035 2036 /* 8168DP family. */ 2037 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2038 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2039 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2040 2041 /* 8168C family. */ 2042 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2043 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2044 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2045 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2046 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2047 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2048 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2049 2050 /* 8168B family. */ 2051 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2052 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2053 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2054 2055 /* 8101 family. */ 2056 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2057 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2058 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2059 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2060 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2061 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2062 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2063 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2064 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2065 /* RTL8401, reportedly works if treated as RTL8101e */ 2066 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_13 }, 2067 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2068 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2069 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2070 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2071 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2072 /* FIXME: where did these entries come from ? -- FR */ 2073 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2074 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2075 2076 /* 8110 family. */ 2077 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2078 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2079 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2080 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2081 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2082 2083 /* Catch-all */ 2084 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2085 }; 2086 const struct rtl_mac_info *p = mac_info; 2087 enum mac_version ver; 2088 2089 while ((xid & p->mask) != p->val) 2090 p++; 2091 ver = p->ver; 2092 2093 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2094 if (ver == RTL_GIGA_MAC_VER_42) 2095 ver = RTL_GIGA_MAC_VER_43; 2096 else if (ver == RTL_GIGA_MAC_VER_45) 2097 ver = RTL_GIGA_MAC_VER_47; 2098 else if (ver == RTL_GIGA_MAC_VER_46) 2099 ver = RTL_GIGA_MAC_VER_48; 2100 } 2101 2102 return ver; 2103 } 2104 2105 static void rtl_release_firmware(struct rtl8169_private *tp) 2106 { 2107 if (tp->rtl_fw) { 2108 rtl_fw_release_firmware(tp->rtl_fw); 2109 kfree(tp->rtl_fw); 2110 tp->rtl_fw = NULL; 2111 } 2112 } 2113 2114 void r8169_apply_firmware(struct rtl8169_private *tp) 2115 { 2116 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2117 if (tp->rtl_fw) { 2118 rtl_fw_write_firmware(tp, tp->rtl_fw); 2119 /* At least one firmware doesn't reset tp->ocp_base. */ 2120 tp->ocp_base = OCP_STD_PHY_BASE; 2121 } 2122 } 2123 2124 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2125 { 2126 /* Adjust EEE LED frequency */ 2127 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2128 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2129 2130 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2131 } 2132 2133 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2134 { 2135 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2136 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2137 } 2138 2139 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2140 { 2141 const u16 w[] = { 2142 addr[0] | (addr[1] << 8), 2143 addr[2] | (addr[3] << 8), 2144 addr[4] | (addr[5] << 8) 2145 }; 2146 2147 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2148 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2149 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2150 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2151 } 2152 2153 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2154 { 2155 u16 data1, data2, ioffset; 2156 2157 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2158 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2159 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2160 2161 ioffset = (data2 >> 1) & 0x7ff8; 2162 ioffset |= data2 & 0x0007; 2163 if (data1 & BIT(7)) 2164 ioffset |= BIT(15); 2165 2166 return ioffset; 2167 } 2168 2169 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2170 { 2171 set_bit(flag, tp->wk.flags); 2172 schedule_work(&tp->wk.work); 2173 } 2174 2175 static void rtl8169_init_phy(struct rtl8169_private *tp) 2176 { 2177 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2178 2179 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2180 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2181 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2182 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2183 RTL_W8(tp, 0x82, 0x01); 2184 } 2185 2186 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2187 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2188 tp->pci_dev->subsystem_device == 0xe000) 2189 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2190 2191 /* We may have called phy_speed_down before */ 2192 phy_speed_up(tp->phydev); 2193 2194 if (rtl_supports_eee(tp)) 2195 rtl_enable_eee(tp); 2196 2197 genphy_soft_reset(tp->phydev); 2198 } 2199 2200 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2201 { 2202 rtl_lock_work(tp); 2203 2204 rtl_unlock_config_regs(tp); 2205 2206 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2207 rtl_pci_commit(tp); 2208 2209 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2210 rtl_pci_commit(tp); 2211 2212 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2213 rtl_rar_exgmac_set(tp, addr); 2214 2215 rtl_lock_config_regs(tp); 2216 2217 rtl_unlock_work(tp); 2218 } 2219 2220 static int rtl_set_mac_address(struct net_device *dev, void *p) 2221 { 2222 struct rtl8169_private *tp = netdev_priv(dev); 2223 struct device *d = tp_to_dev(tp); 2224 int ret; 2225 2226 ret = eth_mac_addr(dev, p); 2227 if (ret) 2228 return ret; 2229 2230 pm_runtime_get_noresume(d); 2231 2232 if (pm_runtime_active(d)) 2233 rtl_rar_set(tp, dev->dev_addr); 2234 2235 pm_runtime_put_noidle(d); 2236 2237 return 0; 2238 } 2239 2240 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2241 { 2242 switch (tp->mac_version) { 2243 case RTL_GIGA_MAC_VER_25: 2244 case RTL_GIGA_MAC_VER_26: 2245 case RTL_GIGA_MAC_VER_29: 2246 case RTL_GIGA_MAC_VER_30: 2247 case RTL_GIGA_MAC_VER_32: 2248 case RTL_GIGA_MAC_VER_33: 2249 case RTL_GIGA_MAC_VER_34: 2250 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61: 2251 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2252 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2253 break; 2254 default: 2255 break; 2256 } 2257 } 2258 2259 static void rtl_pll_power_down(struct rtl8169_private *tp) 2260 { 2261 if (r8168_check_dash(tp)) 2262 return; 2263 2264 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2265 tp->mac_version == RTL_GIGA_MAC_VER_33) 2266 rtl_ephy_write(tp, 0x19, 0xff64); 2267 2268 if (device_may_wakeup(tp_to_dev(tp))) { 2269 phy_speed_down(tp->phydev, false); 2270 rtl_wol_suspend_quirk(tp); 2271 return; 2272 } 2273 2274 switch (tp->mac_version) { 2275 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2276 case RTL_GIGA_MAC_VER_37: 2277 case RTL_GIGA_MAC_VER_39: 2278 case RTL_GIGA_MAC_VER_43: 2279 case RTL_GIGA_MAC_VER_44: 2280 case RTL_GIGA_MAC_VER_45: 2281 case RTL_GIGA_MAC_VER_46: 2282 case RTL_GIGA_MAC_VER_47: 2283 case RTL_GIGA_MAC_VER_48: 2284 case RTL_GIGA_MAC_VER_50: 2285 case RTL_GIGA_MAC_VER_51: 2286 case RTL_GIGA_MAC_VER_52: 2287 case RTL_GIGA_MAC_VER_60: 2288 case RTL_GIGA_MAC_VER_61: 2289 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2290 break; 2291 case RTL_GIGA_MAC_VER_40: 2292 case RTL_GIGA_MAC_VER_41: 2293 case RTL_GIGA_MAC_VER_49: 2294 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 2295 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2296 break; 2297 default: 2298 break; 2299 } 2300 } 2301 2302 static void rtl_pll_power_up(struct rtl8169_private *tp) 2303 { 2304 switch (tp->mac_version) { 2305 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2306 case RTL_GIGA_MAC_VER_37: 2307 case RTL_GIGA_MAC_VER_39: 2308 case RTL_GIGA_MAC_VER_43: 2309 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2310 break; 2311 case RTL_GIGA_MAC_VER_44: 2312 case RTL_GIGA_MAC_VER_45: 2313 case RTL_GIGA_MAC_VER_46: 2314 case RTL_GIGA_MAC_VER_47: 2315 case RTL_GIGA_MAC_VER_48: 2316 case RTL_GIGA_MAC_VER_50: 2317 case RTL_GIGA_MAC_VER_51: 2318 case RTL_GIGA_MAC_VER_52: 2319 case RTL_GIGA_MAC_VER_60: 2320 case RTL_GIGA_MAC_VER_61: 2321 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2322 break; 2323 case RTL_GIGA_MAC_VER_40: 2324 case RTL_GIGA_MAC_VER_41: 2325 case RTL_GIGA_MAC_VER_49: 2326 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2327 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 2328 break; 2329 default: 2330 break; 2331 } 2332 2333 phy_resume(tp->phydev); 2334 } 2335 2336 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2337 { 2338 switch (tp->mac_version) { 2339 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2340 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2341 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2342 break; 2343 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2344 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2345 case RTL_GIGA_MAC_VER_38: 2346 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2347 break; 2348 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2349 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2350 break; 2351 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2352 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2353 break; 2354 default: 2355 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2356 break; 2357 } 2358 } 2359 2360 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2361 { 2362 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2363 } 2364 2365 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2366 { 2367 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2368 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2369 } 2370 2371 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2372 { 2373 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2374 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2375 } 2376 2377 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2378 { 2379 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2380 } 2381 2382 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2383 { 2384 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2385 } 2386 2387 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2388 { 2389 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2390 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2391 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2392 } 2393 2394 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2395 { 2396 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2397 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2398 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2399 } 2400 2401 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2402 { 2403 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2404 } 2405 2406 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2407 { 2408 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2409 } 2410 2411 static void rtl_jumbo_config(struct rtl8169_private *tp) 2412 { 2413 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2414 2415 rtl_unlock_config_regs(tp); 2416 switch (tp->mac_version) { 2417 case RTL_GIGA_MAC_VER_12: 2418 case RTL_GIGA_MAC_VER_17: 2419 if (jumbo) { 2420 pcie_set_readrq(tp->pci_dev, 512); 2421 r8168b_1_hw_jumbo_enable(tp); 2422 } else { 2423 r8168b_1_hw_jumbo_disable(tp); 2424 } 2425 break; 2426 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2427 if (jumbo) { 2428 pcie_set_readrq(tp->pci_dev, 512); 2429 r8168c_hw_jumbo_enable(tp); 2430 } else { 2431 r8168c_hw_jumbo_disable(tp); 2432 } 2433 break; 2434 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2435 if (jumbo) 2436 r8168dp_hw_jumbo_enable(tp); 2437 else 2438 r8168dp_hw_jumbo_disable(tp); 2439 break; 2440 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2441 if (jumbo) { 2442 pcie_set_readrq(tp->pci_dev, 512); 2443 r8168e_hw_jumbo_enable(tp); 2444 } else { 2445 r8168e_hw_jumbo_disable(tp); 2446 } 2447 break; 2448 default: 2449 break; 2450 } 2451 rtl_lock_config_regs(tp); 2452 2453 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2454 pcie_set_readrq(tp->pci_dev, 4096); 2455 } 2456 2457 DECLARE_RTL_COND(rtl_chipcmd_cond) 2458 { 2459 return RTL_R8(tp, ChipCmd) & CmdReset; 2460 } 2461 2462 static void rtl_hw_reset(struct rtl8169_private *tp) 2463 { 2464 RTL_W8(tp, ChipCmd, CmdReset); 2465 2466 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2467 } 2468 2469 static void rtl_request_firmware(struct rtl8169_private *tp) 2470 { 2471 struct rtl_fw *rtl_fw; 2472 2473 /* firmware loaded already or no firmware available */ 2474 if (tp->rtl_fw || !tp->fw_name) 2475 return; 2476 2477 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2478 if (!rtl_fw) 2479 return; 2480 2481 rtl_fw->phy_write = rtl_writephy; 2482 rtl_fw->phy_read = rtl_readphy; 2483 rtl_fw->mac_mcu_write = mac_mcu_write; 2484 rtl_fw->mac_mcu_read = mac_mcu_read; 2485 rtl_fw->fw_name = tp->fw_name; 2486 rtl_fw->dev = tp_to_dev(tp); 2487 2488 if (rtl_fw_request_firmware(rtl_fw)) 2489 kfree(rtl_fw); 2490 else 2491 tp->rtl_fw = rtl_fw; 2492 } 2493 2494 static void rtl_rx_close(struct rtl8169_private *tp) 2495 { 2496 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2497 } 2498 2499 DECLARE_RTL_COND(rtl_npq_cond) 2500 { 2501 return RTL_R8(tp, TxPoll) & NPQ; 2502 } 2503 2504 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2505 { 2506 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2507 } 2508 2509 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2510 { 2511 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2512 } 2513 2514 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2515 { 2516 switch (tp->mac_version) { 2517 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2518 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2519 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2520 break; 2521 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2522 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2523 break; 2524 default: 2525 break; 2526 } 2527 } 2528 2529 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2530 { 2531 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2532 fsleep(2000); 2533 rtl_wait_txrx_fifo_empty(tp); 2534 } 2535 2536 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2537 { 2538 u32 val = TX_DMA_BURST << TxDMAShift | 2539 InterFrameGap << TxInterFrameGapShift; 2540 2541 if (rtl_is_8168evl_up(tp)) 2542 val |= TXCFG_AUTO_FIFO; 2543 2544 RTL_W32(tp, TxConfig, val); 2545 } 2546 2547 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2548 { 2549 /* Low hurts. Let's disable the filtering. */ 2550 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2551 } 2552 2553 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2554 { 2555 /* 2556 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2557 * register to be written before TxDescAddrLow to work. 2558 * Switching from MMIO to I/O access fixes the issue as well. 2559 */ 2560 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2561 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2562 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2563 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2564 } 2565 2566 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2567 { 2568 u32 val; 2569 2570 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2571 val = 0x000fff00; 2572 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2573 val = 0x00ffff00; 2574 else 2575 return; 2576 2577 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2578 val |= 0xff; 2579 2580 RTL_W32(tp, 0x7c, val); 2581 } 2582 2583 static void rtl_set_rx_mode(struct net_device *dev) 2584 { 2585 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2586 /* Multicast hash filter */ 2587 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2588 struct rtl8169_private *tp = netdev_priv(dev); 2589 u32 tmp; 2590 2591 if (dev->flags & IFF_PROMISC) { 2592 rx_mode |= AcceptAllPhys; 2593 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2594 dev->flags & IFF_ALLMULTI || 2595 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2596 /* accept all multicasts */ 2597 } else if (netdev_mc_empty(dev)) { 2598 rx_mode &= ~AcceptMulticast; 2599 } else { 2600 struct netdev_hw_addr *ha; 2601 2602 mc_filter[1] = mc_filter[0] = 0; 2603 netdev_for_each_mc_addr(ha, dev) { 2604 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2605 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2606 } 2607 2608 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2609 tmp = mc_filter[0]; 2610 mc_filter[0] = swab32(mc_filter[1]); 2611 mc_filter[1] = swab32(tmp); 2612 } 2613 } 2614 2615 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2616 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2617 2618 tmp = RTL_R32(tp, RxConfig); 2619 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2620 } 2621 2622 DECLARE_RTL_COND(rtl_csiar_cond) 2623 { 2624 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2625 } 2626 2627 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2628 { 2629 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2630 2631 RTL_W32(tp, CSIDR, value); 2632 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2633 CSIAR_BYTE_ENABLE | func << 16); 2634 2635 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2636 } 2637 2638 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2639 { 2640 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2641 2642 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2643 CSIAR_BYTE_ENABLE); 2644 2645 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2646 RTL_R32(tp, CSIDR) : ~0; 2647 } 2648 2649 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2650 { 2651 struct pci_dev *pdev = tp->pci_dev; 2652 u32 csi; 2653 2654 /* According to Realtek the value at config space address 0x070f 2655 * controls the L0s/L1 entrance latency. We try standard ECAM access 2656 * first and if it fails fall back to CSI. 2657 */ 2658 if (pdev->cfg_size > 0x070f && 2659 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2660 return; 2661 2662 netdev_notice_once(tp->dev, 2663 "No native access to PCI extended config space, falling back to CSI\n"); 2664 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2665 rtl_csi_write(tp, 0x070c, csi | val << 24); 2666 } 2667 2668 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2669 { 2670 rtl_csi_access_enable(tp, 0x27); 2671 } 2672 2673 struct ephy_info { 2674 unsigned int offset; 2675 u16 mask; 2676 u16 bits; 2677 }; 2678 2679 static void __rtl_ephy_init(struct rtl8169_private *tp, 2680 const struct ephy_info *e, int len) 2681 { 2682 u16 w; 2683 2684 while (len-- > 0) { 2685 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2686 rtl_ephy_write(tp, e->offset, w); 2687 e++; 2688 } 2689 } 2690 2691 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2692 2693 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2694 { 2695 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2696 PCI_EXP_LNKCTL_CLKREQ_EN); 2697 } 2698 2699 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2700 { 2701 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2702 PCI_EXP_LNKCTL_CLKREQ_EN); 2703 } 2704 2705 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2706 { 2707 /* work around an issue when PCI reset occurs during L2/L3 state */ 2708 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2709 } 2710 2711 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2712 { 2713 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2714 if (enable && tp->aspm_manageable) { 2715 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2716 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2717 } else { 2718 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2719 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2720 } 2721 2722 udelay(10); 2723 } 2724 2725 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2726 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2727 { 2728 /* Usage of dynamic vs. static FIFO is controlled by bit 2729 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2730 */ 2731 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2732 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2733 } 2734 2735 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2736 u8 low, u8 high) 2737 { 2738 /* FIFO thresholds for pause flow control */ 2739 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2740 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2741 } 2742 2743 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2744 { 2745 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2746 } 2747 2748 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2749 { 2750 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2751 2752 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2753 2754 rtl_disable_clock_request(tp); 2755 } 2756 2757 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2758 { 2759 static const struct ephy_info e_info_8168cp[] = { 2760 { 0x01, 0, 0x0001 }, 2761 { 0x02, 0x0800, 0x1000 }, 2762 { 0x03, 0, 0x0042 }, 2763 { 0x06, 0x0080, 0x0000 }, 2764 { 0x07, 0, 0x2000 } 2765 }; 2766 2767 rtl_set_def_aspm_entry_latency(tp); 2768 2769 rtl_ephy_init(tp, e_info_8168cp); 2770 2771 __rtl_hw_start_8168cp(tp); 2772 } 2773 2774 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2775 { 2776 rtl_set_def_aspm_entry_latency(tp); 2777 2778 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2779 } 2780 2781 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2782 { 2783 rtl_set_def_aspm_entry_latency(tp); 2784 2785 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2786 2787 /* Magic. */ 2788 RTL_W8(tp, DBG_REG, 0x20); 2789 } 2790 2791 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2792 { 2793 static const struct ephy_info e_info_8168c_1[] = { 2794 { 0x02, 0x0800, 0x1000 }, 2795 { 0x03, 0, 0x0002 }, 2796 { 0x06, 0x0080, 0x0000 } 2797 }; 2798 2799 rtl_set_def_aspm_entry_latency(tp); 2800 2801 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2802 2803 rtl_ephy_init(tp, e_info_8168c_1); 2804 2805 __rtl_hw_start_8168cp(tp); 2806 } 2807 2808 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2809 { 2810 static const struct ephy_info e_info_8168c_2[] = { 2811 { 0x01, 0, 0x0001 }, 2812 { 0x03, 0x0400, 0x0020 } 2813 }; 2814 2815 rtl_set_def_aspm_entry_latency(tp); 2816 2817 rtl_ephy_init(tp, e_info_8168c_2); 2818 2819 __rtl_hw_start_8168cp(tp); 2820 } 2821 2822 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2823 { 2824 rtl_hw_start_8168c_2(tp); 2825 } 2826 2827 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2828 { 2829 rtl_set_def_aspm_entry_latency(tp); 2830 2831 __rtl_hw_start_8168cp(tp); 2832 } 2833 2834 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2835 { 2836 rtl_set_def_aspm_entry_latency(tp); 2837 2838 rtl_disable_clock_request(tp); 2839 } 2840 2841 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2842 { 2843 static const struct ephy_info e_info_8168d_4[] = { 2844 { 0x0b, 0x0000, 0x0048 }, 2845 { 0x19, 0x0020, 0x0050 }, 2846 { 0x0c, 0x0100, 0x0020 }, 2847 { 0x10, 0x0004, 0x0000 }, 2848 }; 2849 2850 rtl_set_def_aspm_entry_latency(tp); 2851 2852 rtl_ephy_init(tp, e_info_8168d_4); 2853 2854 rtl_enable_clock_request(tp); 2855 } 2856 2857 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2858 { 2859 static const struct ephy_info e_info_8168e_1[] = { 2860 { 0x00, 0x0200, 0x0100 }, 2861 { 0x00, 0x0000, 0x0004 }, 2862 { 0x06, 0x0002, 0x0001 }, 2863 { 0x06, 0x0000, 0x0030 }, 2864 { 0x07, 0x0000, 0x2000 }, 2865 { 0x00, 0x0000, 0x0020 }, 2866 { 0x03, 0x5800, 0x2000 }, 2867 { 0x03, 0x0000, 0x0001 }, 2868 { 0x01, 0x0800, 0x1000 }, 2869 { 0x07, 0x0000, 0x4000 }, 2870 { 0x1e, 0x0000, 0x2000 }, 2871 { 0x19, 0xffff, 0xfe6c }, 2872 { 0x0a, 0x0000, 0x0040 } 2873 }; 2874 2875 rtl_set_def_aspm_entry_latency(tp); 2876 2877 rtl_ephy_init(tp, e_info_8168e_1); 2878 2879 rtl_disable_clock_request(tp); 2880 2881 /* Reset tx FIFO pointer */ 2882 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2883 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2884 2885 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2886 } 2887 2888 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2889 { 2890 static const struct ephy_info e_info_8168e_2[] = { 2891 { 0x09, 0x0000, 0x0080 }, 2892 { 0x19, 0x0000, 0x0224 }, 2893 { 0x00, 0x0000, 0x0004 }, 2894 { 0x0c, 0x3df0, 0x0200 }, 2895 }; 2896 2897 rtl_set_def_aspm_entry_latency(tp); 2898 2899 rtl_ephy_init(tp, e_info_8168e_2); 2900 2901 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2902 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2903 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2904 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2905 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2906 rtl_reset_packet_filter(tp); 2907 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2908 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2909 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2910 2911 rtl_disable_clock_request(tp); 2912 2913 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2914 2915 rtl8168_config_eee_mac(tp); 2916 2917 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2918 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2919 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2920 2921 rtl_hw_aspm_clkreq_enable(tp, true); 2922 } 2923 2924 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2925 { 2926 rtl_set_def_aspm_entry_latency(tp); 2927 2928 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2929 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2930 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2931 rtl_reset_packet_filter(tp); 2932 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2933 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2934 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2935 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2936 2937 rtl_disable_clock_request(tp); 2938 2939 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2940 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2941 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2942 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2943 2944 rtl8168_config_eee_mac(tp); 2945 } 2946 2947 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2948 { 2949 static const struct ephy_info e_info_8168f_1[] = { 2950 { 0x06, 0x00c0, 0x0020 }, 2951 { 0x08, 0x0001, 0x0002 }, 2952 { 0x09, 0x0000, 0x0080 }, 2953 { 0x19, 0x0000, 0x0224 }, 2954 { 0x00, 0x0000, 0x0004 }, 2955 { 0x0c, 0x3df0, 0x0200 }, 2956 }; 2957 2958 rtl_hw_start_8168f(tp); 2959 2960 rtl_ephy_init(tp, e_info_8168f_1); 2961 2962 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2963 } 2964 2965 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2966 { 2967 static const struct ephy_info e_info_8168f_1[] = { 2968 { 0x06, 0x00c0, 0x0020 }, 2969 { 0x0f, 0xffff, 0x5200 }, 2970 { 0x19, 0x0000, 0x0224 }, 2971 { 0x00, 0x0000, 0x0004 }, 2972 { 0x0c, 0x3df0, 0x0200 }, 2973 }; 2974 2975 rtl_hw_start_8168f(tp); 2976 rtl_pcie_state_l2l3_disable(tp); 2977 2978 rtl_ephy_init(tp, e_info_8168f_1); 2979 2980 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2981 } 2982 2983 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2984 { 2985 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2986 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2987 2988 rtl_set_def_aspm_entry_latency(tp); 2989 2990 rtl_reset_packet_filter(tp); 2991 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2992 2993 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2994 2995 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2996 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2997 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2998 2999 rtl8168_config_eee_mac(tp); 3000 3001 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3002 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3003 3004 rtl_pcie_state_l2l3_disable(tp); 3005 } 3006 3007 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3008 { 3009 static const struct ephy_info e_info_8168g_1[] = { 3010 { 0x00, 0x0008, 0x0000 }, 3011 { 0x0c, 0x3ff0, 0x0820 }, 3012 { 0x1e, 0x0000, 0x0001 }, 3013 { 0x19, 0x8000, 0x0000 } 3014 }; 3015 3016 rtl_hw_start_8168g(tp); 3017 3018 /* disable aspm and clock request before access ephy */ 3019 rtl_hw_aspm_clkreq_enable(tp, false); 3020 rtl_ephy_init(tp, e_info_8168g_1); 3021 rtl_hw_aspm_clkreq_enable(tp, true); 3022 } 3023 3024 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3025 { 3026 static const struct ephy_info e_info_8168g_2[] = { 3027 { 0x00, 0x0008, 0x0000 }, 3028 { 0x0c, 0x3ff0, 0x0820 }, 3029 { 0x19, 0xffff, 0x7c00 }, 3030 { 0x1e, 0xffff, 0x20eb }, 3031 { 0x0d, 0xffff, 0x1666 }, 3032 { 0x00, 0xffff, 0x10a3 }, 3033 { 0x06, 0xffff, 0xf050 }, 3034 { 0x04, 0x0000, 0x0010 }, 3035 { 0x1d, 0x4000, 0x0000 }, 3036 }; 3037 3038 rtl_hw_start_8168g(tp); 3039 3040 /* disable aspm and clock request before access ephy */ 3041 rtl_hw_aspm_clkreq_enable(tp, false); 3042 rtl_ephy_init(tp, e_info_8168g_2); 3043 } 3044 3045 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3046 { 3047 static const struct ephy_info e_info_8411_2[] = { 3048 { 0x00, 0x0008, 0x0000 }, 3049 { 0x0c, 0x37d0, 0x0820 }, 3050 { 0x1e, 0x0000, 0x0001 }, 3051 { 0x19, 0x8021, 0x0000 }, 3052 { 0x1e, 0x0000, 0x2000 }, 3053 { 0x0d, 0x0100, 0x0200 }, 3054 { 0x00, 0x0000, 0x0080 }, 3055 { 0x06, 0x0000, 0x0010 }, 3056 { 0x04, 0x0000, 0x0010 }, 3057 { 0x1d, 0x0000, 0x4000 }, 3058 }; 3059 3060 rtl_hw_start_8168g(tp); 3061 3062 /* disable aspm and clock request before access ephy */ 3063 rtl_hw_aspm_clkreq_enable(tp, false); 3064 rtl_ephy_init(tp, e_info_8411_2); 3065 3066 /* The following Realtek-provided magic fixes an issue with the RX unit 3067 * getting confused after the PHY having been powered-down. 3068 */ 3069 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3070 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3071 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3072 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3073 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3074 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3075 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3076 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3077 mdelay(3); 3078 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3079 3080 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3081 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3082 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3083 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3084 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3085 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3086 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3087 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3088 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3089 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3090 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3091 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3092 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3093 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3094 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3095 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3096 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3097 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3098 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3099 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3100 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3101 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3102 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3103 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3104 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3105 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3106 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3107 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3108 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3109 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3110 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3111 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3112 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3113 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3114 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3115 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3116 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3117 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3118 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3119 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3120 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3121 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3122 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3123 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3124 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3125 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3126 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3127 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3128 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3129 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3130 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3131 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3132 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3133 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3134 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3135 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3136 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3137 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3138 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3139 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3140 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3141 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3142 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3143 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3144 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3145 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3146 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3147 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3148 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3149 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3150 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3151 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3152 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3153 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3154 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3155 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3156 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3157 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3158 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3159 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3160 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3161 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3162 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3163 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3164 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3165 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3166 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3167 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3168 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3169 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3170 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3171 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3172 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3173 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3174 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3175 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3176 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3177 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3178 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3179 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3180 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3181 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3182 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3183 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3184 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3185 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3186 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3187 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3188 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3189 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3190 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3191 3192 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3193 3194 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3195 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3196 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3197 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3198 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3199 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3200 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3201 3202 rtl_hw_aspm_clkreq_enable(tp, true); 3203 } 3204 3205 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3206 { 3207 static const struct ephy_info e_info_8168h_1[] = { 3208 { 0x1e, 0x0800, 0x0001 }, 3209 { 0x1d, 0x0000, 0x0800 }, 3210 { 0x05, 0xffff, 0x2089 }, 3211 { 0x06, 0xffff, 0x5881 }, 3212 { 0x04, 0xffff, 0x854a }, 3213 { 0x01, 0xffff, 0x068b } 3214 }; 3215 int rg_saw_cnt; 3216 3217 /* disable aspm and clock request before access ephy */ 3218 rtl_hw_aspm_clkreq_enable(tp, false); 3219 rtl_ephy_init(tp, e_info_8168h_1); 3220 3221 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3222 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3223 3224 rtl_set_def_aspm_entry_latency(tp); 3225 3226 rtl_reset_packet_filter(tp); 3227 3228 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3229 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3230 3231 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3232 3233 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3234 3235 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3236 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3237 3238 rtl8168_config_eee_mac(tp); 3239 3240 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3241 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3242 3243 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3244 3245 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3246 3247 rtl_pcie_state_l2l3_disable(tp); 3248 3249 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3250 if (rg_saw_cnt > 0) { 3251 u16 sw_cnt_1ms_ini; 3252 3253 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3254 sw_cnt_1ms_ini &= 0x0fff; 3255 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3256 } 3257 3258 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3259 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3260 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3261 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3262 3263 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3264 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3265 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3266 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3267 3268 rtl_hw_aspm_clkreq_enable(tp, true); 3269 } 3270 3271 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3272 { 3273 rtl8168ep_stop_cmac(tp); 3274 3275 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3276 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3277 3278 rtl_set_def_aspm_entry_latency(tp); 3279 3280 rtl_reset_packet_filter(tp); 3281 3282 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3283 3284 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3285 3286 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3287 3288 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3289 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3290 3291 rtl8168_config_eee_mac(tp); 3292 3293 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3294 3295 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3296 3297 rtl_pcie_state_l2l3_disable(tp); 3298 } 3299 3300 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3301 { 3302 static const struct ephy_info e_info_8168ep_1[] = { 3303 { 0x00, 0xffff, 0x10ab }, 3304 { 0x06, 0xffff, 0xf030 }, 3305 { 0x08, 0xffff, 0x2006 }, 3306 { 0x0d, 0xffff, 0x1666 }, 3307 { 0x0c, 0x3ff0, 0x0000 } 3308 }; 3309 3310 /* disable aspm and clock request before access ephy */ 3311 rtl_hw_aspm_clkreq_enable(tp, false); 3312 rtl_ephy_init(tp, e_info_8168ep_1); 3313 3314 rtl_hw_start_8168ep(tp); 3315 3316 rtl_hw_aspm_clkreq_enable(tp, true); 3317 } 3318 3319 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3320 { 3321 static const struct ephy_info e_info_8168ep_2[] = { 3322 { 0x00, 0xffff, 0x10a3 }, 3323 { 0x19, 0xffff, 0xfc00 }, 3324 { 0x1e, 0xffff, 0x20ea } 3325 }; 3326 3327 /* disable aspm and clock request before access ephy */ 3328 rtl_hw_aspm_clkreq_enable(tp, false); 3329 rtl_ephy_init(tp, e_info_8168ep_2); 3330 3331 rtl_hw_start_8168ep(tp); 3332 3333 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3334 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3335 3336 rtl_hw_aspm_clkreq_enable(tp, true); 3337 } 3338 3339 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3340 { 3341 static const struct ephy_info e_info_8168ep_3[] = { 3342 { 0x00, 0x0000, 0x0080 }, 3343 { 0x0d, 0x0100, 0x0200 }, 3344 { 0x19, 0x8021, 0x0000 }, 3345 { 0x1e, 0x0000, 0x2000 }, 3346 }; 3347 3348 /* disable aspm and clock request before access ephy */ 3349 rtl_hw_aspm_clkreq_enable(tp, false); 3350 rtl_ephy_init(tp, e_info_8168ep_3); 3351 3352 rtl_hw_start_8168ep(tp); 3353 3354 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3355 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3356 3357 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3358 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3359 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3360 3361 rtl_hw_aspm_clkreq_enable(tp, true); 3362 } 3363 3364 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3365 { 3366 static const struct ephy_info e_info_8117[] = { 3367 { 0x19, 0x0040, 0x1100 }, 3368 { 0x59, 0x0040, 0x1100 }, 3369 }; 3370 int rg_saw_cnt; 3371 3372 rtl8168ep_stop_cmac(tp); 3373 3374 /* disable aspm and clock request before access ephy */ 3375 rtl_hw_aspm_clkreq_enable(tp, false); 3376 rtl_ephy_init(tp, e_info_8117); 3377 3378 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3379 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3380 3381 rtl_set_def_aspm_entry_latency(tp); 3382 3383 rtl_reset_packet_filter(tp); 3384 3385 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3386 3387 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3388 3389 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3390 3391 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3392 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3393 3394 rtl8168_config_eee_mac(tp); 3395 3396 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3397 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3398 3399 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3400 3401 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3402 3403 rtl_pcie_state_l2l3_disable(tp); 3404 3405 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3406 if (rg_saw_cnt > 0) { 3407 u16 sw_cnt_1ms_ini; 3408 3409 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3410 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3411 } 3412 3413 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3414 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3415 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3416 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3417 3418 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3419 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3420 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3421 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3422 3423 /* firmware is for MAC only */ 3424 r8169_apply_firmware(tp); 3425 3426 rtl_hw_aspm_clkreq_enable(tp, true); 3427 } 3428 3429 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3430 { 3431 static const struct ephy_info e_info_8102e_1[] = { 3432 { 0x01, 0, 0x6e65 }, 3433 { 0x02, 0, 0x091f }, 3434 { 0x03, 0, 0xc2f9 }, 3435 { 0x06, 0, 0xafb5 }, 3436 { 0x07, 0, 0x0e00 }, 3437 { 0x19, 0, 0xec80 }, 3438 { 0x01, 0, 0x2e65 }, 3439 { 0x01, 0, 0x6e65 } 3440 }; 3441 u8 cfg1; 3442 3443 rtl_set_def_aspm_entry_latency(tp); 3444 3445 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3446 3447 RTL_W8(tp, Config1, 3448 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3449 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3450 3451 cfg1 = RTL_R8(tp, Config1); 3452 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3453 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3454 3455 rtl_ephy_init(tp, e_info_8102e_1); 3456 } 3457 3458 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3459 { 3460 rtl_set_def_aspm_entry_latency(tp); 3461 3462 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3463 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3464 } 3465 3466 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3467 { 3468 rtl_hw_start_8102e_2(tp); 3469 3470 rtl_ephy_write(tp, 0x03, 0xc2f9); 3471 } 3472 3473 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3474 { 3475 static const struct ephy_info e_info_8105e_1[] = { 3476 { 0x07, 0, 0x4000 }, 3477 { 0x19, 0, 0x0200 }, 3478 { 0x19, 0, 0x0020 }, 3479 { 0x1e, 0, 0x2000 }, 3480 { 0x03, 0, 0x0001 }, 3481 { 0x19, 0, 0x0100 }, 3482 { 0x19, 0, 0x0004 }, 3483 { 0x0a, 0, 0x0020 } 3484 }; 3485 3486 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3487 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3488 3489 /* Disable Early Tally Counter */ 3490 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3491 3492 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3493 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3494 3495 rtl_ephy_init(tp, e_info_8105e_1); 3496 3497 rtl_pcie_state_l2l3_disable(tp); 3498 } 3499 3500 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3501 { 3502 rtl_hw_start_8105e_1(tp); 3503 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3504 } 3505 3506 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3507 { 3508 static const struct ephy_info e_info_8402[] = { 3509 { 0x19, 0xffff, 0xff64 }, 3510 { 0x1e, 0, 0x4000 } 3511 }; 3512 3513 rtl_set_def_aspm_entry_latency(tp); 3514 3515 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3516 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3517 3518 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3519 3520 rtl_ephy_init(tp, e_info_8402); 3521 3522 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3523 rtl_reset_packet_filter(tp); 3524 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3525 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3526 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3527 3528 /* disable EEE */ 3529 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3530 3531 rtl_pcie_state_l2l3_disable(tp); 3532 } 3533 3534 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3535 { 3536 rtl_hw_aspm_clkreq_enable(tp, false); 3537 3538 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3539 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3540 3541 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3542 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3543 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3544 3545 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3546 3547 /* disable EEE */ 3548 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3549 3550 rtl_pcie_state_l2l3_disable(tp); 3551 rtl_hw_aspm_clkreq_enable(tp, true); 3552 } 3553 3554 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3555 { 3556 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3557 } 3558 3559 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3560 { 3561 rtl_pcie_state_l2l3_disable(tp); 3562 3563 RTL_W16(tp, 0x382, 0x221b); 3564 RTL_W8(tp, 0x4500, 0); 3565 RTL_W16(tp, 0x4800, 0); 3566 3567 /* disable UPS */ 3568 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3569 3570 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3571 3572 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3573 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3574 3575 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3576 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3577 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3578 3579 /* disable new tx descriptor format */ 3580 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3581 3582 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3583 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3584 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3585 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3586 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3587 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3588 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3589 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3590 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 3591 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3592 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3593 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 3594 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3595 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3596 udelay(1); 3597 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3598 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3599 3600 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3601 3602 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3603 3604 rtl8125_config_eee_mac(tp); 3605 3606 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3607 udelay(10); 3608 } 3609 3610 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 3611 { 3612 static const struct ephy_info e_info_8125_1[] = { 3613 { 0x01, 0xffff, 0xa812 }, 3614 { 0x09, 0xffff, 0x520c }, 3615 { 0x04, 0xffff, 0xd000 }, 3616 { 0x0d, 0xffff, 0xf702 }, 3617 { 0x0a, 0xffff, 0x8653 }, 3618 { 0x06, 0xffff, 0x001e }, 3619 { 0x08, 0xffff, 0x3595 }, 3620 { 0x20, 0xffff, 0x9455 }, 3621 { 0x21, 0xffff, 0x99ff }, 3622 { 0x02, 0xffff, 0x6046 }, 3623 { 0x29, 0xffff, 0xfe00 }, 3624 { 0x23, 0xffff, 0xab62 }, 3625 3626 { 0x41, 0xffff, 0xa80c }, 3627 { 0x49, 0xffff, 0x520c }, 3628 { 0x44, 0xffff, 0xd000 }, 3629 { 0x4d, 0xffff, 0xf702 }, 3630 { 0x4a, 0xffff, 0x8653 }, 3631 { 0x46, 0xffff, 0x001e }, 3632 { 0x48, 0xffff, 0x3595 }, 3633 { 0x60, 0xffff, 0x9455 }, 3634 { 0x61, 0xffff, 0x99ff }, 3635 { 0x42, 0xffff, 0x6046 }, 3636 { 0x69, 0xffff, 0xfe00 }, 3637 { 0x63, 0xffff, 0xab62 }, 3638 }; 3639 3640 rtl_set_def_aspm_entry_latency(tp); 3641 3642 /* disable aspm and clock request before access ephy */ 3643 rtl_hw_aspm_clkreq_enable(tp, false); 3644 rtl_ephy_init(tp, e_info_8125_1); 3645 3646 rtl_hw_start_8125_common(tp); 3647 } 3648 3649 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 3650 { 3651 static const struct ephy_info e_info_8125_2[] = { 3652 { 0x04, 0xffff, 0xd000 }, 3653 { 0x0a, 0xffff, 0x8653 }, 3654 { 0x23, 0xffff, 0xab66 }, 3655 { 0x20, 0xffff, 0x9455 }, 3656 { 0x21, 0xffff, 0x99ff }, 3657 { 0x29, 0xffff, 0xfe04 }, 3658 3659 { 0x44, 0xffff, 0xd000 }, 3660 { 0x4a, 0xffff, 0x8653 }, 3661 { 0x63, 0xffff, 0xab66 }, 3662 { 0x60, 0xffff, 0x9455 }, 3663 { 0x61, 0xffff, 0x99ff }, 3664 { 0x69, 0xffff, 0xfe04 }, 3665 }; 3666 3667 rtl_set_def_aspm_entry_latency(tp); 3668 3669 /* disable aspm and clock request before access ephy */ 3670 rtl_hw_aspm_clkreq_enable(tp, false); 3671 rtl_ephy_init(tp, e_info_8125_2); 3672 3673 rtl_hw_start_8125_common(tp); 3674 } 3675 3676 static void rtl_hw_config(struct rtl8169_private *tp) 3677 { 3678 static const rtl_generic_fct hw_configs[] = { 3679 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3680 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3681 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3682 [RTL_GIGA_MAC_VER_10] = NULL, 3683 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3684 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3685 [RTL_GIGA_MAC_VER_13] = NULL, 3686 [RTL_GIGA_MAC_VER_14] = NULL, 3687 [RTL_GIGA_MAC_VER_15] = NULL, 3688 [RTL_GIGA_MAC_VER_16] = NULL, 3689 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3690 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3691 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3692 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3693 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3694 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3695 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3696 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3697 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3698 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3699 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3700 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3701 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3702 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3703 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3704 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3705 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3706 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3707 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3708 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3709 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3710 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3711 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3712 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3713 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3714 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3715 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3716 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3717 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3718 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3719 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3720 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3721 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3722 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3723 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3724 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3725 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 3726 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 3727 }; 3728 3729 if (hw_configs[tp->mac_version]) 3730 hw_configs[tp->mac_version](tp); 3731 } 3732 3733 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3734 { 3735 int i; 3736 3737 /* disable interrupt coalescing */ 3738 for (i = 0xa00; i < 0xb00; i += 4) 3739 RTL_W32(tp, i, 0); 3740 3741 rtl_hw_config(tp); 3742 } 3743 3744 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3745 { 3746 if (rtl_is_8168evl_up(tp)) 3747 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3748 else 3749 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3750 3751 rtl_hw_config(tp); 3752 3753 /* disable interrupt coalescing */ 3754 RTL_W16(tp, IntrMitigate, 0x0000); 3755 } 3756 3757 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3758 { 3759 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3760 3761 tp->cp_cmd |= PCIMulRW; 3762 3763 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3764 tp->mac_version == RTL_GIGA_MAC_VER_03) 3765 tp->cp_cmd |= EnAnaPLL; 3766 3767 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3768 3769 rtl8169_set_magic_reg(tp); 3770 3771 /* disable interrupt coalescing */ 3772 RTL_W16(tp, IntrMitigate, 0x0000); 3773 } 3774 3775 static void rtl_hw_start(struct rtl8169_private *tp) 3776 { 3777 rtl_unlock_config_regs(tp); 3778 3779 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3780 3781 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3782 rtl_hw_start_8169(tp); 3783 else if (rtl_is_8125(tp)) 3784 rtl_hw_start_8125(tp); 3785 else 3786 rtl_hw_start_8168(tp); 3787 3788 rtl_set_rx_max_size(tp); 3789 rtl_set_rx_tx_desc_registers(tp); 3790 rtl_lock_config_regs(tp); 3791 3792 rtl_jumbo_config(tp); 3793 3794 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3795 rtl_pci_commit(tp); 3796 3797 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3798 rtl_init_rxcfg(tp); 3799 rtl_set_tx_config_registers(tp); 3800 rtl_set_rx_config_features(tp, tp->dev->features); 3801 rtl_set_rx_mode(tp->dev); 3802 rtl_irq_enable(tp); 3803 } 3804 3805 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3806 { 3807 struct rtl8169_private *tp = netdev_priv(dev); 3808 3809 dev->mtu = new_mtu; 3810 netdev_update_features(dev); 3811 rtl_jumbo_config(tp); 3812 3813 return 0; 3814 } 3815 3816 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3817 { 3818 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3819 3820 desc->opts2 = 0; 3821 /* Force memory writes to complete before releasing descriptor */ 3822 dma_wmb(); 3823 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3824 } 3825 3826 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3827 struct RxDesc *desc) 3828 { 3829 struct device *d = tp_to_dev(tp); 3830 int node = dev_to_node(d); 3831 dma_addr_t mapping; 3832 struct page *data; 3833 3834 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3835 if (!data) 3836 return NULL; 3837 3838 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3839 if (unlikely(dma_mapping_error(d, mapping))) { 3840 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3841 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3842 return NULL; 3843 } 3844 3845 desc->addr = cpu_to_le64(mapping); 3846 rtl8169_mark_to_asic(desc); 3847 3848 return data; 3849 } 3850 3851 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3852 { 3853 unsigned int i; 3854 3855 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3856 dma_unmap_page(tp_to_dev(tp), 3857 le64_to_cpu(tp->RxDescArray[i].addr), 3858 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3859 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3860 tp->Rx_databuff[i] = NULL; 3861 tp->RxDescArray[i].addr = 0; 3862 tp->RxDescArray[i].opts1 = 0; 3863 } 3864 } 3865 3866 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3867 { 3868 unsigned int i; 3869 3870 for (i = 0; i < NUM_RX_DESC; i++) { 3871 struct page *data; 3872 3873 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3874 if (!data) { 3875 rtl8169_rx_clear(tp); 3876 return -ENOMEM; 3877 } 3878 tp->Rx_databuff[i] = data; 3879 } 3880 3881 /* mark as last descriptor in the ring */ 3882 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3883 3884 return 0; 3885 } 3886 3887 static int rtl8169_init_ring(struct rtl8169_private *tp) 3888 { 3889 rtl8169_init_ring_indexes(tp); 3890 3891 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3892 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3893 3894 return rtl8169_rx_fill(tp); 3895 } 3896 3897 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3898 { 3899 struct ring_info *tx_skb = tp->tx_skb + entry; 3900 struct TxDesc *desc = tp->TxDescArray + entry; 3901 3902 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3903 DMA_TO_DEVICE); 3904 memset(desc, 0, sizeof(*desc)); 3905 memset(tx_skb, 0, sizeof(*tx_skb)); 3906 } 3907 3908 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3909 unsigned int n) 3910 { 3911 unsigned int i; 3912 3913 for (i = 0; i < n; i++) { 3914 unsigned int entry = (start + i) % NUM_TX_DESC; 3915 struct ring_info *tx_skb = tp->tx_skb + entry; 3916 unsigned int len = tx_skb->len; 3917 3918 if (len) { 3919 struct sk_buff *skb = tx_skb->skb; 3920 3921 rtl8169_unmap_tx_skb(tp, entry); 3922 if (skb) 3923 dev_consume_skb_any(skb); 3924 } 3925 } 3926 } 3927 3928 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3929 { 3930 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3931 netdev_reset_queue(tp->dev); 3932 } 3933 3934 static void rtl8169_hw_reset(struct rtl8169_private *tp, bool going_down) 3935 { 3936 /* Give a racing hard_start_xmit a few cycles to complete. */ 3937 synchronize_rcu(); 3938 3939 /* Disable interrupts */ 3940 rtl8169_irq_mask_and_ack(tp); 3941 3942 rtl_rx_close(tp); 3943 3944 if (going_down && tp->dev->wol_enabled) 3945 goto no_reset; 3946 3947 switch (tp->mac_version) { 3948 case RTL_GIGA_MAC_VER_27: 3949 case RTL_GIGA_MAC_VER_28: 3950 case RTL_GIGA_MAC_VER_31: 3951 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3952 break; 3953 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3954 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3955 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3956 break; 3957 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 3958 rtl_enable_rxdvgate(tp); 3959 fsleep(2000); 3960 break; 3961 default: 3962 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3963 fsleep(100); 3964 break; 3965 } 3966 3967 rtl_hw_reset(tp); 3968 no_reset: 3969 rtl8169_tx_clear(tp); 3970 rtl8169_init_ring_indexes(tp); 3971 } 3972 3973 static void rtl_reset_work(struct rtl8169_private *tp) 3974 { 3975 struct net_device *dev = tp->dev; 3976 int i; 3977 3978 napi_disable(&tp->napi); 3979 netif_stop_queue(dev); 3980 3981 rtl8169_hw_reset(tp, false); 3982 3983 for (i = 0; i < NUM_RX_DESC; i++) 3984 rtl8169_mark_to_asic(tp->RxDescArray + i); 3985 3986 napi_enable(&tp->napi); 3987 rtl_hw_start(tp); 3988 netif_wake_queue(dev); 3989 } 3990 3991 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3992 { 3993 struct rtl8169_private *tp = netdev_priv(dev); 3994 3995 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3996 } 3997 3998 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3999 void *addr, unsigned int entry, bool desc_own) 4000 { 4001 struct TxDesc *txd = tp->TxDescArray + entry; 4002 struct device *d = tp_to_dev(tp); 4003 dma_addr_t mapping; 4004 u32 opts1; 4005 int ret; 4006 4007 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4008 ret = dma_mapping_error(d, mapping); 4009 if (unlikely(ret)) { 4010 if (net_ratelimit()) 4011 netdev_err(tp->dev, "Failed to map TX data!\n"); 4012 return ret; 4013 } 4014 4015 txd->addr = cpu_to_le64(mapping); 4016 txd->opts2 = cpu_to_le32(opts[1]); 4017 4018 opts1 = opts[0] | len; 4019 if (entry == NUM_TX_DESC - 1) 4020 opts1 |= RingEnd; 4021 if (desc_own) 4022 opts1 |= DescOwn; 4023 txd->opts1 = cpu_to_le32(opts1); 4024 4025 tp->tx_skb[entry].len = len; 4026 4027 return 0; 4028 } 4029 4030 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4031 const u32 *opts, unsigned int entry) 4032 { 4033 struct skb_shared_info *info = skb_shinfo(skb); 4034 unsigned int cur_frag; 4035 4036 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4037 const skb_frag_t *frag = info->frags + cur_frag; 4038 void *addr = skb_frag_address(frag); 4039 u32 len = skb_frag_size(frag); 4040 4041 entry = (entry + 1) % NUM_TX_DESC; 4042 4043 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4044 goto err_out; 4045 } 4046 4047 return 0; 4048 4049 err_out: 4050 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4051 return -EIO; 4052 } 4053 4054 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 4055 { 4056 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 4057 } 4058 4059 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4060 { 4061 u32 mss = skb_shinfo(skb)->gso_size; 4062 4063 if (mss) { 4064 opts[0] |= TD_LSO; 4065 opts[0] |= mss << TD0_MSS_SHIFT; 4066 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4067 const struct iphdr *ip = ip_hdr(skb); 4068 4069 if (ip->protocol == IPPROTO_TCP) 4070 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4071 else if (ip->protocol == IPPROTO_UDP) 4072 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4073 else 4074 WARN_ON_ONCE(1); 4075 } 4076 } 4077 4078 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4079 struct sk_buff *skb, u32 *opts) 4080 { 4081 u32 transport_offset = (u32)skb_transport_offset(skb); 4082 struct skb_shared_info *shinfo = skb_shinfo(skb); 4083 u32 mss = shinfo->gso_size; 4084 4085 if (mss) { 4086 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4087 opts[0] |= TD1_GTSENV4; 4088 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4089 if (skb_cow_head(skb, 0)) 4090 return false; 4091 4092 tcp_v6_gso_csum_prep(skb); 4093 opts[0] |= TD1_GTSENV6; 4094 } else { 4095 WARN_ON_ONCE(1); 4096 } 4097 4098 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4099 opts[1] |= mss << TD1_MSS_SHIFT; 4100 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4101 u8 ip_protocol; 4102 4103 switch (vlan_get_protocol(skb)) { 4104 case htons(ETH_P_IP): 4105 opts[1] |= TD1_IPv4_CS; 4106 ip_protocol = ip_hdr(skb)->protocol; 4107 break; 4108 4109 case htons(ETH_P_IPV6): 4110 opts[1] |= TD1_IPv6_CS; 4111 ip_protocol = ipv6_hdr(skb)->nexthdr; 4112 break; 4113 4114 default: 4115 ip_protocol = IPPROTO_RAW; 4116 break; 4117 } 4118 4119 if (ip_protocol == IPPROTO_TCP) 4120 opts[1] |= TD1_TCP_CS; 4121 else if (ip_protocol == IPPROTO_UDP) 4122 opts[1] |= TD1_UDP_CS; 4123 else 4124 WARN_ON_ONCE(1); 4125 4126 opts[1] |= transport_offset << TCPHO_SHIFT; 4127 } else { 4128 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 4129 return !eth_skb_pad(skb); 4130 } 4131 4132 return true; 4133 } 4134 4135 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4136 unsigned int nr_frags) 4137 { 4138 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4139 4140 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4141 return slots_avail > nr_frags; 4142 } 4143 4144 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4145 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4146 { 4147 switch (tp->mac_version) { 4148 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4149 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4150 return false; 4151 default: 4152 return true; 4153 } 4154 } 4155 4156 static void rtl8169_doorbell(struct rtl8169_private *tp) 4157 { 4158 if (rtl_is_8125(tp)) 4159 RTL_W16(tp, TxPoll_8125, BIT(0)); 4160 else 4161 RTL_W8(tp, TxPoll, NPQ); 4162 } 4163 4164 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4165 struct net_device *dev) 4166 { 4167 unsigned int frags = skb_shinfo(skb)->nr_frags; 4168 struct rtl8169_private *tp = netdev_priv(dev); 4169 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4170 struct TxDesc *txd_first, *txd_last; 4171 bool stop_queue, door_bell; 4172 u32 opts[2]; 4173 4174 txd_first = tp->TxDescArray + entry; 4175 4176 if (unlikely(!rtl_tx_slots_avail(tp, frags))) { 4177 if (net_ratelimit()) 4178 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4179 goto err_stop_0; 4180 } 4181 4182 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn)) 4183 goto err_stop_0; 4184 4185 opts[1] = rtl8169_tx_vlan_tag(skb); 4186 opts[0] = 0; 4187 4188 if (!rtl_chip_supports_csum_v2(tp)) 4189 rtl8169_tso_csum_v1(skb, opts); 4190 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4191 goto err_dma_0; 4192 4193 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4194 entry, false))) 4195 goto err_dma_0; 4196 4197 if (frags) { 4198 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4199 goto err_dma_1; 4200 entry = (entry + frags) % NUM_TX_DESC; 4201 } 4202 4203 txd_last = tp->TxDescArray + entry; 4204 txd_last->opts1 |= cpu_to_le32(LastFrag); 4205 tp->tx_skb[entry].skb = skb; 4206 4207 skb_tx_timestamp(skb); 4208 4209 /* Force memory writes to complete before releasing descriptor */ 4210 dma_wmb(); 4211 4212 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4213 4214 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4215 4216 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4217 smp_wmb(); 4218 4219 tp->cur_tx += frags + 1; 4220 4221 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4222 if (unlikely(stop_queue)) { 4223 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4224 * not miss a ring update when it notices a stopped queue. 4225 */ 4226 smp_wmb(); 4227 netif_stop_queue(dev); 4228 door_bell = true; 4229 } 4230 4231 if (door_bell) 4232 rtl8169_doorbell(tp); 4233 4234 if (unlikely(stop_queue)) { 4235 /* Sync with rtl_tx: 4236 * - publish queue status and cur_tx ring index (write barrier) 4237 * - refresh dirty_tx ring index (read barrier). 4238 * May the current thread have a pessimistic view of the ring 4239 * status and forget to wake up queue, a racing rtl_tx thread 4240 * can't. 4241 */ 4242 smp_mb(); 4243 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4244 netif_start_queue(dev); 4245 } 4246 4247 return NETDEV_TX_OK; 4248 4249 err_dma_1: 4250 rtl8169_unmap_tx_skb(tp, entry); 4251 err_dma_0: 4252 dev_kfree_skb_any(skb); 4253 dev->stats.tx_dropped++; 4254 return NETDEV_TX_OK; 4255 4256 err_stop_0: 4257 netif_stop_queue(dev); 4258 dev->stats.tx_dropped++; 4259 return NETDEV_TX_BUSY; 4260 } 4261 4262 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4263 { 4264 struct skb_shared_info *info = skb_shinfo(skb); 4265 unsigned int nr_frags = info->nr_frags; 4266 4267 if (!nr_frags) 4268 return UINT_MAX; 4269 4270 return skb_frag_size(info->frags + nr_frags - 1); 4271 } 4272 4273 /* Workaround for hw issues with TSO on RTL8168evl */ 4274 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4275 netdev_features_t features) 4276 { 4277 /* IPv4 header has options field */ 4278 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4279 ip_hdrlen(skb) > sizeof(struct iphdr)) 4280 features &= ~NETIF_F_ALL_TSO; 4281 4282 /* IPv4 TCP header has options field */ 4283 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4284 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4285 features &= ~NETIF_F_ALL_TSO; 4286 4287 else if (rtl_last_frag_len(skb) <= 6) 4288 features &= ~NETIF_F_ALL_TSO; 4289 4290 return features; 4291 } 4292 4293 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4294 struct net_device *dev, 4295 netdev_features_t features) 4296 { 4297 int transport_offset = skb_transport_offset(skb); 4298 struct rtl8169_private *tp = netdev_priv(dev); 4299 4300 if (skb_is_gso(skb)) { 4301 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4302 features = rtl8168evl_fix_tso(skb, features); 4303 4304 if (transport_offset > GTTCPHO_MAX && 4305 rtl_chip_supports_csum_v2(tp)) 4306 features &= ~NETIF_F_ALL_TSO; 4307 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4308 if (skb->len < ETH_ZLEN) { 4309 switch (tp->mac_version) { 4310 case RTL_GIGA_MAC_VER_11: 4311 case RTL_GIGA_MAC_VER_12: 4312 case RTL_GIGA_MAC_VER_17: 4313 case RTL_GIGA_MAC_VER_34: 4314 features &= ~NETIF_F_CSUM_MASK; 4315 break; 4316 default: 4317 break; 4318 } 4319 } 4320 4321 if (transport_offset > TCPHO_MAX && 4322 rtl_chip_supports_csum_v2(tp)) 4323 features &= ~NETIF_F_CSUM_MASK; 4324 } 4325 4326 return vlan_features_check(skb, features); 4327 } 4328 4329 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4330 { 4331 struct rtl8169_private *tp = netdev_priv(dev); 4332 struct pci_dev *pdev = tp->pci_dev; 4333 int pci_status_errs; 4334 u16 pci_cmd; 4335 4336 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4337 4338 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4339 4340 if (net_ratelimit()) 4341 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4342 pci_cmd, pci_status_errs); 4343 /* 4344 * The recovery sequence below admits a very elaborated explanation: 4345 * - it seems to work; 4346 * - I did not see what else could be done; 4347 * - it makes iop3xx happy. 4348 * 4349 * Feel free to adjust to your needs. 4350 */ 4351 if (pdev->broken_parity_status) 4352 pci_cmd &= ~PCI_COMMAND_PARITY; 4353 else 4354 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4355 4356 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4357 4358 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4359 } 4360 4361 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4362 int budget) 4363 { 4364 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4365 4366 dirty_tx = tp->dirty_tx; 4367 smp_rmb(); 4368 4369 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) { 4370 unsigned int entry = dirty_tx % NUM_TX_DESC; 4371 struct sk_buff *skb = tp->tx_skb[entry].skb; 4372 u32 status; 4373 4374 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4375 if (status & DescOwn) 4376 break; 4377 4378 rtl8169_unmap_tx_skb(tp, entry); 4379 4380 if (skb) { 4381 pkts_compl++; 4382 bytes_compl += skb->len; 4383 napi_consume_skb(skb, budget); 4384 } 4385 dirty_tx++; 4386 } 4387 4388 if (tp->dirty_tx != dirty_tx) { 4389 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4390 4391 u64_stats_update_begin(&tp->tx_stats.syncp); 4392 tp->tx_stats.packets += pkts_compl; 4393 tp->tx_stats.bytes += bytes_compl; 4394 u64_stats_update_end(&tp->tx_stats.syncp); 4395 4396 tp->dirty_tx = dirty_tx; 4397 /* Sync with rtl8169_start_xmit: 4398 * - publish dirty_tx ring index (write barrier) 4399 * - refresh cur_tx ring index and queue status (read barrier) 4400 * May the current thread miss the stopped queue condition, 4401 * a racing xmit thread can only have a right view of the 4402 * ring status. 4403 */ 4404 smp_mb(); 4405 if (netif_queue_stopped(dev) && 4406 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4407 netif_wake_queue(dev); 4408 } 4409 /* 4410 * 8168 hack: TxPoll requests are lost when the Tx packets are 4411 * too close. Let's kick an extra TxPoll request when a burst 4412 * of start_xmit activity is detected (if it is not detected, 4413 * it is slow enough). -- FR 4414 */ 4415 if (tp->cur_tx != dirty_tx) 4416 rtl8169_doorbell(tp); 4417 } 4418 } 4419 4420 static inline int rtl8169_fragmented_frame(u32 status) 4421 { 4422 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4423 } 4424 4425 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4426 { 4427 u32 status = opts1 & RxProtoMask; 4428 4429 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4430 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4431 skb->ip_summed = CHECKSUM_UNNECESSARY; 4432 else 4433 skb_checksum_none_assert(skb); 4434 } 4435 4436 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4437 { 4438 unsigned int cur_rx, rx_left, count; 4439 struct device *d = tp_to_dev(tp); 4440 4441 cur_rx = tp->cur_rx; 4442 4443 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4444 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC; 4445 struct RxDesc *desc = tp->RxDescArray + entry; 4446 struct sk_buff *skb; 4447 const void *rx_buf; 4448 dma_addr_t addr; 4449 u32 status; 4450 4451 status = le32_to_cpu(desc->opts1); 4452 if (status & DescOwn) 4453 break; 4454 4455 /* This barrier is needed to keep us from reading 4456 * any other fields out of the Rx descriptor until 4457 * we know the status of DescOwn 4458 */ 4459 dma_rmb(); 4460 4461 if (unlikely(status & RxRES)) { 4462 if (net_ratelimit()) 4463 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4464 status); 4465 dev->stats.rx_errors++; 4466 if (status & (RxRWT | RxRUNT)) 4467 dev->stats.rx_length_errors++; 4468 if (status & RxCRC) 4469 dev->stats.rx_crc_errors++; 4470 4471 if (!(dev->features & NETIF_F_RXALL)) 4472 goto release_descriptor; 4473 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4474 goto release_descriptor; 4475 } 4476 4477 pkt_size = status & GENMASK(13, 0); 4478 if (likely(!(dev->features & NETIF_F_RXFCS))) 4479 pkt_size -= ETH_FCS_LEN; 4480 4481 /* The driver does not support incoming fragmented frames. 4482 * They are seen as a symptom of over-mtu sized frames. 4483 */ 4484 if (unlikely(rtl8169_fragmented_frame(status))) { 4485 dev->stats.rx_dropped++; 4486 dev->stats.rx_length_errors++; 4487 goto release_descriptor; 4488 } 4489 4490 skb = napi_alloc_skb(&tp->napi, pkt_size); 4491 if (unlikely(!skb)) { 4492 dev->stats.rx_dropped++; 4493 goto release_descriptor; 4494 } 4495 4496 addr = le64_to_cpu(desc->addr); 4497 rx_buf = page_address(tp->Rx_databuff[entry]); 4498 4499 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4500 prefetch(rx_buf); 4501 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4502 skb->tail += pkt_size; 4503 skb->len = pkt_size; 4504 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4505 4506 rtl8169_rx_csum(skb, status); 4507 skb->protocol = eth_type_trans(skb, dev); 4508 4509 rtl8169_rx_vlan_tag(desc, skb); 4510 4511 if (skb->pkt_type == PACKET_MULTICAST) 4512 dev->stats.multicast++; 4513 4514 napi_gro_receive(&tp->napi, skb); 4515 4516 u64_stats_update_begin(&tp->rx_stats.syncp); 4517 tp->rx_stats.packets++; 4518 tp->rx_stats.bytes += pkt_size; 4519 u64_stats_update_end(&tp->rx_stats.syncp); 4520 4521 release_descriptor: 4522 rtl8169_mark_to_asic(desc); 4523 } 4524 4525 count = cur_rx - tp->cur_rx; 4526 tp->cur_rx = cur_rx; 4527 4528 return count; 4529 } 4530 4531 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4532 { 4533 struct rtl8169_private *tp = dev_instance; 4534 u32 status = rtl_get_events(tp); 4535 4536 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 4537 !(status & tp->irq_mask)) 4538 return IRQ_NONE; 4539 4540 if (unlikely(status & SYSErr)) { 4541 rtl8169_pcierr_interrupt(tp->dev); 4542 goto out; 4543 } 4544 4545 if (status & LinkChg) 4546 phy_mac_interrupt(tp->phydev); 4547 4548 if (unlikely(status & RxFIFOOver && 4549 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4550 netif_stop_queue(tp->dev); 4551 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4552 } 4553 4554 rtl_irq_disable(tp); 4555 napi_schedule_irqoff(&tp->napi); 4556 out: 4557 rtl_ack_events(tp, status); 4558 4559 return IRQ_HANDLED; 4560 } 4561 4562 static void rtl_task(struct work_struct *work) 4563 { 4564 struct rtl8169_private *tp = 4565 container_of(work, struct rtl8169_private, wk.work); 4566 4567 rtl_lock_work(tp); 4568 4569 if (!netif_running(tp->dev) || 4570 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4571 goto out_unlock; 4572 4573 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) 4574 rtl_reset_work(tp); 4575 out_unlock: 4576 rtl_unlock_work(tp); 4577 } 4578 4579 static int rtl8169_poll(struct napi_struct *napi, int budget) 4580 { 4581 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4582 struct net_device *dev = tp->dev; 4583 int work_done; 4584 4585 work_done = rtl_rx(dev, tp, (u32) budget); 4586 4587 rtl_tx(dev, tp, budget); 4588 4589 if (work_done < budget) { 4590 napi_complete_done(napi, work_done); 4591 rtl_irq_enable(tp); 4592 } 4593 4594 return work_done; 4595 } 4596 4597 static void r8169_phylink_handler(struct net_device *ndev) 4598 { 4599 struct rtl8169_private *tp = netdev_priv(ndev); 4600 4601 if (netif_carrier_ok(ndev)) { 4602 rtl_link_chg_patch(tp); 4603 pm_request_resume(&tp->pci_dev->dev); 4604 } else { 4605 pm_runtime_idle(&tp->pci_dev->dev); 4606 } 4607 4608 if (net_ratelimit()) 4609 phy_print_status(tp->phydev); 4610 } 4611 4612 static int r8169_phy_connect(struct rtl8169_private *tp) 4613 { 4614 struct phy_device *phydev = tp->phydev; 4615 phy_interface_t phy_mode; 4616 int ret; 4617 4618 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4619 PHY_INTERFACE_MODE_MII; 4620 4621 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4622 phy_mode); 4623 if (ret) 4624 return ret; 4625 4626 if (!tp->supports_gmii) 4627 phy_set_max_speed(phydev, SPEED_100); 4628 4629 phy_support_asym_pause(phydev); 4630 4631 phy_attached_info(phydev); 4632 4633 return 0; 4634 } 4635 4636 static void rtl8169_down(struct rtl8169_private *tp) 4637 { 4638 rtl_lock_work(tp); 4639 4640 /* Clear all task flags */ 4641 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4642 4643 phy_stop(tp->phydev); 4644 napi_disable(&tp->napi); 4645 4646 rtl8169_hw_reset(tp, true); 4647 4648 rtl_pll_power_down(tp); 4649 4650 rtl_unlock_work(tp); 4651 } 4652 4653 static int rtl8169_close(struct net_device *dev) 4654 { 4655 struct rtl8169_private *tp = netdev_priv(dev); 4656 struct pci_dev *pdev = tp->pci_dev; 4657 4658 pm_runtime_get_sync(&pdev->dev); 4659 4660 /* Update counters before going down */ 4661 rtl8169_update_counters(tp); 4662 4663 netif_stop_queue(dev); 4664 rtl8169_down(tp); 4665 rtl8169_rx_clear(tp); 4666 4667 cancel_work_sync(&tp->wk.work); 4668 4669 phy_disconnect(tp->phydev); 4670 4671 pci_free_irq(pdev, 0, tp); 4672 4673 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4674 tp->RxPhyAddr); 4675 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4676 tp->TxPhyAddr); 4677 tp->TxDescArray = NULL; 4678 tp->RxDescArray = NULL; 4679 4680 pm_runtime_put_sync(&pdev->dev); 4681 4682 return 0; 4683 } 4684 4685 #ifdef CONFIG_NET_POLL_CONTROLLER 4686 static void rtl8169_netpoll(struct net_device *dev) 4687 { 4688 struct rtl8169_private *tp = netdev_priv(dev); 4689 4690 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4691 } 4692 #endif 4693 4694 static int rtl_open(struct net_device *dev) 4695 { 4696 struct rtl8169_private *tp = netdev_priv(dev); 4697 struct pci_dev *pdev = tp->pci_dev; 4698 int retval = -ENOMEM; 4699 4700 pm_runtime_get_sync(&pdev->dev); 4701 4702 /* 4703 * Rx and Tx descriptors needs 256 bytes alignment. 4704 * dma_alloc_coherent provides more. 4705 */ 4706 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4707 &tp->TxPhyAddr, GFP_KERNEL); 4708 if (!tp->TxDescArray) 4709 goto err_pm_runtime_put; 4710 4711 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4712 &tp->RxPhyAddr, GFP_KERNEL); 4713 if (!tp->RxDescArray) 4714 goto err_free_tx_0; 4715 4716 retval = rtl8169_init_ring(tp); 4717 if (retval < 0) 4718 goto err_free_rx_1; 4719 4720 rtl_request_firmware(tp); 4721 4722 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 4723 dev->name); 4724 if (retval < 0) 4725 goto err_release_fw_2; 4726 4727 retval = r8169_phy_connect(tp); 4728 if (retval) 4729 goto err_free_irq; 4730 4731 rtl_lock_work(tp); 4732 4733 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4734 4735 napi_enable(&tp->napi); 4736 4737 rtl8169_init_phy(tp); 4738 4739 rtl_pll_power_up(tp); 4740 4741 rtl_hw_start(tp); 4742 4743 rtl8169_init_counter_offsets(tp); 4744 4745 phy_start(tp->phydev); 4746 netif_start_queue(dev); 4747 4748 rtl_unlock_work(tp); 4749 4750 pm_runtime_put_sync(&pdev->dev); 4751 out: 4752 return retval; 4753 4754 err_free_irq: 4755 pci_free_irq(pdev, 0, tp); 4756 err_release_fw_2: 4757 rtl_release_firmware(tp); 4758 rtl8169_rx_clear(tp); 4759 err_free_rx_1: 4760 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4761 tp->RxPhyAddr); 4762 tp->RxDescArray = NULL; 4763 err_free_tx_0: 4764 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4765 tp->TxPhyAddr); 4766 tp->TxDescArray = NULL; 4767 err_pm_runtime_put: 4768 pm_runtime_put_noidle(&pdev->dev); 4769 goto out; 4770 } 4771 4772 static void 4773 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4774 { 4775 struct rtl8169_private *tp = netdev_priv(dev); 4776 struct pci_dev *pdev = tp->pci_dev; 4777 struct rtl8169_counters *counters = tp->counters; 4778 unsigned int start; 4779 4780 pm_runtime_get_noresume(&pdev->dev); 4781 4782 netdev_stats_to_stats64(stats, &dev->stats); 4783 4784 do { 4785 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 4786 stats->rx_packets = tp->rx_stats.packets; 4787 stats->rx_bytes = tp->rx_stats.bytes; 4788 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 4789 4790 do { 4791 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 4792 stats->tx_packets = tp->tx_stats.packets; 4793 stats->tx_bytes = tp->tx_stats.bytes; 4794 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 4795 4796 /* 4797 * Fetch additional counter values missing in stats collected by driver 4798 * from tally counters. 4799 */ 4800 if (pm_runtime_active(&pdev->dev)) 4801 rtl8169_update_counters(tp); 4802 4803 /* 4804 * Subtract values fetched during initalization. 4805 * See rtl8169_init_counter_offsets for a description why we do that. 4806 */ 4807 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4808 le64_to_cpu(tp->tc_offset.tx_errors); 4809 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4810 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4811 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4812 le16_to_cpu(tp->tc_offset.tx_aborted); 4813 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4814 le16_to_cpu(tp->tc_offset.rx_missed); 4815 4816 pm_runtime_put_noidle(&pdev->dev); 4817 } 4818 4819 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4820 { 4821 if (!netif_running(tp->dev)) 4822 return; 4823 4824 netif_device_detach(tp->dev); 4825 rtl8169_down(tp); 4826 } 4827 4828 #ifdef CONFIG_PM 4829 4830 static int __maybe_unused rtl8169_suspend(struct device *device) 4831 { 4832 struct rtl8169_private *tp = dev_get_drvdata(device); 4833 4834 rtl8169_net_suspend(tp); 4835 clk_disable_unprepare(tp->clk); 4836 4837 return 0; 4838 } 4839 4840 static void __rtl8169_resume(struct rtl8169_private *tp) 4841 { 4842 netif_device_attach(tp->dev); 4843 4844 rtl_pll_power_up(tp); 4845 rtl8169_init_phy(tp); 4846 4847 phy_start(tp->phydev); 4848 4849 rtl_lock_work(tp); 4850 napi_enable(&tp->napi); 4851 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4852 rtl_reset_work(tp); 4853 rtl_unlock_work(tp); 4854 } 4855 4856 static int __maybe_unused rtl8169_resume(struct device *device) 4857 { 4858 struct rtl8169_private *tp = dev_get_drvdata(device); 4859 4860 rtl_rar_set(tp, tp->dev->dev_addr); 4861 4862 clk_prepare_enable(tp->clk); 4863 4864 if (netif_running(tp->dev)) 4865 __rtl8169_resume(tp); 4866 4867 return 0; 4868 } 4869 4870 static int rtl8169_runtime_suspend(struct device *device) 4871 { 4872 struct rtl8169_private *tp = dev_get_drvdata(device); 4873 4874 if (!tp->TxDescArray) 4875 return 0; 4876 4877 rtl_lock_work(tp); 4878 __rtl8169_set_wol(tp, WAKE_PHY); 4879 rtl_unlock_work(tp); 4880 4881 rtl8169_net_suspend(tp); 4882 4883 /* Update counters before going runtime suspend */ 4884 rtl8169_update_counters(tp); 4885 4886 return 0; 4887 } 4888 4889 static int rtl8169_runtime_resume(struct device *device) 4890 { 4891 struct rtl8169_private *tp = dev_get_drvdata(device); 4892 4893 rtl_rar_set(tp, tp->dev->dev_addr); 4894 4895 if (!tp->TxDescArray) 4896 return 0; 4897 4898 rtl_lock_work(tp); 4899 __rtl8169_set_wol(tp, tp->saved_wolopts); 4900 rtl_unlock_work(tp); 4901 4902 __rtl8169_resume(tp); 4903 4904 return 0; 4905 } 4906 4907 static int rtl8169_runtime_idle(struct device *device) 4908 { 4909 struct rtl8169_private *tp = dev_get_drvdata(device); 4910 4911 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4912 pm_schedule_suspend(device, 10000); 4913 4914 return -EBUSY; 4915 } 4916 4917 static const struct dev_pm_ops rtl8169_pm_ops = { 4918 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4919 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4920 rtl8169_runtime_idle) 4921 }; 4922 4923 #endif /* CONFIG_PM */ 4924 4925 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4926 { 4927 /* WoL fails with 8168b when the receiver is disabled. */ 4928 switch (tp->mac_version) { 4929 case RTL_GIGA_MAC_VER_11: 4930 case RTL_GIGA_MAC_VER_12: 4931 case RTL_GIGA_MAC_VER_17: 4932 pci_clear_master(tp->pci_dev); 4933 4934 RTL_W8(tp, ChipCmd, CmdRxEnb); 4935 rtl_pci_commit(tp); 4936 break; 4937 default: 4938 break; 4939 } 4940 } 4941 4942 static void rtl_shutdown(struct pci_dev *pdev) 4943 { 4944 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4945 4946 rtl8169_net_suspend(tp); 4947 4948 /* Restore original MAC address */ 4949 rtl_rar_set(tp, tp->dev->perm_addr); 4950 4951 if (system_state == SYSTEM_POWER_OFF) { 4952 if (tp->saved_wolopts) { 4953 rtl_wol_suspend_quirk(tp); 4954 rtl_wol_shutdown_quirk(tp); 4955 } 4956 4957 pci_wake_from_d3(pdev, true); 4958 pci_set_power_state(pdev, PCI_D3hot); 4959 } 4960 } 4961 4962 static void rtl_remove_one(struct pci_dev *pdev) 4963 { 4964 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4965 4966 if (pci_dev_run_wake(pdev)) 4967 pm_runtime_get_noresume(&pdev->dev); 4968 4969 unregister_netdev(tp->dev); 4970 4971 if (r8168_check_dash(tp)) 4972 rtl8168_driver_stop(tp); 4973 4974 rtl_release_firmware(tp); 4975 4976 /* restore original MAC address */ 4977 rtl_rar_set(tp, tp->dev->perm_addr); 4978 } 4979 4980 static const struct net_device_ops rtl_netdev_ops = { 4981 .ndo_open = rtl_open, 4982 .ndo_stop = rtl8169_close, 4983 .ndo_get_stats64 = rtl8169_get_stats64, 4984 .ndo_start_xmit = rtl8169_start_xmit, 4985 .ndo_features_check = rtl8169_features_check, 4986 .ndo_tx_timeout = rtl8169_tx_timeout, 4987 .ndo_validate_addr = eth_validate_addr, 4988 .ndo_change_mtu = rtl8169_change_mtu, 4989 .ndo_fix_features = rtl8169_fix_features, 4990 .ndo_set_features = rtl8169_set_features, 4991 .ndo_set_mac_address = rtl_set_mac_address, 4992 .ndo_do_ioctl = phy_do_ioctl_running, 4993 .ndo_set_rx_mode = rtl_set_rx_mode, 4994 #ifdef CONFIG_NET_POLL_CONTROLLER 4995 .ndo_poll_controller = rtl8169_netpoll, 4996 #endif 4997 4998 }; 4999 5000 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5001 { 5002 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5003 5004 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5005 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5006 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5007 /* special workaround needed */ 5008 tp->irq_mask |= RxFIFOOver; 5009 else 5010 tp->irq_mask |= RxOverflow; 5011 } 5012 5013 static int rtl_alloc_irq(struct rtl8169_private *tp) 5014 { 5015 unsigned int flags; 5016 5017 switch (tp->mac_version) { 5018 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5019 rtl_unlock_config_regs(tp); 5020 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5021 rtl_lock_config_regs(tp); 5022 /* fall through */ 5023 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5024 flags = PCI_IRQ_LEGACY; 5025 break; 5026 default: 5027 flags = PCI_IRQ_ALL_TYPES; 5028 break; 5029 } 5030 5031 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5032 } 5033 5034 static void rtl_read_mac_address(struct rtl8169_private *tp, 5035 u8 mac_addr[ETH_ALEN]) 5036 { 5037 /* Get MAC address */ 5038 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5039 u32 value = rtl_eri_read(tp, 0xe0); 5040 5041 mac_addr[0] = (value >> 0) & 0xff; 5042 mac_addr[1] = (value >> 8) & 0xff; 5043 mac_addr[2] = (value >> 16) & 0xff; 5044 mac_addr[3] = (value >> 24) & 0xff; 5045 5046 value = rtl_eri_read(tp, 0xe4); 5047 mac_addr[4] = (value >> 0) & 0xff; 5048 mac_addr[5] = (value >> 8) & 0xff; 5049 } else if (rtl_is_8125(tp)) { 5050 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5051 } 5052 } 5053 5054 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5055 { 5056 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5057 } 5058 5059 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5060 { 5061 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5062 } 5063 5064 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5065 { 5066 struct rtl8169_private *tp = mii_bus->priv; 5067 5068 if (phyaddr > 0) 5069 return -ENODEV; 5070 5071 return rtl_readphy(tp, phyreg); 5072 } 5073 5074 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5075 int phyreg, u16 val) 5076 { 5077 struct rtl8169_private *tp = mii_bus->priv; 5078 5079 if (phyaddr > 0) 5080 return -ENODEV; 5081 5082 rtl_writephy(tp, phyreg, val); 5083 5084 return 0; 5085 } 5086 5087 static int r8169_mdio_register(struct rtl8169_private *tp) 5088 { 5089 struct pci_dev *pdev = tp->pci_dev; 5090 struct mii_bus *new_bus; 5091 int ret; 5092 5093 new_bus = devm_mdiobus_alloc(&pdev->dev); 5094 if (!new_bus) 5095 return -ENOMEM; 5096 5097 new_bus->name = "r8169"; 5098 new_bus->priv = tp; 5099 new_bus->parent = &pdev->dev; 5100 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5101 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5102 5103 new_bus->read = r8169_mdio_read_reg; 5104 new_bus->write = r8169_mdio_write_reg; 5105 5106 ret = devm_mdiobus_register(new_bus); 5107 if (ret) 5108 return ret; 5109 5110 tp->phydev = mdiobus_get_phy(new_bus, 0); 5111 if (!tp->phydev) { 5112 return -ENODEV; 5113 } else if (!tp->phydev->drv) { 5114 /* Most chip versions fail with the genphy driver. 5115 * Therefore ensure that the dedicated PHY driver is loaded. 5116 */ 5117 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5118 tp->phydev->phy_id); 5119 return -EUNATCH; 5120 } 5121 5122 /* PHY will be woken up in rtl_open() */ 5123 phy_suspend(tp->phydev); 5124 5125 return 0; 5126 } 5127 5128 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5129 { 5130 rtl_enable_rxdvgate(tp); 5131 5132 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5133 msleep(1); 5134 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5135 5136 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5137 r8168g_wait_ll_share_fifo_ready(tp); 5138 5139 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5140 r8168g_wait_ll_share_fifo_ready(tp); 5141 } 5142 5143 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5144 { 5145 rtl_enable_rxdvgate(tp); 5146 5147 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5148 msleep(1); 5149 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5150 5151 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5152 r8168g_wait_ll_share_fifo_ready(tp); 5153 5154 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5155 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5156 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5157 r8168g_wait_ll_share_fifo_ready(tp); 5158 } 5159 5160 static void rtl_hw_initialize(struct rtl8169_private *tp) 5161 { 5162 switch (tp->mac_version) { 5163 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5164 rtl8168ep_stop_cmac(tp); 5165 /* fall through */ 5166 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5167 rtl_hw_init_8168g(tp); 5168 break; 5169 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 5170 rtl_hw_init_8125(tp); 5171 break; 5172 default: 5173 break; 5174 } 5175 } 5176 5177 static int rtl_jumbo_max(struct rtl8169_private *tp) 5178 { 5179 /* Non-GBit versions don't support jumbo frames */ 5180 if (!tp->supports_gmii) 5181 return 0; 5182 5183 switch (tp->mac_version) { 5184 /* RTL8169 */ 5185 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5186 return JUMBO_7K; 5187 /* RTL8168b */ 5188 case RTL_GIGA_MAC_VER_11: 5189 case RTL_GIGA_MAC_VER_12: 5190 case RTL_GIGA_MAC_VER_17: 5191 return JUMBO_4K; 5192 /* RTL8168c */ 5193 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5194 return JUMBO_6K; 5195 default: 5196 return JUMBO_9K; 5197 } 5198 } 5199 5200 static void rtl_disable_clk(void *data) 5201 { 5202 clk_disable_unprepare(data); 5203 } 5204 5205 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5206 { 5207 struct device *d = tp_to_dev(tp); 5208 struct clk *clk; 5209 int rc; 5210 5211 clk = devm_clk_get(d, "ether_clk"); 5212 if (IS_ERR(clk)) { 5213 rc = PTR_ERR(clk); 5214 if (rc == -ENOENT) 5215 /* clk-core allows NULL (for suspend / resume) */ 5216 rc = 0; 5217 else if (rc != -EPROBE_DEFER) 5218 dev_err(d, "failed to get clk: %d\n", rc); 5219 } else { 5220 tp->clk = clk; 5221 rc = clk_prepare_enable(clk); 5222 if (rc) 5223 dev_err(d, "failed to enable clk: %d\n", rc); 5224 else 5225 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5226 } 5227 5228 return rc; 5229 } 5230 5231 static void rtl_init_mac_address(struct rtl8169_private *tp) 5232 { 5233 struct net_device *dev = tp->dev; 5234 u8 *mac_addr = dev->dev_addr; 5235 int rc; 5236 5237 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5238 if (!rc) 5239 goto done; 5240 5241 rtl_read_mac_address(tp, mac_addr); 5242 if (is_valid_ether_addr(mac_addr)) 5243 goto done; 5244 5245 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5246 if (is_valid_ether_addr(mac_addr)) 5247 goto done; 5248 5249 eth_hw_addr_random(dev); 5250 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5251 done: 5252 rtl_rar_set(tp, mac_addr); 5253 } 5254 5255 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5256 { 5257 struct rtl8169_private *tp; 5258 int jumbo_max, region, rc; 5259 enum mac_version chipset; 5260 struct net_device *dev; 5261 u16 xid; 5262 5263 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5264 if (!dev) 5265 return -ENOMEM; 5266 5267 SET_NETDEV_DEV(dev, &pdev->dev); 5268 dev->netdev_ops = &rtl_netdev_ops; 5269 tp = netdev_priv(dev); 5270 tp->dev = dev; 5271 tp->pci_dev = pdev; 5272 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5273 tp->eee_adv = -1; 5274 tp->ocp_base = OCP_STD_PHY_BASE; 5275 5276 /* Get the *optional* external "ether_clk" used on some boards */ 5277 rc = rtl_get_ether_clk(tp); 5278 if (rc) 5279 return rc; 5280 5281 /* Disable ASPM completely as that cause random device stop working 5282 * problems as well as full system hangs for some PCIe devices users. 5283 */ 5284 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5285 PCIE_LINK_STATE_L1); 5286 tp->aspm_manageable = !rc; 5287 5288 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5289 rc = pcim_enable_device(pdev); 5290 if (rc < 0) { 5291 dev_err(&pdev->dev, "enable failure\n"); 5292 return rc; 5293 } 5294 5295 if (pcim_set_mwi(pdev) < 0) 5296 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5297 5298 /* use first MMIO region */ 5299 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5300 if (region < 0) { 5301 dev_err(&pdev->dev, "no MMIO resource found\n"); 5302 return -ENODEV; 5303 } 5304 5305 /* check for weird/broken PCI region reporting */ 5306 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5307 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5308 return -ENODEV; 5309 } 5310 5311 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5312 if (rc < 0) { 5313 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5314 return rc; 5315 } 5316 5317 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5318 5319 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5320 5321 /* Identify chip attached to board */ 5322 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5323 if (chipset == RTL_GIGA_MAC_NONE) { 5324 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid); 5325 return -ENODEV; 5326 } 5327 5328 tp->mac_version = chipset; 5329 5330 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5331 5332 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5333 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5334 dev->features |= NETIF_F_HIGHDMA; 5335 5336 rtl_init_rxcfg(tp); 5337 5338 rtl8169_irq_mask_and_ack(tp); 5339 5340 rtl_hw_initialize(tp); 5341 5342 rtl_hw_reset(tp); 5343 5344 pci_set_master(pdev); 5345 5346 rc = rtl_alloc_irq(tp); 5347 if (rc < 0) { 5348 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5349 return rc; 5350 } 5351 5352 mutex_init(&tp->wk.mutex); 5353 INIT_WORK(&tp->wk.work, rtl_task); 5354 u64_stats_init(&tp->rx_stats.syncp); 5355 u64_stats_init(&tp->tx_stats.syncp); 5356 5357 rtl_init_mac_address(tp); 5358 5359 dev->ethtool_ops = &rtl8169_ethtool_ops; 5360 5361 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5362 5363 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5364 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5365 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5366 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5367 5368 /* 5369 * Pretend we are using VLANs; This bypasses a nasty bug where 5370 * Interrupts stop flowing on high load on 8110SCd controllers. 5371 */ 5372 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5373 /* Disallow toggling */ 5374 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5375 5376 if (rtl_chip_supports_csum_v2(tp)) 5377 dev->hw_features |= NETIF_F_IPV6_CSUM; 5378 5379 dev->features |= dev->hw_features; 5380 5381 /* There has been a number of reports that using SG/TSO results in 5382 * tx timeouts. However for a lot of people SG/TSO works fine. 5383 * Therefore disable both features by default, but allow users to 5384 * enable them. Use at own risk! 5385 */ 5386 if (rtl_chip_supports_csum_v2(tp)) { 5387 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5388 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5389 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5390 } else { 5391 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5392 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5393 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5394 } 5395 5396 dev->hw_features |= NETIF_F_RXALL; 5397 dev->hw_features |= NETIF_F_RXFCS; 5398 5399 /* configure chip for default features */ 5400 rtl8169_set_features(dev, dev->features); 5401 5402 jumbo_max = rtl_jumbo_max(tp); 5403 if (jumbo_max) 5404 dev->max_mtu = jumbo_max; 5405 5406 rtl_set_irq_mask(tp); 5407 5408 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5409 5410 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5411 &tp->counters_phys_addr, 5412 GFP_KERNEL); 5413 if (!tp->counters) 5414 return -ENOMEM; 5415 5416 pci_set_drvdata(pdev, tp); 5417 5418 rc = r8169_mdio_register(tp); 5419 if (rc) 5420 return rc; 5421 5422 /* chip gets powered up in rtl_open() */ 5423 rtl_pll_power_down(tp); 5424 5425 rc = register_netdev(dev); 5426 if (rc) 5427 return rc; 5428 5429 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5430 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5431 pci_irq_vector(pdev, 0)); 5432 5433 if (jumbo_max) 5434 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5435 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5436 "ok" : "ko"); 5437 5438 if (r8168_check_dash(tp)) 5439 rtl8168_driver_start(tp); 5440 5441 if (pci_dev_run_wake(pdev)) 5442 pm_runtime_put_sync(&pdev->dev); 5443 5444 return 0; 5445 } 5446 5447 static struct pci_driver rtl8169_pci_driver = { 5448 .name = MODULENAME, 5449 .id_table = rtl8169_pci_tbl, 5450 .probe = rtl_init_one, 5451 .remove = rtl_remove_one, 5452 .shutdown = rtl_shutdown, 5453 #ifdef CONFIG_PM 5454 .driver.pm = &rtl8169_pm_ops, 5455 #endif 5456 }; 5457 5458 module_pci_driver(rtl8169_pci_driver); 5459