1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 58 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 59 60 #define R8169_MSG_DEFAULT \ 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 62 63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 65 #define MC_FILTER_LIMIT 32 66 67 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 69 70 #define R8169_REGS_SIZE 256 71 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 73 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 enum mac_version { 88 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */ 89 RTL_GIGA_MAC_VER_02, 90 RTL_GIGA_MAC_VER_03, 91 RTL_GIGA_MAC_VER_04, 92 RTL_GIGA_MAC_VER_05, 93 RTL_GIGA_MAC_VER_06, 94 RTL_GIGA_MAC_VER_07, 95 RTL_GIGA_MAC_VER_08, 96 RTL_GIGA_MAC_VER_09, 97 RTL_GIGA_MAC_VER_10, 98 RTL_GIGA_MAC_VER_11, 99 RTL_GIGA_MAC_VER_12, 100 RTL_GIGA_MAC_VER_13, 101 RTL_GIGA_MAC_VER_14, 102 RTL_GIGA_MAC_VER_15, 103 RTL_GIGA_MAC_VER_16, 104 RTL_GIGA_MAC_VER_17, 105 RTL_GIGA_MAC_VER_18, 106 RTL_GIGA_MAC_VER_19, 107 RTL_GIGA_MAC_VER_20, 108 RTL_GIGA_MAC_VER_21, 109 RTL_GIGA_MAC_VER_22, 110 RTL_GIGA_MAC_VER_23, 111 RTL_GIGA_MAC_VER_24, 112 RTL_GIGA_MAC_VER_25, 113 RTL_GIGA_MAC_VER_26, 114 RTL_GIGA_MAC_VER_27, 115 RTL_GIGA_MAC_VER_28, 116 RTL_GIGA_MAC_VER_29, 117 RTL_GIGA_MAC_VER_30, 118 RTL_GIGA_MAC_VER_31, 119 RTL_GIGA_MAC_VER_32, 120 RTL_GIGA_MAC_VER_33, 121 RTL_GIGA_MAC_VER_34, 122 RTL_GIGA_MAC_VER_35, 123 RTL_GIGA_MAC_VER_36, 124 RTL_GIGA_MAC_VER_37, 125 RTL_GIGA_MAC_VER_38, 126 RTL_GIGA_MAC_VER_39, 127 RTL_GIGA_MAC_VER_40, 128 RTL_GIGA_MAC_VER_41, 129 RTL_GIGA_MAC_VER_42, 130 RTL_GIGA_MAC_VER_43, 131 RTL_GIGA_MAC_VER_44, 132 RTL_GIGA_MAC_VER_45, 133 RTL_GIGA_MAC_VER_46, 134 RTL_GIGA_MAC_VER_47, 135 RTL_GIGA_MAC_VER_48, 136 RTL_GIGA_MAC_VER_49, 137 RTL_GIGA_MAC_VER_50, 138 RTL_GIGA_MAC_VER_51, 139 RTL_GIGA_MAC_VER_52, 140 RTL_GIGA_MAC_VER_60, 141 RTL_GIGA_MAC_VER_61, 142 RTL_GIGA_MAC_NONE 143 }; 144 145 #define JUMBO_1K ETH_DATA_LEN 146 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 147 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 148 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 149 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 150 151 static const struct { 152 const char *name; 153 const char *fw_name; 154 } rtl_chip_infos[] = { 155 /* PCI devices. */ 156 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 157 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 158 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 159 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 160 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 161 /* PCI-E devices. */ 162 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 163 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 164 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 165 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 166 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 167 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 168 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 169 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 170 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 171 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 172 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 173 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 174 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 175 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 176 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 177 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 178 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 179 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 180 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 181 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 182 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 183 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 184 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 185 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 186 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 187 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 188 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 189 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 190 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 191 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 192 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 193 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 194 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 195 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 196 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 197 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 198 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 199 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 200 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 201 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 202 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 203 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 204 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 205 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 206 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 207 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 208 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 209 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 210 }; 211 212 static const struct pci_device_id rtl8169_pci_tbl[] = { 213 { PCI_VDEVICE(REALTEK, 0x2502) }, 214 { PCI_VDEVICE(REALTEK, 0x2600) }, 215 { PCI_VDEVICE(REALTEK, 0x8129) }, 216 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 217 { PCI_VDEVICE(REALTEK, 0x8161) }, 218 { PCI_VDEVICE(REALTEK, 0x8167) }, 219 { PCI_VDEVICE(REALTEK, 0x8168) }, 220 { PCI_VDEVICE(NCUBE, 0x8168) }, 221 { PCI_VDEVICE(REALTEK, 0x8169) }, 222 { PCI_VENDOR_ID_DLINK, 0x4300, 223 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 224 { PCI_VDEVICE(DLINK, 0x4300) }, 225 { PCI_VDEVICE(DLINK, 0x4302) }, 226 { PCI_VDEVICE(AT, 0xc107) }, 227 { PCI_VDEVICE(USR, 0x0116) }, 228 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 229 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 230 { PCI_VDEVICE(REALTEK, 0x8125) }, 231 { PCI_VDEVICE(REALTEK, 0x3000) }, 232 {} 233 }; 234 235 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 236 237 static struct { 238 u32 msg_enable; 239 } debug = { -1 }; 240 241 enum rtl_registers { 242 MAC0 = 0, /* Ethernet hardware address. */ 243 MAC4 = 4, 244 MAR0 = 8, /* Multicast filter. */ 245 CounterAddrLow = 0x10, 246 CounterAddrHigh = 0x14, 247 TxDescStartAddrLow = 0x20, 248 TxDescStartAddrHigh = 0x24, 249 TxHDescStartAddrLow = 0x28, 250 TxHDescStartAddrHigh = 0x2c, 251 FLASH = 0x30, 252 ERSR = 0x36, 253 ChipCmd = 0x37, 254 TxPoll = 0x38, 255 IntrMask = 0x3c, 256 IntrStatus = 0x3e, 257 258 TxConfig = 0x40, 259 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 260 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 261 262 RxConfig = 0x44, 263 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 264 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 265 #define RXCFG_FIFO_SHIFT 13 266 /* No threshold before first PCI xfer */ 267 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 268 #define RX_EARLY_OFF (1 << 11) 269 #define RXCFG_DMA_SHIFT 8 270 /* Unlimited maximum PCI burst. */ 271 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 272 273 RxMissed = 0x4c, 274 Cfg9346 = 0x50, 275 Config0 = 0x51, 276 Config1 = 0x52, 277 Config2 = 0x53, 278 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 279 280 Config3 = 0x54, 281 Config4 = 0x55, 282 Config5 = 0x56, 283 PHYAR = 0x60, 284 PHYstatus = 0x6c, 285 RxMaxSize = 0xda, 286 CPlusCmd = 0xe0, 287 IntrMitigate = 0xe2, 288 289 #define RTL_COALESCE_MASK 0x0f 290 #define RTL_COALESCE_SHIFT 4 291 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 292 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 293 294 RxDescAddrLow = 0xe4, 295 RxDescAddrHigh = 0xe8, 296 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 297 298 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 299 300 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 301 302 #define TxPacketMax (8064 >> 7) 303 #define EarlySize 0x27 304 305 FuncEvent = 0xf0, 306 FuncEventMask = 0xf4, 307 FuncPresetState = 0xf8, 308 IBCR0 = 0xf8, 309 IBCR2 = 0xf9, 310 IBIMR0 = 0xfa, 311 IBISR0 = 0xfb, 312 FuncForceEvent = 0xfc, 313 }; 314 315 enum rtl8168_8101_registers { 316 CSIDR = 0x64, 317 CSIAR = 0x68, 318 #define CSIAR_FLAG 0x80000000 319 #define CSIAR_WRITE_CMD 0x80000000 320 #define CSIAR_BYTE_ENABLE 0x0000f000 321 #define CSIAR_ADDR_MASK 0x00000fff 322 PMCH = 0x6f, 323 EPHYAR = 0x80, 324 #define EPHYAR_FLAG 0x80000000 325 #define EPHYAR_WRITE_CMD 0x80000000 326 #define EPHYAR_REG_MASK 0x1f 327 #define EPHYAR_REG_SHIFT 16 328 #define EPHYAR_DATA_MASK 0xffff 329 DLLPR = 0xd0, 330 #define PFM_EN (1 << 6) 331 #define TX_10M_PS_EN (1 << 7) 332 DBG_REG = 0xd1, 333 #define FIX_NAK_1 (1 << 4) 334 #define FIX_NAK_2 (1 << 3) 335 TWSI = 0xd2, 336 MCU = 0xd3, 337 #define NOW_IS_OOB (1 << 7) 338 #define TX_EMPTY (1 << 5) 339 #define RX_EMPTY (1 << 4) 340 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 341 #define EN_NDP (1 << 3) 342 #define EN_OOB_RESET (1 << 2) 343 #define LINK_LIST_RDY (1 << 1) 344 EFUSEAR = 0xdc, 345 #define EFUSEAR_FLAG 0x80000000 346 #define EFUSEAR_WRITE_CMD 0x80000000 347 #define EFUSEAR_READ_CMD 0x00000000 348 #define EFUSEAR_REG_MASK 0x03ff 349 #define EFUSEAR_REG_SHIFT 8 350 #define EFUSEAR_DATA_MASK 0xff 351 MISC_1 = 0xf2, 352 #define PFM_D3COLD_EN (1 << 6) 353 }; 354 355 enum rtl8168_registers { 356 LED_FREQ = 0x1a, 357 EEE_LED = 0x1b, 358 ERIDR = 0x70, 359 ERIAR = 0x74, 360 #define ERIAR_FLAG 0x80000000 361 #define ERIAR_WRITE_CMD 0x80000000 362 #define ERIAR_READ_CMD 0x00000000 363 #define ERIAR_ADDR_BYTE_ALIGN 4 364 #define ERIAR_TYPE_SHIFT 16 365 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 366 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 367 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 368 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 369 #define ERIAR_MASK_SHIFT 12 370 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 371 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 372 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 373 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 374 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 375 EPHY_RXER_NUM = 0x7c, 376 OCPDR = 0xb0, /* OCP GPHY access */ 377 #define OCPDR_WRITE_CMD 0x80000000 378 #define OCPDR_READ_CMD 0x00000000 379 #define OCPDR_REG_MASK 0x7f 380 #define OCPDR_GPHY_REG_SHIFT 16 381 #define OCPDR_DATA_MASK 0xffff 382 OCPAR = 0xb4, 383 #define OCPAR_FLAG 0x80000000 384 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 385 #define OCPAR_GPHY_READ_CMD 0x0000f060 386 GPHY_OCP = 0xb8, 387 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 388 MISC = 0xf0, /* 8168e only. */ 389 #define TXPLA_RST (1 << 29) 390 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 391 #define PWM_EN (1 << 22) 392 #define RXDV_GATED_EN (1 << 19) 393 #define EARLY_TALLY_EN (1 << 16) 394 }; 395 396 enum rtl8125_registers { 397 IntrMask_8125 = 0x38, 398 IntrStatus_8125 = 0x3c, 399 TxPoll_8125 = 0x90, 400 MAC0_BKP = 0x19e0, 401 }; 402 403 #define RX_VLAN_INNER_8125 BIT(22) 404 #define RX_VLAN_OUTER_8125 BIT(23) 405 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 406 407 #define RX_FETCH_DFLT_8125 (8 << 27) 408 409 enum rtl_register_content { 410 /* InterruptStatusBits */ 411 SYSErr = 0x8000, 412 PCSTimeout = 0x4000, 413 SWInt = 0x0100, 414 TxDescUnavail = 0x0080, 415 RxFIFOOver = 0x0040, 416 LinkChg = 0x0020, 417 RxOverflow = 0x0010, 418 TxErr = 0x0008, 419 TxOK = 0x0004, 420 RxErr = 0x0002, 421 RxOK = 0x0001, 422 423 /* RxStatusDesc */ 424 RxRWT = (1 << 22), 425 RxRES = (1 << 21), 426 RxRUNT = (1 << 20), 427 RxCRC = (1 << 19), 428 429 /* ChipCmdBits */ 430 StopReq = 0x80, 431 CmdReset = 0x10, 432 CmdRxEnb = 0x08, 433 CmdTxEnb = 0x04, 434 RxBufEmpty = 0x01, 435 436 /* TXPoll register p.5 */ 437 HPQ = 0x80, /* Poll cmd on the high prio queue */ 438 NPQ = 0x40, /* Poll cmd on the low prio queue */ 439 FSWInt = 0x01, /* Forced software interrupt */ 440 441 /* Cfg9346Bits */ 442 Cfg9346_Lock = 0x00, 443 Cfg9346_Unlock = 0xc0, 444 445 /* rx_mode_bits */ 446 AcceptErr = 0x20, 447 AcceptRunt = 0x10, 448 AcceptBroadcast = 0x08, 449 AcceptMulticast = 0x04, 450 AcceptMyPhys = 0x02, 451 AcceptAllPhys = 0x01, 452 #define RX_CONFIG_ACCEPT_MASK 0x3f 453 454 /* TxConfigBits */ 455 TxInterFrameGapShift = 24, 456 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 457 458 /* Config1 register p.24 */ 459 LEDS1 = (1 << 7), 460 LEDS0 = (1 << 6), 461 Speed_down = (1 << 4), 462 MEMMAP = (1 << 3), 463 IOMAP = (1 << 2), 464 VPD = (1 << 1), 465 PMEnable = (1 << 0), /* Power Management Enable */ 466 467 /* Config2 register p. 25 */ 468 ClkReqEn = (1 << 7), /* Clock Request Enable */ 469 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 470 PCI_Clock_66MHz = 0x01, 471 PCI_Clock_33MHz = 0x00, 472 473 /* Config3 register p.25 */ 474 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 475 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 476 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 477 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 478 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 479 480 /* Config4 register */ 481 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 482 483 /* Config5 register p.27 */ 484 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 485 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 486 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 487 Spi_en = (1 << 3), 488 LanWake = (1 << 1), /* LanWake enable/disable */ 489 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 490 ASPM_en = (1 << 0), /* ASPM enable */ 491 492 /* CPlusCmd p.31 */ 493 EnableBist = (1 << 15), // 8168 8101 494 Mac_dbgo_oe = (1 << 14), // 8168 8101 495 Normal_mode = (1 << 13), // unused 496 Force_half_dup = (1 << 12), // 8168 8101 497 Force_rxflow_en = (1 << 11), // 8168 8101 498 Force_txflow_en = (1 << 10), // 8168 8101 499 Cxpl_dbg_sel = (1 << 9), // 8168 8101 500 ASF = (1 << 8), // 8168 8101 501 PktCntrDisable = (1 << 7), // 8168 8101 502 Mac_dbgo_sel = 0x001c, // 8168 503 RxVlan = (1 << 6), 504 RxChkSum = (1 << 5), 505 PCIDAC = (1 << 4), 506 PCIMulRW = (1 << 3), 507 #define INTT_MASK GENMASK(1, 0) 508 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 509 510 /* rtl8169_PHYstatus */ 511 TBI_Enable = 0x80, 512 TxFlowCtrl = 0x40, 513 RxFlowCtrl = 0x20, 514 _1000bpsF = 0x10, 515 _100bps = 0x08, 516 _10bps = 0x04, 517 LinkStatus = 0x02, 518 FullDup = 0x01, 519 520 /* ResetCounterCommand */ 521 CounterReset = 0x1, 522 523 /* DumpCounterCommand */ 524 CounterDump = 0x8, 525 526 /* magic enable v2 */ 527 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 528 }; 529 530 enum rtl_desc_bit { 531 /* First doubleword. */ 532 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 533 RingEnd = (1 << 30), /* End of descriptor ring */ 534 FirstFrag = (1 << 29), /* First segment of a packet */ 535 LastFrag = (1 << 28), /* Final segment of a packet */ 536 }; 537 538 /* Generic case. */ 539 enum rtl_tx_desc_bit { 540 /* First doubleword. */ 541 TD_LSO = (1 << 27), /* Large Send Offload */ 542 #define TD_MSS_MAX 0x07ffu /* MSS value */ 543 544 /* Second doubleword. */ 545 TxVlanTag = (1 << 17), /* Add VLAN tag */ 546 }; 547 548 /* 8169, 8168b and 810x except 8102e. */ 549 enum rtl_tx_desc_bit_0 { 550 /* First doubleword. */ 551 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 552 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 553 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 554 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 555 }; 556 557 /* 8102e, 8168c and beyond. */ 558 enum rtl_tx_desc_bit_1 { 559 /* First doubleword. */ 560 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 561 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 562 #define GTTCPHO_SHIFT 18 563 #define GTTCPHO_MAX 0x7f 564 565 /* Second doubleword. */ 566 #define TCPHO_SHIFT 18 567 #define TCPHO_MAX 0x3ff 568 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 569 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 570 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 571 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 572 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 573 }; 574 575 enum rtl_rx_desc_bit { 576 /* Rx private */ 577 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 578 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 579 580 #define RxProtoUDP (PID1) 581 #define RxProtoTCP (PID0) 582 #define RxProtoIP (PID1 | PID0) 583 #define RxProtoMask RxProtoIP 584 585 IPFail = (1 << 16), /* IP checksum failed */ 586 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 587 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 588 RxVlanTag = (1 << 16), /* VLAN tag available */ 589 }; 590 591 #define RsvdMask 0x3fffc000 592 593 #define RTL_GSO_MAX_SIZE_V1 32000 594 #define RTL_GSO_MAX_SEGS_V1 24 595 #define RTL_GSO_MAX_SIZE_V2 64000 596 #define RTL_GSO_MAX_SEGS_V2 64 597 598 struct TxDesc { 599 __le32 opts1; 600 __le32 opts2; 601 __le64 addr; 602 }; 603 604 struct RxDesc { 605 __le32 opts1; 606 __le32 opts2; 607 __le64 addr; 608 }; 609 610 struct ring_info { 611 struct sk_buff *skb; 612 u32 len; 613 }; 614 615 struct rtl8169_counters { 616 __le64 tx_packets; 617 __le64 rx_packets; 618 __le64 tx_errors; 619 __le32 rx_errors; 620 __le16 rx_missed; 621 __le16 align_errors; 622 __le32 tx_one_collision; 623 __le32 tx_multi_collision; 624 __le64 rx_unicast; 625 __le64 rx_broadcast; 626 __le32 rx_multicast; 627 __le16 tx_aborted; 628 __le16 tx_underun; 629 }; 630 631 struct rtl8169_tc_offsets { 632 bool inited; 633 __le64 tx_errors; 634 __le32 tx_multi_collision; 635 __le16 tx_aborted; 636 }; 637 638 enum rtl_flag { 639 RTL_FLAG_TASK_ENABLED = 0, 640 RTL_FLAG_TASK_RESET_PENDING, 641 RTL_FLAG_MAX 642 }; 643 644 struct rtl8169_stats { 645 u64 packets; 646 u64 bytes; 647 struct u64_stats_sync syncp; 648 }; 649 650 struct rtl8169_private { 651 void __iomem *mmio_addr; /* memory map physical address */ 652 struct pci_dev *pci_dev; 653 struct net_device *dev; 654 struct phy_device *phydev; 655 struct napi_struct napi; 656 u32 msg_enable; 657 enum mac_version mac_version; 658 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 659 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 660 u32 dirty_tx; 661 struct rtl8169_stats rx_stats; 662 struct rtl8169_stats tx_stats; 663 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 664 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 665 dma_addr_t TxPhyAddr; 666 dma_addr_t RxPhyAddr; 667 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 668 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 669 u16 cp_cmd; 670 u32 irq_mask; 671 struct clk *clk; 672 673 struct { 674 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 675 struct mutex mutex; 676 struct work_struct work; 677 } wk; 678 679 unsigned irq_enabled:1; 680 unsigned supports_gmii:1; 681 unsigned aspm_manageable:1; 682 dma_addr_t counters_phys_addr; 683 struct rtl8169_counters *counters; 684 struct rtl8169_tc_offsets tc_offset; 685 u32 saved_wolopts; 686 int eee_adv; 687 688 const char *fw_name; 689 struct rtl_fw *rtl_fw; 690 691 u32 ocp_base; 692 }; 693 694 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 695 696 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 697 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 698 module_param_named(debug, debug.msg_enable, int, 0); 699 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 700 MODULE_SOFTDEP("pre: realtek"); 701 MODULE_LICENSE("GPL"); 702 MODULE_FIRMWARE(FIRMWARE_8168D_1); 703 MODULE_FIRMWARE(FIRMWARE_8168D_2); 704 MODULE_FIRMWARE(FIRMWARE_8168E_1); 705 MODULE_FIRMWARE(FIRMWARE_8168E_2); 706 MODULE_FIRMWARE(FIRMWARE_8168E_3); 707 MODULE_FIRMWARE(FIRMWARE_8105E_1); 708 MODULE_FIRMWARE(FIRMWARE_8168F_1); 709 MODULE_FIRMWARE(FIRMWARE_8168F_2); 710 MODULE_FIRMWARE(FIRMWARE_8402_1); 711 MODULE_FIRMWARE(FIRMWARE_8411_1); 712 MODULE_FIRMWARE(FIRMWARE_8411_2); 713 MODULE_FIRMWARE(FIRMWARE_8106E_1); 714 MODULE_FIRMWARE(FIRMWARE_8106E_2); 715 MODULE_FIRMWARE(FIRMWARE_8168G_2); 716 MODULE_FIRMWARE(FIRMWARE_8168G_3); 717 MODULE_FIRMWARE(FIRMWARE_8168H_1); 718 MODULE_FIRMWARE(FIRMWARE_8168H_2); 719 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 720 MODULE_FIRMWARE(FIRMWARE_8107E_1); 721 MODULE_FIRMWARE(FIRMWARE_8107E_2); 722 MODULE_FIRMWARE(FIRMWARE_8125A_3); 723 724 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 725 { 726 return &tp->pci_dev->dev; 727 } 728 729 static void rtl_lock_work(struct rtl8169_private *tp) 730 { 731 mutex_lock(&tp->wk.mutex); 732 } 733 734 static void rtl_unlock_work(struct rtl8169_private *tp) 735 { 736 mutex_unlock(&tp->wk.mutex); 737 } 738 739 static void rtl_lock_config_regs(struct rtl8169_private *tp) 740 { 741 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 742 } 743 744 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 745 { 746 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 747 } 748 749 static bool rtl_is_8125(struct rtl8169_private *tp) 750 { 751 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 752 } 753 754 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 755 { 756 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 757 tp->mac_version != RTL_GIGA_MAC_VER_39 && 758 tp->mac_version <= RTL_GIGA_MAC_VER_52; 759 } 760 761 static bool rtl_supports_eee(struct rtl8169_private *tp) 762 { 763 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 764 tp->mac_version != RTL_GIGA_MAC_VER_37 && 765 tp->mac_version != RTL_GIGA_MAC_VER_39; 766 } 767 768 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 769 { 770 int i; 771 772 for (i = 0; i < ETH_ALEN; i++) 773 mac[i] = RTL_R8(tp, reg + i); 774 } 775 776 struct rtl_cond { 777 bool (*check)(struct rtl8169_private *); 778 const char *msg; 779 }; 780 781 static void rtl_udelay(unsigned int d) 782 { 783 udelay(d); 784 } 785 786 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 787 void (*delay)(unsigned int), unsigned int d, int n, 788 bool high) 789 { 790 int i; 791 792 for (i = 0; i < n; i++) { 793 if (c->check(tp) == high) 794 return true; 795 delay(d); 796 } 797 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 798 c->msg, !high, n, d); 799 return false; 800 } 801 802 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 803 const struct rtl_cond *c, 804 unsigned int d, int n) 805 { 806 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 807 } 808 809 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 810 const struct rtl_cond *c, 811 unsigned int d, int n) 812 { 813 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 814 } 815 816 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 817 const struct rtl_cond *c, 818 unsigned int d, int n) 819 { 820 return rtl_loop_wait(tp, c, msleep, d, n, true); 821 } 822 823 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 824 const struct rtl_cond *c, 825 unsigned int d, int n) 826 { 827 return rtl_loop_wait(tp, c, msleep, d, n, false); 828 } 829 830 #define DECLARE_RTL_COND(name) \ 831 static bool name ## _check(struct rtl8169_private *); \ 832 \ 833 static const struct rtl_cond name = { \ 834 .check = name ## _check, \ 835 .msg = #name \ 836 }; \ 837 \ 838 static bool name ## _check(struct rtl8169_private *tp) 839 840 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 841 { 842 if (reg & 0xffff0001) { 843 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 844 return true; 845 } 846 return false; 847 } 848 849 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 850 { 851 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 852 } 853 854 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 855 { 856 if (rtl_ocp_reg_failure(tp, reg)) 857 return; 858 859 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 860 861 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 862 } 863 864 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 865 { 866 if (rtl_ocp_reg_failure(tp, reg)) 867 return 0; 868 869 RTL_W32(tp, GPHY_OCP, reg << 15); 870 871 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 872 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 873 } 874 875 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 876 { 877 if (rtl_ocp_reg_failure(tp, reg)) 878 return; 879 880 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 881 } 882 883 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 884 { 885 if (rtl_ocp_reg_failure(tp, reg)) 886 return 0; 887 888 RTL_W32(tp, OCPDR, reg << 15); 889 890 return RTL_R32(tp, OCPDR); 891 } 892 893 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 894 u16 set) 895 { 896 u16 data = r8168_mac_ocp_read(tp, reg); 897 898 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 899 } 900 901 #define OCP_STD_PHY_BASE 0xa400 902 903 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 904 { 905 if (reg == 0x1f) { 906 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 907 return; 908 } 909 910 if (tp->ocp_base != OCP_STD_PHY_BASE) 911 reg -= 0x10; 912 913 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 914 } 915 916 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 917 { 918 if (reg == 0x1f) 919 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 920 921 if (tp->ocp_base != OCP_STD_PHY_BASE) 922 reg -= 0x10; 923 924 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 925 } 926 927 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 928 { 929 if (reg == 0x1f) { 930 tp->ocp_base = value << 4; 931 return; 932 } 933 934 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 935 } 936 937 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 938 { 939 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 940 } 941 942 DECLARE_RTL_COND(rtl_phyar_cond) 943 { 944 return RTL_R32(tp, PHYAR) & 0x80000000; 945 } 946 947 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 948 { 949 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 950 951 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 952 /* 953 * According to hardware specs a 20us delay is required after write 954 * complete indication, but before sending next command. 955 */ 956 udelay(20); 957 } 958 959 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 960 { 961 int value; 962 963 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 964 965 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 966 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 967 968 /* 969 * According to hardware specs a 20us delay is required after read 970 * complete indication, but before sending next command. 971 */ 972 udelay(20); 973 974 return value; 975 } 976 977 DECLARE_RTL_COND(rtl_ocpar_cond) 978 { 979 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 980 } 981 982 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 983 { 984 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 985 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 986 RTL_W32(tp, EPHY_RXER_NUM, 0); 987 988 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 989 } 990 991 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 992 { 993 r8168dp_1_mdio_access(tp, reg, 994 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 995 } 996 997 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 998 { 999 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 1000 1001 mdelay(1); 1002 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1003 RTL_W32(tp, EPHY_RXER_NUM, 0); 1004 1005 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1006 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1007 } 1008 1009 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1010 1011 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1012 { 1013 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1014 } 1015 1016 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1017 { 1018 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1019 } 1020 1021 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1022 { 1023 r8168dp_2_mdio_start(tp); 1024 1025 r8169_mdio_write(tp, reg, value); 1026 1027 r8168dp_2_mdio_stop(tp); 1028 } 1029 1030 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1031 { 1032 int value; 1033 1034 /* Work around issue with chip reporting wrong PHY ID */ 1035 if (reg == MII_PHYSID2) 1036 return 0xc912; 1037 1038 r8168dp_2_mdio_start(tp); 1039 1040 value = r8169_mdio_read(tp, reg); 1041 1042 r8168dp_2_mdio_stop(tp); 1043 1044 return value; 1045 } 1046 1047 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1048 { 1049 switch (tp->mac_version) { 1050 case RTL_GIGA_MAC_VER_27: 1051 r8168dp_1_mdio_write(tp, location, val); 1052 break; 1053 case RTL_GIGA_MAC_VER_28: 1054 case RTL_GIGA_MAC_VER_31: 1055 r8168dp_2_mdio_write(tp, location, val); 1056 break; 1057 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1058 r8168g_mdio_write(tp, location, val); 1059 break; 1060 default: 1061 r8169_mdio_write(tp, location, val); 1062 break; 1063 } 1064 } 1065 1066 static int rtl_readphy(struct rtl8169_private *tp, int location) 1067 { 1068 switch (tp->mac_version) { 1069 case RTL_GIGA_MAC_VER_27: 1070 return r8168dp_1_mdio_read(tp, location); 1071 case RTL_GIGA_MAC_VER_28: 1072 case RTL_GIGA_MAC_VER_31: 1073 return r8168dp_2_mdio_read(tp, location); 1074 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1075 return r8168g_mdio_read(tp, location); 1076 default: 1077 return r8169_mdio_read(tp, location); 1078 } 1079 } 1080 1081 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) 1082 { 1083 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); 1084 } 1085 1086 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) 1087 { 1088 int val; 1089 1090 val = rtl_readphy(tp, reg_addr); 1091 rtl_writephy(tp, reg_addr, (val & ~m) | p); 1092 } 1093 1094 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage, 1095 int reg, u16 mask, u16 val) 1096 { 1097 int oldpage = phy_select_page(phydev, 0x0007); 1098 1099 __phy_write(phydev, 0x1e, extpage); 1100 __phy_modify(phydev, reg, mask, val); 1101 1102 phy_restore_page(phydev, oldpage, 0); 1103 } 1104 1105 static void r8168d_phy_param(struct phy_device *phydev, u16 parm, 1106 u16 mask, u16 val) 1107 { 1108 int oldpage = phy_select_page(phydev, 0x0005); 1109 1110 __phy_write(phydev, 0x05, parm); 1111 __phy_modify(phydev, 0x06, mask, val); 1112 1113 phy_restore_page(phydev, oldpage, 0); 1114 } 1115 1116 static void r8168g_phy_param(struct phy_device *phydev, u16 parm, 1117 u16 mask, u16 val) 1118 { 1119 int oldpage = phy_select_page(phydev, 0x0a43); 1120 1121 __phy_write(phydev, 0x13, parm); 1122 __phy_modify(phydev, 0x14, mask, val); 1123 1124 phy_restore_page(phydev, oldpage, 0); 1125 } 1126 1127 DECLARE_RTL_COND(rtl_ephyar_cond) 1128 { 1129 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1130 } 1131 1132 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1133 { 1134 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1135 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1136 1137 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1138 1139 udelay(10); 1140 } 1141 1142 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1143 { 1144 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1145 1146 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1147 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1148 } 1149 1150 DECLARE_RTL_COND(rtl_eriar_cond) 1151 { 1152 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1153 } 1154 1155 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1156 u32 val, int type) 1157 { 1158 BUG_ON((addr & 3) || (mask == 0)); 1159 RTL_W32(tp, ERIDR, val); 1160 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1161 1162 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1163 } 1164 1165 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1166 u32 val) 1167 { 1168 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1169 } 1170 1171 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1172 { 1173 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1174 1175 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1176 RTL_R32(tp, ERIDR) : ~0; 1177 } 1178 1179 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1180 { 1181 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1182 } 1183 1184 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1185 u32 m) 1186 { 1187 u32 val; 1188 1189 val = rtl_eri_read(tp, addr); 1190 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1191 } 1192 1193 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1194 u32 p) 1195 { 1196 rtl_w0w1_eri(tp, addr, mask, p, 0); 1197 } 1198 1199 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1200 u32 m) 1201 { 1202 rtl_w0w1_eri(tp, addr, mask, 0, m); 1203 } 1204 1205 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1206 { 1207 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1208 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1209 RTL_R32(tp, OCPDR) : ~0; 1210 } 1211 1212 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1213 { 1214 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1215 } 1216 1217 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1218 u32 data) 1219 { 1220 RTL_W32(tp, OCPDR, data); 1221 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1222 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1223 } 1224 1225 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1226 u32 data) 1227 { 1228 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1229 data, ERIAR_OOB); 1230 } 1231 1232 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1233 { 1234 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1235 1236 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1237 } 1238 1239 #define OOB_CMD_RESET 0x00 1240 #define OOB_CMD_DRIVER_START 0x05 1241 #define OOB_CMD_DRIVER_STOP 0x06 1242 1243 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1244 { 1245 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1246 } 1247 1248 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1249 { 1250 u16 reg; 1251 1252 reg = rtl8168_get_ocp_reg(tp); 1253 1254 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1255 } 1256 1257 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1258 { 1259 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1260 } 1261 1262 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1263 { 1264 return RTL_R8(tp, IBISR0) & 0x20; 1265 } 1266 1267 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1268 { 1269 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1270 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1271 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1272 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1273 } 1274 1275 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1276 { 1277 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1278 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1279 } 1280 1281 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1282 { 1283 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1284 r8168ep_ocp_write(tp, 0x01, 0x30, 1285 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1286 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1287 } 1288 1289 static void rtl8168_driver_start(struct rtl8169_private *tp) 1290 { 1291 switch (tp->mac_version) { 1292 case RTL_GIGA_MAC_VER_27: 1293 case RTL_GIGA_MAC_VER_28: 1294 case RTL_GIGA_MAC_VER_31: 1295 rtl8168dp_driver_start(tp); 1296 break; 1297 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1298 rtl8168ep_driver_start(tp); 1299 break; 1300 default: 1301 BUG(); 1302 break; 1303 } 1304 } 1305 1306 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1307 { 1308 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1309 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1310 } 1311 1312 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1313 { 1314 rtl8168ep_stop_cmac(tp); 1315 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1316 r8168ep_ocp_write(tp, 0x01, 0x30, 1317 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1318 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1319 } 1320 1321 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1322 { 1323 switch (tp->mac_version) { 1324 case RTL_GIGA_MAC_VER_27: 1325 case RTL_GIGA_MAC_VER_28: 1326 case RTL_GIGA_MAC_VER_31: 1327 rtl8168dp_driver_stop(tp); 1328 break; 1329 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1330 rtl8168ep_driver_stop(tp); 1331 break; 1332 default: 1333 BUG(); 1334 break; 1335 } 1336 } 1337 1338 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1339 { 1340 u16 reg = rtl8168_get_ocp_reg(tp); 1341 1342 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1343 } 1344 1345 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1346 { 1347 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1348 } 1349 1350 static bool r8168_check_dash(struct rtl8169_private *tp) 1351 { 1352 switch (tp->mac_version) { 1353 case RTL_GIGA_MAC_VER_27: 1354 case RTL_GIGA_MAC_VER_28: 1355 case RTL_GIGA_MAC_VER_31: 1356 return r8168dp_check_dash(tp); 1357 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1358 return r8168ep_check_dash(tp); 1359 default: 1360 return false; 1361 } 1362 } 1363 1364 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1365 { 1366 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1367 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1368 } 1369 1370 DECLARE_RTL_COND(rtl_efusear_cond) 1371 { 1372 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1373 } 1374 1375 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1376 { 1377 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1378 1379 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1380 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1381 } 1382 1383 static u32 rtl_get_events(struct rtl8169_private *tp) 1384 { 1385 if (rtl_is_8125(tp)) 1386 return RTL_R32(tp, IntrStatus_8125); 1387 else 1388 return RTL_R16(tp, IntrStatus); 1389 } 1390 1391 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1392 { 1393 if (rtl_is_8125(tp)) 1394 RTL_W32(tp, IntrStatus_8125, bits); 1395 else 1396 RTL_W16(tp, IntrStatus, bits); 1397 } 1398 1399 static void rtl_irq_disable(struct rtl8169_private *tp) 1400 { 1401 if (rtl_is_8125(tp)) 1402 RTL_W32(tp, IntrMask_8125, 0); 1403 else 1404 RTL_W16(tp, IntrMask, 0); 1405 tp->irq_enabled = 0; 1406 } 1407 1408 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) 1409 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) 1410 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) 1411 1412 static void rtl_irq_enable(struct rtl8169_private *tp) 1413 { 1414 tp->irq_enabled = 1; 1415 if (rtl_is_8125(tp)) 1416 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1417 else 1418 RTL_W16(tp, IntrMask, tp->irq_mask); 1419 } 1420 1421 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1422 { 1423 rtl_irq_disable(tp); 1424 rtl_ack_events(tp, 0xffffffff); 1425 /* PCI commit */ 1426 RTL_R8(tp, ChipCmd); 1427 } 1428 1429 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1430 { 1431 struct net_device *dev = tp->dev; 1432 struct phy_device *phydev = tp->phydev; 1433 1434 if (!netif_running(dev)) 1435 return; 1436 1437 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1438 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1439 if (phydev->speed == SPEED_1000) { 1440 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1441 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1442 } else if (phydev->speed == SPEED_100) { 1443 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1444 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1445 } else { 1446 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1447 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1448 } 1449 rtl_reset_packet_filter(tp); 1450 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1451 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1452 if (phydev->speed == SPEED_1000) { 1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1454 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1455 } else { 1456 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1457 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1458 } 1459 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1460 if (phydev->speed == SPEED_10) { 1461 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1462 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1463 } else { 1464 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1465 } 1466 } 1467 } 1468 1469 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1470 1471 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1472 { 1473 struct rtl8169_private *tp = netdev_priv(dev); 1474 1475 rtl_lock_work(tp); 1476 wol->supported = WAKE_ANY; 1477 wol->wolopts = tp->saved_wolopts; 1478 rtl_unlock_work(tp); 1479 } 1480 1481 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1482 { 1483 static const struct { 1484 u32 opt; 1485 u16 reg; 1486 u8 mask; 1487 } cfg[] = { 1488 { WAKE_PHY, Config3, LinkUp }, 1489 { WAKE_UCAST, Config5, UWF }, 1490 { WAKE_BCAST, Config5, BWF }, 1491 { WAKE_MCAST, Config5, MWF }, 1492 { WAKE_ANY, Config5, LanWake }, 1493 { WAKE_MAGIC, Config3, MagicPacket } 1494 }; 1495 unsigned int i, tmp = ARRAY_SIZE(cfg); 1496 u8 options; 1497 1498 rtl_unlock_config_regs(tp); 1499 1500 if (rtl_is_8168evl_up(tp)) { 1501 tmp--; 1502 if (wolopts & WAKE_MAGIC) 1503 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1504 MagicPacket_v2); 1505 else 1506 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1507 MagicPacket_v2); 1508 } else if (rtl_is_8125(tp)) { 1509 tmp--; 1510 if (wolopts & WAKE_MAGIC) 1511 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1512 else 1513 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1514 } 1515 1516 for (i = 0; i < tmp; i++) { 1517 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1518 if (wolopts & cfg[i].opt) 1519 options |= cfg[i].mask; 1520 RTL_W8(tp, cfg[i].reg, options); 1521 } 1522 1523 switch (tp->mac_version) { 1524 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1525 options = RTL_R8(tp, Config1) & ~PMEnable; 1526 if (wolopts) 1527 options |= PMEnable; 1528 RTL_W8(tp, Config1, options); 1529 break; 1530 case RTL_GIGA_MAC_VER_34: 1531 case RTL_GIGA_MAC_VER_37: 1532 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52: 1533 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1534 if (wolopts) 1535 options |= PME_SIGNAL; 1536 RTL_W8(tp, Config2, options); 1537 break; 1538 default: 1539 break; 1540 } 1541 1542 rtl_lock_config_regs(tp); 1543 1544 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1545 tp->dev->wol_enabled = wolopts ? 1 : 0; 1546 } 1547 1548 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1549 { 1550 struct rtl8169_private *tp = netdev_priv(dev); 1551 struct device *d = tp_to_dev(tp); 1552 1553 if (wol->wolopts & ~WAKE_ANY) 1554 return -EINVAL; 1555 1556 pm_runtime_get_noresume(d); 1557 1558 rtl_lock_work(tp); 1559 1560 tp->saved_wolopts = wol->wolopts; 1561 1562 if (pm_runtime_active(d)) 1563 __rtl8169_set_wol(tp, tp->saved_wolopts); 1564 1565 rtl_unlock_work(tp); 1566 1567 pm_runtime_put_noidle(d); 1568 1569 return 0; 1570 } 1571 1572 static void rtl8169_get_drvinfo(struct net_device *dev, 1573 struct ethtool_drvinfo *info) 1574 { 1575 struct rtl8169_private *tp = netdev_priv(dev); 1576 struct rtl_fw *rtl_fw = tp->rtl_fw; 1577 1578 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1579 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1580 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1581 if (rtl_fw) 1582 strlcpy(info->fw_version, rtl_fw->version, 1583 sizeof(info->fw_version)); 1584 } 1585 1586 static int rtl8169_get_regs_len(struct net_device *dev) 1587 { 1588 return R8169_REGS_SIZE; 1589 } 1590 1591 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1592 netdev_features_t features) 1593 { 1594 struct rtl8169_private *tp = netdev_priv(dev); 1595 1596 if (dev->mtu > TD_MSS_MAX) 1597 features &= ~NETIF_F_ALL_TSO; 1598 1599 if (dev->mtu > JUMBO_1K && 1600 tp->mac_version > RTL_GIGA_MAC_VER_06) 1601 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1602 1603 return features; 1604 } 1605 1606 static int rtl8169_set_features(struct net_device *dev, 1607 netdev_features_t features) 1608 { 1609 struct rtl8169_private *tp = netdev_priv(dev); 1610 u32 rx_config; 1611 1612 rtl_lock_work(tp); 1613 1614 rx_config = RTL_R32(tp, RxConfig); 1615 if (features & NETIF_F_RXALL) 1616 rx_config |= (AcceptErr | AcceptRunt); 1617 else 1618 rx_config &= ~(AcceptErr | AcceptRunt); 1619 1620 if (rtl_is_8125(tp)) { 1621 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1622 rx_config |= RX_VLAN_8125; 1623 else 1624 rx_config &= ~RX_VLAN_8125; 1625 } 1626 1627 RTL_W32(tp, RxConfig, rx_config); 1628 1629 if (features & NETIF_F_RXCSUM) 1630 tp->cp_cmd |= RxChkSum; 1631 else 1632 tp->cp_cmd &= ~RxChkSum; 1633 1634 if (!rtl_is_8125(tp)) { 1635 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1636 tp->cp_cmd |= RxVlan; 1637 else 1638 tp->cp_cmd &= ~RxVlan; 1639 } 1640 1641 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1642 RTL_R16(tp, CPlusCmd); 1643 1644 rtl_unlock_work(tp); 1645 1646 return 0; 1647 } 1648 1649 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1650 { 1651 return (skb_vlan_tag_present(skb)) ? 1652 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1653 } 1654 1655 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1656 { 1657 u32 opts2 = le32_to_cpu(desc->opts2); 1658 1659 if (opts2 & RxVlanTag) 1660 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1661 } 1662 1663 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1664 void *p) 1665 { 1666 struct rtl8169_private *tp = netdev_priv(dev); 1667 u32 __iomem *data = tp->mmio_addr; 1668 u32 *dw = p; 1669 int i; 1670 1671 rtl_lock_work(tp); 1672 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1673 memcpy_fromio(dw++, data++, 4); 1674 rtl_unlock_work(tp); 1675 } 1676 1677 static u32 rtl8169_get_msglevel(struct net_device *dev) 1678 { 1679 struct rtl8169_private *tp = netdev_priv(dev); 1680 1681 return tp->msg_enable; 1682 } 1683 1684 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1685 { 1686 struct rtl8169_private *tp = netdev_priv(dev); 1687 1688 tp->msg_enable = value; 1689 } 1690 1691 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1692 "tx_packets", 1693 "rx_packets", 1694 "tx_errors", 1695 "rx_errors", 1696 "rx_missed", 1697 "align_errors", 1698 "tx_single_collisions", 1699 "tx_multi_collisions", 1700 "unicast", 1701 "broadcast", 1702 "multicast", 1703 "tx_aborted", 1704 "tx_underrun", 1705 }; 1706 1707 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1708 { 1709 switch (sset) { 1710 case ETH_SS_STATS: 1711 return ARRAY_SIZE(rtl8169_gstrings); 1712 default: 1713 return -EOPNOTSUPP; 1714 } 1715 } 1716 1717 DECLARE_RTL_COND(rtl_counters_cond) 1718 { 1719 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1720 } 1721 1722 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1723 { 1724 dma_addr_t paddr = tp->counters_phys_addr; 1725 u32 cmd; 1726 1727 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1728 RTL_R32(tp, CounterAddrHigh); 1729 cmd = (u64)paddr & DMA_BIT_MASK(32); 1730 RTL_W32(tp, CounterAddrLow, cmd); 1731 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1732 1733 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1734 } 1735 1736 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1737 { 1738 /* 1739 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1740 * tally counters. 1741 */ 1742 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1743 return true; 1744 1745 return rtl8169_do_counters(tp, CounterReset); 1746 } 1747 1748 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1749 { 1750 u8 val = RTL_R8(tp, ChipCmd); 1751 1752 /* 1753 * Some chips are unable to dump tally counters when the receiver 1754 * is disabled. If 0xff chip may be in a PCI power-save state. 1755 */ 1756 if (!(val & CmdRxEnb) || val == 0xff) 1757 return true; 1758 1759 return rtl8169_do_counters(tp, CounterDump); 1760 } 1761 1762 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1763 { 1764 struct rtl8169_counters *counters = tp->counters; 1765 bool ret = false; 1766 1767 /* 1768 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1769 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1770 * reset by a power cycle, while the counter values collected by the 1771 * driver are reset at every driver unload/load cycle. 1772 * 1773 * To make sure the HW values returned by @get_stats64 match the SW 1774 * values, we collect the initial values at first open(*) and use them 1775 * as offsets to normalize the values returned by @get_stats64. 1776 * 1777 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1778 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1779 * set at open time by rtl_hw_start. 1780 */ 1781 1782 if (tp->tc_offset.inited) 1783 return true; 1784 1785 /* If both, reset and update fail, propagate to caller. */ 1786 if (rtl8169_reset_counters(tp)) 1787 ret = true; 1788 1789 if (rtl8169_update_counters(tp)) 1790 ret = true; 1791 1792 tp->tc_offset.tx_errors = counters->tx_errors; 1793 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1794 tp->tc_offset.tx_aborted = counters->tx_aborted; 1795 tp->tc_offset.inited = true; 1796 1797 return ret; 1798 } 1799 1800 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1801 struct ethtool_stats *stats, u64 *data) 1802 { 1803 struct rtl8169_private *tp = netdev_priv(dev); 1804 struct device *d = tp_to_dev(tp); 1805 struct rtl8169_counters *counters = tp->counters; 1806 1807 ASSERT_RTNL(); 1808 1809 pm_runtime_get_noresume(d); 1810 1811 if (pm_runtime_active(d)) 1812 rtl8169_update_counters(tp); 1813 1814 pm_runtime_put_noidle(d); 1815 1816 data[0] = le64_to_cpu(counters->tx_packets); 1817 data[1] = le64_to_cpu(counters->rx_packets); 1818 data[2] = le64_to_cpu(counters->tx_errors); 1819 data[3] = le32_to_cpu(counters->rx_errors); 1820 data[4] = le16_to_cpu(counters->rx_missed); 1821 data[5] = le16_to_cpu(counters->align_errors); 1822 data[6] = le32_to_cpu(counters->tx_one_collision); 1823 data[7] = le32_to_cpu(counters->tx_multi_collision); 1824 data[8] = le64_to_cpu(counters->rx_unicast); 1825 data[9] = le64_to_cpu(counters->rx_broadcast); 1826 data[10] = le32_to_cpu(counters->rx_multicast); 1827 data[11] = le16_to_cpu(counters->tx_aborted); 1828 data[12] = le16_to_cpu(counters->tx_underun); 1829 } 1830 1831 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1832 { 1833 switch(stringset) { 1834 case ETH_SS_STATS: 1835 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1836 break; 1837 } 1838 } 1839 1840 /* 1841 * Interrupt coalescing 1842 * 1843 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1844 * > 8169, 8168 and 810x line of chipsets 1845 * 1846 * 8169, 8168, and 8136(810x) serial chipsets support it. 1847 * 1848 * > 2 - the Tx timer unit at gigabit speed 1849 * 1850 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1851 * (0xe0) bit 1 and bit 0. 1852 * 1853 * For 8169 1854 * bit[1:0] \ speed 1000M 100M 10M 1855 * 0 0 320ns 2.56us 40.96us 1856 * 0 1 2.56us 20.48us 327.7us 1857 * 1 0 5.12us 40.96us 655.4us 1858 * 1 1 10.24us 81.92us 1.31ms 1859 * 1860 * For the other 1861 * bit[1:0] \ speed 1000M 100M 10M 1862 * 0 0 5us 2.56us 40.96us 1863 * 0 1 40us 20.48us 327.7us 1864 * 1 0 80us 40.96us 655.4us 1865 * 1 1 160us 81.92us 1.31ms 1866 */ 1867 1868 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1869 struct rtl_coalesce_scale { 1870 /* Rx / Tx */ 1871 u32 nsecs[2]; 1872 }; 1873 1874 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1875 struct rtl_coalesce_info { 1876 u32 speed; 1877 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1878 }; 1879 1880 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1881 #define rxtx_x1822(r, t) { \ 1882 {{(r), (t)}}, \ 1883 {{(r)*8, (t)*8}}, \ 1884 {{(r)*8*2, (t)*8*2}}, \ 1885 {{(r)*8*2*2, (t)*8*2*2}}, \ 1886 } 1887 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1888 /* speed delays: rx00 tx00 */ 1889 { SPEED_10, rxtx_x1822(40960, 40960) }, 1890 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1891 { SPEED_1000, rxtx_x1822( 320, 320) }, 1892 { 0 }, 1893 }; 1894 1895 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1896 /* speed delays: rx00 tx00 */ 1897 { SPEED_10, rxtx_x1822(40960, 40960) }, 1898 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1899 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1900 { 0 }, 1901 }; 1902 #undef rxtx_x1822 1903 1904 /* get rx/tx scale vector corresponding to current speed */ 1905 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1906 { 1907 struct rtl8169_private *tp = netdev_priv(dev); 1908 const struct rtl_coalesce_info *ci; 1909 1910 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1911 ci = rtl_coalesce_info_8169; 1912 else 1913 ci = rtl_coalesce_info_8168_8136; 1914 1915 for (; ci->speed; ci++) { 1916 if (tp->phydev->speed == ci->speed) 1917 return ci; 1918 } 1919 1920 return ERR_PTR(-ELNRNG); 1921 } 1922 1923 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1924 { 1925 struct rtl8169_private *tp = netdev_priv(dev); 1926 const struct rtl_coalesce_info *ci; 1927 const struct rtl_coalesce_scale *scale; 1928 struct { 1929 u32 *max_frames; 1930 u32 *usecs; 1931 } coal_settings [] = { 1932 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1933 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1934 }, *p = coal_settings; 1935 int i; 1936 u16 w; 1937 1938 if (rtl_is_8125(tp)) 1939 return -EOPNOTSUPP; 1940 1941 memset(ec, 0, sizeof(*ec)); 1942 1943 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1944 ci = rtl_coalesce_info(dev); 1945 if (IS_ERR(ci)) 1946 return PTR_ERR(ci); 1947 1948 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1949 1950 /* read IntrMitigate and adjust according to scale */ 1951 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1952 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1953 w >>= RTL_COALESCE_SHIFT; 1954 *p->usecs = w & RTL_COALESCE_MASK; 1955 } 1956 1957 for (i = 0; i < 2; i++) { 1958 p = coal_settings + i; 1959 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1960 1961 /* 1962 * ethtool_coalesce says it is illegal to set both usecs and 1963 * max_frames to 0. 1964 */ 1965 if (!*p->usecs && !*p->max_frames) 1966 *p->max_frames = 1; 1967 } 1968 1969 return 0; 1970 } 1971 1972 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1973 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1974 struct net_device *dev, u32 nsec, u16 *cp01) 1975 { 1976 const struct rtl_coalesce_info *ci; 1977 u16 i; 1978 1979 ci = rtl_coalesce_info(dev); 1980 if (IS_ERR(ci)) 1981 return ERR_CAST(ci); 1982 1983 for (i = 0; i < 4; i++) { 1984 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1985 ci->scalev[i].nsecs[1]); 1986 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1987 *cp01 = i; 1988 return &ci->scalev[i]; 1989 } 1990 } 1991 1992 return ERR_PTR(-EINVAL); 1993 } 1994 1995 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1996 { 1997 struct rtl8169_private *tp = netdev_priv(dev); 1998 const struct rtl_coalesce_scale *scale; 1999 struct { 2000 u32 frames; 2001 u32 usecs; 2002 } coal_settings [] = { 2003 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 2004 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 2005 }, *p = coal_settings; 2006 u16 w = 0, cp01; 2007 int i; 2008 2009 if (rtl_is_8125(tp)) 2010 return -EOPNOTSUPP; 2011 2012 scale = rtl_coalesce_choose_scale(dev, 2013 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 2014 if (IS_ERR(scale)) 2015 return PTR_ERR(scale); 2016 2017 for (i = 0; i < 2; i++, p++) { 2018 u32 units; 2019 2020 /* 2021 * accept max_frames=1 we returned in rtl_get_coalesce. 2022 * accept it not only when usecs=0 because of e.g. the following scenario: 2023 * 2024 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2025 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2026 * - then user does `ethtool -C eth0 rx-usecs 100` 2027 * 2028 * since ethtool sends to kernel whole ethtool_coalesce 2029 * settings, if we do not handle rx_usecs=!0, rx_frames=1 2030 * we'll reject it below in `frames % 4 != 0`. 2031 */ 2032 if (p->frames == 1) { 2033 p->frames = 0; 2034 } 2035 2036 units = p->usecs * 1000 / scale->nsecs[i]; 2037 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 2038 return -EINVAL; 2039 2040 w <<= RTL_COALESCE_SHIFT; 2041 w |= units; 2042 w <<= RTL_COALESCE_SHIFT; 2043 w |= p->frames >> 2; 2044 } 2045 2046 rtl_lock_work(tp); 2047 2048 RTL_W16(tp, IntrMitigate, swab16(w)); 2049 2050 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2051 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2052 RTL_R16(tp, CPlusCmd); 2053 2054 rtl_unlock_work(tp); 2055 2056 return 0; 2057 } 2058 2059 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 2060 { 2061 struct rtl8169_private *tp = netdev_priv(dev); 2062 struct device *d = tp_to_dev(tp); 2063 int ret; 2064 2065 if (!rtl_supports_eee(tp)) 2066 return -EOPNOTSUPP; 2067 2068 pm_runtime_get_noresume(d); 2069 2070 if (!pm_runtime_active(d)) { 2071 ret = -EOPNOTSUPP; 2072 } else { 2073 ret = phy_ethtool_get_eee(tp->phydev, data); 2074 } 2075 2076 pm_runtime_put_noidle(d); 2077 2078 return ret; 2079 } 2080 2081 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 2082 { 2083 struct rtl8169_private *tp = netdev_priv(dev); 2084 struct device *d = tp_to_dev(tp); 2085 int ret; 2086 2087 if (!rtl_supports_eee(tp)) 2088 return -EOPNOTSUPP; 2089 2090 pm_runtime_get_noresume(d); 2091 2092 if (!pm_runtime_active(d)) { 2093 ret = -EOPNOTSUPP; 2094 goto out; 2095 } 2096 2097 if (dev->phydev->autoneg == AUTONEG_DISABLE || 2098 dev->phydev->duplex != DUPLEX_FULL) { 2099 ret = -EPROTONOSUPPORT; 2100 goto out; 2101 } 2102 2103 ret = phy_ethtool_set_eee(tp->phydev, data); 2104 2105 if (!ret) 2106 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 2107 MDIO_AN_EEE_ADV); 2108 out: 2109 pm_runtime_put_noidle(d); 2110 return ret; 2111 } 2112 2113 static const struct ethtool_ops rtl8169_ethtool_ops = { 2114 .get_drvinfo = rtl8169_get_drvinfo, 2115 .get_regs_len = rtl8169_get_regs_len, 2116 .get_link = ethtool_op_get_link, 2117 .get_coalesce = rtl_get_coalesce, 2118 .set_coalesce = rtl_set_coalesce, 2119 .get_msglevel = rtl8169_get_msglevel, 2120 .set_msglevel = rtl8169_set_msglevel, 2121 .get_regs = rtl8169_get_regs, 2122 .get_wol = rtl8169_get_wol, 2123 .set_wol = rtl8169_set_wol, 2124 .get_strings = rtl8169_get_strings, 2125 .get_sset_count = rtl8169_get_sset_count, 2126 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2127 .get_ts_info = ethtool_op_get_ts_info, 2128 .nway_reset = phy_ethtool_nway_reset, 2129 .get_eee = rtl8169_get_eee, 2130 .set_eee = rtl8169_set_eee, 2131 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2132 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2133 }; 2134 2135 static void rtl_enable_eee(struct rtl8169_private *tp) 2136 { 2137 struct phy_device *phydev = tp->phydev; 2138 int adv; 2139 2140 /* respect EEE advertisement the user may have set */ 2141 if (tp->eee_adv >= 0) 2142 adv = tp->eee_adv; 2143 else 2144 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2145 2146 if (adv >= 0) 2147 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2148 } 2149 2150 static void rtl8169_get_mac_version(struct rtl8169_private *tp) 2151 { 2152 /* 2153 * The driver currently handles the 8168Bf and the 8168Be identically 2154 * but they can be identified more specifically through the test below 2155 * if needed: 2156 * 2157 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2158 * 2159 * Same thing for the 8101Eb and the 8101Ec: 2160 * 2161 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2162 */ 2163 static const struct rtl_mac_info { 2164 u16 mask; 2165 u16 val; 2166 u16 mac_version; 2167 } mac_info[] = { 2168 /* 8125 family. */ 2169 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2170 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2171 2172 /* RTL8117 */ 2173 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2174 2175 /* 8168EP family. */ 2176 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2177 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2178 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2179 2180 /* 8168H family. */ 2181 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2182 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2183 2184 /* 8168G family. */ 2185 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2186 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2187 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2188 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2189 2190 /* 8168F family. */ 2191 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2192 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2193 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2194 2195 /* 8168E family. */ 2196 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2197 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2198 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2199 2200 /* 8168D family. */ 2201 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2202 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2203 2204 /* 8168DP family. */ 2205 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2206 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2207 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2208 2209 /* 8168C family. */ 2210 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2211 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2212 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2213 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2214 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2215 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2216 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2217 2218 /* 8168B family. */ 2219 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2220 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2221 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2222 2223 /* 8101 family. */ 2224 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2225 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2226 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2227 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2228 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2229 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2230 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2231 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2232 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2233 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2234 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2235 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2236 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2237 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2238 /* FIXME: where did these entries come from ? -- FR */ 2239 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2240 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2241 2242 /* 8110 family. */ 2243 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2244 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2245 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2246 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2247 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2248 2249 /* Catch-all */ 2250 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2251 }; 2252 const struct rtl_mac_info *p = mac_info; 2253 u16 reg = RTL_R32(tp, TxConfig) >> 20; 2254 2255 while ((reg & p->mask) != p->val) 2256 p++; 2257 tp->mac_version = p->mac_version; 2258 2259 if (tp->mac_version == RTL_GIGA_MAC_NONE) { 2260 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf); 2261 } else if (!tp->supports_gmii) { 2262 if (tp->mac_version == RTL_GIGA_MAC_VER_42) 2263 tp->mac_version = RTL_GIGA_MAC_VER_43; 2264 else if (tp->mac_version == RTL_GIGA_MAC_VER_45) 2265 tp->mac_version = RTL_GIGA_MAC_VER_47; 2266 else if (tp->mac_version == RTL_GIGA_MAC_VER_46) 2267 tp->mac_version = RTL_GIGA_MAC_VER_48; 2268 } 2269 } 2270 2271 struct phy_reg { 2272 u16 reg; 2273 u16 val; 2274 }; 2275 2276 static void __rtl_writephy_batch(struct rtl8169_private *tp, 2277 const struct phy_reg *regs, int len) 2278 { 2279 while (len-- > 0) { 2280 rtl_writephy(tp, regs->reg, regs->val); 2281 regs++; 2282 } 2283 } 2284 2285 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a)) 2286 2287 static void rtl_release_firmware(struct rtl8169_private *tp) 2288 { 2289 if (tp->rtl_fw) { 2290 rtl_fw_release_firmware(tp->rtl_fw); 2291 kfree(tp->rtl_fw); 2292 tp->rtl_fw = NULL; 2293 } 2294 } 2295 2296 static void rtl_apply_firmware(struct rtl8169_private *tp) 2297 { 2298 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2299 if (tp->rtl_fw) 2300 rtl_fw_write_firmware(tp, tp->rtl_fw); 2301 } 2302 2303 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2304 { 2305 /* Adjust EEE LED frequency */ 2306 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2307 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2308 2309 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2310 } 2311 2312 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2313 { 2314 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2315 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2316 } 2317 2318 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp) 2319 { 2320 struct phy_device *phydev = tp->phydev; 2321 2322 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8)); 2323 r8168d_phy_param(phydev, 0x8b85, 0, BIT(13)); 2324 } 2325 2326 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp) 2327 { 2328 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4)); 2329 } 2330 2331 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp) 2332 { 2333 struct phy_device *phydev = tp->phydev; 2334 2335 rtl8168g_config_eee_phy(tp); 2336 2337 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 2338 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 2339 } 2340 2341 static void rtl8125_config_eee_phy(struct rtl8169_private *tp) 2342 { 2343 struct phy_device *phydev = tp->phydev; 2344 2345 rtl8168h_config_eee_phy(tp); 2346 2347 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 2348 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 2349 } 2350 2351 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) 2352 { 2353 static const struct phy_reg phy_reg_init[] = { 2354 { 0x1f, 0x0001 }, 2355 { 0x06, 0x006e }, 2356 { 0x08, 0x0708 }, 2357 { 0x15, 0x4000 }, 2358 { 0x18, 0x65c7 }, 2359 2360 { 0x1f, 0x0001 }, 2361 { 0x03, 0x00a1 }, 2362 { 0x02, 0x0008 }, 2363 { 0x01, 0x0120 }, 2364 { 0x00, 0x1000 }, 2365 { 0x04, 0x0800 }, 2366 { 0x04, 0x0000 }, 2367 2368 { 0x03, 0xff41 }, 2369 { 0x02, 0xdf60 }, 2370 { 0x01, 0x0140 }, 2371 { 0x00, 0x0077 }, 2372 { 0x04, 0x7800 }, 2373 { 0x04, 0x7000 }, 2374 2375 { 0x03, 0x802f }, 2376 { 0x02, 0x4f02 }, 2377 { 0x01, 0x0409 }, 2378 { 0x00, 0xf0f9 }, 2379 { 0x04, 0x9800 }, 2380 { 0x04, 0x9000 }, 2381 2382 { 0x03, 0xdf01 }, 2383 { 0x02, 0xdf20 }, 2384 { 0x01, 0xff95 }, 2385 { 0x00, 0xba00 }, 2386 { 0x04, 0xa800 }, 2387 { 0x04, 0xa000 }, 2388 2389 { 0x03, 0xff41 }, 2390 { 0x02, 0xdf20 }, 2391 { 0x01, 0x0140 }, 2392 { 0x00, 0x00bb }, 2393 { 0x04, 0xb800 }, 2394 { 0x04, 0xb000 }, 2395 2396 { 0x03, 0xdf41 }, 2397 { 0x02, 0xdc60 }, 2398 { 0x01, 0x6340 }, 2399 { 0x00, 0x007d }, 2400 { 0x04, 0xd800 }, 2401 { 0x04, 0xd000 }, 2402 2403 { 0x03, 0xdf01 }, 2404 { 0x02, 0xdf20 }, 2405 { 0x01, 0x100a }, 2406 { 0x00, 0xa0ff }, 2407 { 0x04, 0xf800 }, 2408 { 0x04, 0xf000 }, 2409 2410 { 0x1f, 0x0000 }, 2411 { 0x0b, 0x0000 }, 2412 { 0x00, 0x9200 } 2413 }; 2414 2415 rtl_writephy_batch(tp, phy_reg_init); 2416 } 2417 2418 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) 2419 { 2420 phy_write_paged(tp->phydev, 0x0002, 0x01, 0x90d0); 2421 } 2422 2423 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) 2424 { 2425 struct pci_dev *pdev = tp->pci_dev; 2426 2427 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || 2428 (pdev->subsystem_device != 0xe000)) 2429 return; 2430 2431 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2432 } 2433 2434 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) 2435 { 2436 static const struct phy_reg phy_reg_init[] = { 2437 { 0x1f, 0x0001 }, 2438 { 0x04, 0x0000 }, 2439 { 0x03, 0x00a1 }, 2440 { 0x02, 0x0008 }, 2441 { 0x01, 0x0120 }, 2442 { 0x00, 0x1000 }, 2443 { 0x04, 0x0800 }, 2444 { 0x04, 0x9000 }, 2445 { 0x03, 0x802f }, 2446 { 0x02, 0x4f02 }, 2447 { 0x01, 0x0409 }, 2448 { 0x00, 0xf099 }, 2449 { 0x04, 0x9800 }, 2450 { 0x04, 0xa000 }, 2451 { 0x03, 0xdf01 }, 2452 { 0x02, 0xdf20 }, 2453 { 0x01, 0xff95 }, 2454 { 0x00, 0xba00 }, 2455 { 0x04, 0xa800 }, 2456 { 0x04, 0xf000 }, 2457 { 0x03, 0xdf01 }, 2458 { 0x02, 0xdf20 }, 2459 { 0x01, 0x101a }, 2460 { 0x00, 0xa0ff }, 2461 { 0x04, 0xf800 }, 2462 { 0x04, 0x0000 }, 2463 { 0x1f, 0x0000 }, 2464 2465 { 0x1f, 0x0001 }, 2466 { 0x10, 0xf41b }, 2467 { 0x14, 0xfb54 }, 2468 { 0x18, 0xf5c7 }, 2469 { 0x1f, 0x0000 }, 2470 2471 { 0x1f, 0x0001 }, 2472 { 0x17, 0x0cc0 }, 2473 { 0x1f, 0x0000 } 2474 }; 2475 2476 rtl_writephy_batch(tp, phy_reg_init); 2477 2478 rtl8169scd_hw_phy_config_quirk(tp); 2479 } 2480 2481 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) 2482 { 2483 static const struct phy_reg phy_reg_init[] = { 2484 { 0x1f, 0x0001 }, 2485 { 0x04, 0x0000 }, 2486 { 0x03, 0x00a1 }, 2487 { 0x02, 0x0008 }, 2488 { 0x01, 0x0120 }, 2489 { 0x00, 0x1000 }, 2490 { 0x04, 0x0800 }, 2491 { 0x04, 0x9000 }, 2492 { 0x03, 0x802f }, 2493 { 0x02, 0x4f02 }, 2494 { 0x01, 0x0409 }, 2495 { 0x00, 0xf099 }, 2496 { 0x04, 0x9800 }, 2497 { 0x04, 0xa000 }, 2498 { 0x03, 0xdf01 }, 2499 { 0x02, 0xdf20 }, 2500 { 0x01, 0xff95 }, 2501 { 0x00, 0xba00 }, 2502 { 0x04, 0xa800 }, 2503 { 0x04, 0xf000 }, 2504 { 0x03, 0xdf01 }, 2505 { 0x02, 0xdf20 }, 2506 { 0x01, 0x101a }, 2507 { 0x00, 0xa0ff }, 2508 { 0x04, 0xf800 }, 2509 { 0x04, 0x0000 }, 2510 { 0x1f, 0x0000 }, 2511 2512 { 0x1f, 0x0001 }, 2513 { 0x0b, 0x8480 }, 2514 { 0x1f, 0x0000 }, 2515 2516 { 0x1f, 0x0001 }, 2517 { 0x18, 0x67c7 }, 2518 { 0x04, 0x2000 }, 2519 { 0x03, 0x002f }, 2520 { 0x02, 0x4360 }, 2521 { 0x01, 0x0109 }, 2522 { 0x00, 0x3022 }, 2523 { 0x04, 0x2800 }, 2524 { 0x1f, 0x0000 }, 2525 2526 { 0x1f, 0x0001 }, 2527 { 0x17, 0x0cc0 }, 2528 { 0x1f, 0x0000 } 2529 }; 2530 2531 rtl_writephy_batch(tp, phy_reg_init); 2532 } 2533 2534 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) 2535 { 2536 rtl_writephy(tp, 0x1f, 0x0001); 2537 rtl_patchphy(tp, 0x16, 1 << 0); 2538 rtl_writephy(tp, 0x10, 0xf41b); 2539 rtl_writephy(tp, 0x1f, 0x0000); 2540 } 2541 2542 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) 2543 { 2544 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf41b); 2545 } 2546 2547 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) 2548 { 2549 phy_write(tp->phydev, 0x1d, 0x0f00); 2550 phy_write_paged(tp->phydev, 0x0002, 0x0c, 0x1ec8); 2551 } 2552 2553 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) 2554 { 2555 phy_set_bits(tp->phydev, 0x14, BIT(5)); 2556 phy_set_bits(tp->phydev, 0x0d, BIT(5)); 2557 phy_write_paged(tp->phydev, 0x0001, 0x1d, 0x3d98); 2558 } 2559 2560 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) 2561 { 2562 static const struct phy_reg phy_reg_init[] = { 2563 { 0x1f, 0x0001 }, 2564 { 0x12, 0x2300 }, 2565 { 0x1f, 0x0002 }, 2566 { 0x00, 0x88d4 }, 2567 { 0x01, 0x82b1 }, 2568 { 0x03, 0x7002 }, 2569 { 0x08, 0x9e30 }, 2570 { 0x09, 0x01f0 }, 2571 { 0x0a, 0x5500 }, 2572 { 0x0c, 0x00c8 }, 2573 { 0x1f, 0x0003 }, 2574 { 0x12, 0xc096 }, 2575 { 0x16, 0x000a }, 2576 { 0x1f, 0x0000 }, 2577 { 0x1f, 0x0000 }, 2578 { 0x09, 0x2000 }, 2579 { 0x09, 0x0000 } 2580 }; 2581 2582 rtl_writephy_batch(tp, phy_reg_init); 2583 2584 rtl_patchphy(tp, 0x14, 1 << 5); 2585 rtl_patchphy(tp, 0x0d, 1 << 5); 2586 rtl_writephy(tp, 0x1f, 0x0000); 2587 } 2588 2589 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) 2590 { 2591 static const struct phy_reg phy_reg_init[] = { 2592 { 0x1f, 0x0001 }, 2593 { 0x12, 0x2300 }, 2594 { 0x03, 0x802f }, 2595 { 0x02, 0x4f02 }, 2596 { 0x01, 0x0409 }, 2597 { 0x00, 0xf099 }, 2598 { 0x04, 0x9800 }, 2599 { 0x04, 0x9000 }, 2600 { 0x1d, 0x3d98 }, 2601 { 0x1f, 0x0002 }, 2602 { 0x0c, 0x7eb8 }, 2603 { 0x06, 0x0761 }, 2604 { 0x1f, 0x0003 }, 2605 { 0x16, 0x0f0a }, 2606 { 0x1f, 0x0000 } 2607 }; 2608 2609 rtl_writephy_batch(tp, phy_reg_init); 2610 2611 rtl_patchphy(tp, 0x16, 1 << 0); 2612 rtl_patchphy(tp, 0x14, 1 << 5); 2613 rtl_patchphy(tp, 0x0d, 1 << 5); 2614 rtl_writephy(tp, 0x1f, 0x0000); 2615 } 2616 2617 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) 2618 { 2619 static const struct phy_reg phy_reg_init[] = { 2620 { 0x1f, 0x0001 }, 2621 { 0x12, 0x2300 }, 2622 { 0x1d, 0x3d98 }, 2623 { 0x1f, 0x0002 }, 2624 { 0x0c, 0x7eb8 }, 2625 { 0x06, 0x5461 }, 2626 { 0x1f, 0x0003 }, 2627 { 0x16, 0x0f0a }, 2628 { 0x1f, 0x0000 } 2629 }; 2630 2631 rtl_writephy_batch(tp, phy_reg_init); 2632 2633 rtl_patchphy(tp, 0x16, 1 << 0); 2634 rtl_patchphy(tp, 0x14, 1 << 5); 2635 rtl_patchphy(tp, 0x0d, 1 << 5); 2636 rtl_writephy(tp, 0x1f, 0x0000); 2637 } 2638 2639 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 2640 /* Channel Estimation */ 2641 { 0x1f, 0x0001 }, 2642 { 0x06, 0x4064 }, 2643 { 0x07, 0x2863 }, 2644 { 0x08, 0x059c }, 2645 { 0x09, 0x26b4 }, 2646 { 0x0a, 0x6a19 }, 2647 { 0x0b, 0xdcc8 }, 2648 { 0x10, 0xf06d }, 2649 { 0x14, 0x7f68 }, 2650 { 0x18, 0x7fd9 }, 2651 { 0x1c, 0xf0ff }, 2652 { 0x1d, 0x3d9c }, 2653 { 0x1f, 0x0003 }, 2654 { 0x12, 0xf49f }, 2655 { 0x13, 0x070b }, 2656 { 0x1a, 0x05ad }, 2657 { 0x14, 0x94c0 }, 2658 2659 /* 2660 * Tx Error Issue 2661 * Enhance line driver power 2662 */ 2663 { 0x1f, 0x0002 }, 2664 { 0x06, 0x5561 }, 2665 { 0x1f, 0x0005 }, 2666 { 0x05, 0x8332 }, 2667 { 0x06, 0x5561 }, 2668 2669 /* 2670 * Can not link to 1Gbps with bad cable 2671 * Decrease SNR threshold form 21.07dB to 19.04dB 2672 */ 2673 { 0x1f, 0x0001 }, 2674 { 0x17, 0x0cc0 }, 2675 2676 { 0x1f, 0x0000 }, 2677 { 0x0d, 0xf880 } 2678 }; 2679 2680 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 2681 { 0x1f, 0x0002 }, 2682 { 0x05, 0x669a }, 2683 { 0x1f, 0x0005 }, 2684 { 0x05, 0x8330 }, 2685 { 0x06, 0x669a }, 2686 { 0x1f, 0x0002 } 2687 }; 2688 2689 static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp, u16 val) 2690 { 2691 u16 reg_val; 2692 2693 rtl_writephy(tp, 0x1f, 0x0005); 2694 rtl_writephy(tp, 0x05, 0x001b); 2695 reg_val = rtl_readphy(tp, 0x06); 2696 rtl_writephy(tp, 0x1f, 0x0000); 2697 2698 if (reg_val != val) 2699 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); 2700 else 2701 rtl_apply_firmware(tp); 2702 } 2703 2704 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) 2705 { 2706 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2707 2708 /* 2709 * Rx Error Issue 2710 * Fine Tune Switching regulator parameter 2711 */ 2712 rtl_writephy(tp, 0x1f, 0x0002); 2713 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); 2714 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); 2715 2716 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2717 int val; 2718 2719 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2720 2721 val = rtl_readphy(tp, 0x0d); 2722 2723 if ((val & 0x00ff) != 0x006c) { 2724 static const u32 set[] = { 2725 0x0065, 0x0066, 0x0067, 0x0068, 2726 0x0069, 0x006a, 0x006b, 0x006c 2727 }; 2728 int i; 2729 2730 rtl_writephy(tp, 0x1f, 0x0002); 2731 2732 val &= 0xff00; 2733 for (i = 0; i < ARRAY_SIZE(set); i++) 2734 rtl_writephy(tp, 0x0d, val | set[i]); 2735 } 2736 } else { 2737 phy_write_paged(tp->phydev, 0x0002, 0x05, 0x6662); 2738 r8168d_phy_param(tp->phydev, 0x8330, 0xffff, 0x6662); 2739 } 2740 2741 /* RSET couple improve */ 2742 rtl_writephy(tp, 0x1f, 0x0002); 2743 rtl_patchphy(tp, 0x0d, 0x0300); 2744 rtl_patchphy(tp, 0x0f, 0x0010); 2745 2746 /* Fine tune PLL performance */ 2747 rtl_writephy(tp, 0x1f, 0x0002); 2748 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2749 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2750 rtl_writephy(tp, 0x1f, 0x0000); 2751 2752 rtl8168d_apply_firmware_cond(tp, 0xbf00); 2753 } 2754 2755 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) 2756 { 2757 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2758 2759 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2760 int val; 2761 2762 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2763 2764 val = rtl_readphy(tp, 0x0d); 2765 if ((val & 0x00ff) != 0x006c) { 2766 static const u32 set[] = { 2767 0x0065, 0x0066, 0x0067, 0x0068, 2768 0x0069, 0x006a, 0x006b, 0x006c 2769 }; 2770 int i; 2771 2772 rtl_writephy(tp, 0x1f, 0x0002); 2773 2774 val &= 0xff00; 2775 for (i = 0; i < ARRAY_SIZE(set); i++) 2776 rtl_writephy(tp, 0x0d, val | set[i]); 2777 } 2778 } else { 2779 phy_write_paged(tp->phydev, 0x0002, 0x05, 0x2642); 2780 r8168d_phy_param(tp->phydev, 0x8330, 0xffff, 0x2642); 2781 } 2782 2783 /* Fine tune PLL performance */ 2784 rtl_writephy(tp, 0x1f, 0x0002); 2785 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2786 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2787 2788 /* Switching regulator Slew rate */ 2789 rtl_writephy(tp, 0x1f, 0x0002); 2790 rtl_patchphy(tp, 0x0f, 0x0017); 2791 rtl_writephy(tp, 0x1f, 0x0000); 2792 2793 rtl8168d_apply_firmware_cond(tp, 0xb300); 2794 } 2795 2796 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) 2797 { 2798 static const struct phy_reg phy_reg_init[] = { 2799 { 0x1f, 0x0002 }, 2800 { 0x10, 0x0008 }, 2801 { 0x0d, 0x006c }, 2802 2803 { 0x1f, 0x0000 }, 2804 { 0x0d, 0xf880 }, 2805 2806 { 0x1f, 0x0001 }, 2807 { 0x17, 0x0cc0 }, 2808 2809 { 0x1f, 0x0001 }, 2810 { 0x0b, 0xa4d8 }, 2811 { 0x09, 0x281c }, 2812 { 0x07, 0x2883 }, 2813 { 0x0a, 0x6b35 }, 2814 { 0x1d, 0x3da4 }, 2815 { 0x1c, 0xeffd }, 2816 { 0x14, 0x7f52 }, 2817 { 0x18, 0x7fc6 }, 2818 { 0x08, 0x0601 }, 2819 { 0x06, 0x4063 }, 2820 { 0x10, 0xf074 }, 2821 { 0x1f, 0x0003 }, 2822 { 0x13, 0x0789 }, 2823 { 0x12, 0xf4bd }, 2824 { 0x1a, 0x04fd }, 2825 { 0x14, 0x84b0 }, 2826 { 0x1f, 0x0000 }, 2827 { 0x00, 0x9200 }, 2828 2829 { 0x1f, 0x0005 }, 2830 { 0x01, 0x0340 }, 2831 { 0x1f, 0x0001 }, 2832 { 0x04, 0x4000 }, 2833 { 0x03, 0x1d21 }, 2834 { 0x02, 0x0c32 }, 2835 { 0x01, 0x0200 }, 2836 { 0x00, 0x5554 }, 2837 { 0x04, 0x4800 }, 2838 { 0x04, 0x4000 }, 2839 { 0x04, 0xf000 }, 2840 { 0x03, 0xdf01 }, 2841 { 0x02, 0xdf20 }, 2842 { 0x01, 0x101a }, 2843 { 0x00, 0xa0ff }, 2844 { 0x04, 0xf800 }, 2845 { 0x04, 0xf000 }, 2846 { 0x1f, 0x0000 }, 2847 }; 2848 2849 rtl_writephy_batch(tp, phy_reg_init); 2850 2851 r8168d_modify_extpage(tp->phydev, 0x0023, 0x16, 0xffff, 0x0000); 2852 } 2853 2854 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) 2855 { 2856 phy_write_paged(tp->phydev, 0x0001, 0x17, 0x0cc0); 2857 r8168d_modify_extpage(tp->phydev, 0x002d, 0x18, 0xffff, 0x0040); 2858 phy_set_bits(tp->phydev, 0x0d, BIT(5)); 2859 } 2860 2861 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) 2862 { 2863 static const struct phy_reg phy_reg_init[] = { 2864 /* Channel estimation fine tune */ 2865 { 0x1f, 0x0001 }, 2866 { 0x0b, 0x6c20 }, 2867 { 0x07, 0x2872 }, 2868 { 0x1c, 0xefff }, 2869 { 0x1f, 0x0003 }, 2870 { 0x14, 0x6420 }, 2871 { 0x1f, 0x0000 }, 2872 }; 2873 struct phy_device *phydev = tp->phydev; 2874 2875 rtl_apply_firmware(tp); 2876 2877 /* Enable Delay cap */ 2878 r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896); 2879 2880 rtl_writephy_batch(tp, phy_reg_init); 2881 2882 /* Update PFM & 10M TX idle timer */ 2883 r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919); 2884 2885 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 2886 2887 /* DCO enable for 10M IDLE Power */ 2888 r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006); 2889 2890 /* For impedance matching */ 2891 phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000); 2892 2893 /* PHY auto speed down */ 2894 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050); 2895 phy_set_bits(phydev, 0x14, BIT(15)); 2896 2897 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 2898 r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000); 2899 2900 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000); 2901 phy_write_paged(phydev, 0x0006, 0x00, 0x5a00); 2902 2903 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); 2904 } 2905 2906 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2907 { 2908 const u16 w[] = { 2909 addr[0] | (addr[1] << 8), 2910 addr[2] | (addr[3] << 8), 2911 addr[4] | (addr[5] << 8) 2912 }; 2913 2914 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2915 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2916 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2917 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2918 } 2919 2920 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) 2921 { 2922 struct phy_device *phydev = tp->phydev; 2923 2924 rtl_apply_firmware(tp); 2925 2926 /* Enable Delay cap */ 2927 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 2928 2929 /* Channel estimation fine tune */ 2930 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 2931 2932 /* Green Setting */ 2933 r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222); 2934 r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000); 2935 r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000); 2936 2937 /* For 4-corner performance improve */ 2938 rtl_writephy(tp, 0x1f, 0x0005); 2939 rtl_writephy(tp, 0x05, 0x8b80); 2940 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 2941 rtl_writephy(tp, 0x1f, 0x0000); 2942 2943 /* PHY auto speed down */ 2944 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 2945 phy_set_bits(phydev, 0x14, BIT(15)); 2946 2947 /* improve 10M EEE waveform */ 2948 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 2949 2950 /* Improve 2-pair detection performance */ 2951 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 2952 2953 rtl8168f_config_eee_phy(tp); 2954 rtl_enable_eee(tp); 2955 2956 /* Green feature */ 2957 rtl_writephy(tp, 0x1f, 0x0003); 2958 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000); 2959 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000); 2960 rtl_writephy(tp, 0x1f, 0x0000); 2961 rtl_writephy(tp, 0x1f, 0x0005); 2962 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000); 2963 rtl_writephy(tp, 0x1f, 0x0000); 2964 2965 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ 2966 rtl_rar_exgmac_set(tp, tp->dev->dev_addr); 2967 } 2968 2969 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) 2970 { 2971 struct phy_device *phydev = tp->phydev; 2972 2973 /* For 4-corner performance improve */ 2974 r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006); 2975 2976 /* PHY auto speed down */ 2977 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 2978 phy_set_bits(phydev, 0x14, BIT(15)); 2979 2980 /* Improve 10M EEE waveform */ 2981 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 2982 2983 rtl8168f_config_eee_phy(tp); 2984 rtl_enable_eee(tp); 2985 } 2986 2987 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) 2988 { 2989 struct phy_device *phydev = tp->phydev; 2990 2991 rtl_apply_firmware(tp); 2992 2993 /* Channel estimation fine tune */ 2994 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 2995 2996 /* Modify green table for giga & fnet */ 2997 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 2998 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 2999 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 3000 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 3001 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 3002 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb); 3003 3004 /* Modify green table for 10M */ 3005 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 3006 3007 /* Disable hiimpedance detection (RTCT) */ 3008 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 3009 3010 rtl8168f_hw_phy_config(tp); 3011 3012 /* Improve 2-pair detection performance */ 3013 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 3014 } 3015 3016 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) 3017 { 3018 rtl_apply_firmware(tp); 3019 3020 rtl8168f_hw_phy_config(tp); 3021 } 3022 3023 static void rtl8411_hw_phy_config(struct rtl8169_private *tp) 3024 { 3025 struct phy_device *phydev = tp->phydev; 3026 3027 rtl_apply_firmware(tp); 3028 3029 rtl8168f_hw_phy_config(tp); 3030 3031 /* Improve 2-pair detection performance */ 3032 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 3033 3034 /* Channel estimation fine tune */ 3035 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 3036 3037 /* Modify green table for giga & fnet */ 3038 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 3039 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 3040 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 3041 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 3042 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 3043 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa); 3044 3045 /* Modify green table for 10M */ 3046 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 3047 3048 /* Disable hiimpedance detection (RTCT) */ 3049 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 3050 3051 /* Modify green table for giga */ 3052 r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000); 3053 r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000); 3054 r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000); 3055 r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100); 3056 r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000); 3057 r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000); 3058 r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000); 3059 3060 /* uc same-seed solution */ 3061 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000); 3062 3063 /* Green feature */ 3064 rtl_writephy(tp, 0x1f, 0x0003); 3065 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); 3066 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); 3067 rtl_writephy(tp, 0x1f, 0x0000); 3068 } 3069 3070 static void rtl8168g_disable_aldps(struct rtl8169_private *tp) 3071 { 3072 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0); 3073 } 3074 3075 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp) 3076 { 3077 struct phy_device *phydev = tp->phydev; 3078 3079 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 3080 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 3081 r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000); 3082 phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003); 3083 } 3084 3085 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) 3086 { 3087 int ret; 3088 3089 rtl_apply_firmware(tp); 3090 3091 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10); 3092 if (ret & BIT(8)) 3093 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0); 3094 else 3095 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15)); 3096 3097 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13); 3098 if (ret & BIT(8)) 3099 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1)); 3100 else 3101 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0); 3102 3103 /* Enable PHY auto speed down */ 3104 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3105 3106 rtl8168g_phy_adjust_10m_aldps(tp); 3107 3108 /* EEE auto-fallback function */ 3109 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3110 3111 /* Enable UC LPF tune function */ 3112 r8168g_phy_param(tp->phydev, 0x8012, 0x0000, 0x8000); 3113 3114 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3115 3116 /* Improve SWR Efficiency */ 3117 rtl_writephy(tp, 0x1f, 0x0bcd); 3118 rtl_writephy(tp, 0x14, 0x5065); 3119 rtl_writephy(tp, 0x14, 0xd065); 3120 rtl_writephy(tp, 0x1f, 0x0bc8); 3121 rtl_writephy(tp, 0x11, 0x5655); 3122 rtl_writephy(tp, 0x1f, 0x0bcd); 3123 rtl_writephy(tp, 0x14, 0x1065); 3124 rtl_writephy(tp, 0x14, 0x9065); 3125 rtl_writephy(tp, 0x14, 0x1065); 3126 rtl_writephy(tp, 0x1f, 0x0000); 3127 3128 rtl8168g_disable_aldps(tp); 3129 rtl8168g_config_eee_phy(tp); 3130 rtl_enable_eee(tp); 3131 } 3132 3133 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) 3134 { 3135 rtl_apply_firmware(tp); 3136 rtl8168g_config_eee_phy(tp); 3137 rtl_enable_eee(tp); 3138 } 3139 3140 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) 3141 { 3142 struct phy_device *phydev = tp->phydev; 3143 u16 dout_tapbin; 3144 u32 data; 3145 3146 rtl_apply_firmware(tp); 3147 3148 /* CHN EST parameters adjust - giga master */ 3149 r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000); 3150 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000); 3151 r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500); 3152 r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00); 3153 3154 /* CHN EST parameters adjust - giga slave */ 3155 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000); 3156 r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000); 3157 r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000); 3158 3159 /* CHN EST parameters adjust - fnet */ 3160 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200); 3161 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500); 3162 r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00); 3163 3164 /* enable R-tune & PGA-retune function */ 3165 dout_tapbin = 0; 3166 data = phy_read_paged(phydev, 0x0a46, 0x13); 3167 data &= 3; 3168 data <<= 2; 3169 dout_tapbin |= data; 3170 data = phy_read_paged(phydev, 0x0a46, 0x12); 3171 data &= 0xc000; 3172 data >>= 14; 3173 dout_tapbin |= data; 3174 dout_tapbin = ~(dout_tapbin^0x08); 3175 dout_tapbin <<= 12; 3176 dout_tapbin &= 0xf000; 3177 3178 r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin); 3179 r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin); 3180 r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin); 3181 r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin); 3182 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 3183 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 3184 3185 /* enable GPHY 10M */ 3186 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3187 3188 /* SAR ADC performance */ 3189 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 3190 3191 r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000); 3192 r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000); 3193 r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000); 3194 r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000); 3195 r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000); 3196 r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000); 3197 r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000); 3198 3199 /* disable phy pfm mode */ 3200 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3201 3202 rtl8168g_disable_aldps(tp); 3203 rtl8168h_config_eee_phy(tp); 3204 rtl_enable_eee(tp); 3205 } 3206 3207 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) 3208 { 3209 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; 3210 struct phy_device *phydev = tp->phydev; 3211 u16 rlen; 3212 u32 data; 3213 3214 rtl_apply_firmware(tp); 3215 3216 /* CHIN EST parameter update */ 3217 r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a); 3218 3219 /* enable R-tune & PGA-retune function */ 3220 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 3221 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 3222 3223 /* enable GPHY 10M */ 3224 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3225 3226 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 3227 data = r8168_mac_ocp_read(tp, 0xdd02); 3228 ioffset_p3 = ((data & 0x80)>>7); 3229 ioffset_p3 <<= 3; 3230 3231 data = r8168_mac_ocp_read(tp, 0xdd00); 3232 ioffset_p3 |= ((data & (0xe000))>>13); 3233 ioffset_p2 = ((data & (0x1e00))>>9); 3234 ioffset_p1 = ((data & (0x01e0))>>5); 3235 ioffset_p0 = ((data & 0x0010)>>4); 3236 ioffset_p0 <<= 3; 3237 ioffset_p0 |= (data & (0x07)); 3238 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); 3239 3240 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || 3241 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) 3242 phy_write_paged(phydev, 0x0bcf, 0x16, data); 3243 3244 /* Modify rlen (TX LPF corner frequency) level */ 3245 data = phy_read_paged(phydev, 0x0bcd, 0x16); 3246 data &= 0x000f; 3247 rlen = 0; 3248 if (data > 3) 3249 rlen = data - 3; 3250 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); 3251 phy_write_paged(phydev, 0x0bcd, 0x17, data); 3252 3253 /* disable phy pfm mode */ 3254 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 3255 3256 rtl8168g_disable_aldps(tp); 3257 rtl8168g_config_eee_phy(tp); 3258 rtl_enable_eee(tp); 3259 } 3260 3261 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) 3262 { 3263 struct phy_device *phydev = tp->phydev; 3264 3265 /* Enable PHY auto speed down */ 3266 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3267 3268 rtl8168g_phy_adjust_10m_aldps(tp); 3269 3270 /* Enable EEE auto-fallback function */ 3271 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 3272 3273 /* Enable UC LPF tune function */ 3274 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 3275 3276 /* set rg_sel_sdm_rate */ 3277 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3278 3279 rtl8168g_disable_aldps(tp); 3280 rtl8168g_config_eee_phy(tp); 3281 rtl_enable_eee(tp); 3282 } 3283 3284 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) 3285 { 3286 struct phy_device *phydev = tp->phydev; 3287 3288 rtl8168g_phy_adjust_10m_aldps(tp); 3289 3290 /* Enable UC LPF tune function */ 3291 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 3292 3293 /* Set rg_sel_sdm_rate */ 3294 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3295 3296 /* Channel estimation parameters */ 3297 r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00); 3298 r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00); 3299 r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500); 3300 r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00); 3301 r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800); 3302 r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00); 3303 r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400); 3304 r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500); 3305 r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800); 3306 r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00); 3307 r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500); 3308 r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100); 3309 r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200); 3310 r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400); 3311 r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00); 3312 r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00); 3313 r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00); 3314 r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00); 3315 r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00); 3316 r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00); 3317 r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400); 3318 3319 /* Force PWM-mode */ 3320 rtl_writephy(tp, 0x1f, 0x0bcd); 3321 rtl_writephy(tp, 0x14, 0x5065); 3322 rtl_writephy(tp, 0x14, 0xd065); 3323 rtl_writephy(tp, 0x1f, 0x0bc8); 3324 rtl_writephy(tp, 0x12, 0x00ed); 3325 rtl_writephy(tp, 0x1f, 0x0bcd); 3326 rtl_writephy(tp, 0x14, 0x1065); 3327 rtl_writephy(tp, 0x14, 0x9065); 3328 rtl_writephy(tp, 0x14, 0x1065); 3329 rtl_writephy(tp, 0x1f, 0x0000); 3330 3331 rtl8168g_disable_aldps(tp); 3332 rtl8168g_config_eee_phy(tp); 3333 rtl_enable_eee(tp); 3334 } 3335 3336 static void rtl8117_hw_phy_config(struct rtl8169_private *tp) 3337 { 3338 struct phy_device *phydev = tp->phydev; 3339 3340 /* CHN EST parameters adjust - fnet */ 3341 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800); 3342 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00); 3343 r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000); 3344 3345 r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000); 3346 r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00); 3347 r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600); 3348 r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000); 3349 r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800); 3350 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000); 3351 r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000); 3352 r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00); 3353 r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800); 3354 r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000); 3355 r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300); 3356 r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800); 3357 r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200); 3358 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800); 3359 r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800); 3360 r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00); 3361 r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300); 3362 r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300); 3363 3364 r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800); 3365 3366 /* enable GPHY 10M */ 3367 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3368 3369 r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400); 3370 3371 rtl8168g_disable_aldps(tp); 3372 rtl8168h_config_eee_phy(tp); 3373 rtl_enable_eee(tp); 3374 } 3375 3376 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) 3377 { 3378 static const struct phy_reg phy_reg_init[] = { 3379 { 0x1f, 0x0003 }, 3380 { 0x08, 0x441d }, 3381 { 0x01, 0x9100 }, 3382 { 0x1f, 0x0000 } 3383 }; 3384 3385 rtl_writephy(tp, 0x1f, 0x0000); 3386 rtl_patchphy(tp, 0x11, 1 << 12); 3387 rtl_patchphy(tp, 0x19, 1 << 13); 3388 rtl_patchphy(tp, 0x10, 1 << 15); 3389 3390 rtl_writephy_batch(tp, phy_reg_init); 3391 } 3392 3393 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) 3394 { 3395 /* Disable ALDPS before ram code */ 3396 phy_write(tp->phydev, 0x18, 0x0310); 3397 msleep(100); 3398 3399 rtl_apply_firmware(tp); 3400 3401 phy_write_paged(tp->phydev, 0x0005, 0x1a, 0x0000); 3402 phy_write_paged(tp->phydev, 0x0004, 0x1c, 0x0000); 3403 phy_write_paged(tp->phydev, 0x0001, 0x15, 0x7701); 3404 } 3405 3406 static void rtl8402_hw_phy_config(struct rtl8169_private *tp) 3407 { 3408 /* Disable ALDPS before setting firmware */ 3409 phy_write(tp->phydev, 0x18, 0x0310); 3410 msleep(20); 3411 3412 rtl_apply_firmware(tp); 3413 3414 /* EEE setting */ 3415 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3416 rtl_writephy(tp, 0x1f, 0x0004); 3417 rtl_writephy(tp, 0x10, 0x401f); 3418 rtl_writephy(tp, 0x19, 0x7030); 3419 rtl_writephy(tp, 0x1f, 0x0000); 3420 } 3421 3422 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) 3423 { 3424 static const struct phy_reg phy_reg_init[] = { 3425 { 0x1f, 0x0004 }, 3426 { 0x10, 0xc07f }, 3427 { 0x19, 0x7030 }, 3428 { 0x1f, 0x0000 } 3429 }; 3430 3431 /* Disable ALDPS before ram code */ 3432 phy_write(tp->phydev, 0x18, 0x0310); 3433 msleep(100); 3434 3435 rtl_apply_firmware(tp); 3436 3437 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3438 rtl_writephy_batch(tp, phy_reg_init); 3439 3440 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3441 } 3442 3443 static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp) 3444 { 3445 struct phy_device *phydev = tp->phydev; 3446 3447 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084); 3448 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3449 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006); 3450 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3451 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100); 3452 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000); 3453 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400); 3454 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff); 3455 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff); 3456 3457 r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400); 3458 r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300); 3459 r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00); 3460 r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000); 3461 r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500); 3462 r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000); 3463 r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300); 3464 r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000); 3465 r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000); 3466 r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500); 3467 r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00); 3468 r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100); 3469 r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000); 3470 3471 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038); 3472 r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6); 3473 3474 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555); 3475 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00); 3476 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000); 3477 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3478 3479 rtl8125_config_eee_phy(tp); 3480 rtl_enable_eee(tp); 3481 } 3482 3483 static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp) 3484 { 3485 struct phy_device *phydev = tp->phydev; 3486 int i; 3487 3488 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3489 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 3490 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3491 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 3492 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 3493 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 3494 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 3495 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 3496 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 3497 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 3498 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 3499 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 3500 3501 phy_write(phydev, 0x1f, 0x0b87); 3502 phy_write(phydev, 0x16, 0x80a2); 3503 phy_write(phydev, 0x17, 0x0153); 3504 phy_write(phydev, 0x16, 0x809c); 3505 phy_write(phydev, 0x17, 0x0153); 3506 phy_write(phydev, 0x1f, 0x0000); 3507 3508 phy_write(phydev, 0x1f, 0x0a43); 3509 phy_write(phydev, 0x13, 0x81B3); 3510 phy_write(phydev, 0x14, 0x0043); 3511 phy_write(phydev, 0x14, 0x00A7); 3512 phy_write(phydev, 0x14, 0x00D6); 3513 phy_write(phydev, 0x14, 0x00EC); 3514 phy_write(phydev, 0x14, 0x00F6); 3515 phy_write(phydev, 0x14, 0x00FB); 3516 phy_write(phydev, 0x14, 0x00FD); 3517 phy_write(phydev, 0x14, 0x00FF); 3518 phy_write(phydev, 0x14, 0x00BB); 3519 phy_write(phydev, 0x14, 0x0058); 3520 phy_write(phydev, 0x14, 0x0029); 3521 phy_write(phydev, 0x14, 0x0013); 3522 phy_write(phydev, 0x14, 0x0009); 3523 phy_write(phydev, 0x14, 0x0004); 3524 phy_write(phydev, 0x14, 0x0002); 3525 for (i = 0; i < 25; i++) 3526 phy_write(phydev, 0x14, 0x0000); 3527 phy_write(phydev, 0x1f, 0x0000); 3528 3529 r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F); 3530 r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843); 3531 3532 rtl_apply_firmware(tp); 3533 3534 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 3535 3536 r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100); 3537 3538 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 3539 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 3540 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 3541 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 3542 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 3543 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3544 3545 rtl8125_config_eee_phy(tp); 3546 rtl_enable_eee(tp); 3547 } 3548 3549 static void rtl_hw_phy_config(struct net_device *dev) 3550 { 3551 static const rtl_generic_fct phy_configs[] = { 3552 /* PCI devices. */ 3553 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 3554 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 3555 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 3556 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 3557 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 3558 /* PCI-E devices. */ 3559 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 3560 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 3561 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 3562 [RTL_GIGA_MAC_VER_10] = NULL, 3563 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 3564 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 3565 [RTL_GIGA_MAC_VER_13] = NULL, 3566 [RTL_GIGA_MAC_VER_14] = NULL, 3567 [RTL_GIGA_MAC_VER_15] = NULL, 3568 [RTL_GIGA_MAC_VER_16] = NULL, 3569 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 3570 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 3571 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 3572 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 3573 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 3574 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config, 3575 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 3576 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 3577 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 3578 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 3579 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 3580 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 3581 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 3582 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 3583 [RTL_GIGA_MAC_VER_31] = NULL, 3584 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 3585 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 3586 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 3587 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 3588 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 3589 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 3590 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 3591 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 3592 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 3593 [RTL_GIGA_MAC_VER_41] = NULL, 3594 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 3595 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 3596 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 3597 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 3598 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 3599 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 3600 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 3601 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 3602 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 3603 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 3604 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, 3605 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config, 3606 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config, 3607 }; 3608 struct rtl8169_private *tp = netdev_priv(dev); 3609 3610 if (phy_configs[tp->mac_version]) 3611 phy_configs[tp->mac_version](tp); 3612 } 3613 3614 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 3615 { 3616 if (!test_and_set_bit(flag, tp->wk.flags)) 3617 schedule_work(&tp->wk.work); 3618 } 3619 3620 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 3621 { 3622 rtl_hw_phy_config(dev); 3623 3624 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 3625 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 3626 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 3627 netif_dbg(tp, drv, dev, 3628 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 3629 RTL_W8(tp, 0x82, 0x01); 3630 } 3631 3632 /* We may have called phy_speed_down before */ 3633 phy_speed_up(tp->phydev); 3634 3635 genphy_soft_reset(tp->phydev); 3636 } 3637 3638 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 3639 { 3640 rtl_lock_work(tp); 3641 3642 rtl_unlock_config_regs(tp); 3643 3644 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 3645 RTL_R32(tp, MAC4); 3646 3647 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3648 RTL_R32(tp, MAC0); 3649 3650 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 3651 rtl_rar_exgmac_set(tp, addr); 3652 3653 rtl_lock_config_regs(tp); 3654 3655 rtl_unlock_work(tp); 3656 } 3657 3658 static int rtl_set_mac_address(struct net_device *dev, void *p) 3659 { 3660 struct rtl8169_private *tp = netdev_priv(dev); 3661 struct device *d = tp_to_dev(tp); 3662 int ret; 3663 3664 ret = eth_mac_addr(dev, p); 3665 if (ret) 3666 return ret; 3667 3668 pm_runtime_get_noresume(d); 3669 3670 if (pm_runtime_active(d)) 3671 rtl_rar_set(tp, dev->dev_addr); 3672 3673 pm_runtime_put_noidle(d); 3674 3675 return 0; 3676 } 3677 3678 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3679 { 3680 struct rtl8169_private *tp = netdev_priv(dev); 3681 3682 if (!netif_running(dev)) 3683 return -ENODEV; 3684 3685 return phy_mii_ioctl(tp->phydev, ifr, cmd); 3686 } 3687 3688 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 3689 { 3690 switch (tp->mac_version) { 3691 case RTL_GIGA_MAC_VER_25: 3692 case RTL_GIGA_MAC_VER_26: 3693 case RTL_GIGA_MAC_VER_29: 3694 case RTL_GIGA_MAC_VER_30: 3695 case RTL_GIGA_MAC_VER_32: 3696 case RTL_GIGA_MAC_VER_33: 3697 case RTL_GIGA_MAC_VER_34: 3698 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61: 3699 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 3700 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 3701 break; 3702 default: 3703 break; 3704 } 3705 } 3706 3707 static void rtl_pll_power_down(struct rtl8169_private *tp) 3708 { 3709 if (r8168_check_dash(tp)) 3710 return; 3711 3712 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 3713 tp->mac_version == RTL_GIGA_MAC_VER_33) 3714 rtl_ephy_write(tp, 0x19, 0xff64); 3715 3716 if (device_may_wakeup(tp_to_dev(tp))) { 3717 phy_speed_down(tp->phydev, false); 3718 rtl_wol_suspend_quirk(tp); 3719 return; 3720 } 3721 3722 switch (tp->mac_version) { 3723 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3724 case RTL_GIGA_MAC_VER_37: 3725 case RTL_GIGA_MAC_VER_39: 3726 case RTL_GIGA_MAC_VER_43: 3727 case RTL_GIGA_MAC_VER_44: 3728 case RTL_GIGA_MAC_VER_45: 3729 case RTL_GIGA_MAC_VER_46: 3730 case RTL_GIGA_MAC_VER_47: 3731 case RTL_GIGA_MAC_VER_48: 3732 case RTL_GIGA_MAC_VER_50: 3733 case RTL_GIGA_MAC_VER_51: 3734 case RTL_GIGA_MAC_VER_52: 3735 case RTL_GIGA_MAC_VER_60: 3736 case RTL_GIGA_MAC_VER_61: 3737 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3738 break; 3739 case RTL_GIGA_MAC_VER_40: 3740 case RTL_GIGA_MAC_VER_41: 3741 case RTL_GIGA_MAC_VER_49: 3742 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3743 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3744 break; 3745 default: 3746 break; 3747 } 3748 } 3749 3750 static void rtl_pll_power_up(struct rtl8169_private *tp) 3751 { 3752 switch (tp->mac_version) { 3753 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3754 case RTL_GIGA_MAC_VER_37: 3755 case RTL_GIGA_MAC_VER_39: 3756 case RTL_GIGA_MAC_VER_43: 3757 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 3758 break; 3759 case RTL_GIGA_MAC_VER_44: 3760 case RTL_GIGA_MAC_VER_45: 3761 case RTL_GIGA_MAC_VER_46: 3762 case RTL_GIGA_MAC_VER_47: 3763 case RTL_GIGA_MAC_VER_48: 3764 case RTL_GIGA_MAC_VER_50: 3765 case RTL_GIGA_MAC_VER_51: 3766 case RTL_GIGA_MAC_VER_52: 3767 case RTL_GIGA_MAC_VER_60: 3768 case RTL_GIGA_MAC_VER_61: 3769 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3770 break; 3771 case RTL_GIGA_MAC_VER_40: 3772 case RTL_GIGA_MAC_VER_41: 3773 case RTL_GIGA_MAC_VER_49: 3774 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3775 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3776 break; 3777 default: 3778 break; 3779 } 3780 3781 phy_resume(tp->phydev); 3782 /* give MAC/PHY some time to resume */ 3783 msleep(20); 3784 } 3785 3786 static void rtl_init_rxcfg(struct rtl8169_private *tp) 3787 { 3788 switch (tp->mac_version) { 3789 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 3790 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 3791 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 3792 break; 3793 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 3794 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 3795 case RTL_GIGA_MAC_VER_38: 3796 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 3797 break; 3798 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 3799 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 3800 break; 3801 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 3802 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 | 3803 RX_DMA_BURST); 3804 break; 3805 default: 3806 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 3807 break; 3808 } 3809 } 3810 3811 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 3812 { 3813 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 3814 } 3815 3816 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 3817 { 3818 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 3819 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 3820 } 3821 3822 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 3823 { 3824 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 3825 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 3826 } 3827 3828 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 3829 { 3830 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 3831 } 3832 3833 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 3834 { 3835 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 3836 } 3837 3838 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 3839 { 3840 RTL_W8(tp, MaxTxPacketSize, 0x3f); 3841 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 3842 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 3843 } 3844 3845 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 3846 { 3847 RTL_W8(tp, MaxTxPacketSize, 0x0c); 3848 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 3849 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 3850 } 3851 3852 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 3853 { 3854 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 3855 } 3856 3857 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 3858 { 3859 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 3860 } 3861 3862 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) 3863 { 3864 rtl_unlock_config_regs(tp); 3865 switch (tp->mac_version) { 3866 case RTL_GIGA_MAC_VER_12: 3867 case RTL_GIGA_MAC_VER_17: 3868 r8168b_1_hw_jumbo_enable(tp); 3869 break; 3870 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 3871 r8168c_hw_jumbo_enable(tp); 3872 break; 3873 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 3874 r8168dp_hw_jumbo_enable(tp); 3875 break; 3876 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 3877 r8168e_hw_jumbo_enable(tp); 3878 break; 3879 default: 3880 break; 3881 } 3882 rtl_lock_config_regs(tp); 3883 } 3884 3885 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) 3886 { 3887 rtl_unlock_config_regs(tp); 3888 switch (tp->mac_version) { 3889 case RTL_GIGA_MAC_VER_12: 3890 case RTL_GIGA_MAC_VER_17: 3891 r8168b_1_hw_jumbo_disable(tp); 3892 break; 3893 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 3894 r8168c_hw_jumbo_disable(tp); 3895 break; 3896 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 3897 r8168dp_hw_jumbo_disable(tp); 3898 break; 3899 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 3900 r8168e_hw_jumbo_disable(tp); 3901 break; 3902 default: 3903 break; 3904 } 3905 rtl_lock_config_regs(tp); 3906 } 3907 3908 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu) 3909 { 3910 if (mtu > ETH_DATA_LEN) 3911 rtl_hw_jumbo_enable(tp); 3912 else 3913 rtl_hw_jumbo_disable(tp); 3914 } 3915 3916 DECLARE_RTL_COND(rtl_chipcmd_cond) 3917 { 3918 return RTL_R8(tp, ChipCmd) & CmdReset; 3919 } 3920 3921 static void rtl_hw_reset(struct rtl8169_private *tp) 3922 { 3923 RTL_W8(tp, ChipCmd, CmdReset); 3924 3925 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 3926 } 3927 3928 static void rtl_request_firmware(struct rtl8169_private *tp) 3929 { 3930 struct rtl_fw *rtl_fw; 3931 3932 /* firmware loaded already or no firmware available */ 3933 if (tp->rtl_fw || !tp->fw_name) 3934 return; 3935 3936 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 3937 if (!rtl_fw) { 3938 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 3939 return; 3940 } 3941 3942 rtl_fw->phy_write = rtl_writephy; 3943 rtl_fw->phy_read = rtl_readphy; 3944 rtl_fw->mac_mcu_write = mac_mcu_write; 3945 rtl_fw->mac_mcu_read = mac_mcu_read; 3946 rtl_fw->fw_name = tp->fw_name; 3947 rtl_fw->dev = tp_to_dev(tp); 3948 3949 if (rtl_fw_request_firmware(rtl_fw)) 3950 kfree(rtl_fw); 3951 else 3952 tp->rtl_fw = rtl_fw; 3953 } 3954 3955 static void rtl_rx_close(struct rtl8169_private *tp) 3956 { 3957 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 3958 } 3959 3960 DECLARE_RTL_COND(rtl_npq_cond) 3961 { 3962 return RTL_R8(tp, TxPoll) & NPQ; 3963 } 3964 3965 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 3966 { 3967 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 3968 } 3969 3970 static void rtl8169_hw_reset(struct rtl8169_private *tp) 3971 { 3972 /* Disable interrupts */ 3973 rtl8169_irq_mask_and_ack(tp); 3974 3975 rtl_rx_close(tp); 3976 3977 switch (tp->mac_version) { 3978 case RTL_GIGA_MAC_VER_27: 3979 case RTL_GIGA_MAC_VER_28: 3980 case RTL_GIGA_MAC_VER_31: 3981 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 3982 break; 3983 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3984 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 3985 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3986 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3987 break; 3988 default: 3989 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3990 udelay(100); 3991 break; 3992 } 3993 3994 rtl_hw_reset(tp); 3995 } 3996 3997 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 3998 { 3999 u32 val = TX_DMA_BURST << TxDMAShift | 4000 InterFrameGap << TxInterFrameGapShift; 4001 4002 if (rtl_is_8168evl_up(tp)) 4003 val |= TXCFG_AUTO_FIFO; 4004 4005 RTL_W32(tp, TxConfig, val); 4006 } 4007 4008 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 4009 { 4010 /* Low hurts. Let's disable the filtering. */ 4011 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 4012 } 4013 4014 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 4015 { 4016 /* 4017 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 4018 * register to be written before TxDescAddrLow to work. 4019 * Switching from MMIO to I/O access fixes the issue as well. 4020 */ 4021 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 4022 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 4023 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 4024 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 4025 } 4026 4027 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 4028 { 4029 u32 val; 4030 4031 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 4032 val = 0x000fff00; 4033 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 4034 val = 0x00ffff00; 4035 else 4036 return; 4037 4038 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 4039 val |= 0xff; 4040 4041 RTL_W32(tp, 0x7c, val); 4042 } 4043 4044 static void rtl_set_rx_mode(struct net_device *dev) 4045 { 4046 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 4047 /* Multicast hash filter */ 4048 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 4049 struct rtl8169_private *tp = netdev_priv(dev); 4050 u32 tmp; 4051 4052 if (dev->flags & IFF_PROMISC) { 4053 /* Unconditionally log net taps. */ 4054 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 4055 rx_mode |= AcceptAllPhys; 4056 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 4057 dev->flags & IFF_ALLMULTI || 4058 tp->mac_version == RTL_GIGA_MAC_VER_35) { 4059 /* accept all multicasts */ 4060 } else if (netdev_mc_empty(dev)) { 4061 rx_mode &= ~AcceptMulticast; 4062 } else { 4063 struct netdev_hw_addr *ha; 4064 4065 mc_filter[1] = mc_filter[0] = 0; 4066 netdev_for_each_mc_addr(ha, dev) { 4067 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 4068 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 4069 } 4070 4071 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 4072 tmp = mc_filter[0]; 4073 mc_filter[0] = swab32(mc_filter[1]); 4074 mc_filter[1] = swab32(tmp); 4075 } 4076 } 4077 4078 if (dev->features & NETIF_F_RXALL) 4079 rx_mode |= (AcceptErr | AcceptRunt); 4080 4081 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 4082 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 4083 4084 tmp = RTL_R32(tp, RxConfig); 4085 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); 4086 } 4087 4088 DECLARE_RTL_COND(rtl_csiar_cond) 4089 { 4090 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 4091 } 4092 4093 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 4094 { 4095 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4096 4097 RTL_W32(tp, CSIDR, value); 4098 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 4099 CSIAR_BYTE_ENABLE | func << 16); 4100 4101 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 4102 } 4103 4104 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 4105 { 4106 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4107 4108 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 4109 CSIAR_BYTE_ENABLE); 4110 4111 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 4112 RTL_R32(tp, CSIDR) : ~0; 4113 } 4114 4115 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 4116 { 4117 struct pci_dev *pdev = tp->pci_dev; 4118 u32 csi; 4119 4120 /* According to Realtek the value at config space address 0x070f 4121 * controls the L0s/L1 entrance latency. We try standard ECAM access 4122 * first and if it fails fall back to CSI. 4123 */ 4124 if (pdev->cfg_size > 0x070f && 4125 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 4126 return; 4127 4128 netdev_notice_once(tp->dev, 4129 "No native access to PCI extended config space, falling back to CSI\n"); 4130 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 4131 rtl_csi_write(tp, 0x070c, csi | val << 24); 4132 } 4133 4134 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 4135 { 4136 rtl_csi_access_enable(tp, 0x27); 4137 } 4138 4139 struct ephy_info { 4140 unsigned int offset; 4141 u16 mask; 4142 u16 bits; 4143 }; 4144 4145 static void __rtl_ephy_init(struct rtl8169_private *tp, 4146 const struct ephy_info *e, int len) 4147 { 4148 u16 w; 4149 4150 while (len-- > 0) { 4151 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 4152 rtl_ephy_write(tp, e->offset, w); 4153 e++; 4154 } 4155 } 4156 4157 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 4158 4159 static void rtl_disable_clock_request(struct rtl8169_private *tp) 4160 { 4161 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 4162 PCI_EXP_LNKCTL_CLKREQ_EN); 4163 } 4164 4165 static void rtl_enable_clock_request(struct rtl8169_private *tp) 4166 { 4167 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 4168 PCI_EXP_LNKCTL_CLKREQ_EN); 4169 } 4170 4171 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 4172 { 4173 /* work around an issue when PCI reset occurs during L2/L3 state */ 4174 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 4175 } 4176 4177 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 4178 { 4179 /* Don't enable ASPM in the chip if OS can't control ASPM */ 4180 if (enable && tp->aspm_manageable) { 4181 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 4182 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 4183 } else { 4184 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4185 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4186 } 4187 4188 udelay(10); 4189 } 4190 4191 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 4192 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 4193 { 4194 /* Usage of dynamic vs. static FIFO is controlled by bit 4195 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 4196 */ 4197 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 4198 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 4199 } 4200 4201 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 4202 u8 low, u8 high) 4203 { 4204 /* FIFO thresholds for pause flow control */ 4205 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 4206 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 4207 } 4208 4209 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 4210 { 4211 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4212 } 4213 4214 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 4215 { 4216 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 4217 4218 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4219 4220 rtl_disable_clock_request(tp); 4221 } 4222 4223 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 4224 { 4225 static const struct ephy_info e_info_8168cp[] = { 4226 { 0x01, 0, 0x0001 }, 4227 { 0x02, 0x0800, 0x1000 }, 4228 { 0x03, 0, 0x0042 }, 4229 { 0x06, 0x0080, 0x0000 }, 4230 { 0x07, 0, 0x2000 } 4231 }; 4232 4233 rtl_set_def_aspm_entry_latency(tp); 4234 4235 rtl_ephy_init(tp, e_info_8168cp); 4236 4237 __rtl_hw_start_8168cp(tp); 4238 } 4239 4240 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 4241 { 4242 rtl_set_def_aspm_entry_latency(tp); 4243 4244 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4245 } 4246 4247 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 4248 { 4249 rtl_set_def_aspm_entry_latency(tp); 4250 4251 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4252 4253 /* Magic. */ 4254 RTL_W8(tp, DBG_REG, 0x20); 4255 } 4256 4257 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 4258 { 4259 static const struct ephy_info e_info_8168c_1[] = { 4260 { 0x02, 0x0800, 0x1000 }, 4261 { 0x03, 0, 0x0002 }, 4262 { 0x06, 0x0080, 0x0000 } 4263 }; 4264 4265 rtl_set_def_aspm_entry_latency(tp); 4266 4267 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 4268 4269 rtl_ephy_init(tp, e_info_8168c_1); 4270 4271 __rtl_hw_start_8168cp(tp); 4272 } 4273 4274 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 4275 { 4276 static const struct ephy_info e_info_8168c_2[] = { 4277 { 0x01, 0, 0x0001 }, 4278 { 0x03, 0x0400, 0x0020 } 4279 }; 4280 4281 rtl_set_def_aspm_entry_latency(tp); 4282 4283 rtl_ephy_init(tp, e_info_8168c_2); 4284 4285 __rtl_hw_start_8168cp(tp); 4286 } 4287 4288 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 4289 { 4290 rtl_hw_start_8168c_2(tp); 4291 } 4292 4293 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 4294 { 4295 rtl_set_def_aspm_entry_latency(tp); 4296 4297 __rtl_hw_start_8168cp(tp); 4298 } 4299 4300 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 4301 { 4302 rtl_set_def_aspm_entry_latency(tp); 4303 4304 rtl_disable_clock_request(tp); 4305 } 4306 4307 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 4308 { 4309 static const struct ephy_info e_info_8168d_4[] = { 4310 { 0x0b, 0x0000, 0x0048 }, 4311 { 0x19, 0x0020, 0x0050 }, 4312 { 0x0c, 0x0100, 0x0020 }, 4313 { 0x10, 0x0004, 0x0000 }, 4314 }; 4315 4316 rtl_set_def_aspm_entry_latency(tp); 4317 4318 rtl_ephy_init(tp, e_info_8168d_4); 4319 4320 rtl_enable_clock_request(tp); 4321 } 4322 4323 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 4324 { 4325 static const struct ephy_info e_info_8168e_1[] = { 4326 { 0x00, 0x0200, 0x0100 }, 4327 { 0x00, 0x0000, 0x0004 }, 4328 { 0x06, 0x0002, 0x0001 }, 4329 { 0x06, 0x0000, 0x0030 }, 4330 { 0x07, 0x0000, 0x2000 }, 4331 { 0x00, 0x0000, 0x0020 }, 4332 { 0x03, 0x5800, 0x2000 }, 4333 { 0x03, 0x0000, 0x0001 }, 4334 { 0x01, 0x0800, 0x1000 }, 4335 { 0x07, 0x0000, 0x4000 }, 4336 { 0x1e, 0x0000, 0x2000 }, 4337 { 0x19, 0xffff, 0xfe6c }, 4338 { 0x0a, 0x0000, 0x0040 } 4339 }; 4340 4341 rtl_set_def_aspm_entry_latency(tp); 4342 4343 rtl_ephy_init(tp, e_info_8168e_1); 4344 4345 rtl_disable_clock_request(tp); 4346 4347 /* Reset tx FIFO pointer */ 4348 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 4349 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 4350 4351 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4352 } 4353 4354 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 4355 { 4356 static const struct ephy_info e_info_8168e_2[] = { 4357 { 0x09, 0x0000, 0x0080 }, 4358 { 0x19, 0x0000, 0x0224 }, 4359 { 0x00, 0x0000, 0x0004 }, 4360 { 0x0c, 0x3df0, 0x0200 }, 4361 }; 4362 4363 rtl_set_def_aspm_entry_latency(tp); 4364 4365 rtl_ephy_init(tp, e_info_8168e_2); 4366 4367 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4368 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4369 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4370 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4371 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 4372 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4373 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4374 4375 rtl_disable_clock_request(tp); 4376 4377 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4378 4379 rtl8168_config_eee_mac(tp); 4380 4381 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4382 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4383 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4384 4385 rtl_hw_aspm_clkreq_enable(tp, true); 4386 } 4387 4388 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 4389 { 4390 rtl_set_def_aspm_entry_latency(tp); 4391 4392 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4393 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4394 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4395 rtl_reset_packet_filter(tp); 4396 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4397 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 4398 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4399 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 4400 4401 rtl_disable_clock_request(tp); 4402 4403 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4404 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4405 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4406 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4407 4408 rtl8168_config_eee_mac(tp); 4409 } 4410 4411 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 4412 { 4413 static const struct ephy_info e_info_8168f_1[] = { 4414 { 0x06, 0x00c0, 0x0020 }, 4415 { 0x08, 0x0001, 0x0002 }, 4416 { 0x09, 0x0000, 0x0080 }, 4417 { 0x19, 0x0000, 0x0224 }, 4418 { 0x00, 0x0000, 0x0004 }, 4419 { 0x0c, 0x3df0, 0x0200 }, 4420 }; 4421 4422 rtl_hw_start_8168f(tp); 4423 4424 rtl_ephy_init(tp, e_info_8168f_1); 4425 4426 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4427 } 4428 4429 static void rtl_hw_start_8411(struct rtl8169_private *tp) 4430 { 4431 static const struct ephy_info e_info_8168f_1[] = { 4432 { 0x06, 0x00c0, 0x0020 }, 4433 { 0x0f, 0xffff, 0x5200 }, 4434 { 0x19, 0x0000, 0x0224 }, 4435 { 0x00, 0x0000, 0x0004 }, 4436 { 0x0c, 0x3df0, 0x0200 }, 4437 }; 4438 4439 rtl_hw_start_8168f(tp); 4440 rtl_pcie_state_l2l3_disable(tp); 4441 4442 rtl_ephy_init(tp, e_info_8168f_1); 4443 4444 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 4445 } 4446 4447 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 4448 { 4449 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4450 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4451 4452 rtl_set_def_aspm_entry_latency(tp); 4453 4454 rtl_reset_packet_filter(tp); 4455 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 4456 4457 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4458 4459 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4460 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4461 4462 rtl8168_config_eee_mac(tp); 4463 4464 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4465 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4466 4467 rtl_pcie_state_l2l3_disable(tp); 4468 } 4469 4470 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 4471 { 4472 static const struct ephy_info e_info_8168g_1[] = { 4473 { 0x00, 0x0008, 0x0000 }, 4474 { 0x0c, 0x3ff0, 0x0820 }, 4475 { 0x1e, 0x0000, 0x0001 }, 4476 { 0x19, 0x8000, 0x0000 } 4477 }; 4478 4479 rtl_hw_start_8168g(tp); 4480 4481 /* disable aspm and clock request before access ephy */ 4482 rtl_hw_aspm_clkreq_enable(tp, false); 4483 rtl_ephy_init(tp, e_info_8168g_1); 4484 rtl_hw_aspm_clkreq_enable(tp, true); 4485 } 4486 4487 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 4488 { 4489 static const struct ephy_info e_info_8168g_2[] = { 4490 { 0x00, 0x0008, 0x0000 }, 4491 { 0x0c, 0x3ff0, 0x0820 }, 4492 { 0x19, 0xffff, 0x7c00 }, 4493 { 0x1e, 0xffff, 0x20eb }, 4494 { 0x0d, 0xffff, 0x1666 }, 4495 { 0x00, 0xffff, 0x10a3 }, 4496 { 0x06, 0xffff, 0xf050 }, 4497 { 0x04, 0x0000, 0x0010 }, 4498 { 0x1d, 0x4000, 0x0000 }, 4499 }; 4500 4501 rtl_hw_start_8168g(tp); 4502 4503 /* disable aspm and clock request before access ephy */ 4504 rtl_hw_aspm_clkreq_enable(tp, false); 4505 rtl_ephy_init(tp, e_info_8168g_2); 4506 } 4507 4508 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 4509 { 4510 static const struct ephy_info e_info_8411_2[] = { 4511 { 0x00, 0x0008, 0x0000 }, 4512 { 0x0c, 0x37d0, 0x0820 }, 4513 { 0x1e, 0x0000, 0x0001 }, 4514 { 0x19, 0x8021, 0x0000 }, 4515 { 0x1e, 0x0000, 0x2000 }, 4516 { 0x0d, 0x0100, 0x0200 }, 4517 { 0x00, 0x0000, 0x0080 }, 4518 { 0x06, 0x0000, 0x0010 }, 4519 { 0x04, 0x0000, 0x0010 }, 4520 { 0x1d, 0x0000, 0x4000 }, 4521 }; 4522 4523 rtl_hw_start_8168g(tp); 4524 4525 /* disable aspm and clock request before access ephy */ 4526 rtl_hw_aspm_clkreq_enable(tp, false); 4527 rtl_ephy_init(tp, e_info_8411_2); 4528 4529 /* The following Realtek-provided magic fixes an issue with the RX unit 4530 * getting confused after the PHY having been powered-down. 4531 */ 4532 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 4533 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 4534 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 4535 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 4536 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 4537 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 4538 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 4539 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 4540 mdelay(3); 4541 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 4542 4543 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 4544 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 4545 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 4546 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 4547 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 4548 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 4549 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 4550 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 4551 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 4552 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 4553 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 4554 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 4555 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 4556 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 4557 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 4558 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 4559 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 4560 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 4561 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 4562 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 4563 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 4564 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 4565 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 4566 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 4567 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 4568 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 4569 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 4570 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 4571 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 4572 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 4573 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 4574 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 4575 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 4576 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 4577 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 4578 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 4579 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 4580 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 4581 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 4582 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 4583 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 4584 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 4585 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 4586 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 4587 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 4588 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 4589 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 4590 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 4591 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 4592 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 4593 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 4594 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 4595 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 4596 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 4597 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 4598 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 4599 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 4600 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 4601 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 4602 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 4603 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 4604 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 4605 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 4606 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 4607 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 4608 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 4609 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 4610 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 4611 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 4612 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 4613 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 4614 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 4615 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 4616 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 4617 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 4618 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 4619 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 4620 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 4621 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 4622 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 4623 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 4624 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 4625 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 4626 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 4627 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 4628 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 4629 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 4630 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 4631 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 4632 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 4633 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 4634 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 4635 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 4636 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 4637 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 4638 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 4639 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 4640 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 4641 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 4642 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 4643 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 4644 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 4645 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 4646 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 4647 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 4648 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 4649 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 4650 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 4651 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 4652 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 4653 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 4654 4655 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 4656 4657 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 4658 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 4659 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 4660 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 4661 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 4662 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 4663 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 4664 4665 rtl_hw_aspm_clkreq_enable(tp, true); 4666 } 4667 4668 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 4669 { 4670 static const struct ephy_info e_info_8168h_1[] = { 4671 { 0x1e, 0x0800, 0x0001 }, 4672 { 0x1d, 0x0000, 0x0800 }, 4673 { 0x05, 0xffff, 0x2089 }, 4674 { 0x06, 0xffff, 0x5881 }, 4675 { 0x04, 0xffff, 0x854a }, 4676 { 0x01, 0xffff, 0x068b } 4677 }; 4678 int rg_saw_cnt; 4679 4680 /* disable aspm and clock request before access ephy */ 4681 rtl_hw_aspm_clkreq_enable(tp, false); 4682 rtl_ephy_init(tp, e_info_8168h_1); 4683 4684 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4685 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4686 4687 rtl_set_def_aspm_entry_latency(tp); 4688 4689 rtl_reset_packet_filter(tp); 4690 4691 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 4692 4693 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 4694 4695 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4696 4697 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4698 4699 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4700 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4701 4702 rtl8168_config_eee_mac(tp); 4703 4704 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4705 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4706 4707 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4708 4709 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4710 4711 rtl_pcie_state_l2l3_disable(tp); 4712 4713 rtl_writephy(tp, 0x1f, 0x0c42); 4714 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff); 4715 rtl_writephy(tp, 0x1f, 0x0000); 4716 if (rg_saw_cnt > 0) { 4717 u16 sw_cnt_1ms_ini; 4718 4719 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 4720 sw_cnt_1ms_ini &= 0x0fff; 4721 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 4722 } 4723 4724 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 4725 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 4726 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 4727 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 4728 4729 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 4730 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 4731 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 4732 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 4733 4734 rtl_hw_aspm_clkreq_enable(tp, true); 4735 } 4736 4737 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 4738 { 4739 rtl8168ep_stop_cmac(tp); 4740 4741 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4742 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 4743 4744 rtl_set_def_aspm_entry_latency(tp); 4745 4746 rtl_reset_packet_filter(tp); 4747 4748 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 4749 4750 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4751 4752 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4753 4754 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4755 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4756 4757 rtl8168_config_eee_mac(tp); 4758 4759 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4760 4761 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4762 4763 rtl_pcie_state_l2l3_disable(tp); 4764 } 4765 4766 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 4767 { 4768 static const struct ephy_info e_info_8168ep_1[] = { 4769 { 0x00, 0xffff, 0x10ab }, 4770 { 0x06, 0xffff, 0xf030 }, 4771 { 0x08, 0xffff, 0x2006 }, 4772 { 0x0d, 0xffff, 0x1666 }, 4773 { 0x0c, 0x3ff0, 0x0000 } 4774 }; 4775 4776 /* disable aspm and clock request before access ephy */ 4777 rtl_hw_aspm_clkreq_enable(tp, false); 4778 rtl_ephy_init(tp, e_info_8168ep_1); 4779 4780 rtl_hw_start_8168ep(tp); 4781 4782 rtl_hw_aspm_clkreq_enable(tp, true); 4783 } 4784 4785 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 4786 { 4787 static const struct ephy_info e_info_8168ep_2[] = { 4788 { 0x00, 0xffff, 0x10a3 }, 4789 { 0x19, 0xffff, 0xfc00 }, 4790 { 0x1e, 0xffff, 0x20ea } 4791 }; 4792 4793 /* disable aspm and clock request before access ephy */ 4794 rtl_hw_aspm_clkreq_enable(tp, false); 4795 rtl_ephy_init(tp, e_info_8168ep_2); 4796 4797 rtl_hw_start_8168ep(tp); 4798 4799 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4800 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4801 4802 rtl_hw_aspm_clkreq_enable(tp, true); 4803 } 4804 4805 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 4806 { 4807 static const struct ephy_info e_info_8168ep_3[] = { 4808 { 0x00, 0x0000, 0x0080 }, 4809 { 0x0d, 0x0100, 0x0200 }, 4810 { 0x19, 0x8021, 0x0000 }, 4811 { 0x1e, 0x0000, 0x2000 }, 4812 }; 4813 4814 /* disable aspm and clock request before access ephy */ 4815 rtl_hw_aspm_clkreq_enable(tp, false); 4816 rtl_ephy_init(tp, e_info_8168ep_3); 4817 4818 rtl_hw_start_8168ep(tp); 4819 4820 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4821 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4822 4823 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 4824 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 4825 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 4826 4827 rtl_hw_aspm_clkreq_enable(tp, true); 4828 } 4829 4830 static void rtl_hw_start_8117(struct rtl8169_private *tp) 4831 { 4832 static const struct ephy_info e_info_8117[] = { 4833 { 0x19, 0x0040, 0x1100 }, 4834 { 0x59, 0x0040, 0x1100 }, 4835 }; 4836 int rg_saw_cnt; 4837 4838 rtl8168ep_stop_cmac(tp); 4839 4840 /* disable aspm and clock request before access ephy */ 4841 rtl_hw_aspm_clkreq_enable(tp, false); 4842 rtl_ephy_init(tp, e_info_8117); 4843 4844 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4845 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 4846 4847 rtl_set_def_aspm_entry_latency(tp); 4848 4849 rtl_reset_packet_filter(tp); 4850 4851 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90); 4852 4853 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4854 4855 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4856 4857 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4858 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4859 4860 rtl8168_config_eee_mac(tp); 4861 4862 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4863 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4864 4865 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4866 4867 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4868 4869 rtl_pcie_state_l2l3_disable(tp); 4870 4871 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 4872 if (rg_saw_cnt > 0) { 4873 u16 sw_cnt_1ms_ini; 4874 4875 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 4876 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 4877 } 4878 4879 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 4880 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 4881 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 4882 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 4883 4884 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 4885 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 4886 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 4887 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 4888 4889 /* firmware is for MAC only */ 4890 rtl_apply_firmware(tp); 4891 4892 rtl_hw_aspm_clkreq_enable(tp, true); 4893 } 4894 4895 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 4896 { 4897 static const struct ephy_info e_info_8102e_1[] = { 4898 { 0x01, 0, 0x6e65 }, 4899 { 0x02, 0, 0x091f }, 4900 { 0x03, 0, 0xc2f9 }, 4901 { 0x06, 0, 0xafb5 }, 4902 { 0x07, 0, 0x0e00 }, 4903 { 0x19, 0, 0xec80 }, 4904 { 0x01, 0, 0x2e65 }, 4905 { 0x01, 0, 0x6e65 } 4906 }; 4907 u8 cfg1; 4908 4909 rtl_set_def_aspm_entry_latency(tp); 4910 4911 RTL_W8(tp, DBG_REG, FIX_NAK_1); 4912 4913 RTL_W8(tp, Config1, 4914 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 4915 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4916 4917 cfg1 = RTL_R8(tp, Config1); 4918 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 4919 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 4920 4921 rtl_ephy_init(tp, e_info_8102e_1); 4922 } 4923 4924 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 4925 { 4926 rtl_set_def_aspm_entry_latency(tp); 4927 4928 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 4929 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4930 } 4931 4932 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 4933 { 4934 rtl_hw_start_8102e_2(tp); 4935 4936 rtl_ephy_write(tp, 0x03, 0xc2f9); 4937 } 4938 4939 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 4940 { 4941 static const struct ephy_info e_info_8105e_1[] = { 4942 { 0x07, 0, 0x4000 }, 4943 { 0x19, 0, 0x0200 }, 4944 { 0x19, 0, 0x0020 }, 4945 { 0x1e, 0, 0x2000 }, 4946 { 0x03, 0, 0x0001 }, 4947 { 0x19, 0, 0x0100 }, 4948 { 0x19, 0, 0x0004 }, 4949 { 0x0a, 0, 0x0020 } 4950 }; 4951 4952 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 4953 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 4954 4955 /* Disable Early Tally Counter */ 4956 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 4957 4958 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 4959 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4960 4961 rtl_ephy_init(tp, e_info_8105e_1); 4962 4963 rtl_pcie_state_l2l3_disable(tp); 4964 } 4965 4966 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 4967 { 4968 rtl_hw_start_8105e_1(tp); 4969 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 4970 } 4971 4972 static void rtl_hw_start_8402(struct rtl8169_private *tp) 4973 { 4974 static const struct ephy_info e_info_8402[] = { 4975 { 0x19, 0xffff, 0xff64 }, 4976 { 0x1e, 0, 0x4000 } 4977 }; 4978 4979 rtl_set_def_aspm_entry_latency(tp); 4980 4981 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 4982 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 4983 4984 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4985 4986 rtl_ephy_init(tp, e_info_8402); 4987 4988 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 4989 rtl_reset_packet_filter(tp); 4990 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4991 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4992 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 4993 4994 rtl_pcie_state_l2l3_disable(tp); 4995 } 4996 4997 static void rtl_hw_start_8106(struct rtl8169_private *tp) 4998 { 4999 rtl_hw_aspm_clkreq_enable(tp, false); 5000 5001 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5002 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5003 5004 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 5005 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5006 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5007 5008 rtl_pcie_state_l2l3_disable(tp); 5009 rtl_hw_aspm_clkreq_enable(tp, true); 5010 } 5011 5012 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 5013 { 5014 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 5015 } 5016 5017 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 5018 { 5019 rtl_pcie_state_l2l3_disable(tp); 5020 5021 RTL_W16(tp, 0x382, 0x221b); 5022 RTL_W8(tp, 0x4500, 0); 5023 RTL_W16(tp, 0x4800, 0); 5024 5025 /* disable UPS */ 5026 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 5027 5028 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 5029 5030 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 5031 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 5032 5033 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 5034 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5035 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5036 5037 /* disable new tx descriptor format */ 5038 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 5039 5040 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 5041 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 5042 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 5043 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 5044 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 5045 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 5046 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 5047 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 5048 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 5049 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 5050 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 5051 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 5052 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 5053 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 5054 udelay(1); 5055 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 5056 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 5057 5058 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 5059 5060 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 5061 5062 rtl8125_config_eee_mac(tp); 5063 5064 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 5065 udelay(10); 5066 } 5067 5068 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 5069 { 5070 static const struct ephy_info e_info_8125_1[] = { 5071 { 0x01, 0xffff, 0xa812 }, 5072 { 0x09, 0xffff, 0x520c }, 5073 { 0x04, 0xffff, 0xd000 }, 5074 { 0x0d, 0xffff, 0xf702 }, 5075 { 0x0a, 0xffff, 0x8653 }, 5076 { 0x06, 0xffff, 0x001e }, 5077 { 0x08, 0xffff, 0x3595 }, 5078 { 0x20, 0xffff, 0x9455 }, 5079 { 0x21, 0xffff, 0x99ff }, 5080 { 0x02, 0xffff, 0x6046 }, 5081 { 0x29, 0xffff, 0xfe00 }, 5082 { 0x23, 0xffff, 0xab62 }, 5083 5084 { 0x41, 0xffff, 0xa80c }, 5085 { 0x49, 0xffff, 0x520c }, 5086 { 0x44, 0xffff, 0xd000 }, 5087 { 0x4d, 0xffff, 0xf702 }, 5088 { 0x4a, 0xffff, 0x8653 }, 5089 { 0x46, 0xffff, 0x001e }, 5090 { 0x48, 0xffff, 0x3595 }, 5091 { 0x60, 0xffff, 0x9455 }, 5092 { 0x61, 0xffff, 0x99ff }, 5093 { 0x42, 0xffff, 0x6046 }, 5094 { 0x69, 0xffff, 0xfe00 }, 5095 { 0x63, 0xffff, 0xab62 }, 5096 }; 5097 5098 rtl_set_def_aspm_entry_latency(tp); 5099 5100 /* disable aspm and clock request before access ephy */ 5101 rtl_hw_aspm_clkreq_enable(tp, false); 5102 rtl_ephy_init(tp, e_info_8125_1); 5103 5104 rtl_hw_start_8125_common(tp); 5105 } 5106 5107 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 5108 { 5109 static const struct ephy_info e_info_8125_2[] = { 5110 { 0x04, 0xffff, 0xd000 }, 5111 { 0x0a, 0xffff, 0x8653 }, 5112 { 0x23, 0xffff, 0xab66 }, 5113 { 0x20, 0xffff, 0x9455 }, 5114 { 0x21, 0xffff, 0x99ff }, 5115 { 0x29, 0xffff, 0xfe04 }, 5116 5117 { 0x44, 0xffff, 0xd000 }, 5118 { 0x4a, 0xffff, 0x8653 }, 5119 { 0x63, 0xffff, 0xab66 }, 5120 { 0x60, 0xffff, 0x9455 }, 5121 { 0x61, 0xffff, 0x99ff }, 5122 { 0x69, 0xffff, 0xfe04 }, 5123 }; 5124 5125 rtl_set_def_aspm_entry_latency(tp); 5126 5127 /* disable aspm and clock request before access ephy */ 5128 rtl_hw_aspm_clkreq_enable(tp, false); 5129 rtl_ephy_init(tp, e_info_8125_2); 5130 5131 rtl_hw_start_8125_common(tp); 5132 } 5133 5134 static void rtl_hw_config(struct rtl8169_private *tp) 5135 { 5136 static const rtl_generic_fct hw_configs[] = { 5137 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 5138 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 5139 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 5140 [RTL_GIGA_MAC_VER_10] = NULL, 5141 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 5142 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 5143 [RTL_GIGA_MAC_VER_13] = NULL, 5144 [RTL_GIGA_MAC_VER_14] = NULL, 5145 [RTL_GIGA_MAC_VER_15] = NULL, 5146 [RTL_GIGA_MAC_VER_16] = NULL, 5147 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 5148 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 5149 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 5150 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 5151 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 5152 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 5153 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 5154 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 5155 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 5156 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 5157 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 5158 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 5159 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 5160 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 5161 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 5162 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 5163 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 5164 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 5165 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 5166 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 5167 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 5168 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 5169 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 5170 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 5171 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 5172 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 5173 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 5174 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 5175 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 5176 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 5177 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 5178 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 5179 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 5180 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 5181 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 5182 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 5183 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 5184 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 5185 }; 5186 5187 if (hw_configs[tp->mac_version]) 5188 hw_configs[tp->mac_version](tp); 5189 } 5190 5191 static void rtl_hw_start_8125(struct rtl8169_private *tp) 5192 { 5193 int i; 5194 5195 /* disable interrupt coalescing */ 5196 for (i = 0xa00; i < 0xb00; i += 4) 5197 RTL_W32(tp, i, 0); 5198 5199 rtl_hw_config(tp); 5200 } 5201 5202 static void rtl_hw_start_8168(struct rtl8169_private *tp) 5203 { 5204 if (rtl_is_8168evl_up(tp)) 5205 RTL_W8(tp, MaxTxPacketSize, EarlySize); 5206 else 5207 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5208 5209 rtl_hw_config(tp); 5210 5211 /* disable interrupt coalescing */ 5212 RTL_W16(tp, IntrMitigate, 0x0000); 5213 } 5214 5215 static void rtl_hw_start_8169(struct rtl8169_private *tp) 5216 { 5217 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5218 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 5219 5220 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 5221 5222 tp->cp_cmd |= PCIMulRW; 5223 5224 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 5225 tp->mac_version == RTL_GIGA_MAC_VER_03) { 5226 netif_dbg(tp, drv, tp->dev, 5227 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n"); 5228 tp->cp_cmd |= (1 << 14); 5229 } 5230 5231 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5232 5233 rtl8169_set_magic_reg(tp, tp->mac_version); 5234 5235 RTL_W32(tp, RxMissed, 0); 5236 5237 /* disable interrupt coalescing */ 5238 RTL_W16(tp, IntrMitigate, 0x0000); 5239 } 5240 5241 static void rtl_hw_start(struct rtl8169_private *tp) 5242 { 5243 rtl_unlock_config_regs(tp); 5244 5245 tp->cp_cmd &= CPCMD_MASK; 5246 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5247 5248 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5249 rtl_hw_start_8169(tp); 5250 else if (rtl_is_8125(tp)) 5251 rtl_hw_start_8125(tp); 5252 else 5253 rtl_hw_start_8168(tp); 5254 5255 rtl_set_rx_max_size(tp); 5256 rtl_set_rx_tx_desc_registers(tp); 5257 rtl_lock_config_regs(tp); 5258 5259 rtl_jumbo_config(tp, tp->dev->mtu); 5260 5261 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 5262 RTL_R16(tp, CPlusCmd); 5263 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 5264 rtl_init_rxcfg(tp); 5265 rtl_set_tx_config_registers(tp); 5266 rtl_set_rx_mode(tp->dev); 5267 rtl_irq_enable(tp); 5268 } 5269 5270 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 5271 { 5272 struct rtl8169_private *tp = netdev_priv(dev); 5273 5274 rtl_jumbo_config(tp, new_mtu); 5275 5276 dev->mtu = new_mtu; 5277 netdev_update_features(dev); 5278 5279 return 0; 5280 } 5281 5282 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 5283 { 5284 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); 5285 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 5286 } 5287 5288 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 5289 { 5290 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 5291 5292 /* Force memory writes to complete before releasing descriptor */ 5293 dma_wmb(); 5294 5295 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 5296 } 5297 5298 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 5299 struct RxDesc *desc) 5300 { 5301 struct device *d = tp_to_dev(tp); 5302 int node = dev_to_node(d); 5303 dma_addr_t mapping; 5304 struct page *data; 5305 5306 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 5307 if (!data) 5308 return NULL; 5309 5310 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5311 if (unlikely(dma_mapping_error(d, mapping))) { 5312 if (net_ratelimit()) 5313 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 5314 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 5315 return NULL; 5316 } 5317 5318 desc->addr = cpu_to_le64(mapping); 5319 rtl8169_mark_to_asic(desc); 5320 5321 return data; 5322 } 5323 5324 static void rtl8169_rx_clear(struct rtl8169_private *tp) 5325 { 5326 unsigned int i; 5327 5328 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 5329 dma_unmap_page(tp_to_dev(tp), 5330 le64_to_cpu(tp->RxDescArray[i].addr), 5331 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5332 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 5333 tp->Rx_databuff[i] = NULL; 5334 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5335 } 5336 } 5337 5338 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 5339 { 5340 desc->opts1 |= cpu_to_le32(RingEnd); 5341 } 5342 5343 static int rtl8169_rx_fill(struct rtl8169_private *tp) 5344 { 5345 unsigned int i; 5346 5347 for (i = 0; i < NUM_RX_DESC; i++) { 5348 struct page *data; 5349 5350 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 5351 if (!data) { 5352 rtl8169_rx_clear(tp); 5353 return -ENOMEM; 5354 } 5355 tp->Rx_databuff[i] = data; 5356 } 5357 5358 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 5359 5360 return 0; 5361 } 5362 5363 static int rtl8169_init_ring(struct rtl8169_private *tp) 5364 { 5365 rtl8169_init_ring_indexes(tp); 5366 5367 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 5368 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 5369 5370 return rtl8169_rx_fill(tp); 5371 } 5372 5373 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, 5374 struct TxDesc *desc) 5375 { 5376 unsigned int len = tx_skb->len; 5377 5378 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); 5379 5380 desc->opts1 = 0x00; 5381 desc->opts2 = 0x00; 5382 desc->addr = 0x00; 5383 tx_skb->len = 0; 5384 } 5385 5386 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 5387 unsigned int n) 5388 { 5389 unsigned int i; 5390 5391 for (i = 0; i < n; i++) { 5392 unsigned int entry = (start + i) % NUM_TX_DESC; 5393 struct ring_info *tx_skb = tp->tx_skb + entry; 5394 unsigned int len = tx_skb->len; 5395 5396 if (len) { 5397 struct sk_buff *skb = tx_skb->skb; 5398 5399 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5400 tp->TxDescArray + entry); 5401 if (skb) { 5402 dev_consume_skb_any(skb); 5403 tx_skb->skb = NULL; 5404 } 5405 } 5406 } 5407 } 5408 5409 static void rtl8169_tx_clear(struct rtl8169_private *tp) 5410 { 5411 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 5412 tp->cur_tx = tp->dirty_tx = 0; 5413 netdev_reset_queue(tp->dev); 5414 } 5415 5416 static void rtl_reset_work(struct rtl8169_private *tp) 5417 { 5418 struct net_device *dev = tp->dev; 5419 int i; 5420 5421 napi_disable(&tp->napi); 5422 netif_stop_queue(dev); 5423 synchronize_rcu(); 5424 5425 rtl8169_hw_reset(tp); 5426 5427 for (i = 0; i < NUM_RX_DESC; i++) 5428 rtl8169_mark_to_asic(tp->RxDescArray + i); 5429 5430 rtl8169_tx_clear(tp); 5431 rtl8169_init_ring_indexes(tp); 5432 5433 napi_enable(&tp->napi); 5434 rtl_hw_start(tp); 5435 netif_wake_queue(dev); 5436 } 5437 5438 static void rtl8169_tx_timeout(struct net_device *dev) 5439 { 5440 struct rtl8169_private *tp = netdev_priv(dev); 5441 5442 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5443 } 5444 5445 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry) 5446 { 5447 u32 status = opts0 | len; 5448 5449 if (entry == NUM_TX_DESC - 1) 5450 status |= RingEnd; 5451 5452 return cpu_to_le32(status); 5453 } 5454 5455 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 5456 u32 *opts) 5457 { 5458 struct skb_shared_info *info = skb_shinfo(skb); 5459 unsigned int cur_frag, entry; 5460 struct TxDesc *uninitialized_var(txd); 5461 struct device *d = tp_to_dev(tp); 5462 5463 entry = tp->cur_tx; 5464 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 5465 const skb_frag_t *frag = info->frags + cur_frag; 5466 dma_addr_t mapping; 5467 u32 len; 5468 void *addr; 5469 5470 entry = (entry + 1) % NUM_TX_DESC; 5471 5472 txd = tp->TxDescArray + entry; 5473 len = skb_frag_size(frag); 5474 addr = skb_frag_address(frag); 5475 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 5476 if (unlikely(dma_mapping_error(d, mapping))) { 5477 if (net_ratelimit()) 5478 netif_err(tp, drv, tp->dev, 5479 "Failed to map TX fragments DMA!\n"); 5480 goto err_out; 5481 } 5482 5483 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5484 txd->opts2 = cpu_to_le32(opts[1]); 5485 txd->addr = cpu_to_le64(mapping); 5486 5487 tp->tx_skb[entry].len = len; 5488 } 5489 5490 if (cur_frag) { 5491 tp->tx_skb[entry].skb = skb; 5492 txd->opts1 |= cpu_to_le32(LastFrag); 5493 } 5494 5495 return cur_frag; 5496 5497 err_out: 5498 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 5499 return -EIO; 5500 } 5501 5502 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 5503 { 5504 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 5505 } 5506 5507 /* msdn_giant_send_check() 5508 * According to the document of microsoft, the TCP Pseudo Header excludes the 5509 * packet length for IPv6 TCP large packets. 5510 */ 5511 static int msdn_giant_send_check(struct sk_buff *skb) 5512 { 5513 const struct ipv6hdr *ipv6h; 5514 struct tcphdr *th; 5515 int ret; 5516 5517 ret = skb_cow_head(skb, 0); 5518 if (ret) 5519 return ret; 5520 5521 ipv6h = ipv6_hdr(skb); 5522 th = tcp_hdr(skb); 5523 5524 th->check = 0; 5525 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 5526 5527 return ret; 5528 } 5529 5530 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 5531 { 5532 u32 mss = skb_shinfo(skb)->gso_size; 5533 5534 if (mss) { 5535 opts[0] |= TD_LSO; 5536 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; 5537 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5538 const struct iphdr *ip = ip_hdr(skb); 5539 5540 if (ip->protocol == IPPROTO_TCP) 5541 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 5542 else if (ip->protocol == IPPROTO_UDP) 5543 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 5544 else 5545 WARN_ON_ONCE(1); 5546 } 5547 } 5548 5549 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 5550 struct sk_buff *skb, u32 *opts) 5551 { 5552 u32 transport_offset = (u32)skb_transport_offset(skb); 5553 u32 mss = skb_shinfo(skb)->gso_size; 5554 5555 if (mss) { 5556 switch (vlan_get_protocol(skb)) { 5557 case htons(ETH_P_IP): 5558 opts[0] |= TD1_GTSENV4; 5559 break; 5560 5561 case htons(ETH_P_IPV6): 5562 if (msdn_giant_send_check(skb)) 5563 return false; 5564 5565 opts[0] |= TD1_GTSENV6; 5566 break; 5567 5568 default: 5569 WARN_ON_ONCE(1); 5570 break; 5571 } 5572 5573 opts[0] |= transport_offset << GTTCPHO_SHIFT; 5574 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; 5575 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5576 u8 ip_protocol; 5577 5578 switch (vlan_get_protocol(skb)) { 5579 case htons(ETH_P_IP): 5580 opts[1] |= TD1_IPv4_CS; 5581 ip_protocol = ip_hdr(skb)->protocol; 5582 break; 5583 5584 case htons(ETH_P_IPV6): 5585 opts[1] |= TD1_IPv6_CS; 5586 ip_protocol = ipv6_hdr(skb)->nexthdr; 5587 break; 5588 5589 default: 5590 ip_protocol = IPPROTO_RAW; 5591 break; 5592 } 5593 5594 if (ip_protocol == IPPROTO_TCP) 5595 opts[1] |= TD1_TCP_CS; 5596 else if (ip_protocol == IPPROTO_UDP) 5597 opts[1] |= TD1_UDP_CS; 5598 else 5599 WARN_ON_ONCE(1); 5600 5601 opts[1] |= transport_offset << TCPHO_SHIFT; 5602 } else { 5603 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 5604 return !eth_skb_pad(skb); 5605 } 5606 5607 return true; 5608 } 5609 5610 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 5611 unsigned int nr_frags) 5612 { 5613 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 5614 5615 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 5616 return slots_avail > nr_frags; 5617 } 5618 5619 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 5620 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 5621 { 5622 switch (tp->mac_version) { 5623 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5624 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 5625 return false; 5626 default: 5627 return true; 5628 } 5629 } 5630 5631 static void rtl8169_doorbell(struct rtl8169_private *tp) 5632 { 5633 if (rtl_is_8125(tp)) 5634 RTL_W16(tp, TxPoll_8125, BIT(0)); 5635 else 5636 RTL_W8(tp, TxPoll, NPQ); 5637 } 5638 5639 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 5640 struct net_device *dev) 5641 { 5642 struct rtl8169_private *tp = netdev_priv(dev); 5643 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 5644 struct TxDesc *txd = tp->TxDescArray + entry; 5645 struct device *d = tp_to_dev(tp); 5646 dma_addr_t mapping; 5647 u32 opts[2], len; 5648 bool stop_queue; 5649 bool door_bell; 5650 int frags; 5651 5652 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) { 5653 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 5654 goto err_stop_0; 5655 } 5656 5657 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 5658 goto err_stop_0; 5659 5660 opts[1] = rtl8169_tx_vlan_tag(skb); 5661 opts[0] = DescOwn; 5662 5663 if (rtl_chip_supports_csum_v2(tp)) { 5664 if (!rtl8169_tso_csum_v2(tp, skb, opts)) 5665 goto err_dma_0; 5666 } else { 5667 rtl8169_tso_csum_v1(skb, opts); 5668 } 5669 5670 len = skb_headlen(skb); 5671 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); 5672 if (unlikely(dma_mapping_error(d, mapping))) { 5673 if (net_ratelimit()) 5674 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); 5675 goto err_dma_0; 5676 } 5677 5678 tp->tx_skb[entry].len = len; 5679 txd->addr = cpu_to_le64(mapping); 5680 5681 frags = rtl8169_xmit_frags(tp, skb, opts); 5682 if (frags < 0) 5683 goto err_dma_1; 5684 else if (frags) 5685 opts[0] |= FirstFrag; 5686 else { 5687 opts[0] |= FirstFrag | LastFrag; 5688 tp->tx_skb[entry].skb = skb; 5689 } 5690 5691 txd->opts2 = cpu_to_le32(opts[1]); 5692 5693 skb_tx_timestamp(skb); 5694 5695 /* Force memory writes to complete before releasing descriptor */ 5696 dma_wmb(); 5697 5698 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 5699 5700 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5701 5702 /* Force all memory writes to complete before notifying device */ 5703 wmb(); 5704 5705 tp->cur_tx += frags + 1; 5706 5707 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 5708 if (unlikely(stop_queue)) { 5709 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 5710 * not miss a ring update when it notices a stopped queue. 5711 */ 5712 smp_wmb(); 5713 netif_stop_queue(dev); 5714 door_bell = true; 5715 } 5716 5717 if (door_bell) 5718 rtl8169_doorbell(tp); 5719 5720 if (unlikely(stop_queue)) { 5721 /* Sync with rtl_tx: 5722 * - publish queue status and cur_tx ring index (write barrier) 5723 * - refresh dirty_tx ring index (read barrier). 5724 * May the current thread have a pessimistic view of the ring 5725 * status and forget to wake up queue, a racing rtl_tx thread 5726 * can't. 5727 */ 5728 smp_mb(); 5729 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 5730 netif_start_queue(dev); 5731 } 5732 5733 return NETDEV_TX_OK; 5734 5735 err_dma_1: 5736 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); 5737 err_dma_0: 5738 dev_kfree_skb_any(skb); 5739 dev->stats.tx_dropped++; 5740 return NETDEV_TX_OK; 5741 5742 err_stop_0: 5743 netif_stop_queue(dev); 5744 dev->stats.tx_dropped++; 5745 return NETDEV_TX_BUSY; 5746 } 5747 5748 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 5749 struct net_device *dev, 5750 netdev_features_t features) 5751 { 5752 int transport_offset = skb_transport_offset(skb); 5753 struct rtl8169_private *tp = netdev_priv(dev); 5754 5755 if (skb_is_gso(skb)) { 5756 if (transport_offset > GTTCPHO_MAX && 5757 rtl_chip_supports_csum_v2(tp)) 5758 features &= ~NETIF_F_ALL_TSO; 5759 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5760 if (skb->len < ETH_ZLEN) { 5761 switch (tp->mac_version) { 5762 case RTL_GIGA_MAC_VER_11: 5763 case RTL_GIGA_MAC_VER_12: 5764 case RTL_GIGA_MAC_VER_17: 5765 case RTL_GIGA_MAC_VER_34: 5766 features &= ~NETIF_F_CSUM_MASK; 5767 break; 5768 default: 5769 break; 5770 } 5771 } 5772 5773 if (transport_offset > TCPHO_MAX && 5774 rtl_chip_supports_csum_v2(tp)) 5775 features &= ~NETIF_F_CSUM_MASK; 5776 } 5777 5778 return vlan_features_check(skb, features); 5779 } 5780 5781 static void rtl8169_pcierr_interrupt(struct net_device *dev) 5782 { 5783 struct rtl8169_private *tp = netdev_priv(dev); 5784 struct pci_dev *pdev = tp->pci_dev; 5785 u16 pci_status, pci_cmd; 5786 5787 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 5788 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 5789 5790 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", 5791 pci_cmd, pci_status); 5792 5793 /* 5794 * The recovery sequence below admits a very elaborated explanation: 5795 * - it seems to work; 5796 * - I did not see what else could be done; 5797 * - it makes iop3xx happy. 5798 * 5799 * Feel free to adjust to your needs. 5800 */ 5801 if (pdev->broken_parity_status) 5802 pci_cmd &= ~PCI_COMMAND_PARITY; 5803 else 5804 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 5805 5806 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 5807 5808 pci_write_config_word(pdev, PCI_STATUS, 5809 pci_status & (PCI_STATUS_DETECTED_PARITY | 5810 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | 5811 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); 5812 5813 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5814 } 5815 5816 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 5817 int budget) 5818 { 5819 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 5820 5821 dirty_tx = tp->dirty_tx; 5822 smp_rmb(); 5823 tx_left = tp->cur_tx - dirty_tx; 5824 5825 while (tx_left > 0) { 5826 unsigned int entry = dirty_tx % NUM_TX_DESC; 5827 struct ring_info *tx_skb = tp->tx_skb + entry; 5828 u32 status; 5829 5830 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 5831 if (status & DescOwn) 5832 break; 5833 5834 /* This barrier is needed to keep us from reading 5835 * any other fields out of the Tx descriptor until 5836 * we know the status of DescOwn 5837 */ 5838 dma_rmb(); 5839 5840 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5841 tp->TxDescArray + entry); 5842 if (tx_skb->skb) { 5843 pkts_compl++; 5844 bytes_compl += tx_skb->skb->len; 5845 napi_consume_skb(tx_skb->skb, budget); 5846 tx_skb->skb = NULL; 5847 } 5848 dirty_tx++; 5849 tx_left--; 5850 } 5851 5852 if (tp->dirty_tx != dirty_tx) { 5853 netdev_completed_queue(dev, pkts_compl, bytes_compl); 5854 5855 u64_stats_update_begin(&tp->tx_stats.syncp); 5856 tp->tx_stats.packets += pkts_compl; 5857 tp->tx_stats.bytes += bytes_compl; 5858 u64_stats_update_end(&tp->tx_stats.syncp); 5859 5860 tp->dirty_tx = dirty_tx; 5861 /* Sync with rtl8169_start_xmit: 5862 * - publish dirty_tx ring index (write barrier) 5863 * - refresh cur_tx ring index and queue status (read barrier) 5864 * May the current thread miss the stopped queue condition, 5865 * a racing xmit thread can only have a right view of the 5866 * ring status. 5867 */ 5868 smp_mb(); 5869 if (netif_queue_stopped(dev) && 5870 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 5871 netif_wake_queue(dev); 5872 } 5873 /* 5874 * 8168 hack: TxPoll requests are lost when the Tx packets are 5875 * too close. Let's kick an extra TxPoll request when a burst 5876 * of start_xmit activity is detected (if it is not detected, 5877 * it is slow enough). -- FR 5878 */ 5879 if (tp->cur_tx != dirty_tx) 5880 rtl8169_doorbell(tp); 5881 } 5882 } 5883 5884 static inline int rtl8169_fragmented_frame(u32 status) 5885 { 5886 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 5887 } 5888 5889 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 5890 { 5891 u32 status = opts1 & RxProtoMask; 5892 5893 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 5894 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 5895 skb->ip_summed = CHECKSUM_UNNECESSARY; 5896 else 5897 skb_checksum_none_assert(skb); 5898 } 5899 5900 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 5901 { 5902 unsigned int cur_rx, rx_left; 5903 unsigned int count; 5904 5905 cur_rx = tp->cur_rx; 5906 5907 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 5908 unsigned int entry = cur_rx % NUM_RX_DESC; 5909 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 5910 struct RxDesc *desc = tp->RxDescArray + entry; 5911 u32 status; 5912 5913 status = le32_to_cpu(desc->opts1); 5914 if (status & DescOwn) 5915 break; 5916 5917 /* This barrier is needed to keep us from reading 5918 * any other fields out of the Rx descriptor until 5919 * we know the status of DescOwn 5920 */ 5921 dma_rmb(); 5922 5923 if (unlikely(status & RxRES)) { 5924 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 5925 status); 5926 dev->stats.rx_errors++; 5927 if (status & (RxRWT | RxRUNT)) 5928 dev->stats.rx_length_errors++; 5929 if (status & RxCRC) 5930 dev->stats.rx_crc_errors++; 5931 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 5932 dev->features & NETIF_F_RXALL) { 5933 goto process_pkt; 5934 } 5935 } else { 5936 unsigned int pkt_size; 5937 struct sk_buff *skb; 5938 5939 process_pkt: 5940 pkt_size = status & GENMASK(13, 0); 5941 if (likely(!(dev->features & NETIF_F_RXFCS))) 5942 pkt_size -= ETH_FCS_LEN; 5943 /* 5944 * The driver does not support incoming fragmented 5945 * frames. They are seen as a symptom of over-mtu 5946 * sized frames. 5947 */ 5948 if (unlikely(rtl8169_fragmented_frame(status))) { 5949 dev->stats.rx_dropped++; 5950 dev->stats.rx_length_errors++; 5951 goto release_descriptor; 5952 } 5953 5954 skb = napi_alloc_skb(&tp->napi, pkt_size); 5955 if (unlikely(!skb)) { 5956 dev->stats.rx_dropped++; 5957 goto release_descriptor; 5958 } 5959 5960 dma_sync_single_for_cpu(tp_to_dev(tp), 5961 le64_to_cpu(desc->addr), 5962 pkt_size, DMA_FROM_DEVICE); 5963 prefetch(rx_buf); 5964 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 5965 skb->tail += pkt_size; 5966 skb->len = pkt_size; 5967 5968 dma_sync_single_for_device(tp_to_dev(tp), 5969 le64_to_cpu(desc->addr), 5970 pkt_size, DMA_FROM_DEVICE); 5971 5972 rtl8169_rx_csum(skb, status); 5973 skb->protocol = eth_type_trans(skb, dev); 5974 5975 rtl8169_rx_vlan_tag(desc, skb); 5976 5977 if (skb->pkt_type == PACKET_MULTICAST) 5978 dev->stats.multicast++; 5979 5980 napi_gro_receive(&tp->napi, skb); 5981 5982 u64_stats_update_begin(&tp->rx_stats.syncp); 5983 tp->rx_stats.packets++; 5984 tp->rx_stats.bytes += pkt_size; 5985 u64_stats_update_end(&tp->rx_stats.syncp); 5986 } 5987 release_descriptor: 5988 desc->opts2 = 0; 5989 rtl8169_mark_to_asic(desc); 5990 } 5991 5992 count = cur_rx - tp->cur_rx; 5993 tp->cur_rx = cur_rx; 5994 5995 return count; 5996 } 5997 5998 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 5999 { 6000 struct rtl8169_private *tp = dev_instance; 6001 u32 status = rtl_get_events(tp); 6002 6003 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 6004 !(status & tp->irq_mask)) 6005 return IRQ_NONE; 6006 6007 if (unlikely(status & SYSErr)) { 6008 rtl8169_pcierr_interrupt(tp->dev); 6009 goto out; 6010 } 6011 6012 if (status & LinkChg) 6013 phy_mac_interrupt(tp->phydev); 6014 6015 if (unlikely(status & RxFIFOOver && 6016 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 6017 netif_stop_queue(tp->dev); 6018 /* XXX - Hack alert. See rtl_task(). */ 6019 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); 6020 } 6021 6022 rtl_irq_disable(tp); 6023 napi_schedule_irqoff(&tp->napi); 6024 out: 6025 rtl_ack_events(tp, status); 6026 6027 return IRQ_HANDLED; 6028 } 6029 6030 static void rtl_task(struct work_struct *work) 6031 { 6032 static const struct { 6033 int bitnr; 6034 void (*action)(struct rtl8169_private *); 6035 } rtl_work[] = { 6036 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, 6037 }; 6038 struct rtl8169_private *tp = 6039 container_of(work, struct rtl8169_private, wk.work); 6040 struct net_device *dev = tp->dev; 6041 int i; 6042 6043 rtl_lock_work(tp); 6044 6045 if (!netif_running(dev) || 6046 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 6047 goto out_unlock; 6048 6049 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { 6050 bool pending; 6051 6052 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); 6053 if (pending) 6054 rtl_work[i].action(tp); 6055 } 6056 6057 out_unlock: 6058 rtl_unlock_work(tp); 6059 } 6060 6061 static int rtl8169_poll(struct napi_struct *napi, int budget) 6062 { 6063 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 6064 struct net_device *dev = tp->dev; 6065 int work_done; 6066 6067 work_done = rtl_rx(dev, tp, (u32) budget); 6068 6069 rtl_tx(dev, tp, budget); 6070 6071 if (work_done < budget) { 6072 napi_complete_done(napi, work_done); 6073 rtl_irq_enable(tp); 6074 } 6075 6076 return work_done; 6077 } 6078 6079 static void rtl8169_rx_missed(struct net_device *dev) 6080 { 6081 struct rtl8169_private *tp = netdev_priv(dev); 6082 6083 if (tp->mac_version > RTL_GIGA_MAC_VER_06) 6084 return; 6085 6086 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff; 6087 RTL_W32(tp, RxMissed, 0); 6088 } 6089 6090 static void r8169_phylink_handler(struct net_device *ndev) 6091 { 6092 struct rtl8169_private *tp = netdev_priv(ndev); 6093 6094 if (netif_carrier_ok(ndev)) { 6095 rtl_link_chg_patch(tp); 6096 pm_request_resume(&tp->pci_dev->dev); 6097 } else { 6098 pm_runtime_idle(&tp->pci_dev->dev); 6099 } 6100 6101 if (net_ratelimit()) 6102 phy_print_status(tp->phydev); 6103 } 6104 6105 static int r8169_phy_connect(struct rtl8169_private *tp) 6106 { 6107 struct phy_device *phydev = tp->phydev; 6108 phy_interface_t phy_mode; 6109 int ret; 6110 6111 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 6112 PHY_INTERFACE_MODE_MII; 6113 6114 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 6115 phy_mode); 6116 if (ret) 6117 return ret; 6118 6119 if (!tp->supports_gmii) 6120 phy_set_max_speed(phydev, SPEED_100); 6121 6122 phy_support_asym_pause(phydev); 6123 6124 phy_attached_info(phydev); 6125 6126 return 0; 6127 } 6128 6129 static void rtl8169_down(struct net_device *dev) 6130 { 6131 struct rtl8169_private *tp = netdev_priv(dev); 6132 6133 phy_stop(tp->phydev); 6134 6135 napi_disable(&tp->napi); 6136 netif_stop_queue(dev); 6137 6138 rtl8169_hw_reset(tp); 6139 /* 6140 * At this point device interrupts can not be enabled in any function, 6141 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) 6142 * and napi is disabled (rtl8169_poll). 6143 */ 6144 rtl8169_rx_missed(dev); 6145 6146 /* Give a racing hard_start_xmit a few cycles to complete. */ 6147 synchronize_rcu(); 6148 6149 rtl8169_tx_clear(tp); 6150 6151 rtl8169_rx_clear(tp); 6152 6153 rtl_pll_power_down(tp); 6154 } 6155 6156 static int rtl8169_close(struct net_device *dev) 6157 { 6158 struct rtl8169_private *tp = netdev_priv(dev); 6159 struct pci_dev *pdev = tp->pci_dev; 6160 6161 pm_runtime_get_sync(&pdev->dev); 6162 6163 /* Update counters before going down */ 6164 rtl8169_update_counters(tp); 6165 6166 rtl_lock_work(tp); 6167 /* Clear all task flags */ 6168 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6169 6170 rtl8169_down(dev); 6171 rtl_unlock_work(tp); 6172 6173 cancel_work_sync(&tp->wk.work); 6174 6175 phy_disconnect(tp->phydev); 6176 6177 pci_free_irq(pdev, 0, tp); 6178 6179 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6180 tp->RxPhyAddr); 6181 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6182 tp->TxPhyAddr); 6183 tp->TxDescArray = NULL; 6184 tp->RxDescArray = NULL; 6185 6186 pm_runtime_put_sync(&pdev->dev); 6187 6188 return 0; 6189 } 6190 6191 #ifdef CONFIG_NET_POLL_CONTROLLER 6192 static void rtl8169_netpoll(struct net_device *dev) 6193 { 6194 struct rtl8169_private *tp = netdev_priv(dev); 6195 6196 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 6197 } 6198 #endif 6199 6200 static int rtl_open(struct net_device *dev) 6201 { 6202 struct rtl8169_private *tp = netdev_priv(dev); 6203 struct pci_dev *pdev = tp->pci_dev; 6204 int retval = -ENOMEM; 6205 6206 pm_runtime_get_sync(&pdev->dev); 6207 6208 /* 6209 * Rx and Tx descriptors needs 256 bytes alignment. 6210 * dma_alloc_coherent provides more. 6211 */ 6212 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 6213 &tp->TxPhyAddr, GFP_KERNEL); 6214 if (!tp->TxDescArray) 6215 goto err_pm_runtime_put; 6216 6217 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 6218 &tp->RxPhyAddr, GFP_KERNEL); 6219 if (!tp->RxDescArray) 6220 goto err_free_tx_0; 6221 6222 retval = rtl8169_init_ring(tp); 6223 if (retval < 0) 6224 goto err_free_rx_1; 6225 6226 rtl_request_firmware(tp); 6227 6228 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 6229 dev->name); 6230 if (retval < 0) 6231 goto err_release_fw_2; 6232 6233 retval = r8169_phy_connect(tp); 6234 if (retval) 6235 goto err_free_irq; 6236 6237 rtl_lock_work(tp); 6238 6239 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6240 6241 napi_enable(&tp->napi); 6242 6243 rtl8169_init_phy(dev, tp); 6244 6245 rtl_pll_power_up(tp); 6246 6247 rtl_hw_start(tp); 6248 6249 if (!rtl8169_init_counter_offsets(tp)) 6250 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 6251 6252 phy_start(tp->phydev); 6253 netif_start_queue(dev); 6254 6255 rtl_unlock_work(tp); 6256 6257 pm_runtime_put_sync(&pdev->dev); 6258 out: 6259 return retval; 6260 6261 err_free_irq: 6262 pci_free_irq(pdev, 0, tp); 6263 err_release_fw_2: 6264 rtl_release_firmware(tp); 6265 rtl8169_rx_clear(tp); 6266 err_free_rx_1: 6267 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6268 tp->RxPhyAddr); 6269 tp->RxDescArray = NULL; 6270 err_free_tx_0: 6271 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6272 tp->TxPhyAddr); 6273 tp->TxDescArray = NULL; 6274 err_pm_runtime_put: 6275 pm_runtime_put_noidle(&pdev->dev); 6276 goto out; 6277 } 6278 6279 static void 6280 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6281 { 6282 struct rtl8169_private *tp = netdev_priv(dev); 6283 struct pci_dev *pdev = tp->pci_dev; 6284 struct rtl8169_counters *counters = tp->counters; 6285 unsigned int start; 6286 6287 pm_runtime_get_noresume(&pdev->dev); 6288 6289 if (netif_running(dev) && pm_runtime_active(&pdev->dev)) 6290 rtl8169_rx_missed(dev); 6291 6292 do { 6293 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 6294 stats->rx_packets = tp->rx_stats.packets; 6295 stats->rx_bytes = tp->rx_stats.bytes; 6296 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 6297 6298 do { 6299 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 6300 stats->tx_packets = tp->tx_stats.packets; 6301 stats->tx_bytes = tp->tx_stats.bytes; 6302 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 6303 6304 stats->rx_dropped = dev->stats.rx_dropped; 6305 stats->tx_dropped = dev->stats.tx_dropped; 6306 stats->rx_length_errors = dev->stats.rx_length_errors; 6307 stats->rx_errors = dev->stats.rx_errors; 6308 stats->rx_crc_errors = dev->stats.rx_crc_errors; 6309 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 6310 stats->rx_missed_errors = dev->stats.rx_missed_errors; 6311 stats->multicast = dev->stats.multicast; 6312 6313 /* 6314 * Fetch additional counter values missing in stats collected by driver 6315 * from tally counters. 6316 */ 6317 if (pm_runtime_active(&pdev->dev)) 6318 rtl8169_update_counters(tp); 6319 6320 /* 6321 * Subtract values fetched during initalization. 6322 * See rtl8169_init_counter_offsets for a description why we do that. 6323 */ 6324 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 6325 le64_to_cpu(tp->tc_offset.tx_errors); 6326 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 6327 le32_to_cpu(tp->tc_offset.tx_multi_collision); 6328 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 6329 le16_to_cpu(tp->tc_offset.tx_aborted); 6330 6331 pm_runtime_put_noidle(&pdev->dev); 6332 } 6333 6334 static void rtl8169_net_suspend(struct net_device *dev) 6335 { 6336 struct rtl8169_private *tp = netdev_priv(dev); 6337 6338 if (!netif_running(dev)) 6339 return; 6340 6341 phy_stop(tp->phydev); 6342 netif_device_detach(dev); 6343 6344 rtl_lock_work(tp); 6345 napi_disable(&tp->napi); 6346 /* Clear all task flags */ 6347 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6348 6349 rtl_unlock_work(tp); 6350 6351 rtl_pll_power_down(tp); 6352 } 6353 6354 #ifdef CONFIG_PM 6355 6356 static int rtl8169_suspend(struct device *device) 6357 { 6358 struct net_device *dev = dev_get_drvdata(device); 6359 struct rtl8169_private *tp = netdev_priv(dev); 6360 6361 rtl8169_net_suspend(dev); 6362 clk_disable_unprepare(tp->clk); 6363 6364 return 0; 6365 } 6366 6367 static void __rtl8169_resume(struct net_device *dev) 6368 { 6369 struct rtl8169_private *tp = netdev_priv(dev); 6370 6371 netif_device_attach(dev); 6372 6373 rtl_pll_power_up(tp); 6374 rtl8169_init_phy(dev, tp); 6375 6376 phy_start(tp->phydev); 6377 6378 rtl_lock_work(tp); 6379 napi_enable(&tp->napi); 6380 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6381 rtl_reset_work(tp); 6382 rtl_unlock_work(tp); 6383 } 6384 6385 static int rtl8169_resume(struct device *device) 6386 { 6387 struct net_device *dev = dev_get_drvdata(device); 6388 struct rtl8169_private *tp = netdev_priv(dev); 6389 6390 rtl_rar_set(tp, dev->dev_addr); 6391 6392 clk_prepare_enable(tp->clk); 6393 6394 if (netif_running(dev)) 6395 __rtl8169_resume(dev); 6396 6397 return 0; 6398 } 6399 6400 static int rtl8169_runtime_suspend(struct device *device) 6401 { 6402 struct net_device *dev = dev_get_drvdata(device); 6403 struct rtl8169_private *tp = netdev_priv(dev); 6404 6405 if (!tp->TxDescArray) 6406 return 0; 6407 6408 rtl_lock_work(tp); 6409 __rtl8169_set_wol(tp, WAKE_ANY); 6410 rtl_unlock_work(tp); 6411 6412 rtl8169_net_suspend(dev); 6413 6414 /* Update counters before going runtime suspend */ 6415 rtl8169_rx_missed(dev); 6416 rtl8169_update_counters(tp); 6417 6418 return 0; 6419 } 6420 6421 static int rtl8169_runtime_resume(struct device *device) 6422 { 6423 struct net_device *dev = dev_get_drvdata(device); 6424 struct rtl8169_private *tp = netdev_priv(dev); 6425 6426 rtl_rar_set(tp, dev->dev_addr); 6427 6428 if (!tp->TxDescArray) 6429 return 0; 6430 6431 rtl_lock_work(tp); 6432 __rtl8169_set_wol(tp, tp->saved_wolopts); 6433 rtl_unlock_work(tp); 6434 6435 __rtl8169_resume(dev); 6436 6437 return 0; 6438 } 6439 6440 static int rtl8169_runtime_idle(struct device *device) 6441 { 6442 struct net_device *dev = dev_get_drvdata(device); 6443 6444 if (!netif_running(dev) || !netif_carrier_ok(dev)) 6445 pm_schedule_suspend(device, 10000); 6446 6447 return -EBUSY; 6448 } 6449 6450 static const struct dev_pm_ops rtl8169_pm_ops = { 6451 .suspend = rtl8169_suspend, 6452 .resume = rtl8169_resume, 6453 .freeze = rtl8169_suspend, 6454 .thaw = rtl8169_resume, 6455 .poweroff = rtl8169_suspend, 6456 .restore = rtl8169_resume, 6457 .runtime_suspend = rtl8169_runtime_suspend, 6458 .runtime_resume = rtl8169_runtime_resume, 6459 .runtime_idle = rtl8169_runtime_idle, 6460 }; 6461 6462 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 6463 6464 #else /* !CONFIG_PM */ 6465 6466 #define RTL8169_PM_OPS NULL 6467 6468 #endif /* !CONFIG_PM */ 6469 6470 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 6471 { 6472 /* WoL fails with 8168b when the receiver is disabled. */ 6473 switch (tp->mac_version) { 6474 case RTL_GIGA_MAC_VER_11: 6475 case RTL_GIGA_MAC_VER_12: 6476 case RTL_GIGA_MAC_VER_17: 6477 pci_clear_master(tp->pci_dev); 6478 6479 RTL_W8(tp, ChipCmd, CmdRxEnb); 6480 /* PCI commit */ 6481 RTL_R8(tp, ChipCmd); 6482 break; 6483 default: 6484 break; 6485 } 6486 } 6487 6488 static void rtl_shutdown(struct pci_dev *pdev) 6489 { 6490 struct net_device *dev = pci_get_drvdata(pdev); 6491 struct rtl8169_private *tp = netdev_priv(dev); 6492 6493 rtl8169_net_suspend(dev); 6494 6495 /* Restore original MAC address */ 6496 rtl_rar_set(tp, dev->perm_addr); 6497 6498 rtl8169_hw_reset(tp); 6499 6500 if (system_state == SYSTEM_POWER_OFF) { 6501 if (tp->saved_wolopts) { 6502 rtl_wol_suspend_quirk(tp); 6503 rtl_wol_shutdown_quirk(tp); 6504 } 6505 6506 pci_wake_from_d3(pdev, true); 6507 pci_set_power_state(pdev, PCI_D3hot); 6508 } 6509 } 6510 6511 static void rtl_remove_one(struct pci_dev *pdev) 6512 { 6513 struct net_device *dev = pci_get_drvdata(pdev); 6514 struct rtl8169_private *tp = netdev_priv(dev); 6515 6516 if (r8168_check_dash(tp)) 6517 rtl8168_driver_stop(tp); 6518 6519 netif_napi_del(&tp->napi); 6520 6521 unregister_netdev(dev); 6522 mdiobus_unregister(tp->phydev->mdio.bus); 6523 6524 rtl_release_firmware(tp); 6525 6526 if (pci_dev_run_wake(pdev)) 6527 pm_runtime_get_noresume(&pdev->dev); 6528 6529 /* restore original MAC address */ 6530 rtl_rar_set(tp, dev->perm_addr); 6531 } 6532 6533 static const struct net_device_ops rtl_netdev_ops = { 6534 .ndo_open = rtl_open, 6535 .ndo_stop = rtl8169_close, 6536 .ndo_get_stats64 = rtl8169_get_stats64, 6537 .ndo_start_xmit = rtl8169_start_xmit, 6538 .ndo_features_check = rtl8169_features_check, 6539 .ndo_tx_timeout = rtl8169_tx_timeout, 6540 .ndo_validate_addr = eth_validate_addr, 6541 .ndo_change_mtu = rtl8169_change_mtu, 6542 .ndo_fix_features = rtl8169_fix_features, 6543 .ndo_set_features = rtl8169_set_features, 6544 .ndo_set_mac_address = rtl_set_mac_address, 6545 .ndo_do_ioctl = rtl8169_ioctl, 6546 .ndo_set_rx_mode = rtl_set_rx_mode, 6547 #ifdef CONFIG_NET_POLL_CONTROLLER 6548 .ndo_poll_controller = rtl8169_netpoll, 6549 #endif 6550 6551 }; 6552 6553 static void rtl_set_irq_mask(struct rtl8169_private *tp) 6554 { 6555 tp->irq_mask = RTL_EVENT_NAPI | LinkChg; 6556 6557 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 6558 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 6559 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 6560 /* special workaround needed */ 6561 tp->irq_mask |= RxFIFOOver; 6562 else 6563 tp->irq_mask |= RxOverflow; 6564 } 6565 6566 static int rtl_alloc_irq(struct rtl8169_private *tp) 6567 { 6568 unsigned int flags; 6569 6570 switch (tp->mac_version) { 6571 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6572 rtl_unlock_config_regs(tp); 6573 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 6574 rtl_lock_config_regs(tp); 6575 /* fall through */ 6576 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24: 6577 flags = PCI_IRQ_LEGACY; 6578 break; 6579 default: 6580 flags = PCI_IRQ_ALL_TYPES; 6581 break; 6582 } 6583 6584 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 6585 } 6586 6587 static void rtl_read_mac_address(struct rtl8169_private *tp, 6588 u8 mac_addr[ETH_ALEN]) 6589 { 6590 /* Get MAC address */ 6591 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 6592 u32 value = rtl_eri_read(tp, 0xe0); 6593 6594 mac_addr[0] = (value >> 0) & 0xff; 6595 mac_addr[1] = (value >> 8) & 0xff; 6596 mac_addr[2] = (value >> 16) & 0xff; 6597 mac_addr[3] = (value >> 24) & 0xff; 6598 6599 value = rtl_eri_read(tp, 0xe4); 6600 mac_addr[4] = (value >> 0) & 0xff; 6601 mac_addr[5] = (value >> 8) & 0xff; 6602 } else if (rtl_is_8125(tp)) { 6603 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 6604 } 6605 } 6606 6607 DECLARE_RTL_COND(rtl_link_list_ready_cond) 6608 { 6609 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 6610 } 6611 6612 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 6613 { 6614 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 6615 } 6616 6617 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 6618 { 6619 struct rtl8169_private *tp = mii_bus->priv; 6620 6621 if (phyaddr > 0) 6622 return -ENODEV; 6623 6624 return rtl_readphy(tp, phyreg); 6625 } 6626 6627 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 6628 int phyreg, u16 val) 6629 { 6630 struct rtl8169_private *tp = mii_bus->priv; 6631 6632 if (phyaddr > 0) 6633 return -ENODEV; 6634 6635 rtl_writephy(tp, phyreg, val); 6636 6637 return 0; 6638 } 6639 6640 static int r8169_mdio_register(struct rtl8169_private *tp) 6641 { 6642 struct pci_dev *pdev = tp->pci_dev; 6643 struct mii_bus *new_bus; 6644 int ret; 6645 6646 new_bus = devm_mdiobus_alloc(&pdev->dev); 6647 if (!new_bus) 6648 return -ENOMEM; 6649 6650 new_bus->name = "r8169"; 6651 new_bus->priv = tp; 6652 new_bus->parent = &pdev->dev; 6653 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 6654 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 6655 6656 new_bus->read = r8169_mdio_read_reg; 6657 new_bus->write = r8169_mdio_write_reg; 6658 6659 ret = mdiobus_register(new_bus); 6660 if (ret) 6661 return ret; 6662 6663 tp->phydev = mdiobus_get_phy(new_bus, 0); 6664 if (!tp->phydev) { 6665 mdiobus_unregister(new_bus); 6666 return -ENODEV; 6667 } 6668 6669 /* PHY will be woken up in rtl_open() */ 6670 phy_suspend(tp->phydev); 6671 6672 return 0; 6673 } 6674 6675 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 6676 { 6677 tp->ocp_base = OCP_STD_PHY_BASE; 6678 6679 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6680 6681 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 6682 return; 6683 6684 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6685 return; 6686 6687 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6688 msleep(1); 6689 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6690 6691 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6692 6693 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6694 return; 6695 6696 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 6697 6698 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6699 } 6700 6701 static void rtl_hw_init_8125(struct rtl8169_private *tp) 6702 { 6703 tp->ocp_base = OCP_STD_PHY_BASE; 6704 6705 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6706 6707 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6708 return; 6709 6710 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6711 msleep(1); 6712 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6713 6714 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6715 6716 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6717 return; 6718 6719 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 6720 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 6721 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 6722 6723 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6724 } 6725 6726 static void rtl_hw_initialize(struct rtl8169_private *tp) 6727 { 6728 switch (tp->mac_version) { 6729 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 6730 rtl8168ep_stop_cmac(tp); 6731 /* fall through */ 6732 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 6733 rtl_hw_init_8168g(tp); 6734 break; 6735 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 6736 rtl_hw_init_8125(tp); 6737 break; 6738 default: 6739 break; 6740 } 6741 } 6742 6743 static int rtl_jumbo_max(struct rtl8169_private *tp) 6744 { 6745 /* Non-GBit versions don't support jumbo frames */ 6746 if (!tp->supports_gmii) 6747 return JUMBO_1K; 6748 6749 switch (tp->mac_version) { 6750 /* RTL8169 */ 6751 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6752 return JUMBO_7K; 6753 /* RTL8168b */ 6754 case RTL_GIGA_MAC_VER_11: 6755 case RTL_GIGA_MAC_VER_12: 6756 case RTL_GIGA_MAC_VER_17: 6757 return JUMBO_4K; 6758 /* RTL8168c */ 6759 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 6760 return JUMBO_6K; 6761 default: 6762 return JUMBO_9K; 6763 } 6764 } 6765 6766 static void rtl_disable_clk(void *data) 6767 { 6768 clk_disable_unprepare(data); 6769 } 6770 6771 static int rtl_get_ether_clk(struct rtl8169_private *tp) 6772 { 6773 struct device *d = tp_to_dev(tp); 6774 struct clk *clk; 6775 int rc; 6776 6777 clk = devm_clk_get(d, "ether_clk"); 6778 if (IS_ERR(clk)) { 6779 rc = PTR_ERR(clk); 6780 if (rc == -ENOENT) 6781 /* clk-core allows NULL (for suspend / resume) */ 6782 rc = 0; 6783 else if (rc != -EPROBE_DEFER) 6784 dev_err(d, "failed to get clk: %d\n", rc); 6785 } else { 6786 tp->clk = clk; 6787 rc = clk_prepare_enable(clk); 6788 if (rc) 6789 dev_err(d, "failed to enable clk: %d\n", rc); 6790 else 6791 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 6792 } 6793 6794 return rc; 6795 } 6796 6797 static void rtl_init_mac_address(struct rtl8169_private *tp) 6798 { 6799 struct net_device *dev = tp->dev; 6800 u8 *mac_addr = dev->dev_addr; 6801 int rc; 6802 6803 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 6804 if (!rc) 6805 goto done; 6806 6807 rtl_read_mac_address(tp, mac_addr); 6808 if (is_valid_ether_addr(mac_addr)) 6809 goto done; 6810 6811 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 6812 if (is_valid_ether_addr(mac_addr)) 6813 goto done; 6814 6815 eth_hw_addr_random(dev); 6816 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 6817 done: 6818 rtl_rar_set(tp, mac_addr); 6819 } 6820 6821 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 6822 { 6823 struct rtl8169_private *tp; 6824 struct net_device *dev; 6825 int chipset, region; 6826 int jumbo_max, rc; 6827 6828 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 6829 if (!dev) 6830 return -ENOMEM; 6831 6832 SET_NETDEV_DEV(dev, &pdev->dev); 6833 dev->netdev_ops = &rtl_netdev_ops; 6834 tp = netdev_priv(dev); 6835 tp->dev = dev; 6836 tp->pci_dev = pdev; 6837 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 6838 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 6839 tp->eee_adv = -1; 6840 6841 /* Get the *optional* external "ether_clk" used on some boards */ 6842 rc = rtl_get_ether_clk(tp); 6843 if (rc) 6844 return rc; 6845 6846 /* Disable ASPM completely as that cause random device stop working 6847 * problems as well as full system hangs for some PCIe devices users. 6848 */ 6849 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 6850 PCIE_LINK_STATE_L1); 6851 tp->aspm_manageable = !rc; 6852 6853 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 6854 rc = pcim_enable_device(pdev); 6855 if (rc < 0) { 6856 dev_err(&pdev->dev, "enable failure\n"); 6857 return rc; 6858 } 6859 6860 if (pcim_set_mwi(pdev) < 0) 6861 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 6862 6863 /* use first MMIO region */ 6864 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 6865 if (region < 0) { 6866 dev_err(&pdev->dev, "no MMIO resource found\n"); 6867 return -ENODEV; 6868 } 6869 6870 /* check for weird/broken PCI region reporting */ 6871 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 6872 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 6873 return -ENODEV; 6874 } 6875 6876 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 6877 if (rc < 0) { 6878 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 6879 return rc; 6880 } 6881 6882 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 6883 6884 /* Identify chip attached to board */ 6885 rtl8169_get_mac_version(tp); 6886 if (tp->mac_version == RTL_GIGA_MAC_NONE) 6887 return -ENODEV; 6888 6889 tp->cp_cmd = RTL_R16(tp, CPlusCmd); 6890 6891 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 6892 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 6893 dev->features |= NETIF_F_HIGHDMA; 6894 6895 rtl_init_rxcfg(tp); 6896 6897 rtl8169_irq_mask_and_ack(tp); 6898 6899 rtl_hw_initialize(tp); 6900 6901 rtl_hw_reset(tp); 6902 6903 pci_set_master(pdev); 6904 6905 chipset = tp->mac_version; 6906 6907 rc = rtl_alloc_irq(tp); 6908 if (rc < 0) { 6909 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 6910 return rc; 6911 } 6912 6913 mutex_init(&tp->wk.mutex); 6914 INIT_WORK(&tp->wk.work, rtl_task); 6915 u64_stats_init(&tp->rx_stats.syncp); 6916 u64_stats_init(&tp->tx_stats.syncp); 6917 6918 rtl_init_mac_address(tp); 6919 6920 dev->ethtool_ops = &rtl8169_ethtool_ops; 6921 6922 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 6923 6924 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 6925 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 6926 NETIF_F_HW_VLAN_CTAG_RX; 6927 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 6928 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 6929 NETIF_F_HW_VLAN_CTAG_RX; 6930 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 6931 NETIF_F_HIGHDMA; 6932 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 6933 6934 tp->cp_cmd |= RxChkSum; 6935 /* RTL8125 uses register RxConfig for VLAN offloading config */ 6936 if (!rtl_is_8125(tp)) 6937 tp->cp_cmd |= RxVlan; 6938 /* 6939 * Pretend we are using VLANs; This bypasses a nasty bug where 6940 * Interrupts stop flowing on high load on 8110SCd controllers. 6941 */ 6942 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 6943 /* Disallow toggling */ 6944 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 6945 6946 if (rtl_chip_supports_csum_v2(tp)) { 6947 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 6948 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 6949 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 6950 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 6951 } else { 6952 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 6953 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 6954 } 6955 6956 /* RTL8168e-vl and one RTL8168c variant are known to have a 6957 * HW issue with TSO. 6958 */ 6959 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 6960 tp->mac_version == RTL_GIGA_MAC_VER_22) { 6961 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 6962 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 6963 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 6964 } 6965 6966 dev->hw_features |= NETIF_F_RXALL; 6967 dev->hw_features |= NETIF_F_RXFCS; 6968 6969 /* MTU range: 60 - hw-specific max */ 6970 dev->min_mtu = ETH_ZLEN; 6971 jumbo_max = rtl_jumbo_max(tp); 6972 dev->max_mtu = jumbo_max; 6973 6974 rtl_set_irq_mask(tp); 6975 6976 tp->fw_name = rtl_chip_infos[chipset].fw_name; 6977 6978 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 6979 &tp->counters_phys_addr, 6980 GFP_KERNEL); 6981 if (!tp->counters) 6982 return -ENOMEM; 6983 6984 pci_set_drvdata(pdev, dev); 6985 6986 rc = r8169_mdio_register(tp); 6987 if (rc) 6988 return rc; 6989 6990 /* chip gets powered up in rtl_open() */ 6991 rtl_pll_power_down(tp); 6992 6993 rc = register_netdev(dev); 6994 if (rc) 6995 goto err_mdio_unregister; 6996 6997 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 6998 rtl_chip_infos[chipset].name, dev->dev_addr, 6999 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf, 7000 pci_irq_vector(pdev, 0)); 7001 7002 if (jumbo_max > JUMBO_1K) 7003 netif_info(tp, probe, dev, 7004 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 7005 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 7006 "ok" : "ko"); 7007 7008 if (r8168_check_dash(tp)) 7009 rtl8168_driver_start(tp); 7010 7011 if (pci_dev_run_wake(pdev)) 7012 pm_runtime_put_sync(&pdev->dev); 7013 7014 return 0; 7015 7016 err_mdio_unregister: 7017 mdiobus_unregister(tp->phydev->mdio.bus); 7018 return rc; 7019 } 7020 7021 static struct pci_driver rtl8169_pci_driver = { 7022 .name = MODULENAME, 7023 .id_table = rtl8169_pci_tbl, 7024 .probe = rtl_init_one, 7025 .remove = rtl_remove_one, 7026 .shutdown = rtl_shutdown, 7027 .driver.pm = RTL8169_PM_OPS, 7028 }; 7029 7030 module_pci_driver(rtl8169_pci_driver); 7031