1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define MODULENAME "r8169" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 56 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 59 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 60 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define OCP_STD_PHY_BASE 0xa400 77 78 #define RTL_CFG_NO_GBIT 1 79 80 /* write/read MMIO register */ 81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 87 88 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 92 93 static const struct { 94 const char *name; 95 const char *fw_name; 96 } rtl_chip_infos[] = { 97 /* PCI devices. */ 98 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 99 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 100 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 101 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 102 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 103 /* PCI-E devices. */ 104 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 106 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 107 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 108 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 111 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 112 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 113 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 114 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 115 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 119 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 121 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 122 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 123 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 125 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 127 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 128 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 129 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 130 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 131 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 132 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 133 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 134 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 135 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 136 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 137 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 138 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 139 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 140 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 141 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 142 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 143 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 144 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 145 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 148 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 149 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 150 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 151 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 152 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 153 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 154 }; 155 156 static const struct pci_device_id rtl8169_pci_tbl[] = { 157 { PCI_VDEVICE(REALTEK, 0x2502) }, 158 { PCI_VDEVICE(REALTEK, 0x2600) }, 159 { PCI_VDEVICE(REALTEK, 0x8129) }, 160 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 161 { PCI_VDEVICE(REALTEK, 0x8161) }, 162 { PCI_VDEVICE(REALTEK, 0x8167) }, 163 { PCI_VDEVICE(REALTEK, 0x8168) }, 164 { PCI_VDEVICE(NCUBE, 0x8168) }, 165 { PCI_VDEVICE(REALTEK, 0x8169) }, 166 { PCI_VENDOR_ID_DLINK, 0x4300, 167 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 168 { PCI_VDEVICE(DLINK, 0x4300) }, 169 { PCI_VDEVICE(DLINK, 0x4302) }, 170 { PCI_VDEVICE(AT, 0xc107) }, 171 { PCI_VDEVICE(USR, 0x0116) }, 172 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 173 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 174 { PCI_VDEVICE(REALTEK, 0x8125) }, 175 { PCI_VDEVICE(REALTEK, 0x3000) }, 176 {} 177 }; 178 179 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 180 181 enum rtl_registers { 182 MAC0 = 0, /* Ethernet hardware address. */ 183 MAC4 = 4, 184 MAR0 = 8, /* Multicast filter. */ 185 CounterAddrLow = 0x10, 186 CounterAddrHigh = 0x14, 187 TxDescStartAddrLow = 0x20, 188 TxDescStartAddrHigh = 0x24, 189 TxHDescStartAddrLow = 0x28, 190 TxHDescStartAddrHigh = 0x2c, 191 FLASH = 0x30, 192 ERSR = 0x36, 193 ChipCmd = 0x37, 194 TxPoll = 0x38, 195 IntrMask = 0x3c, 196 IntrStatus = 0x3e, 197 198 TxConfig = 0x40, 199 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 200 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 201 202 RxConfig = 0x44, 203 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 204 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 205 #define RXCFG_FIFO_SHIFT 13 206 /* No threshold before first PCI xfer */ 207 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 208 #define RX_EARLY_OFF (1 << 11) 209 #define RXCFG_DMA_SHIFT 8 210 /* Unlimited maximum PCI burst. */ 211 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 212 213 Cfg9346 = 0x50, 214 Config0 = 0x51, 215 Config1 = 0x52, 216 Config2 = 0x53, 217 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 218 219 Config3 = 0x54, 220 Config4 = 0x55, 221 Config5 = 0x56, 222 PHYAR = 0x60, 223 PHYstatus = 0x6c, 224 RxMaxSize = 0xda, 225 CPlusCmd = 0xe0, 226 IntrMitigate = 0xe2, 227 228 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 229 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 230 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 231 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 232 233 #define RTL_COALESCE_T_MAX 0x0fU 234 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 235 236 RxDescAddrLow = 0xe4, 237 RxDescAddrHigh = 0xe8, 238 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 239 240 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 241 242 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 243 244 #define TxPacketMax (8064 >> 7) 245 #define EarlySize 0x27 246 247 FuncEvent = 0xf0, 248 FuncEventMask = 0xf4, 249 FuncPresetState = 0xf8, 250 IBCR0 = 0xf8, 251 IBCR2 = 0xf9, 252 IBIMR0 = 0xfa, 253 IBISR0 = 0xfb, 254 FuncForceEvent = 0xfc, 255 }; 256 257 enum rtl8168_8101_registers { 258 CSIDR = 0x64, 259 CSIAR = 0x68, 260 #define CSIAR_FLAG 0x80000000 261 #define CSIAR_WRITE_CMD 0x80000000 262 #define CSIAR_BYTE_ENABLE 0x0000f000 263 #define CSIAR_ADDR_MASK 0x00000fff 264 PMCH = 0x6f, 265 #define D3COLD_NO_PLL_DOWN BIT(7) 266 #define D3HOT_NO_PLL_DOWN BIT(6) 267 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 268 EPHYAR = 0x80, 269 #define EPHYAR_FLAG 0x80000000 270 #define EPHYAR_WRITE_CMD 0x80000000 271 #define EPHYAR_REG_MASK 0x1f 272 #define EPHYAR_REG_SHIFT 16 273 #define EPHYAR_DATA_MASK 0xffff 274 DLLPR = 0xd0, 275 #define PFM_EN (1 << 6) 276 #define TX_10M_PS_EN (1 << 7) 277 DBG_REG = 0xd1, 278 #define FIX_NAK_1 (1 << 4) 279 #define FIX_NAK_2 (1 << 3) 280 TWSI = 0xd2, 281 MCU = 0xd3, 282 #define NOW_IS_OOB (1 << 7) 283 #define TX_EMPTY (1 << 5) 284 #define RX_EMPTY (1 << 4) 285 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 286 #define EN_NDP (1 << 3) 287 #define EN_OOB_RESET (1 << 2) 288 #define LINK_LIST_RDY (1 << 1) 289 EFUSEAR = 0xdc, 290 #define EFUSEAR_FLAG 0x80000000 291 #define EFUSEAR_WRITE_CMD 0x80000000 292 #define EFUSEAR_READ_CMD 0x00000000 293 #define EFUSEAR_REG_MASK 0x03ff 294 #define EFUSEAR_REG_SHIFT 8 295 #define EFUSEAR_DATA_MASK 0xff 296 MISC_1 = 0xf2, 297 #define PFM_D3COLD_EN (1 << 6) 298 }; 299 300 enum rtl8168_registers { 301 LED_FREQ = 0x1a, 302 EEE_LED = 0x1b, 303 ERIDR = 0x70, 304 ERIAR = 0x74, 305 #define ERIAR_FLAG 0x80000000 306 #define ERIAR_WRITE_CMD 0x80000000 307 #define ERIAR_READ_CMD 0x00000000 308 #define ERIAR_ADDR_BYTE_ALIGN 4 309 #define ERIAR_TYPE_SHIFT 16 310 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 312 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 313 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 314 #define ERIAR_MASK_SHIFT 12 315 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 317 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 318 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 319 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 320 EPHY_RXER_NUM = 0x7c, 321 OCPDR = 0xb0, /* OCP GPHY access */ 322 #define OCPDR_WRITE_CMD 0x80000000 323 #define OCPDR_READ_CMD 0x00000000 324 #define OCPDR_REG_MASK 0x7f 325 #define OCPDR_GPHY_REG_SHIFT 16 326 #define OCPDR_DATA_MASK 0xffff 327 OCPAR = 0xb4, 328 #define OCPAR_FLAG 0x80000000 329 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 330 #define OCPAR_GPHY_READ_CMD 0x0000f060 331 GPHY_OCP = 0xb8, 332 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 333 MISC = 0xf0, /* 8168e only. */ 334 #define TXPLA_RST (1 << 29) 335 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 336 #define PWM_EN (1 << 22) 337 #define RXDV_GATED_EN (1 << 19) 338 #define EARLY_TALLY_EN (1 << 16) 339 }; 340 341 enum rtl8125_registers { 342 IntrMask_8125 = 0x38, 343 IntrStatus_8125 = 0x3c, 344 TxPoll_8125 = 0x90, 345 MAC0_BKP = 0x19e0, 346 EEE_TXIDLE_TIMER_8125 = 0x6048, 347 }; 348 349 #define RX_VLAN_INNER_8125 BIT(22) 350 #define RX_VLAN_OUTER_8125 BIT(23) 351 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 352 353 #define RX_FETCH_DFLT_8125 (8 << 27) 354 355 enum rtl_register_content { 356 /* InterruptStatusBits */ 357 SYSErr = 0x8000, 358 PCSTimeout = 0x4000, 359 SWInt = 0x0100, 360 TxDescUnavail = 0x0080, 361 RxFIFOOver = 0x0040, 362 LinkChg = 0x0020, 363 RxOverflow = 0x0010, 364 TxErr = 0x0008, 365 TxOK = 0x0004, 366 RxErr = 0x0002, 367 RxOK = 0x0001, 368 369 /* RxStatusDesc */ 370 RxRWT = (1 << 22), 371 RxRES = (1 << 21), 372 RxRUNT = (1 << 20), 373 RxCRC = (1 << 19), 374 375 /* ChipCmdBits */ 376 StopReq = 0x80, 377 CmdReset = 0x10, 378 CmdRxEnb = 0x08, 379 CmdTxEnb = 0x04, 380 RxBufEmpty = 0x01, 381 382 /* TXPoll register p.5 */ 383 HPQ = 0x80, /* Poll cmd on the high prio queue */ 384 NPQ = 0x40, /* Poll cmd on the low prio queue */ 385 FSWInt = 0x01, /* Forced software interrupt */ 386 387 /* Cfg9346Bits */ 388 Cfg9346_Lock = 0x00, 389 Cfg9346_Unlock = 0xc0, 390 391 /* rx_mode_bits */ 392 AcceptErr = 0x20, 393 AcceptRunt = 0x10, 394 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 395 AcceptBroadcast = 0x08, 396 AcceptMulticast = 0x04, 397 AcceptMyPhys = 0x02, 398 AcceptAllPhys = 0x01, 399 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 400 #define RX_CONFIG_ACCEPT_MASK 0x3f 401 402 /* TxConfigBits */ 403 TxInterFrameGapShift = 24, 404 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 405 406 /* Config1 register p.24 */ 407 LEDS1 = (1 << 7), 408 LEDS0 = (1 << 6), 409 Speed_down = (1 << 4), 410 MEMMAP = (1 << 3), 411 IOMAP = (1 << 2), 412 VPD = (1 << 1), 413 PMEnable = (1 << 0), /* Power Management Enable */ 414 415 /* Config2 register p. 25 */ 416 ClkReqEn = (1 << 7), /* Clock Request Enable */ 417 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 418 PCI_Clock_66MHz = 0x01, 419 PCI_Clock_33MHz = 0x00, 420 421 /* Config3 register p.25 */ 422 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 423 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 424 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 425 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 426 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 427 428 /* Config4 register */ 429 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 430 431 /* Config5 register p.27 */ 432 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 433 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 434 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 435 Spi_en = (1 << 3), 436 LanWake = (1 << 1), /* LanWake enable/disable */ 437 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 438 ASPM_en = (1 << 0), /* ASPM enable */ 439 440 /* CPlusCmd p.31 */ 441 EnableBist = (1 << 15), // 8168 8101 442 Mac_dbgo_oe = (1 << 14), // 8168 8101 443 EnAnaPLL = (1 << 14), // 8169 444 Normal_mode = (1 << 13), // unused 445 Force_half_dup = (1 << 12), // 8168 8101 446 Force_rxflow_en = (1 << 11), // 8168 8101 447 Force_txflow_en = (1 << 10), // 8168 8101 448 Cxpl_dbg_sel = (1 << 9), // 8168 8101 449 ASF = (1 << 8), // 8168 8101 450 PktCntrDisable = (1 << 7), // 8168 8101 451 Mac_dbgo_sel = 0x001c, // 8168 452 RxVlan = (1 << 6), 453 RxChkSum = (1 << 5), 454 PCIDAC = (1 << 4), 455 PCIMulRW = (1 << 3), 456 #define INTT_MASK GENMASK(1, 0) 457 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 458 459 /* rtl8169_PHYstatus */ 460 TBI_Enable = 0x80, 461 TxFlowCtrl = 0x40, 462 RxFlowCtrl = 0x20, 463 _1000bpsF = 0x10, 464 _100bps = 0x08, 465 _10bps = 0x04, 466 LinkStatus = 0x02, 467 FullDup = 0x01, 468 469 /* ResetCounterCommand */ 470 CounterReset = 0x1, 471 472 /* DumpCounterCommand */ 473 CounterDump = 0x8, 474 475 /* magic enable v2 */ 476 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 477 }; 478 479 enum rtl_desc_bit { 480 /* First doubleword. */ 481 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 482 RingEnd = (1 << 30), /* End of descriptor ring */ 483 FirstFrag = (1 << 29), /* First segment of a packet */ 484 LastFrag = (1 << 28), /* Final segment of a packet */ 485 }; 486 487 /* Generic case. */ 488 enum rtl_tx_desc_bit { 489 /* First doubleword. */ 490 TD_LSO = (1 << 27), /* Large Send Offload */ 491 #define TD_MSS_MAX 0x07ffu /* MSS value */ 492 493 /* Second doubleword. */ 494 TxVlanTag = (1 << 17), /* Add VLAN tag */ 495 }; 496 497 /* 8169, 8168b and 810x except 8102e. */ 498 enum rtl_tx_desc_bit_0 { 499 /* First doubleword. */ 500 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 501 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 502 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 503 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 504 }; 505 506 /* 8102e, 8168c and beyond. */ 507 enum rtl_tx_desc_bit_1 { 508 /* First doubleword. */ 509 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 510 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 511 #define GTTCPHO_SHIFT 18 512 #define GTTCPHO_MAX 0x7f 513 514 /* Second doubleword. */ 515 #define TCPHO_SHIFT 18 516 #define TCPHO_MAX 0x3ff 517 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 518 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 519 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 520 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 521 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 522 }; 523 524 enum rtl_rx_desc_bit { 525 /* Rx private */ 526 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 527 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 528 529 #define RxProtoUDP (PID1) 530 #define RxProtoTCP (PID0) 531 #define RxProtoIP (PID1 | PID0) 532 #define RxProtoMask RxProtoIP 533 534 IPFail = (1 << 16), /* IP checksum failed */ 535 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 536 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 537 538 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 539 540 RxVlanTag = (1 << 16), /* VLAN tag available */ 541 }; 542 543 #define RTL_GSO_MAX_SIZE_V1 32000 544 #define RTL_GSO_MAX_SEGS_V1 24 545 #define RTL_GSO_MAX_SIZE_V2 64000 546 #define RTL_GSO_MAX_SEGS_V2 64 547 548 struct TxDesc { 549 __le32 opts1; 550 __le32 opts2; 551 __le64 addr; 552 }; 553 554 struct RxDesc { 555 __le32 opts1; 556 __le32 opts2; 557 __le64 addr; 558 }; 559 560 struct ring_info { 561 struct sk_buff *skb; 562 u32 len; 563 }; 564 565 struct rtl8169_counters { 566 __le64 tx_packets; 567 __le64 rx_packets; 568 __le64 tx_errors; 569 __le32 rx_errors; 570 __le16 rx_missed; 571 __le16 align_errors; 572 __le32 tx_one_collision; 573 __le32 tx_multi_collision; 574 __le64 rx_unicast; 575 __le64 rx_broadcast; 576 __le32 rx_multicast; 577 __le16 tx_aborted; 578 __le16 tx_underun; 579 }; 580 581 struct rtl8169_tc_offsets { 582 bool inited; 583 __le64 tx_errors; 584 __le32 tx_multi_collision; 585 __le16 tx_aborted; 586 __le16 rx_missed; 587 }; 588 589 enum rtl_flag { 590 RTL_FLAG_TASK_ENABLED = 0, 591 RTL_FLAG_TASK_RESET_PENDING, 592 RTL_FLAG_MAX 593 }; 594 595 enum rtl_dash_type { 596 RTL_DASH_NONE, 597 RTL_DASH_DP, 598 RTL_DASH_EP, 599 }; 600 601 struct rtl8169_private { 602 void __iomem *mmio_addr; /* memory map physical address */ 603 struct pci_dev *pci_dev; 604 struct net_device *dev; 605 struct phy_device *phydev; 606 struct napi_struct napi; 607 enum mac_version mac_version; 608 enum rtl_dash_type dash_type; 609 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 610 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 611 u32 dirty_tx; 612 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 613 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 614 dma_addr_t TxPhyAddr; 615 dma_addr_t RxPhyAddr; 616 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 617 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 618 u16 cp_cmd; 619 u32 irq_mask; 620 struct clk *clk; 621 622 struct { 623 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 624 struct work_struct work; 625 } wk; 626 627 unsigned supports_gmii:1; 628 unsigned aspm_manageable:1; 629 dma_addr_t counters_phys_addr; 630 struct rtl8169_counters *counters; 631 struct rtl8169_tc_offsets tc_offset; 632 u32 saved_wolopts; 633 int eee_adv; 634 635 const char *fw_name; 636 struct rtl_fw *rtl_fw; 637 638 u32 ocp_base; 639 }; 640 641 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 642 643 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 644 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 645 MODULE_SOFTDEP("pre: realtek"); 646 MODULE_LICENSE("GPL"); 647 MODULE_FIRMWARE(FIRMWARE_8168D_1); 648 MODULE_FIRMWARE(FIRMWARE_8168D_2); 649 MODULE_FIRMWARE(FIRMWARE_8168E_1); 650 MODULE_FIRMWARE(FIRMWARE_8168E_2); 651 MODULE_FIRMWARE(FIRMWARE_8168E_3); 652 MODULE_FIRMWARE(FIRMWARE_8105E_1); 653 MODULE_FIRMWARE(FIRMWARE_8168F_1); 654 MODULE_FIRMWARE(FIRMWARE_8168F_2); 655 MODULE_FIRMWARE(FIRMWARE_8402_1); 656 MODULE_FIRMWARE(FIRMWARE_8411_1); 657 MODULE_FIRMWARE(FIRMWARE_8411_2); 658 MODULE_FIRMWARE(FIRMWARE_8106E_1); 659 MODULE_FIRMWARE(FIRMWARE_8106E_2); 660 MODULE_FIRMWARE(FIRMWARE_8168G_2); 661 MODULE_FIRMWARE(FIRMWARE_8168G_3); 662 MODULE_FIRMWARE(FIRMWARE_8168H_1); 663 MODULE_FIRMWARE(FIRMWARE_8168H_2); 664 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 665 MODULE_FIRMWARE(FIRMWARE_8107E_1); 666 MODULE_FIRMWARE(FIRMWARE_8107E_2); 667 MODULE_FIRMWARE(FIRMWARE_8125A_3); 668 MODULE_FIRMWARE(FIRMWARE_8125B_2); 669 670 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 671 { 672 return &tp->pci_dev->dev; 673 } 674 675 static void rtl_lock_config_regs(struct rtl8169_private *tp) 676 { 677 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 678 } 679 680 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 681 { 682 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 683 } 684 685 static void rtl_pci_commit(struct rtl8169_private *tp) 686 { 687 /* Read an arbitrary register to commit a preceding PCI write */ 688 RTL_R8(tp, ChipCmd); 689 } 690 691 static bool rtl_is_8125(struct rtl8169_private *tp) 692 { 693 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 694 } 695 696 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 697 { 698 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 699 tp->mac_version != RTL_GIGA_MAC_VER_39 && 700 tp->mac_version <= RTL_GIGA_MAC_VER_53; 701 } 702 703 static bool rtl_supports_eee(struct rtl8169_private *tp) 704 { 705 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 706 tp->mac_version != RTL_GIGA_MAC_VER_37 && 707 tp->mac_version != RTL_GIGA_MAC_VER_39; 708 } 709 710 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 711 { 712 int i; 713 714 for (i = 0; i < ETH_ALEN; i++) 715 mac[i] = RTL_R8(tp, reg + i); 716 } 717 718 struct rtl_cond { 719 bool (*check)(struct rtl8169_private *); 720 const char *msg; 721 }; 722 723 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 724 unsigned long usecs, int n, bool high) 725 { 726 int i; 727 728 for (i = 0; i < n; i++) { 729 if (c->check(tp) == high) 730 return true; 731 fsleep(usecs); 732 } 733 734 if (net_ratelimit()) 735 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 736 c->msg, !high, n, usecs); 737 return false; 738 } 739 740 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 741 const struct rtl_cond *c, 742 unsigned long d, int n) 743 { 744 return rtl_loop_wait(tp, c, d, n, true); 745 } 746 747 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 748 const struct rtl_cond *c, 749 unsigned long d, int n) 750 { 751 return rtl_loop_wait(tp, c, d, n, false); 752 } 753 754 #define DECLARE_RTL_COND(name) \ 755 static bool name ## _check(struct rtl8169_private *); \ 756 \ 757 static const struct rtl_cond name = { \ 758 .check = name ## _check, \ 759 .msg = #name \ 760 }; \ 761 \ 762 static bool name ## _check(struct rtl8169_private *tp) 763 764 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 765 { 766 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 767 if (type == ERIAR_OOB && 768 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 769 tp->mac_version == RTL_GIGA_MAC_VER_53)) 770 *cmd |= 0x7f0 << 18; 771 } 772 773 DECLARE_RTL_COND(rtl_eriar_cond) 774 { 775 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 776 } 777 778 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 779 u32 val, int type) 780 { 781 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 782 783 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 784 return; 785 786 RTL_W32(tp, ERIDR, val); 787 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 788 RTL_W32(tp, ERIAR, cmd); 789 790 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 791 } 792 793 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 794 u32 val) 795 { 796 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 797 } 798 799 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 800 { 801 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 802 803 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 804 RTL_W32(tp, ERIAR, cmd); 805 806 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 807 RTL_R32(tp, ERIDR) : ~0; 808 } 809 810 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 811 { 812 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 813 } 814 815 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 816 { 817 u32 val = rtl_eri_read(tp, addr); 818 819 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 820 } 821 822 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 823 { 824 rtl_w0w1_eri(tp, addr, p, 0); 825 } 826 827 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 828 { 829 rtl_w0w1_eri(tp, addr, 0, m); 830 } 831 832 static bool rtl_ocp_reg_failure(u32 reg) 833 { 834 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 835 } 836 837 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 838 { 839 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 840 } 841 842 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 843 { 844 if (rtl_ocp_reg_failure(reg)) 845 return; 846 847 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 848 849 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 850 } 851 852 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 853 { 854 if (rtl_ocp_reg_failure(reg)) 855 return 0; 856 857 RTL_W32(tp, GPHY_OCP, reg << 15); 858 859 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 860 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 861 } 862 863 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 864 { 865 if (rtl_ocp_reg_failure(reg)) 866 return; 867 868 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 869 } 870 871 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 872 { 873 if (rtl_ocp_reg_failure(reg)) 874 return 0; 875 876 RTL_W32(tp, OCPDR, reg << 15); 877 878 return RTL_R32(tp, OCPDR); 879 } 880 881 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 882 u16 set) 883 { 884 u16 data = r8168_mac_ocp_read(tp, reg); 885 886 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 887 } 888 889 /* Work around a hw issue with RTL8168g PHY, the quirk disables 890 * PHY MCU interrupts before PHY power-down. 891 */ 892 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 893 { 894 switch (tp->mac_version) { 895 case RTL_GIGA_MAC_VER_40: 896 case RTL_GIGA_MAC_VER_41: 897 case RTL_GIGA_MAC_VER_49: 898 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 899 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 900 else 901 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 902 break; 903 default: 904 break; 905 } 906 }; 907 908 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 909 { 910 if (reg == 0x1f) { 911 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 912 return; 913 } 914 915 if (tp->ocp_base != OCP_STD_PHY_BASE) 916 reg -= 0x10; 917 918 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 919 rtl8168g_phy_suspend_quirk(tp, value); 920 921 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 922 } 923 924 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 925 { 926 if (reg == 0x1f) 927 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 928 929 if (tp->ocp_base != OCP_STD_PHY_BASE) 930 reg -= 0x10; 931 932 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 933 } 934 935 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 936 { 937 if (reg == 0x1f) { 938 tp->ocp_base = value << 4; 939 return; 940 } 941 942 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 943 } 944 945 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 946 { 947 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 948 } 949 950 DECLARE_RTL_COND(rtl_phyar_cond) 951 { 952 return RTL_R32(tp, PHYAR) & 0x80000000; 953 } 954 955 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 956 { 957 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 958 959 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 960 /* 961 * According to hardware specs a 20us delay is required after write 962 * complete indication, but before sending next command. 963 */ 964 udelay(20); 965 } 966 967 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 968 { 969 int value; 970 971 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 972 973 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 974 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 975 976 /* 977 * According to hardware specs a 20us delay is required after read 978 * complete indication, but before sending next command. 979 */ 980 udelay(20); 981 982 return value; 983 } 984 985 DECLARE_RTL_COND(rtl_ocpar_cond) 986 { 987 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 988 } 989 990 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 991 { 992 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 993 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 994 RTL_W32(tp, EPHY_RXER_NUM, 0); 995 996 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 997 } 998 999 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 1000 { 1001 r8168dp_1_mdio_access(tp, reg, 1002 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 1003 } 1004 1005 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 1006 { 1007 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 1008 1009 mdelay(1); 1010 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1011 RTL_W32(tp, EPHY_RXER_NUM, 0); 1012 1013 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1014 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1015 } 1016 1017 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1018 1019 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1020 { 1021 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1022 } 1023 1024 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1025 { 1026 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1027 } 1028 1029 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1030 { 1031 r8168dp_2_mdio_start(tp); 1032 1033 r8169_mdio_write(tp, reg, value); 1034 1035 r8168dp_2_mdio_stop(tp); 1036 } 1037 1038 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1039 { 1040 int value; 1041 1042 /* Work around issue with chip reporting wrong PHY ID */ 1043 if (reg == MII_PHYSID2) 1044 return 0xc912; 1045 1046 r8168dp_2_mdio_start(tp); 1047 1048 value = r8169_mdio_read(tp, reg); 1049 1050 r8168dp_2_mdio_stop(tp); 1051 1052 return value; 1053 } 1054 1055 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1056 { 1057 switch (tp->mac_version) { 1058 case RTL_GIGA_MAC_VER_27: 1059 r8168dp_1_mdio_write(tp, location, val); 1060 break; 1061 case RTL_GIGA_MAC_VER_28: 1062 case RTL_GIGA_MAC_VER_31: 1063 r8168dp_2_mdio_write(tp, location, val); 1064 break; 1065 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1066 r8168g_mdio_write(tp, location, val); 1067 break; 1068 default: 1069 r8169_mdio_write(tp, location, val); 1070 break; 1071 } 1072 } 1073 1074 static int rtl_readphy(struct rtl8169_private *tp, int location) 1075 { 1076 switch (tp->mac_version) { 1077 case RTL_GIGA_MAC_VER_27: 1078 return r8168dp_1_mdio_read(tp, location); 1079 case RTL_GIGA_MAC_VER_28: 1080 case RTL_GIGA_MAC_VER_31: 1081 return r8168dp_2_mdio_read(tp, location); 1082 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1083 return r8168g_mdio_read(tp, location); 1084 default: 1085 return r8169_mdio_read(tp, location); 1086 } 1087 } 1088 1089 DECLARE_RTL_COND(rtl_ephyar_cond) 1090 { 1091 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1092 } 1093 1094 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1095 { 1096 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1097 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1098 1099 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1100 1101 udelay(10); 1102 } 1103 1104 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1105 { 1106 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1107 1108 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1109 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1110 } 1111 1112 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1113 { 1114 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1115 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1116 RTL_R32(tp, OCPDR) : ~0; 1117 } 1118 1119 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1120 { 1121 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1122 } 1123 1124 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1125 u32 data) 1126 { 1127 RTL_W32(tp, OCPDR, data); 1128 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1129 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1130 } 1131 1132 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1133 u32 data) 1134 { 1135 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1136 data, ERIAR_OOB); 1137 } 1138 1139 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1140 { 1141 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1142 1143 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1144 } 1145 1146 #define OOB_CMD_RESET 0x00 1147 #define OOB_CMD_DRIVER_START 0x05 1148 #define OOB_CMD_DRIVER_STOP 0x06 1149 1150 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1151 { 1152 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1153 } 1154 1155 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1156 { 1157 u16 reg; 1158 1159 reg = rtl8168_get_ocp_reg(tp); 1160 1161 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1162 } 1163 1164 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1165 { 1166 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1167 } 1168 1169 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1170 { 1171 return RTL_R8(tp, IBISR0) & 0x20; 1172 } 1173 1174 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1175 { 1176 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1177 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1178 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1179 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1180 } 1181 1182 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1183 { 1184 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1185 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1186 } 1187 1188 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1189 { 1190 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1191 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1192 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1193 } 1194 1195 static void rtl8168_driver_start(struct rtl8169_private *tp) 1196 { 1197 if (tp->dash_type == RTL_DASH_DP) 1198 rtl8168dp_driver_start(tp); 1199 else 1200 rtl8168ep_driver_start(tp); 1201 } 1202 1203 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1204 { 1205 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1206 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1207 } 1208 1209 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1210 { 1211 rtl8168ep_stop_cmac(tp); 1212 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1213 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1214 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1215 } 1216 1217 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1218 { 1219 if (tp->dash_type == RTL_DASH_DP) 1220 rtl8168dp_driver_stop(tp); 1221 else 1222 rtl8168ep_driver_stop(tp); 1223 } 1224 1225 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1226 { 1227 u16 reg = rtl8168_get_ocp_reg(tp); 1228 1229 return r8168dp_ocp_read(tp, reg) & BIT(15); 1230 } 1231 1232 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1233 { 1234 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1235 } 1236 1237 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1238 { 1239 switch (tp->mac_version) { 1240 case RTL_GIGA_MAC_VER_27: 1241 case RTL_GIGA_MAC_VER_28: 1242 case RTL_GIGA_MAC_VER_31: 1243 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1244 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 1245 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1246 default: 1247 return RTL_DASH_NONE; 1248 } 1249 } 1250 1251 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1252 { 1253 switch (tp->mac_version) { 1254 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1255 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1256 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1257 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1258 if (enable) 1259 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1260 else 1261 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1262 break; 1263 default: 1264 break; 1265 } 1266 } 1267 1268 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1269 { 1270 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1271 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1272 } 1273 1274 DECLARE_RTL_COND(rtl_efusear_cond) 1275 { 1276 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1277 } 1278 1279 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1280 { 1281 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1282 1283 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1284 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1285 } 1286 1287 static u32 rtl_get_events(struct rtl8169_private *tp) 1288 { 1289 if (rtl_is_8125(tp)) 1290 return RTL_R32(tp, IntrStatus_8125); 1291 else 1292 return RTL_R16(tp, IntrStatus); 1293 } 1294 1295 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1296 { 1297 if (rtl_is_8125(tp)) 1298 RTL_W32(tp, IntrStatus_8125, bits); 1299 else 1300 RTL_W16(tp, IntrStatus, bits); 1301 } 1302 1303 static void rtl_irq_disable(struct rtl8169_private *tp) 1304 { 1305 if (rtl_is_8125(tp)) 1306 RTL_W32(tp, IntrMask_8125, 0); 1307 else 1308 RTL_W16(tp, IntrMask, 0); 1309 } 1310 1311 static void rtl_irq_enable(struct rtl8169_private *tp) 1312 { 1313 if (rtl_is_8125(tp)) 1314 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1315 else 1316 RTL_W16(tp, IntrMask, tp->irq_mask); 1317 } 1318 1319 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1320 { 1321 rtl_irq_disable(tp); 1322 rtl_ack_events(tp, 0xffffffff); 1323 rtl_pci_commit(tp); 1324 } 1325 1326 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1327 { 1328 struct phy_device *phydev = tp->phydev; 1329 1330 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1331 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1332 if (phydev->speed == SPEED_1000) { 1333 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1334 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1335 } else if (phydev->speed == SPEED_100) { 1336 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1337 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1338 } else { 1339 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1340 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1341 } 1342 rtl_reset_packet_filter(tp); 1343 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1344 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1345 if (phydev->speed == SPEED_1000) { 1346 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1347 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1348 } else { 1349 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1350 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1351 } 1352 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1353 if (phydev->speed == SPEED_10) { 1354 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1355 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1356 } else { 1357 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1358 } 1359 } 1360 } 1361 1362 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1363 1364 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1365 { 1366 struct rtl8169_private *tp = netdev_priv(dev); 1367 1368 wol->supported = WAKE_ANY; 1369 wol->wolopts = tp->saved_wolopts; 1370 } 1371 1372 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1373 { 1374 static const struct { 1375 u32 opt; 1376 u16 reg; 1377 u8 mask; 1378 } cfg[] = { 1379 { WAKE_PHY, Config3, LinkUp }, 1380 { WAKE_UCAST, Config5, UWF }, 1381 { WAKE_BCAST, Config5, BWF }, 1382 { WAKE_MCAST, Config5, MWF }, 1383 { WAKE_ANY, Config5, LanWake }, 1384 { WAKE_MAGIC, Config3, MagicPacket } 1385 }; 1386 unsigned int i, tmp = ARRAY_SIZE(cfg); 1387 u8 options; 1388 1389 rtl_unlock_config_regs(tp); 1390 1391 if (rtl_is_8168evl_up(tp)) { 1392 tmp--; 1393 if (wolopts & WAKE_MAGIC) 1394 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1395 else 1396 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1397 } else if (rtl_is_8125(tp)) { 1398 tmp--; 1399 if (wolopts & WAKE_MAGIC) 1400 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1401 else 1402 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1403 } 1404 1405 for (i = 0; i < tmp; i++) { 1406 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1407 if (wolopts & cfg[i].opt) 1408 options |= cfg[i].mask; 1409 RTL_W8(tp, cfg[i].reg, options); 1410 } 1411 1412 switch (tp->mac_version) { 1413 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1414 options = RTL_R8(tp, Config1) & ~PMEnable; 1415 if (wolopts) 1416 options |= PMEnable; 1417 RTL_W8(tp, Config1, options); 1418 break; 1419 case RTL_GIGA_MAC_VER_34: 1420 case RTL_GIGA_MAC_VER_37: 1421 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1422 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1423 if (wolopts) 1424 options |= PME_SIGNAL; 1425 RTL_W8(tp, Config2, options); 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 rtl_lock_config_regs(tp); 1432 1433 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1434 rtl_set_d3_pll_down(tp, !wolopts); 1435 tp->dev->wol_enabled = wolopts ? 1 : 0; 1436 } 1437 1438 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1439 { 1440 struct rtl8169_private *tp = netdev_priv(dev); 1441 1442 if (wol->wolopts & ~WAKE_ANY) 1443 return -EINVAL; 1444 1445 tp->saved_wolopts = wol->wolopts; 1446 __rtl8169_set_wol(tp, tp->saved_wolopts); 1447 1448 return 0; 1449 } 1450 1451 static void rtl8169_get_drvinfo(struct net_device *dev, 1452 struct ethtool_drvinfo *info) 1453 { 1454 struct rtl8169_private *tp = netdev_priv(dev); 1455 struct rtl_fw *rtl_fw = tp->rtl_fw; 1456 1457 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1458 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1459 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1460 if (rtl_fw) 1461 strlcpy(info->fw_version, rtl_fw->version, 1462 sizeof(info->fw_version)); 1463 } 1464 1465 static int rtl8169_get_regs_len(struct net_device *dev) 1466 { 1467 return R8169_REGS_SIZE; 1468 } 1469 1470 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1471 netdev_features_t features) 1472 { 1473 struct rtl8169_private *tp = netdev_priv(dev); 1474 1475 if (dev->mtu > TD_MSS_MAX) 1476 features &= ~NETIF_F_ALL_TSO; 1477 1478 if (dev->mtu > ETH_DATA_LEN && 1479 tp->mac_version > RTL_GIGA_MAC_VER_06) 1480 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1481 1482 return features; 1483 } 1484 1485 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1486 netdev_features_t features) 1487 { 1488 u32 rx_config = RTL_R32(tp, RxConfig); 1489 1490 if (features & NETIF_F_RXALL) 1491 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1492 else 1493 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1494 1495 if (rtl_is_8125(tp)) { 1496 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1497 rx_config |= RX_VLAN_8125; 1498 else 1499 rx_config &= ~RX_VLAN_8125; 1500 } 1501 1502 RTL_W32(tp, RxConfig, rx_config); 1503 } 1504 1505 static int rtl8169_set_features(struct net_device *dev, 1506 netdev_features_t features) 1507 { 1508 struct rtl8169_private *tp = netdev_priv(dev); 1509 1510 rtl_set_rx_config_features(tp, features); 1511 1512 if (features & NETIF_F_RXCSUM) 1513 tp->cp_cmd |= RxChkSum; 1514 else 1515 tp->cp_cmd &= ~RxChkSum; 1516 1517 if (!rtl_is_8125(tp)) { 1518 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1519 tp->cp_cmd |= RxVlan; 1520 else 1521 tp->cp_cmd &= ~RxVlan; 1522 } 1523 1524 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1525 rtl_pci_commit(tp); 1526 1527 return 0; 1528 } 1529 1530 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1531 { 1532 return (skb_vlan_tag_present(skb)) ? 1533 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1534 } 1535 1536 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1537 { 1538 u32 opts2 = le32_to_cpu(desc->opts2); 1539 1540 if (opts2 & RxVlanTag) 1541 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1542 } 1543 1544 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1545 void *p) 1546 { 1547 struct rtl8169_private *tp = netdev_priv(dev); 1548 u32 __iomem *data = tp->mmio_addr; 1549 u32 *dw = p; 1550 int i; 1551 1552 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1553 memcpy_fromio(dw++, data++, 4); 1554 } 1555 1556 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1557 "tx_packets", 1558 "rx_packets", 1559 "tx_errors", 1560 "rx_errors", 1561 "rx_missed", 1562 "align_errors", 1563 "tx_single_collisions", 1564 "tx_multi_collisions", 1565 "unicast", 1566 "broadcast", 1567 "multicast", 1568 "tx_aborted", 1569 "tx_underrun", 1570 }; 1571 1572 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1573 { 1574 switch (sset) { 1575 case ETH_SS_STATS: 1576 return ARRAY_SIZE(rtl8169_gstrings); 1577 default: 1578 return -EOPNOTSUPP; 1579 } 1580 } 1581 1582 DECLARE_RTL_COND(rtl_counters_cond) 1583 { 1584 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1585 } 1586 1587 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1588 { 1589 dma_addr_t paddr = tp->counters_phys_addr; 1590 u32 cmd; 1591 1592 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1593 rtl_pci_commit(tp); 1594 cmd = (u64)paddr & DMA_BIT_MASK(32); 1595 RTL_W32(tp, CounterAddrLow, cmd); 1596 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1597 1598 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1599 } 1600 1601 static void rtl8169_update_counters(struct rtl8169_private *tp) 1602 { 1603 u8 val = RTL_R8(tp, ChipCmd); 1604 1605 /* 1606 * Some chips are unable to dump tally counters when the receiver 1607 * is disabled. If 0xff chip may be in a PCI power-save state. 1608 */ 1609 if (val & CmdRxEnb && val != 0xff) 1610 rtl8169_do_counters(tp, CounterDump); 1611 } 1612 1613 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1614 { 1615 struct rtl8169_counters *counters = tp->counters; 1616 1617 /* 1618 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1619 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1620 * reset by a power cycle, while the counter values collected by the 1621 * driver are reset at every driver unload/load cycle. 1622 * 1623 * To make sure the HW values returned by @get_stats64 match the SW 1624 * values, we collect the initial values at first open(*) and use them 1625 * as offsets to normalize the values returned by @get_stats64. 1626 * 1627 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1628 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1629 * set at open time by rtl_hw_start. 1630 */ 1631 1632 if (tp->tc_offset.inited) 1633 return; 1634 1635 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1636 rtl8169_do_counters(tp, CounterReset); 1637 } else { 1638 rtl8169_update_counters(tp); 1639 tp->tc_offset.tx_errors = counters->tx_errors; 1640 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1641 tp->tc_offset.tx_aborted = counters->tx_aborted; 1642 tp->tc_offset.rx_missed = counters->rx_missed; 1643 } 1644 1645 tp->tc_offset.inited = true; 1646 } 1647 1648 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1649 struct ethtool_stats *stats, u64 *data) 1650 { 1651 struct rtl8169_private *tp = netdev_priv(dev); 1652 struct rtl8169_counters *counters; 1653 1654 counters = tp->counters; 1655 rtl8169_update_counters(tp); 1656 1657 data[0] = le64_to_cpu(counters->tx_packets); 1658 data[1] = le64_to_cpu(counters->rx_packets); 1659 data[2] = le64_to_cpu(counters->tx_errors); 1660 data[3] = le32_to_cpu(counters->rx_errors); 1661 data[4] = le16_to_cpu(counters->rx_missed); 1662 data[5] = le16_to_cpu(counters->align_errors); 1663 data[6] = le32_to_cpu(counters->tx_one_collision); 1664 data[7] = le32_to_cpu(counters->tx_multi_collision); 1665 data[8] = le64_to_cpu(counters->rx_unicast); 1666 data[9] = le64_to_cpu(counters->rx_broadcast); 1667 data[10] = le32_to_cpu(counters->rx_multicast); 1668 data[11] = le16_to_cpu(counters->tx_aborted); 1669 data[12] = le16_to_cpu(counters->tx_underun); 1670 } 1671 1672 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1673 { 1674 switch(stringset) { 1675 case ETH_SS_STATS: 1676 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1677 break; 1678 } 1679 } 1680 1681 /* 1682 * Interrupt coalescing 1683 * 1684 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1685 * > 8169, 8168 and 810x line of chipsets 1686 * 1687 * 8169, 8168, and 8136(810x) serial chipsets support it. 1688 * 1689 * > 2 - the Tx timer unit at gigabit speed 1690 * 1691 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1692 * (0xe0) bit 1 and bit 0. 1693 * 1694 * For 8169 1695 * bit[1:0] \ speed 1000M 100M 10M 1696 * 0 0 320ns 2.56us 40.96us 1697 * 0 1 2.56us 20.48us 327.7us 1698 * 1 0 5.12us 40.96us 655.4us 1699 * 1 1 10.24us 81.92us 1.31ms 1700 * 1701 * For the other 1702 * bit[1:0] \ speed 1000M 100M 10M 1703 * 0 0 5us 2.56us 40.96us 1704 * 0 1 40us 20.48us 327.7us 1705 * 1 0 80us 40.96us 655.4us 1706 * 1 1 160us 81.92us 1.31ms 1707 */ 1708 1709 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1710 struct rtl_coalesce_info { 1711 u32 speed; 1712 u32 scale_nsecs[4]; 1713 }; 1714 1715 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1716 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1717 1718 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1719 { SPEED_1000, COALESCE_DELAY(320) }, 1720 { SPEED_100, COALESCE_DELAY(2560) }, 1721 { SPEED_10, COALESCE_DELAY(40960) }, 1722 { 0 }, 1723 }; 1724 1725 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1726 { SPEED_1000, COALESCE_DELAY(5000) }, 1727 { SPEED_100, COALESCE_DELAY(2560) }, 1728 { SPEED_10, COALESCE_DELAY(40960) }, 1729 { 0 }, 1730 }; 1731 #undef COALESCE_DELAY 1732 1733 /* get rx/tx scale vector corresponding to current speed */ 1734 static const struct rtl_coalesce_info * 1735 rtl_coalesce_info(struct rtl8169_private *tp) 1736 { 1737 const struct rtl_coalesce_info *ci; 1738 1739 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1740 ci = rtl_coalesce_info_8169; 1741 else 1742 ci = rtl_coalesce_info_8168_8136; 1743 1744 /* if speed is unknown assume highest one */ 1745 if (tp->phydev->speed == SPEED_UNKNOWN) 1746 return ci; 1747 1748 for (; ci->speed; ci++) { 1749 if (tp->phydev->speed == ci->speed) 1750 return ci; 1751 } 1752 1753 return ERR_PTR(-ELNRNG); 1754 } 1755 1756 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1757 { 1758 struct rtl8169_private *tp = netdev_priv(dev); 1759 const struct rtl_coalesce_info *ci; 1760 u32 scale, c_us, c_fr; 1761 u16 intrmit; 1762 1763 if (rtl_is_8125(tp)) 1764 return -EOPNOTSUPP; 1765 1766 memset(ec, 0, sizeof(*ec)); 1767 1768 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1769 ci = rtl_coalesce_info(tp); 1770 if (IS_ERR(ci)) 1771 return PTR_ERR(ci); 1772 1773 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1774 1775 intrmit = RTL_R16(tp, IntrMitigate); 1776 1777 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1778 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1779 1780 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1781 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1782 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1783 1784 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1785 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1786 1787 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1788 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1789 1790 return 0; 1791 } 1792 1793 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1794 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1795 u16 *cp01) 1796 { 1797 const struct rtl_coalesce_info *ci; 1798 u16 i; 1799 1800 ci = rtl_coalesce_info(tp); 1801 if (IS_ERR(ci)) 1802 return PTR_ERR(ci); 1803 1804 for (i = 0; i < 4; i++) { 1805 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1806 *cp01 = i; 1807 return ci->scale_nsecs[i]; 1808 } 1809 } 1810 1811 return -ERANGE; 1812 } 1813 1814 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1815 { 1816 struct rtl8169_private *tp = netdev_priv(dev); 1817 u32 tx_fr = ec->tx_max_coalesced_frames; 1818 u32 rx_fr = ec->rx_max_coalesced_frames; 1819 u32 coal_usec_max, units; 1820 u16 w = 0, cp01 = 0; 1821 int scale; 1822 1823 if (rtl_is_8125(tp)) 1824 return -EOPNOTSUPP; 1825 1826 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1827 return -ERANGE; 1828 1829 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1830 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1831 if (scale < 0) 1832 return scale; 1833 1834 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1835 * not only when usecs=0 because of e.g. the following scenario: 1836 * 1837 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1838 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1839 * - then user does `ethtool -C eth0 rx-usecs 100` 1840 * 1841 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1842 * if we want to ignore rx_frames then it has to be set to 0. 1843 */ 1844 if (rx_fr == 1) 1845 rx_fr = 0; 1846 if (tx_fr == 1) 1847 tx_fr = 0; 1848 1849 /* HW requires time limit to be set if frame limit is set */ 1850 if ((tx_fr && !ec->tx_coalesce_usecs) || 1851 (rx_fr && !ec->rx_coalesce_usecs)) 1852 return -EINVAL; 1853 1854 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1855 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1856 1857 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1858 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1859 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1860 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1861 1862 RTL_W16(tp, IntrMitigate, w); 1863 1864 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1865 if (rtl_is_8168evl_up(tp)) { 1866 if (!rx_fr && !tx_fr) 1867 /* disable packet counter */ 1868 tp->cp_cmd |= PktCntrDisable; 1869 else 1870 tp->cp_cmd &= ~PktCntrDisable; 1871 } 1872 1873 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1874 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1875 rtl_pci_commit(tp); 1876 1877 return 0; 1878 } 1879 1880 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1881 { 1882 struct rtl8169_private *tp = netdev_priv(dev); 1883 1884 if (!rtl_supports_eee(tp)) 1885 return -EOPNOTSUPP; 1886 1887 return phy_ethtool_get_eee(tp->phydev, data); 1888 } 1889 1890 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1891 { 1892 struct rtl8169_private *tp = netdev_priv(dev); 1893 int ret; 1894 1895 if (!rtl_supports_eee(tp)) 1896 return -EOPNOTSUPP; 1897 1898 ret = phy_ethtool_set_eee(tp->phydev, data); 1899 1900 if (!ret) 1901 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1902 MDIO_AN_EEE_ADV); 1903 return ret; 1904 } 1905 1906 static const struct ethtool_ops rtl8169_ethtool_ops = { 1907 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1908 ETHTOOL_COALESCE_MAX_FRAMES, 1909 .get_drvinfo = rtl8169_get_drvinfo, 1910 .get_regs_len = rtl8169_get_regs_len, 1911 .get_link = ethtool_op_get_link, 1912 .get_coalesce = rtl_get_coalesce, 1913 .set_coalesce = rtl_set_coalesce, 1914 .get_regs = rtl8169_get_regs, 1915 .get_wol = rtl8169_get_wol, 1916 .set_wol = rtl8169_set_wol, 1917 .get_strings = rtl8169_get_strings, 1918 .get_sset_count = rtl8169_get_sset_count, 1919 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1920 .get_ts_info = ethtool_op_get_ts_info, 1921 .nway_reset = phy_ethtool_nway_reset, 1922 .get_eee = rtl8169_get_eee, 1923 .set_eee = rtl8169_set_eee, 1924 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1925 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1926 }; 1927 1928 static void rtl_enable_eee(struct rtl8169_private *tp) 1929 { 1930 struct phy_device *phydev = tp->phydev; 1931 int adv; 1932 1933 /* respect EEE advertisement the user may have set */ 1934 if (tp->eee_adv >= 0) 1935 adv = tp->eee_adv; 1936 else 1937 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1938 1939 if (adv >= 0) 1940 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1941 } 1942 1943 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1944 { 1945 /* 1946 * The driver currently handles the 8168Bf and the 8168Be identically 1947 * but they can be identified more specifically through the test below 1948 * if needed: 1949 * 1950 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1951 * 1952 * Same thing for the 8101Eb and the 8101Ec: 1953 * 1954 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1955 */ 1956 static const struct rtl_mac_info { 1957 u16 mask; 1958 u16 val; 1959 enum mac_version ver; 1960 } mac_info[] = { 1961 /* 8125B family. */ 1962 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1963 1964 /* 8125A family. */ 1965 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1966 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1967 1968 /* RTL8117 */ 1969 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 1970 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1971 1972 /* 8168EP family. */ 1973 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1974 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1975 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1976 1977 /* 8168H family. */ 1978 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1979 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1980 1981 /* 8168G family. */ 1982 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1983 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1984 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1985 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1986 1987 /* 8168F family. */ 1988 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 1989 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 1990 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 1991 1992 /* 8168E family. */ 1993 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 1994 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 1995 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 1996 1997 /* 8168D family. */ 1998 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 1999 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2000 2001 /* 8168DP family. */ 2002 /* It seems this early RTL8168dp version never made it to 2003 * the wild. Let's see whether somebody complains, if not 2004 * we'll remove support for this chip version completely. 2005 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2006 */ 2007 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2008 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2009 2010 /* 8168C family. */ 2011 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2012 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2013 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2014 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2015 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2016 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2017 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2018 2019 /* 8168B family. */ 2020 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2021 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2022 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2023 2024 /* 8101 family. */ 2025 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2026 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2027 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2028 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2029 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2030 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2031 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2032 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2033 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2034 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2035 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2036 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2037 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2038 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2039 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2040 /* FIXME: where did these entries come from ? -- FR 2041 * Not even r8101 vendor driver knows these id's, 2042 * so let's disable detection for now. -- HK 2043 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2044 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2045 */ 2046 2047 /* 8110 family. */ 2048 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2049 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2050 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2051 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2052 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2053 2054 /* Catch-all */ 2055 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2056 }; 2057 const struct rtl_mac_info *p = mac_info; 2058 enum mac_version ver; 2059 2060 while ((xid & p->mask) != p->val) 2061 p++; 2062 ver = p->ver; 2063 2064 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2065 if (ver == RTL_GIGA_MAC_VER_42) 2066 ver = RTL_GIGA_MAC_VER_43; 2067 else if (ver == RTL_GIGA_MAC_VER_45) 2068 ver = RTL_GIGA_MAC_VER_47; 2069 else if (ver == RTL_GIGA_MAC_VER_46) 2070 ver = RTL_GIGA_MAC_VER_48; 2071 } 2072 2073 return ver; 2074 } 2075 2076 static void rtl_release_firmware(struct rtl8169_private *tp) 2077 { 2078 if (tp->rtl_fw) { 2079 rtl_fw_release_firmware(tp->rtl_fw); 2080 kfree(tp->rtl_fw); 2081 tp->rtl_fw = NULL; 2082 } 2083 } 2084 2085 void r8169_apply_firmware(struct rtl8169_private *tp) 2086 { 2087 int val; 2088 2089 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2090 if (tp->rtl_fw) { 2091 rtl_fw_write_firmware(tp, tp->rtl_fw); 2092 /* At least one firmware doesn't reset tp->ocp_base. */ 2093 tp->ocp_base = OCP_STD_PHY_BASE; 2094 2095 /* PHY soft reset may still be in progress */ 2096 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2097 !(val & BMCR_RESET), 2098 50000, 600000, true); 2099 } 2100 } 2101 2102 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2103 { 2104 /* Adjust EEE LED frequency */ 2105 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2106 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2107 2108 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2109 } 2110 2111 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2112 { 2113 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2114 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2115 } 2116 2117 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2118 { 2119 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2120 } 2121 2122 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2123 { 2124 rtl8125_set_eee_txidle_timer(tp); 2125 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2126 } 2127 2128 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2129 { 2130 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2131 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2132 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2133 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2134 } 2135 2136 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2137 { 2138 u16 data1, data2, ioffset; 2139 2140 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2141 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2142 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2143 2144 ioffset = (data2 >> 1) & 0x7ff8; 2145 ioffset |= data2 & 0x0007; 2146 if (data1 & BIT(7)) 2147 ioffset |= BIT(15); 2148 2149 return ioffset; 2150 } 2151 2152 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2153 { 2154 set_bit(flag, tp->wk.flags); 2155 schedule_work(&tp->wk.work); 2156 } 2157 2158 static void rtl8169_init_phy(struct rtl8169_private *tp) 2159 { 2160 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2161 2162 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2163 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2164 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2165 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2166 RTL_W8(tp, 0x82, 0x01); 2167 } 2168 2169 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2170 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2171 tp->pci_dev->subsystem_device == 0xe000) 2172 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2173 2174 /* We may have called phy_speed_down before */ 2175 phy_speed_up(tp->phydev); 2176 2177 if (rtl_supports_eee(tp)) 2178 rtl_enable_eee(tp); 2179 2180 genphy_soft_reset(tp->phydev); 2181 } 2182 2183 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2184 { 2185 rtl_unlock_config_regs(tp); 2186 2187 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2188 rtl_pci_commit(tp); 2189 2190 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2191 rtl_pci_commit(tp); 2192 2193 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2194 rtl_rar_exgmac_set(tp, addr); 2195 2196 rtl_lock_config_regs(tp); 2197 } 2198 2199 static int rtl_set_mac_address(struct net_device *dev, void *p) 2200 { 2201 struct rtl8169_private *tp = netdev_priv(dev); 2202 int ret; 2203 2204 ret = eth_mac_addr(dev, p); 2205 if (ret) 2206 return ret; 2207 2208 rtl_rar_set(tp, dev->dev_addr); 2209 2210 return 0; 2211 } 2212 2213 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2214 { 2215 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2216 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2217 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2218 } 2219 2220 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2221 { 2222 if (tp->dash_type != RTL_DASH_NONE) 2223 return; 2224 2225 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2226 tp->mac_version == RTL_GIGA_MAC_VER_33) 2227 rtl_ephy_write(tp, 0x19, 0xff64); 2228 2229 if (device_may_wakeup(tp_to_dev(tp))) { 2230 phy_speed_down(tp->phydev, false); 2231 rtl_wol_enable_rx(tp); 2232 } 2233 } 2234 2235 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2236 { 2237 switch (tp->mac_version) { 2238 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2239 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2240 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2241 break; 2242 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2243 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2244 case RTL_GIGA_MAC_VER_38: 2245 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2246 break; 2247 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2248 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2249 break; 2250 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2251 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2252 break; 2253 default: 2254 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2255 break; 2256 } 2257 } 2258 2259 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2260 { 2261 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2262 } 2263 2264 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2265 { 2266 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2267 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2268 } 2269 2270 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2271 { 2272 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2273 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2274 } 2275 2276 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2277 { 2278 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2279 } 2280 2281 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2282 { 2283 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2284 } 2285 2286 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2287 { 2288 RTL_W8(tp, MaxTxPacketSize, 0x24); 2289 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2290 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2291 } 2292 2293 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2294 { 2295 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2296 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2297 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2298 } 2299 2300 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2301 { 2302 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2303 } 2304 2305 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2306 { 2307 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2308 } 2309 2310 static void rtl_jumbo_config(struct rtl8169_private *tp) 2311 { 2312 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2313 int readrq = 4096; 2314 2315 rtl_unlock_config_regs(tp); 2316 switch (tp->mac_version) { 2317 case RTL_GIGA_MAC_VER_12: 2318 case RTL_GIGA_MAC_VER_17: 2319 if (jumbo) { 2320 readrq = 512; 2321 r8168b_1_hw_jumbo_enable(tp); 2322 } else { 2323 r8168b_1_hw_jumbo_disable(tp); 2324 } 2325 break; 2326 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2327 if (jumbo) { 2328 readrq = 512; 2329 r8168c_hw_jumbo_enable(tp); 2330 } else { 2331 r8168c_hw_jumbo_disable(tp); 2332 } 2333 break; 2334 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2335 if (jumbo) 2336 r8168dp_hw_jumbo_enable(tp); 2337 else 2338 r8168dp_hw_jumbo_disable(tp); 2339 break; 2340 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2341 if (jumbo) 2342 r8168e_hw_jumbo_enable(tp); 2343 else 2344 r8168e_hw_jumbo_disable(tp); 2345 break; 2346 default: 2347 break; 2348 } 2349 rtl_lock_config_regs(tp); 2350 2351 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2352 pcie_set_readrq(tp->pci_dev, readrq); 2353 } 2354 2355 DECLARE_RTL_COND(rtl_chipcmd_cond) 2356 { 2357 return RTL_R8(tp, ChipCmd) & CmdReset; 2358 } 2359 2360 static void rtl_hw_reset(struct rtl8169_private *tp) 2361 { 2362 RTL_W8(tp, ChipCmd, CmdReset); 2363 2364 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2365 } 2366 2367 static void rtl_request_firmware(struct rtl8169_private *tp) 2368 { 2369 struct rtl_fw *rtl_fw; 2370 2371 /* firmware loaded already or no firmware available */ 2372 if (tp->rtl_fw || !tp->fw_name) 2373 return; 2374 2375 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2376 if (!rtl_fw) 2377 return; 2378 2379 rtl_fw->phy_write = rtl_writephy; 2380 rtl_fw->phy_read = rtl_readphy; 2381 rtl_fw->mac_mcu_write = mac_mcu_write; 2382 rtl_fw->mac_mcu_read = mac_mcu_read; 2383 rtl_fw->fw_name = tp->fw_name; 2384 rtl_fw->dev = tp_to_dev(tp); 2385 2386 if (rtl_fw_request_firmware(rtl_fw)) 2387 kfree(rtl_fw); 2388 else 2389 tp->rtl_fw = rtl_fw; 2390 } 2391 2392 static void rtl_rx_close(struct rtl8169_private *tp) 2393 { 2394 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2395 } 2396 2397 DECLARE_RTL_COND(rtl_npq_cond) 2398 { 2399 return RTL_R8(tp, TxPoll) & NPQ; 2400 } 2401 2402 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2403 { 2404 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2405 } 2406 2407 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2408 { 2409 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2410 } 2411 2412 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2413 { 2414 /* IntrMitigate has new functionality on RTL8125 */ 2415 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2416 } 2417 2418 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2419 { 2420 switch (tp->mac_version) { 2421 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2422 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2423 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2424 break; 2425 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2426 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2427 break; 2428 case RTL_GIGA_MAC_VER_63: 2429 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2430 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2431 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2432 break; 2433 default: 2434 break; 2435 } 2436 } 2437 2438 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2439 { 2440 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2441 fsleep(2000); 2442 rtl_wait_txrx_fifo_empty(tp); 2443 } 2444 2445 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2446 { 2447 u32 val = TX_DMA_BURST << TxDMAShift | 2448 InterFrameGap << TxInterFrameGapShift; 2449 2450 if (rtl_is_8168evl_up(tp)) 2451 val |= TXCFG_AUTO_FIFO; 2452 2453 RTL_W32(tp, TxConfig, val); 2454 } 2455 2456 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2457 { 2458 /* Low hurts. Let's disable the filtering. */ 2459 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2460 } 2461 2462 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2463 { 2464 /* 2465 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2466 * register to be written before TxDescAddrLow to work. 2467 * Switching from MMIO to I/O access fixes the issue as well. 2468 */ 2469 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2470 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2471 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2472 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2473 } 2474 2475 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2476 { 2477 u32 val; 2478 2479 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2480 val = 0x000fff00; 2481 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2482 val = 0x00ffff00; 2483 else 2484 return; 2485 2486 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2487 val |= 0xff; 2488 2489 RTL_W32(tp, 0x7c, val); 2490 } 2491 2492 static void rtl_set_rx_mode(struct net_device *dev) 2493 { 2494 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2495 /* Multicast hash filter */ 2496 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2497 struct rtl8169_private *tp = netdev_priv(dev); 2498 u32 tmp; 2499 2500 if (dev->flags & IFF_PROMISC) { 2501 rx_mode |= AcceptAllPhys; 2502 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2503 dev->flags & IFF_ALLMULTI || 2504 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2505 /* accept all multicasts */ 2506 } else if (netdev_mc_empty(dev)) { 2507 rx_mode &= ~AcceptMulticast; 2508 } else { 2509 struct netdev_hw_addr *ha; 2510 2511 mc_filter[1] = mc_filter[0] = 0; 2512 netdev_for_each_mc_addr(ha, dev) { 2513 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2514 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2515 } 2516 2517 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2518 tmp = mc_filter[0]; 2519 mc_filter[0] = swab32(mc_filter[1]); 2520 mc_filter[1] = swab32(tmp); 2521 } 2522 } 2523 2524 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2525 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2526 2527 tmp = RTL_R32(tp, RxConfig); 2528 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2529 } 2530 2531 DECLARE_RTL_COND(rtl_csiar_cond) 2532 { 2533 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2534 } 2535 2536 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2537 { 2538 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2539 2540 RTL_W32(tp, CSIDR, value); 2541 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2542 CSIAR_BYTE_ENABLE | func << 16); 2543 2544 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2545 } 2546 2547 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2548 { 2549 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2550 2551 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2552 CSIAR_BYTE_ENABLE); 2553 2554 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2555 RTL_R32(tp, CSIDR) : ~0; 2556 } 2557 2558 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2559 { 2560 struct pci_dev *pdev = tp->pci_dev; 2561 u32 csi; 2562 2563 /* According to Realtek the value at config space address 0x070f 2564 * controls the L0s/L1 entrance latency. We try standard ECAM access 2565 * first and if it fails fall back to CSI. 2566 */ 2567 if (pdev->cfg_size > 0x070f && 2568 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2569 return; 2570 2571 netdev_notice_once(tp->dev, 2572 "No native access to PCI extended config space, falling back to CSI\n"); 2573 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2574 rtl_csi_write(tp, 0x070c, csi | val << 24); 2575 } 2576 2577 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2578 { 2579 rtl_csi_access_enable(tp, 0x27); 2580 } 2581 2582 struct ephy_info { 2583 unsigned int offset; 2584 u16 mask; 2585 u16 bits; 2586 }; 2587 2588 static void __rtl_ephy_init(struct rtl8169_private *tp, 2589 const struct ephy_info *e, int len) 2590 { 2591 u16 w; 2592 2593 while (len-- > 0) { 2594 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2595 rtl_ephy_write(tp, e->offset, w); 2596 e++; 2597 } 2598 } 2599 2600 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2601 2602 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2603 { 2604 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2605 PCI_EXP_LNKCTL_CLKREQ_EN); 2606 } 2607 2608 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2609 { 2610 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2611 PCI_EXP_LNKCTL_CLKREQ_EN); 2612 } 2613 2614 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2615 { 2616 /* work around an issue when PCI reset occurs during L2/L3 state */ 2617 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2618 } 2619 2620 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2621 { 2622 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2623 if (enable && tp->aspm_manageable) { 2624 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2625 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2626 } else { 2627 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2628 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2629 } 2630 2631 udelay(10); 2632 } 2633 2634 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2635 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2636 { 2637 /* Usage of dynamic vs. static FIFO is controlled by bit 2638 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2639 */ 2640 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2641 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2642 } 2643 2644 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2645 u8 low, u8 high) 2646 { 2647 /* FIFO thresholds for pause flow control */ 2648 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2649 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2650 } 2651 2652 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2653 { 2654 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2655 } 2656 2657 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2658 { 2659 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2660 2661 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2662 2663 rtl_disable_clock_request(tp); 2664 } 2665 2666 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2667 { 2668 static const struct ephy_info e_info_8168cp[] = { 2669 { 0x01, 0, 0x0001 }, 2670 { 0x02, 0x0800, 0x1000 }, 2671 { 0x03, 0, 0x0042 }, 2672 { 0x06, 0x0080, 0x0000 }, 2673 { 0x07, 0, 0x2000 } 2674 }; 2675 2676 rtl_set_def_aspm_entry_latency(tp); 2677 2678 rtl_ephy_init(tp, e_info_8168cp); 2679 2680 __rtl_hw_start_8168cp(tp); 2681 } 2682 2683 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2684 { 2685 rtl_set_def_aspm_entry_latency(tp); 2686 2687 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2688 } 2689 2690 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2691 { 2692 rtl_set_def_aspm_entry_latency(tp); 2693 2694 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2695 2696 /* Magic. */ 2697 RTL_W8(tp, DBG_REG, 0x20); 2698 } 2699 2700 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2701 { 2702 static const struct ephy_info e_info_8168c_1[] = { 2703 { 0x02, 0x0800, 0x1000 }, 2704 { 0x03, 0, 0x0002 }, 2705 { 0x06, 0x0080, 0x0000 } 2706 }; 2707 2708 rtl_set_def_aspm_entry_latency(tp); 2709 2710 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2711 2712 rtl_ephy_init(tp, e_info_8168c_1); 2713 2714 __rtl_hw_start_8168cp(tp); 2715 } 2716 2717 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2718 { 2719 static const struct ephy_info e_info_8168c_2[] = { 2720 { 0x01, 0, 0x0001 }, 2721 { 0x03, 0x0400, 0x0020 } 2722 }; 2723 2724 rtl_set_def_aspm_entry_latency(tp); 2725 2726 rtl_ephy_init(tp, e_info_8168c_2); 2727 2728 __rtl_hw_start_8168cp(tp); 2729 } 2730 2731 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2732 { 2733 rtl_hw_start_8168c_2(tp); 2734 } 2735 2736 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2737 { 2738 rtl_set_def_aspm_entry_latency(tp); 2739 2740 __rtl_hw_start_8168cp(tp); 2741 } 2742 2743 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2744 { 2745 rtl_set_def_aspm_entry_latency(tp); 2746 2747 rtl_disable_clock_request(tp); 2748 } 2749 2750 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2751 { 2752 static const struct ephy_info e_info_8168d_4[] = { 2753 { 0x0b, 0x0000, 0x0048 }, 2754 { 0x19, 0x0020, 0x0050 }, 2755 { 0x0c, 0x0100, 0x0020 }, 2756 { 0x10, 0x0004, 0x0000 }, 2757 }; 2758 2759 rtl_set_def_aspm_entry_latency(tp); 2760 2761 rtl_ephy_init(tp, e_info_8168d_4); 2762 2763 rtl_enable_clock_request(tp); 2764 } 2765 2766 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2767 { 2768 static const struct ephy_info e_info_8168e_1[] = { 2769 { 0x00, 0x0200, 0x0100 }, 2770 { 0x00, 0x0000, 0x0004 }, 2771 { 0x06, 0x0002, 0x0001 }, 2772 { 0x06, 0x0000, 0x0030 }, 2773 { 0x07, 0x0000, 0x2000 }, 2774 { 0x00, 0x0000, 0x0020 }, 2775 { 0x03, 0x5800, 0x2000 }, 2776 { 0x03, 0x0000, 0x0001 }, 2777 { 0x01, 0x0800, 0x1000 }, 2778 { 0x07, 0x0000, 0x4000 }, 2779 { 0x1e, 0x0000, 0x2000 }, 2780 { 0x19, 0xffff, 0xfe6c }, 2781 { 0x0a, 0x0000, 0x0040 } 2782 }; 2783 2784 rtl_set_def_aspm_entry_latency(tp); 2785 2786 rtl_ephy_init(tp, e_info_8168e_1); 2787 2788 rtl_disable_clock_request(tp); 2789 2790 /* Reset tx FIFO pointer */ 2791 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2792 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2793 2794 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2795 } 2796 2797 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2798 { 2799 static const struct ephy_info e_info_8168e_2[] = { 2800 { 0x09, 0x0000, 0x0080 }, 2801 { 0x19, 0x0000, 0x0224 }, 2802 { 0x00, 0x0000, 0x0004 }, 2803 { 0x0c, 0x3df0, 0x0200 }, 2804 }; 2805 2806 rtl_set_def_aspm_entry_latency(tp); 2807 2808 rtl_ephy_init(tp, e_info_8168e_2); 2809 2810 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2811 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2812 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2813 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2814 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2815 rtl_reset_packet_filter(tp); 2816 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2817 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2818 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2819 2820 rtl_disable_clock_request(tp); 2821 2822 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2823 2824 rtl8168_config_eee_mac(tp); 2825 2826 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2827 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2828 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2829 2830 rtl_hw_aspm_clkreq_enable(tp, true); 2831 } 2832 2833 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2834 { 2835 rtl_set_def_aspm_entry_latency(tp); 2836 2837 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2838 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2839 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2840 rtl_reset_packet_filter(tp); 2841 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2842 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2843 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2844 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2845 2846 rtl_disable_clock_request(tp); 2847 2848 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2849 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2850 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2851 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2852 2853 rtl8168_config_eee_mac(tp); 2854 } 2855 2856 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2857 { 2858 static const struct ephy_info e_info_8168f_1[] = { 2859 { 0x06, 0x00c0, 0x0020 }, 2860 { 0x08, 0x0001, 0x0002 }, 2861 { 0x09, 0x0000, 0x0080 }, 2862 { 0x19, 0x0000, 0x0224 }, 2863 { 0x00, 0x0000, 0x0008 }, 2864 { 0x0c, 0x3df0, 0x0200 }, 2865 }; 2866 2867 rtl_hw_start_8168f(tp); 2868 2869 rtl_ephy_init(tp, e_info_8168f_1); 2870 2871 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2872 } 2873 2874 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2875 { 2876 static const struct ephy_info e_info_8168f_1[] = { 2877 { 0x06, 0x00c0, 0x0020 }, 2878 { 0x0f, 0xffff, 0x5200 }, 2879 { 0x19, 0x0000, 0x0224 }, 2880 { 0x00, 0x0000, 0x0008 }, 2881 { 0x0c, 0x3df0, 0x0200 }, 2882 }; 2883 2884 rtl_hw_start_8168f(tp); 2885 rtl_pcie_state_l2l3_disable(tp); 2886 2887 rtl_ephy_init(tp, e_info_8168f_1); 2888 2889 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2890 } 2891 2892 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2893 { 2894 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2895 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2896 2897 rtl_set_def_aspm_entry_latency(tp); 2898 2899 rtl_reset_packet_filter(tp); 2900 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2901 2902 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2903 2904 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2905 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2906 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2907 2908 rtl8168_config_eee_mac(tp); 2909 2910 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2911 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2912 2913 rtl_pcie_state_l2l3_disable(tp); 2914 } 2915 2916 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2917 { 2918 static const struct ephy_info e_info_8168g_1[] = { 2919 { 0x00, 0x0008, 0x0000 }, 2920 { 0x0c, 0x3ff0, 0x0820 }, 2921 { 0x1e, 0x0000, 0x0001 }, 2922 { 0x19, 0x8000, 0x0000 } 2923 }; 2924 2925 rtl_hw_start_8168g(tp); 2926 2927 /* disable aspm and clock request before access ephy */ 2928 rtl_hw_aspm_clkreq_enable(tp, false); 2929 rtl_ephy_init(tp, e_info_8168g_1); 2930 rtl_hw_aspm_clkreq_enable(tp, true); 2931 } 2932 2933 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 2934 { 2935 static const struct ephy_info e_info_8168g_2[] = { 2936 { 0x00, 0x0008, 0x0000 }, 2937 { 0x0c, 0x3ff0, 0x0820 }, 2938 { 0x19, 0xffff, 0x7c00 }, 2939 { 0x1e, 0xffff, 0x20eb }, 2940 { 0x0d, 0xffff, 0x1666 }, 2941 { 0x00, 0xffff, 0x10a3 }, 2942 { 0x06, 0xffff, 0xf050 }, 2943 { 0x04, 0x0000, 0x0010 }, 2944 { 0x1d, 0x4000, 0x0000 }, 2945 }; 2946 2947 rtl_hw_start_8168g(tp); 2948 2949 /* disable aspm and clock request before access ephy */ 2950 rtl_hw_aspm_clkreq_enable(tp, false); 2951 rtl_ephy_init(tp, e_info_8168g_2); 2952 } 2953 2954 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 2955 { 2956 static const struct ephy_info e_info_8411_2[] = { 2957 { 0x00, 0x0008, 0x0000 }, 2958 { 0x0c, 0x37d0, 0x0820 }, 2959 { 0x1e, 0x0000, 0x0001 }, 2960 { 0x19, 0x8021, 0x0000 }, 2961 { 0x1e, 0x0000, 0x2000 }, 2962 { 0x0d, 0x0100, 0x0200 }, 2963 { 0x00, 0x0000, 0x0080 }, 2964 { 0x06, 0x0000, 0x0010 }, 2965 { 0x04, 0x0000, 0x0010 }, 2966 { 0x1d, 0x0000, 0x4000 }, 2967 }; 2968 2969 rtl_hw_start_8168g(tp); 2970 2971 /* disable aspm and clock request before access ephy */ 2972 rtl_hw_aspm_clkreq_enable(tp, false); 2973 rtl_ephy_init(tp, e_info_8411_2); 2974 2975 /* The following Realtek-provided magic fixes an issue with the RX unit 2976 * getting confused after the PHY having been powered-down. 2977 */ 2978 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 2979 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 2980 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 2981 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 2982 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 2983 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 2984 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 2985 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 2986 mdelay(3); 2987 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 2988 2989 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 2990 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 2991 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 2992 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 2993 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 2994 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 2995 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 2996 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 2997 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 2998 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 2999 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3000 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3001 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3002 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3003 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3004 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3005 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3006 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3007 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3008 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3009 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3010 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3011 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3012 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3013 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3014 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3015 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3016 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3017 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3018 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3019 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3020 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3021 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3022 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3023 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3024 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3025 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3026 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3027 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3028 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3029 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3030 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3031 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3032 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3033 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3034 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3035 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3036 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3037 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3038 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3039 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3040 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3041 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3042 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3043 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3044 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3045 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3046 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3047 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3048 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3049 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3050 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3051 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3052 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3053 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3054 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3055 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3056 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3057 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3058 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3059 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3060 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3061 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3062 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3063 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3064 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3065 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3066 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3067 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3068 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3069 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3070 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3071 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3072 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3073 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3074 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3075 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3076 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3077 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3078 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3079 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3080 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3081 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3082 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3083 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3084 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3085 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3086 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3087 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3088 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3089 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3090 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3091 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3092 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3093 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3094 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3095 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3096 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3097 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3098 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3099 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3100 3101 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3102 3103 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3104 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3105 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3106 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3107 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3108 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3109 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3110 3111 rtl_hw_aspm_clkreq_enable(tp, true); 3112 } 3113 3114 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3115 { 3116 static const struct ephy_info e_info_8168h_1[] = { 3117 { 0x1e, 0x0800, 0x0001 }, 3118 { 0x1d, 0x0000, 0x0800 }, 3119 { 0x05, 0xffff, 0x2089 }, 3120 { 0x06, 0xffff, 0x5881 }, 3121 { 0x04, 0xffff, 0x854a }, 3122 { 0x01, 0xffff, 0x068b } 3123 }; 3124 int rg_saw_cnt; 3125 3126 /* disable aspm and clock request before access ephy */ 3127 rtl_hw_aspm_clkreq_enable(tp, false); 3128 rtl_ephy_init(tp, e_info_8168h_1); 3129 3130 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3131 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3132 3133 rtl_set_def_aspm_entry_latency(tp); 3134 3135 rtl_reset_packet_filter(tp); 3136 3137 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3138 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3139 3140 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3141 3142 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3143 3144 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3145 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3146 3147 rtl8168_config_eee_mac(tp); 3148 3149 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3150 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3151 3152 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3153 3154 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3155 3156 rtl_pcie_state_l2l3_disable(tp); 3157 3158 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3159 if (rg_saw_cnt > 0) { 3160 u16 sw_cnt_1ms_ini; 3161 3162 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3163 sw_cnt_1ms_ini &= 0x0fff; 3164 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3165 } 3166 3167 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3168 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3169 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3170 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3171 3172 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3173 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3174 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3175 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3176 3177 rtl_hw_aspm_clkreq_enable(tp, true); 3178 } 3179 3180 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3181 { 3182 rtl8168ep_stop_cmac(tp); 3183 3184 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3185 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3186 3187 rtl_set_def_aspm_entry_latency(tp); 3188 3189 rtl_reset_packet_filter(tp); 3190 3191 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3192 3193 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3194 3195 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3196 3197 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3198 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3199 3200 rtl8168_config_eee_mac(tp); 3201 3202 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3203 3204 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3205 3206 rtl_pcie_state_l2l3_disable(tp); 3207 } 3208 3209 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3210 { 3211 static const struct ephy_info e_info_8168ep_1[] = { 3212 { 0x00, 0xffff, 0x10ab }, 3213 { 0x06, 0xffff, 0xf030 }, 3214 { 0x08, 0xffff, 0x2006 }, 3215 { 0x0d, 0xffff, 0x1666 }, 3216 { 0x0c, 0x3ff0, 0x0000 } 3217 }; 3218 3219 /* disable aspm and clock request before access ephy */ 3220 rtl_hw_aspm_clkreq_enable(tp, false); 3221 rtl_ephy_init(tp, e_info_8168ep_1); 3222 3223 rtl_hw_start_8168ep(tp); 3224 3225 rtl_hw_aspm_clkreq_enable(tp, true); 3226 } 3227 3228 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3229 { 3230 static const struct ephy_info e_info_8168ep_2[] = { 3231 { 0x00, 0xffff, 0x10a3 }, 3232 { 0x19, 0xffff, 0xfc00 }, 3233 { 0x1e, 0xffff, 0x20ea } 3234 }; 3235 3236 /* disable aspm and clock request before access ephy */ 3237 rtl_hw_aspm_clkreq_enable(tp, false); 3238 rtl_ephy_init(tp, e_info_8168ep_2); 3239 3240 rtl_hw_start_8168ep(tp); 3241 3242 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3243 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3244 3245 rtl_hw_aspm_clkreq_enable(tp, true); 3246 } 3247 3248 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3249 { 3250 static const struct ephy_info e_info_8168ep_3[] = { 3251 { 0x00, 0x0000, 0x0080 }, 3252 { 0x0d, 0x0100, 0x0200 }, 3253 { 0x19, 0x8021, 0x0000 }, 3254 { 0x1e, 0x0000, 0x2000 }, 3255 }; 3256 3257 /* disable aspm and clock request before access ephy */ 3258 rtl_hw_aspm_clkreq_enable(tp, false); 3259 rtl_ephy_init(tp, e_info_8168ep_3); 3260 3261 rtl_hw_start_8168ep(tp); 3262 3263 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3264 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3265 3266 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3267 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3268 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3269 3270 rtl_hw_aspm_clkreq_enable(tp, true); 3271 } 3272 3273 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3274 { 3275 static const struct ephy_info e_info_8117[] = { 3276 { 0x19, 0x0040, 0x1100 }, 3277 { 0x59, 0x0040, 0x1100 }, 3278 }; 3279 int rg_saw_cnt; 3280 3281 rtl8168ep_stop_cmac(tp); 3282 3283 /* disable aspm and clock request before access ephy */ 3284 rtl_hw_aspm_clkreq_enable(tp, false); 3285 rtl_ephy_init(tp, e_info_8117); 3286 3287 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3288 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3289 3290 rtl_set_def_aspm_entry_latency(tp); 3291 3292 rtl_reset_packet_filter(tp); 3293 3294 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3295 3296 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3297 3298 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3299 3300 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3301 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3302 3303 rtl8168_config_eee_mac(tp); 3304 3305 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3306 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3307 3308 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3309 3310 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3311 3312 rtl_pcie_state_l2l3_disable(tp); 3313 3314 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3315 if (rg_saw_cnt > 0) { 3316 u16 sw_cnt_1ms_ini; 3317 3318 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3319 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3320 } 3321 3322 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3323 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3324 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3325 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3326 3327 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3328 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3329 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3330 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3331 3332 /* firmware is for MAC only */ 3333 r8169_apply_firmware(tp); 3334 3335 rtl_hw_aspm_clkreq_enable(tp, true); 3336 } 3337 3338 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3339 { 3340 static const struct ephy_info e_info_8102e_1[] = { 3341 { 0x01, 0, 0x6e65 }, 3342 { 0x02, 0, 0x091f }, 3343 { 0x03, 0, 0xc2f9 }, 3344 { 0x06, 0, 0xafb5 }, 3345 { 0x07, 0, 0x0e00 }, 3346 { 0x19, 0, 0xec80 }, 3347 { 0x01, 0, 0x2e65 }, 3348 { 0x01, 0, 0x6e65 } 3349 }; 3350 u8 cfg1; 3351 3352 rtl_set_def_aspm_entry_latency(tp); 3353 3354 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3355 3356 RTL_W8(tp, Config1, 3357 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3358 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3359 3360 cfg1 = RTL_R8(tp, Config1); 3361 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3362 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3363 3364 rtl_ephy_init(tp, e_info_8102e_1); 3365 } 3366 3367 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3368 { 3369 rtl_set_def_aspm_entry_latency(tp); 3370 3371 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3372 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3373 } 3374 3375 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3376 { 3377 rtl_hw_start_8102e_2(tp); 3378 3379 rtl_ephy_write(tp, 0x03, 0xc2f9); 3380 } 3381 3382 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3383 { 3384 static const struct ephy_info e_info_8401[] = { 3385 { 0x01, 0xffff, 0x6fe5 }, 3386 { 0x03, 0xffff, 0x0599 }, 3387 { 0x06, 0xffff, 0xaf25 }, 3388 { 0x07, 0xffff, 0x8e68 }, 3389 }; 3390 3391 rtl_ephy_init(tp, e_info_8401); 3392 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3393 } 3394 3395 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3396 { 3397 static const struct ephy_info e_info_8105e_1[] = { 3398 { 0x07, 0, 0x4000 }, 3399 { 0x19, 0, 0x0200 }, 3400 { 0x19, 0, 0x0020 }, 3401 { 0x1e, 0, 0x2000 }, 3402 { 0x03, 0, 0x0001 }, 3403 { 0x19, 0, 0x0100 }, 3404 { 0x19, 0, 0x0004 }, 3405 { 0x0a, 0, 0x0020 } 3406 }; 3407 3408 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3409 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3410 3411 /* Disable Early Tally Counter */ 3412 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3413 3414 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3415 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3416 3417 rtl_ephy_init(tp, e_info_8105e_1); 3418 3419 rtl_pcie_state_l2l3_disable(tp); 3420 } 3421 3422 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3423 { 3424 rtl_hw_start_8105e_1(tp); 3425 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3426 } 3427 3428 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3429 { 3430 static const struct ephy_info e_info_8402[] = { 3431 { 0x19, 0xffff, 0xff64 }, 3432 { 0x1e, 0, 0x4000 } 3433 }; 3434 3435 rtl_set_def_aspm_entry_latency(tp); 3436 3437 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3438 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3439 3440 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3441 3442 rtl_ephy_init(tp, e_info_8402); 3443 3444 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3445 rtl_reset_packet_filter(tp); 3446 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3447 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3448 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3449 3450 /* disable EEE */ 3451 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3452 3453 rtl_pcie_state_l2l3_disable(tp); 3454 } 3455 3456 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3457 { 3458 rtl_hw_aspm_clkreq_enable(tp, false); 3459 3460 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3461 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3462 3463 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3464 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3465 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3466 3467 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3468 3469 /* disable EEE */ 3470 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3471 3472 rtl_pcie_state_l2l3_disable(tp); 3473 rtl_hw_aspm_clkreq_enable(tp, true); 3474 } 3475 3476 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3477 { 3478 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3479 } 3480 3481 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3482 { 3483 rtl_pcie_state_l2l3_disable(tp); 3484 3485 RTL_W16(tp, 0x382, 0x221b); 3486 RTL_W8(tp, 0x4500, 0); 3487 RTL_W16(tp, 0x4800, 0); 3488 3489 /* disable UPS */ 3490 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3491 3492 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3493 3494 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3495 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3496 3497 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3498 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3499 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3500 3501 /* disable new tx descriptor format */ 3502 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3503 3504 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3505 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3506 else 3507 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3508 3509 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3510 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3511 else 3512 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3513 3514 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3515 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3516 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3517 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3518 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3519 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3520 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3521 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3522 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3523 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3524 3525 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3526 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3527 udelay(1); 3528 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3529 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3530 3531 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3532 3533 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3534 3535 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3536 rtl8125b_config_eee_mac(tp); 3537 else 3538 rtl8125a_config_eee_mac(tp); 3539 3540 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3541 udelay(10); 3542 } 3543 3544 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3545 { 3546 static const struct ephy_info e_info_8125a_1[] = { 3547 { 0x01, 0xffff, 0xa812 }, 3548 { 0x09, 0xffff, 0x520c }, 3549 { 0x04, 0xffff, 0xd000 }, 3550 { 0x0d, 0xffff, 0xf702 }, 3551 { 0x0a, 0xffff, 0x8653 }, 3552 { 0x06, 0xffff, 0x001e }, 3553 { 0x08, 0xffff, 0x3595 }, 3554 { 0x20, 0xffff, 0x9455 }, 3555 { 0x21, 0xffff, 0x99ff }, 3556 { 0x02, 0xffff, 0x6046 }, 3557 { 0x29, 0xffff, 0xfe00 }, 3558 { 0x23, 0xffff, 0xab62 }, 3559 3560 { 0x41, 0xffff, 0xa80c }, 3561 { 0x49, 0xffff, 0x520c }, 3562 { 0x44, 0xffff, 0xd000 }, 3563 { 0x4d, 0xffff, 0xf702 }, 3564 { 0x4a, 0xffff, 0x8653 }, 3565 { 0x46, 0xffff, 0x001e }, 3566 { 0x48, 0xffff, 0x3595 }, 3567 { 0x60, 0xffff, 0x9455 }, 3568 { 0x61, 0xffff, 0x99ff }, 3569 { 0x42, 0xffff, 0x6046 }, 3570 { 0x69, 0xffff, 0xfe00 }, 3571 { 0x63, 0xffff, 0xab62 }, 3572 }; 3573 3574 rtl_set_def_aspm_entry_latency(tp); 3575 3576 /* disable aspm and clock request before access ephy */ 3577 rtl_hw_aspm_clkreq_enable(tp, false); 3578 rtl_ephy_init(tp, e_info_8125a_1); 3579 3580 rtl_hw_start_8125_common(tp); 3581 rtl_hw_aspm_clkreq_enable(tp, true); 3582 } 3583 3584 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3585 { 3586 static const struct ephy_info e_info_8125a_2[] = { 3587 { 0x04, 0xffff, 0xd000 }, 3588 { 0x0a, 0xffff, 0x8653 }, 3589 { 0x23, 0xffff, 0xab66 }, 3590 { 0x20, 0xffff, 0x9455 }, 3591 { 0x21, 0xffff, 0x99ff }, 3592 { 0x29, 0xffff, 0xfe04 }, 3593 3594 { 0x44, 0xffff, 0xd000 }, 3595 { 0x4a, 0xffff, 0x8653 }, 3596 { 0x63, 0xffff, 0xab66 }, 3597 { 0x60, 0xffff, 0x9455 }, 3598 { 0x61, 0xffff, 0x99ff }, 3599 { 0x69, 0xffff, 0xfe04 }, 3600 }; 3601 3602 rtl_set_def_aspm_entry_latency(tp); 3603 3604 /* disable aspm and clock request before access ephy */ 3605 rtl_hw_aspm_clkreq_enable(tp, false); 3606 rtl_ephy_init(tp, e_info_8125a_2); 3607 3608 rtl_hw_start_8125_common(tp); 3609 rtl_hw_aspm_clkreq_enable(tp, true); 3610 } 3611 3612 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3613 { 3614 static const struct ephy_info e_info_8125b[] = { 3615 { 0x0b, 0xffff, 0xa908 }, 3616 { 0x1e, 0xffff, 0x20eb }, 3617 { 0x4b, 0xffff, 0xa908 }, 3618 { 0x5e, 0xffff, 0x20eb }, 3619 { 0x22, 0x0030, 0x0020 }, 3620 { 0x62, 0x0030, 0x0020 }, 3621 }; 3622 3623 rtl_set_def_aspm_entry_latency(tp); 3624 rtl_hw_aspm_clkreq_enable(tp, false); 3625 3626 rtl_ephy_init(tp, e_info_8125b); 3627 rtl_hw_start_8125_common(tp); 3628 3629 rtl_hw_aspm_clkreq_enable(tp, true); 3630 } 3631 3632 static void rtl_hw_config(struct rtl8169_private *tp) 3633 { 3634 static const rtl_generic_fct hw_configs[] = { 3635 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3636 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3637 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3638 [RTL_GIGA_MAC_VER_10] = NULL, 3639 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3640 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3641 [RTL_GIGA_MAC_VER_13] = NULL, 3642 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3643 [RTL_GIGA_MAC_VER_16] = NULL, 3644 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3645 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3646 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3647 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3648 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3649 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3650 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3651 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3652 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3653 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3654 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3655 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3656 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3657 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3658 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3659 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3660 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3661 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3662 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3663 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3664 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3665 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3666 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3667 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3668 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3669 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3670 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3671 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3672 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3673 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3674 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3675 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3676 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3677 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3678 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3679 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3680 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3681 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3682 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3683 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3684 }; 3685 3686 if (hw_configs[tp->mac_version]) 3687 hw_configs[tp->mac_version](tp); 3688 } 3689 3690 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3691 { 3692 int i; 3693 3694 /* disable interrupt coalescing */ 3695 for (i = 0xa00; i < 0xb00; i += 4) 3696 RTL_W32(tp, i, 0); 3697 3698 rtl_hw_config(tp); 3699 } 3700 3701 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3702 { 3703 if (rtl_is_8168evl_up(tp)) 3704 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3705 else 3706 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3707 3708 rtl_hw_config(tp); 3709 3710 /* disable interrupt coalescing */ 3711 RTL_W16(tp, IntrMitigate, 0x0000); 3712 } 3713 3714 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3715 { 3716 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3717 3718 tp->cp_cmd |= PCIMulRW; 3719 3720 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3721 tp->mac_version == RTL_GIGA_MAC_VER_03) 3722 tp->cp_cmd |= EnAnaPLL; 3723 3724 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3725 3726 rtl8169_set_magic_reg(tp); 3727 3728 /* disable interrupt coalescing */ 3729 RTL_W16(tp, IntrMitigate, 0x0000); 3730 } 3731 3732 static void rtl_hw_start(struct rtl8169_private *tp) 3733 { 3734 rtl_unlock_config_regs(tp); 3735 3736 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3737 3738 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3739 rtl_hw_start_8169(tp); 3740 else if (rtl_is_8125(tp)) 3741 rtl_hw_start_8125(tp); 3742 else 3743 rtl_hw_start_8168(tp); 3744 3745 rtl_set_rx_max_size(tp); 3746 rtl_set_rx_tx_desc_registers(tp); 3747 rtl_lock_config_regs(tp); 3748 3749 rtl_jumbo_config(tp); 3750 3751 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3752 rtl_pci_commit(tp); 3753 3754 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3755 rtl_init_rxcfg(tp); 3756 rtl_set_tx_config_registers(tp); 3757 rtl_set_rx_config_features(tp, tp->dev->features); 3758 rtl_set_rx_mode(tp->dev); 3759 rtl_irq_enable(tp); 3760 } 3761 3762 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3763 { 3764 struct rtl8169_private *tp = netdev_priv(dev); 3765 3766 dev->mtu = new_mtu; 3767 netdev_update_features(dev); 3768 rtl_jumbo_config(tp); 3769 3770 switch (tp->mac_version) { 3771 case RTL_GIGA_MAC_VER_61: 3772 case RTL_GIGA_MAC_VER_63: 3773 rtl8125_set_eee_txidle_timer(tp); 3774 break; 3775 default: 3776 break; 3777 } 3778 3779 return 0; 3780 } 3781 3782 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3783 { 3784 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3785 3786 desc->opts2 = 0; 3787 /* Force memory writes to complete before releasing descriptor */ 3788 dma_wmb(); 3789 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3790 } 3791 3792 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3793 struct RxDesc *desc) 3794 { 3795 struct device *d = tp_to_dev(tp); 3796 int node = dev_to_node(d); 3797 dma_addr_t mapping; 3798 struct page *data; 3799 3800 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3801 if (!data) 3802 return NULL; 3803 3804 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3805 if (unlikely(dma_mapping_error(d, mapping))) { 3806 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3807 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3808 return NULL; 3809 } 3810 3811 desc->addr = cpu_to_le64(mapping); 3812 rtl8169_mark_to_asic(desc); 3813 3814 return data; 3815 } 3816 3817 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3818 { 3819 int i; 3820 3821 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3822 dma_unmap_page(tp_to_dev(tp), 3823 le64_to_cpu(tp->RxDescArray[i].addr), 3824 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3825 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3826 tp->Rx_databuff[i] = NULL; 3827 tp->RxDescArray[i].addr = 0; 3828 tp->RxDescArray[i].opts1 = 0; 3829 } 3830 } 3831 3832 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3833 { 3834 int i; 3835 3836 for (i = 0; i < NUM_RX_DESC; i++) { 3837 struct page *data; 3838 3839 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3840 if (!data) { 3841 rtl8169_rx_clear(tp); 3842 return -ENOMEM; 3843 } 3844 tp->Rx_databuff[i] = data; 3845 } 3846 3847 /* mark as last descriptor in the ring */ 3848 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3849 3850 return 0; 3851 } 3852 3853 static int rtl8169_init_ring(struct rtl8169_private *tp) 3854 { 3855 rtl8169_init_ring_indexes(tp); 3856 3857 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3858 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3859 3860 return rtl8169_rx_fill(tp); 3861 } 3862 3863 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3864 { 3865 struct ring_info *tx_skb = tp->tx_skb + entry; 3866 struct TxDesc *desc = tp->TxDescArray + entry; 3867 3868 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3869 DMA_TO_DEVICE); 3870 memset(desc, 0, sizeof(*desc)); 3871 memset(tx_skb, 0, sizeof(*tx_skb)); 3872 } 3873 3874 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3875 unsigned int n) 3876 { 3877 unsigned int i; 3878 3879 for (i = 0; i < n; i++) { 3880 unsigned int entry = (start + i) % NUM_TX_DESC; 3881 struct ring_info *tx_skb = tp->tx_skb + entry; 3882 unsigned int len = tx_skb->len; 3883 3884 if (len) { 3885 struct sk_buff *skb = tx_skb->skb; 3886 3887 rtl8169_unmap_tx_skb(tp, entry); 3888 if (skb) 3889 dev_consume_skb_any(skb); 3890 } 3891 } 3892 } 3893 3894 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3895 { 3896 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3897 netdev_reset_queue(tp->dev); 3898 } 3899 3900 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3901 { 3902 napi_disable(&tp->napi); 3903 3904 /* Give a racing hard_start_xmit a few cycles to complete. */ 3905 synchronize_net(); 3906 3907 /* Disable interrupts */ 3908 rtl8169_irq_mask_and_ack(tp); 3909 3910 rtl_rx_close(tp); 3911 3912 if (going_down && tp->dev->wol_enabled) 3913 goto no_reset; 3914 3915 switch (tp->mac_version) { 3916 case RTL_GIGA_MAC_VER_27: 3917 case RTL_GIGA_MAC_VER_28: 3918 case RTL_GIGA_MAC_VER_31: 3919 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3920 break; 3921 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3922 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3923 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3924 break; 3925 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3926 rtl_enable_rxdvgate(tp); 3927 fsleep(2000); 3928 break; 3929 default: 3930 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3931 fsleep(100); 3932 break; 3933 } 3934 3935 rtl_hw_reset(tp); 3936 no_reset: 3937 rtl8169_tx_clear(tp); 3938 rtl8169_init_ring_indexes(tp); 3939 } 3940 3941 static void rtl_reset_work(struct rtl8169_private *tp) 3942 { 3943 int i; 3944 3945 netif_stop_queue(tp->dev); 3946 3947 rtl8169_cleanup(tp, false); 3948 3949 for (i = 0; i < NUM_RX_DESC; i++) 3950 rtl8169_mark_to_asic(tp->RxDescArray + i); 3951 3952 napi_enable(&tp->napi); 3953 rtl_hw_start(tp); 3954 } 3955 3956 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3957 { 3958 struct rtl8169_private *tp = netdev_priv(dev); 3959 3960 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3961 } 3962 3963 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3964 void *addr, unsigned int entry, bool desc_own) 3965 { 3966 struct TxDesc *txd = tp->TxDescArray + entry; 3967 struct device *d = tp_to_dev(tp); 3968 dma_addr_t mapping; 3969 u32 opts1; 3970 int ret; 3971 3972 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3973 ret = dma_mapping_error(d, mapping); 3974 if (unlikely(ret)) { 3975 if (net_ratelimit()) 3976 netdev_err(tp->dev, "Failed to map TX data!\n"); 3977 return ret; 3978 } 3979 3980 txd->addr = cpu_to_le64(mapping); 3981 txd->opts2 = cpu_to_le32(opts[1]); 3982 3983 opts1 = opts[0] | len; 3984 if (entry == NUM_TX_DESC - 1) 3985 opts1 |= RingEnd; 3986 if (desc_own) 3987 opts1 |= DescOwn; 3988 txd->opts1 = cpu_to_le32(opts1); 3989 3990 tp->tx_skb[entry].len = len; 3991 3992 return 0; 3993 } 3994 3995 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3996 const u32 *opts, unsigned int entry) 3997 { 3998 struct skb_shared_info *info = skb_shinfo(skb); 3999 unsigned int cur_frag; 4000 4001 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4002 const skb_frag_t *frag = info->frags + cur_frag; 4003 void *addr = skb_frag_address(frag); 4004 u32 len = skb_frag_size(frag); 4005 4006 entry = (entry + 1) % NUM_TX_DESC; 4007 4008 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4009 goto err_out; 4010 } 4011 4012 return 0; 4013 4014 err_out: 4015 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4016 return -EIO; 4017 } 4018 4019 static bool rtl_skb_is_udp(struct sk_buff *skb) 4020 { 4021 int no = skb_network_offset(skb); 4022 struct ipv6hdr *i6h, _i6h; 4023 struct iphdr *ih, _ih; 4024 4025 switch (vlan_get_protocol(skb)) { 4026 case htons(ETH_P_IP): 4027 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4028 return ih && ih->protocol == IPPROTO_UDP; 4029 case htons(ETH_P_IPV6): 4030 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4031 return i6h && i6h->nexthdr == IPPROTO_UDP; 4032 default: 4033 return false; 4034 } 4035 } 4036 4037 #define RTL_MIN_PATCH_LEN 47 4038 4039 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4040 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4041 struct sk_buff *skb) 4042 { 4043 unsigned int padto = 0, len = skb->len; 4044 4045 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4046 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4047 unsigned int trans_data_len = skb_tail_pointer(skb) - 4048 skb_transport_header(skb); 4049 4050 if (trans_data_len >= offsetof(struct udphdr, len) && 4051 trans_data_len < RTL_MIN_PATCH_LEN) { 4052 u16 dest = ntohs(udp_hdr(skb)->dest); 4053 4054 /* dest is a standard PTP port */ 4055 if (dest == 319 || dest == 320) 4056 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4057 } 4058 4059 if (trans_data_len < sizeof(struct udphdr)) 4060 padto = max_t(unsigned int, padto, 4061 len + sizeof(struct udphdr) - trans_data_len); 4062 } 4063 4064 return padto; 4065 } 4066 4067 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4068 struct sk_buff *skb) 4069 { 4070 unsigned int padto; 4071 4072 padto = rtl8125_quirk_udp_padto(tp, skb); 4073 4074 switch (tp->mac_version) { 4075 case RTL_GIGA_MAC_VER_34: 4076 case RTL_GIGA_MAC_VER_60: 4077 case RTL_GIGA_MAC_VER_61: 4078 case RTL_GIGA_MAC_VER_63: 4079 padto = max_t(unsigned int, padto, ETH_ZLEN); 4080 default: 4081 break; 4082 } 4083 4084 return padto; 4085 } 4086 4087 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4088 { 4089 u32 mss = skb_shinfo(skb)->gso_size; 4090 4091 if (mss) { 4092 opts[0] |= TD_LSO; 4093 opts[0] |= mss << TD0_MSS_SHIFT; 4094 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4095 const struct iphdr *ip = ip_hdr(skb); 4096 4097 if (ip->protocol == IPPROTO_TCP) 4098 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4099 else if (ip->protocol == IPPROTO_UDP) 4100 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4101 else 4102 WARN_ON_ONCE(1); 4103 } 4104 } 4105 4106 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4107 struct sk_buff *skb, u32 *opts) 4108 { 4109 u32 transport_offset = (u32)skb_transport_offset(skb); 4110 struct skb_shared_info *shinfo = skb_shinfo(skb); 4111 u32 mss = shinfo->gso_size; 4112 4113 if (mss) { 4114 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4115 opts[0] |= TD1_GTSENV4; 4116 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4117 if (skb_cow_head(skb, 0)) 4118 return false; 4119 4120 tcp_v6_gso_csum_prep(skb); 4121 opts[0] |= TD1_GTSENV6; 4122 } else { 4123 WARN_ON_ONCE(1); 4124 } 4125 4126 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4127 opts[1] |= mss << TD1_MSS_SHIFT; 4128 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4129 u8 ip_protocol; 4130 4131 switch (vlan_get_protocol(skb)) { 4132 case htons(ETH_P_IP): 4133 opts[1] |= TD1_IPv4_CS; 4134 ip_protocol = ip_hdr(skb)->protocol; 4135 break; 4136 4137 case htons(ETH_P_IPV6): 4138 opts[1] |= TD1_IPv6_CS; 4139 ip_protocol = ipv6_hdr(skb)->nexthdr; 4140 break; 4141 4142 default: 4143 ip_protocol = IPPROTO_RAW; 4144 break; 4145 } 4146 4147 if (ip_protocol == IPPROTO_TCP) 4148 opts[1] |= TD1_TCP_CS; 4149 else if (ip_protocol == IPPROTO_UDP) 4150 opts[1] |= TD1_UDP_CS; 4151 else 4152 WARN_ON_ONCE(1); 4153 4154 opts[1] |= transport_offset << TCPHO_SHIFT; 4155 } else { 4156 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4157 4158 /* skb_padto would free the skb on error */ 4159 return !__skb_put_padto(skb, padto, false); 4160 } 4161 4162 return true; 4163 } 4164 4165 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4166 { 4167 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4168 - READ_ONCE(tp->cur_tx); 4169 4170 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4171 return slots_avail > MAX_SKB_FRAGS; 4172 } 4173 4174 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4175 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4176 { 4177 switch (tp->mac_version) { 4178 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4179 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4180 return false; 4181 default: 4182 return true; 4183 } 4184 } 4185 4186 static void rtl8169_doorbell(struct rtl8169_private *tp) 4187 { 4188 if (rtl_is_8125(tp)) 4189 RTL_W16(tp, TxPoll_8125, BIT(0)); 4190 else 4191 RTL_W8(tp, TxPoll, NPQ); 4192 } 4193 4194 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4195 struct net_device *dev) 4196 { 4197 unsigned int frags = skb_shinfo(skb)->nr_frags; 4198 struct rtl8169_private *tp = netdev_priv(dev); 4199 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4200 struct TxDesc *txd_first, *txd_last; 4201 bool stop_queue, door_bell; 4202 u32 opts[2]; 4203 4204 if (unlikely(!rtl_tx_slots_avail(tp))) { 4205 if (net_ratelimit()) 4206 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4207 goto err_stop_0; 4208 } 4209 4210 opts[1] = rtl8169_tx_vlan_tag(skb); 4211 opts[0] = 0; 4212 4213 if (!rtl_chip_supports_csum_v2(tp)) 4214 rtl8169_tso_csum_v1(skb, opts); 4215 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4216 goto err_dma_0; 4217 4218 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4219 entry, false))) 4220 goto err_dma_0; 4221 4222 txd_first = tp->TxDescArray + entry; 4223 4224 if (frags) { 4225 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4226 goto err_dma_1; 4227 entry = (entry + frags) % NUM_TX_DESC; 4228 } 4229 4230 txd_last = tp->TxDescArray + entry; 4231 txd_last->opts1 |= cpu_to_le32(LastFrag); 4232 tp->tx_skb[entry].skb = skb; 4233 4234 skb_tx_timestamp(skb); 4235 4236 /* Force memory writes to complete before releasing descriptor */ 4237 dma_wmb(); 4238 4239 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4240 4241 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4242 4243 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4244 smp_wmb(); 4245 4246 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4247 4248 stop_queue = !rtl_tx_slots_avail(tp); 4249 if (unlikely(stop_queue)) { 4250 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4251 * not miss a ring update when it notices a stopped queue. 4252 */ 4253 smp_wmb(); 4254 netif_stop_queue(dev); 4255 /* Sync with rtl_tx: 4256 * - publish queue status and cur_tx ring index (write barrier) 4257 * - refresh dirty_tx ring index (read barrier). 4258 * May the current thread have a pessimistic view of the ring 4259 * status and forget to wake up queue, a racing rtl_tx thread 4260 * can't. 4261 */ 4262 smp_mb__after_atomic(); 4263 if (rtl_tx_slots_avail(tp)) 4264 netif_start_queue(dev); 4265 door_bell = true; 4266 } 4267 4268 if (door_bell) 4269 rtl8169_doorbell(tp); 4270 4271 return NETDEV_TX_OK; 4272 4273 err_dma_1: 4274 rtl8169_unmap_tx_skb(tp, entry); 4275 err_dma_0: 4276 dev_kfree_skb_any(skb); 4277 dev->stats.tx_dropped++; 4278 return NETDEV_TX_OK; 4279 4280 err_stop_0: 4281 netif_stop_queue(dev); 4282 dev->stats.tx_dropped++; 4283 return NETDEV_TX_BUSY; 4284 } 4285 4286 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4287 { 4288 struct skb_shared_info *info = skb_shinfo(skb); 4289 unsigned int nr_frags = info->nr_frags; 4290 4291 if (!nr_frags) 4292 return UINT_MAX; 4293 4294 return skb_frag_size(info->frags + nr_frags - 1); 4295 } 4296 4297 /* Workaround for hw issues with TSO on RTL8168evl */ 4298 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4299 netdev_features_t features) 4300 { 4301 /* IPv4 header has options field */ 4302 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4303 ip_hdrlen(skb) > sizeof(struct iphdr)) 4304 features &= ~NETIF_F_ALL_TSO; 4305 4306 /* IPv4 TCP header has options field */ 4307 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4308 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4309 features &= ~NETIF_F_ALL_TSO; 4310 4311 else if (rtl_last_frag_len(skb) <= 6) 4312 features &= ~NETIF_F_ALL_TSO; 4313 4314 return features; 4315 } 4316 4317 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4318 struct net_device *dev, 4319 netdev_features_t features) 4320 { 4321 int transport_offset = skb_transport_offset(skb); 4322 struct rtl8169_private *tp = netdev_priv(dev); 4323 4324 if (skb_is_gso(skb)) { 4325 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4326 features = rtl8168evl_fix_tso(skb, features); 4327 4328 if (transport_offset > GTTCPHO_MAX && 4329 rtl_chip_supports_csum_v2(tp)) 4330 features &= ~NETIF_F_ALL_TSO; 4331 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4332 /* work around hw bug on some chip versions */ 4333 if (skb->len < ETH_ZLEN) 4334 features &= ~NETIF_F_CSUM_MASK; 4335 4336 if (rtl_quirk_packet_padto(tp, skb)) 4337 features &= ~NETIF_F_CSUM_MASK; 4338 4339 if (transport_offset > TCPHO_MAX && 4340 rtl_chip_supports_csum_v2(tp)) 4341 features &= ~NETIF_F_CSUM_MASK; 4342 } 4343 4344 return vlan_features_check(skb, features); 4345 } 4346 4347 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4348 { 4349 struct rtl8169_private *tp = netdev_priv(dev); 4350 struct pci_dev *pdev = tp->pci_dev; 4351 int pci_status_errs; 4352 u16 pci_cmd; 4353 4354 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4355 4356 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4357 4358 if (net_ratelimit()) 4359 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4360 pci_cmd, pci_status_errs); 4361 /* 4362 * The recovery sequence below admits a very elaborated explanation: 4363 * - it seems to work; 4364 * - I did not see what else could be done; 4365 * - it makes iop3xx happy. 4366 * 4367 * Feel free to adjust to your needs. 4368 */ 4369 if (pdev->broken_parity_status) 4370 pci_cmd &= ~PCI_COMMAND_PARITY; 4371 else 4372 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4373 4374 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4375 4376 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4377 } 4378 4379 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4380 int budget) 4381 { 4382 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4383 struct sk_buff *skb; 4384 4385 dirty_tx = tp->dirty_tx; 4386 4387 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4388 unsigned int entry = dirty_tx % NUM_TX_DESC; 4389 u32 status; 4390 4391 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4392 if (status & DescOwn) 4393 break; 4394 4395 skb = tp->tx_skb[entry].skb; 4396 rtl8169_unmap_tx_skb(tp, entry); 4397 4398 if (skb) { 4399 pkts_compl++; 4400 bytes_compl += skb->len; 4401 napi_consume_skb(skb, budget); 4402 } 4403 dirty_tx++; 4404 } 4405 4406 if (tp->dirty_tx != dirty_tx) { 4407 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4408 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4409 4410 /* Sync with rtl8169_start_xmit: 4411 * - publish dirty_tx ring index (write barrier) 4412 * - refresh cur_tx ring index and queue status (read barrier) 4413 * May the current thread miss the stopped queue condition, 4414 * a racing xmit thread can only have a right view of the 4415 * ring status. 4416 */ 4417 smp_store_mb(tp->dirty_tx, dirty_tx); 4418 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4419 netif_wake_queue(dev); 4420 /* 4421 * 8168 hack: TxPoll requests are lost when the Tx packets are 4422 * too close. Let's kick an extra TxPoll request when a burst 4423 * of start_xmit activity is detected (if it is not detected, 4424 * it is slow enough). -- FR 4425 * If skb is NULL then we come here again once a tx irq is 4426 * triggered after the last fragment is marked transmitted. 4427 */ 4428 if (tp->cur_tx != dirty_tx && skb) 4429 rtl8169_doorbell(tp); 4430 } 4431 } 4432 4433 static inline int rtl8169_fragmented_frame(u32 status) 4434 { 4435 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4436 } 4437 4438 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4439 { 4440 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4441 4442 if (status == RxProtoTCP || status == RxProtoUDP) 4443 skb->ip_summed = CHECKSUM_UNNECESSARY; 4444 else 4445 skb_checksum_none_assert(skb); 4446 } 4447 4448 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4449 { 4450 struct device *d = tp_to_dev(tp); 4451 int count; 4452 4453 for (count = 0; count < budget; count++, tp->cur_rx++) { 4454 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4455 struct RxDesc *desc = tp->RxDescArray + entry; 4456 struct sk_buff *skb; 4457 const void *rx_buf; 4458 dma_addr_t addr; 4459 u32 status; 4460 4461 status = le32_to_cpu(desc->opts1); 4462 if (status & DescOwn) 4463 break; 4464 4465 /* This barrier is needed to keep us from reading 4466 * any other fields out of the Rx descriptor until 4467 * we know the status of DescOwn 4468 */ 4469 dma_rmb(); 4470 4471 if (unlikely(status & RxRES)) { 4472 if (net_ratelimit()) 4473 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4474 status); 4475 dev->stats.rx_errors++; 4476 if (status & (RxRWT | RxRUNT)) 4477 dev->stats.rx_length_errors++; 4478 if (status & RxCRC) 4479 dev->stats.rx_crc_errors++; 4480 4481 if (!(dev->features & NETIF_F_RXALL)) 4482 goto release_descriptor; 4483 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4484 goto release_descriptor; 4485 } 4486 4487 pkt_size = status & GENMASK(13, 0); 4488 if (likely(!(dev->features & NETIF_F_RXFCS))) 4489 pkt_size -= ETH_FCS_LEN; 4490 4491 /* The driver does not support incoming fragmented frames. 4492 * They are seen as a symptom of over-mtu sized frames. 4493 */ 4494 if (unlikely(rtl8169_fragmented_frame(status))) { 4495 dev->stats.rx_dropped++; 4496 dev->stats.rx_length_errors++; 4497 goto release_descriptor; 4498 } 4499 4500 skb = napi_alloc_skb(&tp->napi, pkt_size); 4501 if (unlikely(!skb)) { 4502 dev->stats.rx_dropped++; 4503 goto release_descriptor; 4504 } 4505 4506 addr = le64_to_cpu(desc->addr); 4507 rx_buf = page_address(tp->Rx_databuff[entry]); 4508 4509 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4510 prefetch(rx_buf); 4511 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4512 skb->tail += pkt_size; 4513 skb->len = pkt_size; 4514 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4515 4516 rtl8169_rx_csum(skb, status); 4517 skb->protocol = eth_type_trans(skb, dev); 4518 4519 rtl8169_rx_vlan_tag(desc, skb); 4520 4521 if (skb->pkt_type == PACKET_MULTICAST) 4522 dev->stats.multicast++; 4523 4524 napi_gro_receive(&tp->napi, skb); 4525 4526 dev_sw_netstats_rx_add(dev, pkt_size); 4527 release_descriptor: 4528 rtl8169_mark_to_asic(desc); 4529 } 4530 4531 return count; 4532 } 4533 4534 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4535 { 4536 struct rtl8169_private *tp = dev_instance; 4537 u32 status = rtl_get_events(tp); 4538 4539 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4540 return IRQ_NONE; 4541 4542 if (unlikely(status & SYSErr)) { 4543 rtl8169_pcierr_interrupt(tp->dev); 4544 goto out; 4545 } 4546 4547 if (status & LinkChg) 4548 phy_mac_interrupt(tp->phydev); 4549 4550 if (unlikely(status & RxFIFOOver && 4551 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4552 netif_stop_queue(tp->dev); 4553 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4554 } 4555 4556 if (napi_schedule_prep(&tp->napi)) { 4557 rtl_irq_disable(tp); 4558 __napi_schedule(&tp->napi); 4559 } 4560 out: 4561 rtl_ack_events(tp, status); 4562 4563 return IRQ_HANDLED; 4564 } 4565 4566 static void rtl_task(struct work_struct *work) 4567 { 4568 struct rtl8169_private *tp = 4569 container_of(work, struct rtl8169_private, wk.work); 4570 4571 rtnl_lock(); 4572 4573 if (!netif_running(tp->dev) || 4574 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4575 goto out_unlock; 4576 4577 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4578 rtl_reset_work(tp); 4579 netif_wake_queue(tp->dev); 4580 } 4581 out_unlock: 4582 rtnl_unlock(); 4583 } 4584 4585 static int rtl8169_poll(struct napi_struct *napi, int budget) 4586 { 4587 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4588 struct net_device *dev = tp->dev; 4589 int work_done; 4590 4591 rtl_tx(dev, tp, budget); 4592 4593 work_done = rtl_rx(dev, tp, budget); 4594 4595 if (work_done < budget && napi_complete_done(napi, work_done)) 4596 rtl_irq_enable(tp); 4597 4598 return work_done; 4599 } 4600 4601 static void r8169_phylink_handler(struct net_device *ndev) 4602 { 4603 struct rtl8169_private *tp = netdev_priv(ndev); 4604 4605 if (netif_carrier_ok(ndev)) { 4606 rtl_link_chg_patch(tp); 4607 pm_request_resume(&tp->pci_dev->dev); 4608 } else { 4609 pm_runtime_idle(&tp->pci_dev->dev); 4610 } 4611 4612 if (net_ratelimit()) 4613 phy_print_status(tp->phydev); 4614 } 4615 4616 static int r8169_phy_connect(struct rtl8169_private *tp) 4617 { 4618 struct phy_device *phydev = tp->phydev; 4619 phy_interface_t phy_mode; 4620 int ret; 4621 4622 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4623 PHY_INTERFACE_MODE_MII; 4624 4625 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4626 phy_mode); 4627 if (ret) 4628 return ret; 4629 4630 if (!tp->supports_gmii) 4631 phy_set_max_speed(phydev, SPEED_100); 4632 4633 phy_support_asym_pause(phydev); 4634 4635 phy_attached_info(phydev); 4636 4637 return 0; 4638 } 4639 4640 static void rtl8169_down(struct rtl8169_private *tp) 4641 { 4642 /* Clear all task flags */ 4643 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4644 4645 phy_stop(tp->phydev); 4646 4647 rtl8169_update_counters(tp); 4648 4649 rtl8169_cleanup(tp, true); 4650 4651 rtl_prepare_power_down(tp); 4652 } 4653 4654 static void rtl8169_up(struct rtl8169_private *tp) 4655 { 4656 phy_resume(tp->phydev); 4657 rtl8169_init_phy(tp); 4658 napi_enable(&tp->napi); 4659 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4660 rtl_reset_work(tp); 4661 4662 phy_start(tp->phydev); 4663 } 4664 4665 static int rtl8169_close(struct net_device *dev) 4666 { 4667 struct rtl8169_private *tp = netdev_priv(dev); 4668 struct pci_dev *pdev = tp->pci_dev; 4669 4670 pm_runtime_get_sync(&pdev->dev); 4671 4672 netif_stop_queue(dev); 4673 rtl8169_down(tp); 4674 rtl8169_rx_clear(tp); 4675 4676 cancel_work_sync(&tp->wk.work); 4677 4678 free_irq(pci_irq_vector(pdev, 0), tp); 4679 4680 phy_disconnect(tp->phydev); 4681 4682 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4683 tp->RxPhyAddr); 4684 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4685 tp->TxPhyAddr); 4686 tp->TxDescArray = NULL; 4687 tp->RxDescArray = NULL; 4688 4689 pm_runtime_put_sync(&pdev->dev); 4690 4691 return 0; 4692 } 4693 4694 #ifdef CONFIG_NET_POLL_CONTROLLER 4695 static void rtl8169_netpoll(struct net_device *dev) 4696 { 4697 struct rtl8169_private *tp = netdev_priv(dev); 4698 4699 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4700 } 4701 #endif 4702 4703 static int rtl_open(struct net_device *dev) 4704 { 4705 struct rtl8169_private *tp = netdev_priv(dev); 4706 struct pci_dev *pdev = tp->pci_dev; 4707 unsigned long irqflags; 4708 int retval = -ENOMEM; 4709 4710 pm_runtime_get_sync(&pdev->dev); 4711 4712 /* 4713 * Rx and Tx descriptors needs 256 bytes alignment. 4714 * dma_alloc_coherent provides more. 4715 */ 4716 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4717 &tp->TxPhyAddr, GFP_KERNEL); 4718 if (!tp->TxDescArray) 4719 goto out; 4720 4721 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4722 &tp->RxPhyAddr, GFP_KERNEL); 4723 if (!tp->RxDescArray) 4724 goto err_free_tx_0; 4725 4726 retval = rtl8169_init_ring(tp); 4727 if (retval < 0) 4728 goto err_free_rx_1; 4729 4730 rtl_request_firmware(tp); 4731 4732 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4733 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt, 4734 irqflags, dev->name, tp); 4735 if (retval < 0) 4736 goto err_release_fw_2; 4737 4738 retval = r8169_phy_connect(tp); 4739 if (retval) 4740 goto err_free_irq; 4741 4742 rtl8169_up(tp); 4743 rtl8169_init_counter_offsets(tp); 4744 netif_start_queue(dev); 4745 out: 4746 pm_runtime_put_sync(&pdev->dev); 4747 4748 return retval; 4749 4750 err_free_irq: 4751 free_irq(pci_irq_vector(pdev, 0), tp); 4752 err_release_fw_2: 4753 rtl_release_firmware(tp); 4754 rtl8169_rx_clear(tp); 4755 err_free_rx_1: 4756 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4757 tp->RxPhyAddr); 4758 tp->RxDescArray = NULL; 4759 err_free_tx_0: 4760 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4761 tp->TxPhyAddr); 4762 tp->TxDescArray = NULL; 4763 goto out; 4764 } 4765 4766 static void 4767 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4768 { 4769 struct rtl8169_private *tp = netdev_priv(dev); 4770 struct pci_dev *pdev = tp->pci_dev; 4771 struct rtl8169_counters *counters = tp->counters; 4772 4773 pm_runtime_get_noresume(&pdev->dev); 4774 4775 netdev_stats_to_stats64(stats, &dev->stats); 4776 dev_fetch_sw_netstats(stats, dev->tstats); 4777 4778 /* 4779 * Fetch additional counter values missing in stats collected by driver 4780 * from tally counters. 4781 */ 4782 if (pm_runtime_active(&pdev->dev)) 4783 rtl8169_update_counters(tp); 4784 4785 /* 4786 * Subtract values fetched during initalization. 4787 * See rtl8169_init_counter_offsets for a description why we do that. 4788 */ 4789 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4790 le64_to_cpu(tp->tc_offset.tx_errors); 4791 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4792 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4793 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4794 le16_to_cpu(tp->tc_offset.tx_aborted); 4795 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4796 le16_to_cpu(tp->tc_offset.rx_missed); 4797 4798 pm_runtime_put_noidle(&pdev->dev); 4799 } 4800 4801 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4802 { 4803 netif_device_detach(tp->dev); 4804 4805 if (netif_running(tp->dev)) 4806 rtl8169_down(tp); 4807 } 4808 4809 #ifdef CONFIG_PM 4810 4811 static int rtl8169_runtime_resume(struct device *dev) 4812 { 4813 struct rtl8169_private *tp = dev_get_drvdata(dev); 4814 4815 rtl_rar_set(tp, tp->dev->dev_addr); 4816 __rtl8169_set_wol(tp, tp->saved_wolopts); 4817 4818 if (tp->TxDescArray) 4819 rtl8169_up(tp); 4820 4821 netif_device_attach(tp->dev); 4822 4823 return 0; 4824 } 4825 4826 static int __maybe_unused rtl8169_suspend(struct device *device) 4827 { 4828 struct rtl8169_private *tp = dev_get_drvdata(device); 4829 4830 rtnl_lock(); 4831 rtl8169_net_suspend(tp); 4832 if (!device_may_wakeup(tp_to_dev(tp))) 4833 clk_disable_unprepare(tp->clk); 4834 rtnl_unlock(); 4835 4836 return 0; 4837 } 4838 4839 static int __maybe_unused rtl8169_resume(struct device *device) 4840 { 4841 struct rtl8169_private *tp = dev_get_drvdata(device); 4842 4843 if (!device_may_wakeup(tp_to_dev(tp))) 4844 clk_prepare_enable(tp->clk); 4845 4846 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4847 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4848 rtl_init_rxcfg(tp); 4849 4850 return rtl8169_runtime_resume(device); 4851 } 4852 4853 static int rtl8169_runtime_suspend(struct device *device) 4854 { 4855 struct rtl8169_private *tp = dev_get_drvdata(device); 4856 4857 if (!tp->TxDescArray) { 4858 netif_device_detach(tp->dev); 4859 return 0; 4860 } 4861 4862 rtnl_lock(); 4863 __rtl8169_set_wol(tp, WAKE_PHY); 4864 rtl8169_net_suspend(tp); 4865 rtnl_unlock(); 4866 4867 return 0; 4868 } 4869 4870 static int rtl8169_runtime_idle(struct device *device) 4871 { 4872 struct rtl8169_private *tp = dev_get_drvdata(device); 4873 4874 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4875 pm_schedule_suspend(device, 10000); 4876 4877 return -EBUSY; 4878 } 4879 4880 static const struct dev_pm_ops rtl8169_pm_ops = { 4881 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4882 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4883 rtl8169_runtime_idle) 4884 }; 4885 4886 #endif /* CONFIG_PM */ 4887 4888 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4889 { 4890 /* WoL fails with 8168b when the receiver is disabled. */ 4891 switch (tp->mac_version) { 4892 case RTL_GIGA_MAC_VER_11: 4893 case RTL_GIGA_MAC_VER_12: 4894 case RTL_GIGA_MAC_VER_17: 4895 pci_clear_master(tp->pci_dev); 4896 4897 RTL_W8(tp, ChipCmd, CmdRxEnb); 4898 rtl_pci_commit(tp); 4899 break; 4900 default: 4901 break; 4902 } 4903 } 4904 4905 static void rtl_shutdown(struct pci_dev *pdev) 4906 { 4907 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4908 4909 rtnl_lock(); 4910 rtl8169_net_suspend(tp); 4911 rtnl_unlock(); 4912 4913 /* Restore original MAC address */ 4914 rtl_rar_set(tp, tp->dev->perm_addr); 4915 4916 if (system_state == SYSTEM_POWER_OFF) { 4917 if (tp->saved_wolopts) 4918 rtl_wol_shutdown_quirk(tp); 4919 4920 pci_wake_from_d3(pdev, tp->saved_wolopts); 4921 pci_set_power_state(pdev, PCI_D3hot); 4922 } 4923 } 4924 4925 static void rtl_remove_one(struct pci_dev *pdev) 4926 { 4927 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4928 4929 if (pci_dev_run_wake(pdev)) 4930 pm_runtime_get_noresume(&pdev->dev); 4931 4932 unregister_netdev(tp->dev); 4933 4934 if (tp->dash_type != RTL_DASH_NONE) 4935 rtl8168_driver_stop(tp); 4936 4937 rtl_release_firmware(tp); 4938 4939 /* restore original MAC address */ 4940 rtl_rar_set(tp, tp->dev->perm_addr); 4941 } 4942 4943 static const struct net_device_ops rtl_netdev_ops = { 4944 .ndo_open = rtl_open, 4945 .ndo_stop = rtl8169_close, 4946 .ndo_get_stats64 = rtl8169_get_stats64, 4947 .ndo_start_xmit = rtl8169_start_xmit, 4948 .ndo_features_check = rtl8169_features_check, 4949 .ndo_tx_timeout = rtl8169_tx_timeout, 4950 .ndo_validate_addr = eth_validate_addr, 4951 .ndo_change_mtu = rtl8169_change_mtu, 4952 .ndo_fix_features = rtl8169_fix_features, 4953 .ndo_set_features = rtl8169_set_features, 4954 .ndo_set_mac_address = rtl_set_mac_address, 4955 .ndo_do_ioctl = phy_do_ioctl_running, 4956 .ndo_set_rx_mode = rtl_set_rx_mode, 4957 #ifdef CONFIG_NET_POLL_CONTROLLER 4958 .ndo_poll_controller = rtl8169_netpoll, 4959 #endif 4960 4961 }; 4962 4963 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4964 { 4965 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4966 4967 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4968 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4969 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4970 /* special workaround needed */ 4971 tp->irq_mask |= RxFIFOOver; 4972 else 4973 tp->irq_mask |= RxOverflow; 4974 } 4975 4976 static int rtl_alloc_irq(struct rtl8169_private *tp) 4977 { 4978 unsigned int flags; 4979 4980 switch (tp->mac_version) { 4981 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4982 rtl_unlock_config_regs(tp); 4983 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4984 rtl_lock_config_regs(tp); 4985 fallthrough; 4986 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4987 flags = PCI_IRQ_LEGACY; 4988 break; 4989 default: 4990 flags = PCI_IRQ_ALL_TYPES; 4991 break; 4992 } 4993 4994 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4995 } 4996 4997 static void rtl_read_mac_address(struct rtl8169_private *tp, 4998 u8 mac_addr[ETH_ALEN]) 4999 { 5000 /* Get MAC address */ 5001 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5002 u32 value; 5003 5004 value = rtl_eri_read(tp, 0xe0); 5005 put_unaligned_le32(value, mac_addr); 5006 value = rtl_eri_read(tp, 0xe4); 5007 put_unaligned_le16(value, mac_addr + 4); 5008 } else if (rtl_is_8125(tp)) { 5009 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5010 } 5011 } 5012 5013 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5014 { 5015 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5016 } 5017 5018 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5019 { 5020 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5021 } 5022 5023 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5024 { 5025 struct rtl8169_private *tp = mii_bus->priv; 5026 5027 if (phyaddr > 0) 5028 return -ENODEV; 5029 5030 return rtl_readphy(tp, phyreg); 5031 } 5032 5033 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5034 int phyreg, u16 val) 5035 { 5036 struct rtl8169_private *tp = mii_bus->priv; 5037 5038 if (phyaddr > 0) 5039 return -ENODEV; 5040 5041 rtl_writephy(tp, phyreg, val); 5042 5043 return 0; 5044 } 5045 5046 static int r8169_mdio_register(struct rtl8169_private *tp) 5047 { 5048 struct pci_dev *pdev = tp->pci_dev; 5049 struct mii_bus *new_bus; 5050 int ret; 5051 5052 new_bus = devm_mdiobus_alloc(&pdev->dev); 5053 if (!new_bus) 5054 return -ENOMEM; 5055 5056 new_bus->name = "r8169"; 5057 new_bus->priv = tp; 5058 new_bus->parent = &pdev->dev; 5059 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5060 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5061 5062 new_bus->read = r8169_mdio_read_reg; 5063 new_bus->write = r8169_mdio_write_reg; 5064 5065 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5066 if (ret) 5067 return ret; 5068 5069 tp->phydev = mdiobus_get_phy(new_bus, 0); 5070 if (!tp->phydev) { 5071 return -ENODEV; 5072 } else if (!tp->phydev->drv) { 5073 /* Most chip versions fail with the genphy driver. 5074 * Therefore ensure that the dedicated PHY driver is loaded. 5075 */ 5076 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5077 tp->phydev->phy_id); 5078 return -EUNATCH; 5079 } 5080 5081 /* PHY will be woken up in rtl_open() */ 5082 phy_suspend(tp->phydev); 5083 5084 return 0; 5085 } 5086 5087 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5088 { 5089 rtl_enable_rxdvgate(tp); 5090 5091 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5092 msleep(1); 5093 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5094 5095 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5096 r8168g_wait_ll_share_fifo_ready(tp); 5097 5098 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5099 r8168g_wait_ll_share_fifo_ready(tp); 5100 } 5101 5102 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5103 { 5104 rtl_enable_rxdvgate(tp); 5105 5106 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5107 msleep(1); 5108 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5109 5110 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5111 r8168g_wait_ll_share_fifo_ready(tp); 5112 5113 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5114 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5115 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5116 r8168g_wait_ll_share_fifo_ready(tp); 5117 } 5118 5119 static void rtl_hw_initialize(struct rtl8169_private *tp) 5120 { 5121 switch (tp->mac_version) { 5122 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 5123 rtl8168ep_stop_cmac(tp); 5124 fallthrough; 5125 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5126 rtl_hw_init_8168g(tp); 5127 break; 5128 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5129 rtl_hw_init_8125(tp); 5130 break; 5131 default: 5132 break; 5133 } 5134 } 5135 5136 static int rtl_jumbo_max(struct rtl8169_private *tp) 5137 { 5138 /* Non-GBit versions don't support jumbo frames */ 5139 if (!tp->supports_gmii) 5140 return 0; 5141 5142 switch (tp->mac_version) { 5143 /* RTL8169 */ 5144 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5145 return JUMBO_7K; 5146 /* RTL8168b */ 5147 case RTL_GIGA_MAC_VER_11: 5148 case RTL_GIGA_MAC_VER_12: 5149 case RTL_GIGA_MAC_VER_17: 5150 return JUMBO_4K; 5151 /* RTL8168c */ 5152 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5153 return JUMBO_6K; 5154 default: 5155 return JUMBO_9K; 5156 } 5157 } 5158 5159 static void rtl_disable_clk(void *data) 5160 { 5161 clk_disable_unprepare(data); 5162 } 5163 5164 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5165 { 5166 struct device *d = tp_to_dev(tp); 5167 struct clk *clk; 5168 int rc; 5169 5170 clk = devm_clk_get(d, "ether_clk"); 5171 if (IS_ERR(clk)) { 5172 rc = PTR_ERR(clk); 5173 if (rc == -ENOENT) 5174 /* clk-core allows NULL (for suspend / resume) */ 5175 rc = 0; 5176 else 5177 dev_err_probe(d, rc, "failed to get clk\n"); 5178 } else { 5179 tp->clk = clk; 5180 rc = clk_prepare_enable(clk); 5181 if (rc) 5182 dev_err(d, "failed to enable clk: %d\n", rc); 5183 else 5184 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5185 } 5186 5187 return rc; 5188 } 5189 5190 static void rtl_init_mac_address(struct rtl8169_private *tp) 5191 { 5192 struct net_device *dev = tp->dev; 5193 u8 *mac_addr = dev->dev_addr; 5194 int rc; 5195 5196 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5197 if (!rc) 5198 goto done; 5199 5200 rtl_read_mac_address(tp, mac_addr); 5201 if (is_valid_ether_addr(mac_addr)) 5202 goto done; 5203 5204 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5205 if (is_valid_ether_addr(mac_addr)) 5206 goto done; 5207 5208 eth_hw_addr_random(dev); 5209 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5210 done: 5211 rtl_rar_set(tp, mac_addr); 5212 } 5213 5214 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5215 { 5216 struct rtl8169_private *tp; 5217 int jumbo_max, region, rc; 5218 enum mac_version chipset; 5219 struct net_device *dev; 5220 u16 xid; 5221 5222 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5223 if (!dev) 5224 return -ENOMEM; 5225 5226 SET_NETDEV_DEV(dev, &pdev->dev); 5227 dev->netdev_ops = &rtl_netdev_ops; 5228 tp = netdev_priv(dev); 5229 tp->dev = dev; 5230 tp->pci_dev = pdev; 5231 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5232 tp->eee_adv = -1; 5233 tp->ocp_base = OCP_STD_PHY_BASE; 5234 5235 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5236 struct pcpu_sw_netstats); 5237 if (!dev->tstats) 5238 return -ENOMEM; 5239 5240 /* Get the *optional* external "ether_clk" used on some boards */ 5241 rc = rtl_get_ether_clk(tp); 5242 if (rc) 5243 return rc; 5244 5245 /* Disable ASPM completely as that cause random device stop working 5246 * problems as well as full system hangs for some PCIe devices users. 5247 */ 5248 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5249 PCIE_LINK_STATE_L1); 5250 tp->aspm_manageable = !rc; 5251 5252 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5253 rc = pcim_enable_device(pdev); 5254 if (rc < 0) { 5255 dev_err(&pdev->dev, "enable failure\n"); 5256 return rc; 5257 } 5258 5259 if (pcim_set_mwi(pdev) < 0) 5260 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5261 5262 /* use first MMIO region */ 5263 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5264 if (region < 0) { 5265 dev_err(&pdev->dev, "no MMIO resource found\n"); 5266 return -ENODEV; 5267 } 5268 5269 /* check for weird/broken PCI region reporting */ 5270 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5271 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5272 return -ENODEV; 5273 } 5274 5275 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5276 if (rc < 0) { 5277 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5278 return rc; 5279 } 5280 5281 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5282 5283 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5284 5285 /* Identify chip attached to board */ 5286 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5287 if (chipset == RTL_GIGA_MAC_NONE) { 5288 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5289 return -ENODEV; 5290 } 5291 5292 tp->mac_version = chipset; 5293 5294 tp->dash_type = rtl_check_dash(tp); 5295 5296 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5297 5298 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5299 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5300 dev->features |= NETIF_F_HIGHDMA; 5301 5302 rtl_init_rxcfg(tp); 5303 5304 rtl8169_irq_mask_and_ack(tp); 5305 5306 rtl_hw_initialize(tp); 5307 5308 rtl_hw_reset(tp); 5309 5310 pci_set_master(pdev); 5311 5312 rc = rtl_alloc_irq(tp); 5313 if (rc < 0) { 5314 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5315 return rc; 5316 } 5317 5318 INIT_WORK(&tp->wk.work, rtl_task); 5319 5320 rtl_init_mac_address(tp); 5321 5322 dev->ethtool_ops = &rtl8169_ethtool_ops; 5323 5324 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5325 5326 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5327 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5328 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5329 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5330 5331 /* 5332 * Pretend we are using VLANs; This bypasses a nasty bug where 5333 * Interrupts stop flowing on high load on 8110SCd controllers. 5334 */ 5335 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5336 /* Disallow toggling */ 5337 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5338 5339 if (rtl_chip_supports_csum_v2(tp)) 5340 dev->hw_features |= NETIF_F_IPV6_CSUM; 5341 5342 dev->features |= dev->hw_features; 5343 5344 /* There has been a number of reports that using SG/TSO results in 5345 * tx timeouts. However for a lot of people SG/TSO works fine. 5346 * Therefore disable both features by default, but allow users to 5347 * enable them. Use at own risk! 5348 */ 5349 if (rtl_chip_supports_csum_v2(tp)) { 5350 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5351 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5352 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5353 } else { 5354 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5355 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5356 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5357 } 5358 5359 dev->hw_features |= NETIF_F_RXALL; 5360 dev->hw_features |= NETIF_F_RXFCS; 5361 5362 /* configure chip for default features */ 5363 rtl8169_set_features(dev, dev->features); 5364 5365 rtl_set_d3_pll_down(tp, true); 5366 5367 jumbo_max = rtl_jumbo_max(tp); 5368 if (jumbo_max) 5369 dev->max_mtu = jumbo_max; 5370 5371 rtl_set_irq_mask(tp); 5372 5373 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5374 5375 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5376 &tp->counters_phys_addr, 5377 GFP_KERNEL); 5378 if (!tp->counters) 5379 return -ENOMEM; 5380 5381 pci_set_drvdata(pdev, tp); 5382 5383 rc = r8169_mdio_register(tp); 5384 if (rc) 5385 return rc; 5386 5387 rc = register_netdev(dev); 5388 if (rc) 5389 return rc; 5390 5391 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5392 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5393 pci_irq_vector(pdev, 0)); 5394 5395 if (jumbo_max) 5396 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5397 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5398 "ok" : "ko"); 5399 5400 if (tp->dash_type != RTL_DASH_NONE) { 5401 netdev_info(dev, "DASH enabled\n"); 5402 rtl8168_driver_start(tp); 5403 } 5404 5405 if (pci_dev_run_wake(pdev)) 5406 pm_runtime_put_sync(&pdev->dev); 5407 5408 return 0; 5409 } 5410 5411 static struct pci_driver rtl8169_pci_driver = { 5412 .name = MODULENAME, 5413 .id_table = rtl8169_pci_tbl, 5414 .probe = rtl_init_one, 5415 .remove = rtl_remove_one, 5416 .shutdown = rtl_shutdown, 5417 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5418 }; 5419 5420 module_pci_driver(rtl8169_pci_driver); 5421