1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 59 #define R8169_MSG_DEFAULT \ 60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 enum mac_version { 87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */ 88 RTL_GIGA_MAC_VER_02, 89 RTL_GIGA_MAC_VER_03, 90 RTL_GIGA_MAC_VER_04, 91 RTL_GIGA_MAC_VER_05, 92 RTL_GIGA_MAC_VER_06, 93 RTL_GIGA_MAC_VER_07, 94 RTL_GIGA_MAC_VER_08, 95 RTL_GIGA_MAC_VER_09, 96 RTL_GIGA_MAC_VER_10, 97 RTL_GIGA_MAC_VER_11, 98 RTL_GIGA_MAC_VER_12, 99 RTL_GIGA_MAC_VER_13, 100 RTL_GIGA_MAC_VER_14, 101 RTL_GIGA_MAC_VER_15, 102 RTL_GIGA_MAC_VER_16, 103 RTL_GIGA_MAC_VER_17, 104 RTL_GIGA_MAC_VER_18, 105 RTL_GIGA_MAC_VER_19, 106 RTL_GIGA_MAC_VER_20, 107 RTL_GIGA_MAC_VER_21, 108 RTL_GIGA_MAC_VER_22, 109 RTL_GIGA_MAC_VER_23, 110 RTL_GIGA_MAC_VER_24, 111 RTL_GIGA_MAC_VER_25, 112 RTL_GIGA_MAC_VER_26, 113 RTL_GIGA_MAC_VER_27, 114 RTL_GIGA_MAC_VER_28, 115 RTL_GIGA_MAC_VER_29, 116 RTL_GIGA_MAC_VER_30, 117 RTL_GIGA_MAC_VER_31, 118 RTL_GIGA_MAC_VER_32, 119 RTL_GIGA_MAC_VER_33, 120 RTL_GIGA_MAC_VER_34, 121 RTL_GIGA_MAC_VER_35, 122 RTL_GIGA_MAC_VER_36, 123 RTL_GIGA_MAC_VER_37, 124 RTL_GIGA_MAC_VER_38, 125 RTL_GIGA_MAC_VER_39, 126 RTL_GIGA_MAC_VER_40, 127 RTL_GIGA_MAC_VER_41, 128 RTL_GIGA_MAC_VER_42, 129 RTL_GIGA_MAC_VER_43, 130 RTL_GIGA_MAC_VER_44, 131 RTL_GIGA_MAC_VER_45, 132 RTL_GIGA_MAC_VER_46, 133 RTL_GIGA_MAC_VER_47, 134 RTL_GIGA_MAC_VER_48, 135 RTL_GIGA_MAC_VER_49, 136 RTL_GIGA_MAC_VER_50, 137 RTL_GIGA_MAC_VER_51, 138 RTL_GIGA_MAC_VER_60, 139 RTL_GIGA_MAC_VER_61, 140 RTL_GIGA_MAC_NONE 141 }; 142 143 #define JUMBO_1K ETH_DATA_LEN 144 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 145 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 146 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 147 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 148 149 static const struct { 150 const char *name; 151 const char *fw_name; 152 } rtl_chip_infos[] = { 153 /* PCI devices. */ 154 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 155 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 156 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 157 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 158 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 159 /* PCI-E devices. */ 160 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 161 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 162 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 163 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 164 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 165 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 166 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 167 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 168 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 169 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 170 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 171 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 172 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 173 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 174 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 175 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 176 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 177 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 178 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 179 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 180 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 181 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 182 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 183 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 184 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 185 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 186 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 187 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 188 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 189 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 190 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 191 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 192 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 193 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 194 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 195 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 196 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 197 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 198 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 199 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 200 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 201 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 202 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 203 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 204 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 205 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 206 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 207 }; 208 209 static const struct pci_device_id rtl8169_pci_tbl[] = { 210 { PCI_VDEVICE(REALTEK, 0x2502) }, 211 { PCI_VDEVICE(REALTEK, 0x2600) }, 212 { PCI_VDEVICE(REALTEK, 0x8129) }, 213 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 214 { PCI_VDEVICE(REALTEK, 0x8161) }, 215 { PCI_VDEVICE(REALTEK, 0x8167) }, 216 { PCI_VDEVICE(REALTEK, 0x8168) }, 217 { PCI_VDEVICE(NCUBE, 0x8168) }, 218 { PCI_VDEVICE(REALTEK, 0x8169) }, 219 { PCI_VENDOR_ID_DLINK, 0x4300, 220 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 221 { PCI_VDEVICE(DLINK, 0x4300) }, 222 { PCI_VDEVICE(DLINK, 0x4302) }, 223 { PCI_VDEVICE(AT, 0xc107) }, 224 { PCI_VDEVICE(USR, 0x0116) }, 225 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 226 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 227 { PCI_VDEVICE(REALTEK, 0x8125) }, 228 { PCI_VDEVICE(REALTEK, 0x3000) }, 229 {} 230 }; 231 232 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 233 234 static struct { 235 u32 msg_enable; 236 } debug = { -1 }; 237 238 enum rtl_registers { 239 MAC0 = 0, /* Ethernet hardware address. */ 240 MAC4 = 4, 241 MAR0 = 8, /* Multicast filter. */ 242 CounterAddrLow = 0x10, 243 CounterAddrHigh = 0x14, 244 TxDescStartAddrLow = 0x20, 245 TxDescStartAddrHigh = 0x24, 246 TxHDescStartAddrLow = 0x28, 247 TxHDescStartAddrHigh = 0x2c, 248 FLASH = 0x30, 249 ERSR = 0x36, 250 ChipCmd = 0x37, 251 TxPoll = 0x38, 252 IntrMask = 0x3c, 253 IntrStatus = 0x3e, 254 255 TxConfig = 0x40, 256 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 257 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 258 259 RxConfig = 0x44, 260 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 261 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 262 #define RXCFG_FIFO_SHIFT 13 263 /* No threshold before first PCI xfer */ 264 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 265 #define RX_EARLY_OFF (1 << 11) 266 #define RXCFG_DMA_SHIFT 8 267 /* Unlimited maximum PCI burst. */ 268 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 269 270 RxMissed = 0x4c, 271 Cfg9346 = 0x50, 272 Config0 = 0x51, 273 Config1 = 0x52, 274 Config2 = 0x53, 275 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 276 277 Config3 = 0x54, 278 Config4 = 0x55, 279 Config5 = 0x56, 280 PHYAR = 0x60, 281 PHYstatus = 0x6c, 282 RxMaxSize = 0xda, 283 CPlusCmd = 0xe0, 284 IntrMitigate = 0xe2, 285 286 #define RTL_COALESCE_MASK 0x0f 287 #define RTL_COALESCE_SHIFT 4 288 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 289 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 290 291 RxDescAddrLow = 0xe4, 292 RxDescAddrHigh = 0xe8, 293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 294 295 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 296 297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 298 299 #define TxPacketMax (8064 >> 7) 300 #define EarlySize 0x27 301 302 FuncEvent = 0xf0, 303 FuncEventMask = 0xf4, 304 FuncPresetState = 0xf8, 305 IBCR0 = 0xf8, 306 IBCR2 = 0xf9, 307 IBIMR0 = 0xfa, 308 IBISR0 = 0xfb, 309 FuncForceEvent = 0xfc, 310 }; 311 312 enum rtl8168_8101_registers { 313 CSIDR = 0x64, 314 CSIAR = 0x68, 315 #define CSIAR_FLAG 0x80000000 316 #define CSIAR_WRITE_CMD 0x80000000 317 #define CSIAR_BYTE_ENABLE 0x0000f000 318 #define CSIAR_ADDR_MASK 0x00000fff 319 PMCH = 0x6f, 320 EPHYAR = 0x80, 321 #define EPHYAR_FLAG 0x80000000 322 #define EPHYAR_WRITE_CMD 0x80000000 323 #define EPHYAR_REG_MASK 0x1f 324 #define EPHYAR_REG_SHIFT 16 325 #define EPHYAR_DATA_MASK 0xffff 326 DLLPR = 0xd0, 327 #define PFM_EN (1 << 6) 328 #define TX_10M_PS_EN (1 << 7) 329 DBG_REG = 0xd1, 330 #define FIX_NAK_1 (1 << 4) 331 #define FIX_NAK_2 (1 << 3) 332 TWSI = 0xd2, 333 MCU = 0xd3, 334 #define NOW_IS_OOB (1 << 7) 335 #define TX_EMPTY (1 << 5) 336 #define RX_EMPTY (1 << 4) 337 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 338 #define EN_NDP (1 << 3) 339 #define EN_OOB_RESET (1 << 2) 340 #define LINK_LIST_RDY (1 << 1) 341 EFUSEAR = 0xdc, 342 #define EFUSEAR_FLAG 0x80000000 343 #define EFUSEAR_WRITE_CMD 0x80000000 344 #define EFUSEAR_READ_CMD 0x00000000 345 #define EFUSEAR_REG_MASK 0x03ff 346 #define EFUSEAR_REG_SHIFT 8 347 #define EFUSEAR_DATA_MASK 0xff 348 MISC_1 = 0xf2, 349 #define PFM_D3COLD_EN (1 << 6) 350 }; 351 352 enum rtl8168_registers { 353 LED_FREQ = 0x1a, 354 EEE_LED = 0x1b, 355 ERIDR = 0x70, 356 ERIAR = 0x74, 357 #define ERIAR_FLAG 0x80000000 358 #define ERIAR_WRITE_CMD 0x80000000 359 #define ERIAR_READ_CMD 0x00000000 360 #define ERIAR_ADDR_BYTE_ALIGN 4 361 #define ERIAR_TYPE_SHIFT 16 362 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 363 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 364 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 365 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 366 #define ERIAR_MASK_SHIFT 12 367 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 368 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 369 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 370 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 371 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 372 EPHY_RXER_NUM = 0x7c, 373 OCPDR = 0xb0, /* OCP GPHY access */ 374 #define OCPDR_WRITE_CMD 0x80000000 375 #define OCPDR_READ_CMD 0x00000000 376 #define OCPDR_REG_MASK 0x7f 377 #define OCPDR_GPHY_REG_SHIFT 16 378 #define OCPDR_DATA_MASK 0xffff 379 OCPAR = 0xb4, 380 #define OCPAR_FLAG 0x80000000 381 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 382 #define OCPAR_GPHY_READ_CMD 0x0000f060 383 GPHY_OCP = 0xb8, 384 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 385 MISC = 0xf0, /* 8168e only. */ 386 #define TXPLA_RST (1 << 29) 387 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 388 #define PWM_EN (1 << 22) 389 #define RXDV_GATED_EN (1 << 19) 390 #define EARLY_TALLY_EN (1 << 16) 391 }; 392 393 enum rtl8125_registers { 394 IntrMask_8125 = 0x38, 395 IntrStatus_8125 = 0x3c, 396 TxPoll_8125 = 0x90, 397 MAC0_BKP = 0x19e0, 398 }; 399 400 #define RX_VLAN_INNER_8125 BIT(22) 401 #define RX_VLAN_OUTER_8125 BIT(23) 402 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 403 404 #define RX_FETCH_DFLT_8125 (8 << 27) 405 406 enum rtl_register_content { 407 /* InterruptStatusBits */ 408 SYSErr = 0x8000, 409 PCSTimeout = 0x4000, 410 SWInt = 0x0100, 411 TxDescUnavail = 0x0080, 412 RxFIFOOver = 0x0040, 413 LinkChg = 0x0020, 414 RxOverflow = 0x0010, 415 TxErr = 0x0008, 416 TxOK = 0x0004, 417 RxErr = 0x0002, 418 RxOK = 0x0001, 419 420 /* RxStatusDesc */ 421 RxRWT = (1 << 22), 422 RxRES = (1 << 21), 423 RxRUNT = (1 << 20), 424 RxCRC = (1 << 19), 425 426 /* ChipCmdBits */ 427 StopReq = 0x80, 428 CmdReset = 0x10, 429 CmdRxEnb = 0x08, 430 CmdTxEnb = 0x04, 431 RxBufEmpty = 0x01, 432 433 /* TXPoll register p.5 */ 434 HPQ = 0x80, /* Poll cmd on the high prio queue */ 435 NPQ = 0x40, /* Poll cmd on the low prio queue */ 436 FSWInt = 0x01, /* Forced software interrupt */ 437 438 /* Cfg9346Bits */ 439 Cfg9346_Lock = 0x00, 440 Cfg9346_Unlock = 0xc0, 441 442 /* rx_mode_bits */ 443 AcceptErr = 0x20, 444 AcceptRunt = 0x10, 445 AcceptBroadcast = 0x08, 446 AcceptMulticast = 0x04, 447 AcceptMyPhys = 0x02, 448 AcceptAllPhys = 0x01, 449 #define RX_CONFIG_ACCEPT_MASK 0x3f 450 451 /* TxConfigBits */ 452 TxInterFrameGapShift = 24, 453 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 454 455 /* Config1 register p.24 */ 456 LEDS1 = (1 << 7), 457 LEDS0 = (1 << 6), 458 Speed_down = (1 << 4), 459 MEMMAP = (1 << 3), 460 IOMAP = (1 << 2), 461 VPD = (1 << 1), 462 PMEnable = (1 << 0), /* Power Management Enable */ 463 464 /* Config2 register p. 25 */ 465 ClkReqEn = (1 << 7), /* Clock Request Enable */ 466 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 467 PCI_Clock_66MHz = 0x01, 468 PCI_Clock_33MHz = 0x00, 469 470 /* Config3 register p.25 */ 471 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 472 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 473 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 474 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 475 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 476 477 /* Config4 register */ 478 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 479 480 /* Config5 register p.27 */ 481 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 482 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 483 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 484 Spi_en = (1 << 3), 485 LanWake = (1 << 1), /* LanWake enable/disable */ 486 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 487 ASPM_en = (1 << 0), /* ASPM enable */ 488 489 /* CPlusCmd p.31 */ 490 EnableBist = (1 << 15), // 8168 8101 491 Mac_dbgo_oe = (1 << 14), // 8168 8101 492 Normal_mode = (1 << 13), // unused 493 Force_half_dup = (1 << 12), // 8168 8101 494 Force_rxflow_en = (1 << 11), // 8168 8101 495 Force_txflow_en = (1 << 10), // 8168 8101 496 Cxpl_dbg_sel = (1 << 9), // 8168 8101 497 ASF = (1 << 8), // 8168 8101 498 PktCntrDisable = (1 << 7), // 8168 8101 499 Mac_dbgo_sel = 0x001c, // 8168 500 RxVlan = (1 << 6), 501 RxChkSum = (1 << 5), 502 PCIDAC = (1 << 4), 503 PCIMulRW = (1 << 3), 504 #define INTT_MASK GENMASK(1, 0) 505 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 506 507 /* rtl8169_PHYstatus */ 508 TBI_Enable = 0x80, 509 TxFlowCtrl = 0x40, 510 RxFlowCtrl = 0x20, 511 _1000bpsF = 0x10, 512 _100bps = 0x08, 513 _10bps = 0x04, 514 LinkStatus = 0x02, 515 FullDup = 0x01, 516 517 /* ResetCounterCommand */ 518 CounterReset = 0x1, 519 520 /* DumpCounterCommand */ 521 CounterDump = 0x8, 522 523 /* magic enable v2 */ 524 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 525 }; 526 527 enum rtl_desc_bit { 528 /* First doubleword. */ 529 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 530 RingEnd = (1 << 30), /* End of descriptor ring */ 531 FirstFrag = (1 << 29), /* First segment of a packet */ 532 LastFrag = (1 << 28), /* Final segment of a packet */ 533 }; 534 535 /* Generic case. */ 536 enum rtl_tx_desc_bit { 537 /* First doubleword. */ 538 TD_LSO = (1 << 27), /* Large Send Offload */ 539 #define TD_MSS_MAX 0x07ffu /* MSS value */ 540 541 /* Second doubleword. */ 542 TxVlanTag = (1 << 17), /* Add VLAN tag */ 543 }; 544 545 /* 8169, 8168b and 810x except 8102e. */ 546 enum rtl_tx_desc_bit_0 { 547 /* First doubleword. */ 548 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 549 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 550 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 551 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 552 }; 553 554 /* 8102e, 8168c and beyond. */ 555 enum rtl_tx_desc_bit_1 { 556 /* First doubleword. */ 557 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 558 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 559 #define GTTCPHO_SHIFT 18 560 #define GTTCPHO_MAX 0x7f 561 562 /* Second doubleword. */ 563 #define TCPHO_SHIFT 18 564 #define TCPHO_MAX 0x3ff 565 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 566 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 567 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 568 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 569 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 570 }; 571 572 enum rtl_rx_desc_bit { 573 /* Rx private */ 574 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 575 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 576 577 #define RxProtoUDP (PID1) 578 #define RxProtoTCP (PID0) 579 #define RxProtoIP (PID1 | PID0) 580 #define RxProtoMask RxProtoIP 581 582 IPFail = (1 << 16), /* IP checksum failed */ 583 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 584 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 585 RxVlanTag = (1 << 16), /* VLAN tag available */ 586 }; 587 588 #define RsvdMask 0x3fffc000 589 590 #define RTL_GSO_MAX_SIZE_V1 32000 591 #define RTL_GSO_MAX_SEGS_V1 24 592 #define RTL_GSO_MAX_SIZE_V2 64000 593 #define RTL_GSO_MAX_SEGS_V2 64 594 595 struct TxDesc { 596 __le32 opts1; 597 __le32 opts2; 598 __le64 addr; 599 }; 600 601 struct RxDesc { 602 __le32 opts1; 603 __le32 opts2; 604 __le64 addr; 605 }; 606 607 struct ring_info { 608 struct sk_buff *skb; 609 u32 len; 610 }; 611 612 struct rtl8169_counters { 613 __le64 tx_packets; 614 __le64 rx_packets; 615 __le64 tx_errors; 616 __le32 rx_errors; 617 __le16 rx_missed; 618 __le16 align_errors; 619 __le32 tx_one_collision; 620 __le32 tx_multi_collision; 621 __le64 rx_unicast; 622 __le64 rx_broadcast; 623 __le32 rx_multicast; 624 __le16 tx_aborted; 625 __le16 tx_underun; 626 }; 627 628 struct rtl8169_tc_offsets { 629 bool inited; 630 __le64 tx_errors; 631 __le32 tx_multi_collision; 632 __le16 tx_aborted; 633 }; 634 635 enum rtl_flag { 636 RTL_FLAG_TASK_ENABLED = 0, 637 RTL_FLAG_TASK_RESET_PENDING, 638 RTL_FLAG_MAX 639 }; 640 641 struct rtl8169_stats { 642 u64 packets; 643 u64 bytes; 644 struct u64_stats_sync syncp; 645 }; 646 647 struct rtl8169_private { 648 void __iomem *mmio_addr; /* memory map physical address */ 649 struct pci_dev *pci_dev; 650 struct net_device *dev; 651 struct phy_device *phydev; 652 struct napi_struct napi; 653 u32 msg_enable; 654 enum mac_version mac_version; 655 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 656 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 657 u32 dirty_tx; 658 struct rtl8169_stats rx_stats; 659 struct rtl8169_stats tx_stats; 660 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 661 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 662 dma_addr_t TxPhyAddr; 663 dma_addr_t RxPhyAddr; 664 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 665 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 666 u16 cp_cmd; 667 u32 irq_mask; 668 struct clk *clk; 669 670 struct { 671 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 672 struct mutex mutex; 673 struct work_struct work; 674 } wk; 675 676 unsigned irq_enabled:1; 677 unsigned supports_gmii:1; 678 unsigned aspm_manageable:1; 679 dma_addr_t counters_phys_addr; 680 struct rtl8169_counters *counters; 681 struct rtl8169_tc_offsets tc_offset; 682 u32 saved_wolopts; 683 684 const char *fw_name; 685 struct rtl_fw *rtl_fw; 686 687 u32 ocp_base; 688 }; 689 690 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 691 692 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 693 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 694 module_param_named(debug, debug.msg_enable, int, 0); 695 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 696 MODULE_SOFTDEP("pre: realtek"); 697 MODULE_LICENSE("GPL"); 698 MODULE_FIRMWARE(FIRMWARE_8168D_1); 699 MODULE_FIRMWARE(FIRMWARE_8168D_2); 700 MODULE_FIRMWARE(FIRMWARE_8168E_1); 701 MODULE_FIRMWARE(FIRMWARE_8168E_2); 702 MODULE_FIRMWARE(FIRMWARE_8168E_3); 703 MODULE_FIRMWARE(FIRMWARE_8105E_1); 704 MODULE_FIRMWARE(FIRMWARE_8168F_1); 705 MODULE_FIRMWARE(FIRMWARE_8168F_2); 706 MODULE_FIRMWARE(FIRMWARE_8402_1); 707 MODULE_FIRMWARE(FIRMWARE_8411_1); 708 MODULE_FIRMWARE(FIRMWARE_8411_2); 709 MODULE_FIRMWARE(FIRMWARE_8106E_1); 710 MODULE_FIRMWARE(FIRMWARE_8106E_2); 711 MODULE_FIRMWARE(FIRMWARE_8168G_2); 712 MODULE_FIRMWARE(FIRMWARE_8168G_3); 713 MODULE_FIRMWARE(FIRMWARE_8168H_1); 714 MODULE_FIRMWARE(FIRMWARE_8168H_2); 715 MODULE_FIRMWARE(FIRMWARE_8107E_1); 716 MODULE_FIRMWARE(FIRMWARE_8107E_2); 717 MODULE_FIRMWARE(FIRMWARE_8125A_3); 718 719 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 720 { 721 return &tp->pci_dev->dev; 722 } 723 724 static void rtl_lock_work(struct rtl8169_private *tp) 725 { 726 mutex_lock(&tp->wk.mutex); 727 } 728 729 static void rtl_unlock_work(struct rtl8169_private *tp) 730 { 731 mutex_unlock(&tp->wk.mutex); 732 } 733 734 static void rtl_lock_config_regs(struct rtl8169_private *tp) 735 { 736 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 737 } 738 739 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 740 { 741 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 742 } 743 744 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force) 745 { 746 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL, 747 PCI_EXP_DEVCTL_READRQ, force); 748 } 749 750 static bool rtl_is_8125(struct rtl8169_private *tp) 751 { 752 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 753 } 754 755 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 756 { 757 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 758 tp->mac_version != RTL_GIGA_MAC_VER_39 && 759 tp->mac_version <= RTL_GIGA_MAC_VER_51; 760 } 761 762 static bool rtl_supports_eee(struct rtl8169_private *tp) 763 { 764 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 765 tp->mac_version != RTL_GIGA_MAC_VER_37 && 766 tp->mac_version != RTL_GIGA_MAC_VER_39; 767 } 768 769 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 770 { 771 int i; 772 773 for (i = 0; i < ETH_ALEN; i++) 774 mac[i] = RTL_R8(tp, reg + i); 775 } 776 777 struct rtl_cond { 778 bool (*check)(struct rtl8169_private *); 779 const char *msg; 780 }; 781 782 static void rtl_udelay(unsigned int d) 783 { 784 udelay(d); 785 } 786 787 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 788 void (*delay)(unsigned int), unsigned int d, int n, 789 bool high) 790 { 791 int i; 792 793 for (i = 0; i < n; i++) { 794 if (c->check(tp) == high) 795 return true; 796 delay(d); 797 } 798 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 799 c->msg, !high, n, d); 800 return false; 801 } 802 803 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 804 const struct rtl_cond *c, 805 unsigned int d, int n) 806 { 807 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 808 } 809 810 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 811 const struct rtl_cond *c, 812 unsigned int d, int n) 813 { 814 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 815 } 816 817 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 818 const struct rtl_cond *c, 819 unsigned int d, int n) 820 { 821 return rtl_loop_wait(tp, c, msleep, d, n, true); 822 } 823 824 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 825 const struct rtl_cond *c, 826 unsigned int d, int n) 827 { 828 return rtl_loop_wait(tp, c, msleep, d, n, false); 829 } 830 831 #define DECLARE_RTL_COND(name) \ 832 static bool name ## _check(struct rtl8169_private *); \ 833 \ 834 static const struct rtl_cond name = { \ 835 .check = name ## _check, \ 836 .msg = #name \ 837 }; \ 838 \ 839 static bool name ## _check(struct rtl8169_private *tp) 840 841 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 842 { 843 if (reg & 0xffff0001) { 844 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 845 return true; 846 } 847 return false; 848 } 849 850 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 851 { 852 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 853 } 854 855 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 856 { 857 if (rtl_ocp_reg_failure(tp, reg)) 858 return; 859 860 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 861 862 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 863 } 864 865 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 866 { 867 if (rtl_ocp_reg_failure(tp, reg)) 868 return 0; 869 870 RTL_W32(tp, GPHY_OCP, reg << 15); 871 872 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 873 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 874 } 875 876 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 877 { 878 if (rtl_ocp_reg_failure(tp, reg)) 879 return; 880 881 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 882 } 883 884 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 885 { 886 if (rtl_ocp_reg_failure(tp, reg)) 887 return 0; 888 889 RTL_W32(tp, OCPDR, reg << 15); 890 891 return RTL_R32(tp, OCPDR); 892 } 893 894 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 895 u16 set) 896 { 897 u16 data = r8168_mac_ocp_read(tp, reg); 898 899 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 900 } 901 902 #define OCP_STD_PHY_BASE 0xa400 903 904 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 905 { 906 if (reg == 0x1f) { 907 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 908 return; 909 } 910 911 if (tp->ocp_base != OCP_STD_PHY_BASE) 912 reg -= 0x10; 913 914 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 915 } 916 917 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 918 { 919 if (tp->ocp_base != OCP_STD_PHY_BASE) 920 reg -= 0x10; 921 922 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 923 } 924 925 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 926 { 927 if (reg == 0x1f) { 928 tp->ocp_base = value << 4; 929 return; 930 } 931 932 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 933 } 934 935 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 936 { 937 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 938 } 939 940 DECLARE_RTL_COND(rtl_phyar_cond) 941 { 942 return RTL_R32(tp, PHYAR) & 0x80000000; 943 } 944 945 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 946 { 947 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 948 949 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 950 /* 951 * According to hardware specs a 20us delay is required after write 952 * complete indication, but before sending next command. 953 */ 954 udelay(20); 955 } 956 957 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 958 { 959 int value; 960 961 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 962 963 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 964 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 965 966 /* 967 * According to hardware specs a 20us delay is required after read 968 * complete indication, but before sending next command. 969 */ 970 udelay(20); 971 972 return value; 973 } 974 975 DECLARE_RTL_COND(rtl_ocpar_cond) 976 { 977 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 978 } 979 980 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 981 { 982 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 983 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 984 RTL_W32(tp, EPHY_RXER_NUM, 0); 985 986 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 987 } 988 989 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 990 { 991 r8168dp_1_mdio_access(tp, reg, 992 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 993 } 994 995 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 996 { 997 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 998 999 mdelay(1); 1000 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1001 RTL_W32(tp, EPHY_RXER_NUM, 0); 1002 1003 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1004 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1005 } 1006 1007 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1008 1009 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1010 { 1011 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1012 } 1013 1014 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1015 { 1016 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1017 } 1018 1019 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1020 { 1021 r8168dp_2_mdio_start(tp); 1022 1023 r8169_mdio_write(tp, reg, value); 1024 1025 r8168dp_2_mdio_stop(tp); 1026 } 1027 1028 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1029 { 1030 int value; 1031 1032 r8168dp_2_mdio_start(tp); 1033 1034 value = r8169_mdio_read(tp, reg); 1035 1036 r8168dp_2_mdio_stop(tp); 1037 1038 return value; 1039 } 1040 1041 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1042 { 1043 switch (tp->mac_version) { 1044 case RTL_GIGA_MAC_VER_27: 1045 r8168dp_1_mdio_write(tp, location, val); 1046 break; 1047 case RTL_GIGA_MAC_VER_28: 1048 case RTL_GIGA_MAC_VER_31: 1049 r8168dp_2_mdio_write(tp, location, val); 1050 break; 1051 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1052 r8168g_mdio_write(tp, location, val); 1053 break; 1054 default: 1055 r8169_mdio_write(tp, location, val); 1056 break; 1057 } 1058 } 1059 1060 static int rtl_readphy(struct rtl8169_private *tp, int location) 1061 { 1062 switch (tp->mac_version) { 1063 case RTL_GIGA_MAC_VER_27: 1064 return r8168dp_1_mdio_read(tp, location); 1065 case RTL_GIGA_MAC_VER_28: 1066 case RTL_GIGA_MAC_VER_31: 1067 return r8168dp_2_mdio_read(tp, location); 1068 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1069 return r8168g_mdio_read(tp, location); 1070 default: 1071 return r8169_mdio_read(tp, location); 1072 } 1073 } 1074 1075 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) 1076 { 1077 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); 1078 } 1079 1080 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) 1081 { 1082 int val; 1083 1084 val = rtl_readphy(tp, reg_addr); 1085 rtl_writephy(tp, reg_addr, (val & ~m) | p); 1086 } 1087 1088 DECLARE_RTL_COND(rtl_ephyar_cond) 1089 { 1090 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1091 } 1092 1093 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1094 { 1095 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1096 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1097 1098 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1099 1100 udelay(10); 1101 } 1102 1103 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1104 { 1105 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1106 1107 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1108 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1109 } 1110 1111 DECLARE_RTL_COND(rtl_eriar_cond) 1112 { 1113 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1114 } 1115 1116 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1117 u32 val, int type) 1118 { 1119 BUG_ON((addr & 3) || (mask == 0)); 1120 RTL_W32(tp, ERIDR, val); 1121 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1122 1123 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1124 } 1125 1126 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1127 u32 val) 1128 { 1129 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1130 } 1131 1132 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1133 { 1134 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1135 1136 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1137 RTL_R32(tp, ERIDR) : ~0; 1138 } 1139 1140 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1141 { 1142 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1143 } 1144 1145 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1146 u32 m) 1147 { 1148 u32 val; 1149 1150 val = rtl_eri_read(tp, addr); 1151 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1152 } 1153 1154 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1155 u32 p) 1156 { 1157 rtl_w0w1_eri(tp, addr, mask, p, 0); 1158 } 1159 1160 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1161 u32 m) 1162 { 1163 rtl_w0w1_eri(tp, addr, mask, 0, m); 1164 } 1165 1166 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1167 { 1168 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1169 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1170 RTL_R32(tp, OCPDR) : ~0; 1171 } 1172 1173 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1174 { 1175 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1176 } 1177 1178 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1179 u32 data) 1180 { 1181 RTL_W32(tp, OCPDR, data); 1182 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1183 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1184 } 1185 1186 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1187 u32 data) 1188 { 1189 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1190 data, ERIAR_OOB); 1191 } 1192 1193 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1194 { 1195 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1196 1197 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1198 } 1199 1200 #define OOB_CMD_RESET 0x00 1201 #define OOB_CMD_DRIVER_START 0x05 1202 #define OOB_CMD_DRIVER_STOP 0x06 1203 1204 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1205 { 1206 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1207 } 1208 1209 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1210 { 1211 u16 reg; 1212 1213 reg = rtl8168_get_ocp_reg(tp); 1214 1215 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1216 } 1217 1218 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1219 { 1220 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1221 } 1222 1223 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1224 { 1225 return RTL_R8(tp, IBISR0) & 0x20; 1226 } 1227 1228 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1229 { 1230 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1231 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1232 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1233 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1234 } 1235 1236 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1237 { 1238 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1239 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1240 } 1241 1242 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1243 { 1244 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1245 r8168ep_ocp_write(tp, 0x01, 0x30, 1246 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1247 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1248 } 1249 1250 static void rtl8168_driver_start(struct rtl8169_private *tp) 1251 { 1252 switch (tp->mac_version) { 1253 case RTL_GIGA_MAC_VER_27: 1254 case RTL_GIGA_MAC_VER_28: 1255 case RTL_GIGA_MAC_VER_31: 1256 rtl8168dp_driver_start(tp); 1257 break; 1258 case RTL_GIGA_MAC_VER_49: 1259 case RTL_GIGA_MAC_VER_50: 1260 case RTL_GIGA_MAC_VER_51: 1261 rtl8168ep_driver_start(tp); 1262 break; 1263 default: 1264 BUG(); 1265 break; 1266 } 1267 } 1268 1269 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1270 { 1271 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1272 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1273 } 1274 1275 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1276 { 1277 rtl8168ep_stop_cmac(tp); 1278 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1279 r8168ep_ocp_write(tp, 0x01, 0x30, 1280 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1281 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1282 } 1283 1284 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1285 { 1286 switch (tp->mac_version) { 1287 case RTL_GIGA_MAC_VER_27: 1288 case RTL_GIGA_MAC_VER_28: 1289 case RTL_GIGA_MAC_VER_31: 1290 rtl8168dp_driver_stop(tp); 1291 break; 1292 case RTL_GIGA_MAC_VER_49: 1293 case RTL_GIGA_MAC_VER_50: 1294 case RTL_GIGA_MAC_VER_51: 1295 rtl8168ep_driver_stop(tp); 1296 break; 1297 default: 1298 BUG(); 1299 break; 1300 } 1301 } 1302 1303 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1304 { 1305 u16 reg = rtl8168_get_ocp_reg(tp); 1306 1307 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1308 } 1309 1310 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1311 { 1312 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1313 } 1314 1315 static bool r8168_check_dash(struct rtl8169_private *tp) 1316 { 1317 switch (tp->mac_version) { 1318 case RTL_GIGA_MAC_VER_27: 1319 case RTL_GIGA_MAC_VER_28: 1320 case RTL_GIGA_MAC_VER_31: 1321 return r8168dp_check_dash(tp); 1322 case RTL_GIGA_MAC_VER_49: 1323 case RTL_GIGA_MAC_VER_50: 1324 case RTL_GIGA_MAC_VER_51: 1325 return r8168ep_check_dash(tp); 1326 default: 1327 return false; 1328 } 1329 } 1330 1331 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1332 { 1333 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1334 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1335 } 1336 1337 DECLARE_RTL_COND(rtl_efusear_cond) 1338 { 1339 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1340 } 1341 1342 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1343 { 1344 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1345 1346 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1347 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1348 } 1349 1350 static u32 rtl_get_events(struct rtl8169_private *tp) 1351 { 1352 if (rtl_is_8125(tp)) 1353 return RTL_R32(tp, IntrStatus_8125); 1354 else 1355 return RTL_R16(tp, IntrStatus); 1356 } 1357 1358 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1359 { 1360 if (rtl_is_8125(tp)) 1361 RTL_W32(tp, IntrStatus_8125, bits); 1362 else 1363 RTL_W16(tp, IntrStatus, bits); 1364 } 1365 1366 static void rtl_irq_disable(struct rtl8169_private *tp) 1367 { 1368 if (rtl_is_8125(tp)) 1369 RTL_W32(tp, IntrMask_8125, 0); 1370 else 1371 RTL_W16(tp, IntrMask, 0); 1372 tp->irq_enabled = 0; 1373 } 1374 1375 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) 1376 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) 1377 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) 1378 1379 static void rtl_irq_enable(struct rtl8169_private *tp) 1380 { 1381 tp->irq_enabled = 1; 1382 if (rtl_is_8125(tp)) 1383 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1384 else 1385 RTL_W16(tp, IntrMask, tp->irq_mask); 1386 } 1387 1388 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1389 { 1390 rtl_irq_disable(tp); 1391 rtl_ack_events(tp, 0xffffffff); 1392 /* PCI commit */ 1393 RTL_R8(tp, ChipCmd); 1394 } 1395 1396 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1397 { 1398 struct net_device *dev = tp->dev; 1399 struct phy_device *phydev = tp->phydev; 1400 1401 if (!netif_running(dev)) 1402 return; 1403 1404 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1405 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1406 if (phydev->speed == SPEED_1000) { 1407 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1408 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1409 } else if (phydev->speed == SPEED_100) { 1410 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1411 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1412 } else { 1413 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1414 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1415 } 1416 rtl_reset_packet_filter(tp); 1417 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1418 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1419 if (phydev->speed == SPEED_1000) { 1420 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1421 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1422 } else { 1423 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1424 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1425 } 1426 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1427 if (phydev->speed == SPEED_10) { 1428 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1429 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1430 } else { 1431 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1432 } 1433 } 1434 } 1435 1436 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1437 1438 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1439 { 1440 struct rtl8169_private *tp = netdev_priv(dev); 1441 1442 rtl_lock_work(tp); 1443 wol->supported = WAKE_ANY; 1444 wol->wolopts = tp->saved_wolopts; 1445 rtl_unlock_work(tp); 1446 } 1447 1448 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1449 { 1450 static const struct { 1451 u32 opt; 1452 u16 reg; 1453 u8 mask; 1454 } cfg[] = { 1455 { WAKE_PHY, Config3, LinkUp }, 1456 { WAKE_UCAST, Config5, UWF }, 1457 { WAKE_BCAST, Config5, BWF }, 1458 { WAKE_MCAST, Config5, MWF }, 1459 { WAKE_ANY, Config5, LanWake }, 1460 { WAKE_MAGIC, Config3, MagicPacket } 1461 }; 1462 unsigned int i, tmp = ARRAY_SIZE(cfg); 1463 u8 options; 1464 1465 rtl_unlock_config_regs(tp); 1466 1467 if (rtl_is_8168evl_up(tp)) { 1468 tmp--; 1469 if (wolopts & WAKE_MAGIC) 1470 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1471 MagicPacket_v2); 1472 else 1473 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1474 MagicPacket_v2); 1475 } else if (rtl_is_8125(tp)) { 1476 tmp--; 1477 if (wolopts & WAKE_MAGIC) 1478 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1479 else 1480 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1481 } 1482 1483 for (i = 0; i < tmp; i++) { 1484 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1485 if (wolopts & cfg[i].opt) 1486 options |= cfg[i].mask; 1487 RTL_W8(tp, cfg[i].reg, options); 1488 } 1489 1490 switch (tp->mac_version) { 1491 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1492 options = RTL_R8(tp, Config1) & ~PMEnable; 1493 if (wolopts) 1494 options |= PMEnable; 1495 RTL_W8(tp, Config1, options); 1496 break; 1497 case RTL_GIGA_MAC_VER_34: 1498 case RTL_GIGA_MAC_VER_37: 1499 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51: 1500 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1501 if (wolopts) 1502 options |= PME_SIGNAL; 1503 RTL_W8(tp, Config2, options); 1504 break; 1505 default: 1506 break; 1507 } 1508 1509 rtl_lock_config_regs(tp); 1510 1511 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1512 } 1513 1514 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1515 { 1516 struct rtl8169_private *tp = netdev_priv(dev); 1517 struct device *d = tp_to_dev(tp); 1518 1519 if (wol->wolopts & ~WAKE_ANY) 1520 return -EINVAL; 1521 1522 pm_runtime_get_noresume(d); 1523 1524 rtl_lock_work(tp); 1525 1526 tp->saved_wolopts = wol->wolopts; 1527 1528 if (pm_runtime_active(d)) 1529 __rtl8169_set_wol(tp, tp->saved_wolopts); 1530 1531 rtl_unlock_work(tp); 1532 1533 pm_runtime_put_noidle(d); 1534 1535 return 0; 1536 } 1537 1538 static void rtl8169_get_drvinfo(struct net_device *dev, 1539 struct ethtool_drvinfo *info) 1540 { 1541 struct rtl8169_private *tp = netdev_priv(dev); 1542 struct rtl_fw *rtl_fw = tp->rtl_fw; 1543 1544 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1545 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1546 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1547 if (rtl_fw) 1548 strlcpy(info->fw_version, rtl_fw->version, 1549 sizeof(info->fw_version)); 1550 } 1551 1552 static int rtl8169_get_regs_len(struct net_device *dev) 1553 { 1554 return R8169_REGS_SIZE; 1555 } 1556 1557 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1558 netdev_features_t features) 1559 { 1560 struct rtl8169_private *tp = netdev_priv(dev); 1561 1562 if (dev->mtu > TD_MSS_MAX) 1563 features &= ~NETIF_F_ALL_TSO; 1564 1565 if (dev->mtu > JUMBO_1K && 1566 tp->mac_version > RTL_GIGA_MAC_VER_06) 1567 features &= ~NETIF_F_IP_CSUM; 1568 1569 return features; 1570 } 1571 1572 static int rtl8169_set_features(struct net_device *dev, 1573 netdev_features_t features) 1574 { 1575 struct rtl8169_private *tp = netdev_priv(dev); 1576 u32 rx_config; 1577 1578 rtl_lock_work(tp); 1579 1580 rx_config = RTL_R32(tp, RxConfig); 1581 if (features & NETIF_F_RXALL) 1582 rx_config |= (AcceptErr | AcceptRunt); 1583 else 1584 rx_config &= ~(AcceptErr | AcceptRunt); 1585 1586 if (rtl_is_8125(tp)) { 1587 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1588 rx_config |= RX_VLAN_8125; 1589 else 1590 rx_config &= ~RX_VLAN_8125; 1591 } 1592 1593 RTL_W32(tp, RxConfig, rx_config); 1594 1595 if (features & NETIF_F_RXCSUM) 1596 tp->cp_cmd |= RxChkSum; 1597 else 1598 tp->cp_cmd &= ~RxChkSum; 1599 1600 if (!rtl_is_8125(tp)) { 1601 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1602 tp->cp_cmd |= RxVlan; 1603 else 1604 tp->cp_cmd &= ~RxVlan; 1605 } 1606 1607 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1608 RTL_R16(tp, CPlusCmd); 1609 1610 rtl_unlock_work(tp); 1611 1612 return 0; 1613 } 1614 1615 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1616 { 1617 return (skb_vlan_tag_present(skb)) ? 1618 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1619 } 1620 1621 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1622 { 1623 u32 opts2 = le32_to_cpu(desc->opts2); 1624 1625 if (opts2 & RxVlanTag) 1626 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1627 } 1628 1629 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1630 void *p) 1631 { 1632 struct rtl8169_private *tp = netdev_priv(dev); 1633 u32 __iomem *data = tp->mmio_addr; 1634 u32 *dw = p; 1635 int i; 1636 1637 rtl_lock_work(tp); 1638 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1639 memcpy_fromio(dw++, data++, 4); 1640 rtl_unlock_work(tp); 1641 } 1642 1643 static u32 rtl8169_get_msglevel(struct net_device *dev) 1644 { 1645 struct rtl8169_private *tp = netdev_priv(dev); 1646 1647 return tp->msg_enable; 1648 } 1649 1650 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1651 { 1652 struct rtl8169_private *tp = netdev_priv(dev); 1653 1654 tp->msg_enable = value; 1655 } 1656 1657 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1658 "tx_packets", 1659 "rx_packets", 1660 "tx_errors", 1661 "rx_errors", 1662 "rx_missed", 1663 "align_errors", 1664 "tx_single_collisions", 1665 "tx_multi_collisions", 1666 "unicast", 1667 "broadcast", 1668 "multicast", 1669 "tx_aborted", 1670 "tx_underrun", 1671 }; 1672 1673 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1674 { 1675 switch (sset) { 1676 case ETH_SS_STATS: 1677 return ARRAY_SIZE(rtl8169_gstrings); 1678 default: 1679 return -EOPNOTSUPP; 1680 } 1681 } 1682 1683 DECLARE_RTL_COND(rtl_counters_cond) 1684 { 1685 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1686 } 1687 1688 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1689 { 1690 dma_addr_t paddr = tp->counters_phys_addr; 1691 u32 cmd; 1692 1693 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1694 RTL_R32(tp, CounterAddrHigh); 1695 cmd = (u64)paddr & DMA_BIT_MASK(32); 1696 RTL_W32(tp, CounterAddrLow, cmd); 1697 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1698 1699 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1700 } 1701 1702 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1703 { 1704 /* 1705 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1706 * tally counters. 1707 */ 1708 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1709 return true; 1710 1711 return rtl8169_do_counters(tp, CounterReset); 1712 } 1713 1714 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1715 { 1716 u8 val = RTL_R8(tp, ChipCmd); 1717 1718 /* 1719 * Some chips are unable to dump tally counters when the receiver 1720 * is disabled. If 0xff chip may be in a PCI power-save state. 1721 */ 1722 if (!(val & CmdRxEnb) || val == 0xff) 1723 return true; 1724 1725 return rtl8169_do_counters(tp, CounterDump); 1726 } 1727 1728 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1729 { 1730 struct rtl8169_counters *counters = tp->counters; 1731 bool ret = false; 1732 1733 /* 1734 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1735 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1736 * reset by a power cycle, while the counter values collected by the 1737 * driver are reset at every driver unload/load cycle. 1738 * 1739 * To make sure the HW values returned by @get_stats64 match the SW 1740 * values, we collect the initial values at first open(*) and use them 1741 * as offsets to normalize the values returned by @get_stats64. 1742 * 1743 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1744 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1745 * set at open time by rtl_hw_start. 1746 */ 1747 1748 if (tp->tc_offset.inited) 1749 return true; 1750 1751 /* If both, reset and update fail, propagate to caller. */ 1752 if (rtl8169_reset_counters(tp)) 1753 ret = true; 1754 1755 if (rtl8169_update_counters(tp)) 1756 ret = true; 1757 1758 tp->tc_offset.tx_errors = counters->tx_errors; 1759 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1760 tp->tc_offset.tx_aborted = counters->tx_aborted; 1761 tp->tc_offset.inited = true; 1762 1763 return ret; 1764 } 1765 1766 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1767 struct ethtool_stats *stats, u64 *data) 1768 { 1769 struct rtl8169_private *tp = netdev_priv(dev); 1770 struct device *d = tp_to_dev(tp); 1771 struct rtl8169_counters *counters = tp->counters; 1772 1773 ASSERT_RTNL(); 1774 1775 pm_runtime_get_noresume(d); 1776 1777 if (pm_runtime_active(d)) 1778 rtl8169_update_counters(tp); 1779 1780 pm_runtime_put_noidle(d); 1781 1782 data[0] = le64_to_cpu(counters->tx_packets); 1783 data[1] = le64_to_cpu(counters->rx_packets); 1784 data[2] = le64_to_cpu(counters->tx_errors); 1785 data[3] = le32_to_cpu(counters->rx_errors); 1786 data[4] = le16_to_cpu(counters->rx_missed); 1787 data[5] = le16_to_cpu(counters->align_errors); 1788 data[6] = le32_to_cpu(counters->tx_one_collision); 1789 data[7] = le32_to_cpu(counters->tx_multi_collision); 1790 data[8] = le64_to_cpu(counters->rx_unicast); 1791 data[9] = le64_to_cpu(counters->rx_broadcast); 1792 data[10] = le32_to_cpu(counters->rx_multicast); 1793 data[11] = le16_to_cpu(counters->tx_aborted); 1794 data[12] = le16_to_cpu(counters->tx_underun); 1795 } 1796 1797 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1798 { 1799 switch(stringset) { 1800 case ETH_SS_STATS: 1801 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1802 break; 1803 } 1804 } 1805 1806 /* 1807 * Interrupt coalescing 1808 * 1809 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1810 * > 8169, 8168 and 810x line of chipsets 1811 * 1812 * 8169, 8168, and 8136(810x) serial chipsets support it. 1813 * 1814 * > 2 - the Tx timer unit at gigabit speed 1815 * 1816 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1817 * (0xe0) bit 1 and bit 0. 1818 * 1819 * For 8169 1820 * bit[1:0] \ speed 1000M 100M 10M 1821 * 0 0 320ns 2.56us 40.96us 1822 * 0 1 2.56us 20.48us 327.7us 1823 * 1 0 5.12us 40.96us 655.4us 1824 * 1 1 10.24us 81.92us 1.31ms 1825 * 1826 * For the other 1827 * bit[1:0] \ speed 1000M 100M 10M 1828 * 0 0 5us 2.56us 40.96us 1829 * 0 1 40us 20.48us 327.7us 1830 * 1 0 80us 40.96us 655.4us 1831 * 1 1 160us 81.92us 1.31ms 1832 */ 1833 1834 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1835 struct rtl_coalesce_scale { 1836 /* Rx / Tx */ 1837 u32 nsecs[2]; 1838 }; 1839 1840 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1841 struct rtl_coalesce_info { 1842 u32 speed; 1843 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1844 }; 1845 1846 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1847 #define rxtx_x1822(r, t) { \ 1848 {{(r), (t)}}, \ 1849 {{(r)*8, (t)*8}}, \ 1850 {{(r)*8*2, (t)*8*2}}, \ 1851 {{(r)*8*2*2, (t)*8*2*2}}, \ 1852 } 1853 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1854 /* speed delays: rx00 tx00 */ 1855 { SPEED_10, rxtx_x1822(40960, 40960) }, 1856 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1857 { SPEED_1000, rxtx_x1822( 320, 320) }, 1858 { 0 }, 1859 }; 1860 1861 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1862 /* speed delays: rx00 tx00 */ 1863 { SPEED_10, rxtx_x1822(40960, 40960) }, 1864 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1865 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1866 { 0 }, 1867 }; 1868 #undef rxtx_x1822 1869 1870 /* get rx/tx scale vector corresponding to current speed */ 1871 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1872 { 1873 struct rtl8169_private *tp = netdev_priv(dev); 1874 const struct rtl_coalesce_info *ci; 1875 1876 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1877 ci = rtl_coalesce_info_8169; 1878 else 1879 ci = rtl_coalesce_info_8168_8136; 1880 1881 for (; ci->speed; ci++) { 1882 if (tp->phydev->speed == ci->speed) 1883 return ci; 1884 } 1885 1886 return ERR_PTR(-ELNRNG); 1887 } 1888 1889 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1890 { 1891 struct rtl8169_private *tp = netdev_priv(dev); 1892 const struct rtl_coalesce_info *ci; 1893 const struct rtl_coalesce_scale *scale; 1894 struct { 1895 u32 *max_frames; 1896 u32 *usecs; 1897 } coal_settings [] = { 1898 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1899 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1900 }, *p = coal_settings; 1901 int i; 1902 u16 w; 1903 1904 if (rtl_is_8125(tp)) 1905 return -EOPNOTSUPP; 1906 1907 memset(ec, 0, sizeof(*ec)); 1908 1909 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1910 ci = rtl_coalesce_info(dev); 1911 if (IS_ERR(ci)) 1912 return PTR_ERR(ci); 1913 1914 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1915 1916 /* read IntrMitigate and adjust according to scale */ 1917 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1918 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1919 w >>= RTL_COALESCE_SHIFT; 1920 *p->usecs = w & RTL_COALESCE_MASK; 1921 } 1922 1923 for (i = 0; i < 2; i++) { 1924 p = coal_settings + i; 1925 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1926 1927 /* 1928 * ethtool_coalesce says it is illegal to set both usecs and 1929 * max_frames to 0. 1930 */ 1931 if (!*p->usecs && !*p->max_frames) 1932 *p->max_frames = 1; 1933 } 1934 1935 return 0; 1936 } 1937 1938 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1939 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1940 struct net_device *dev, u32 nsec, u16 *cp01) 1941 { 1942 const struct rtl_coalesce_info *ci; 1943 u16 i; 1944 1945 ci = rtl_coalesce_info(dev); 1946 if (IS_ERR(ci)) 1947 return ERR_CAST(ci); 1948 1949 for (i = 0; i < 4; i++) { 1950 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1951 ci->scalev[i].nsecs[1]); 1952 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1953 *cp01 = i; 1954 return &ci->scalev[i]; 1955 } 1956 } 1957 1958 return ERR_PTR(-EINVAL); 1959 } 1960 1961 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1962 { 1963 struct rtl8169_private *tp = netdev_priv(dev); 1964 const struct rtl_coalesce_scale *scale; 1965 struct { 1966 u32 frames; 1967 u32 usecs; 1968 } coal_settings [] = { 1969 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 1970 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 1971 }, *p = coal_settings; 1972 u16 w = 0, cp01; 1973 int i; 1974 1975 if (rtl_is_8125(tp)) 1976 return -EOPNOTSUPP; 1977 1978 scale = rtl_coalesce_choose_scale(dev, 1979 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 1980 if (IS_ERR(scale)) 1981 return PTR_ERR(scale); 1982 1983 for (i = 0; i < 2; i++, p++) { 1984 u32 units; 1985 1986 /* 1987 * accept max_frames=1 we returned in rtl_get_coalesce. 1988 * accept it not only when usecs=0 because of e.g. the following scenario: 1989 * 1990 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1991 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1992 * - then user does `ethtool -C eth0 rx-usecs 100` 1993 * 1994 * since ethtool sends to kernel whole ethtool_coalesce 1995 * settings, if we do not handle rx_usecs=!0, rx_frames=1 1996 * we'll reject it below in `frames % 4 != 0`. 1997 */ 1998 if (p->frames == 1) { 1999 p->frames = 0; 2000 } 2001 2002 units = p->usecs * 1000 / scale->nsecs[i]; 2003 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 2004 return -EINVAL; 2005 2006 w <<= RTL_COALESCE_SHIFT; 2007 w |= units; 2008 w <<= RTL_COALESCE_SHIFT; 2009 w |= p->frames >> 2; 2010 } 2011 2012 rtl_lock_work(tp); 2013 2014 RTL_W16(tp, IntrMitigate, swab16(w)); 2015 2016 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2017 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2018 RTL_R16(tp, CPlusCmd); 2019 2020 rtl_unlock_work(tp); 2021 2022 return 0; 2023 } 2024 2025 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 2026 { 2027 struct rtl8169_private *tp = netdev_priv(dev); 2028 struct device *d = tp_to_dev(tp); 2029 int ret; 2030 2031 if (!rtl_supports_eee(tp)) 2032 return -EOPNOTSUPP; 2033 2034 pm_runtime_get_noresume(d); 2035 2036 if (!pm_runtime_active(d)) { 2037 ret = -EOPNOTSUPP; 2038 } else { 2039 ret = phy_ethtool_get_eee(tp->phydev, data); 2040 } 2041 2042 pm_runtime_put_noidle(d); 2043 2044 return ret; 2045 } 2046 2047 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 2048 { 2049 struct rtl8169_private *tp = netdev_priv(dev); 2050 struct device *d = tp_to_dev(tp); 2051 int ret; 2052 2053 if (!rtl_supports_eee(tp)) 2054 return -EOPNOTSUPP; 2055 2056 pm_runtime_get_noresume(d); 2057 2058 if (!pm_runtime_active(d)) { 2059 ret = -EOPNOTSUPP; 2060 goto out; 2061 } 2062 2063 if (dev->phydev->autoneg == AUTONEG_DISABLE || 2064 dev->phydev->duplex != DUPLEX_FULL) { 2065 ret = -EPROTONOSUPPORT; 2066 goto out; 2067 } 2068 2069 ret = phy_ethtool_set_eee(tp->phydev, data); 2070 out: 2071 pm_runtime_put_noidle(d); 2072 return ret; 2073 } 2074 2075 static const struct ethtool_ops rtl8169_ethtool_ops = { 2076 .get_drvinfo = rtl8169_get_drvinfo, 2077 .get_regs_len = rtl8169_get_regs_len, 2078 .get_link = ethtool_op_get_link, 2079 .get_coalesce = rtl_get_coalesce, 2080 .set_coalesce = rtl_set_coalesce, 2081 .get_msglevel = rtl8169_get_msglevel, 2082 .set_msglevel = rtl8169_set_msglevel, 2083 .get_regs = rtl8169_get_regs, 2084 .get_wol = rtl8169_get_wol, 2085 .set_wol = rtl8169_set_wol, 2086 .get_strings = rtl8169_get_strings, 2087 .get_sset_count = rtl8169_get_sset_count, 2088 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2089 .get_ts_info = ethtool_op_get_ts_info, 2090 .nway_reset = phy_ethtool_nway_reset, 2091 .get_eee = rtl8169_get_eee, 2092 .set_eee = rtl8169_set_eee, 2093 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2094 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2095 }; 2096 2097 static void rtl_enable_eee(struct rtl8169_private *tp) 2098 { 2099 struct phy_device *phydev = tp->phydev; 2100 int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2101 2102 if (supported > 0) 2103 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported); 2104 } 2105 2106 static void rtl8169_get_mac_version(struct rtl8169_private *tp) 2107 { 2108 /* 2109 * The driver currently handles the 8168Bf and the 8168Be identically 2110 * but they can be identified more specifically through the test below 2111 * if needed: 2112 * 2113 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2114 * 2115 * Same thing for the 8101Eb and the 8101Ec: 2116 * 2117 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2118 */ 2119 static const struct rtl_mac_info { 2120 u16 mask; 2121 u16 val; 2122 u16 mac_version; 2123 } mac_info[] = { 2124 /* 8125 family. */ 2125 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2126 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2127 2128 /* 8168EP family. */ 2129 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2130 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2131 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2132 2133 /* 8168H family. */ 2134 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2135 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2136 2137 /* 8168G family. */ 2138 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2139 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2140 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2141 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2142 2143 /* 8168F family. */ 2144 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2145 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2146 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2147 2148 /* 8168E family. */ 2149 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2150 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2151 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2152 2153 /* 8168D family. */ 2154 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2155 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2156 2157 /* 8168DP family. */ 2158 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2159 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2160 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2161 2162 /* 8168C family. */ 2163 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2164 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2165 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2166 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2167 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2168 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2169 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2170 2171 /* 8168B family. */ 2172 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2173 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2174 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2175 2176 /* 8101 family. */ 2177 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2178 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2179 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2180 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2181 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2182 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2183 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2184 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2185 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2186 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2187 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2188 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2189 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2190 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2191 /* FIXME: where did these entries come from ? -- FR */ 2192 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2193 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2194 2195 /* 8110 family. */ 2196 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2197 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2198 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2199 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2200 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2201 2202 /* Catch-all */ 2203 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2204 }; 2205 const struct rtl_mac_info *p = mac_info; 2206 u16 reg = RTL_R32(tp, TxConfig) >> 20; 2207 2208 while ((reg & p->mask) != p->val) 2209 p++; 2210 tp->mac_version = p->mac_version; 2211 2212 if (tp->mac_version == RTL_GIGA_MAC_NONE) { 2213 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf); 2214 } else if (!tp->supports_gmii) { 2215 if (tp->mac_version == RTL_GIGA_MAC_VER_42) 2216 tp->mac_version = RTL_GIGA_MAC_VER_43; 2217 else if (tp->mac_version == RTL_GIGA_MAC_VER_45) 2218 tp->mac_version = RTL_GIGA_MAC_VER_47; 2219 else if (tp->mac_version == RTL_GIGA_MAC_VER_46) 2220 tp->mac_version = RTL_GIGA_MAC_VER_48; 2221 } 2222 } 2223 2224 struct phy_reg { 2225 u16 reg; 2226 u16 val; 2227 }; 2228 2229 static void __rtl_writephy_batch(struct rtl8169_private *tp, 2230 const struct phy_reg *regs, int len) 2231 { 2232 while (len-- > 0) { 2233 rtl_writephy(tp, regs->reg, regs->val); 2234 regs++; 2235 } 2236 } 2237 2238 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a)) 2239 2240 static void rtl_release_firmware(struct rtl8169_private *tp) 2241 { 2242 if (tp->rtl_fw) { 2243 rtl_fw_release_firmware(tp->rtl_fw); 2244 kfree(tp->rtl_fw); 2245 tp->rtl_fw = NULL; 2246 } 2247 } 2248 2249 static void rtl_apply_firmware(struct rtl8169_private *tp) 2250 { 2251 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2252 if (tp->rtl_fw) 2253 rtl_fw_write_firmware(tp, tp->rtl_fw); 2254 } 2255 2256 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) 2257 { 2258 if (rtl_readphy(tp, reg) != val) 2259 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); 2260 else 2261 rtl_apply_firmware(tp); 2262 } 2263 2264 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2265 { 2266 /* Adjust EEE LED frequency */ 2267 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2268 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2269 2270 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2271 } 2272 2273 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2274 { 2275 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2276 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2277 } 2278 2279 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp) 2280 { 2281 struct phy_device *phydev = tp->phydev; 2282 2283 phy_write(phydev, 0x1f, 0x0007); 2284 phy_write(phydev, 0x1e, 0x0020); 2285 phy_set_bits(phydev, 0x15, BIT(8)); 2286 2287 phy_write(phydev, 0x1f, 0x0005); 2288 phy_write(phydev, 0x05, 0x8b85); 2289 phy_set_bits(phydev, 0x06, BIT(13)); 2290 2291 phy_write(phydev, 0x1f, 0x0000); 2292 } 2293 2294 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp) 2295 { 2296 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4)); 2297 } 2298 2299 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp) 2300 { 2301 struct phy_device *phydev = tp->phydev; 2302 2303 rtl8168g_config_eee_phy(tp); 2304 2305 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 2306 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 2307 } 2308 2309 static void rtl8125_config_eee_phy(struct rtl8169_private *tp) 2310 { 2311 struct phy_device *phydev = tp->phydev; 2312 2313 rtl8168h_config_eee_phy(tp); 2314 2315 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 2316 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 2317 } 2318 2319 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) 2320 { 2321 static const struct phy_reg phy_reg_init[] = { 2322 { 0x1f, 0x0001 }, 2323 { 0x06, 0x006e }, 2324 { 0x08, 0x0708 }, 2325 { 0x15, 0x4000 }, 2326 { 0x18, 0x65c7 }, 2327 2328 { 0x1f, 0x0001 }, 2329 { 0x03, 0x00a1 }, 2330 { 0x02, 0x0008 }, 2331 { 0x01, 0x0120 }, 2332 { 0x00, 0x1000 }, 2333 { 0x04, 0x0800 }, 2334 { 0x04, 0x0000 }, 2335 2336 { 0x03, 0xff41 }, 2337 { 0x02, 0xdf60 }, 2338 { 0x01, 0x0140 }, 2339 { 0x00, 0x0077 }, 2340 { 0x04, 0x7800 }, 2341 { 0x04, 0x7000 }, 2342 2343 { 0x03, 0x802f }, 2344 { 0x02, 0x4f02 }, 2345 { 0x01, 0x0409 }, 2346 { 0x00, 0xf0f9 }, 2347 { 0x04, 0x9800 }, 2348 { 0x04, 0x9000 }, 2349 2350 { 0x03, 0xdf01 }, 2351 { 0x02, 0xdf20 }, 2352 { 0x01, 0xff95 }, 2353 { 0x00, 0xba00 }, 2354 { 0x04, 0xa800 }, 2355 { 0x04, 0xa000 }, 2356 2357 { 0x03, 0xff41 }, 2358 { 0x02, 0xdf20 }, 2359 { 0x01, 0x0140 }, 2360 { 0x00, 0x00bb }, 2361 { 0x04, 0xb800 }, 2362 { 0x04, 0xb000 }, 2363 2364 { 0x03, 0xdf41 }, 2365 { 0x02, 0xdc60 }, 2366 { 0x01, 0x6340 }, 2367 { 0x00, 0x007d }, 2368 { 0x04, 0xd800 }, 2369 { 0x04, 0xd000 }, 2370 2371 { 0x03, 0xdf01 }, 2372 { 0x02, 0xdf20 }, 2373 { 0x01, 0x100a }, 2374 { 0x00, 0xa0ff }, 2375 { 0x04, 0xf800 }, 2376 { 0x04, 0xf000 }, 2377 2378 { 0x1f, 0x0000 }, 2379 { 0x0b, 0x0000 }, 2380 { 0x00, 0x9200 } 2381 }; 2382 2383 rtl_writephy_batch(tp, phy_reg_init); 2384 } 2385 2386 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) 2387 { 2388 static const struct phy_reg phy_reg_init[] = { 2389 { 0x1f, 0x0002 }, 2390 { 0x01, 0x90d0 }, 2391 { 0x1f, 0x0000 } 2392 }; 2393 2394 rtl_writephy_batch(tp, phy_reg_init); 2395 } 2396 2397 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) 2398 { 2399 struct pci_dev *pdev = tp->pci_dev; 2400 2401 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || 2402 (pdev->subsystem_device != 0xe000)) 2403 return; 2404 2405 rtl_writephy(tp, 0x1f, 0x0001); 2406 rtl_writephy(tp, 0x10, 0xf01b); 2407 rtl_writephy(tp, 0x1f, 0x0000); 2408 } 2409 2410 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) 2411 { 2412 static const struct phy_reg phy_reg_init[] = { 2413 { 0x1f, 0x0001 }, 2414 { 0x04, 0x0000 }, 2415 { 0x03, 0x00a1 }, 2416 { 0x02, 0x0008 }, 2417 { 0x01, 0x0120 }, 2418 { 0x00, 0x1000 }, 2419 { 0x04, 0x0800 }, 2420 { 0x04, 0x9000 }, 2421 { 0x03, 0x802f }, 2422 { 0x02, 0x4f02 }, 2423 { 0x01, 0x0409 }, 2424 { 0x00, 0xf099 }, 2425 { 0x04, 0x9800 }, 2426 { 0x04, 0xa000 }, 2427 { 0x03, 0xdf01 }, 2428 { 0x02, 0xdf20 }, 2429 { 0x01, 0xff95 }, 2430 { 0x00, 0xba00 }, 2431 { 0x04, 0xa800 }, 2432 { 0x04, 0xf000 }, 2433 { 0x03, 0xdf01 }, 2434 { 0x02, 0xdf20 }, 2435 { 0x01, 0x101a }, 2436 { 0x00, 0xa0ff }, 2437 { 0x04, 0xf800 }, 2438 { 0x04, 0x0000 }, 2439 { 0x1f, 0x0000 }, 2440 2441 { 0x1f, 0x0001 }, 2442 { 0x10, 0xf41b }, 2443 { 0x14, 0xfb54 }, 2444 { 0x18, 0xf5c7 }, 2445 { 0x1f, 0x0000 }, 2446 2447 { 0x1f, 0x0001 }, 2448 { 0x17, 0x0cc0 }, 2449 { 0x1f, 0x0000 } 2450 }; 2451 2452 rtl_writephy_batch(tp, phy_reg_init); 2453 2454 rtl8169scd_hw_phy_config_quirk(tp); 2455 } 2456 2457 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) 2458 { 2459 static const struct phy_reg phy_reg_init[] = { 2460 { 0x1f, 0x0001 }, 2461 { 0x04, 0x0000 }, 2462 { 0x03, 0x00a1 }, 2463 { 0x02, 0x0008 }, 2464 { 0x01, 0x0120 }, 2465 { 0x00, 0x1000 }, 2466 { 0x04, 0x0800 }, 2467 { 0x04, 0x9000 }, 2468 { 0x03, 0x802f }, 2469 { 0x02, 0x4f02 }, 2470 { 0x01, 0x0409 }, 2471 { 0x00, 0xf099 }, 2472 { 0x04, 0x9800 }, 2473 { 0x04, 0xa000 }, 2474 { 0x03, 0xdf01 }, 2475 { 0x02, 0xdf20 }, 2476 { 0x01, 0xff95 }, 2477 { 0x00, 0xba00 }, 2478 { 0x04, 0xa800 }, 2479 { 0x04, 0xf000 }, 2480 { 0x03, 0xdf01 }, 2481 { 0x02, 0xdf20 }, 2482 { 0x01, 0x101a }, 2483 { 0x00, 0xa0ff }, 2484 { 0x04, 0xf800 }, 2485 { 0x04, 0x0000 }, 2486 { 0x1f, 0x0000 }, 2487 2488 { 0x1f, 0x0001 }, 2489 { 0x0b, 0x8480 }, 2490 { 0x1f, 0x0000 }, 2491 2492 { 0x1f, 0x0001 }, 2493 { 0x18, 0x67c7 }, 2494 { 0x04, 0x2000 }, 2495 { 0x03, 0x002f }, 2496 { 0x02, 0x4360 }, 2497 { 0x01, 0x0109 }, 2498 { 0x00, 0x3022 }, 2499 { 0x04, 0x2800 }, 2500 { 0x1f, 0x0000 }, 2501 2502 { 0x1f, 0x0001 }, 2503 { 0x17, 0x0cc0 }, 2504 { 0x1f, 0x0000 } 2505 }; 2506 2507 rtl_writephy_batch(tp, phy_reg_init); 2508 } 2509 2510 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) 2511 { 2512 static const struct phy_reg phy_reg_init[] = { 2513 { 0x10, 0xf41b }, 2514 { 0x1f, 0x0000 } 2515 }; 2516 2517 rtl_writephy(tp, 0x1f, 0x0001); 2518 rtl_patchphy(tp, 0x16, 1 << 0); 2519 2520 rtl_writephy_batch(tp, phy_reg_init); 2521 } 2522 2523 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) 2524 { 2525 static const struct phy_reg phy_reg_init[] = { 2526 { 0x1f, 0x0001 }, 2527 { 0x10, 0xf41b }, 2528 { 0x1f, 0x0000 } 2529 }; 2530 2531 rtl_writephy_batch(tp, phy_reg_init); 2532 } 2533 2534 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) 2535 { 2536 static const struct phy_reg phy_reg_init[] = { 2537 { 0x1f, 0x0000 }, 2538 { 0x1d, 0x0f00 }, 2539 { 0x1f, 0x0002 }, 2540 { 0x0c, 0x1ec8 }, 2541 { 0x1f, 0x0000 } 2542 }; 2543 2544 rtl_writephy_batch(tp, phy_reg_init); 2545 } 2546 2547 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) 2548 { 2549 static const struct phy_reg phy_reg_init[] = { 2550 { 0x1f, 0x0001 }, 2551 { 0x1d, 0x3d98 }, 2552 { 0x1f, 0x0000 } 2553 }; 2554 2555 rtl_writephy(tp, 0x1f, 0x0000); 2556 rtl_patchphy(tp, 0x14, 1 << 5); 2557 rtl_patchphy(tp, 0x0d, 1 << 5); 2558 2559 rtl_writephy_batch(tp, phy_reg_init); 2560 } 2561 2562 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) 2563 { 2564 static const struct phy_reg phy_reg_init[] = { 2565 { 0x1f, 0x0001 }, 2566 { 0x12, 0x2300 }, 2567 { 0x1f, 0x0002 }, 2568 { 0x00, 0x88d4 }, 2569 { 0x01, 0x82b1 }, 2570 { 0x03, 0x7002 }, 2571 { 0x08, 0x9e30 }, 2572 { 0x09, 0x01f0 }, 2573 { 0x0a, 0x5500 }, 2574 { 0x0c, 0x00c8 }, 2575 { 0x1f, 0x0003 }, 2576 { 0x12, 0xc096 }, 2577 { 0x16, 0x000a }, 2578 { 0x1f, 0x0000 }, 2579 { 0x1f, 0x0000 }, 2580 { 0x09, 0x2000 }, 2581 { 0x09, 0x0000 } 2582 }; 2583 2584 rtl_writephy_batch(tp, phy_reg_init); 2585 2586 rtl_patchphy(tp, 0x14, 1 << 5); 2587 rtl_patchphy(tp, 0x0d, 1 << 5); 2588 rtl_writephy(tp, 0x1f, 0x0000); 2589 } 2590 2591 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) 2592 { 2593 static const struct phy_reg phy_reg_init[] = { 2594 { 0x1f, 0x0001 }, 2595 { 0x12, 0x2300 }, 2596 { 0x03, 0x802f }, 2597 { 0x02, 0x4f02 }, 2598 { 0x01, 0x0409 }, 2599 { 0x00, 0xf099 }, 2600 { 0x04, 0x9800 }, 2601 { 0x04, 0x9000 }, 2602 { 0x1d, 0x3d98 }, 2603 { 0x1f, 0x0002 }, 2604 { 0x0c, 0x7eb8 }, 2605 { 0x06, 0x0761 }, 2606 { 0x1f, 0x0003 }, 2607 { 0x16, 0x0f0a }, 2608 { 0x1f, 0x0000 } 2609 }; 2610 2611 rtl_writephy_batch(tp, phy_reg_init); 2612 2613 rtl_patchphy(tp, 0x16, 1 << 0); 2614 rtl_patchphy(tp, 0x14, 1 << 5); 2615 rtl_patchphy(tp, 0x0d, 1 << 5); 2616 rtl_writephy(tp, 0x1f, 0x0000); 2617 } 2618 2619 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) 2620 { 2621 static const struct phy_reg phy_reg_init[] = { 2622 { 0x1f, 0x0001 }, 2623 { 0x12, 0x2300 }, 2624 { 0x1d, 0x3d98 }, 2625 { 0x1f, 0x0002 }, 2626 { 0x0c, 0x7eb8 }, 2627 { 0x06, 0x5461 }, 2628 { 0x1f, 0x0003 }, 2629 { 0x16, 0x0f0a }, 2630 { 0x1f, 0x0000 } 2631 }; 2632 2633 rtl_writephy_batch(tp, phy_reg_init); 2634 2635 rtl_patchphy(tp, 0x16, 1 << 0); 2636 rtl_patchphy(tp, 0x14, 1 << 5); 2637 rtl_patchphy(tp, 0x0d, 1 << 5); 2638 rtl_writephy(tp, 0x1f, 0x0000); 2639 } 2640 2641 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) 2642 { 2643 rtl8168c_3_hw_phy_config(tp); 2644 } 2645 2646 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 2647 /* Channel Estimation */ 2648 { 0x1f, 0x0001 }, 2649 { 0x06, 0x4064 }, 2650 { 0x07, 0x2863 }, 2651 { 0x08, 0x059c }, 2652 { 0x09, 0x26b4 }, 2653 { 0x0a, 0x6a19 }, 2654 { 0x0b, 0xdcc8 }, 2655 { 0x10, 0xf06d }, 2656 { 0x14, 0x7f68 }, 2657 { 0x18, 0x7fd9 }, 2658 { 0x1c, 0xf0ff }, 2659 { 0x1d, 0x3d9c }, 2660 { 0x1f, 0x0003 }, 2661 { 0x12, 0xf49f }, 2662 { 0x13, 0x070b }, 2663 { 0x1a, 0x05ad }, 2664 { 0x14, 0x94c0 }, 2665 2666 /* 2667 * Tx Error Issue 2668 * Enhance line driver power 2669 */ 2670 { 0x1f, 0x0002 }, 2671 { 0x06, 0x5561 }, 2672 { 0x1f, 0x0005 }, 2673 { 0x05, 0x8332 }, 2674 { 0x06, 0x5561 }, 2675 2676 /* 2677 * Can not link to 1Gbps with bad cable 2678 * Decrease SNR threshold form 21.07dB to 19.04dB 2679 */ 2680 { 0x1f, 0x0001 }, 2681 { 0x17, 0x0cc0 }, 2682 2683 { 0x1f, 0x0000 }, 2684 { 0x0d, 0xf880 } 2685 }; 2686 2687 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 2688 { 0x1f, 0x0002 }, 2689 { 0x05, 0x669a }, 2690 { 0x1f, 0x0005 }, 2691 { 0x05, 0x8330 }, 2692 { 0x06, 0x669a }, 2693 { 0x1f, 0x0002 } 2694 }; 2695 2696 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) 2697 { 2698 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2699 2700 /* 2701 * Rx Error Issue 2702 * Fine Tune Switching regulator parameter 2703 */ 2704 rtl_writephy(tp, 0x1f, 0x0002); 2705 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); 2706 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); 2707 2708 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2709 int val; 2710 2711 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2712 2713 val = rtl_readphy(tp, 0x0d); 2714 2715 if ((val & 0x00ff) != 0x006c) { 2716 static const u32 set[] = { 2717 0x0065, 0x0066, 0x0067, 0x0068, 2718 0x0069, 0x006a, 0x006b, 0x006c 2719 }; 2720 int i; 2721 2722 rtl_writephy(tp, 0x1f, 0x0002); 2723 2724 val &= 0xff00; 2725 for (i = 0; i < ARRAY_SIZE(set); i++) 2726 rtl_writephy(tp, 0x0d, val | set[i]); 2727 } 2728 } else { 2729 static const struct phy_reg phy_reg_init[] = { 2730 { 0x1f, 0x0002 }, 2731 { 0x05, 0x6662 }, 2732 { 0x1f, 0x0005 }, 2733 { 0x05, 0x8330 }, 2734 { 0x06, 0x6662 } 2735 }; 2736 2737 rtl_writephy_batch(tp, phy_reg_init); 2738 } 2739 2740 /* RSET couple improve */ 2741 rtl_writephy(tp, 0x1f, 0x0002); 2742 rtl_patchphy(tp, 0x0d, 0x0300); 2743 rtl_patchphy(tp, 0x0f, 0x0010); 2744 2745 /* Fine tune PLL performance */ 2746 rtl_writephy(tp, 0x1f, 0x0002); 2747 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2748 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2749 2750 rtl_writephy(tp, 0x1f, 0x0005); 2751 rtl_writephy(tp, 0x05, 0x001b); 2752 2753 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); 2754 2755 rtl_writephy(tp, 0x1f, 0x0000); 2756 } 2757 2758 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) 2759 { 2760 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2761 2762 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2763 int val; 2764 2765 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2766 2767 val = rtl_readphy(tp, 0x0d); 2768 if ((val & 0x00ff) != 0x006c) { 2769 static const u32 set[] = { 2770 0x0065, 0x0066, 0x0067, 0x0068, 2771 0x0069, 0x006a, 0x006b, 0x006c 2772 }; 2773 int i; 2774 2775 rtl_writephy(tp, 0x1f, 0x0002); 2776 2777 val &= 0xff00; 2778 for (i = 0; i < ARRAY_SIZE(set); i++) 2779 rtl_writephy(tp, 0x0d, val | set[i]); 2780 } 2781 } else { 2782 static const struct phy_reg phy_reg_init[] = { 2783 { 0x1f, 0x0002 }, 2784 { 0x05, 0x2642 }, 2785 { 0x1f, 0x0005 }, 2786 { 0x05, 0x8330 }, 2787 { 0x06, 0x2642 } 2788 }; 2789 2790 rtl_writephy_batch(tp, phy_reg_init); 2791 } 2792 2793 /* Fine tune PLL performance */ 2794 rtl_writephy(tp, 0x1f, 0x0002); 2795 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2796 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2797 2798 /* Switching regulator Slew rate */ 2799 rtl_writephy(tp, 0x1f, 0x0002); 2800 rtl_patchphy(tp, 0x0f, 0x0017); 2801 2802 rtl_writephy(tp, 0x1f, 0x0005); 2803 rtl_writephy(tp, 0x05, 0x001b); 2804 2805 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); 2806 2807 rtl_writephy(tp, 0x1f, 0x0000); 2808 } 2809 2810 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) 2811 { 2812 static const struct phy_reg phy_reg_init[] = { 2813 { 0x1f, 0x0002 }, 2814 { 0x10, 0x0008 }, 2815 { 0x0d, 0x006c }, 2816 2817 { 0x1f, 0x0000 }, 2818 { 0x0d, 0xf880 }, 2819 2820 { 0x1f, 0x0001 }, 2821 { 0x17, 0x0cc0 }, 2822 2823 { 0x1f, 0x0001 }, 2824 { 0x0b, 0xa4d8 }, 2825 { 0x09, 0x281c }, 2826 { 0x07, 0x2883 }, 2827 { 0x0a, 0x6b35 }, 2828 { 0x1d, 0x3da4 }, 2829 { 0x1c, 0xeffd }, 2830 { 0x14, 0x7f52 }, 2831 { 0x18, 0x7fc6 }, 2832 { 0x08, 0x0601 }, 2833 { 0x06, 0x4063 }, 2834 { 0x10, 0xf074 }, 2835 { 0x1f, 0x0003 }, 2836 { 0x13, 0x0789 }, 2837 { 0x12, 0xf4bd }, 2838 { 0x1a, 0x04fd }, 2839 { 0x14, 0x84b0 }, 2840 { 0x1f, 0x0000 }, 2841 { 0x00, 0x9200 }, 2842 2843 { 0x1f, 0x0005 }, 2844 { 0x01, 0x0340 }, 2845 { 0x1f, 0x0001 }, 2846 { 0x04, 0x4000 }, 2847 { 0x03, 0x1d21 }, 2848 { 0x02, 0x0c32 }, 2849 { 0x01, 0x0200 }, 2850 { 0x00, 0x5554 }, 2851 { 0x04, 0x4800 }, 2852 { 0x04, 0x4000 }, 2853 { 0x04, 0xf000 }, 2854 { 0x03, 0xdf01 }, 2855 { 0x02, 0xdf20 }, 2856 { 0x01, 0x101a }, 2857 { 0x00, 0xa0ff }, 2858 { 0x04, 0xf800 }, 2859 { 0x04, 0xf000 }, 2860 { 0x1f, 0x0000 }, 2861 2862 { 0x1f, 0x0007 }, 2863 { 0x1e, 0x0023 }, 2864 { 0x16, 0x0000 }, 2865 { 0x1f, 0x0000 } 2866 }; 2867 2868 rtl_writephy_batch(tp, phy_reg_init); 2869 } 2870 2871 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) 2872 { 2873 static const struct phy_reg phy_reg_init[] = { 2874 { 0x1f, 0x0001 }, 2875 { 0x17, 0x0cc0 }, 2876 2877 { 0x1f, 0x0007 }, 2878 { 0x1e, 0x002d }, 2879 { 0x18, 0x0040 }, 2880 { 0x1f, 0x0000 } 2881 }; 2882 2883 rtl_writephy_batch(tp, phy_reg_init); 2884 rtl_patchphy(tp, 0x0d, 1 << 5); 2885 } 2886 2887 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) 2888 { 2889 static const struct phy_reg phy_reg_init[] = { 2890 /* Enable Delay cap */ 2891 { 0x1f, 0x0005 }, 2892 { 0x05, 0x8b80 }, 2893 { 0x06, 0xc896 }, 2894 { 0x1f, 0x0000 }, 2895 2896 /* Channel estimation fine tune */ 2897 { 0x1f, 0x0001 }, 2898 { 0x0b, 0x6c20 }, 2899 { 0x07, 0x2872 }, 2900 { 0x1c, 0xefff }, 2901 { 0x1f, 0x0003 }, 2902 { 0x14, 0x6420 }, 2903 { 0x1f, 0x0000 }, 2904 2905 /* Update PFM & 10M TX idle timer */ 2906 { 0x1f, 0x0007 }, 2907 { 0x1e, 0x002f }, 2908 { 0x15, 0x1919 }, 2909 { 0x1f, 0x0000 }, 2910 2911 { 0x1f, 0x0007 }, 2912 { 0x1e, 0x00ac }, 2913 { 0x18, 0x0006 }, 2914 { 0x1f, 0x0000 } 2915 }; 2916 2917 rtl_apply_firmware(tp); 2918 2919 rtl_writephy_batch(tp, phy_reg_init); 2920 2921 /* DCO enable for 10M IDLE Power */ 2922 rtl_writephy(tp, 0x1f, 0x0007); 2923 rtl_writephy(tp, 0x1e, 0x0023); 2924 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 2925 rtl_writephy(tp, 0x1f, 0x0000); 2926 2927 /* For impedance matching */ 2928 rtl_writephy(tp, 0x1f, 0x0002); 2929 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00); 2930 rtl_writephy(tp, 0x1f, 0x0000); 2931 2932 /* PHY auto speed down */ 2933 rtl_writephy(tp, 0x1f, 0x0007); 2934 rtl_writephy(tp, 0x1e, 0x002d); 2935 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000); 2936 rtl_writephy(tp, 0x1f, 0x0000); 2937 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 2938 2939 rtl_writephy(tp, 0x1f, 0x0005); 2940 rtl_writephy(tp, 0x05, 0x8b86); 2941 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 2942 rtl_writephy(tp, 0x1f, 0x0000); 2943 2944 rtl_writephy(tp, 0x1f, 0x0005); 2945 rtl_writephy(tp, 0x05, 0x8b85); 2946 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); 2947 rtl_writephy(tp, 0x1f, 0x0007); 2948 rtl_writephy(tp, 0x1e, 0x0020); 2949 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100); 2950 rtl_writephy(tp, 0x1f, 0x0006); 2951 rtl_writephy(tp, 0x00, 0x5a00); 2952 rtl_writephy(tp, 0x1f, 0x0000); 2953 rtl_writephy(tp, 0x0d, 0x0007); 2954 rtl_writephy(tp, 0x0e, 0x003c); 2955 rtl_writephy(tp, 0x0d, 0x4007); 2956 rtl_writephy(tp, 0x0e, 0x0000); 2957 rtl_writephy(tp, 0x0d, 0x0000); 2958 } 2959 2960 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2961 { 2962 const u16 w[] = { 2963 addr[0] | (addr[1] << 8), 2964 addr[2] | (addr[3] << 8), 2965 addr[4] | (addr[5] << 8) 2966 }; 2967 2968 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2969 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2970 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2971 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2972 } 2973 2974 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) 2975 { 2976 static const struct phy_reg phy_reg_init[] = { 2977 /* Enable Delay cap */ 2978 { 0x1f, 0x0004 }, 2979 { 0x1f, 0x0007 }, 2980 { 0x1e, 0x00ac }, 2981 { 0x18, 0x0006 }, 2982 { 0x1f, 0x0002 }, 2983 { 0x1f, 0x0000 }, 2984 { 0x1f, 0x0000 }, 2985 2986 /* Channel estimation fine tune */ 2987 { 0x1f, 0x0003 }, 2988 { 0x09, 0xa20f }, 2989 { 0x1f, 0x0000 }, 2990 { 0x1f, 0x0000 }, 2991 2992 /* Green Setting */ 2993 { 0x1f, 0x0005 }, 2994 { 0x05, 0x8b5b }, 2995 { 0x06, 0x9222 }, 2996 { 0x05, 0x8b6d }, 2997 { 0x06, 0x8000 }, 2998 { 0x05, 0x8b76 }, 2999 { 0x06, 0x8000 }, 3000 { 0x1f, 0x0000 } 3001 }; 3002 3003 rtl_apply_firmware(tp); 3004 3005 rtl_writephy_batch(tp, phy_reg_init); 3006 3007 /* For 4-corner performance improve */ 3008 rtl_writephy(tp, 0x1f, 0x0005); 3009 rtl_writephy(tp, 0x05, 0x8b80); 3010 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 3011 rtl_writephy(tp, 0x1f, 0x0000); 3012 3013 /* PHY auto speed down */ 3014 rtl_writephy(tp, 0x1f, 0x0004); 3015 rtl_writephy(tp, 0x1f, 0x0007); 3016 rtl_writephy(tp, 0x1e, 0x002d); 3017 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3018 rtl_writephy(tp, 0x1f, 0x0002); 3019 rtl_writephy(tp, 0x1f, 0x0000); 3020 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3021 3022 /* improve 10M EEE waveform */ 3023 rtl_writephy(tp, 0x1f, 0x0005); 3024 rtl_writephy(tp, 0x05, 0x8b86); 3025 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3026 rtl_writephy(tp, 0x1f, 0x0000); 3027 3028 /* Improve 2-pair detection performance */ 3029 rtl_writephy(tp, 0x1f, 0x0005); 3030 rtl_writephy(tp, 0x05, 0x8b85); 3031 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3032 rtl_writephy(tp, 0x1f, 0x0000); 3033 3034 rtl8168f_config_eee_phy(tp); 3035 rtl_enable_eee(tp); 3036 3037 /* Green feature */ 3038 rtl_writephy(tp, 0x1f, 0x0003); 3039 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000); 3040 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000); 3041 rtl_writephy(tp, 0x1f, 0x0000); 3042 rtl_writephy(tp, 0x1f, 0x0005); 3043 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000); 3044 rtl_writephy(tp, 0x1f, 0x0000); 3045 3046 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ 3047 rtl_rar_exgmac_set(tp, tp->dev->dev_addr); 3048 } 3049 3050 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) 3051 { 3052 /* For 4-corner performance improve */ 3053 rtl_writephy(tp, 0x1f, 0x0005); 3054 rtl_writephy(tp, 0x05, 0x8b80); 3055 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000); 3056 rtl_writephy(tp, 0x1f, 0x0000); 3057 3058 /* PHY auto speed down */ 3059 rtl_writephy(tp, 0x1f, 0x0007); 3060 rtl_writephy(tp, 0x1e, 0x002d); 3061 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3062 rtl_writephy(tp, 0x1f, 0x0000); 3063 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3064 3065 /* Improve 10M EEE waveform */ 3066 rtl_writephy(tp, 0x1f, 0x0005); 3067 rtl_writephy(tp, 0x05, 0x8b86); 3068 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3069 rtl_writephy(tp, 0x1f, 0x0000); 3070 3071 rtl8168f_config_eee_phy(tp); 3072 rtl_enable_eee(tp); 3073 } 3074 3075 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) 3076 { 3077 static const struct phy_reg phy_reg_init[] = { 3078 /* Channel estimation fine tune */ 3079 { 0x1f, 0x0003 }, 3080 { 0x09, 0xa20f }, 3081 { 0x1f, 0x0000 }, 3082 3083 /* Modify green table for giga & fnet */ 3084 { 0x1f, 0x0005 }, 3085 { 0x05, 0x8b55 }, 3086 { 0x06, 0x0000 }, 3087 { 0x05, 0x8b5e }, 3088 { 0x06, 0x0000 }, 3089 { 0x05, 0x8b67 }, 3090 { 0x06, 0x0000 }, 3091 { 0x05, 0x8b70 }, 3092 { 0x06, 0x0000 }, 3093 { 0x1f, 0x0000 }, 3094 { 0x1f, 0x0007 }, 3095 { 0x1e, 0x0078 }, 3096 { 0x17, 0x0000 }, 3097 { 0x19, 0x00fb }, 3098 { 0x1f, 0x0000 }, 3099 3100 /* Modify green table for 10M */ 3101 { 0x1f, 0x0005 }, 3102 { 0x05, 0x8b79 }, 3103 { 0x06, 0xaa00 }, 3104 { 0x1f, 0x0000 }, 3105 3106 /* Disable hiimpedance detection (RTCT) */ 3107 { 0x1f, 0x0003 }, 3108 { 0x01, 0x328a }, 3109 { 0x1f, 0x0000 } 3110 }; 3111 3112 rtl_apply_firmware(tp); 3113 3114 rtl_writephy_batch(tp, phy_reg_init); 3115 3116 rtl8168f_hw_phy_config(tp); 3117 3118 /* Improve 2-pair detection performance */ 3119 rtl_writephy(tp, 0x1f, 0x0005); 3120 rtl_writephy(tp, 0x05, 0x8b85); 3121 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3122 rtl_writephy(tp, 0x1f, 0x0000); 3123 } 3124 3125 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) 3126 { 3127 rtl_apply_firmware(tp); 3128 3129 rtl8168f_hw_phy_config(tp); 3130 } 3131 3132 static void rtl8411_hw_phy_config(struct rtl8169_private *tp) 3133 { 3134 static const struct phy_reg phy_reg_init[] = { 3135 /* Channel estimation fine tune */ 3136 { 0x1f, 0x0003 }, 3137 { 0x09, 0xa20f }, 3138 { 0x1f, 0x0000 }, 3139 3140 /* Modify green table for giga & fnet */ 3141 { 0x1f, 0x0005 }, 3142 { 0x05, 0x8b55 }, 3143 { 0x06, 0x0000 }, 3144 { 0x05, 0x8b5e }, 3145 { 0x06, 0x0000 }, 3146 { 0x05, 0x8b67 }, 3147 { 0x06, 0x0000 }, 3148 { 0x05, 0x8b70 }, 3149 { 0x06, 0x0000 }, 3150 { 0x1f, 0x0000 }, 3151 { 0x1f, 0x0007 }, 3152 { 0x1e, 0x0078 }, 3153 { 0x17, 0x0000 }, 3154 { 0x19, 0x00aa }, 3155 { 0x1f, 0x0000 }, 3156 3157 /* Modify green table for 10M */ 3158 { 0x1f, 0x0005 }, 3159 { 0x05, 0x8b79 }, 3160 { 0x06, 0xaa00 }, 3161 { 0x1f, 0x0000 }, 3162 3163 /* Disable hiimpedance detection (RTCT) */ 3164 { 0x1f, 0x0003 }, 3165 { 0x01, 0x328a }, 3166 { 0x1f, 0x0000 } 3167 }; 3168 3169 3170 rtl_apply_firmware(tp); 3171 3172 rtl8168f_hw_phy_config(tp); 3173 3174 /* Improve 2-pair detection performance */ 3175 rtl_writephy(tp, 0x1f, 0x0005); 3176 rtl_writephy(tp, 0x05, 0x8b85); 3177 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3178 rtl_writephy(tp, 0x1f, 0x0000); 3179 3180 rtl_writephy_batch(tp, phy_reg_init); 3181 3182 /* Modify green table for giga */ 3183 rtl_writephy(tp, 0x1f, 0x0005); 3184 rtl_writephy(tp, 0x05, 0x8b54); 3185 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3186 rtl_writephy(tp, 0x05, 0x8b5d); 3187 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3188 rtl_writephy(tp, 0x05, 0x8a7c); 3189 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3190 rtl_writephy(tp, 0x05, 0x8a7f); 3191 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000); 3192 rtl_writephy(tp, 0x05, 0x8a82); 3193 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3194 rtl_writephy(tp, 0x05, 0x8a85); 3195 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3196 rtl_writephy(tp, 0x05, 0x8a88); 3197 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3198 rtl_writephy(tp, 0x1f, 0x0000); 3199 3200 /* uc same-seed solution */ 3201 rtl_writephy(tp, 0x1f, 0x0005); 3202 rtl_writephy(tp, 0x05, 0x8b85); 3203 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000); 3204 rtl_writephy(tp, 0x1f, 0x0000); 3205 3206 /* Green feature */ 3207 rtl_writephy(tp, 0x1f, 0x0003); 3208 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); 3209 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); 3210 rtl_writephy(tp, 0x1f, 0x0000); 3211 } 3212 3213 static void rtl8168g_disable_aldps(struct rtl8169_private *tp) 3214 { 3215 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0); 3216 } 3217 3218 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp) 3219 { 3220 struct phy_device *phydev = tp->phydev; 3221 3222 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 3223 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 3224 phy_write(phydev, 0x1f, 0x0a43); 3225 phy_write(phydev, 0x13, 0x8084); 3226 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13)); 3227 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0)); 3228 3229 phy_write(phydev, 0x1f, 0x0000); 3230 } 3231 3232 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) 3233 { 3234 int ret; 3235 3236 rtl_apply_firmware(tp); 3237 3238 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10); 3239 if (ret & BIT(8)) 3240 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0); 3241 else 3242 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15)); 3243 3244 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13); 3245 if (ret & BIT(8)) 3246 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1)); 3247 else 3248 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0); 3249 3250 /* Enable PHY auto speed down */ 3251 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3252 3253 rtl8168g_phy_adjust_10m_aldps(tp); 3254 3255 /* EEE auto-fallback function */ 3256 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3257 3258 /* Enable UC LPF tune function */ 3259 rtl_writephy(tp, 0x1f, 0x0a43); 3260 rtl_writephy(tp, 0x13, 0x8012); 3261 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3262 3263 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3264 3265 /* Improve SWR Efficiency */ 3266 rtl_writephy(tp, 0x1f, 0x0bcd); 3267 rtl_writephy(tp, 0x14, 0x5065); 3268 rtl_writephy(tp, 0x14, 0xd065); 3269 rtl_writephy(tp, 0x1f, 0x0bc8); 3270 rtl_writephy(tp, 0x11, 0x5655); 3271 rtl_writephy(tp, 0x1f, 0x0bcd); 3272 rtl_writephy(tp, 0x14, 0x1065); 3273 rtl_writephy(tp, 0x14, 0x9065); 3274 rtl_writephy(tp, 0x14, 0x1065); 3275 rtl_writephy(tp, 0x1f, 0x0000); 3276 3277 rtl8168g_disable_aldps(tp); 3278 rtl8168g_config_eee_phy(tp); 3279 rtl_enable_eee(tp); 3280 } 3281 3282 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) 3283 { 3284 rtl_apply_firmware(tp); 3285 rtl8168g_config_eee_phy(tp); 3286 rtl_enable_eee(tp); 3287 } 3288 3289 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) 3290 { 3291 u16 dout_tapbin; 3292 u32 data; 3293 3294 rtl_apply_firmware(tp); 3295 3296 /* CHN EST parameters adjust - giga master */ 3297 rtl_writephy(tp, 0x1f, 0x0a43); 3298 rtl_writephy(tp, 0x13, 0x809b); 3299 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800); 3300 rtl_writephy(tp, 0x13, 0x80a2); 3301 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00); 3302 rtl_writephy(tp, 0x13, 0x80a4); 3303 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00); 3304 rtl_writephy(tp, 0x13, 0x809c); 3305 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00); 3306 rtl_writephy(tp, 0x1f, 0x0000); 3307 3308 /* CHN EST parameters adjust - giga slave */ 3309 rtl_writephy(tp, 0x1f, 0x0a43); 3310 rtl_writephy(tp, 0x13, 0x80ad); 3311 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800); 3312 rtl_writephy(tp, 0x13, 0x80b4); 3313 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00); 3314 rtl_writephy(tp, 0x13, 0x80ac); 3315 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00); 3316 rtl_writephy(tp, 0x1f, 0x0000); 3317 3318 /* CHN EST parameters adjust - fnet */ 3319 rtl_writephy(tp, 0x1f, 0x0a43); 3320 rtl_writephy(tp, 0x13, 0x808e); 3321 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00); 3322 rtl_writephy(tp, 0x13, 0x8090); 3323 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00); 3324 rtl_writephy(tp, 0x13, 0x8092); 3325 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00); 3326 rtl_writephy(tp, 0x1f, 0x0000); 3327 3328 /* enable R-tune & PGA-retune function */ 3329 dout_tapbin = 0; 3330 rtl_writephy(tp, 0x1f, 0x0a46); 3331 data = rtl_readphy(tp, 0x13); 3332 data &= 3; 3333 data <<= 2; 3334 dout_tapbin |= data; 3335 data = rtl_readphy(tp, 0x12); 3336 data &= 0xc000; 3337 data >>= 14; 3338 dout_tapbin |= data; 3339 dout_tapbin = ~(dout_tapbin^0x08); 3340 dout_tapbin <<= 12; 3341 dout_tapbin &= 0xf000; 3342 rtl_writephy(tp, 0x1f, 0x0a43); 3343 rtl_writephy(tp, 0x13, 0x827a); 3344 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3345 rtl_writephy(tp, 0x13, 0x827b); 3346 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3347 rtl_writephy(tp, 0x13, 0x827c); 3348 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3349 rtl_writephy(tp, 0x13, 0x827d); 3350 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3351 3352 rtl_writephy(tp, 0x1f, 0x0a43); 3353 rtl_writephy(tp, 0x13, 0x0811); 3354 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3355 rtl_writephy(tp, 0x1f, 0x0a42); 3356 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3357 rtl_writephy(tp, 0x1f, 0x0000); 3358 3359 /* enable GPHY 10M */ 3360 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3361 3362 /* SAR ADC performance */ 3363 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 3364 3365 rtl_writephy(tp, 0x1f, 0x0a43); 3366 rtl_writephy(tp, 0x13, 0x803f); 3367 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3368 rtl_writephy(tp, 0x13, 0x8047); 3369 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3370 rtl_writephy(tp, 0x13, 0x804f); 3371 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3372 rtl_writephy(tp, 0x13, 0x8057); 3373 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3374 rtl_writephy(tp, 0x13, 0x805f); 3375 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3376 rtl_writephy(tp, 0x13, 0x8067); 3377 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3378 rtl_writephy(tp, 0x13, 0x806f); 3379 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3380 rtl_writephy(tp, 0x1f, 0x0000); 3381 3382 /* disable phy pfm mode */ 3383 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3384 3385 rtl8168g_disable_aldps(tp); 3386 rtl8168h_config_eee_phy(tp); 3387 rtl_enable_eee(tp); 3388 } 3389 3390 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) 3391 { 3392 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; 3393 u16 rlen; 3394 u32 data; 3395 3396 rtl_apply_firmware(tp); 3397 3398 /* CHIN EST parameter update */ 3399 rtl_writephy(tp, 0x1f, 0x0a43); 3400 rtl_writephy(tp, 0x13, 0x808a); 3401 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f); 3402 rtl_writephy(tp, 0x1f, 0x0000); 3403 3404 /* enable R-tune & PGA-retune function */ 3405 rtl_writephy(tp, 0x1f, 0x0a43); 3406 rtl_writephy(tp, 0x13, 0x0811); 3407 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3408 rtl_writephy(tp, 0x1f, 0x0a42); 3409 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3410 rtl_writephy(tp, 0x1f, 0x0000); 3411 3412 /* enable GPHY 10M */ 3413 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3414 3415 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 3416 data = r8168_mac_ocp_read(tp, 0xdd02); 3417 ioffset_p3 = ((data & 0x80)>>7); 3418 ioffset_p3 <<= 3; 3419 3420 data = r8168_mac_ocp_read(tp, 0xdd00); 3421 ioffset_p3 |= ((data & (0xe000))>>13); 3422 ioffset_p2 = ((data & (0x1e00))>>9); 3423 ioffset_p1 = ((data & (0x01e0))>>5); 3424 ioffset_p0 = ((data & 0x0010)>>4); 3425 ioffset_p0 <<= 3; 3426 ioffset_p0 |= (data & (0x07)); 3427 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); 3428 3429 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || 3430 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) { 3431 rtl_writephy(tp, 0x1f, 0x0bcf); 3432 rtl_writephy(tp, 0x16, data); 3433 rtl_writephy(tp, 0x1f, 0x0000); 3434 } 3435 3436 /* Modify rlen (TX LPF corner frequency) level */ 3437 rtl_writephy(tp, 0x1f, 0x0bcd); 3438 data = rtl_readphy(tp, 0x16); 3439 data &= 0x000f; 3440 rlen = 0; 3441 if (data > 3) 3442 rlen = data - 3; 3443 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); 3444 rtl_writephy(tp, 0x17, data); 3445 rtl_writephy(tp, 0x1f, 0x0bcd); 3446 rtl_writephy(tp, 0x1f, 0x0000); 3447 3448 /* disable phy pfm mode */ 3449 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3450 3451 rtl8168g_disable_aldps(tp); 3452 rtl8168g_config_eee_phy(tp); 3453 rtl_enable_eee(tp); 3454 } 3455 3456 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) 3457 { 3458 /* Enable PHY auto speed down */ 3459 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3460 3461 rtl8168g_phy_adjust_10m_aldps(tp); 3462 3463 /* Enable EEE auto-fallback function */ 3464 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3465 3466 /* Enable UC LPF tune function */ 3467 rtl_writephy(tp, 0x1f, 0x0a43); 3468 rtl_writephy(tp, 0x13, 0x8012); 3469 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3470 rtl_writephy(tp, 0x1f, 0x0000); 3471 3472 /* set rg_sel_sdm_rate */ 3473 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3474 3475 rtl8168g_disable_aldps(tp); 3476 rtl8168g_config_eee_phy(tp); 3477 rtl_enable_eee(tp); 3478 } 3479 3480 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) 3481 { 3482 rtl8168g_phy_adjust_10m_aldps(tp); 3483 3484 /* Enable UC LPF tune function */ 3485 rtl_writephy(tp, 0x1f, 0x0a43); 3486 rtl_writephy(tp, 0x13, 0x8012); 3487 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3488 rtl_writephy(tp, 0x1f, 0x0000); 3489 3490 /* Set rg_sel_sdm_rate */ 3491 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3492 3493 /* Channel estimation parameters */ 3494 rtl_writephy(tp, 0x1f, 0x0a43); 3495 rtl_writephy(tp, 0x13, 0x80f3); 3496 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff); 3497 rtl_writephy(tp, 0x13, 0x80f0); 3498 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff); 3499 rtl_writephy(tp, 0x13, 0x80ef); 3500 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff); 3501 rtl_writephy(tp, 0x13, 0x80f6); 3502 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff); 3503 rtl_writephy(tp, 0x13, 0x80ec); 3504 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff); 3505 rtl_writephy(tp, 0x13, 0x80ed); 3506 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3507 rtl_writephy(tp, 0x13, 0x80f2); 3508 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff); 3509 rtl_writephy(tp, 0x13, 0x80f4); 3510 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff); 3511 rtl_writephy(tp, 0x1f, 0x0a43); 3512 rtl_writephy(tp, 0x13, 0x8110); 3513 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff); 3514 rtl_writephy(tp, 0x13, 0x810f); 3515 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff); 3516 rtl_writephy(tp, 0x13, 0x8111); 3517 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff); 3518 rtl_writephy(tp, 0x13, 0x8113); 3519 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff); 3520 rtl_writephy(tp, 0x13, 0x8115); 3521 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff); 3522 rtl_writephy(tp, 0x13, 0x810e); 3523 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff); 3524 rtl_writephy(tp, 0x13, 0x810c); 3525 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3526 rtl_writephy(tp, 0x13, 0x810b); 3527 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff); 3528 rtl_writephy(tp, 0x1f, 0x0a43); 3529 rtl_writephy(tp, 0x13, 0x80d1); 3530 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff); 3531 rtl_writephy(tp, 0x13, 0x80cd); 3532 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff); 3533 rtl_writephy(tp, 0x13, 0x80d3); 3534 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff); 3535 rtl_writephy(tp, 0x13, 0x80d5); 3536 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff); 3537 rtl_writephy(tp, 0x13, 0x80d7); 3538 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff); 3539 3540 /* Force PWM-mode */ 3541 rtl_writephy(tp, 0x1f, 0x0bcd); 3542 rtl_writephy(tp, 0x14, 0x5065); 3543 rtl_writephy(tp, 0x14, 0xd065); 3544 rtl_writephy(tp, 0x1f, 0x0bc8); 3545 rtl_writephy(tp, 0x12, 0x00ed); 3546 rtl_writephy(tp, 0x1f, 0x0bcd); 3547 rtl_writephy(tp, 0x14, 0x1065); 3548 rtl_writephy(tp, 0x14, 0x9065); 3549 rtl_writephy(tp, 0x14, 0x1065); 3550 rtl_writephy(tp, 0x1f, 0x0000); 3551 3552 rtl8168g_disable_aldps(tp); 3553 rtl8168g_config_eee_phy(tp); 3554 rtl_enable_eee(tp); 3555 } 3556 3557 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) 3558 { 3559 static const struct phy_reg phy_reg_init[] = { 3560 { 0x1f, 0x0003 }, 3561 { 0x08, 0x441d }, 3562 { 0x01, 0x9100 }, 3563 { 0x1f, 0x0000 } 3564 }; 3565 3566 rtl_writephy(tp, 0x1f, 0x0000); 3567 rtl_patchphy(tp, 0x11, 1 << 12); 3568 rtl_patchphy(tp, 0x19, 1 << 13); 3569 rtl_patchphy(tp, 0x10, 1 << 15); 3570 3571 rtl_writephy_batch(tp, phy_reg_init); 3572 } 3573 3574 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) 3575 { 3576 static const struct phy_reg phy_reg_init[] = { 3577 { 0x1f, 0x0005 }, 3578 { 0x1a, 0x0000 }, 3579 { 0x1f, 0x0000 }, 3580 3581 { 0x1f, 0x0004 }, 3582 { 0x1c, 0x0000 }, 3583 { 0x1f, 0x0000 }, 3584 3585 { 0x1f, 0x0001 }, 3586 { 0x15, 0x7701 }, 3587 { 0x1f, 0x0000 } 3588 }; 3589 3590 /* Disable ALDPS before ram code */ 3591 rtl_writephy(tp, 0x1f, 0x0000); 3592 rtl_writephy(tp, 0x18, 0x0310); 3593 msleep(100); 3594 3595 rtl_apply_firmware(tp); 3596 3597 rtl_writephy_batch(tp, phy_reg_init); 3598 } 3599 3600 static void rtl8402_hw_phy_config(struct rtl8169_private *tp) 3601 { 3602 /* Disable ALDPS before setting firmware */ 3603 rtl_writephy(tp, 0x1f, 0x0000); 3604 rtl_writephy(tp, 0x18, 0x0310); 3605 msleep(20); 3606 3607 rtl_apply_firmware(tp); 3608 3609 /* EEE setting */ 3610 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3611 rtl_writephy(tp, 0x1f, 0x0004); 3612 rtl_writephy(tp, 0x10, 0x401f); 3613 rtl_writephy(tp, 0x19, 0x7030); 3614 rtl_writephy(tp, 0x1f, 0x0000); 3615 } 3616 3617 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) 3618 { 3619 static const struct phy_reg phy_reg_init[] = { 3620 { 0x1f, 0x0004 }, 3621 { 0x10, 0xc07f }, 3622 { 0x19, 0x7030 }, 3623 { 0x1f, 0x0000 } 3624 }; 3625 3626 /* Disable ALDPS before ram code */ 3627 rtl_writephy(tp, 0x1f, 0x0000); 3628 rtl_writephy(tp, 0x18, 0x0310); 3629 msleep(100); 3630 3631 rtl_apply_firmware(tp); 3632 3633 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3634 rtl_writephy_batch(tp, phy_reg_init); 3635 3636 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3637 } 3638 3639 static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp) 3640 { 3641 struct phy_device *phydev = tp->phydev; 3642 3643 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084); 3644 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3645 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006); 3646 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3647 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100); 3648 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000); 3649 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400); 3650 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff); 3651 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff); 3652 3653 phy_write(phydev, 0x1f, 0x0a43); 3654 phy_write(phydev, 0x13, 0x80ea); 3655 phy_modify(phydev, 0x14, 0xff00, 0xc400); 3656 phy_write(phydev, 0x13, 0x80eb); 3657 phy_modify(phydev, 0x14, 0x0700, 0x0300); 3658 phy_write(phydev, 0x13, 0x80f8); 3659 phy_modify(phydev, 0x14, 0xff00, 0x1c00); 3660 phy_write(phydev, 0x13, 0x80f1); 3661 phy_modify(phydev, 0x14, 0xff00, 0x3000); 3662 phy_write(phydev, 0x13, 0x80fe); 3663 phy_modify(phydev, 0x14, 0xff00, 0xa500); 3664 phy_write(phydev, 0x13, 0x8102); 3665 phy_modify(phydev, 0x14, 0xff00, 0x5000); 3666 phy_write(phydev, 0x13, 0x8105); 3667 phy_modify(phydev, 0x14, 0xff00, 0x3300); 3668 phy_write(phydev, 0x13, 0x8100); 3669 phy_modify(phydev, 0x14, 0xff00, 0x7000); 3670 phy_write(phydev, 0x13, 0x8104); 3671 phy_modify(phydev, 0x14, 0xff00, 0xf000); 3672 phy_write(phydev, 0x13, 0x8106); 3673 phy_modify(phydev, 0x14, 0xff00, 0x6500); 3674 phy_write(phydev, 0x13, 0x80dc); 3675 phy_modify(phydev, 0x14, 0xff00, 0xed00); 3676 phy_write(phydev, 0x13, 0x80df); 3677 phy_set_bits(phydev, 0x14, BIT(8)); 3678 phy_write(phydev, 0x13, 0x80e1); 3679 phy_clear_bits(phydev, 0x14, BIT(8)); 3680 phy_write(phydev, 0x1f, 0x0000); 3681 3682 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038); 3683 phy_write_paged(phydev, 0xa43, 0x13, 0x819f); 3684 phy_write_paged(phydev, 0xa43, 0x14, 0xd0b6); 3685 3686 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555); 3687 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00); 3688 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000); 3689 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3690 3691 rtl8125_config_eee_phy(tp); 3692 rtl_enable_eee(tp); 3693 } 3694 3695 static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp) 3696 { 3697 struct phy_device *phydev = tp->phydev; 3698 int i; 3699 3700 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3701 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 3702 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3703 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 3704 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 3705 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 3706 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 3707 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 3708 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 3709 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 3710 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 3711 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 3712 3713 phy_write(phydev, 0x1f, 0x0b87); 3714 phy_write(phydev, 0x16, 0x80a2); 3715 phy_write(phydev, 0x17, 0x0153); 3716 phy_write(phydev, 0x16, 0x809c); 3717 phy_write(phydev, 0x17, 0x0153); 3718 phy_write(phydev, 0x1f, 0x0000); 3719 3720 phy_write(phydev, 0x1f, 0x0a43); 3721 phy_write(phydev, 0x13, 0x81B3); 3722 phy_write(phydev, 0x14, 0x0043); 3723 phy_write(phydev, 0x14, 0x00A7); 3724 phy_write(phydev, 0x14, 0x00D6); 3725 phy_write(phydev, 0x14, 0x00EC); 3726 phy_write(phydev, 0x14, 0x00F6); 3727 phy_write(phydev, 0x14, 0x00FB); 3728 phy_write(phydev, 0x14, 0x00FD); 3729 phy_write(phydev, 0x14, 0x00FF); 3730 phy_write(phydev, 0x14, 0x00BB); 3731 phy_write(phydev, 0x14, 0x0058); 3732 phy_write(phydev, 0x14, 0x0029); 3733 phy_write(phydev, 0x14, 0x0013); 3734 phy_write(phydev, 0x14, 0x0009); 3735 phy_write(phydev, 0x14, 0x0004); 3736 phy_write(phydev, 0x14, 0x0002); 3737 for (i = 0; i < 25; i++) 3738 phy_write(phydev, 0x14, 0x0000); 3739 3740 phy_write(phydev, 0x13, 0x8257); 3741 phy_write(phydev, 0x14, 0x020F); 3742 3743 phy_write(phydev, 0x13, 0x80EA); 3744 phy_write(phydev, 0x14, 0x7843); 3745 phy_write(phydev, 0x1f, 0x0000); 3746 3747 rtl_apply_firmware(tp); 3748 3749 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 3750 3751 phy_write(phydev, 0x1f, 0x0a43); 3752 phy_write(phydev, 0x13, 0x81a2); 3753 phy_set_bits(phydev, 0x14, BIT(8)); 3754 phy_write(phydev, 0x1f, 0x0000); 3755 3756 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 3757 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 3758 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 3759 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 3760 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 3761 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3762 3763 rtl8125_config_eee_phy(tp); 3764 rtl_enable_eee(tp); 3765 } 3766 3767 static void rtl_hw_phy_config(struct net_device *dev) 3768 { 3769 static const rtl_generic_fct phy_configs[] = { 3770 /* PCI devices. */ 3771 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 3772 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 3773 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 3774 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 3775 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 3776 /* PCI-E devices. */ 3777 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 3778 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 3779 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 3780 [RTL_GIGA_MAC_VER_10] = NULL, 3781 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 3782 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 3783 [RTL_GIGA_MAC_VER_13] = NULL, 3784 [RTL_GIGA_MAC_VER_14] = NULL, 3785 [RTL_GIGA_MAC_VER_15] = NULL, 3786 [RTL_GIGA_MAC_VER_16] = NULL, 3787 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 3788 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 3789 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 3790 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 3791 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 3792 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config, 3793 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 3794 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 3795 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 3796 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 3797 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 3798 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 3799 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 3800 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 3801 [RTL_GIGA_MAC_VER_31] = NULL, 3802 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 3803 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 3804 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 3805 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 3806 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 3807 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 3808 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 3809 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 3810 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 3811 [RTL_GIGA_MAC_VER_41] = NULL, 3812 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 3813 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 3814 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 3815 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 3816 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 3817 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 3818 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 3819 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 3820 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 3821 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 3822 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config, 3823 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config, 3824 }; 3825 struct rtl8169_private *tp = netdev_priv(dev); 3826 3827 if (phy_configs[tp->mac_version]) 3828 phy_configs[tp->mac_version](tp); 3829 } 3830 3831 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 3832 { 3833 if (!test_and_set_bit(flag, tp->wk.flags)) 3834 schedule_work(&tp->wk.work); 3835 } 3836 3837 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 3838 { 3839 rtl_hw_phy_config(dev); 3840 3841 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 3842 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 3843 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 3844 netif_dbg(tp, drv, dev, 3845 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 3846 RTL_W8(tp, 0x82, 0x01); 3847 } 3848 3849 /* We may have called phy_speed_down before */ 3850 phy_speed_up(tp->phydev); 3851 3852 genphy_soft_reset(tp->phydev); 3853 } 3854 3855 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 3856 { 3857 rtl_lock_work(tp); 3858 3859 rtl_unlock_config_regs(tp); 3860 3861 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 3862 RTL_R32(tp, MAC4); 3863 3864 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3865 RTL_R32(tp, MAC0); 3866 3867 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 3868 rtl_rar_exgmac_set(tp, addr); 3869 3870 rtl_lock_config_regs(tp); 3871 3872 rtl_unlock_work(tp); 3873 } 3874 3875 static int rtl_set_mac_address(struct net_device *dev, void *p) 3876 { 3877 struct rtl8169_private *tp = netdev_priv(dev); 3878 struct device *d = tp_to_dev(tp); 3879 int ret; 3880 3881 ret = eth_mac_addr(dev, p); 3882 if (ret) 3883 return ret; 3884 3885 pm_runtime_get_noresume(d); 3886 3887 if (pm_runtime_active(d)) 3888 rtl_rar_set(tp, dev->dev_addr); 3889 3890 pm_runtime_put_noidle(d); 3891 3892 return 0; 3893 } 3894 3895 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3896 { 3897 struct rtl8169_private *tp = netdev_priv(dev); 3898 3899 if (!netif_running(dev)) 3900 return -ENODEV; 3901 3902 return phy_mii_ioctl(tp->phydev, ifr, cmd); 3903 } 3904 3905 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 3906 { 3907 switch (tp->mac_version) { 3908 case RTL_GIGA_MAC_VER_25: 3909 case RTL_GIGA_MAC_VER_26: 3910 case RTL_GIGA_MAC_VER_29: 3911 case RTL_GIGA_MAC_VER_30: 3912 case RTL_GIGA_MAC_VER_32: 3913 case RTL_GIGA_MAC_VER_33: 3914 case RTL_GIGA_MAC_VER_34: 3915 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51: 3916 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 3917 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 3918 break; 3919 default: 3920 break; 3921 } 3922 } 3923 3924 static void rtl_pll_power_down(struct rtl8169_private *tp) 3925 { 3926 if (r8168_check_dash(tp)) 3927 return; 3928 3929 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 3930 tp->mac_version == RTL_GIGA_MAC_VER_33) 3931 rtl_ephy_write(tp, 0x19, 0xff64); 3932 3933 if (device_may_wakeup(tp_to_dev(tp))) { 3934 phy_speed_down(tp->phydev, false); 3935 rtl_wol_suspend_quirk(tp); 3936 return; 3937 } 3938 3939 switch (tp->mac_version) { 3940 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3941 case RTL_GIGA_MAC_VER_37: 3942 case RTL_GIGA_MAC_VER_39: 3943 case RTL_GIGA_MAC_VER_43: 3944 case RTL_GIGA_MAC_VER_44: 3945 case RTL_GIGA_MAC_VER_45: 3946 case RTL_GIGA_MAC_VER_46: 3947 case RTL_GIGA_MAC_VER_47: 3948 case RTL_GIGA_MAC_VER_48: 3949 case RTL_GIGA_MAC_VER_50: 3950 case RTL_GIGA_MAC_VER_51: 3951 case RTL_GIGA_MAC_VER_60: 3952 case RTL_GIGA_MAC_VER_61: 3953 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3954 break; 3955 case RTL_GIGA_MAC_VER_40: 3956 case RTL_GIGA_MAC_VER_41: 3957 case RTL_GIGA_MAC_VER_49: 3958 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3959 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3960 break; 3961 default: 3962 break; 3963 } 3964 } 3965 3966 static void rtl_pll_power_up(struct rtl8169_private *tp) 3967 { 3968 switch (tp->mac_version) { 3969 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3970 case RTL_GIGA_MAC_VER_37: 3971 case RTL_GIGA_MAC_VER_39: 3972 case RTL_GIGA_MAC_VER_43: 3973 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 3974 break; 3975 case RTL_GIGA_MAC_VER_44: 3976 case RTL_GIGA_MAC_VER_45: 3977 case RTL_GIGA_MAC_VER_46: 3978 case RTL_GIGA_MAC_VER_47: 3979 case RTL_GIGA_MAC_VER_48: 3980 case RTL_GIGA_MAC_VER_50: 3981 case RTL_GIGA_MAC_VER_51: 3982 case RTL_GIGA_MAC_VER_60: 3983 case RTL_GIGA_MAC_VER_61: 3984 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3985 break; 3986 case RTL_GIGA_MAC_VER_40: 3987 case RTL_GIGA_MAC_VER_41: 3988 case RTL_GIGA_MAC_VER_49: 3989 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3990 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3991 break; 3992 default: 3993 break; 3994 } 3995 3996 phy_resume(tp->phydev); 3997 /* give MAC/PHY some time to resume */ 3998 msleep(20); 3999 } 4000 4001 static void rtl_init_rxcfg(struct rtl8169_private *tp) 4002 { 4003 switch (tp->mac_version) { 4004 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4005 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4006 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 4007 break; 4008 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 4009 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 4010 case RTL_GIGA_MAC_VER_38: 4011 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 4012 break; 4013 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 4014 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 4015 break; 4016 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 4017 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 | 4018 RX_DMA_BURST); 4019 break; 4020 default: 4021 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 4022 break; 4023 } 4024 } 4025 4026 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 4027 { 4028 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 4029 } 4030 4031 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 4032 { 4033 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4034 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 4035 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); 4036 } 4037 4038 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 4039 { 4040 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4041 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 4042 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4043 } 4044 4045 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 4046 { 4047 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4048 } 4049 4050 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 4051 { 4052 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4053 } 4054 4055 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 4056 { 4057 RTL_W8(tp, MaxTxPacketSize, 0x3f); 4058 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4059 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 4060 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); 4061 } 4062 4063 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 4064 { 4065 RTL_W8(tp, MaxTxPacketSize, 0x0c); 4066 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4067 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 4068 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4069 } 4070 4071 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) 4072 { 4073 rtl_tx_performance_tweak(tp, 4074 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN); 4075 } 4076 4077 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) 4078 { 4079 rtl_tx_performance_tweak(tp, 4080 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN); 4081 } 4082 4083 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 4084 { 4085 r8168b_0_hw_jumbo_enable(tp); 4086 4087 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 4088 } 4089 4090 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 4091 { 4092 r8168b_0_hw_jumbo_disable(tp); 4093 4094 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 4095 } 4096 4097 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) 4098 { 4099 rtl_unlock_config_regs(tp); 4100 switch (tp->mac_version) { 4101 case RTL_GIGA_MAC_VER_11: 4102 r8168b_0_hw_jumbo_enable(tp); 4103 break; 4104 case RTL_GIGA_MAC_VER_12: 4105 case RTL_GIGA_MAC_VER_17: 4106 r8168b_1_hw_jumbo_enable(tp); 4107 break; 4108 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 4109 r8168c_hw_jumbo_enable(tp); 4110 break; 4111 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 4112 r8168dp_hw_jumbo_enable(tp); 4113 break; 4114 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4115 r8168e_hw_jumbo_enable(tp); 4116 break; 4117 default: 4118 break; 4119 } 4120 rtl_lock_config_regs(tp); 4121 } 4122 4123 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) 4124 { 4125 rtl_unlock_config_regs(tp); 4126 switch (tp->mac_version) { 4127 case RTL_GIGA_MAC_VER_11: 4128 r8168b_0_hw_jumbo_disable(tp); 4129 break; 4130 case RTL_GIGA_MAC_VER_12: 4131 case RTL_GIGA_MAC_VER_17: 4132 r8168b_1_hw_jumbo_disable(tp); 4133 break; 4134 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 4135 r8168c_hw_jumbo_disable(tp); 4136 break; 4137 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 4138 r8168dp_hw_jumbo_disable(tp); 4139 break; 4140 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4141 r8168e_hw_jumbo_disable(tp); 4142 break; 4143 default: 4144 break; 4145 } 4146 rtl_lock_config_regs(tp); 4147 } 4148 4149 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu) 4150 { 4151 if (mtu > ETH_DATA_LEN) 4152 rtl_hw_jumbo_enable(tp); 4153 else 4154 rtl_hw_jumbo_disable(tp); 4155 } 4156 4157 DECLARE_RTL_COND(rtl_chipcmd_cond) 4158 { 4159 return RTL_R8(tp, ChipCmd) & CmdReset; 4160 } 4161 4162 static void rtl_hw_reset(struct rtl8169_private *tp) 4163 { 4164 RTL_W8(tp, ChipCmd, CmdReset); 4165 4166 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 4167 } 4168 4169 static void rtl_request_firmware(struct rtl8169_private *tp) 4170 { 4171 struct rtl_fw *rtl_fw; 4172 4173 /* firmware loaded already or no firmware available */ 4174 if (tp->rtl_fw || !tp->fw_name) 4175 return; 4176 4177 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 4178 if (!rtl_fw) { 4179 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 4180 return; 4181 } 4182 4183 rtl_fw->phy_write = rtl_writephy; 4184 rtl_fw->phy_read = rtl_readphy; 4185 rtl_fw->mac_mcu_write = mac_mcu_write; 4186 rtl_fw->mac_mcu_read = mac_mcu_read; 4187 rtl_fw->fw_name = tp->fw_name; 4188 rtl_fw->dev = tp_to_dev(tp); 4189 4190 if (rtl_fw_request_firmware(rtl_fw)) 4191 kfree(rtl_fw); 4192 else 4193 tp->rtl_fw = rtl_fw; 4194 } 4195 4196 static void rtl_rx_close(struct rtl8169_private *tp) 4197 { 4198 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 4199 } 4200 4201 DECLARE_RTL_COND(rtl_npq_cond) 4202 { 4203 return RTL_R8(tp, TxPoll) & NPQ; 4204 } 4205 4206 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 4207 { 4208 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 4209 } 4210 4211 static void rtl8169_hw_reset(struct rtl8169_private *tp) 4212 { 4213 /* Disable interrupts */ 4214 rtl8169_irq_mask_and_ack(tp); 4215 4216 rtl_rx_close(tp); 4217 4218 switch (tp->mac_version) { 4219 case RTL_GIGA_MAC_VER_27: 4220 case RTL_GIGA_MAC_VER_28: 4221 case RTL_GIGA_MAC_VER_31: 4222 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 4223 break; 4224 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4225 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 4226 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4227 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4228 break; 4229 default: 4230 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4231 udelay(100); 4232 break; 4233 } 4234 4235 rtl_hw_reset(tp); 4236 } 4237 4238 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 4239 { 4240 u32 val = TX_DMA_BURST << TxDMAShift | 4241 InterFrameGap << TxInterFrameGapShift; 4242 4243 if (rtl_is_8168evl_up(tp)) 4244 val |= TXCFG_AUTO_FIFO; 4245 4246 RTL_W32(tp, TxConfig, val); 4247 } 4248 4249 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 4250 { 4251 /* Low hurts. Let's disable the filtering. */ 4252 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 4253 } 4254 4255 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 4256 { 4257 /* 4258 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 4259 * register to be written before TxDescAddrLow to work. 4260 * Switching from MMIO to I/O access fixes the issue as well. 4261 */ 4262 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 4263 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 4264 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 4265 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 4266 } 4267 4268 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 4269 { 4270 u32 val; 4271 4272 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 4273 val = 0x000fff00; 4274 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 4275 val = 0x00ffff00; 4276 else 4277 return; 4278 4279 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 4280 val |= 0xff; 4281 4282 RTL_W32(tp, 0x7c, val); 4283 } 4284 4285 static void rtl_set_rx_mode(struct net_device *dev) 4286 { 4287 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 4288 /* Multicast hash filter */ 4289 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 4290 struct rtl8169_private *tp = netdev_priv(dev); 4291 u32 tmp; 4292 4293 if (dev->flags & IFF_PROMISC) { 4294 /* Unconditionally log net taps. */ 4295 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 4296 rx_mode |= AcceptAllPhys; 4297 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 4298 dev->flags & IFF_ALLMULTI || 4299 tp->mac_version == RTL_GIGA_MAC_VER_35) { 4300 /* accept all multicasts */ 4301 } else if (netdev_mc_empty(dev)) { 4302 rx_mode &= ~AcceptMulticast; 4303 } else { 4304 struct netdev_hw_addr *ha; 4305 4306 mc_filter[1] = mc_filter[0] = 0; 4307 netdev_for_each_mc_addr(ha, dev) { 4308 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 4309 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 4310 } 4311 4312 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 4313 tmp = mc_filter[0]; 4314 mc_filter[0] = swab32(mc_filter[1]); 4315 mc_filter[1] = swab32(tmp); 4316 } 4317 } 4318 4319 if (dev->features & NETIF_F_RXALL) 4320 rx_mode |= (AcceptErr | AcceptRunt); 4321 4322 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 4323 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 4324 4325 tmp = RTL_R32(tp, RxConfig); 4326 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); 4327 } 4328 4329 DECLARE_RTL_COND(rtl_csiar_cond) 4330 { 4331 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 4332 } 4333 4334 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 4335 { 4336 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4337 4338 RTL_W32(tp, CSIDR, value); 4339 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 4340 CSIAR_BYTE_ENABLE | func << 16); 4341 4342 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 4343 } 4344 4345 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 4346 { 4347 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4348 4349 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 4350 CSIAR_BYTE_ENABLE); 4351 4352 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 4353 RTL_R32(tp, CSIDR) : ~0; 4354 } 4355 4356 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 4357 { 4358 struct pci_dev *pdev = tp->pci_dev; 4359 u32 csi; 4360 4361 /* According to Realtek the value at config space address 0x070f 4362 * controls the L0s/L1 entrance latency. We try standard ECAM access 4363 * first and if it fails fall back to CSI. 4364 */ 4365 if (pdev->cfg_size > 0x070f && 4366 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 4367 return; 4368 4369 netdev_notice_once(tp->dev, 4370 "No native access to PCI extended config space, falling back to CSI\n"); 4371 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 4372 rtl_csi_write(tp, 0x070c, csi | val << 24); 4373 } 4374 4375 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 4376 { 4377 rtl_csi_access_enable(tp, 0x27); 4378 } 4379 4380 struct ephy_info { 4381 unsigned int offset; 4382 u16 mask; 4383 u16 bits; 4384 }; 4385 4386 static void __rtl_ephy_init(struct rtl8169_private *tp, 4387 const struct ephy_info *e, int len) 4388 { 4389 u16 w; 4390 4391 while (len-- > 0) { 4392 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 4393 rtl_ephy_write(tp, e->offset, w); 4394 e++; 4395 } 4396 } 4397 4398 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 4399 4400 static void rtl_disable_clock_request(struct rtl8169_private *tp) 4401 { 4402 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 4403 PCI_EXP_LNKCTL_CLKREQ_EN); 4404 } 4405 4406 static void rtl_enable_clock_request(struct rtl8169_private *tp) 4407 { 4408 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 4409 PCI_EXP_LNKCTL_CLKREQ_EN); 4410 } 4411 4412 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 4413 { 4414 /* work around an issue when PCI reset occurs during L2/L3 state */ 4415 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 4416 } 4417 4418 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 4419 { 4420 /* Don't enable ASPM in the chip if OS can't control ASPM */ 4421 if (enable && tp->aspm_manageable) { 4422 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 4423 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 4424 } else { 4425 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4426 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4427 } 4428 4429 udelay(10); 4430 } 4431 4432 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 4433 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 4434 { 4435 /* Usage of dynamic vs. static FIFO is controlled by bit 4436 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 4437 */ 4438 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 4439 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 4440 } 4441 4442 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 4443 u8 low, u8 high) 4444 { 4445 /* FIFO thresholds for pause flow control */ 4446 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 4447 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 4448 } 4449 4450 static void rtl_hw_start_8168bb(struct rtl8169_private *tp) 4451 { 4452 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4453 } 4454 4455 static void rtl_hw_start_8168bef(struct rtl8169_private *tp) 4456 { 4457 rtl_hw_start_8168bb(tp); 4458 4459 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 4460 } 4461 4462 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 4463 { 4464 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 4465 4466 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4467 4468 rtl_disable_clock_request(tp); 4469 } 4470 4471 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 4472 { 4473 static const struct ephy_info e_info_8168cp[] = { 4474 { 0x01, 0, 0x0001 }, 4475 { 0x02, 0x0800, 0x1000 }, 4476 { 0x03, 0, 0x0042 }, 4477 { 0x06, 0x0080, 0x0000 }, 4478 { 0x07, 0, 0x2000 } 4479 }; 4480 4481 rtl_set_def_aspm_entry_latency(tp); 4482 4483 rtl_ephy_init(tp, e_info_8168cp); 4484 4485 __rtl_hw_start_8168cp(tp); 4486 } 4487 4488 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 4489 { 4490 rtl_set_def_aspm_entry_latency(tp); 4491 4492 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4493 } 4494 4495 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 4496 { 4497 rtl_set_def_aspm_entry_latency(tp); 4498 4499 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4500 4501 /* Magic. */ 4502 RTL_W8(tp, DBG_REG, 0x20); 4503 } 4504 4505 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 4506 { 4507 static const struct ephy_info e_info_8168c_1[] = { 4508 { 0x02, 0x0800, 0x1000 }, 4509 { 0x03, 0, 0x0002 }, 4510 { 0x06, 0x0080, 0x0000 } 4511 }; 4512 4513 rtl_set_def_aspm_entry_latency(tp); 4514 4515 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 4516 4517 rtl_ephy_init(tp, e_info_8168c_1); 4518 4519 __rtl_hw_start_8168cp(tp); 4520 } 4521 4522 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 4523 { 4524 static const struct ephy_info e_info_8168c_2[] = { 4525 { 0x01, 0, 0x0001 }, 4526 { 0x03, 0x0400, 0x0020 } 4527 }; 4528 4529 rtl_set_def_aspm_entry_latency(tp); 4530 4531 rtl_ephy_init(tp, e_info_8168c_2); 4532 4533 __rtl_hw_start_8168cp(tp); 4534 } 4535 4536 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 4537 { 4538 rtl_hw_start_8168c_2(tp); 4539 } 4540 4541 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 4542 { 4543 rtl_set_def_aspm_entry_latency(tp); 4544 4545 __rtl_hw_start_8168cp(tp); 4546 } 4547 4548 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 4549 { 4550 rtl_set_def_aspm_entry_latency(tp); 4551 4552 rtl_disable_clock_request(tp); 4553 4554 if (tp->dev->mtu <= ETH_DATA_LEN) 4555 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4556 } 4557 4558 static void rtl_hw_start_8168dp(struct rtl8169_private *tp) 4559 { 4560 rtl_set_def_aspm_entry_latency(tp); 4561 4562 if (tp->dev->mtu <= ETH_DATA_LEN) 4563 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4564 4565 rtl_disable_clock_request(tp); 4566 } 4567 4568 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 4569 { 4570 static const struct ephy_info e_info_8168d_4[] = { 4571 { 0x0b, 0x0000, 0x0048 }, 4572 { 0x19, 0x0020, 0x0050 }, 4573 { 0x0c, 0x0100, 0x0020 }, 4574 { 0x10, 0x0004, 0x0000 }, 4575 }; 4576 4577 rtl_set_def_aspm_entry_latency(tp); 4578 4579 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4580 4581 rtl_ephy_init(tp, e_info_8168d_4); 4582 4583 rtl_enable_clock_request(tp); 4584 } 4585 4586 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 4587 { 4588 static const struct ephy_info e_info_8168e_1[] = { 4589 { 0x00, 0x0200, 0x0100 }, 4590 { 0x00, 0x0000, 0x0004 }, 4591 { 0x06, 0x0002, 0x0001 }, 4592 { 0x06, 0x0000, 0x0030 }, 4593 { 0x07, 0x0000, 0x2000 }, 4594 { 0x00, 0x0000, 0x0020 }, 4595 { 0x03, 0x5800, 0x2000 }, 4596 { 0x03, 0x0000, 0x0001 }, 4597 { 0x01, 0x0800, 0x1000 }, 4598 { 0x07, 0x0000, 0x4000 }, 4599 { 0x1e, 0x0000, 0x2000 }, 4600 { 0x19, 0xffff, 0xfe6c }, 4601 { 0x0a, 0x0000, 0x0040 } 4602 }; 4603 4604 rtl_set_def_aspm_entry_latency(tp); 4605 4606 rtl_ephy_init(tp, e_info_8168e_1); 4607 4608 rtl_disable_clock_request(tp); 4609 4610 /* Reset tx FIFO pointer */ 4611 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 4612 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 4613 4614 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4615 } 4616 4617 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 4618 { 4619 static const struct ephy_info e_info_8168e_2[] = { 4620 { 0x09, 0x0000, 0x0080 }, 4621 { 0x19, 0x0000, 0x0224 }, 4622 { 0x00, 0x0000, 0x0004 }, 4623 { 0x0c, 0x3df0, 0x0200 }, 4624 }; 4625 4626 rtl_set_def_aspm_entry_latency(tp); 4627 4628 rtl_ephy_init(tp, e_info_8168e_2); 4629 4630 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4631 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4632 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4633 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4634 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 4635 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4636 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4637 4638 rtl_disable_clock_request(tp); 4639 4640 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4641 4642 rtl8168_config_eee_mac(tp); 4643 4644 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4645 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4646 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4647 4648 rtl_hw_aspm_clkreq_enable(tp, true); 4649 } 4650 4651 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 4652 { 4653 rtl_set_def_aspm_entry_latency(tp); 4654 4655 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4656 4657 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4658 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4659 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4660 rtl_reset_packet_filter(tp); 4661 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4662 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 4663 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4664 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 4665 4666 rtl_disable_clock_request(tp); 4667 4668 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4669 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4670 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4671 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4672 4673 rtl8168_config_eee_mac(tp); 4674 } 4675 4676 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 4677 { 4678 static const struct ephy_info e_info_8168f_1[] = { 4679 { 0x06, 0x00c0, 0x0020 }, 4680 { 0x08, 0x0001, 0x0002 }, 4681 { 0x09, 0x0000, 0x0080 }, 4682 { 0x19, 0x0000, 0x0224 }, 4683 { 0x00, 0x0000, 0x0004 }, 4684 { 0x0c, 0x3df0, 0x0200 }, 4685 }; 4686 4687 rtl_hw_start_8168f(tp); 4688 4689 rtl_ephy_init(tp, e_info_8168f_1); 4690 4691 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4692 } 4693 4694 static void rtl_hw_start_8411(struct rtl8169_private *tp) 4695 { 4696 static const struct ephy_info e_info_8168f_1[] = { 4697 { 0x06, 0x00c0, 0x0020 }, 4698 { 0x0f, 0xffff, 0x5200 }, 4699 { 0x19, 0x0000, 0x0224 }, 4700 { 0x00, 0x0000, 0x0004 }, 4701 { 0x0c, 0x3df0, 0x0200 }, 4702 }; 4703 4704 rtl_hw_start_8168f(tp); 4705 rtl_pcie_state_l2l3_disable(tp); 4706 4707 rtl_ephy_init(tp, e_info_8168f_1); 4708 4709 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 4710 } 4711 4712 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 4713 { 4714 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4715 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4716 4717 rtl_set_def_aspm_entry_latency(tp); 4718 4719 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4720 4721 rtl_reset_packet_filter(tp); 4722 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 4723 4724 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4725 4726 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4727 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4728 4729 rtl8168_config_eee_mac(tp); 4730 4731 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4732 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4733 4734 rtl_pcie_state_l2l3_disable(tp); 4735 } 4736 4737 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 4738 { 4739 static const struct ephy_info e_info_8168g_1[] = { 4740 { 0x00, 0x0008, 0x0000 }, 4741 { 0x0c, 0x3ff0, 0x0820 }, 4742 { 0x1e, 0x0000, 0x0001 }, 4743 { 0x19, 0x8000, 0x0000 } 4744 }; 4745 4746 rtl_hw_start_8168g(tp); 4747 4748 /* disable aspm and clock request before access ephy */ 4749 rtl_hw_aspm_clkreq_enable(tp, false); 4750 rtl_ephy_init(tp, e_info_8168g_1); 4751 rtl_hw_aspm_clkreq_enable(tp, true); 4752 } 4753 4754 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 4755 { 4756 static const struct ephy_info e_info_8168g_2[] = { 4757 { 0x00, 0x0008, 0x0000 }, 4758 { 0x0c, 0x3ff0, 0x0820 }, 4759 { 0x19, 0xffff, 0x7c00 }, 4760 { 0x1e, 0xffff, 0x20eb }, 4761 { 0x0d, 0xffff, 0x1666 }, 4762 { 0x00, 0xffff, 0x10a3 }, 4763 { 0x06, 0xffff, 0xf050 }, 4764 { 0x04, 0x0000, 0x0010 }, 4765 { 0x1d, 0x4000, 0x0000 }, 4766 }; 4767 4768 rtl_hw_start_8168g(tp); 4769 4770 /* disable aspm and clock request before access ephy */ 4771 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4772 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4773 rtl_ephy_init(tp, e_info_8168g_2); 4774 } 4775 4776 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 4777 { 4778 static const struct ephy_info e_info_8411_2[] = { 4779 { 0x00, 0x0008, 0x0000 }, 4780 { 0x0c, 0x37d0, 0x0820 }, 4781 { 0x1e, 0x0000, 0x0001 }, 4782 { 0x19, 0x8021, 0x0000 }, 4783 { 0x1e, 0x0000, 0x2000 }, 4784 { 0x0d, 0x0100, 0x0200 }, 4785 { 0x00, 0x0000, 0x0080 }, 4786 { 0x06, 0x0000, 0x0010 }, 4787 { 0x04, 0x0000, 0x0010 }, 4788 { 0x1d, 0x0000, 0x4000 }, 4789 }; 4790 4791 rtl_hw_start_8168g(tp); 4792 4793 /* disable aspm and clock request before access ephy */ 4794 rtl_hw_aspm_clkreq_enable(tp, false); 4795 rtl_ephy_init(tp, e_info_8411_2); 4796 4797 /* The following Realtek-provided magic fixes an issue with the RX unit 4798 * getting confused after the PHY having been powered-down. 4799 */ 4800 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 4801 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 4802 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 4803 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 4804 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 4805 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 4806 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 4807 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 4808 mdelay(3); 4809 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 4810 4811 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 4812 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 4813 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 4814 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 4815 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 4816 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 4817 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 4818 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 4819 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 4820 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 4821 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 4822 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 4823 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 4824 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 4825 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 4826 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 4827 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 4828 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 4829 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 4830 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 4831 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 4832 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 4833 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 4834 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 4835 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 4836 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 4837 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 4838 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 4839 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 4840 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 4841 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 4842 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 4843 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 4844 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 4845 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 4846 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 4847 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 4848 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 4849 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 4850 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 4851 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 4852 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 4853 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 4854 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 4855 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 4856 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 4857 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 4858 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 4859 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 4860 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 4861 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 4862 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 4863 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 4864 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 4865 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 4866 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 4867 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 4868 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 4869 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 4870 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 4871 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 4872 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 4873 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 4874 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 4875 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 4876 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 4877 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 4878 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 4879 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 4880 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 4881 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 4882 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 4883 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 4884 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 4885 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 4886 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 4887 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 4888 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 4889 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 4890 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 4891 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 4892 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 4893 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 4894 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 4895 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 4896 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 4897 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 4898 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 4899 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 4900 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 4901 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 4902 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 4903 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 4904 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 4905 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 4906 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 4907 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 4908 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 4909 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 4910 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 4911 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 4912 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 4913 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 4914 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 4915 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 4916 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 4917 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 4918 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 4919 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 4920 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 4921 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 4922 4923 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 4924 4925 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 4926 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 4927 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 4928 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 4929 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 4930 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 4931 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 4932 4933 rtl_hw_aspm_clkreq_enable(tp, true); 4934 } 4935 4936 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 4937 { 4938 static const struct ephy_info e_info_8168h_1[] = { 4939 { 0x1e, 0x0800, 0x0001 }, 4940 { 0x1d, 0x0000, 0x0800 }, 4941 { 0x05, 0xffff, 0x2089 }, 4942 { 0x06, 0xffff, 0x5881 }, 4943 { 0x04, 0xffff, 0x854a }, 4944 { 0x01, 0xffff, 0x068b } 4945 }; 4946 int rg_saw_cnt; 4947 4948 /* disable aspm and clock request before access ephy */ 4949 rtl_hw_aspm_clkreq_enable(tp, false); 4950 rtl_ephy_init(tp, e_info_8168h_1); 4951 4952 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4953 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4954 4955 rtl_set_def_aspm_entry_latency(tp); 4956 4957 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4958 4959 rtl_reset_packet_filter(tp); 4960 4961 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 4962 4963 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 4964 4965 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4966 4967 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4968 4969 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4970 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4971 4972 rtl8168_config_eee_mac(tp); 4973 4974 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4975 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4976 4977 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4978 4979 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4980 4981 rtl_pcie_state_l2l3_disable(tp); 4982 4983 rtl_writephy(tp, 0x1f, 0x0c42); 4984 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff); 4985 rtl_writephy(tp, 0x1f, 0x0000); 4986 if (rg_saw_cnt > 0) { 4987 u16 sw_cnt_1ms_ini; 4988 4989 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 4990 sw_cnt_1ms_ini &= 0x0fff; 4991 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 4992 } 4993 4994 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 4995 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 4996 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 4997 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 4998 4999 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 5000 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 5001 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 5002 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 5003 5004 rtl_hw_aspm_clkreq_enable(tp, true); 5005 } 5006 5007 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 5008 { 5009 rtl8168ep_stop_cmac(tp); 5010 5011 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 5012 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 5013 5014 rtl_set_def_aspm_entry_latency(tp); 5015 5016 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5017 5018 rtl_reset_packet_filter(tp); 5019 5020 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 5021 5022 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 5023 5024 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 5025 5026 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 5027 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 5028 5029 rtl8168_config_eee_mac(tp); 5030 5031 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 5032 5033 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 5034 5035 rtl_pcie_state_l2l3_disable(tp); 5036 } 5037 5038 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 5039 { 5040 static const struct ephy_info e_info_8168ep_1[] = { 5041 { 0x00, 0xffff, 0x10ab }, 5042 { 0x06, 0xffff, 0xf030 }, 5043 { 0x08, 0xffff, 0x2006 }, 5044 { 0x0d, 0xffff, 0x1666 }, 5045 { 0x0c, 0x3ff0, 0x0000 } 5046 }; 5047 5048 /* disable aspm and clock request before access ephy */ 5049 rtl_hw_aspm_clkreq_enable(tp, false); 5050 rtl_ephy_init(tp, e_info_8168ep_1); 5051 5052 rtl_hw_start_8168ep(tp); 5053 5054 rtl_hw_aspm_clkreq_enable(tp, true); 5055 } 5056 5057 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 5058 { 5059 static const struct ephy_info e_info_8168ep_2[] = { 5060 { 0x00, 0xffff, 0x10a3 }, 5061 { 0x19, 0xffff, 0xfc00 }, 5062 { 0x1e, 0xffff, 0x20ea } 5063 }; 5064 5065 /* disable aspm and clock request before access ephy */ 5066 rtl_hw_aspm_clkreq_enable(tp, false); 5067 rtl_ephy_init(tp, e_info_8168ep_2); 5068 5069 rtl_hw_start_8168ep(tp); 5070 5071 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5072 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 5073 5074 rtl_hw_aspm_clkreq_enable(tp, true); 5075 } 5076 5077 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 5078 { 5079 static const struct ephy_info e_info_8168ep_3[] = { 5080 { 0x00, 0x0000, 0x0080 }, 5081 { 0x0d, 0x0100, 0x0200 }, 5082 { 0x19, 0x8021, 0x0000 }, 5083 { 0x1e, 0x0000, 0x2000 }, 5084 }; 5085 5086 /* disable aspm and clock request before access ephy */ 5087 rtl_hw_aspm_clkreq_enable(tp, false); 5088 rtl_ephy_init(tp, e_info_8168ep_3); 5089 5090 rtl_hw_start_8168ep(tp); 5091 5092 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5093 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 5094 5095 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 5096 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5097 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5098 5099 rtl_hw_aspm_clkreq_enable(tp, true); 5100 } 5101 5102 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 5103 { 5104 static const struct ephy_info e_info_8102e_1[] = { 5105 { 0x01, 0, 0x6e65 }, 5106 { 0x02, 0, 0x091f }, 5107 { 0x03, 0, 0xc2f9 }, 5108 { 0x06, 0, 0xafb5 }, 5109 { 0x07, 0, 0x0e00 }, 5110 { 0x19, 0, 0xec80 }, 5111 { 0x01, 0, 0x2e65 }, 5112 { 0x01, 0, 0x6e65 } 5113 }; 5114 u8 cfg1; 5115 5116 rtl_set_def_aspm_entry_latency(tp); 5117 5118 RTL_W8(tp, DBG_REG, FIX_NAK_1); 5119 5120 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5121 5122 RTL_W8(tp, Config1, 5123 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 5124 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5125 5126 cfg1 = RTL_R8(tp, Config1); 5127 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 5128 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 5129 5130 rtl_ephy_init(tp, e_info_8102e_1); 5131 } 5132 5133 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 5134 { 5135 rtl_set_def_aspm_entry_latency(tp); 5136 5137 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5138 5139 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 5140 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5141 } 5142 5143 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 5144 { 5145 rtl_hw_start_8102e_2(tp); 5146 5147 rtl_ephy_write(tp, 0x03, 0xc2f9); 5148 } 5149 5150 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 5151 { 5152 static const struct ephy_info e_info_8105e_1[] = { 5153 { 0x07, 0, 0x4000 }, 5154 { 0x19, 0, 0x0200 }, 5155 { 0x19, 0, 0x0020 }, 5156 { 0x1e, 0, 0x2000 }, 5157 { 0x03, 0, 0x0001 }, 5158 { 0x19, 0, 0x0100 }, 5159 { 0x19, 0, 0x0004 }, 5160 { 0x0a, 0, 0x0020 } 5161 }; 5162 5163 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5164 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5165 5166 /* Disable Early Tally Counter */ 5167 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 5168 5169 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5170 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 5171 5172 rtl_ephy_init(tp, e_info_8105e_1); 5173 5174 rtl_pcie_state_l2l3_disable(tp); 5175 } 5176 5177 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 5178 { 5179 rtl_hw_start_8105e_1(tp); 5180 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 5181 } 5182 5183 static void rtl_hw_start_8402(struct rtl8169_private *tp) 5184 { 5185 static const struct ephy_info e_info_8402[] = { 5186 { 0x19, 0xffff, 0xff64 }, 5187 { 0x1e, 0, 0x4000 } 5188 }; 5189 5190 rtl_set_def_aspm_entry_latency(tp); 5191 5192 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5193 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5194 5195 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5196 5197 rtl_ephy_init(tp, e_info_8402); 5198 5199 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5200 5201 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 5202 rtl_reset_packet_filter(tp); 5203 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 5204 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 5205 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 5206 5207 rtl_pcie_state_l2l3_disable(tp); 5208 } 5209 5210 static void rtl_hw_start_8106(struct rtl8169_private *tp) 5211 { 5212 rtl_hw_aspm_clkreq_enable(tp, false); 5213 5214 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5215 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5216 5217 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 5218 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5219 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5220 5221 rtl_pcie_state_l2l3_disable(tp); 5222 rtl_hw_aspm_clkreq_enable(tp, true); 5223 } 5224 5225 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 5226 { 5227 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 5228 } 5229 5230 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 5231 { 5232 rtl_pcie_state_l2l3_disable(tp); 5233 5234 RTL_W16(tp, 0x382, 0x221b); 5235 RTL_W8(tp, 0x4500, 0); 5236 RTL_W16(tp, 0x4800, 0); 5237 5238 /* disable UPS */ 5239 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 5240 5241 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 5242 5243 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 5244 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 5245 5246 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 5247 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5248 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5249 5250 /* disable new tx descriptor format */ 5251 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 5252 5253 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 5254 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 5255 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 5256 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 5257 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 5258 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 5259 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 5260 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 5261 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 5262 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 5263 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 5264 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 5265 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 5266 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 5267 udelay(1); 5268 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 5269 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 5270 5271 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 5272 5273 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 5274 5275 rtl8125_config_eee_mac(tp); 5276 5277 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 5278 udelay(10); 5279 } 5280 5281 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 5282 { 5283 static const struct ephy_info e_info_8125_1[] = { 5284 { 0x01, 0xffff, 0xa812 }, 5285 { 0x09, 0xffff, 0x520c }, 5286 { 0x04, 0xffff, 0xd000 }, 5287 { 0x0d, 0xffff, 0xf702 }, 5288 { 0x0a, 0xffff, 0x8653 }, 5289 { 0x06, 0xffff, 0x001e }, 5290 { 0x08, 0xffff, 0x3595 }, 5291 { 0x20, 0xffff, 0x9455 }, 5292 { 0x21, 0xffff, 0x99ff }, 5293 { 0x02, 0xffff, 0x6046 }, 5294 { 0x29, 0xffff, 0xfe00 }, 5295 { 0x23, 0xffff, 0xab62 }, 5296 5297 { 0x41, 0xffff, 0xa80c }, 5298 { 0x49, 0xffff, 0x520c }, 5299 { 0x44, 0xffff, 0xd000 }, 5300 { 0x4d, 0xffff, 0xf702 }, 5301 { 0x4a, 0xffff, 0x8653 }, 5302 { 0x46, 0xffff, 0x001e }, 5303 { 0x48, 0xffff, 0x3595 }, 5304 { 0x60, 0xffff, 0x9455 }, 5305 { 0x61, 0xffff, 0x99ff }, 5306 { 0x42, 0xffff, 0x6046 }, 5307 { 0x69, 0xffff, 0xfe00 }, 5308 { 0x63, 0xffff, 0xab62 }, 5309 }; 5310 5311 rtl_set_def_aspm_entry_latency(tp); 5312 5313 /* disable aspm and clock request before access ephy */ 5314 rtl_hw_aspm_clkreq_enable(tp, false); 5315 rtl_ephy_init(tp, e_info_8125_1); 5316 5317 rtl_hw_start_8125_common(tp); 5318 } 5319 5320 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 5321 { 5322 static const struct ephy_info e_info_8125_2[] = { 5323 { 0x04, 0xffff, 0xd000 }, 5324 { 0x0a, 0xffff, 0x8653 }, 5325 { 0x23, 0xffff, 0xab66 }, 5326 { 0x20, 0xffff, 0x9455 }, 5327 { 0x21, 0xffff, 0x99ff }, 5328 { 0x29, 0xffff, 0xfe04 }, 5329 5330 { 0x44, 0xffff, 0xd000 }, 5331 { 0x4a, 0xffff, 0x8653 }, 5332 { 0x63, 0xffff, 0xab66 }, 5333 { 0x60, 0xffff, 0x9455 }, 5334 { 0x61, 0xffff, 0x99ff }, 5335 { 0x69, 0xffff, 0xfe04 }, 5336 }; 5337 5338 rtl_set_def_aspm_entry_latency(tp); 5339 5340 /* disable aspm and clock request before access ephy */ 5341 rtl_hw_aspm_clkreq_enable(tp, false); 5342 rtl_ephy_init(tp, e_info_8125_2); 5343 5344 rtl_hw_start_8125_common(tp); 5345 } 5346 5347 static void rtl_hw_config(struct rtl8169_private *tp) 5348 { 5349 static const rtl_generic_fct hw_configs[] = { 5350 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 5351 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 5352 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 5353 [RTL_GIGA_MAC_VER_10] = NULL, 5354 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb, 5355 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef, 5356 [RTL_GIGA_MAC_VER_13] = NULL, 5357 [RTL_GIGA_MAC_VER_14] = NULL, 5358 [RTL_GIGA_MAC_VER_15] = NULL, 5359 [RTL_GIGA_MAC_VER_16] = NULL, 5360 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef, 5361 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 5362 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 5363 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 5364 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 5365 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 5366 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 5367 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 5368 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 5369 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 5370 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 5371 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 5372 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 5373 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 5374 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp, 5375 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 5376 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 5377 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 5378 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 5379 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 5380 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 5381 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 5382 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 5383 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 5384 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 5385 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 5386 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 5387 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 5388 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 5389 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 5390 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 5391 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 5392 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 5393 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 5394 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 5395 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 5396 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 5397 }; 5398 5399 if (hw_configs[tp->mac_version]) 5400 hw_configs[tp->mac_version](tp); 5401 } 5402 5403 static void rtl_hw_start_8125(struct rtl8169_private *tp) 5404 { 5405 int i; 5406 5407 /* disable interrupt coalescing */ 5408 for (i = 0xa00; i < 0xb00; i += 4) 5409 RTL_W32(tp, i, 0); 5410 5411 rtl_hw_config(tp); 5412 } 5413 5414 static void rtl_hw_start_8168(struct rtl8169_private *tp) 5415 { 5416 if (tp->mac_version == RTL_GIGA_MAC_VER_13 || 5417 tp->mac_version == RTL_GIGA_MAC_VER_16) 5418 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, 5419 PCI_EXP_DEVCTL_NOSNOOP_EN); 5420 5421 if (rtl_is_8168evl_up(tp)) 5422 RTL_W8(tp, MaxTxPacketSize, EarlySize); 5423 else 5424 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5425 5426 rtl_hw_config(tp); 5427 5428 /* disable interrupt coalescing */ 5429 RTL_W16(tp, IntrMitigate, 0x0000); 5430 } 5431 5432 static void rtl_hw_start_8169(struct rtl8169_private *tp) 5433 { 5434 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5435 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 5436 5437 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 5438 5439 tp->cp_cmd |= PCIMulRW; 5440 5441 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 5442 tp->mac_version == RTL_GIGA_MAC_VER_03) { 5443 netif_dbg(tp, drv, tp->dev, 5444 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n"); 5445 tp->cp_cmd |= (1 << 14); 5446 } 5447 5448 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5449 5450 rtl8169_set_magic_reg(tp, tp->mac_version); 5451 5452 RTL_W32(tp, RxMissed, 0); 5453 5454 /* disable interrupt coalescing */ 5455 RTL_W16(tp, IntrMitigate, 0x0000); 5456 } 5457 5458 static void rtl_hw_start(struct rtl8169_private *tp) 5459 { 5460 rtl_unlock_config_regs(tp); 5461 5462 tp->cp_cmd &= CPCMD_MASK; 5463 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5464 5465 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5466 rtl_hw_start_8169(tp); 5467 else if (rtl_is_8125(tp)) 5468 rtl_hw_start_8125(tp); 5469 else 5470 rtl_hw_start_8168(tp); 5471 5472 rtl_set_rx_max_size(tp); 5473 rtl_set_rx_tx_desc_registers(tp); 5474 rtl_lock_config_regs(tp); 5475 5476 rtl_jumbo_config(tp, tp->dev->mtu); 5477 5478 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 5479 RTL_R16(tp, CPlusCmd); 5480 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 5481 rtl_init_rxcfg(tp); 5482 rtl_set_tx_config_registers(tp); 5483 rtl_set_rx_mode(tp->dev); 5484 rtl_irq_enable(tp); 5485 } 5486 5487 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 5488 { 5489 struct rtl8169_private *tp = netdev_priv(dev); 5490 5491 rtl_jumbo_config(tp, new_mtu); 5492 5493 dev->mtu = new_mtu; 5494 netdev_update_features(dev); 5495 5496 return 0; 5497 } 5498 5499 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 5500 { 5501 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); 5502 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 5503 } 5504 5505 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 5506 { 5507 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 5508 5509 /* Force memory writes to complete before releasing descriptor */ 5510 dma_wmb(); 5511 5512 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 5513 } 5514 5515 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 5516 struct RxDesc *desc) 5517 { 5518 struct device *d = tp_to_dev(tp); 5519 int node = dev_to_node(d); 5520 dma_addr_t mapping; 5521 struct page *data; 5522 5523 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 5524 if (!data) 5525 return NULL; 5526 5527 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5528 if (unlikely(dma_mapping_error(d, mapping))) { 5529 if (net_ratelimit()) 5530 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 5531 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 5532 return NULL; 5533 } 5534 5535 desc->addr = cpu_to_le64(mapping); 5536 rtl8169_mark_to_asic(desc); 5537 5538 return data; 5539 } 5540 5541 static void rtl8169_rx_clear(struct rtl8169_private *tp) 5542 { 5543 unsigned int i; 5544 5545 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 5546 dma_unmap_page(tp_to_dev(tp), 5547 le64_to_cpu(tp->RxDescArray[i].addr), 5548 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5549 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 5550 tp->Rx_databuff[i] = NULL; 5551 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5552 } 5553 } 5554 5555 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 5556 { 5557 desc->opts1 |= cpu_to_le32(RingEnd); 5558 } 5559 5560 static int rtl8169_rx_fill(struct rtl8169_private *tp) 5561 { 5562 unsigned int i; 5563 5564 for (i = 0; i < NUM_RX_DESC; i++) { 5565 struct page *data; 5566 5567 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 5568 if (!data) { 5569 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5570 goto err_out; 5571 } 5572 tp->Rx_databuff[i] = data; 5573 } 5574 5575 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 5576 return 0; 5577 5578 err_out: 5579 rtl8169_rx_clear(tp); 5580 return -ENOMEM; 5581 } 5582 5583 static int rtl8169_init_ring(struct rtl8169_private *tp) 5584 { 5585 rtl8169_init_ring_indexes(tp); 5586 5587 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 5588 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 5589 5590 return rtl8169_rx_fill(tp); 5591 } 5592 5593 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, 5594 struct TxDesc *desc) 5595 { 5596 unsigned int len = tx_skb->len; 5597 5598 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); 5599 5600 desc->opts1 = 0x00; 5601 desc->opts2 = 0x00; 5602 desc->addr = 0x00; 5603 tx_skb->len = 0; 5604 } 5605 5606 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 5607 unsigned int n) 5608 { 5609 unsigned int i; 5610 5611 for (i = 0; i < n; i++) { 5612 unsigned int entry = (start + i) % NUM_TX_DESC; 5613 struct ring_info *tx_skb = tp->tx_skb + entry; 5614 unsigned int len = tx_skb->len; 5615 5616 if (len) { 5617 struct sk_buff *skb = tx_skb->skb; 5618 5619 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5620 tp->TxDescArray + entry); 5621 if (skb) { 5622 dev_consume_skb_any(skb); 5623 tx_skb->skb = NULL; 5624 } 5625 } 5626 } 5627 } 5628 5629 static void rtl8169_tx_clear(struct rtl8169_private *tp) 5630 { 5631 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 5632 tp->cur_tx = tp->dirty_tx = 0; 5633 netdev_reset_queue(tp->dev); 5634 } 5635 5636 static void rtl_reset_work(struct rtl8169_private *tp) 5637 { 5638 struct net_device *dev = tp->dev; 5639 int i; 5640 5641 napi_disable(&tp->napi); 5642 netif_stop_queue(dev); 5643 synchronize_rcu(); 5644 5645 rtl8169_hw_reset(tp); 5646 5647 for (i = 0; i < NUM_RX_DESC; i++) 5648 rtl8169_mark_to_asic(tp->RxDescArray + i); 5649 5650 rtl8169_tx_clear(tp); 5651 rtl8169_init_ring_indexes(tp); 5652 5653 napi_enable(&tp->napi); 5654 rtl_hw_start(tp); 5655 netif_wake_queue(dev); 5656 } 5657 5658 static void rtl8169_tx_timeout(struct net_device *dev) 5659 { 5660 struct rtl8169_private *tp = netdev_priv(dev); 5661 5662 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5663 } 5664 5665 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry) 5666 { 5667 u32 status = opts0 | len; 5668 5669 if (entry == NUM_TX_DESC - 1) 5670 status |= RingEnd; 5671 5672 return cpu_to_le32(status); 5673 } 5674 5675 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 5676 u32 *opts) 5677 { 5678 struct skb_shared_info *info = skb_shinfo(skb); 5679 unsigned int cur_frag, entry; 5680 struct TxDesc *uninitialized_var(txd); 5681 struct device *d = tp_to_dev(tp); 5682 5683 entry = tp->cur_tx; 5684 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 5685 const skb_frag_t *frag = info->frags + cur_frag; 5686 dma_addr_t mapping; 5687 u32 len; 5688 void *addr; 5689 5690 entry = (entry + 1) % NUM_TX_DESC; 5691 5692 txd = tp->TxDescArray + entry; 5693 len = skb_frag_size(frag); 5694 addr = skb_frag_address(frag); 5695 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 5696 if (unlikely(dma_mapping_error(d, mapping))) { 5697 if (net_ratelimit()) 5698 netif_err(tp, drv, tp->dev, 5699 "Failed to map TX fragments DMA!\n"); 5700 goto err_out; 5701 } 5702 5703 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5704 txd->opts2 = cpu_to_le32(opts[1]); 5705 txd->addr = cpu_to_le64(mapping); 5706 5707 tp->tx_skb[entry].len = len; 5708 } 5709 5710 if (cur_frag) { 5711 tp->tx_skb[entry].skb = skb; 5712 txd->opts1 |= cpu_to_le32(LastFrag); 5713 } 5714 5715 return cur_frag; 5716 5717 err_out: 5718 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 5719 return -EIO; 5720 } 5721 5722 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 5723 { 5724 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 5725 } 5726 5727 /* msdn_giant_send_check() 5728 * According to the document of microsoft, the TCP Pseudo Header excludes the 5729 * packet length for IPv6 TCP large packets. 5730 */ 5731 static int msdn_giant_send_check(struct sk_buff *skb) 5732 { 5733 const struct ipv6hdr *ipv6h; 5734 struct tcphdr *th; 5735 int ret; 5736 5737 ret = skb_cow_head(skb, 0); 5738 if (ret) 5739 return ret; 5740 5741 ipv6h = ipv6_hdr(skb); 5742 th = tcp_hdr(skb); 5743 5744 th->check = 0; 5745 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 5746 5747 return ret; 5748 } 5749 5750 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 5751 { 5752 u32 mss = skb_shinfo(skb)->gso_size; 5753 5754 if (mss) { 5755 opts[0] |= TD_LSO; 5756 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; 5757 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5758 const struct iphdr *ip = ip_hdr(skb); 5759 5760 if (ip->protocol == IPPROTO_TCP) 5761 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 5762 else if (ip->protocol == IPPROTO_UDP) 5763 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 5764 else 5765 WARN_ON_ONCE(1); 5766 } 5767 } 5768 5769 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 5770 struct sk_buff *skb, u32 *opts) 5771 { 5772 u32 transport_offset = (u32)skb_transport_offset(skb); 5773 u32 mss = skb_shinfo(skb)->gso_size; 5774 5775 if (mss) { 5776 switch (vlan_get_protocol(skb)) { 5777 case htons(ETH_P_IP): 5778 opts[0] |= TD1_GTSENV4; 5779 break; 5780 5781 case htons(ETH_P_IPV6): 5782 if (msdn_giant_send_check(skb)) 5783 return false; 5784 5785 opts[0] |= TD1_GTSENV6; 5786 break; 5787 5788 default: 5789 WARN_ON_ONCE(1); 5790 break; 5791 } 5792 5793 opts[0] |= transport_offset << GTTCPHO_SHIFT; 5794 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; 5795 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5796 u8 ip_protocol; 5797 5798 switch (vlan_get_protocol(skb)) { 5799 case htons(ETH_P_IP): 5800 opts[1] |= TD1_IPv4_CS; 5801 ip_protocol = ip_hdr(skb)->protocol; 5802 break; 5803 5804 case htons(ETH_P_IPV6): 5805 opts[1] |= TD1_IPv6_CS; 5806 ip_protocol = ipv6_hdr(skb)->nexthdr; 5807 break; 5808 5809 default: 5810 ip_protocol = IPPROTO_RAW; 5811 break; 5812 } 5813 5814 if (ip_protocol == IPPROTO_TCP) 5815 opts[1] |= TD1_TCP_CS; 5816 else if (ip_protocol == IPPROTO_UDP) 5817 opts[1] |= TD1_UDP_CS; 5818 else 5819 WARN_ON_ONCE(1); 5820 5821 opts[1] |= transport_offset << TCPHO_SHIFT; 5822 } else { 5823 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 5824 return !eth_skb_pad(skb); 5825 } 5826 5827 return true; 5828 } 5829 5830 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 5831 unsigned int nr_frags) 5832 { 5833 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 5834 5835 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 5836 return slots_avail > nr_frags; 5837 } 5838 5839 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 5840 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 5841 { 5842 switch (tp->mac_version) { 5843 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5844 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 5845 return false; 5846 default: 5847 return true; 5848 } 5849 } 5850 5851 static void rtl8169_doorbell(struct rtl8169_private *tp) 5852 { 5853 if (rtl_is_8125(tp)) 5854 RTL_W16(tp, TxPoll_8125, BIT(0)); 5855 else 5856 RTL_W8(tp, TxPoll, NPQ); 5857 } 5858 5859 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 5860 struct net_device *dev) 5861 { 5862 struct rtl8169_private *tp = netdev_priv(dev); 5863 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 5864 struct TxDesc *txd = tp->TxDescArray + entry; 5865 struct device *d = tp_to_dev(tp); 5866 dma_addr_t mapping; 5867 u32 opts[2], len; 5868 bool stop_queue; 5869 bool door_bell; 5870 int frags; 5871 5872 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) { 5873 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 5874 goto err_stop_0; 5875 } 5876 5877 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 5878 goto err_stop_0; 5879 5880 opts[1] = rtl8169_tx_vlan_tag(skb); 5881 opts[0] = DescOwn; 5882 5883 if (rtl_chip_supports_csum_v2(tp)) { 5884 if (!rtl8169_tso_csum_v2(tp, skb, opts)) 5885 goto err_dma_0; 5886 } else { 5887 rtl8169_tso_csum_v1(skb, opts); 5888 } 5889 5890 len = skb_headlen(skb); 5891 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); 5892 if (unlikely(dma_mapping_error(d, mapping))) { 5893 if (net_ratelimit()) 5894 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); 5895 goto err_dma_0; 5896 } 5897 5898 tp->tx_skb[entry].len = len; 5899 txd->addr = cpu_to_le64(mapping); 5900 5901 frags = rtl8169_xmit_frags(tp, skb, opts); 5902 if (frags < 0) 5903 goto err_dma_1; 5904 else if (frags) 5905 opts[0] |= FirstFrag; 5906 else { 5907 opts[0] |= FirstFrag | LastFrag; 5908 tp->tx_skb[entry].skb = skb; 5909 } 5910 5911 txd->opts2 = cpu_to_le32(opts[1]); 5912 5913 skb_tx_timestamp(skb); 5914 5915 /* Force memory writes to complete before releasing descriptor */ 5916 dma_wmb(); 5917 5918 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 5919 5920 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5921 5922 /* Force all memory writes to complete before notifying device */ 5923 wmb(); 5924 5925 tp->cur_tx += frags + 1; 5926 5927 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 5928 if (unlikely(stop_queue)) { 5929 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 5930 * not miss a ring update when it notices a stopped queue. 5931 */ 5932 smp_wmb(); 5933 netif_stop_queue(dev); 5934 door_bell = true; 5935 } 5936 5937 if (door_bell) 5938 rtl8169_doorbell(tp); 5939 5940 if (unlikely(stop_queue)) { 5941 /* Sync with rtl_tx: 5942 * - publish queue status and cur_tx ring index (write barrier) 5943 * - refresh dirty_tx ring index (read barrier). 5944 * May the current thread have a pessimistic view of the ring 5945 * status and forget to wake up queue, a racing rtl_tx thread 5946 * can't. 5947 */ 5948 smp_mb(); 5949 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 5950 netif_start_queue(dev); 5951 } 5952 5953 return NETDEV_TX_OK; 5954 5955 err_dma_1: 5956 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); 5957 err_dma_0: 5958 dev_kfree_skb_any(skb); 5959 dev->stats.tx_dropped++; 5960 return NETDEV_TX_OK; 5961 5962 err_stop_0: 5963 netif_stop_queue(dev); 5964 dev->stats.tx_dropped++; 5965 return NETDEV_TX_BUSY; 5966 } 5967 5968 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 5969 struct net_device *dev, 5970 netdev_features_t features) 5971 { 5972 int transport_offset = skb_transport_offset(skb); 5973 struct rtl8169_private *tp = netdev_priv(dev); 5974 5975 if (skb_is_gso(skb)) { 5976 if (transport_offset > GTTCPHO_MAX && 5977 rtl_chip_supports_csum_v2(tp)) 5978 features &= ~NETIF_F_ALL_TSO; 5979 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5980 if (skb->len < ETH_ZLEN) { 5981 switch (tp->mac_version) { 5982 case RTL_GIGA_MAC_VER_11: 5983 case RTL_GIGA_MAC_VER_12: 5984 case RTL_GIGA_MAC_VER_17: 5985 case RTL_GIGA_MAC_VER_34: 5986 features &= ~NETIF_F_CSUM_MASK; 5987 break; 5988 default: 5989 break; 5990 } 5991 } 5992 5993 if (transport_offset > TCPHO_MAX && 5994 rtl_chip_supports_csum_v2(tp)) 5995 features &= ~NETIF_F_CSUM_MASK; 5996 } 5997 5998 return vlan_features_check(skb, features); 5999 } 6000 6001 static void rtl8169_pcierr_interrupt(struct net_device *dev) 6002 { 6003 struct rtl8169_private *tp = netdev_priv(dev); 6004 struct pci_dev *pdev = tp->pci_dev; 6005 u16 pci_status, pci_cmd; 6006 6007 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 6008 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 6009 6010 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", 6011 pci_cmd, pci_status); 6012 6013 /* 6014 * The recovery sequence below admits a very elaborated explanation: 6015 * - it seems to work; 6016 * - I did not see what else could be done; 6017 * - it makes iop3xx happy. 6018 * 6019 * Feel free to adjust to your needs. 6020 */ 6021 if (pdev->broken_parity_status) 6022 pci_cmd &= ~PCI_COMMAND_PARITY; 6023 else 6024 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 6025 6026 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 6027 6028 pci_write_config_word(pdev, PCI_STATUS, 6029 pci_status & (PCI_STATUS_DETECTED_PARITY | 6030 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | 6031 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); 6032 6033 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 6034 } 6035 6036 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 6037 int budget) 6038 { 6039 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 6040 6041 dirty_tx = tp->dirty_tx; 6042 smp_rmb(); 6043 tx_left = tp->cur_tx - dirty_tx; 6044 6045 while (tx_left > 0) { 6046 unsigned int entry = dirty_tx % NUM_TX_DESC; 6047 struct ring_info *tx_skb = tp->tx_skb + entry; 6048 u32 status; 6049 6050 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 6051 if (status & DescOwn) 6052 break; 6053 6054 /* This barrier is needed to keep us from reading 6055 * any other fields out of the Tx descriptor until 6056 * we know the status of DescOwn 6057 */ 6058 dma_rmb(); 6059 6060 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 6061 tp->TxDescArray + entry); 6062 if (tx_skb->skb) { 6063 pkts_compl++; 6064 bytes_compl += tx_skb->skb->len; 6065 napi_consume_skb(tx_skb->skb, budget); 6066 tx_skb->skb = NULL; 6067 } 6068 dirty_tx++; 6069 tx_left--; 6070 } 6071 6072 if (tp->dirty_tx != dirty_tx) { 6073 netdev_completed_queue(dev, pkts_compl, bytes_compl); 6074 6075 u64_stats_update_begin(&tp->tx_stats.syncp); 6076 tp->tx_stats.packets += pkts_compl; 6077 tp->tx_stats.bytes += bytes_compl; 6078 u64_stats_update_end(&tp->tx_stats.syncp); 6079 6080 tp->dirty_tx = dirty_tx; 6081 /* Sync with rtl8169_start_xmit: 6082 * - publish dirty_tx ring index (write barrier) 6083 * - refresh cur_tx ring index and queue status (read barrier) 6084 * May the current thread miss the stopped queue condition, 6085 * a racing xmit thread can only have a right view of the 6086 * ring status. 6087 */ 6088 smp_mb(); 6089 if (netif_queue_stopped(dev) && 6090 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 6091 netif_wake_queue(dev); 6092 } 6093 /* 6094 * 8168 hack: TxPoll requests are lost when the Tx packets are 6095 * too close. Let's kick an extra TxPoll request when a burst 6096 * of start_xmit activity is detected (if it is not detected, 6097 * it is slow enough). -- FR 6098 */ 6099 if (tp->cur_tx != dirty_tx) 6100 rtl8169_doorbell(tp); 6101 } 6102 } 6103 6104 static inline int rtl8169_fragmented_frame(u32 status) 6105 { 6106 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 6107 } 6108 6109 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 6110 { 6111 u32 status = opts1 & RxProtoMask; 6112 6113 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 6114 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 6115 skb->ip_summed = CHECKSUM_UNNECESSARY; 6116 else 6117 skb_checksum_none_assert(skb); 6118 } 6119 6120 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 6121 { 6122 unsigned int cur_rx, rx_left; 6123 unsigned int count; 6124 6125 cur_rx = tp->cur_rx; 6126 6127 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 6128 unsigned int entry = cur_rx % NUM_RX_DESC; 6129 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 6130 struct RxDesc *desc = tp->RxDescArray + entry; 6131 u32 status; 6132 6133 status = le32_to_cpu(desc->opts1); 6134 if (status & DescOwn) 6135 break; 6136 6137 /* This barrier is needed to keep us from reading 6138 * any other fields out of the Rx descriptor until 6139 * we know the status of DescOwn 6140 */ 6141 dma_rmb(); 6142 6143 if (unlikely(status & RxRES)) { 6144 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 6145 status); 6146 dev->stats.rx_errors++; 6147 if (status & (RxRWT | RxRUNT)) 6148 dev->stats.rx_length_errors++; 6149 if (status & RxCRC) 6150 dev->stats.rx_crc_errors++; 6151 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 6152 dev->features & NETIF_F_RXALL) { 6153 goto process_pkt; 6154 } 6155 } else { 6156 unsigned int pkt_size; 6157 struct sk_buff *skb; 6158 6159 process_pkt: 6160 pkt_size = status & GENMASK(13, 0); 6161 if (likely(!(dev->features & NETIF_F_RXFCS))) 6162 pkt_size -= ETH_FCS_LEN; 6163 /* 6164 * The driver does not support incoming fragmented 6165 * frames. They are seen as a symptom of over-mtu 6166 * sized frames. 6167 */ 6168 if (unlikely(rtl8169_fragmented_frame(status))) { 6169 dev->stats.rx_dropped++; 6170 dev->stats.rx_length_errors++; 6171 goto release_descriptor; 6172 } 6173 6174 skb = napi_alloc_skb(&tp->napi, pkt_size); 6175 if (unlikely(!skb)) { 6176 dev->stats.rx_dropped++; 6177 goto release_descriptor; 6178 } 6179 6180 dma_sync_single_for_cpu(tp_to_dev(tp), 6181 le64_to_cpu(desc->addr), 6182 pkt_size, DMA_FROM_DEVICE); 6183 prefetch(rx_buf); 6184 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 6185 skb->tail += pkt_size; 6186 skb->len = pkt_size; 6187 6188 dma_sync_single_for_device(tp_to_dev(tp), 6189 le64_to_cpu(desc->addr), 6190 pkt_size, DMA_FROM_DEVICE); 6191 6192 rtl8169_rx_csum(skb, status); 6193 skb->protocol = eth_type_trans(skb, dev); 6194 6195 rtl8169_rx_vlan_tag(desc, skb); 6196 6197 if (skb->pkt_type == PACKET_MULTICAST) 6198 dev->stats.multicast++; 6199 6200 napi_gro_receive(&tp->napi, skb); 6201 6202 u64_stats_update_begin(&tp->rx_stats.syncp); 6203 tp->rx_stats.packets++; 6204 tp->rx_stats.bytes += pkt_size; 6205 u64_stats_update_end(&tp->rx_stats.syncp); 6206 } 6207 release_descriptor: 6208 desc->opts2 = 0; 6209 rtl8169_mark_to_asic(desc); 6210 } 6211 6212 count = cur_rx - tp->cur_rx; 6213 tp->cur_rx = cur_rx; 6214 6215 return count; 6216 } 6217 6218 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 6219 { 6220 struct rtl8169_private *tp = dev_instance; 6221 u32 status = rtl_get_events(tp); 6222 6223 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 6224 !(status & tp->irq_mask)) 6225 return IRQ_NONE; 6226 6227 if (unlikely(status & SYSErr)) { 6228 rtl8169_pcierr_interrupt(tp->dev); 6229 goto out; 6230 } 6231 6232 if (status & LinkChg) 6233 phy_mac_interrupt(tp->phydev); 6234 6235 if (unlikely(status & RxFIFOOver && 6236 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 6237 netif_stop_queue(tp->dev); 6238 /* XXX - Hack alert. See rtl_task(). */ 6239 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); 6240 } 6241 6242 rtl_irq_disable(tp); 6243 napi_schedule_irqoff(&tp->napi); 6244 out: 6245 rtl_ack_events(tp, status); 6246 6247 return IRQ_HANDLED; 6248 } 6249 6250 static void rtl_task(struct work_struct *work) 6251 { 6252 static const struct { 6253 int bitnr; 6254 void (*action)(struct rtl8169_private *); 6255 } rtl_work[] = { 6256 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, 6257 }; 6258 struct rtl8169_private *tp = 6259 container_of(work, struct rtl8169_private, wk.work); 6260 struct net_device *dev = tp->dev; 6261 int i; 6262 6263 rtl_lock_work(tp); 6264 6265 if (!netif_running(dev) || 6266 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 6267 goto out_unlock; 6268 6269 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { 6270 bool pending; 6271 6272 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); 6273 if (pending) 6274 rtl_work[i].action(tp); 6275 } 6276 6277 out_unlock: 6278 rtl_unlock_work(tp); 6279 } 6280 6281 static int rtl8169_poll(struct napi_struct *napi, int budget) 6282 { 6283 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 6284 struct net_device *dev = tp->dev; 6285 int work_done; 6286 6287 work_done = rtl_rx(dev, tp, (u32) budget); 6288 6289 rtl_tx(dev, tp, budget); 6290 6291 if (work_done < budget) { 6292 napi_complete_done(napi, work_done); 6293 rtl_irq_enable(tp); 6294 } 6295 6296 return work_done; 6297 } 6298 6299 static void rtl8169_rx_missed(struct net_device *dev) 6300 { 6301 struct rtl8169_private *tp = netdev_priv(dev); 6302 6303 if (tp->mac_version > RTL_GIGA_MAC_VER_06) 6304 return; 6305 6306 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff; 6307 RTL_W32(tp, RxMissed, 0); 6308 } 6309 6310 static void r8169_phylink_handler(struct net_device *ndev) 6311 { 6312 struct rtl8169_private *tp = netdev_priv(ndev); 6313 6314 if (netif_carrier_ok(ndev)) { 6315 rtl_link_chg_patch(tp); 6316 pm_request_resume(&tp->pci_dev->dev); 6317 } else { 6318 pm_runtime_idle(&tp->pci_dev->dev); 6319 } 6320 6321 if (net_ratelimit()) 6322 phy_print_status(tp->phydev); 6323 } 6324 6325 static int r8169_phy_connect(struct rtl8169_private *tp) 6326 { 6327 struct phy_device *phydev = tp->phydev; 6328 phy_interface_t phy_mode; 6329 int ret; 6330 6331 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 6332 PHY_INTERFACE_MODE_MII; 6333 6334 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 6335 phy_mode); 6336 if (ret) 6337 return ret; 6338 6339 if (!tp->supports_gmii) 6340 phy_set_max_speed(phydev, SPEED_100); 6341 6342 phy_support_asym_pause(phydev); 6343 6344 phy_attached_info(phydev); 6345 6346 return 0; 6347 } 6348 6349 static void rtl8169_down(struct net_device *dev) 6350 { 6351 struct rtl8169_private *tp = netdev_priv(dev); 6352 6353 phy_stop(tp->phydev); 6354 6355 napi_disable(&tp->napi); 6356 netif_stop_queue(dev); 6357 6358 rtl8169_hw_reset(tp); 6359 /* 6360 * At this point device interrupts can not be enabled in any function, 6361 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) 6362 * and napi is disabled (rtl8169_poll). 6363 */ 6364 rtl8169_rx_missed(dev); 6365 6366 /* Give a racing hard_start_xmit a few cycles to complete. */ 6367 synchronize_rcu(); 6368 6369 rtl8169_tx_clear(tp); 6370 6371 rtl8169_rx_clear(tp); 6372 6373 rtl_pll_power_down(tp); 6374 } 6375 6376 static int rtl8169_close(struct net_device *dev) 6377 { 6378 struct rtl8169_private *tp = netdev_priv(dev); 6379 struct pci_dev *pdev = tp->pci_dev; 6380 6381 pm_runtime_get_sync(&pdev->dev); 6382 6383 /* Update counters before going down */ 6384 rtl8169_update_counters(tp); 6385 6386 rtl_lock_work(tp); 6387 /* Clear all task flags */ 6388 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6389 6390 rtl8169_down(dev); 6391 rtl_unlock_work(tp); 6392 6393 cancel_work_sync(&tp->wk.work); 6394 6395 phy_disconnect(tp->phydev); 6396 6397 pci_free_irq(pdev, 0, tp); 6398 6399 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6400 tp->RxPhyAddr); 6401 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6402 tp->TxPhyAddr); 6403 tp->TxDescArray = NULL; 6404 tp->RxDescArray = NULL; 6405 6406 pm_runtime_put_sync(&pdev->dev); 6407 6408 return 0; 6409 } 6410 6411 #ifdef CONFIG_NET_POLL_CONTROLLER 6412 static void rtl8169_netpoll(struct net_device *dev) 6413 { 6414 struct rtl8169_private *tp = netdev_priv(dev); 6415 6416 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 6417 } 6418 #endif 6419 6420 static int rtl_open(struct net_device *dev) 6421 { 6422 struct rtl8169_private *tp = netdev_priv(dev); 6423 struct pci_dev *pdev = tp->pci_dev; 6424 int retval = -ENOMEM; 6425 6426 pm_runtime_get_sync(&pdev->dev); 6427 6428 /* 6429 * Rx and Tx descriptors needs 256 bytes alignment. 6430 * dma_alloc_coherent provides more. 6431 */ 6432 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 6433 &tp->TxPhyAddr, GFP_KERNEL); 6434 if (!tp->TxDescArray) 6435 goto err_pm_runtime_put; 6436 6437 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 6438 &tp->RxPhyAddr, GFP_KERNEL); 6439 if (!tp->RxDescArray) 6440 goto err_free_tx_0; 6441 6442 retval = rtl8169_init_ring(tp); 6443 if (retval < 0) 6444 goto err_free_rx_1; 6445 6446 rtl_request_firmware(tp); 6447 6448 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 6449 dev->name); 6450 if (retval < 0) 6451 goto err_release_fw_2; 6452 6453 retval = r8169_phy_connect(tp); 6454 if (retval) 6455 goto err_free_irq; 6456 6457 rtl_lock_work(tp); 6458 6459 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6460 6461 napi_enable(&tp->napi); 6462 6463 rtl8169_init_phy(dev, tp); 6464 6465 rtl_pll_power_up(tp); 6466 6467 rtl_hw_start(tp); 6468 6469 if (!rtl8169_init_counter_offsets(tp)) 6470 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 6471 6472 phy_start(tp->phydev); 6473 netif_start_queue(dev); 6474 6475 rtl_unlock_work(tp); 6476 6477 pm_runtime_put_sync(&pdev->dev); 6478 out: 6479 return retval; 6480 6481 err_free_irq: 6482 pci_free_irq(pdev, 0, tp); 6483 err_release_fw_2: 6484 rtl_release_firmware(tp); 6485 rtl8169_rx_clear(tp); 6486 err_free_rx_1: 6487 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6488 tp->RxPhyAddr); 6489 tp->RxDescArray = NULL; 6490 err_free_tx_0: 6491 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6492 tp->TxPhyAddr); 6493 tp->TxDescArray = NULL; 6494 err_pm_runtime_put: 6495 pm_runtime_put_noidle(&pdev->dev); 6496 goto out; 6497 } 6498 6499 static void 6500 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6501 { 6502 struct rtl8169_private *tp = netdev_priv(dev); 6503 struct pci_dev *pdev = tp->pci_dev; 6504 struct rtl8169_counters *counters = tp->counters; 6505 unsigned int start; 6506 6507 pm_runtime_get_noresume(&pdev->dev); 6508 6509 if (netif_running(dev) && pm_runtime_active(&pdev->dev)) 6510 rtl8169_rx_missed(dev); 6511 6512 do { 6513 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 6514 stats->rx_packets = tp->rx_stats.packets; 6515 stats->rx_bytes = tp->rx_stats.bytes; 6516 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 6517 6518 do { 6519 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 6520 stats->tx_packets = tp->tx_stats.packets; 6521 stats->tx_bytes = tp->tx_stats.bytes; 6522 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 6523 6524 stats->rx_dropped = dev->stats.rx_dropped; 6525 stats->tx_dropped = dev->stats.tx_dropped; 6526 stats->rx_length_errors = dev->stats.rx_length_errors; 6527 stats->rx_errors = dev->stats.rx_errors; 6528 stats->rx_crc_errors = dev->stats.rx_crc_errors; 6529 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 6530 stats->rx_missed_errors = dev->stats.rx_missed_errors; 6531 stats->multicast = dev->stats.multicast; 6532 6533 /* 6534 * Fetch additional counter values missing in stats collected by driver 6535 * from tally counters. 6536 */ 6537 if (pm_runtime_active(&pdev->dev)) 6538 rtl8169_update_counters(tp); 6539 6540 /* 6541 * Subtract values fetched during initalization. 6542 * See rtl8169_init_counter_offsets for a description why we do that. 6543 */ 6544 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 6545 le64_to_cpu(tp->tc_offset.tx_errors); 6546 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 6547 le32_to_cpu(tp->tc_offset.tx_multi_collision); 6548 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 6549 le16_to_cpu(tp->tc_offset.tx_aborted); 6550 6551 pm_runtime_put_noidle(&pdev->dev); 6552 } 6553 6554 static void rtl8169_net_suspend(struct net_device *dev) 6555 { 6556 struct rtl8169_private *tp = netdev_priv(dev); 6557 6558 if (!netif_running(dev)) 6559 return; 6560 6561 phy_stop(tp->phydev); 6562 netif_device_detach(dev); 6563 6564 rtl_lock_work(tp); 6565 napi_disable(&tp->napi); 6566 /* Clear all task flags */ 6567 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6568 6569 rtl_unlock_work(tp); 6570 6571 rtl_pll_power_down(tp); 6572 } 6573 6574 #ifdef CONFIG_PM 6575 6576 static int rtl8169_suspend(struct device *device) 6577 { 6578 struct net_device *dev = dev_get_drvdata(device); 6579 struct rtl8169_private *tp = netdev_priv(dev); 6580 6581 rtl8169_net_suspend(dev); 6582 clk_disable_unprepare(tp->clk); 6583 6584 return 0; 6585 } 6586 6587 static void __rtl8169_resume(struct net_device *dev) 6588 { 6589 struct rtl8169_private *tp = netdev_priv(dev); 6590 6591 netif_device_attach(dev); 6592 6593 rtl_pll_power_up(tp); 6594 rtl8169_init_phy(dev, tp); 6595 6596 phy_start(tp->phydev); 6597 6598 rtl_lock_work(tp); 6599 napi_enable(&tp->napi); 6600 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6601 rtl_reset_work(tp); 6602 rtl_unlock_work(tp); 6603 } 6604 6605 static int rtl8169_resume(struct device *device) 6606 { 6607 struct net_device *dev = dev_get_drvdata(device); 6608 struct rtl8169_private *tp = netdev_priv(dev); 6609 6610 rtl_rar_set(tp, dev->dev_addr); 6611 6612 clk_prepare_enable(tp->clk); 6613 6614 if (netif_running(dev)) 6615 __rtl8169_resume(dev); 6616 6617 return 0; 6618 } 6619 6620 static int rtl8169_runtime_suspend(struct device *device) 6621 { 6622 struct net_device *dev = dev_get_drvdata(device); 6623 struct rtl8169_private *tp = netdev_priv(dev); 6624 6625 if (!tp->TxDescArray) 6626 return 0; 6627 6628 rtl_lock_work(tp); 6629 __rtl8169_set_wol(tp, WAKE_ANY); 6630 rtl_unlock_work(tp); 6631 6632 rtl8169_net_suspend(dev); 6633 6634 /* Update counters before going runtime suspend */ 6635 rtl8169_rx_missed(dev); 6636 rtl8169_update_counters(tp); 6637 6638 return 0; 6639 } 6640 6641 static int rtl8169_runtime_resume(struct device *device) 6642 { 6643 struct net_device *dev = dev_get_drvdata(device); 6644 struct rtl8169_private *tp = netdev_priv(dev); 6645 6646 rtl_rar_set(tp, dev->dev_addr); 6647 6648 if (!tp->TxDescArray) 6649 return 0; 6650 6651 rtl_lock_work(tp); 6652 __rtl8169_set_wol(tp, tp->saved_wolopts); 6653 rtl_unlock_work(tp); 6654 6655 __rtl8169_resume(dev); 6656 6657 return 0; 6658 } 6659 6660 static int rtl8169_runtime_idle(struct device *device) 6661 { 6662 struct net_device *dev = dev_get_drvdata(device); 6663 6664 if (!netif_running(dev) || !netif_carrier_ok(dev)) 6665 pm_schedule_suspend(device, 10000); 6666 6667 return -EBUSY; 6668 } 6669 6670 static const struct dev_pm_ops rtl8169_pm_ops = { 6671 .suspend = rtl8169_suspend, 6672 .resume = rtl8169_resume, 6673 .freeze = rtl8169_suspend, 6674 .thaw = rtl8169_resume, 6675 .poweroff = rtl8169_suspend, 6676 .restore = rtl8169_resume, 6677 .runtime_suspend = rtl8169_runtime_suspend, 6678 .runtime_resume = rtl8169_runtime_resume, 6679 .runtime_idle = rtl8169_runtime_idle, 6680 }; 6681 6682 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 6683 6684 #else /* !CONFIG_PM */ 6685 6686 #define RTL8169_PM_OPS NULL 6687 6688 #endif /* !CONFIG_PM */ 6689 6690 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 6691 { 6692 /* WoL fails with 8168b when the receiver is disabled. */ 6693 switch (tp->mac_version) { 6694 case RTL_GIGA_MAC_VER_11: 6695 case RTL_GIGA_MAC_VER_12: 6696 case RTL_GIGA_MAC_VER_17: 6697 pci_clear_master(tp->pci_dev); 6698 6699 RTL_W8(tp, ChipCmd, CmdRxEnb); 6700 /* PCI commit */ 6701 RTL_R8(tp, ChipCmd); 6702 break; 6703 default: 6704 break; 6705 } 6706 } 6707 6708 static void rtl_shutdown(struct pci_dev *pdev) 6709 { 6710 struct net_device *dev = pci_get_drvdata(pdev); 6711 struct rtl8169_private *tp = netdev_priv(dev); 6712 6713 rtl8169_net_suspend(dev); 6714 6715 /* Restore original MAC address */ 6716 rtl_rar_set(tp, dev->perm_addr); 6717 6718 rtl8169_hw_reset(tp); 6719 6720 if (system_state == SYSTEM_POWER_OFF) { 6721 if (tp->saved_wolopts) { 6722 rtl_wol_suspend_quirk(tp); 6723 rtl_wol_shutdown_quirk(tp); 6724 } 6725 6726 pci_wake_from_d3(pdev, true); 6727 pci_set_power_state(pdev, PCI_D3hot); 6728 } 6729 } 6730 6731 static void rtl_remove_one(struct pci_dev *pdev) 6732 { 6733 struct net_device *dev = pci_get_drvdata(pdev); 6734 struct rtl8169_private *tp = netdev_priv(dev); 6735 6736 if (r8168_check_dash(tp)) 6737 rtl8168_driver_stop(tp); 6738 6739 netif_napi_del(&tp->napi); 6740 6741 unregister_netdev(dev); 6742 mdiobus_unregister(tp->phydev->mdio.bus); 6743 6744 rtl_release_firmware(tp); 6745 6746 if (pci_dev_run_wake(pdev)) 6747 pm_runtime_get_noresume(&pdev->dev); 6748 6749 /* restore original MAC address */ 6750 rtl_rar_set(tp, dev->perm_addr); 6751 } 6752 6753 static const struct net_device_ops rtl_netdev_ops = { 6754 .ndo_open = rtl_open, 6755 .ndo_stop = rtl8169_close, 6756 .ndo_get_stats64 = rtl8169_get_stats64, 6757 .ndo_start_xmit = rtl8169_start_xmit, 6758 .ndo_features_check = rtl8169_features_check, 6759 .ndo_tx_timeout = rtl8169_tx_timeout, 6760 .ndo_validate_addr = eth_validate_addr, 6761 .ndo_change_mtu = rtl8169_change_mtu, 6762 .ndo_fix_features = rtl8169_fix_features, 6763 .ndo_set_features = rtl8169_set_features, 6764 .ndo_set_mac_address = rtl_set_mac_address, 6765 .ndo_do_ioctl = rtl8169_ioctl, 6766 .ndo_set_rx_mode = rtl_set_rx_mode, 6767 #ifdef CONFIG_NET_POLL_CONTROLLER 6768 .ndo_poll_controller = rtl8169_netpoll, 6769 #endif 6770 6771 }; 6772 6773 static void rtl_set_irq_mask(struct rtl8169_private *tp) 6774 { 6775 tp->irq_mask = RTL_EVENT_NAPI | LinkChg; 6776 6777 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 6778 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 6779 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 6780 /* special workaround needed */ 6781 tp->irq_mask |= RxFIFOOver; 6782 else 6783 tp->irq_mask |= RxOverflow; 6784 } 6785 6786 static int rtl_alloc_irq(struct rtl8169_private *tp) 6787 { 6788 unsigned int flags; 6789 6790 switch (tp->mac_version) { 6791 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6792 rtl_unlock_config_regs(tp); 6793 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 6794 rtl_lock_config_regs(tp); 6795 /* fall through */ 6796 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24: 6797 flags = PCI_IRQ_LEGACY; 6798 break; 6799 default: 6800 flags = PCI_IRQ_ALL_TYPES; 6801 break; 6802 } 6803 6804 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 6805 } 6806 6807 static void rtl_read_mac_address(struct rtl8169_private *tp, 6808 u8 mac_addr[ETH_ALEN]) 6809 { 6810 /* Get MAC address */ 6811 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 6812 u32 value = rtl_eri_read(tp, 0xe0); 6813 6814 mac_addr[0] = (value >> 0) & 0xff; 6815 mac_addr[1] = (value >> 8) & 0xff; 6816 mac_addr[2] = (value >> 16) & 0xff; 6817 mac_addr[3] = (value >> 24) & 0xff; 6818 6819 value = rtl_eri_read(tp, 0xe4); 6820 mac_addr[4] = (value >> 0) & 0xff; 6821 mac_addr[5] = (value >> 8) & 0xff; 6822 } else if (rtl_is_8125(tp)) { 6823 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 6824 } 6825 } 6826 6827 DECLARE_RTL_COND(rtl_link_list_ready_cond) 6828 { 6829 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 6830 } 6831 6832 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 6833 { 6834 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 6835 } 6836 6837 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 6838 { 6839 struct rtl8169_private *tp = mii_bus->priv; 6840 6841 if (phyaddr > 0) 6842 return -ENODEV; 6843 6844 return rtl_readphy(tp, phyreg); 6845 } 6846 6847 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 6848 int phyreg, u16 val) 6849 { 6850 struct rtl8169_private *tp = mii_bus->priv; 6851 6852 if (phyaddr > 0) 6853 return -ENODEV; 6854 6855 rtl_writephy(tp, phyreg, val); 6856 6857 return 0; 6858 } 6859 6860 static int r8169_mdio_register(struct rtl8169_private *tp) 6861 { 6862 struct pci_dev *pdev = tp->pci_dev; 6863 struct mii_bus *new_bus; 6864 int ret; 6865 6866 new_bus = devm_mdiobus_alloc(&pdev->dev); 6867 if (!new_bus) 6868 return -ENOMEM; 6869 6870 new_bus->name = "r8169"; 6871 new_bus->priv = tp; 6872 new_bus->parent = &pdev->dev; 6873 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 6874 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 6875 6876 new_bus->read = r8169_mdio_read_reg; 6877 new_bus->write = r8169_mdio_write_reg; 6878 6879 ret = mdiobus_register(new_bus); 6880 if (ret) 6881 return ret; 6882 6883 tp->phydev = mdiobus_get_phy(new_bus, 0); 6884 if (!tp->phydev) { 6885 mdiobus_unregister(new_bus); 6886 return -ENODEV; 6887 } 6888 6889 /* PHY will be woken up in rtl_open() */ 6890 phy_suspend(tp->phydev); 6891 6892 return 0; 6893 } 6894 6895 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 6896 { 6897 tp->ocp_base = OCP_STD_PHY_BASE; 6898 6899 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6900 6901 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 6902 return; 6903 6904 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6905 return; 6906 6907 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6908 msleep(1); 6909 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6910 6911 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6912 6913 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6914 return; 6915 6916 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 6917 6918 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6919 } 6920 6921 static void rtl_hw_init_8125(struct rtl8169_private *tp) 6922 { 6923 tp->ocp_base = OCP_STD_PHY_BASE; 6924 6925 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6926 6927 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6928 return; 6929 6930 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6931 msleep(1); 6932 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6933 6934 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6935 6936 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6937 return; 6938 6939 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 6940 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 6941 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 6942 6943 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6944 } 6945 6946 static void rtl_hw_initialize(struct rtl8169_private *tp) 6947 { 6948 switch (tp->mac_version) { 6949 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51: 6950 rtl8168ep_stop_cmac(tp); 6951 /* fall through */ 6952 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 6953 rtl_hw_init_8168g(tp); 6954 break; 6955 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 6956 rtl_hw_init_8125(tp); 6957 break; 6958 default: 6959 break; 6960 } 6961 } 6962 6963 static int rtl_jumbo_max(struct rtl8169_private *tp) 6964 { 6965 /* Non-GBit versions don't support jumbo frames */ 6966 if (!tp->supports_gmii) 6967 return JUMBO_1K; 6968 6969 switch (tp->mac_version) { 6970 /* RTL8169 */ 6971 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6972 return JUMBO_7K; 6973 /* RTL8168b */ 6974 case RTL_GIGA_MAC_VER_11: 6975 case RTL_GIGA_MAC_VER_12: 6976 case RTL_GIGA_MAC_VER_17: 6977 return JUMBO_4K; 6978 /* RTL8168c */ 6979 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 6980 return JUMBO_6K; 6981 default: 6982 return JUMBO_9K; 6983 } 6984 } 6985 6986 static void rtl_disable_clk(void *data) 6987 { 6988 clk_disable_unprepare(data); 6989 } 6990 6991 static int rtl_get_ether_clk(struct rtl8169_private *tp) 6992 { 6993 struct device *d = tp_to_dev(tp); 6994 struct clk *clk; 6995 int rc; 6996 6997 clk = devm_clk_get(d, "ether_clk"); 6998 if (IS_ERR(clk)) { 6999 rc = PTR_ERR(clk); 7000 if (rc == -ENOENT) 7001 /* clk-core allows NULL (for suspend / resume) */ 7002 rc = 0; 7003 else if (rc != -EPROBE_DEFER) 7004 dev_err(d, "failed to get clk: %d\n", rc); 7005 } else { 7006 tp->clk = clk; 7007 rc = clk_prepare_enable(clk); 7008 if (rc) 7009 dev_err(d, "failed to enable clk: %d\n", rc); 7010 else 7011 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 7012 } 7013 7014 return rc; 7015 } 7016 7017 static void rtl_init_mac_address(struct rtl8169_private *tp) 7018 { 7019 struct net_device *dev = tp->dev; 7020 u8 *mac_addr = dev->dev_addr; 7021 int rc; 7022 7023 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 7024 if (!rc) 7025 goto done; 7026 7027 rtl_read_mac_address(tp, mac_addr); 7028 if (is_valid_ether_addr(mac_addr)) 7029 goto done; 7030 7031 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 7032 if (is_valid_ether_addr(mac_addr)) 7033 goto done; 7034 7035 eth_hw_addr_random(dev); 7036 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 7037 done: 7038 rtl_rar_set(tp, mac_addr); 7039 } 7040 7041 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 7042 { 7043 struct rtl8169_private *tp; 7044 struct net_device *dev; 7045 int chipset, region; 7046 int jumbo_max, rc; 7047 7048 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 7049 if (!dev) 7050 return -ENOMEM; 7051 7052 SET_NETDEV_DEV(dev, &pdev->dev); 7053 dev->netdev_ops = &rtl_netdev_ops; 7054 tp = netdev_priv(dev); 7055 tp->dev = dev; 7056 tp->pci_dev = pdev; 7057 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 7058 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 7059 7060 /* Get the *optional* external "ether_clk" used on some boards */ 7061 rc = rtl_get_ether_clk(tp); 7062 if (rc) 7063 return rc; 7064 7065 /* Disable ASPM completely as that cause random device stop working 7066 * problems as well as full system hangs for some PCIe devices users. 7067 */ 7068 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 7069 PCIE_LINK_STATE_L1); 7070 tp->aspm_manageable = !rc; 7071 7072 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 7073 rc = pcim_enable_device(pdev); 7074 if (rc < 0) { 7075 dev_err(&pdev->dev, "enable failure\n"); 7076 return rc; 7077 } 7078 7079 if (pcim_set_mwi(pdev) < 0) 7080 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 7081 7082 /* use first MMIO region */ 7083 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 7084 if (region < 0) { 7085 dev_err(&pdev->dev, "no MMIO resource found\n"); 7086 return -ENODEV; 7087 } 7088 7089 /* check for weird/broken PCI region reporting */ 7090 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 7091 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 7092 return -ENODEV; 7093 } 7094 7095 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 7096 if (rc < 0) { 7097 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 7098 return rc; 7099 } 7100 7101 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 7102 7103 /* Identify chip attached to board */ 7104 rtl8169_get_mac_version(tp); 7105 if (tp->mac_version == RTL_GIGA_MAC_NONE) 7106 return -ENODEV; 7107 7108 tp->cp_cmd = RTL_R16(tp, CPlusCmd); 7109 7110 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 7111 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 7112 dev->features |= NETIF_F_HIGHDMA; 7113 7114 rtl_init_rxcfg(tp); 7115 7116 rtl8169_irq_mask_and_ack(tp); 7117 7118 rtl_hw_initialize(tp); 7119 7120 rtl_hw_reset(tp); 7121 7122 pci_set_master(pdev); 7123 7124 chipset = tp->mac_version; 7125 7126 rc = rtl_alloc_irq(tp); 7127 if (rc < 0) { 7128 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 7129 return rc; 7130 } 7131 7132 mutex_init(&tp->wk.mutex); 7133 INIT_WORK(&tp->wk.work, rtl_task); 7134 u64_stats_init(&tp->rx_stats.syncp); 7135 u64_stats_init(&tp->tx_stats.syncp); 7136 7137 rtl_init_mac_address(tp); 7138 7139 dev->ethtool_ops = &rtl8169_ethtool_ops; 7140 7141 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 7142 7143 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7144 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 7145 NETIF_F_HW_VLAN_CTAG_RX; 7146 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7147 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 7148 NETIF_F_HW_VLAN_CTAG_RX; 7149 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7150 NETIF_F_HIGHDMA; 7151 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 7152 7153 tp->cp_cmd |= RxChkSum; 7154 /* RTL8125 uses register RxConfig for VLAN offloading config */ 7155 if (!rtl_is_8125(tp)) 7156 tp->cp_cmd |= RxVlan; 7157 /* 7158 * Pretend we are using VLANs; This bypasses a nasty bug where 7159 * Interrupts stop flowing on high load on 8110SCd controllers. 7160 */ 7161 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 7162 /* Disallow toggling */ 7163 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 7164 7165 if (rtl_chip_supports_csum_v2(tp)) { 7166 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 7167 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 7168 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 7169 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 7170 } else { 7171 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 7172 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 7173 } 7174 7175 /* RTL8168e-vl has a HW issue with TSO */ 7176 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { 7177 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7178 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7179 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7180 } 7181 7182 dev->hw_features |= NETIF_F_RXALL; 7183 dev->hw_features |= NETIF_F_RXFCS; 7184 7185 /* MTU range: 60 - hw-specific max */ 7186 dev->min_mtu = ETH_ZLEN; 7187 jumbo_max = rtl_jumbo_max(tp); 7188 dev->max_mtu = jumbo_max; 7189 7190 rtl_set_irq_mask(tp); 7191 7192 tp->fw_name = rtl_chip_infos[chipset].fw_name; 7193 7194 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 7195 &tp->counters_phys_addr, 7196 GFP_KERNEL); 7197 if (!tp->counters) 7198 return -ENOMEM; 7199 7200 pci_set_drvdata(pdev, dev); 7201 7202 rc = r8169_mdio_register(tp); 7203 if (rc) 7204 return rc; 7205 7206 /* chip gets powered up in rtl_open() */ 7207 rtl_pll_power_down(tp); 7208 7209 rc = register_netdev(dev); 7210 if (rc) 7211 goto err_mdio_unregister; 7212 7213 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 7214 rtl_chip_infos[chipset].name, dev->dev_addr, 7215 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf, 7216 pci_irq_vector(pdev, 0)); 7217 7218 if (jumbo_max > JUMBO_1K) 7219 netif_info(tp, probe, dev, 7220 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 7221 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 7222 "ok" : "ko"); 7223 7224 if (r8168_check_dash(tp)) 7225 rtl8168_driver_start(tp); 7226 7227 if (pci_dev_run_wake(pdev)) 7228 pm_runtime_put_sync(&pdev->dev); 7229 7230 return 0; 7231 7232 err_mdio_unregister: 7233 mdiobus_unregister(tp->phydev->mdio.bus); 7234 return rc; 7235 } 7236 7237 static struct pci_driver rtl8169_pci_driver = { 7238 .name = MODULENAME, 7239 .id_table = rtl8169_pci_tbl, 7240 .probe = rtl_init_one, 7241 .remove = rtl_remove_one, 7242 .shutdown = rtl_shutdown, 7243 .driver.pm = RTL8169_PM_OPS, 7244 }; 7245 7246 module_pci_driver(rtl8169_pci_driver); 7247