1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 52 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 53 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 54 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 55 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 56 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 57 58 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 59 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 60 #define MC_FILTER_LIMIT 32 61 62 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 63 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 64 65 #define R8169_REGS_SIZE 256 66 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 67 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 68 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 69 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 70 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 71 72 #define OCP_STD_PHY_BASE 0xa400 73 74 #define RTL_CFG_NO_GBIT 1 75 76 /* write/read MMIO register */ 77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 83 84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 89 static const struct { 90 const char *name; 91 const char *fw_name; 92 } rtl_chip_infos[] = { 93 /* PCI devices. */ 94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 99 /* PCI-E devices. */ 100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 105 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 106 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 107 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 108 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 143 }; 144 145 static const struct pci_device_id rtl8169_pci_tbl[] = { 146 { PCI_VDEVICE(REALTEK, 0x2502) }, 147 { PCI_VDEVICE(REALTEK, 0x2600) }, 148 { PCI_VDEVICE(REALTEK, 0x8129) }, 149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 150 { PCI_VDEVICE(REALTEK, 0x8161) }, 151 { PCI_VDEVICE(REALTEK, 0x8162) }, 152 { PCI_VDEVICE(REALTEK, 0x8167) }, 153 { PCI_VDEVICE(REALTEK, 0x8168) }, 154 { PCI_VDEVICE(NCUBE, 0x8168) }, 155 { PCI_VDEVICE(REALTEK, 0x8169) }, 156 { PCI_VENDOR_ID_DLINK, 0x4300, 157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 158 { PCI_VDEVICE(DLINK, 0x4300) }, 159 { PCI_VDEVICE(DLINK, 0x4302) }, 160 { PCI_VDEVICE(AT, 0xc107) }, 161 { PCI_VDEVICE(USR, 0x0116) }, 162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 164 { PCI_VDEVICE(REALTEK, 0x8125) }, 165 { PCI_VDEVICE(REALTEK, 0x3000) }, 166 {} 167 }; 168 169 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 170 171 enum rtl_registers { 172 MAC0 = 0, /* Ethernet hardware address. */ 173 MAC4 = 4, 174 MAR0 = 8, /* Multicast filter. */ 175 CounterAddrLow = 0x10, 176 CounterAddrHigh = 0x14, 177 TxDescStartAddrLow = 0x20, 178 TxDescStartAddrHigh = 0x24, 179 TxHDescStartAddrLow = 0x28, 180 TxHDescStartAddrHigh = 0x2c, 181 FLASH = 0x30, 182 ERSR = 0x36, 183 ChipCmd = 0x37, 184 TxPoll = 0x38, 185 IntrMask = 0x3c, 186 IntrStatus = 0x3e, 187 188 TxConfig = 0x40, 189 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 190 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 191 192 RxConfig = 0x44, 193 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 194 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 195 #define RXCFG_FIFO_SHIFT 13 196 /* No threshold before first PCI xfer */ 197 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 198 #define RX_EARLY_OFF (1 << 11) 199 #define RXCFG_DMA_SHIFT 8 200 /* Unlimited maximum PCI burst. */ 201 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 202 203 Cfg9346 = 0x50, 204 Config0 = 0x51, 205 Config1 = 0x52, 206 Config2 = 0x53, 207 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 208 209 Config3 = 0x54, 210 Config4 = 0x55, 211 Config5 = 0x56, 212 PHYAR = 0x60, 213 PHYstatus = 0x6c, 214 RxMaxSize = 0xda, 215 CPlusCmd = 0xe0, 216 IntrMitigate = 0xe2, 217 218 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 219 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 220 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 221 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 222 223 #define RTL_COALESCE_T_MAX 0x0fU 224 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 225 226 RxDescAddrLow = 0xe4, 227 RxDescAddrHigh = 0xe8, 228 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 229 230 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 231 232 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 233 234 #define TxPacketMax (8064 >> 7) 235 #define EarlySize 0x27 236 237 FuncEvent = 0xf0, 238 FuncEventMask = 0xf4, 239 FuncPresetState = 0xf8, 240 IBCR0 = 0xf8, 241 IBCR2 = 0xf9, 242 IBIMR0 = 0xfa, 243 IBISR0 = 0xfb, 244 FuncForceEvent = 0xfc, 245 }; 246 247 enum rtl8168_8101_registers { 248 CSIDR = 0x64, 249 CSIAR = 0x68, 250 #define CSIAR_FLAG 0x80000000 251 #define CSIAR_WRITE_CMD 0x80000000 252 #define CSIAR_BYTE_ENABLE 0x0000f000 253 #define CSIAR_ADDR_MASK 0x00000fff 254 PMCH = 0x6f, 255 #define D3COLD_NO_PLL_DOWN BIT(7) 256 #define D3HOT_NO_PLL_DOWN BIT(6) 257 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 258 EPHYAR = 0x80, 259 #define EPHYAR_FLAG 0x80000000 260 #define EPHYAR_WRITE_CMD 0x80000000 261 #define EPHYAR_REG_MASK 0x1f 262 #define EPHYAR_REG_SHIFT 16 263 #define EPHYAR_DATA_MASK 0xffff 264 DLLPR = 0xd0, 265 #define PFM_EN (1 << 6) 266 #define TX_10M_PS_EN (1 << 7) 267 DBG_REG = 0xd1, 268 #define FIX_NAK_1 (1 << 4) 269 #define FIX_NAK_2 (1 << 3) 270 TWSI = 0xd2, 271 MCU = 0xd3, 272 #define NOW_IS_OOB (1 << 7) 273 #define TX_EMPTY (1 << 5) 274 #define RX_EMPTY (1 << 4) 275 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 276 #define EN_NDP (1 << 3) 277 #define EN_OOB_RESET (1 << 2) 278 #define LINK_LIST_RDY (1 << 1) 279 EFUSEAR = 0xdc, 280 #define EFUSEAR_FLAG 0x80000000 281 #define EFUSEAR_WRITE_CMD 0x80000000 282 #define EFUSEAR_READ_CMD 0x00000000 283 #define EFUSEAR_REG_MASK 0x03ff 284 #define EFUSEAR_REG_SHIFT 8 285 #define EFUSEAR_DATA_MASK 0xff 286 MISC_1 = 0xf2, 287 #define PFM_D3COLD_EN (1 << 6) 288 }; 289 290 enum rtl8168_registers { 291 LED_FREQ = 0x1a, 292 EEE_LED = 0x1b, 293 ERIDR = 0x70, 294 ERIAR = 0x74, 295 #define ERIAR_FLAG 0x80000000 296 #define ERIAR_WRITE_CMD 0x80000000 297 #define ERIAR_READ_CMD 0x00000000 298 #define ERIAR_ADDR_BYTE_ALIGN 4 299 #define ERIAR_TYPE_SHIFT 16 300 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 301 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_MASK_SHIFT 12 305 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 306 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 310 EPHY_RXER_NUM = 0x7c, 311 OCPDR = 0xb0, /* OCP GPHY access */ 312 #define OCPDR_WRITE_CMD 0x80000000 313 #define OCPDR_READ_CMD 0x00000000 314 #define OCPDR_REG_MASK 0x7f 315 #define OCPDR_GPHY_REG_SHIFT 16 316 #define OCPDR_DATA_MASK 0xffff 317 OCPAR = 0xb4, 318 #define OCPAR_FLAG 0x80000000 319 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 320 #define OCPAR_GPHY_READ_CMD 0x0000f060 321 GPHY_OCP = 0xb8, 322 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 323 MISC = 0xf0, /* 8168e only. */ 324 #define TXPLA_RST (1 << 29) 325 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 326 #define PWM_EN (1 << 22) 327 #define RXDV_GATED_EN (1 << 19) 328 #define EARLY_TALLY_EN (1 << 16) 329 }; 330 331 enum rtl8125_registers { 332 IntrMask_8125 = 0x38, 333 IntrStatus_8125 = 0x3c, 334 TxPoll_8125 = 0x90, 335 MAC0_BKP = 0x19e0, 336 EEE_TXIDLE_TIMER_8125 = 0x6048, 337 }; 338 339 #define RX_VLAN_INNER_8125 BIT(22) 340 #define RX_VLAN_OUTER_8125 BIT(23) 341 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 342 343 #define RX_FETCH_DFLT_8125 (8 << 27) 344 345 enum rtl_register_content { 346 /* InterruptStatusBits */ 347 SYSErr = 0x8000, 348 PCSTimeout = 0x4000, 349 SWInt = 0x0100, 350 TxDescUnavail = 0x0080, 351 RxFIFOOver = 0x0040, 352 LinkChg = 0x0020, 353 RxOverflow = 0x0010, 354 TxErr = 0x0008, 355 TxOK = 0x0004, 356 RxErr = 0x0002, 357 RxOK = 0x0001, 358 359 /* RxStatusDesc */ 360 RxRWT = (1 << 22), 361 RxRES = (1 << 21), 362 RxRUNT = (1 << 20), 363 RxCRC = (1 << 19), 364 365 /* ChipCmdBits */ 366 StopReq = 0x80, 367 CmdReset = 0x10, 368 CmdRxEnb = 0x08, 369 CmdTxEnb = 0x04, 370 RxBufEmpty = 0x01, 371 372 /* TXPoll register p.5 */ 373 HPQ = 0x80, /* Poll cmd on the high prio queue */ 374 NPQ = 0x40, /* Poll cmd on the low prio queue */ 375 FSWInt = 0x01, /* Forced software interrupt */ 376 377 /* Cfg9346Bits */ 378 Cfg9346_Lock = 0x00, 379 Cfg9346_Unlock = 0xc0, 380 381 /* rx_mode_bits */ 382 AcceptErr = 0x20, 383 AcceptRunt = 0x10, 384 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 385 AcceptBroadcast = 0x08, 386 AcceptMulticast = 0x04, 387 AcceptMyPhys = 0x02, 388 AcceptAllPhys = 0x01, 389 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 390 #define RX_CONFIG_ACCEPT_MASK 0x3f 391 392 /* TxConfigBits */ 393 TxInterFrameGapShift = 24, 394 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 395 396 /* Config1 register p.24 */ 397 LEDS1 = (1 << 7), 398 LEDS0 = (1 << 6), 399 Speed_down = (1 << 4), 400 MEMMAP = (1 << 3), 401 IOMAP = (1 << 2), 402 VPD = (1 << 1), 403 PMEnable = (1 << 0), /* Power Management Enable */ 404 405 /* Config2 register p. 25 */ 406 ClkReqEn = (1 << 7), /* Clock Request Enable */ 407 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 408 PCI_Clock_66MHz = 0x01, 409 PCI_Clock_33MHz = 0x00, 410 411 /* Config3 register p.25 */ 412 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 413 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 414 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 415 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 416 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 417 418 /* Config4 register */ 419 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 420 421 /* Config5 register p.27 */ 422 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 423 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 424 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 425 Spi_en = (1 << 3), 426 LanWake = (1 << 1), /* LanWake enable/disable */ 427 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 428 ASPM_en = (1 << 0), /* ASPM enable */ 429 430 /* CPlusCmd p.31 */ 431 EnableBist = (1 << 15), // 8168 8101 432 Mac_dbgo_oe = (1 << 14), // 8168 8101 433 EnAnaPLL = (1 << 14), // 8169 434 Normal_mode = (1 << 13), // unused 435 Force_half_dup = (1 << 12), // 8168 8101 436 Force_rxflow_en = (1 << 11), // 8168 8101 437 Force_txflow_en = (1 << 10), // 8168 8101 438 Cxpl_dbg_sel = (1 << 9), // 8168 8101 439 ASF = (1 << 8), // 8168 8101 440 PktCntrDisable = (1 << 7), // 8168 8101 441 Mac_dbgo_sel = 0x001c, // 8168 442 RxVlan = (1 << 6), 443 RxChkSum = (1 << 5), 444 PCIDAC = (1 << 4), 445 PCIMulRW = (1 << 3), 446 #define INTT_MASK GENMASK(1, 0) 447 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 448 449 /* rtl8169_PHYstatus */ 450 TBI_Enable = 0x80, 451 TxFlowCtrl = 0x40, 452 RxFlowCtrl = 0x20, 453 _1000bpsF = 0x10, 454 _100bps = 0x08, 455 _10bps = 0x04, 456 LinkStatus = 0x02, 457 FullDup = 0x01, 458 459 /* ResetCounterCommand */ 460 CounterReset = 0x1, 461 462 /* DumpCounterCommand */ 463 CounterDump = 0x8, 464 465 /* magic enable v2 */ 466 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 467 }; 468 469 enum rtl_desc_bit { 470 /* First doubleword. */ 471 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 472 RingEnd = (1 << 30), /* End of descriptor ring */ 473 FirstFrag = (1 << 29), /* First segment of a packet */ 474 LastFrag = (1 << 28), /* Final segment of a packet */ 475 }; 476 477 /* Generic case. */ 478 enum rtl_tx_desc_bit { 479 /* First doubleword. */ 480 TD_LSO = (1 << 27), /* Large Send Offload */ 481 #define TD_MSS_MAX 0x07ffu /* MSS value */ 482 483 /* Second doubleword. */ 484 TxVlanTag = (1 << 17), /* Add VLAN tag */ 485 }; 486 487 /* 8169, 8168b and 810x except 8102e. */ 488 enum rtl_tx_desc_bit_0 { 489 /* First doubleword. */ 490 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 491 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 492 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 493 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 494 }; 495 496 /* 8102e, 8168c and beyond. */ 497 enum rtl_tx_desc_bit_1 { 498 /* First doubleword. */ 499 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 500 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 501 #define GTTCPHO_SHIFT 18 502 #define GTTCPHO_MAX 0x7f 503 504 /* Second doubleword. */ 505 #define TCPHO_SHIFT 18 506 #define TCPHO_MAX 0x3ff 507 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 508 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 509 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 510 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 511 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 512 }; 513 514 enum rtl_rx_desc_bit { 515 /* Rx private */ 516 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 517 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 518 519 #define RxProtoUDP (PID1) 520 #define RxProtoTCP (PID0) 521 #define RxProtoIP (PID1 | PID0) 522 #define RxProtoMask RxProtoIP 523 524 IPFail = (1 << 16), /* IP checksum failed */ 525 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 526 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 527 528 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 529 530 RxVlanTag = (1 << 16), /* VLAN tag available */ 531 }; 532 533 #define RTL_GSO_MAX_SIZE_V1 32000 534 #define RTL_GSO_MAX_SEGS_V1 24 535 #define RTL_GSO_MAX_SIZE_V2 64000 536 #define RTL_GSO_MAX_SEGS_V2 64 537 538 struct TxDesc { 539 __le32 opts1; 540 __le32 opts2; 541 __le64 addr; 542 }; 543 544 struct RxDesc { 545 __le32 opts1; 546 __le32 opts2; 547 __le64 addr; 548 }; 549 550 struct ring_info { 551 struct sk_buff *skb; 552 u32 len; 553 }; 554 555 struct rtl8169_counters { 556 __le64 tx_packets; 557 __le64 rx_packets; 558 __le64 tx_errors; 559 __le32 rx_errors; 560 __le16 rx_missed; 561 __le16 align_errors; 562 __le32 tx_one_collision; 563 __le32 tx_multi_collision; 564 __le64 rx_unicast; 565 __le64 rx_broadcast; 566 __le32 rx_multicast; 567 __le16 tx_aborted; 568 __le16 tx_underun; 569 }; 570 571 struct rtl8169_tc_offsets { 572 bool inited; 573 __le64 tx_errors; 574 __le32 tx_multi_collision; 575 __le16 tx_aborted; 576 __le16 rx_missed; 577 }; 578 579 enum rtl_flag { 580 RTL_FLAG_TASK_ENABLED = 0, 581 RTL_FLAG_TASK_RESET_PENDING, 582 RTL_FLAG_MAX 583 }; 584 585 enum rtl_dash_type { 586 RTL_DASH_NONE, 587 RTL_DASH_DP, 588 RTL_DASH_EP, 589 }; 590 591 struct rtl8169_private { 592 void __iomem *mmio_addr; /* memory map physical address */ 593 struct pci_dev *pci_dev; 594 struct net_device *dev; 595 struct phy_device *phydev; 596 struct napi_struct napi; 597 enum mac_version mac_version; 598 enum rtl_dash_type dash_type; 599 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 600 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 601 u32 dirty_tx; 602 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 603 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 604 dma_addr_t TxPhyAddr; 605 dma_addr_t RxPhyAddr; 606 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 607 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 608 u16 cp_cmd; 609 u32 irq_mask; 610 int irq; 611 struct clk *clk; 612 613 struct { 614 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 615 struct work_struct work; 616 } wk; 617 618 unsigned supports_gmii:1; 619 unsigned aspm_manageable:1; 620 dma_addr_t counters_phys_addr; 621 struct rtl8169_counters *counters; 622 struct rtl8169_tc_offsets tc_offset; 623 u32 saved_wolopts; 624 int eee_adv; 625 626 const char *fw_name; 627 struct rtl_fw *rtl_fw; 628 629 u32 ocp_base; 630 }; 631 632 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 633 634 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 635 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 636 MODULE_SOFTDEP("pre: realtek"); 637 MODULE_LICENSE("GPL"); 638 MODULE_FIRMWARE(FIRMWARE_8168D_1); 639 MODULE_FIRMWARE(FIRMWARE_8168D_2); 640 MODULE_FIRMWARE(FIRMWARE_8168E_1); 641 MODULE_FIRMWARE(FIRMWARE_8168E_2); 642 MODULE_FIRMWARE(FIRMWARE_8168E_3); 643 MODULE_FIRMWARE(FIRMWARE_8105E_1); 644 MODULE_FIRMWARE(FIRMWARE_8168F_1); 645 MODULE_FIRMWARE(FIRMWARE_8168F_2); 646 MODULE_FIRMWARE(FIRMWARE_8402_1); 647 MODULE_FIRMWARE(FIRMWARE_8411_1); 648 MODULE_FIRMWARE(FIRMWARE_8411_2); 649 MODULE_FIRMWARE(FIRMWARE_8106E_1); 650 MODULE_FIRMWARE(FIRMWARE_8106E_2); 651 MODULE_FIRMWARE(FIRMWARE_8168G_2); 652 MODULE_FIRMWARE(FIRMWARE_8168G_3); 653 MODULE_FIRMWARE(FIRMWARE_8168H_2); 654 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 655 MODULE_FIRMWARE(FIRMWARE_8107E_2); 656 MODULE_FIRMWARE(FIRMWARE_8125A_3); 657 MODULE_FIRMWARE(FIRMWARE_8125B_2); 658 659 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 660 { 661 return &tp->pci_dev->dev; 662 } 663 664 static void rtl_lock_config_regs(struct rtl8169_private *tp) 665 { 666 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 667 } 668 669 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 670 { 671 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 672 } 673 674 static void rtl_pci_commit(struct rtl8169_private *tp) 675 { 676 /* Read an arbitrary register to commit a preceding PCI write */ 677 RTL_R8(tp, ChipCmd); 678 } 679 680 static bool rtl_is_8125(struct rtl8169_private *tp) 681 { 682 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 683 } 684 685 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 686 { 687 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 688 tp->mac_version != RTL_GIGA_MAC_VER_39 && 689 tp->mac_version <= RTL_GIGA_MAC_VER_53; 690 } 691 692 static bool rtl_supports_eee(struct rtl8169_private *tp) 693 { 694 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 695 tp->mac_version != RTL_GIGA_MAC_VER_37 && 696 tp->mac_version != RTL_GIGA_MAC_VER_39; 697 } 698 699 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 700 { 701 int i; 702 703 for (i = 0; i < ETH_ALEN; i++) 704 mac[i] = RTL_R8(tp, reg + i); 705 } 706 707 struct rtl_cond { 708 bool (*check)(struct rtl8169_private *); 709 const char *msg; 710 }; 711 712 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 713 unsigned long usecs, int n, bool high) 714 { 715 int i; 716 717 for (i = 0; i < n; i++) { 718 if (c->check(tp) == high) 719 return true; 720 fsleep(usecs); 721 } 722 723 if (net_ratelimit()) 724 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 725 c->msg, !high, n, usecs); 726 return false; 727 } 728 729 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 730 const struct rtl_cond *c, 731 unsigned long d, int n) 732 { 733 return rtl_loop_wait(tp, c, d, n, true); 734 } 735 736 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 737 const struct rtl_cond *c, 738 unsigned long d, int n) 739 { 740 return rtl_loop_wait(tp, c, d, n, false); 741 } 742 743 #define DECLARE_RTL_COND(name) \ 744 static bool name ## _check(struct rtl8169_private *); \ 745 \ 746 static const struct rtl_cond name = { \ 747 .check = name ## _check, \ 748 .msg = #name \ 749 }; \ 750 \ 751 static bool name ## _check(struct rtl8169_private *tp) 752 753 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 754 { 755 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 756 if (type == ERIAR_OOB && 757 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 758 tp->mac_version == RTL_GIGA_MAC_VER_53)) 759 *cmd |= 0xf70 << 18; 760 } 761 762 DECLARE_RTL_COND(rtl_eriar_cond) 763 { 764 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 765 } 766 767 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 768 u32 val, int type) 769 { 770 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 771 772 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 773 return; 774 775 RTL_W32(tp, ERIDR, val); 776 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 777 RTL_W32(tp, ERIAR, cmd); 778 779 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 780 } 781 782 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 783 u32 val) 784 { 785 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 786 } 787 788 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 789 { 790 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 791 792 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 793 RTL_W32(tp, ERIAR, cmd); 794 795 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 796 RTL_R32(tp, ERIDR) : ~0; 797 } 798 799 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 800 { 801 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 802 } 803 804 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 805 { 806 u32 val = rtl_eri_read(tp, addr); 807 808 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 809 } 810 811 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 812 { 813 rtl_w0w1_eri(tp, addr, p, 0); 814 } 815 816 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 817 { 818 rtl_w0w1_eri(tp, addr, 0, m); 819 } 820 821 static bool rtl_ocp_reg_failure(u32 reg) 822 { 823 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 824 } 825 826 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 827 { 828 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 829 } 830 831 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 832 { 833 if (rtl_ocp_reg_failure(reg)) 834 return; 835 836 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 837 838 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 839 } 840 841 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 842 { 843 if (rtl_ocp_reg_failure(reg)) 844 return 0; 845 846 RTL_W32(tp, GPHY_OCP, reg << 15); 847 848 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 849 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 850 } 851 852 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 853 { 854 if (rtl_ocp_reg_failure(reg)) 855 return; 856 857 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 858 } 859 860 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 861 { 862 if (rtl_ocp_reg_failure(reg)) 863 return 0; 864 865 RTL_W32(tp, OCPDR, reg << 15); 866 867 return RTL_R32(tp, OCPDR); 868 } 869 870 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 871 u16 set) 872 { 873 u16 data = r8168_mac_ocp_read(tp, reg); 874 875 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 876 } 877 878 /* Work around a hw issue with RTL8168g PHY, the quirk disables 879 * PHY MCU interrupts before PHY power-down. 880 */ 881 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 882 { 883 switch (tp->mac_version) { 884 case RTL_GIGA_MAC_VER_40: 885 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 886 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 887 else 888 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 889 break; 890 default: 891 break; 892 } 893 }; 894 895 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 896 { 897 if (reg == 0x1f) { 898 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 899 return; 900 } 901 902 if (tp->ocp_base != OCP_STD_PHY_BASE) 903 reg -= 0x10; 904 905 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 906 rtl8168g_phy_suspend_quirk(tp, value); 907 908 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 909 } 910 911 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 912 { 913 if (reg == 0x1f) 914 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 915 916 if (tp->ocp_base != OCP_STD_PHY_BASE) 917 reg -= 0x10; 918 919 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 920 } 921 922 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 923 { 924 if (reg == 0x1f) { 925 tp->ocp_base = value << 4; 926 return; 927 } 928 929 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 930 } 931 932 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 933 { 934 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 935 } 936 937 DECLARE_RTL_COND(rtl_phyar_cond) 938 { 939 return RTL_R32(tp, PHYAR) & 0x80000000; 940 } 941 942 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 943 { 944 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 945 946 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 947 /* 948 * According to hardware specs a 20us delay is required after write 949 * complete indication, but before sending next command. 950 */ 951 udelay(20); 952 } 953 954 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 955 { 956 int value; 957 958 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 959 960 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 961 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 962 963 /* 964 * According to hardware specs a 20us delay is required after read 965 * complete indication, but before sending next command. 966 */ 967 udelay(20); 968 969 return value; 970 } 971 972 DECLARE_RTL_COND(rtl_ocpar_cond) 973 { 974 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 975 } 976 977 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 978 979 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 980 { 981 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 982 } 983 984 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 985 { 986 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 987 } 988 989 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 990 { 991 r8168dp_2_mdio_start(tp); 992 993 r8169_mdio_write(tp, reg, value); 994 995 r8168dp_2_mdio_stop(tp); 996 } 997 998 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 999 { 1000 int value; 1001 1002 /* Work around issue with chip reporting wrong PHY ID */ 1003 if (reg == MII_PHYSID2) 1004 return 0xc912; 1005 1006 r8168dp_2_mdio_start(tp); 1007 1008 value = r8169_mdio_read(tp, reg); 1009 1010 r8168dp_2_mdio_stop(tp); 1011 1012 return value; 1013 } 1014 1015 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1016 { 1017 switch (tp->mac_version) { 1018 case RTL_GIGA_MAC_VER_28: 1019 case RTL_GIGA_MAC_VER_31: 1020 r8168dp_2_mdio_write(tp, location, val); 1021 break; 1022 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1023 r8168g_mdio_write(tp, location, val); 1024 break; 1025 default: 1026 r8169_mdio_write(tp, location, val); 1027 break; 1028 } 1029 } 1030 1031 static int rtl_readphy(struct rtl8169_private *tp, int location) 1032 { 1033 switch (tp->mac_version) { 1034 case RTL_GIGA_MAC_VER_28: 1035 case RTL_GIGA_MAC_VER_31: 1036 return r8168dp_2_mdio_read(tp, location); 1037 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1038 return r8168g_mdio_read(tp, location); 1039 default: 1040 return r8169_mdio_read(tp, location); 1041 } 1042 } 1043 1044 DECLARE_RTL_COND(rtl_ephyar_cond) 1045 { 1046 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1047 } 1048 1049 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1050 { 1051 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1052 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1053 1054 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1055 1056 udelay(10); 1057 } 1058 1059 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1060 { 1061 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1062 1063 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1064 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1065 } 1066 1067 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1068 { 1069 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1070 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1071 RTL_R32(tp, OCPDR) : ~0; 1072 } 1073 1074 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1075 { 1076 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1077 } 1078 1079 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1080 u32 data) 1081 { 1082 RTL_W32(tp, OCPDR, data); 1083 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1084 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1085 } 1086 1087 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1088 u32 data) 1089 { 1090 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1091 data, ERIAR_OOB); 1092 } 1093 1094 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1095 { 1096 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1097 1098 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1099 } 1100 1101 #define OOB_CMD_RESET 0x00 1102 #define OOB_CMD_DRIVER_START 0x05 1103 #define OOB_CMD_DRIVER_STOP 0x06 1104 1105 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1106 { 1107 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1108 } 1109 1110 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1111 { 1112 u16 reg; 1113 1114 reg = rtl8168_get_ocp_reg(tp); 1115 1116 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1117 } 1118 1119 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1120 { 1121 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1122 } 1123 1124 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1125 { 1126 return RTL_R8(tp, IBISR0) & 0x20; 1127 } 1128 1129 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1130 { 1131 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1132 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1133 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1134 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1135 } 1136 1137 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1138 { 1139 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1140 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1141 } 1142 1143 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1144 { 1145 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1146 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1147 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1148 } 1149 1150 static void rtl8168_driver_start(struct rtl8169_private *tp) 1151 { 1152 if (tp->dash_type == RTL_DASH_DP) 1153 rtl8168dp_driver_start(tp); 1154 else 1155 rtl8168ep_driver_start(tp); 1156 } 1157 1158 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1159 { 1160 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1161 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1162 } 1163 1164 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1165 { 1166 rtl8168ep_stop_cmac(tp); 1167 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1168 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1169 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1170 } 1171 1172 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1173 { 1174 if (tp->dash_type == RTL_DASH_DP) 1175 rtl8168dp_driver_stop(tp); 1176 else 1177 rtl8168ep_driver_stop(tp); 1178 } 1179 1180 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1181 { 1182 u16 reg = rtl8168_get_ocp_reg(tp); 1183 1184 return r8168dp_ocp_read(tp, reg) & BIT(15); 1185 } 1186 1187 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1188 { 1189 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1190 } 1191 1192 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1193 { 1194 switch (tp->mac_version) { 1195 case RTL_GIGA_MAC_VER_28: 1196 case RTL_GIGA_MAC_VER_31: 1197 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1198 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1199 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1200 default: 1201 return RTL_DASH_NONE; 1202 } 1203 } 1204 1205 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1206 { 1207 switch (tp->mac_version) { 1208 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1209 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1210 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1211 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1212 if (enable) 1213 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1214 else 1215 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1216 break; 1217 default: 1218 break; 1219 } 1220 } 1221 1222 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1223 { 1224 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1225 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1226 } 1227 1228 DECLARE_RTL_COND(rtl_efusear_cond) 1229 { 1230 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1231 } 1232 1233 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1234 { 1235 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1236 1237 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1238 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1239 } 1240 1241 static u32 rtl_get_events(struct rtl8169_private *tp) 1242 { 1243 if (rtl_is_8125(tp)) 1244 return RTL_R32(tp, IntrStatus_8125); 1245 else 1246 return RTL_R16(tp, IntrStatus); 1247 } 1248 1249 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1250 { 1251 if (rtl_is_8125(tp)) 1252 RTL_W32(tp, IntrStatus_8125, bits); 1253 else 1254 RTL_W16(tp, IntrStatus, bits); 1255 } 1256 1257 static void rtl_irq_disable(struct rtl8169_private *tp) 1258 { 1259 if (rtl_is_8125(tp)) 1260 RTL_W32(tp, IntrMask_8125, 0); 1261 else 1262 RTL_W16(tp, IntrMask, 0); 1263 } 1264 1265 static void rtl_irq_enable(struct rtl8169_private *tp) 1266 { 1267 if (rtl_is_8125(tp)) 1268 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1269 else 1270 RTL_W16(tp, IntrMask, tp->irq_mask); 1271 } 1272 1273 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1274 { 1275 rtl_irq_disable(tp); 1276 rtl_ack_events(tp, 0xffffffff); 1277 rtl_pci_commit(tp); 1278 } 1279 1280 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1281 { 1282 struct phy_device *phydev = tp->phydev; 1283 1284 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1285 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1286 if (phydev->speed == SPEED_1000) { 1287 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1288 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1289 } else if (phydev->speed == SPEED_100) { 1290 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1291 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1292 } else { 1293 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1294 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1295 } 1296 rtl_reset_packet_filter(tp); 1297 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1298 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1299 if (phydev->speed == SPEED_1000) { 1300 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1301 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1302 } else { 1303 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1304 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1305 } 1306 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1307 if (phydev->speed == SPEED_10) { 1308 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1309 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1310 } else { 1311 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1312 } 1313 } 1314 } 1315 1316 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1317 1318 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1319 { 1320 struct rtl8169_private *tp = netdev_priv(dev); 1321 1322 wol->supported = WAKE_ANY; 1323 wol->wolopts = tp->saved_wolopts; 1324 } 1325 1326 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1327 { 1328 static const struct { 1329 u32 opt; 1330 u16 reg; 1331 u8 mask; 1332 } cfg[] = { 1333 { WAKE_PHY, Config3, LinkUp }, 1334 { WAKE_UCAST, Config5, UWF }, 1335 { WAKE_BCAST, Config5, BWF }, 1336 { WAKE_MCAST, Config5, MWF }, 1337 { WAKE_ANY, Config5, LanWake }, 1338 { WAKE_MAGIC, Config3, MagicPacket } 1339 }; 1340 unsigned int i, tmp = ARRAY_SIZE(cfg); 1341 u8 options; 1342 1343 rtl_unlock_config_regs(tp); 1344 1345 if (rtl_is_8168evl_up(tp)) { 1346 tmp--; 1347 if (wolopts & WAKE_MAGIC) 1348 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1349 else 1350 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1351 } else if (rtl_is_8125(tp)) { 1352 tmp--; 1353 if (wolopts & WAKE_MAGIC) 1354 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1355 else 1356 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1357 } 1358 1359 for (i = 0; i < tmp; i++) { 1360 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1361 if (wolopts & cfg[i].opt) 1362 options |= cfg[i].mask; 1363 RTL_W8(tp, cfg[i].reg, options); 1364 } 1365 1366 switch (tp->mac_version) { 1367 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1368 options = RTL_R8(tp, Config1) & ~PMEnable; 1369 if (wolopts) 1370 options |= PMEnable; 1371 RTL_W8(tp, Config1, options); 1372 break; 1373 case RTL_GIGA_MAC_VER_34: 1374 case RTL_GIGA_MAC_VER_37: 1375 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1376 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1377 if (wolopts) 1378 options |= PME_SIGNAL; 1379 RTL_W8(tp, Config2, options); 1380 break; 1381 default: 1382 break; 1383 } 1384 1385 rtl_lock_config_regs(tp); 1386 1387 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1388 1389 if (tp->dash_type == RTL_DASH_NONE) { 1390 rtl_set_d3_pll_down(tp, !wolopts); 1391 tp->dev->wol_enabled = wolopts ? 1 : 0; 1392 } 1393 } 1394 1395 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1396 { 1397 struct rtl8169_private *tp = netdev_priv(dev); 1398 1399 if (wol->wolopts & ~WAKE_ANY) 1400 return -EINVAL; 1401 1402 tp->saved_wolopts = wol->wolopts; 1403 __rtl8169_set_wol(tp, tp->saved_wolopts); 1404 1405 return 0; 1406 } 1407 1408 static void rtl8169_get_drvinfo(struct net_device *dev, 1409 struct ethtool_drvinfo *info) 1410 { 1411 struct rtl8169_private *tp = netdev_priv(dev); 1412 struct rtl_fw *rtl_fw = tp->rtl_fw; 1413 1414 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1415 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1416 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1417 if (rtl_fw) 1418 strscpy(info->fw_version, rtl_fw->version, 1419 sizeof(info->fw_version)); 1420 } 1421 1422 static int rtl8169_get_regs_len(struct net_device *dev) 1423 { 1424 return R8169_REGS_SIZE; 1425 } 1426 1427 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1428 netdev_features_t features) 1429 { 1430 struct rtl8169_private *tp = netdev_priv(dev); 1431 1432 if (dev->mtu > TD_MSS_MAX) 1433 features &= ~NETIF_F_ALL_TSO; 1434 1435 if (dev->mtu > ETH_DATA_LEN && 1436 tp->mac_version > RTL_GIGA_MAC_VER_06) 1437 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1438 1439 return features; 1440 } 1441 1442 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1443 netdev_features_t features) 1444 { 1445 u32 rx_config = RTL_R32(tp, RxConfig); 1446 1447 if (features & NETIF_F_RXALL) 1448 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1449 else 1450 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1451 1452 if (rtl_is_8125(tp)) { 1453 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1454 rx_config |= RX_VLAN_8125; 1455 else 1456 rx_config &= ~RX_VLAN_8125; 1457 } 1458 1459 RTL_W32(tp, RxConfig, rx_config); 1460 } 1461 1462 static int rtl8169_set_features(struct net_device *dev, 1463 netdev_features_t features) 1464 { 1465 struct rtl8169_private *tp = netdev_priv(dev); 1466 1467 rtl_set_rx_config_features(tp, features); 1468 1469 if (features & NETIF_F_RXCSUM) 1470 tp->cp_cmd |= RxChkSum; 1471 else 1472 tp->cp_cmd &= ~RxChkSum; 1473 1474 if (!rtl_is_8125(tp)) { 1475 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1476 tp->cp_cmd |= RxVlan; 1477 else 1478 tp->cp_cmd &= ~RxVlan; 1479 } 1480 1481 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1482 rtl_pci_commit(tp); 1483 1484 return 0; 1485 } 1486 1487 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1488 { 1489 return (skb_vlan_tag_present(skb)) ? 1490 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1491 } 1492 1493 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1494 { 1495 u32 opts2 = le32_to_cpu(desc->opts2); 1496 1497 if (opts2 & RxVlanTag) 1498 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1499 } 1500 1501 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1502 void *p) 1503 { 1504 struct rtl8169_private *tp = netdev_priv(dev); 1505 u32 __iomem *data = tp->mmio_addr; 1506 u32 *dw = p; 1507 int i; 1508 1509 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1510 memcpy_fromio(dw++, data++, 4); 1511 } 1512 1513 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1514 "tx_packets", 1515 "rx_packets", 1516 "tx_errors", 1517 "rx_errors", 1518 "rx_missed", 1519 "align_errors", 1520 "tx_single_collisions", 1521 "tx_multi_collisions", 1522 "unicast", 1523 "broadcast", 1524 "multicast", 1525 "tx_aborted", 1526 "tx_underrun", 1527 }; 1528 1529 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1530 { 1531 switch (sset) { 1532 case ETH_SS_STATS: 1533 return ARRAY_SIZE(rtl8169_gstrings); 1534 default: 1535 return -EOPNOTSUPP; 1536 } 1537 } 1538 1539 DECLARE_RTL_COND(rtl_counters_cond) 1540 { 1541 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1542 } 1543 1544 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1545 { 1546 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1547 1548 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1549 rtl_pci_commit(tp); 1550 RTL_W32(tp, CounterAddrLow, cmd); 1551 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1552 1553 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1554 } 1555 1556 static void rtl8169_update_counters(struct rtl8169_private *tp) 1557 { 1558 u8 val = RTL_R8(tp, ChipCmd); 1559 1560 /* 1561 * Some chips are unable to dump tally counters when the receiver 1562 * is disabled. If 0xff chip may be in a PCI power-save state. 1563 */ 1564 if (val & CmdRxEnb && val != 0xff) 1565 rtl8169_do_counters(tp, CounterDump); 1566 } 1567 1568 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1569 { 1570 struct rtl8169_counters *counters = tp->counters; 1571 1572 /* 1573 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1574 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1575 * reset by a power cycle, while the counter values collected by the 1576 * driver are reset at every driver unload/load cycle. 1577 * 1578 * To make sure the HW values returned by @get_stats64 match the SW 1579 * values, we collect the initial values at first open(*) and use them 1580 * as offsets to normalize the values returned by @get_stats64. 1581 * 1582 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1583 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1584 * set at open time by rtl_hw_start. 1585 */ 1586 1587 if (tp->tc_offset.inited) 1588 return; 1589 1590 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1591 rtl8169_do_counters(tp, CounterReset); 1592 } else { 1593 rtl8169_update_counters(tp); 1594 tp->tc_offset.tx_errors = counters->tx_errors; 1595 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1596 tp->tc_offset.tx_aborted = counters->tx_aborted; 1597 tp->tc_offset.rx_missed = counters->rx_missed; 1598 } 1599 1600 tp->tc_offset.inited = true; 1601 } 1602 1603 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1604 struct ethtool_stats *stats, u64 *data) 1605 { 1606 struct rtl8169_private *tp = netdev_priv(dev); 1607 struct rtl8169_counters *counters; 1608 1609 counters = tp->counters; 1610 rtl8169_update_counters(tp); 1611 1612 data[0] = le64_to_cpu(counters->tx_packets); 1613 data[1] = le64_to_cpu(counters->rx_packets); 1614 data[2] = le64_to_cpu(counters->tx_errors); 1615 data[3] = le32_to_cpu(counters->rx_errors); 1616 data[4] = le16_to_cpu(counters->rx_missed); 1617 data[5] = le16_to_cpu(counters->align_errors); 1618 data[6] = le32_to_cpu(counters->tx_one_collision); 1619 data[7] = le32_to_cpu(counters->tx_multi_collision); 1620 data[8] = le64_to_cpu(counters->rx_unicast); 1621 data[9] = le64_to_cpu(counters->rx_broadcast); 1622 data[10] = le32_to_cpu(counters->rx_multicast); 1623 data[11] = le16_to_cpu(counters->tx_aborted); 1624 data[12] = le16_to_cpu(counters->tx_underun); 1625 } 1626 1627 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1628 { 1629 switch(stringset) { 1630 case ETH_SS_STATS: 1631 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1632 break; 1633 } 1634 } 1635 1636 /* 1637 * Interrupt coalescing 1638 * 1639 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1640 * > 8169, 8168 and 810x line of chipsets 1641 * 1642 * 8169, 8168, and 8136(810x) serial chipsets support it. 1643 * 1644 * > 2 - the Tx timer unit at gigabit speed 1645 * 1646 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1647 * (0xe0) bit 1 and bit 0. 1648 * 1649 * For 8169 1650 * bit[1:0] \ speed 1000M 100M 10M 1651 * 0 0 320ns 2.56us 40.96us 1652 * 0 1 2.56us 20.48us 327.7us 1653 * 1 0 5.12us 40.96us 655.4us 1654 * 1 1 10.24us 81.92us 1.31ms 1655 * 1656 * For the other 1657 * bit[1:0] \ speed 1000M 100M 10M 1658 * 0 0 5us 2.56us 40.96us 1659 * 0 1 40us 20.48us 327.7us 1660 * 1 0 80us 40.96us 655.4us 1661 * 1 1 160us 81.92us 1.31ms 1662 */ 1663 1664 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1665 struct rtl_coalesce_info { 1666 u32 speed; 1667 u32 scale_nsecs[4]; 1668 }; 1669 1670 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1671 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1672 1673 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1674 { SPEED_1000, COALESCE_DELAY(320) }, 1675 { SPEED_100, COALESCE_DELAY(2560) }, 1676 { SPEED_10, COALESCE_DELAY(40960) }, 1677 { 0 }, 1678 }; 1679 1680 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1681 { SPEED_1000, COALESCE_DELAY(5000) }, 1682 { SPEED_100, COALESCE_DELAY(2560) }, 1683 { SPEED_10, COALESCE_DELAY(40960) }, 1684 { 0 }, 1685 }; 1686 #undef COALESCE_DELAY 1687 1688 /* get rx/tx scale vector corresponding to current speed */ 1689 static const struct rtl_coalesce_info * 1690 rtl_coalesce_info(struct rtl8169_private *tp) 1691 { 1692 const struct rtl_coalesce_info *ci; 1693 1694 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1695 ci = rtl_coalesce_info_8169; 1696 else 1697 ci = rtl_coalesce_info_8168_8136; 1698 1699 /* if speed is unknown assume highest one */ 1700 if (tp->phydev->speed == SPEED_UNKNOWN) 1701 return ci; 1702 1703 for (; ci->speed; ci++) { 1704 if (tp->phydev->speed == ci->speed) 1705 return ci; 1706 } 1707 1708 return ERR_PTR(-ELNRNG); 1709 } 1710 1711 static int rtl_get_coalesce(struct net_device *dev, 1712 struct ethtool_coalesce *ec, 1713 struct kernel_ethtool_coalesce *kernel_coal, 1714 struct netlink_ext_ack *extack) 1715 { 1716 struct rtl8169_private *tp = netdev_priv(dev); 1717 const struct rtl_coalesce_info *ci; 1718 u32 scale, c_us, c_fr; 1719 u16 intrmit; 1720 1721 if (rtl_is_8125(tp)) 1722 return -EOPNOTSUPP; 1723 1724 memset(ec, 0, sizeof(*ec)); 1725 1726 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1727 ci = rtl_coalesce_info(tp); 1728 if (IS_ERR(ci)) 1729 return PTR_ERR(ci); 1730 1731 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1732 1733 intrmit = RTL_R16(tp, IntrMitigate); 1734 1735 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1736 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1737 1738 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1739 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1740 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1741 1742 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1743 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1744 1745 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1746 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1747 1748 return 0; 1749 } 1750 1751 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1752 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1753 u16 *cp01) 1754 { 1755 const struct rtl_coalesce_info *ci; 1756 u16 i; 1757 1758 ci = rtl_coalesce_info(tp); 1759 if (IS_ERR(ci)) 1760 return PTR_ERR(ci); 1761 1762 for (i = 0; i < 4; i++) { 1763 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1764 *cp01 = i; 1765 return ci->scale_nsecs[i]; 1766 } 1767 } 1768 1769 return -ERANGE; 1770 } 1771 1772 static int rtl_set_coalesce(struct net_device *dev, 1773 struct ethtool_coalesce *ec, 1774 struct kernel_ethtool_coalesce *kernel_coal, 1775 struct netlink_ext_ack *extack) 1776 { 1777 struct rtl8169_private *tp = netdev_priv(dev); 1778 u32 tx_fr = ec->tx_max_coalesced_frames; 1779 u32 rx_fr = ec->rx_max_coalesced_frames; 1780 u32 coal_usec_max, units; 1781 u16 w = 0, cp01 = 0; 1782 int scale; 1783 1784 if (rtl_is_8125(tp)) 1785 return -EOPNOTSUPP; 1786 1787 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1788 return -ERANGE; 1789 1790 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1791 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1792 if (scale < 0) 1793 return scale; 1794 1795 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1796 * not only when usecs=0 because of e.g. the following scenario: 1797 * 1798 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1799 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1800 * - then user does `ethtool -C eth0 rx-usecs 100` 1801 * 1802 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1803 * if we want to ignore rx_frames then it has to be set to 0. 1804 */ 1805 if (rx_fr == 1) 1806 rx_fr = 0; 1807 if (tx_fr == 1) 1808 tx_fr = 0; 1809 1810 /* HW requires time limit to be set if frame limit is set */ 1811 if ((tx_fr && !ec->tx_coalesce_usecs) || 1812 (rx_fr && !ec->rx_coalesce_usecs)) 1813 return -EINVAL; 1814 1815 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1816 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1817 1818 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1819 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1820 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1821 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1822 1823 RTL_W16(tp, IntrMitigate, w); 1824 1825 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1826 if (rtl_is_8168evl_up(tp)) { 1827 if (!rx_fr && !tx_fr) 1828 /* disable packet counter */ 1829 tp->cp_cmd |= PktCntrDisable; 1830 else 1831 tp->cp_cmd &= ~PktCntrDisable; 1832 } 1833 1834 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1835 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1836 rtl_pci_commit(tp); 1837 1838 return 0; 1839 } 1840 1841 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1842 { 1843 struct rtl8169_private *tp = netdev_priv(dev); 1844 1845 if (!rtl_supports_eee(tp)) 1846 return -EOPNOTSUPP; 1847 1848 return phy_ethtool_get_eee(tp->phydev, data); 1849 } 1850 1851 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1852 { 1853 struct rtl8169_private *tp = netdev_priv(dev); 1854 int ret; 1855 1856 if (!rtl_supports_eee(tp)) 1857 return -EOPNOTSUPP; 1858 1859 ret = phy_ethtool_set_eee(tp->phydev, data); 1860 1861 if (!ret) 1862 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1863 MDIO_AN_EEE_ADV); 1864 return ret; 1865 } 1866 1867 static void rtl8169_get_ringparam(struct net_device *dev, 1868 struct ethtool_ringparam *data, 1869 struct kernel_ethtool_ringparam *kernel_data, 1870 struct netlink_ext_ack *extack) 1871 { 1872 data->rx_max_pending = NUM_RX_DESC; 1873 data->rx_pending = NUM_RX_DESC; 1874 data->tx_max_pending = NUM_TX_DESC; 1875 data->tx_pending = NUM_TX_DESC; 1876 } 1877 1878 static void rtl8169_get_pauseparam(struct net_device *dev, 1879 struct ethtool_pauseparam *data) 1880 { 1881 struct rtl8169_private *tp = netdev_priv(dev); 1882 bool tx_pause, rx_pause; 1883 1884 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1885 1886 data->autoneg = tp->phydev->autoneg; 1887 data->tx_pause = tx_pause ? 1 : 0; 1888 data->rx_pause = rx_pause ? 1 : 0; 1889 } 1890 1891 static int rtl8169_set_pauseparam(struct net_device *dev, 1892 struct ethtool_pauseparam *data) 1893 { 1894 struct rtl8169_private *tp = netdev_priv(dev); 1895 1896 if (dev->mtu > ETH_DATA_LEN) 1897 return -EOPNOTSUPP; 1898 1899 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1900 1901 return 0; 1902 } 1903 1904 static const struct ethtool_ops rtl8169_ethtool_ops = { 1905 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1906 ETHTOOL_COALESCE_MAX_FRAMES, 1907 .get_drvinfo = rtl8169_get_drvinfo, 1908 .get_regs_len = rtl8169_get_regs_len, 1909 .get_link = ethtool_op_get_link, 1910 .get_coalesce = rtl_get_coalesce, 1911 .set_coalesce = rtl_set_coalesce, 1912 .get_regs = rtl8169_get_regs, 1913 .get_wol = rtl8169_get_wol, 1914 .set_wol = rtl8169_set_wol, 1915 .get_strings = rtl8169_get_strings, 1916 .get_sset_count = rtl8169_get_sset_count, 1917 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1918 .get_ts_info = ethtool_op_get_ts_info, 1919 .nway_reset = phy_ethtool_nway_reset, 1920 .get_eee = rtl8169_get_eee, 1921 .set_eee = rtl8169_set_eee, 1922 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1923 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1924 .get_ringparam = rtl8169_get_ringparam, 1925 .get_pauseparam = rtl8169_get_pauseparam, 1926 .set_pauseparam = rtl8169_set_pauseparam, 1927 }; 1928 1929 static void rtl_enable_eee(struct rtl8169_private *tp) 1930 { 1931 struct phy_device *phydev = tp->phydev; 1932 int adv; 1933 1934 /* respect EEE advertisement the user may have set */ 1935 if (tp->eee_adv >= 0) 1936 adv = tp->eee_adv; 1937 else 1938 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1939 1940 if (adv >= 0) 1941 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1942 } 1943 1944 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1945 { 1946 /* 1947 * The driver currently handles the 8168Bf and the 8168Be identically 1948 * but they can be identified more specifically through the test below 1949 * if needed: 1950 * 1951 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1952 * 1953 * Same thing for the 8101Eb and the 8101Ec: 1954 * 1955 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1956 */ 1957 static const struct rtl_mac_info { 1958 u16 mask; 1959 u16 val; 1960 enum mac_version ver; 1961 } mac_info[] = { 1962 /* 8125B family. */ 1963 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1964 1965 /* 8125A family. */ 1966 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 1967 /* It seems only XID 609 made it to the mass market. 1968 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1969 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1970 */ 1971 1972 /* RTL8117 */ 1973 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 1974 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1975 1976 /* 8168EP family. */ 1977 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1978 /* It seems this chip version never made it to 1979 * the wild. Let's disable detection. 1980 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1981 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1982 */ 1983 1984 /* 8168H family. */ 1985 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1986 /* It seems this chip version never made it to 1987 * the wild. Let's disable detection. 1988 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1989 */ 1990 1991 /* 8168G family. */ 1992 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1993 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1994 /* It seems this chip version never made it to 1995 * the wild. Let's disable detection. 1996 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1997 */ 1998 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1999 2000 /* 8168F family. */ 2001 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2002 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2003 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2004 2005 /* 8168E family. */ 2006 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2007 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2008 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2009 2010 /* 8168D family. */ 2011 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2012 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2013 2014 /* 8168DP family. */ 2015 /* It seems this early RTL8168dp version never made it to 2016 * the wild. Support has been removed. 2017 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2018 */ 2019 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2020 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2021 2022 /* 8168C family. */ 2023 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2024 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2025 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2026 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2027 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2028 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2029 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2030 2031 /* 8168B family. */ 2032 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2033 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2034 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2035 2036 /* 8101 family. */ 2037 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2038 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2039 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2040 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2041 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2042 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2043 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2044 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2045 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2046 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2047 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2048 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2049 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2050 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2051 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2052 /* FIXME: where did these entries come from ? -- FR 2053 * Not even r8101 vendor driver knows these id's, 2054 * so let's disable detection for now. -- HK 2055 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2056 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2057 */ 2058 2059 /* 8110 family. */ 2060 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2061 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2062 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2063 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2064 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2065 2066 /* Catch-all */ 2067 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2068 }; 2069 const struct rtl_mac_info *p = mac_info; 2070 enum mac_version ver; 2071 2072 while ((xid & p->mask) != p->val) 2073 p++; 2074 ver = p->ver; 2075 2076 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2077 if (ver == RTL_GIGA_MAC_VER_42) 2078 ver = RTL_GIGA_MAC_VER_43; 2079 else if (ver == RTL_GIGA_MAC_VER_46) 2080 ver = RTL_GIGA_MAC_VER_48; 2081 } 2082 2083 return ver; 2084 } 2085 2086 static void rtl_release_firmware(struct rtl8169_private *tp) 2087 { 2088 if (tp->rtl_fw) { 2089 rtl_fw_release_firmware(tp->rtl_fw); 2090 kfree(tp->rtl_fw); 2091 tp->rtl_fw = NULL; 2092 } 2093 } 2094 2095 void r8169_apply_firmware(struct rtl8169_private *tp) 2096 { 2097 int val; 2098 2099 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2100 if (tp->rtl_fw) { 2101 rtl_fw_write_firmware(tp, tp->rtl_fw); 2102 /* At least one firmware doesn't reset tp->ocp_base. */ 2103 tp->ocp_base = OCP_STD_PHY_BASE; 2104 2105 /* PHY soft reset may still be in progress */ 2106 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2107 !(val & BMCR_RESET), 2108 50000, 600000, true); 2109 } 2110 } 2111 2112 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2113 { 2114 /* Adjust EEE LED frequency */ 2115 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2116 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2117 2118 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2119 } 2120 2121 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2122 { 2123 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2124 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2125 } 2126 2127 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2128 { 2129 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2130 } 2131 2132 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2133 { 2134 rtl8125_set_eee_txidle_timer(tp); 2135 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2136 } 2137 2138 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2139 { 2140 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2141 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2142 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2143 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2144 } 2145 2146 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2147 { 2148 u16 data1, data2, ioffset; 2149 2150 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2151 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2152 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2153 2154 ioffset = (data2 >> 1) & 0x7ff8; 2155 ioffset |= data2 & 0x0007; 2156 if (data1 & BIT(7)) 2157 ioffset |= BIT(15); 2158 2159 return ioffset; 2160 } 2161 2162 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2163 { 2164 set_bit(flag, tp->wk.flags); 2165 schedule_work(&tp->wk.work); 2166 } 2167 2168 static void rtl8169_init_phy(struct rtl8169_private *tp) 2169 { 2170 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2171 2172 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2173 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2174 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2175 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2176 RTL_W8(tp, 0x82, 0x01); 2177 } 2178 2179 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2180 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2181 tp->pci_dev->subsystem_device == 0xe000) 2182 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2183 2184 /* We may have called phy_speed_down before */ 2185 phy_speed_up(tp->phydev); 2186 2187 if (rtl_supports_eee(tp)) 2188 rtl_enable_eee(tp); 2189 2190 genphy_soft_reset(tp->phydev); 2191 } 2192 2193 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2194 { 2195 rtl_unlock_config_regs(tp); 2196 2197 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2198 rtl_pci_commit(tp); 2199 2200 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2201 rtl_pci_commit(tp); 2202 2203 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2204 rtl_rar_exgmac_set(tp, addr); 2205 2206 rtl_lock_config_regs(tp); 2207 } 2208 2209 static int rtl_set_mac_address(struct net_device *dev, void *p) 2210 { 2211 struct rtl8169_private *tp = netdev_priv(dev); 2212 int ret; 2213 2214 ret = eth_mac_addr(dev, p); 2215 if (ret) 2216 return ret; 2217 2218 rtl_rar_set(tp, dev->dev_addr); 2219 2220 return 0; 2221 } 2222 2223 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2224 { 2225 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2226 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2227 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2228 } 2229 2230 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2231 { 2232 if (tp->dash_type != RTL_DASH_NONE) 2233 return; 2234 2235 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2236 tp->mac_version == RTL_GIGA_MAC_VER_33) 2237 rtl_ephy_write(tp, 0x19, 0xff64); 2238 2239 if (device_may_wakeup(tp_to_dev(tp))) { 2240 phy_speed_down(tp->phydev, false); 2241 rtl_wol_enable_rx(tp); 2242 } 2243 } 2244 2245 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2246 { 2247 switch (tp->mac_version) { 2248 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2249 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2250 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2251 break; 2252 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2253 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2254 case RTL_GIGA_MAC_VER_38: 2255 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2256 break; 2257 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2258 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2259 break; 2260 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2261 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2262 break; 2263 default: 2264 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2265 break; 2266 } 2267 } 2268 2269 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2270 { 2271 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2272 } 2273 2274 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2275 { 2276 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2277 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2278 } 2279 2280 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2281 { 2282 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2283 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2284 } 2285 2286 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2287 { 2288 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2289 } 2290 2291 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2292 { 2293 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2294 } 2295 2296 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2297 { 2298 RTL_W8(tp, MaxTxPacketSize, 0x24); 2299 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2300 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2301 } 2302 2303 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2304 { 2305 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2306 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2307 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2308 } 2309 2310 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2311 { 2312 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2313 } 2314 2315 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2316 { 2317 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2318 } 2319 2320 static void rtl_jumbo_config(struct rtl8169_private *tp) 2321 { 2322 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2323 int readrq = 4096; 2324 2325 rtl_unlock_config_regs(tp); 2326 switch (tp->mac_version) { 2327 case RTL_GIGA_MAC_VER_12: 2328 case RTL_GIGA_MAC_VER_17: 2329 if (jumbo) { 2330 readrq = 512; 2331 r8168b_1_hw_jumbo_enable(tp); 2332 } else { 2333 r8168b_1_hw_jumbo_disable(tp); 2334 } 2335 break; 2336 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2337 if (jumbo) { 2338 readrq = 512; 2339 r8168c_hw_jumbo_enable(tp); 2340 } else { 2341 r8168c_hw_jumbo_disable(tp); 2342 } 2343 break; 2344 case RTL_GIGA_MAC_VER_28: 2345 if (jumbo) 2346 r8168dp_hw_jumbo_enable(tp); 2347 else 2348 r8168dp_hw_jumbo_disable(tp); 2349 break; 2350 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2351 if (jumbo) 2352 r8168e_hw_jumbo_enable(tp); 2353 else 2354 r8168e_hw_jumbo_disable(tp); 2355 break; 2356 default: 2357 break; 2358 } 2359 rtl_lock_config_regs(tp); 2360 2361 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2362 pcie_set_readrq(tp->pci_dev, readrq); 2363 2364 /* Chip doesn't support pause in jumbo mode */ 2365 if (jumbo) { 2366 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2367 tp->phydev->advertising); 2368 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2369 tp->phydev->advertising); 2370 phy_start_aneg(tp->phydev); 2371 } 2372 } 2373 2374 DECLARE_RTL_COND(rtl_chipcmd_cond) 2375 { 2376 return RTL_R8(tp, ChipCmd) & CmdReset; 2377 } 2378 2379 static void rtl_hw_reset(struct rtl8169_private *tp) 2380 { 2381 RTL_W8(tp, ChipCmd, CmdReset); 2382 2383 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2384 } 2385 2386 static void rtl_request_firmware(struct rtl8169_private *tp) 2387 { 2388 struct rtl_fw *rtl_fw; 2389 2390 /* firmware loaded already or no firmware available */ 2391 if (tp->rtl_fw || !tp->fw_name) 2392 return; 2393 2394 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2395 if (!rtl_fw) 2396 return; 2397 2398 rtl_fw->phy_write = rtl_writephy; 2399 rtl_fw->phy_read = rtl_readphy; 2400 rtl_fw->mac_mcu_write = mac_mcu_write; 2401 rtl_fw->mac_mcu_read = mac_mcu_read; 2402 rtl_fw->fw_name = tp->fw_name; 2403 rtl_fw->dev = tp_to_dev(tp); 2404 2405 if (rtl_fw_request_firmware(rtl_fw)) 2406 kfree(rtl_fw); 2407 else 2408 tp->rtl_fw = rtl_fw; 2409 } 2410 2411 static void rtl_rx_close(struct rtl8169_private *tp) 2412 { 2413 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2414 } 2415 2416 DECLARE_RTL_COND(rtl_npq_cond) 2417 { 2418 return RTL_R8(tp, TxPoll) & NPQ; 2419 } 2420 2421 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2422 { 2423 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2424 } 2425 2426 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2427 { 2428 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2429 } 2430 2431 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2432 { 2433 /* IntrMitigate has new functionality on RTL8125 */ 2434 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2435 } 2436 2437 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2438 { 2439 switch (tp->mac_version) { 2440 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2441 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2442 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2443 break; 2444 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2445 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2446 break; 2447 case RTL_GIGA_MAC_VER_63: 2448 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2449 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2450 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2451 break; 2452 default: 2453 break; 2454 } 2455 } 2456 2457 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2458 { 2459 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2460 fsleep(2000); 2461 rtl_wait_txrx_fifo_empty(tp); 2462 } 2463 2464 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2465 { 2466 u32 val = TX_DMA_BURST << TxDMAShift | 2467 InterFrameGap << TxInterFrameGapShift; 2468 2469 if (rtl_is_8168evl_up(tp)) 2470 val |= TXCFG_AUTO_FIFO; 2471 2472 RTL_W32(tp, TxConfig, val); 2473 } 2474 2475 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2476 { 2477 /* Low hurts. Let's disable the filtering. */ 2478 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2479 } 2480 2481 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2482 { 2483 /* 2484 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2485 * register to be written before TxDescAddrLow to work. 2486 * Switching from MMIO to I/O access fixes the issue as well. 2487 */ 2488 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2489 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2490 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2491 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2492 } 2493 2494 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2495 { 2496 u32 val; 2497 2498 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2499 val = 0x000fff00; 2500 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2501 val = 0x00ffff00; 2502 else 2503 return; 2504 2505 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2506 val |= 0xff; 2507 2508 RTL_W32(tp, 0x7c, val); 2509 } 2510 2511 static void rtl_set_rx_mode(struct net_device *dev) 2512 { 2513 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2514 /* Multicast hash filter */ 2515 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2516 struct rtl8169_private *tp = netdev_priv(dev); 2517 u32 tmp; 2518 2519 if (dev->flags & IFF_PROMISC) { 2520 rx_mode |= AcceptAllPhys; 2521 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2522 dev->flags & IFF_ALLMULTI || 2523 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2524 /* accept all multicasts */ 2525 } else if (netdev_mc_empty(dev)) { 2526 rx_mode &= ~AcceptMulticast; 2527 } else { 2528 struct netdev_hw_addr *ha; 2529 2530 mc_filter[1] = mc_filter[0] = 0; 2531 netdev_for_each_mc_addr(ha, dev) { 2532 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2533 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2534 } 2535 2536 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2537 tmp = mc_filter[0]; 2538 mc_filter[0] = swab32(mc_filter[1]); 2539 mc_filter[1] = swab32(tmp); 2540 } 2541 } 2542 2543 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2544 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2545 2546 tmp = RTL_R32(tp, RxConfig); 2547 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2548 } 2549 2550 DECLARE_RTL_COND(rtl_csiar_cond) 2551 { 2552 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2553 } 2554 2555 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2556 { 2557 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2558 2559 RTL_W32(tp, CSIDR, value); 2560 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2561 CSIAR_BYTE_ENABLE | func << 16); 2562 2563 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2564 } 2565 2566 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2567 { 2568 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2569 2570 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2571 CSIAR_BYTE_ENABLE); 2572 2573 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2574 RTL_R32(tp, CSIDR) : ~0; 2575 } 2576 2577 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2578 { 2579 struct pci_dev *pdev = tp->pci_dev; 2580 u32 csi; 2581 2582 /* According to Realtek the value at config space address 0x070f 2583 * controls the L0s/L1 entrance latency. We try standard ECAM access 2584 * first and if it fails fall back to CSI. 2585 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2586 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2587 */ 2588 if (pdev->cfg_size > 0x070f && 2589 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2590 return; 2591 2592 netdev_notice_once(tp->dev, 2593 "No native access to PCI extended config space, falling back to CSI\n"); 2594 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2595 rtl_csi_write(tp, 0x070c, csi | val << 24); 2596 } 2597 2598 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2599 { 2600 /* L0 7us, L1 16us */ 2601 rtl_set_aspm_entry_latency(tp, 0x27); 2602 } 2603 2604 struct ephy_info { 2605 unsigned int offset; 2606 u16 mask; 2607 u16 bits; 2608 }; 2609 2610 static void __rtl_ephy_init(struct rtl8169_private *tp, 2611 const struct ephy_info *e, int len) 2612 { 2613 u16 w; 2614 2615 while (len-- > 0) { 2616 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2617 rtl_ephy_write(tp, e->offset, w); 2618 e++; 2619 } 2620 } 2621 2622 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2623 2624 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2625 { 2626 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2627 PCI_EXP_LNKCTL_CLKREQ_EN); 2628 } 2629 2630 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2631 { 2632 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2633 PCI_EXP_LNKCTL_CLKREQ_EN); 2634 } 2635 2636 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2637 { 2638 /* work around an issue when PCI reset occurs during L2/L3 state */ 2639 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2640 } 2641 2642 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2643 { 2644 /* Bits control which events trigger ASPM L1 exit: 2645 * Bit 12: rxdv 2646 * Bit 11: ltr_msg 2647 * Bit 10: txdma_poll 2648 * Bit 9: xadm 2649 * Bit 8: pktavi 2650 * Bit 7: txpla 2651 */ 2652 switch (tp->mac_version) { 2653 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2654 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2655 break; 2656 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2657 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2658 break; 2659 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2660 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2661 break; 2662 default: 2663 break; 2664 } 2665 } 2666 2667 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2668 { 2669 switch (tp->mac_version) { 2670 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2671 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2672 break; 2673 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2674 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2675 break; 2676 default: 2677 break; 2678 } 2679 } 2680 2681 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2682 { 2683 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2684 if (enable && tp->aspm_manageable) { 2685 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2686 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2687 2688 switch (tp->mac_version) { 2689 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2690 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2691 /* reset ephy tx/rx disable timer */ 2692 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2693 /* chip can trigger L1.2 */ 2694 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2695 break; 2696 default: 2697 break; 2698 } 2699 } else { 2700 switch (tp->mac_version) { 2701 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2702 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2703 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2704 break; 2705 default: 2706 break; 2707 } 2708 2709 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2710 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2711 } 2712 2713 udelay(10); 2714 } 2715 2716 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2717 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2718 { 2719 /* Usage of dynamic vs. static FIFO is controlled by bit 2720 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2721 */ 2722 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2723 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2724 } 2725 2726 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2727 u8 low, u8 high) 2728 { 2729 /* FIFO thresholds for pause flow control */ 2730 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2731 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2732 } 2733 2734 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2735 { 2736 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2737 } 2738 2739 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2740 { 2741 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2742 2743 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2744 2745 rtl_disable_clock_request(tp); 2746 } 2747 2748 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2749 { 2750 static const struct ephy_info e_info_8168cp[] = { 2751 { 0x01, 0, 0x0001 }, 2752 { 0x02, 0x0800, 0x1000 }, 2753 { 0x03, 0, 0x0042 }, 2754 { 0x06, 0x0080, 0x0000 }, 2755 { 0x07, 0, 0x2000 } 2756 }; 2757 2758 rtl_set_def_aspm_entry_latency(tp); 2759 2760 rtl_ephy_init(tp, e_info_8168cp); 2761 2762 __rtl_hw_start_8168cp(tp); 2763 } 2764 2765 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2766 { 2767 rtl_set_def_aspm_entry_latency(tp); 2768 2769 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2770 } 2771 2772 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2773 { 2774 rtl_set_def_aspm_entry_latency(tp); 2775 2776 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2777 2778 /* Magic. */ 2779 RTL_W8(tp, DBG_REG, 0x20); 2780 } 2781 2782 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2783 { 2784 static const struct ephy_info e_info_8168c_1[] = { 2785 { 0x02, 0x0800, 0x1000 }, 2786 { 0x03, 0, 0x0002 }, 2787 { 0x06, 0x0080, 0x0000 } 2788 }; 2789 2790 rtl_set_def_aspm_entry_latency(tp); 2791 2792 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2793 2794 rtl_ephy_init(tp, e_info_8168c_1); 2795 2796 __rtl_hw_start_8168cp(tp); 2797 } 2798 2799 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2800 { 2801 static const struct ephy_info e_info_8168c_2[] = { 2802 { 0x01, 0, 0x0001 }, 2803 { 0x03, 0x0400, 0x0020 } 2804 }; 2805 2806 rtl_set_def_aspm_entry_latency(tp); 2807 2808 rtl_ephy_init(tp, e_info_8168c_2); 2809 2810 __rtl_hw_start_8168cp(tp); 2811 } 2812 2813 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2814 { 2815 rtl_set_def_aspm_entry_latency(tp); 2816 2817 __rtl_hw_start_8168cp(tp); 2818 } 2819 2820 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2821 { 2822 rtl_set_def_aspm_entry_latency(tp); 2823 2824 rtl_disable_clock_request(tp); 2825 } 2826 2827 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2828 { 2829 static const struct ephy_info e_info_8168d_4[] = { 2830 { 0x0b, 0x0000, 0x0048 }, 2831 { 0x19, 0x0020, 0x0050 }, 2832 { 0x0c, 0x0100, 0x0020 }, 2833 { 0x10, 0x0004, 0x0000 }, 2834 }; 2835 2836 rtl_set_def_aspm_entry_latency(tp); 2837 2838 rtl_ephy_init(tp, e_info_8168d_4); 2839 2840 rtl_enable_clock_request(tp); 2841 } 2842 2843 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2844 { 2845 static const struct ephy_info e_info_8168e_1[] = { 2846 { 0x00, 0x0200, 0x0100 }, 2847 { 0x00, 0x0000, 0x0004 }, 2848 { 0x06, 0x0002, 0x0001 }, 2849 { 0x06, 0x0000, 0x0030 }, 2850 { 0x07, 0x0000, 0x2000 }, 2851 { 0x00, 0x0000, 0x0020 }, 2852 { 0x03, 0x5800, 0x2000 }, 2853 { 0x03, 0x0000, 0x0001 }, 2854 { 0x01, 0x0800, 0x1000 }, 2855 { 0x07, 0x0000, 0x4000 }, 2856 { 0x1e, 0x0000, 0x2000 }, 2857 { 0x19, 0xffff, 0xfe6c }, 2858 { 0x0a, 0x0000, 0x0040 } 2859 }; 2860 2861 rtl_set_def_aspm_entry_latency(tp); 2862 2863 rtl_ephy_init(tp, e_info_8168e_1); 2864 2865 rtl_disable_clock_request(tp); 2866 2867 /* Reset tx FIFO pointer */ 2868 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2869 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2870 2871 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2872 } 2873 2874 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2875 { 2876 static const struct ephy_info e_info_8168e_2[] = { 2877 { 0x09, 0x0000, 0x0080 }, 2878 { 0x19, 0x0000, 0x0224 }, 2879 { 0x00, 0x0000, 0x0004 }, 2880 { 0x0c, 0x3df0, 0x0200 }, 2881 }; 2882 2883 rtl_set_def_aspm_entry_latency(tp); 2884 2885 rtl_ephy_init(tp, e_info_8168e_2); 2886 2887 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2888 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2889 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2890 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2891 rtl_reset_packet_filter(tp); 2892 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2893 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2894 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2895 2896 rtl_disable_clock_request(tp); 2897 2898 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2899 2900 rtl8168_config_eee_mac(tp); 2901 2902 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2903 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2904 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2905 2906 rtl_hw_aspm_clkreq_enable(tp, true); 2907 } 2908 2909 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2910 { 2911 rtl_set_def_aspm_entry_latency(tp); 2912 2913 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2914 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2915 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2916 rtl_reset_packet_filter(tp); 2917 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2918 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2919 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2920 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2921 2922 rtl_disable_clock_request(tp); 2923 2924 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2925 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2926 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2927 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2928 2929 rtl8168_config_eee_mac(tp); 2930 } 2931 2932 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2933 { 2934 static const struct ephy_info e_info_8168f_1[] = { 2935 { 0x06, 0x00c0, 0x0020 }, 2936 { 0x08, 0x0001, 0x0002 }, 2937 { 0x09, 0x0000, 0x0080 }, 2938 { 0x19, 0x0000, 0x0224 }, 2939 { 0x00, 0x0000, 0x0008 }, 2940 { 0x0c, 0x3df0, 0x0200 }, 2941 }; 2942 2943 rtl_hw_start_8168f(tp); 2944 2945 rtl_ephy_init(tp, e_info_8168f_1); 2946 } 2947 2948 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2949 { 2950 static const struct ephy_info e_info_8168f_1[] = { 2951 { 0x06, 0x00c0, 0x0020 }, 2952 { 0x0f, 0xffff, 0x5200 }, 2953 { 0x19, 0x0000, 0x0224 }, 2954 { 0x00, 0x0000, 0x0008 }, 2955 { 0x0c, 0x3df0, 0x0200 }, 2956 }; 2957 2958 rtl_hw_start_8168f(tp); 2959 rtl_pcie_state_l2l3_disable(tp); 2960 2961 rtl_ephy_init(tp, e_info_8168f_1); 2962 } 2963 2964 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2965 { 2966 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2967 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2968 2969 rtl_set_def_aspm_entry_latency(tp); 2970 2971 rtl_reset_packet_filter(tp); 2972 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2973 2974 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2975 2976 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2977 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2978 2979 rtl8168_config_eee_mac(tp); 2980 2981 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2982 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2983 2984 rtl_pcie_state_l2l3_disable(tp); 2985 } 2986 2987 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2988 { 2989 static const struct ephy_info e_info_8168g_1[] = { 2990 { 0x00, 0x0008, 0x0000 }, 2991 { 0x0c, 0x3ff0, 0x0820 }, 2992 { 0x1e, 0x0000, 0x0001 }, 2993 { 0x19, 0x8000, 0x0000 } 2994 }; 2995 2996 rtl_hw_start_8168g(tp); 2997 2998 /* disable aspm and clock request before access ephy */ 2999 rtl_hw_aspm_clkreq_enable(tp, false); 3000 rtl_ephy_init(tp, e_info_8168g_1); 3001 rtl_hw_aspm_clkreq_enable(tp, true); 3002 } 3003 3004 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3005 { 3006 static const struct ephy_info e_info_8168g_2[] = { 3007 { 0x00, 0x0008, 0x0000 }, 3008 { 0x0c, 0x3ff0, 0x0820 }, 3009 { 0x19, 0xffff, 0x7c00 }, 3010 { 0x1e, 0xffff, 0x20eb }, 3011 { 0x0d, 0xffff, 0x1666 }, 3012 { 0x00, 0xffff, 0x10a3 }, 3013 { 0x06, 0xffff, 0xf050 }, 3014 { 0x04, 0x0000, 0x0010 }, 3015 { 0x1d, 0x4000, 0x0000 }, 3016 }; 3017 3018 rtl_hw_start_8168g(tp); 3019 3020 /* disable aspm and clock request before access ephy */ 3021 rtl_hw_aspm_clkreq_enable(tp, false); 3022 rtl_ephy_init(tp, e_info_8168g_2); 3023 } 3024 3025 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3026 { 3027 static const struct ephy_info e_info_8411_2[] = { 3028 { 0x00, 0x0008, 0x0000 }, 3029 { 0x0c, 0x37d0, 0x0820 }, 3030 { 0x1e, 0x0000, 0x0001 }, 3031 { 0x19, 0x8021, 0x0000 }, 3032 { 0x1e, 0x0000, 0x2000 }, 3033 { 0x0d, 0x0100, 0x0200 }, 3034 { 0x00, 0x0000, 0x0080 }, 3035 { 0x06, 0x0000, 0x0010 }, 3036 { 0x04, 0x0000, 0x0010 }, 3037 { 0x1d, 0x0000, 0x4000 }, 3038 }; 3039 3040 rtl_hw_start_8168g(tp); 3041 3042 /* disable aspm and clock request before access ephy */ 3043 rtl_hw_aspm_clkreq_enable(tp, false); 3044 rtl_ephy_init(tp, e_info_8411_2); 3045 3046 /* The following Realtek-provided magic fixes an issue with the RX unit 3047 * getting confused after the PHY having been powered-down. 3048 */ 3049 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3050 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3051 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3052 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3053 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3054 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3055 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3056 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3057 mdelay(3); 3058 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3059 3060 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3061 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3062 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3063 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3064 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3065 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3066 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3067 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3068 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3069 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3070 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3071 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3072 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3073 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3074 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3075 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3076 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3077 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3078 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3079 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3080 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3081 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3082 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3083 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3084 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3085 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3086 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3087 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3088 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3089 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3090 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3091 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3092 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3093 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3094 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3095 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3096 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3097 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3098 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3099 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3100 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3101 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3102 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3103 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3104 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3105 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3106 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3107 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3108 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3109 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3110 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3111 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3112 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3113 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3114 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3115 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3116 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3117 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3118 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3119 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3120 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3121 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3122 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3123 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3124 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3125 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3126 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3127 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3128 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3129 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3130 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3131 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3132 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3133 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3134 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3135 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3136 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3137 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3138 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3139 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3140 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3141 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3142 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3143 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3144 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3145 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3146 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3147 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3148 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3149 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3150 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3151 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3152 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3153 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3154 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3155 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3156 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3157 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3158 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3159 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3160 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3161 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3162 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3163 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3164 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3165 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3166 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3167 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3168 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3169 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3170 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3171 3172 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3173 3174 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3175 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3176 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3177 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3178 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3179 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3180 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3181 3182 rtl_hw_aspm_clkreq_enable(tp, true); 3183 } 3184 3185 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3186 { 3187 static const struct ephy_info e_info_8168h_1[] = { 3188 { 0x1e, 0x0800, 0x0001 }, 3189 { 0x1d, 0x0000, 0x0800 }, 3190 { 0x05, 0xffff, 0x2089 }, 3191 { 0x06, 0xffff, 0x5881 }, 3192 { 0x04, 0xffff, 0x854a }, 3193 { 0x01, 0xffff, 0x068b } 3194 }; 3195 int rg_saw_cnt; 3196 3197 /* disable aspm and clock request before access ephy */ 3198 rtl_hw_aspm_clkreq_enable(tp, false); 3199 rtl_ephy_init(tp, e_info_8168h_1); 3200 3201 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3202 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3203 3204 rtl_set_def_aspm_entry_latency(tp); 3205 3206 rtl_reset_packet_filter(tp); 3207 3208 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3209 3210 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3211 3212 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3213 3214 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3215 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3216 3217 rtl8168_config_eee_mac(tp); 3218 3219 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3220 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3221 3222 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3223 3224 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3225 3226 rtl_pcie_state_l2l3_disable(tp); 3227 3228 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3229 if (rg_saw_cnt > 0) { 3230 u16 sw_cnt_1ms_ini; 3231 3232 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3233 sw_cnt_1ms_ini &= 0x0fff; 3234 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3235 } 3236 3237 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3238 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3239 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3240 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3241 3242 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3243 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3244 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3245 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3246 3247 rtl_hw_aspm_clkreq_enable(tp, true); 3248 } 3249 3250 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3251 { 3252 rtl8168ep_stop_cmac(tp); 3253 3254 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3255 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3256 3257 rtl_set_def_aspm_entry_latency(tp); 3258 3259 rtl_reset_packet_filter(tp); 3260 3261 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3262 3263 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3264 3265 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3266 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3267 3268 rtl8168_config_eee_mac(tp); 3269 3270 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3271 3272 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3273 3274 rtl_pcie_state_l2l3_disable(tp); 3275 } 3276 3277 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3278 { 3279 static const struct ephy_info e_info_8168ep_3[] = { 3280 { 0x00, 0x0000, 0x0080 }, 3281 { 0x0d, 0x0100, 0x0200 }, 3282 { 0x19, 0x8021, 0x0000 }, 3283 { 0x1e, 0x0000, 0x2000 }, 3284 }; 3285 3286 /* disable aspm and clock request before access ephy */ 3287 rtl_hw_aspm_clkreq_enable(tp, false); 3288 rtl_ephy_init(tp, e_info_8168ep_3); 3289 3290 rtl_hw_start_8168ep(tp); 3291 3292 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3293 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3294 3295 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3296 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3297 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3298 3299 rtl_hw_aspm_clkreq_enable(tp, true); 3300 } 3301 3302 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3303 { 3304 static const struct ephy_info e_info_8117[] = { 3305 { 0x19, 0x0040, 0x1100 }, 3306 { 0x59, 0x0040, 0x1100 }, 3307 }; 3308 int rg_saw_cnt; 3309 3310 rtl8168ep_stop_cmac(tp); 3311 3312 /* disable aspm and clock request before access ephy */ 3313 rtl_hw_aspm_clkreq_enable(tp, false); 3314 rtl_ephy_init(tp, e_info_8117); 3315 3316 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3317 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3318 3319 rtl_set_def_aspm_entry_latency(tp); 3320 3321 rtl_reset_packet_filter(tp); 3322 3323 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3324 3325 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3326 3327 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3328 3329 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3330 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3331 3332 rtl8168_config_eee_mac(tp); 3333 3334 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3335 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3336 3337 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3338 3339 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3340 3341 rtl_pcie_state_l2l3_disable(tp); 3342 3343 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3344 if (rg_saw_cnt > 0) { 3345 u16 sw_cnt_1ms_ini; 3346 3347 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3348 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3349 } 3350 3351 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3352 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3353 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3354 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3355 3356 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3357 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3358 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3359 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3360 3361 /* firmware is for MAC only */ 3362 r8169_apply_firmware(tp); 3363 3364 rtl_hw_aspm_clkreq_enable(tp, true); 3365 } 3366 3367 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3368 { 3369 static const struct ephy_info e_info_8102e_1[] = { 3370 { 0x01, 0, 0x6e65 }, 3371 { 0x02, 0, 0x091f }, 3372 { 0x03, 0, 0xc2f9 }, 3373 { 0x06, 0, 0xafb5 }, 3374 { 0x07, 0, 0x0e00 }, 3375 { 0x19, 0, 0xec80 }, 3376 { 0x01, 0, 0x2e65 }, 3377 { 0x01, 0, 0x6e65 } 3378 }; 3379 u8 cfg1; 3380 3381 rtl_set_def_aspm_entry_latency(tp); 3382 3383 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3384 3385 RTL_W8(tp, Config1, 3386 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3387 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3388 3389 cfg1 = RTL_R8(tp, Config1); 3390 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3391 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3392 3393 rtl_ephy_init(tp, e_info_8102e_1); 3394 } 3395 3396 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3397 { 3398 rtl_set_def_aspm_entry_latency(tp); 3399 3400 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3401 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3402 } 3403 3404 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3405 { 3406 rtl_hw_start_8102e_2(tp); 3407 3408 rtl_ephy_write(tp, 0x03, 0xc2f9); 3409 } 3410 3411 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3412 { 3413 static const struct ephy_info e_info_8401[] = { 3414 { 0x01, 0xffff, 0x6fe5 }, 3415 { 0x03, 0xffff, 0x0599 }, 3416 { 0x06, 0xffff, 0xaf25 }, 3417 { 0x07, 0xffff, 0x8e68 }, 3418 }; 3419 3420 rtl_ephy_init(tp, e_info_8401); 3421 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3422 } 3423 3424 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3425 { 3426 static const struct ephy_info e_info_8105e_1[] = { 3427 { 0x07, 0, 0x4000 }, 3428 { 0x19, 0, 0x0200 }, 3429 { 0x19, 0, 0x0020 }, 3430 { 0x1e, 0, 0x2000 }, 3431 { 0x03, 0, 0x0001 }, 3432 { 0x19, 0, 0x0100 }, 3433 { 0x19, 0, 0x0004 }, 3434 { 0x0a, 0, 0x0020 } 3435 }; 3436 3437 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3438 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3439 3440 /* Disable Early Tally Counter */ 3441 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3442 3443 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3444 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3445 3446 rtl_ephy_init(tp, e_info_8105e_1); 3447 3448 rtl_pcie_state_l2l3_disable(tp); 3449 } 3450 3451 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3452 { 3453 rtl_hw_start_8105e_1(tp); 3454 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3455 } 3456 3457 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3458 { 3459 static const struct ephy_info e_info_8402[] = { 3460 { 0x19, 0xffff, 0xff64 }, 3461 { 0x1e, 0, 0x4000 } 3462 }; 3463 3464 rtl_set_def_aspm_entry_latency(tp); 3465 3466 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3467 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3468 3469 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3470 3471 rtl_ephy_init(tp, e_info_8402); 3472 3473 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3474 rtl_reset_packet_filter(tp); 3475 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3476 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3477 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3478 3479 /* disable EEE */ 3480 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3481 3482 rtl_pcie_state_l2l3_disable(tp); 3483 } 3484 3485 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3486 { 3487 rtl_hw_aspm_clkreq_enable(tp, false); 3488 3489 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3490 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3491 3492 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3493 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3494 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3495 3496 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3497 rtl_set_aspm_entry_latency(tp, 0x2f); 3498 3499 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3500 3501 /* disable EEE */ 3502 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3503 3504 rtl_pcie_state_l2l3_disable(tp); 3505 rtl_hw_aspm_clkreq_enable(tp, true); 3506 } 3507 3508 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3509 { 3510 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3511 } 3512 3513 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3514 { 3515 rtl_pcie_state_l2l3_disable(tp); 3516 3517 RTL_W16(tp, 0x382, 0x221b); 3518 RTL_W8(tp, 0x4500, 0); 3519 RTL_W16(tp, 0x4800, 0); 3520 3521 /* disable UPS */ 3522 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3523 3524 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3525 3526 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3527 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3528 3529 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3530 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3531 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3532 3533 /* disable new tx descriptor format */ 3534 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3535 3536 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3537 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3538 else 3539 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3540 3541 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3542 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3543 else 3544 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3545 3546 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3547 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3548 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3549 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3550 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3551 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3552 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3553 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3554 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3555 3556 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3557 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3558 udelay(1); 3559 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3560 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3561 3562 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3563 3564 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3565 3566 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3567 rtl8125b_config_eee_mac(tp); 3568 else 3569 rtl8125a_config_eee_mac(tp); 3570 3571 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3572 udelay(10); 3573 } 3574 3575 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3576 { 3577 static const struct ephy_info e_info_8125a_2[] = { 3578 { 0x04, 0xffff, 0xd000 }, 3579 { 0x0a, 0xffff, 0x8653 }, 3580 { 0x23, 0xffff, 0xab66 }, 3581 { 0x20, 0xffff, 0x9455 }, 3582 { 0x21, 0xffff, 0x99ff }, 3583 { 0x29, 0xffff, 0xfe04 }, 3584 3585 { 0x44, 0xffff, 0xd000 }, 3586 { 0x4a, 0xffff, 0x8653 }, 3587 { 0x63, 0xffff, 0xab66 }, 3588 { 0x60, 0xffff, 0x9455 }, 3589 { 0x61, 0xffff, 0x99ff }, 3590 { 0x69, 0xffff, 0xfe04 }, 3591 }; 3592 3593 rtl_set_def_aspm_entry_latency(tp); 3594 3595 /* disable aspm and clock request before access ephy */ 3596 rtl_hw_aspm_clkreq_enable(tp, false); 3597 rtl_ephy_init(tp, e_info_8125a_2); 3598 3599 rtl_hw_start_8125_common(tp); 3600 rtl_hw_aspm_clkreq_enable(tp, true); 3601 } 3602 3603 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3604 { 3605 static const struct ephy_info e_info_8125b[] = { 3606 { 0x0b, 0xffff, 0xa908 }, 3607 { 0x1e, 0xffff, 0x20eb }, 3608 { 0x4b, 0xffff, 0xa908 }, 3609 { 0x5e, 0xffff, 0x20eb }, 3610 { 0x22, 0x0030, 0x0020 }, 3611 { 0x62, 0x0030, 0x0020 }, 3612 }; 3613 3614 rtl_set_def_aspm_entry_latency(tp); 3615 rtl_hw_aspm_clkreq_enable(tp, false); 3616 3617 rtl_ephy_init(tp, e_info_8125b); 3618 rtl_hw_start_8125_common(tp); 3619 3620 rtl_hw_aspm_clkreq_enable(tp, true); 3621 } 3622 3623 static void rtl_hw_config(struct rtl8169_private *tp) 3624 { 3625 static const rtl_generic_fct hw_configs[] = { 3626 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3627 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3628 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3629 [RTL_GIGA_MAC_VER_10] = NULL, 3630 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3631 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3632 [RTL_GIGA_MAC_VER_13] = NULL, 3633 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3634 [RTL_GIGA_MAC_VER_16] = NULL, 3635 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3636 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3637 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3638 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3639 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3640 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3641 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3642 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3643 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3644 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3645 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3646 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3647 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3648 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3649 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3650 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3651 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3652 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3653 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3654 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3655 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3656 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3657 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3658 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3659 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3660 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3661 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3662 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3663 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3664 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3665 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3666 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3667 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3668 }; 3669 3670 if (hw_configs[tp->mac_version]) 3671 hw_configs[tp->mac_version](tp); 3672 } 3673 3674 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3675 { 3676 int i; 3677 3678 /* disable interrupt coalescing */ 3679 for (i = 0xa00; i < 0xb00; i += 4) 3680 RTL_W32(tp, i, 0); 3681 3682 rtl_hw_config(tp); 3683 } 3684 3685 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3686 { 3687 if (rtl_is_8168evl_up(tp)) 3688 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3689 else 3690 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3691 3692 rtl_hw_config(tp); 3693 3694 /* disable interrupt coalescing */ 3695 RTL_W16(tp, IntrMitigate, 0x0000); 3696 } 3697 3698 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3699 { 3700 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3701 3702 tp->cp_cmd |= PCIMulRW; 3703 3704 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3705 tp->mac_version == RTL_GIGA_MAC_VER_03) 3706 tp->cp_cmd |= EnAnaPLL; 3707 3708 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3709 3710 rtl8169_set_magic_reg(tp); 3711 3712 /* disable interrupt coalescing */ 3713 RTL_W16(tp, IntrMitigate, 0x0000); 3714 } 3715 3716 static void rtl_hw_start(struct rtl8169_private *tp) 3717 { 3718 rtl_unlock_config_regs(tp); 3719 3720 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3721 3722 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3723 rtl_hw_start_8169(tp); 3724 else if (rtl_is_8125(tp)) 3725 rtl_hw_start_8125(tp); 3726 else 3727 rtl_hw_start_8168(tp); 3728 3729 rtl_enable_exit_l1(tp); 3730 rtl_set_rx_max_size(tp); 3731 rtl_set_rx_tx_desc_registers(tp); 3732 rtl_lock_config_regs(tp); 3733 3734 rtl_jumbo_config(tp); 3735 3736 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3737 rtl_pci_commit(tp); 3738 3739 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3740 rtl_init_rxcfg(tp); 3741 rtl_set_tx_config_registers(tp); 3742 rtl_set_rx_config_features(tp, tp->dev->features); 3743 rtl_set_rx_mode(tp->dev); 3744 rtl_irq_enable(tp); 3745 } 3746 3747 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3748 { 3749 struct rtl8169_private *tp = netdev_priv(dev); 3750 3751 dev->mtu = new_mtu; 3752 netdev_update_features(dev); 3753 rtl_jumbo_config(tp); 3754 3755 switch (tp->mac_version) { 3756 case RTL_GIGA_MAC_VER_61: 3757 case RTL_GIGA_MAC_VER_63: 3758 rtl8125_set_eee_txidle_timer(tp); 3759 break; 3760 default: 3761 break; 3762 } 3763 3764 return 0; 3765 } 3766 3767 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3768 { 3769 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3770 3771 desc->opts2 = 0; 3772 /* Force memory writes to complete before releasing descriptor */ 3773 dma_wmb(); 3774 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3775 } 3776 3777 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3778 struct RxDesc *desc) 3779 { 3780 struct device *d = tp_to_dev(tp); 3781 int node = dev_to_node(d); 3782 dma_addr_t mapping; 3783 struct page *data; 3784 3785 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3786 if (!data) 3787 return NULL; 3788 3789 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3790 if (unlikely(dma_mapping_error(d, mapping))) { 3791 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3792 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3793 return NULL; 3794 } 3795 3796 desc->addr = cpu_to_le64(mapping); 3797 rtl8169_mark_to_asic(desc); 3798 3799 return data; 3800 } 3801 3802 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3803 { 3804 int i; 3805 3806 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3807 dma_unmap_page(tp_to_dev(tp), 3808 le64_to_cpu(tp->RxDescArray[i].addr), 3809 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3810 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3811 tp->Rx_databuff[i] = NULL; 3812 tp->RxDescArray[i].addr = 0; 3813 tp->RxDescArray[i].opts1 = 0; 3814 } 3815 } 3816 3817 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3818 { 3819 int i; 3820 3821 for (i = 0; i < NUM_RX_DESC; i++) { 3822 struct page *data; 3823 3824 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3825 if (!data) { 3826 rtl8169_rx_clear(tp); 3827 return -ENOMEM; 3828 } 3829 tp->Rx_databuff[i] = data; 3830 } 3831 3832 /* mark as last descriptor in the ring */ 3833 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3834 3835 return 0; 3836 } 3837 3838 static int rtl8169_init_ring(struct rtl8169_private *tp) 3839 { 3840 rtl8169_init_ring_indexes(tp); 3841 3842 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3843 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3844 3845 return rtl8169_rx_fill(tp); 3846 } 3847 3848 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3849 { 3850 struct ring_info *tx_skb = tp->tx_skb + entry; 3851 struct TxDesc *desc = tp->TxDescArray + entry; 3852 3853 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3854 DMA_TO_DEVICE); 3855 memset(desc, 0, sizeof(*desc)); 3856 memset(tx_skb, 0, sizeof(*tx_skb)); 3857 } 3858 3859 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3860 unsigned int n) 3861 { 3862 unsigned int i; 3863 3864 for (i = 0; i < n; i++) { 3865 unsigned int entry = (start + i) % NUM_TX_DESC; 3866 struct ring_info *tx_skb = tp->tx_skb + entry; 3867 unsigned int len = tx_skb->len; 3868 3869 if (len) { 3870 struct sk_buff *skb = tx_skb->skb; 3871 3872 rtl8169_unmap_tx_skb(tp, entry); 3873 if (skb) 3874 dev_consume_skb_any(skb); 3875 } 3876 } 3877 } 3878 3879 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3880 { 3881 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3882 netdev_reset_queue(tp->dev); 3883 } 3884 3885 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3886 { 3887 napi_disable(&tp->napi); 3888 3889 /* Give a racing hard_start_xmit a few cycles to complete. */ 3890 synchronize_net(); 3891 3892 /* Disable interrupts */ 3893 rtl8169_irq_mask_and_ack(tp); 3894 3895 rtl_rx_close(tp); 3896 3897 if (going_down && tp->dev->wol_enabled) 3898 goto no_reset; 3899 3900 switch (tp->mac_version) { 3901 case RTL_GIGA_MAC_VER_28: 3902 case RTL_GIGA_MAC_VER_31: 3903 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3904 break; 3905 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3906 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3907 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3908 break; 3909 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3910 rtl_enable_rxdvgate(tp); 3911 fsleep(2000); 3912 break; 3913 default: 3914 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3915 fsleep(100); 3916 break; 3917 } 3918 3919 rtl_hw_reset(tp); 3920 no_reset: 3921 rtl8169_tx_clear(tp); 3922 rtl8169_init_ring_indexes(tp); 3923 } 3924 3925 static void rtl_reset_work(struct rtl8169_private *tp) 3926 { 3927 int i; 3928 3929 netif_stop_queue(tp->dev); 3930 3931 rtl8169_cleanup(tp, false); 3932 3933 for (i = 0; i < NUM_RX_DESC; i++) 3934 rtl8169_mark_to_asic(tp->RxDescArray + i); 3935 3936 napi_enable(&tp->napi); 3937 rtl_hw_start(tp); 3938 } 3939 3940 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3941 { 3942 struct rtl8169_private *tp = netdev_priv(dev); 3943 3944 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3945 } 3946 3947 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3948 void *addr, unsigned int entry, bool desc_own) 3949 { 3950 struct TxDesc *txd = tp->TxDescArray + entry; 3951 struct device *d = tp_to_dev(tp); 3952 dma_addr_t mapping; 3953 u32 opts1; 3954 int ret; 3955 3956 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3957 ret = dma_mapping_error(d, mapping); 3958 if (unlikely(ret)) { 3959 if (net_ratelimit()) 3960 netdev_err(tp->dev, "Failed to map TX data!\n"); 3961 return ret; 3962 } 3963 3964 txd->addr = cpu_to_le64(mapping); 3965 txd->opts2 = cpu_to_le32(opts[1]); 3966 3967 opts1 = opts[0] | len; 3968 if (entry == NUM_TX_DESC - 1) 3969 opts1 |= RingEnd; 3970 if (desc_own) 3971 opts1 |= DescOwn; 3972 txd->opts1 = cpu_to_le32(opts1); 3973 3974 tp->tx_skb[entry].len = len; 3975 3976 return 0; 3977 } 3978 3979 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3980 const u32 *opts, unsigned int entry) 3981 { 3982 struct skb_shared_info *info = skb_shinfo(skb); 3983 unsigned int cur_frag; 3984 3985 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 3986 const skb_frag_t *frag = info->frags + cur_frag; 3987 void *addr = skb_frag_address(frag); 3988 u32 len = skb_frag_size(frag); 3989 3990 entry = (entry + 1) % NUM_TX_DESC; 3991 3992 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 3993 goto err_out; 3994 } 3995 3996 return 0; 3997 3998 err_out: 3999 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4000 return -EIO; 4001 } 4002 4003 static bool rtl_skb_is_udp(struct sk_buff *skb) 4004 { 4005 int no = skb_network_offset(skb); 4006 struct ipv6hdr *i6h, _i6h; 4007 struct iphdr *ih, _ih; 4008 4009 switch (vlan_get_protocol(skb)) { 4010 case htons(ETH_P_IP): 4011 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4012 return ih && ih->protocol == IPPROTO_UDP; 4013 case htons(ETH_P_IPV6): 4014 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4015 return i6h && i6h->nexthdr == IPPROTO_UDP; 4016 default: 4017 return false; 4018 } 4019 } 4020 4021 #define RTL_MIN_PATCH_LEN 47 4022 4023 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4024 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4025 struct sk_buff *skb) 4026 { 4027 unsigned int padto = 0, len = skb->len; 4028 4029 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4030 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4031 unsigned int trans_data_len = skb_tail_pointer(skb) - 4032 skb_transport_header(skb); 4033 4034 if (trans_data_len >= offsetof(struct udphdr, len) && 4035 trans_data_len < RTL_MIN_PATCH_LEN) { 4036 u16 dest = ntohs(udp_hdr(skb)->dest); 4037 4038 /* dest is a standard PTP port */ 4039 if (dest == 319 || dest == 320) 4040 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4041 } 4042 4043 if (trans_data_len < sizeof(struct udphdr)) 4044 padto = max_t(unsigned int, padto, 4045 len + sizeof(struct udphdr) - trans_data_len); 4046 } 4047 4048 return padto; 4049 } 4050 4051 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4052 struct sk_buff *skb) 4053 { 4054 unsigned int padto; 4055 4056 padto = rtl8125_quirk_udp_padto(tp, skb); 4057 4058 switch (tp->mac_version) { 4059 case RTL_GIGA_MAC_VER_34: 4060 case RTL_GIGA_MAC_VER_61: 4061 case RTL_GIGA_MAC_VER_63: 4062 padto = max_t(unsigned int, padto, ETH_ZLEN); 4063 break; 4064 default: 4065 break; 4066 } 4067 4068 return padto; 4069 } 4070 4071 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4072 { 4073 u32 mss = skb_shinfo(skb)->gso_size; 4074 4075 if (mss) { 4076 opts[0] |= TD_LSO; 4077 opts[0] |= mss << TD0_MSS_SHIFT; 4078 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4079 const struct iphdr *ip = ip_hdr(skb); 4080 4081 if (ip->protocol == IPPROTO_TCP) 4082 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4083 else if (ip->protocol == IPPROTO_UDP) 4084 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4085 else 4086 WARN_ON_ONCE(1); 4087 } 4088 } 4089 4090 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4091 struct sk_buff *skb, u32 *opts) 4092 { 4093 struct skb_shared_info *shinfo = skb_shinfo(skb); 4094 u32 mss = shinfo->gso_size; 4095 4096 if (mss) { 4097 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4098 opts[0] |= TD1_GTSENV4; 4099 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4100 if (skb_cow_head(skb, 0)) 4101 return false; 4102 4103 tcp_v6_gso_csum_prep(skb); 4104 opts[0] |= TD1_GTSENV6; 4105 } else { 4106 WARN_ON_ONCE(1); 4107 } 4108 4109 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4110 opts[1] |= mss << TD1_MSS_SHIFT; 4111 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4112 u8 ip_protocol; 4113 4114 switch (vlan_get_protocol(skb)) { 4115 case htons(ETH_P_IP): 4116 opts[1] |= TD1_IPv4_CS; 4117 ip_protocol = ip_hdr(skb)->protocol; 4118 break; 4119 4120 case htons(ETH_P_IPV6): 4121 opts[1] |= TD1_IPv6_CS; 4122 ip_protocol = ipv6_hdr(skb)->nexthdr; 4123 break; 4124 4125 default: 4126 ip_protocol = IPPROTO_RAW; 4127 break; 4128 } 4129 4130 if (ip_protocol == IPPROTO_TCP) 4131 opts[1] |= TD1_TCP_CS; 4132 else if (ip_protocol == IPPROTO_UDP) 4133 opts[1] |= TD1_UDP_CS; 4134 else 4135 WARN_ON_ONCE(1); 4136 4137 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4138 } else { 4139 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4140 4141 /* skb_padto would free the skb on error */ 4142 return !__skb_put_padto(skb, padto, false); 4143 } 4144 4145 return true; 4146 } 4147 4148 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4149 { 4150 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4151 - READ_ONCE(tp->cur_tx); 4152 4153 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4154 return slots_avail > MAX_SKB_FRAGS; 4155 } 4156 4157 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4158 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4159 { 4160 switch (tp->mac_version) { 4161 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4162 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4163 return false; 4164 default: 4165 return true; 4166 } 4167 } 4168 4169 static void rtl8169_doorbell(struct rtl8169_private *tp) 4170 { 4171 if (rtl_is_8125(tp)) 4172 RTL_W16(tp, TxPoll_8125, BIT(0)); 4173 else 4174 RTL_W8(tp, TxPoll, NPQ); 4175 } 4176 4177 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4178 struct net_device *dev) 4179 { 4180 unsigned int frags = skb_shinfo(skb)->nr_frags; 4181 struct rtl8169_private *tp = netdev_priv(dev); 4182 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4183 struct TxDesc *txd_first, *txd_last; 4184 bool stop_queue, door_bell; 4185 u32 opts[2]; 4186 4187 if (unlikely(!rtl_tx_slots_avail(tp))) { 4188 if (net_ratelimit()) 4189 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4190 goto err_stop_0; 4191 } 4192 4193 opts[1] = rtl8169_tx_vlan_tag(skb); 4194 opts[0] = 0; 4195 4196 if (!rtl_chip_supports_csum_v2(tp)) 4197 rtl8169_tso_csum_v1(skb, opts); 4198 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4199 goto err_dma_0; 4200 4201 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4202 entry, false))) 4203 goto err_dma_0; 4204 4205 txd_first = tp->TxDescArray + entry; 4206 4207 if (frags) { 4208 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4209 goto err_dma_1; 4210 entry = (entry + frags) % NUM_TX_DESC; 4211 } 4212 4213 txd_last = tp->TxDescArray + entry; 4214 txd_last->opts1 |= cpu_to_le32(LastFrag); 4215 tp->tx_skb[entry].skb = skb; 4216 4217 skb_tx_timestamp(skb); 4218 4219 /* Force memory writes to complete before releasing descriptor */ 4220 dma_wmb(); 4221 4222 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4223 4224 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4225 4226 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4227 smp_wmb(); 4228 4229 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4230 4231 stop_queue = !rtl_tx_slots_avail(tp); 4232 if (unlikely(stop_queue)) { 4233 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4234 * not miss a ring update when it notices a stopped queue. 4235 */ 4236 smp_wmb(); 4237 netif_stop_queue(dev); 4238 /* Sync with rtl_tx: 4239 * - publish queue status and cur_tx ring index (write barrier) 4240 * - refresh dirty_tx ring index (read barrier). 4241 * May the current thread have a pessimistic view of the ring 4242 * status and forget to wake up queue, a racing rtl_tx thread 4243 * can't. 4244 */ 4245 smp_mb__after_atomic(); 4246 if (rtl_tx_slots_avail(tp)) 4247 netif_start_queue(dev); 4248 door_bell = true; 4249 } 4250 4251 if (door_bell) 4252 rtl8169_doorbell(tp); 4253 4254 return NETDEV_TX_OK; 4255 4256 err_dma_1: 4257 rtl8169_unmap_tx_skb(tp, entry); 4258 err_dma_0: 4259 dev_kfree_skb_any(skb); 4260 dev->stats.tx_dropped++; 4261 return NETDEV_TX_OK; 4262 4263 err_stop_0: 4264 netif_stop_queue(dev); 4265 dev->stats.tx_dropped++; 4266 return NETDEV_TX_BUSY; 4267 } 4268 4269 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4270 { 4271 struct skb_shared_info *info = skb_shinfo(skb); 4272 unsigned int nr_frags = info->nr_frags; 4273 4274 if (!nr_frags) 4275 return UINT_MAX; 4276 4277 return skb_frag_size(info->frags + nr_frags - 1); 4278 } 4279 4280 /* Workaround for hw issues with TSO on RTL8168evl */ 4281 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4282 netdev_features_t features) 4283 { 4284 /* IPv4 header has options field */ 4285 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4286 ip_hdrlen(skb) > sizeof(struct iphdr)) 4287 features &= ~NETIF_F_ALL_TSO; 4288 4289 /* IPv4 TCP header has options field */ 4290 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4291 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4292 features &= ~NETIF_F_ALL_TSO; 4293 4294 else if (rtl_last_frag_len(skb) <= 6) 4295 features &= ~NETIF_F_ALL_TSO; 4296 4297 return features; 4298 } 4299 4300 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4301 struct net_device *dev, 4302 netdev_features_t features) 4303 { 4304 struct rtl8169_private *tp = netdev_priv(dev); 4305 4306 if (skb_is_gso(skb)) { 4307 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4308 features = rtl8168evl_fix_tso(skb, features); 4309 4310 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4311 rtl_chip_supports_csum_v2(tp)) 4312 features &= ~NETIF_F_ALL_TSO; 4313 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4314 /* work around hw bug on some chip versions */ 4315 if (skb->len < ETH_ZLEN) 4316 features &= ~NETIF_F_CSUM_MASK; 4317 4318 if (rtl_quirk_packet_padto(tp, skb)) 4319 features &= ~NETIF_F_CSUM_MASK; 4320 4321 if (skb_transport_offset(skb) > TCPHO_MAX && 4322 rtl_chip_supports_csum_v2(tp)) 4323 features &= ~NETIF_F_CSUM_MASK; 4324 } 4325 4326 return vlan_features_check(skb, features); 4327 } 4328 4329 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4330 { 4331 struct rtl8169_private *tp = netdev_priv(dev); 4332 struct pci_dev *pdev = tp->pci_dev; 4333 int pci_status_errs; 4334 u16 pci_cmd; 4335 4336 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4337 4338 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4339 4340 if (net_ratelimit()) 4341 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4342 pci_cmd, pci_status_errs); 4343 4344 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4345 } 4346 4347 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4348 int budget) 4349 { 4350 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4351 struct sk_buff *skb; 4352 4353 dirty_tx = tp->dirty_tx; 4354 4355 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4356 unsigned int entry = dirty_tx % NUM_TX_DESC; 4357 u32 status; 4358 4359 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4360 if (status & DescOwn) 4361 break; 4362 4363 skb = tp->tx_skb[entry].skb; 4364 rtl8169_unmap_tx_skb(tp, entry); 4365 4366 if (skb) { 4367 pkts_compl++; 4368 bytes_compl += skb->len; 4369 napi_consume_skb(skb, budget); 4370 } 4371 dirty_tx++; 4372 } 4373 4374 if (tp->dirty_tx != dirty_tx) { 4375 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4376 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4377 4378 /* Sync with rtl8169_start_xmit: 4379 * - publish dirty_tx ring index (write barrier) 4380 * - refresh cur_tx ring index and queue status (read barrier) 4381 * May the current thread miss the stopped queue condition, 4382 * a racing xmit thread can only have a right view of the 4383 * ring status. 4384 */ 4385 smp_store_mb(tp->dirty_tx, dirty_tx); 4386 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4387 netif_wake_queue(dev); 4388 /* 4389 * 8168 hack: TxPoll requests are lost when the Tx packets are 4390 * too close. Let's kick an extra TxPoll request when a burst 4391 * of start_xmit activity is detected (if it is not detected, 4392 * it is slow enough). -- FR 4393 * If skb is NULL then we come here again once a tx irq is 4394 * triggered after the last fragment is marked transmitted. 4395 */ 4396 if (tp->cur_tx != dirty_tx && skb) 4397 rtl8169_doorbell(tp); 4398 } 4399 } 4400 4401 static inline int rtl8169_fragmented_frame(u32 status) 4402 { 4403 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4404 } 4405 4406 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4407 { 4408 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4409 4410 if (status == RxProtoTCP || status == RxProtoUDP) 4411 skb->ip_summed = CHECKSUM_UNNECESSARY; 4412 else 4413 skb_checksum_none_assert(skb); 4414 } 4415 4416 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4417 { 4418 struct device *d = tp_to_dev(tp); 4419 int count; 4420 4421 for (count = 0; count < budget; count++, tp->cur_rx++) { 4422 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4423 struct RxDesc *desc = tp->RxDescArray + entry; 4424 struct sk_buff *skb; 4425 const void *rx_buf; 4426 dma_addr_t addr; 4427 u32 status; 4428 4429 status = le32_to_cpu(desc->opts1); 4430 if (status & DescOwn) 4431 break; 4432 4433 /* This barrier is needed to keep us from reading 4434 * any other fields out of the Rx descriptor until 4435 * we know the status of DescOwn 4436 */ 4437 dma_rmb(); 4438 4439 if (unlikely(status & RxRES)) { 4440 if (net_ratelimit()) 4441 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4442 status); 4443 dev->stats.rx_errors++; 4444 if (status & (RxRWT | RxRUNT)) 4445 dev->stats.rx_length_errors++; 4446 if (status & RxCRC) 4447 dev->stats.rx_crc_errors++; 4448 4449 if (!(dev->features & NETIF_F_RXALL)) 4450 goto release_descriptor; 4451 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4452 goto release_descriptor; 4453 } 4454 4455 pkt_size = status & GENMASK(13, 0); 4456 if (likely(!(dev->features & NETIF_F_RXFCS))) 4457 pkt_size -= ETH_FCS_LEN; 4458 4459 /* The driver does not support incoming fragmented frames. 4460 * They are seen as a symptom of over-mtu sized frames. 4461 */ 4462 if (unlikely(rtl8169_fragmented_frame(status))) { 4463 dev->stats.rx_dropped++; 4464 dev->stats.rx_length_errors++; 4465 goto release_descriptor; 4466 } 4467 4468 skb = napi_alloc_skb(&tp->napi, pkt_size); 4469 if (unlikely(!skb)) { 4470 dev->stats.rx_dropped++; 4471 goto release_descriptor; 4472 } 4473 4474 addr = le64_to_cpu(desc->addr); 4475 rx_buf = page_address(tp->Rx_databuff[entry]); 4476 4477 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4478 prefetch(rx_buf); 4479 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4480 skb->tail += pkt_size; 4481 skb->len = pkt_size; 4482 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4483 4484 rtl8169_rx_csum(skb, status); 4485 skb->protocol = eth_type_trans(skb, dev); 4486 4487 rtl8169_rx_vlan_tag(desc, skb); 4488 4489 if (skb->pkt_type == PACKET_MULTICAST) 4490 dev->stats.multicast++; 4491 4492 napi_gro_receive(&tp->napi, skb); 4493 4494 dev_sw_netstats_rx_add(dev, pkt_size); 4495 release_descriptor: 4496 rtl8169_mark_to_asic(desc); 4497 } 4498 4499 return count; 4500 } 4501 4502 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4503 { 4504 struct rtl8169_private *tp = dev_instance; 4505 u32 status = rtl_get_events(tp); 4506 4507 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4508 return IRQ_NONE; 4509 4510 if (unlikely(status & SYSErr)) { 4511 rtl8169_pcierr_interrupt(tp->dev); 4512 goto out; 4513 } 4514 4515 if (status & LinkChg) 4516 phy_mac_interrupt(tp->phydev); 4517 4518 if (unlikely(status & RxFIFOOver && 4519 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4520 netif_stop_queue(tp->dev); 4521 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4522 } 4523 4524 if (napi_schedule_prep(&tp->napi)) { 4525 rtl_irq_disable(tp); 4526 __napi_schedule(&tp->napi); 4527 } 4528 out: 4529 rtl_ack_events(tp, status); 4530 4531 return IRQ_HANDLED; 4532 } 4533 4534 static void rtl_task(struct work_struct *work) 4535 { 4536 struct rtl8169_private *tp = 4537 container_of(work, struct rtl8169_private, wk.work); 4538 4539 rtnl_lock(); 4540 4541 if (!netif_running(tp->dev) || 4542 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4543 goto out_unlock; 4544 4545 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4546 rtl_reset_work(tp); 4547 netif_wake_queue(tp->dev); 4548 } 4549 out_unlock: 4550 rtnl_unlock(); 4551 } 4552 4553 static int rtl8169_poll(struct napi_struct *napi, int budget) 4554 { 4555 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4556 struct net_device *dev = tp->dev; 4557 int work_done; 4558 4559 rtl_tx(dev, tp, budget); 4560 4561 work_done = rtl_rx(dev, tp, budget); 4562 4563 if (work_done < budget && napi_complete_done(napi, work_done)) 4564 rtl_irq_enable(tp); 4565 4566 return work_done; 4567 } 4568 4569 static void r8169_phylink_handler(struct net_device *ndev) 4570 { 4571 struct rtl8169_private *tp = netdev_priv(ndev); 4572 4573 if (netif_carrier_ok(ndev)) { 4574 rtl_link_chg_patch(tp); 4575 pm_request_resume(&tp->pci_dev->dev); 4576 } else { 4577 pm_runtime_idle(&tp->pci_dev->dev); 4578 } 4579 4580 if (net_ratelimit()) 4581 phy_print_status(tp->phydev); 4582 } 4583 4584 static int r8169_phy_connect(struct rtl8169_private *tp) 4585 { 4586 struct phy_device *phydev = tp->phydev; 4587 phy_interface_t phy_mode; 4588 int ret; 4589 4590 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4591 PHY_INTERFACE_MODE_MII; 4592 4593 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4594 phy_mode); 4595 if (ret) 4596 return ret; 4597 4598 if (!tp->supports_gmii) 4599 phy_set_max_speed(phydev, SPEED_100); 4600 4601 phy_attached_info(phydev); 4602 4603 return 0; 4604 } 4605 4606 static void rtl8169_down(struct rtl8169_private *tp) 4607 { 4608 /* Clear all task flags */ 4609 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4610 4611 phy_stop(tp->phydev); 4612 4613 rtl8169_update_counters(tp); 4614 4615 pci_clear_master(tp->pci_dev); 4616 rtl_pci_commit(tp); 4617 4618 rtl8169_cleanup(tp, true); 4619 rtl_disable_exit_l1(tp); 4620 rtl_prepare_power_down(tp); 4621 } 4622 4623 static void rtl8169_up(struct rtl8169_private *tp) 4624 { 4625 pci_set_master(tp->pci_dev); 4626 phy_init_hw(tp->phydev); 4627 phy_resume(tp->phydev); 4628 rtl8169_init_phy(tp); 4629 napi_enable(&tp->napi); 4630 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4631 rtl_reset_work(tp); 4632 4633 phy_start(tp->phydev); 4634 } 4635 4636 static int rtl8169_close(struct net_device *dev) 4637 { 4638 struct rtl8169_private *tp = netdev_priv(dev); 4639 struct pci_dev *pdev = tp->pci_dev; 4640 4641 pm_runtime_get_sync(&pdev->dev); 4642 4643 netif_stop_queue(dev); 4644 rtl8169_down(tp); 4645 rtl8169_rx_clear(tp); 4646 4647 cancel_work_sync(&tp->wk.work); 4648 4649 free_irq(tp->irq, tp); 4650 4651 phy_disconnect(tp->phydev); 4652 4653 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4654 tp->RxPhyAddr); 4655 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4656 tp->TxPhyAddr); 4657 tp->TxDescArray = NULL; 4658 tp->RxDescArray = NULL; 4659 4660 pm_runtime_put_sync(&pdev->dev); 4661 4662 return 0; 4663 } 4664 4665 #ifdef CONFIG_NET_POLL_CONTROLLER 4666 static void rtl8169_netpoll(struct net_device *dev) 4667 { 4668 struct rtl8169_private *tp = netdev_priv(dev); 4669 4670 rtl8169_interrupt(tp->irq, tp); 4671 } 4672 #endif 4673 4674 static int rtl_open(struct net_device *dev) 4675 { 4676 struct rtl8169_private *tp = netdev_priv(dev); 4677 struct pci_dev *pdev = tp->pci_dev; 4678 unsigned long irqflags; 4679 int retval = -ENOMEM; 4680 4681 pm_runtime_get_sync(&pdev->dev); 4682 4683 /* 4684 * Rx and Tx descriptors needs 256 bytes alignment. 4685 * dma_alloc_coherent provides more. 4686 */ 4687 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4688 &tp->TxPhyAddr, GFP_KERNEL); 4689 if (!tp->TxDescArray) 4690 goto out; 4691 4692 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4693 &tp->RxPhyAddr, GFP_KERNEL); 4694 if (!tp->RxDescArray) 4695 goto err_free_tx_0; 4696 4697 retval = rtl8169_init_ring(tp); 4698 if (retval < 0) 4699 goto err_free_rx_1; 4700 4701 rtl_request_firmware(tp); 4702 4703 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4704 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4705 if (retval < 0) 4706 goto err_release_fw_2; 4707 4708 retval = r8169_phy_connect(tp); 4709 if (retval) 4710 goto err_free_irq; 4711 4712 rtl8169_up(tp); 4713 rtl8169_init_counter_offsets(tp); 4714 netif_start_queue(dev); 4715 out: 4716 pm_runtime_put_sync(&pdev->dev); 4717 4718 return retval; 4719 4720 err_free_irq: 4721 free_irq(tp->irq, tp); 4722 err_release_fw_2: 4723 rtl_release_firmware(tp); 4724 rtl8169_rx_clear(tp); 4725 err_free_rx_1: 4726 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4727 tp->RxPhyAddr); 4728 tp->RxDescArray = NULL; 4729 err_free_tx_0: 4730 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4731 tp->TxPhyAddr); 4732 tp->TxDescArray = NULL; 4733 goto out; 4734 } 4735 4736 static void 4737 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4738 { 4739 struct rtl8169_private *tp = netdev_priv(dev); 4740 struct pci_dev *pdev = tp->pci_dev; 4741 struct rtl8169_counters *counters = tp->counters; 4742 4743 pm_runtime_get_noresume(&pdev->dev); 4744 4745 netdev_stats_to_stats64(stats, &dev->stats); 4746 dev_fetch_sw_netstats(stats, dev->tstats); 4747 4748 /* 4749 * Fetch additional counter values missing in stats collected by driver 4750 * from tally counters. 4751 */ 4752 if (pm_runtime_active(&pdev->dev)) 4753 rtl8169_update_counters(tp); 4754 4755 /* 4756 * Subtract values fetched during initalization. 4757 * See rtl8169_init_counter_offsets for a description why we do that. 4758 */ 4759 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4760 le64_to_cpu(tp->tc_offset.tx_errors); 4761 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4762 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4763 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4764 le16_to_cpu(tp->tc_offset.tx_aborted); 4765 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4766 le16_to_cpu(tp->tc_offset.rx_missed); 4767 4768 pm_runtime_put_noidle(&pdev->dev); 4769 } 4770 4771 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4772 { 4773 netif_device_detach(tp->dev); 4774 4775 if (netif_running(tp->dev)) 4776 rtl8169_down(tp); 4777 } 4778 4779 static int rtl8169_runtime_resume(struct device *dev) 4780 { 4781 struct rtl8169_private *tp = dev_get_drvdata(dev); 4782 4783 rtl_rar_set(tp, tp->dev->dev_addr); 4784 __rtl8169_set_wol(tp, tp->saved_wolopts); 4785 4786 if (tp->TxDescArray) 4787 rtl8169_up(tp); 4788 4789 netif_device_attach(tp->dev); 4790 4791 return 0; 4792 } 4793 4794 static int rtl8169_suspend(struct device *device) 4795 { 4796 struct rtl8169_private *tp = dev_get_drvdata(device); 4797 4798 rtnl_lock(); 4799 rtl8169_net_suspend(tp); 4800 if (!device_may_wakeup(tp_to_dev(tp))) 4801 clk_disable_unprepare(tp->clk); 4802 rtnl_unlock(); 4803 4804 return 0; 4805 } 4806 4807 static int rtl8169_resume(struct device *device) 4808 { 4809 struct rtl8169_private *tp = dev_get_drvdata(device); 4810 4811 if (!device_may_wakeup(tp_to_dev(tp))) 4812 clk_prepare_enable(tp->clk); 4813 4814 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4815 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4816 rtl_init_rxcfg(tp); 4817 4818 return rtl8169_runtime_resume(device); 4819 } 4820 4821 static int rtl8169_runtime_suspend(struct device *device) 4822 { 4823 struct rtl8169_private *tp = dev_get_drvdata(device); 4824 4825 if (!tp->TxDescArray) { 4826 netif_device_detach(tp->dev); 4827 return 0; 4828 } 4829 4830 rtnl_lock(); 4831 __rtl8169_set_wol(tp, WAKE_PHY); 4832 rtl8169_net_suspend(tp); 4833 rtnl_unlock(); 4834 4835 return 0; 4836 } 4837 4838 static int rtl8169_runtime_idle(struct device *device) 4839 { 4840 struct rtl8169_private *tp = dev_get_drvdata(device); 4841 4842 if (tp->dash_type != RTL_DASH_NONE) 4843 return -EBUSY; 4844 4845 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4846 pm_schedule_suspend(device, 10000); 4847 4848 return -EBUSY; 4849 } 4850 4851 static const struct dev_pm_ops rtl8169_pm_ops = { 4852 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4853 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4854 rtl8169_runtime_idle) 4855 }; 4856 4857 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4858 { 4859 /* WoL fails with 8168b when the receiver is disabled. */ 4860 switch (tp->mac_version) { 4861 case RTL_GIGA_MAC_VER_11: 4862 case RTL_GIGA_MAC_VER_12: 4863 case RTL_GIGA_MAC_VER_17: 4864 pci_clear_master(tp->pci_dev); 4865 4866 RTL_W8(tp, ChipCmd, CmdRxEnb); 4867 rtl_pci_commit(tp); 4868 break; 4869 default: 4870 break; 4871 } 4872 } 4873 4874 static void rtl_shutdown(struct pci_dev *pdev) 4875 { 4876 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4877 4878 rtnl_lock(); 4879 rtl8169_net_suspend(tp); 4880 rtnl_unlock(); 4881 4882 /* Restore original MAC address */ 4883 rtl_rar_set(tp, tp->dev->perm_addr); 4884 4885 if (system_state == SYSTEM_POWER_OFF && 4886 tp->dash_type == RTL_DASH_NONE) { 4887 if (tp->saved_wolopts) 4888 rtl_wol_shutdown_quirk(tp); 4889 4890 pci_wake_from_d3(pdev, tp->saved_wolopts); 4891 pci_set_power_state(pdev, PCI_D3hot); 4892 } 4893 } 4894 4895 static void rtl_remove_one(struct pci_dev *pdev) 4896 { 4897 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4898 4899 if (pci_dev_run_wake(pdev)) 4900 pm_runtime_get_noresume(&pdev->dev); 4901 4902 unregister_netdev(tp->dev); 4903 4904 if (tp->dash_type != RTL_DASH_NONE) 4905 rtl8168_driver_stop(tp); 4906 4907 rtl_release_firmware(tp); 4908 4909 /* restore original MAC address */ 4910 rtl_rar_set(tp, tp->dev->perm_addr); 4911 } 4912 4913 static const struct net_device_ops rtl_netdev_ops = { 4914 .ndo_open = rtl_open, 4915 .ndo_stop = rtl8169_close, 4916 .ndo_get_stats64 = rtl8169_get_stats64, 4917 .ndo_start_xmit = rtl8169_start_xmit, 4918 .ndo_features_check = rtl8169_features_check, 4919 .ndo_tx_timeout = rtl8169_tx_timeout, 4920 .ndo_validate_addr = eth_validate_addr, 4921 .ndo_change_mtu = rtl8169_change_mtu, 4922 .ndo_fix_features = rtl8169_fix_features, 4923 .ndo_set_features = rtl8169_set_features, 4924 .ndo_set_mac_address = rtl_set_mac_address, 4925 .ndo_eth_ioctl = phy_do_ioctl_running, 4926 .ndo_set_rx_mode = rtl_set_rx_mode, 4927 #ifdef CONFIG_NET_POLL_CONTROLLER 4928 .ndo_poll_controller = rtl8169_netpoll, 4929 #endif 4930 4931 }; 4932 4933 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4934 { 4935 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4936 4937 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4938 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4939 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4940 /* special workaround needed */ 4941 tp->irq_mask |= RxFIFOOver; 4942 else 4943 tp->irq_mask |= RxOverflow; 4944 } 4945 4946 static int rtl_alloc_irq(struct rtl8169_private *tp) 4947 { 4948 unsigned int flags; 4949 4950 switch (tp->mac_version) { 4951 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4952 rtl_unlock_config_regs(tp); 4953 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4954 rtl_lock_config_regs(tp); 4955 fallthrough; 4956 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4957 flags = PCI_IRQ_LEGACY; 4958 break; 4959 default: 4960 flags = PCI_IRQ_ALL_TYPES; 4961 break; 4962 } 4963 4964 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4965 } 4966 4967 static void rtl_read_mac_address(struct rtl8169_private *tp, 4968 u8 mac_addr[ETH_ALEN]) 4969 { 4970 /* Get MAC address */ 4971 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 4972 u32 value; 4973 4974 value = rtl_eri_read(tp, 0xe0); 4975 put_unaligned_le32(value, mac_addr); 4976 value = rtl_eri_read(tp, 0xe4); 4977 put_unaligned_le16(value, mac_addr + 4); 4978 } else if (rtl_is_8125(tp)) { 4979 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 4980 } 4981 } 4982 4983 DECLARE_RTL_COND(rtl_link_list_ready_cond) 4984 { 4985 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 4986 } 4987 4988 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 4989 { 4990 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 4991 } 4992 4993 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 4994 { 4995 struct rtl8169_private *tp = mii_bus->priv; 4996 4997 if (phyaddr > 0) 4998 return -ENODEV; 4999 5000 return rtl_readphy(tp, phyreg); 5001 } 5002 5003 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5004 int phyreg, u16 val) 5005 { 5006 struct rtl8169_private *tp = mii_bus->priv; 5007 5008 if (phyaddr > 0) 5009 return -ENODEV; 5010 5011 rtl_writephy(tp, phyreg, val); 5012 5013 return 0; 5014 } 5015 5016 static int r8169_mdio_register(struct rtl8169_private *tp) 5017 { 5018 struct pci_dev *pdev = tp->pci_dev; 5019 struct mii_bus *new_bus; 5020 int ret; 5021 5022 new_bus = devm_mdiobus_alloc(&pdev->dev); 5023 if (!new_bus) 5024 return -ENOMEM; 5025 5026 new_bus->name = "r8169"; 5027 new_bus->priv = tp; 5028 new_bus->parent = &pdev->dev; 5029 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5030 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5031 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5032 5033 new_bus->read = r8169_mdio_read_reg; 5034 new_bus->write = r8169_mdio_write_reg; 5035 5036 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5037 if (ret) 5038 return ret; 5039 5040 tp->phydev = mdiobus_get_phy(new_bus, 0); 5041 if (!tp->phydev) { 5042 return -ENODEV; 5043 } else if (!tp->phydev->drv) { 5044 /* Most chip versions fail with the genphy driver. 5045 * Therefore ensure that the dedicated PHY driver is loaded. 5046 */ 5047 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5048 tp->phydev->phy_id); 5049 return -EUNATCH; 5050 } 5051 5052 tp->phydev->mac_managed_pm = 1; 5053 5054 phy_support_asym_pause(tp->phydev); 5055 5056 /* PHY will be woken up in rtl_open() */ 5057 phy_suspend(tp->phydev); 5058 5059 return 0; 5060 } 5061 5062 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5063 { 5064 rtl_enable_rxdvgate(tp); 5065 5066 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5067 msleep(1); 5068 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5069 5070 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5071 r8168g_wait_ll_share_fifo_ready(tp); 5072 5073 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5074 r8168g_wait_ll_share_fifo_ready(tp); 5075 } 5076 5077 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5078 { 5079 rtl_enable_rxdvgate(tp); 5080 5081 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5082 msleep(1); 5083 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5084 5085 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5086 r8168g_wait_ll_share_fifo_ready(tp); 5087 5088 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5089 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5090 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5091 r8168g_wait_ll_share_fifo_ready(tp); 5092 } 5093 5094 static void rtl_hw_initialize(struct rtl8169_private *tp) 5095 { 5096 switch (tp->mac_version) { 5097 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5098 rtl8168ep_stop_cmac(tp); 5099 fallthrough; 5100 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5101 rtl_hw_init_8168g(tp); 5102 break; 5103 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5104 rtl_hw_init_8125(tp); 5105 break; 5106 default: 5107 break; 5108 } 5109 } 5110 5111 static int rtl_jumbo_max(struct rtl8169_private *tp) 5112 { 5113 /* Non-GBit versions don't support jumbo frames */ 5114 if (!tp->supports_gmii) 5115 return 0; 5116 5117 switch (tp->mac_version) { 5118 /* RTL8169 */ 5119 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5120 return JUMBO_7K; 5121 /* RTL8168b */ 5122 case RTL_GIGA_MAC_VER_11: 5123 case RTL_GIGA_MAC_VER_12: 5124 case RTL_GIGA_MAC_VER_17: 5125 return JUMBO_4K; 5126 /* RTL8168c */ 5127 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5128 return JUMBO_6K; 5129 default: 5130 return JUMBO_9K; 5131 } 5132 } 5133 5134 static void rtl_disable_clk(void *data) 5135 { 5136 clk_disable_unprepare(data); 5137 } 5138 5139 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5140 { 5141 struct device *d = tp_to_dev(tp); 5142 struct clk *clk; 5143 int rc; 5144 5145 clk = devm_clk_get(d, "ether_clk"); 5146 if (IS_ERR(clk)) { 5147 rc = PTR_ERR(clk); 5148 if (rc == -ENOENT) 5149 /* clk-core allows NULL (for suspend / resume) */ 5150 rc = 0; 5151 else 5152 dev_err_probe(d, rc, "failed to get clk\n"); 5153 } else { 5154 tp->clk = clk; 5155 rc = clk_prepare_enable(clk); 5156 if (rc) 5157 dev_err(d, "failed to enable clk: %d\n", rc); 5158 else 5159 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5160 } 5161 5162 return rc; 5163 } 5164 5165 static void rtl_init_mac_address(struct rtl8169_private *tp) 5166 { 5167 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5168 struct net_device *dev = tp->dev; 5169 int rc; 5170 5171 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5172 if (!rc) 5173 goto done; 5174 5175 rtl_read_mac_address(tp, mac_addr); 5176 if (is_valid_ether_addr(mac_addr)) 5177 goto done; 5178 5179 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5180 if (is_valid_ether_addr(mac_addr)) 5181 goto done; 5182 5183 eth_random_addr(mac_addr); 5184 dev->addr_assign_type = NET_ADDR_RANDOM; 5185 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5186 done: 5187 eth_hw_addr_set(dev, mac_addr); 5188 rtl_rar_set(tp, mac_addr); 5189 } 5190 5191 /* register is set if system vendor successfully tested ASPM 1.2 */ 5192 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5193 { 5194 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5195 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5196 return true; 5197 5198 return false; 5199 } 5200 5201 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5202 { 5203 struct rtl8169_private *tp; 5204 int jumbo_max, region, rc; 5205 enum mac_version chipset; 5206 struct net_device *dev; 5207 u16 xid; 5208 5209 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5210 if (!dev) 5211 return -ENOMEM; 5212 5213 SET_NETDEV_DEV(dev, &pdev->dev); 5214 dev->netdev_ops = &rtl_netdev_ops; 5215 tp = netdev_priv(dev); 5216 tp->dev = dev; 5217 tp->pci_dev = pdev; 5218 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5219 tp->eee_adv = -1; 5220 tp->ocp_base = OCP_STD_PHY_BASE; 5221 5222 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5223 struct pcpu_sw_netstats); 5224 if (!dev->tstats) 5225 return -ENOMEM; 5226 5227 /* Get the *optional* external "ether_clk" used on some boards */ 5228 rc = rtl_get_ether_clk(tp); 5229 if (rc) 5230 return rc; 5231 5232 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5233 rc = pcim_enable_device(pdev); 5234 if (rc < 0) { 5235 dev_err(&pdev->dev, "enable failure\n"); 5236 return rc; 5237 } 5238 5239 if (pcim_set_mwi(pdev) < 0) 5240 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5241 5242 /* use first MMIO region */ 5243 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5244 if (region < 0) { 5245 dev_err(&pdev->dev, "no MMIO resource found\n"); 5246 return -ENODEV; 5247 } 5248 5249 /* check for weird/broken PCI region reporting */ 5250 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5251 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5252 return -ENODEV; 5253 } 5254 5255 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5256 if (rc < 0) { 5257 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5258 return rc; 5259 } 5260 5261 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5262 5263 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5264 5265 /* Identify chip attached to board */ 5266 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5267 if (chipset == RTL_GIGA_MAC_NONE) { 5268 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5269 return -ENODEV; 5270 } 5271 5272 tp->mac_version = chipset; 5273 5274 /* Disable ASPM L1 as that cause random device stop working 5275 * problems as well as full system hangs for some PCIe devices users. 5276 * Chips from RTL8168h partially have issues with L1.2, but seem 5277 * to work fine with L1 and L1.1. 5278 */ 5279 if (rtl_aspm_is_safe(tp)) 5280 rc = 0; 5281 else if (tp->mac_version >= RTL_GIGA_MAC_VER_46) 5282 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2); 5283 else 5284 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5285 tp->aspm_manageable = !rc; 5286 5287 tp->dash_type = rtl_check_dash(tp); 5288 5289 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5290 5291 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5292 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5293 dev->features |= NETIF_F_HIGHDMA; 5294 5295 rtl_init_rxcfg(tp); 5296 5297 rtl8169_irq_mask_and_ack(tp); 5298 5299 rtl_hw_initialize(tp); 5300 5301 rtl_hw_reset(tp); 5302 5303 rc = rtl_alloc_irq(tp); 5304 if (rc < 0) { 5305 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5306 return rc; 5307 } 5308 tp->irq = pci_irq_vector(pdev, 0); 5309 5310 INIT_WORK(&tp->wk.work, rtl_task); 5311 5312 rtl_init_mac_address(tp); 5313 5314 dev->ethtool_ops = &rtl8169_ethtool_ops; 5315 5316 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5317 5318 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5319 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5320 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5321 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5322 5323 /* 5324 * Pretend we are using VLANs; This bypasses a nasty bug where 5325 * Interrupts stop flowing on high load on 8110SCd controllers. 5326 */ 5327 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5328 /* Disallow toggling */ 5329 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5330 5331 if (rtl_chip_supports_csum_v2(tp)) 5332 dev->hw_features |= NETIF_F_IPV6_CSUM; 5333 5334 dev->features |= dev->hw_features; 5335 5336 /* There has been a number of reports that using SG/TSO results in 5337 * tx timeouts. However for a lot of people SG/TSO works fine. 5338 * Therefore disable both features by default, but allow users to 5339 * enable them. Use at own risk! 5340 */ 5341 if (rtl_chip_supports_csum_v2(tp)) { 5342 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5343 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5344 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5345 } else { 5346 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5347 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5348 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5349 } 5350 5351 dev->hw_features |= NETIF_F_RXALL; 5352 dev->hw_features |= NETIF_F_RXFCS; 5353 5354 /* configure chip for default features */ 5355 rtl8169_set_features(dev, dev->features); 5356 5357 if (tp->dash_type == RTL_DASH_NONE) { 5358 rtl_set_d3_pll_down(tp, true); 5359 } else { 5360 rtl_set_d3_pll_down(tp, false); 5361 dev->wol_enabled = 1; 5362 } 5363 5364 jumbo_max = rtl_jumbo_max(tp); 5365 if (jumbo_max) 5366 dev->max_mtu = jumbo_max; 5367 5368 rtl_set_irq_mask(tp); 5369 5370 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5371 5372 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5373 &tp->counters_phys_addr, 5374 GFP_KERNEL); 5375 if (!tp->counters) 5376 return -ENOMEM; 5377 5378 pci_set_drvdata(pdev, tp); 5379 5380 rc = r8169_mdio_register(tp); 5381 if (rc) 5382 return rc; 5383 5384 rc = register_netdev(dev); 5385 if (rc) 5386 return rc; 5387 5388 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5389 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5390 5391 if (jumbo_max) 5392 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5393 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5394 "ok" : "ko"); 5395 5396 if (tp->dash_type != RTL_DASH_NONE) { 5397 netdev_info(dev, "DASH enabled\n"); 5398 rtl8168_driver_start(tp); 5399 } 5400 5401 if (pci_dev_run_wake(pdev)) 5402 pm_runtime_put_sync(&pdev->dev); 5403 5404 return 0; 5405 } 5406 5407 static struct pci_driver rtl8169_pci_driver = { 5408 .name = KBUILD_MODNAME, 5409 .id_table = rtl8169_pci_tbl, 5410 .probe = rtl_init_one, 5411 .remove = rtl_remove_one, 5412 .shutdown = rtl_shutdown, 5413 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5414 }; 5415 5416 module_pci_driver(rtl8169_pci_driver); 5417