1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 61 #define MC_FILTER_LIMIT 32 62 63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 65 66 #define R8169_REGS_SIZE 256 67 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 68 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 69 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 72 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 73 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 74 75 #define OCP_STD_PHY_BASE 0xa400 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92 static const struct { 93 const char *name; 94 const char *fw_name; 95 } rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 143 }; 144 145 static const struct pci_device_id rtl8169_pci_tbl[] = { 146 { PCI_VDEVICE(REALTEK, 0x2502) }, 147 { PCI_VDEVICE(REALTEK, 0x2600) }, 148 { PCI_VDEVICE(REALTEK, 0x8129) }, 149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 150 { PCI_VDEVICE(REALTEK, 0x8161) }, 151 { PCI_VDEVICE(REALTEK, 0x8162) }, 152 { PCI_VDEVICE(REALTEK, 0x8167) }, 153 { PCI_VDEVICE(REALTEK, 0x8168) }, 154 { PCI_VDEVICE(NCUBE, 0x8168) }, 155 { PCI_VDEVICE(REALTEK, 0x8169) }, 156 { PCI_VENDOR_ID_DLINK, 0x4300, 157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 158 { PCI_VDEVICE(DLINK, 0x4300) }, 159 { PCI_VDEVICE(DLINK, 0x4302) }, 160 { PCI_VDEVICE(AT, 0xc107) }, 161 { PCI_VDEVICE(USR, 0x0116) }, 162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 164 { PCI_VDEVICE(REALTEK, 0x8125) }, 165 { PCI_VDEVICE(REALTEK, 0x3000) }, 166 {} 167 }; 168 169 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 170 171 enum rtl_registers { 172 MAC0 = 0, /* Ethernet hardware address. */ 173 MAC4 = 4, 174 MAR0 = 8, /* Multicast filter. */ 175 CounterAddrLow = 0x10, 176 CounterAddrHigh = 0x14, 177 TxDescStartAddrLow = 0x20, 178 TxDescStartAddrHigh = 0x24, 179 TxHDescStartAddrLow = 0x28, 180 TxHDescStartAddrHigh = 0x2c, 181 FLASH = 0x30, 182 ERSR = 0x36, 183 ChipCmd = 0x37, 184 TxPoll = 0x38, 185 IntrMask = 0x3c, 186 IntrStatus = 0x3e, 187 188 TxConfig = 0x40, 189 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 190 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 191 192 RxConfig = 0x44, 193 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 194 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 195 #define RXCFG_FIFO_SHIFT 13 196 /* No threshold before first PCI xfer */ 197 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 198 #define RX_EARLY_OFF (1 << 11) 199 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 200 #define RXCFG_DMA_SHIFT 8 201 /* Unlimited maximum PCI burst. */ 202 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 203 204 Cfg9346 = 0x50, 205 Config0 = 0x51, 206 Config1 = 0x52, 207 Config2 = 0x53, 208 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 209 210 Config3 = 0x54, 211 Config4 = 0x55, 212 Config5 = 0x56, 213 PHYAR = 0x60, 214 PHYstatus = 0x6c, 215 RxMaxSize = 0xda, 216 CPlusCmd = 0xe0, 217 IntrMitigate = 0xe2, 218 219 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 220 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 221 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 222 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 223 224 #define RTL_COALESCE_T_MAX 0x0fU 225 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 226 227 RxDescAddrLow = 0xe4, 228 RxDescAddrHigh = 0xe8, 229 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 230 231 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 232 233 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 234 235 #define TxPacketMax (8064 >> 7) 236 #define EarlySize 0x27 237 238 FuncEvent = 0xf0, 239 FuncEventMask = 0xf4, 240 FuncPresetState = 0xf8, 241 IBCR0 = 0xf8, 242 IBCR2 = 0xf9, 243 IBIMR0 = 0xfa, 244 IBISR0 = 0xfb, 245 FuncForceEvent = 0xfc, 246 }; 247 248 enum rtl8168_8101_registers { 249 CSIDR = 0x64, 250 CSIAR = 0x68, 251 #define CSIAR_FLAG 0x80000000 252 #define CSIAR_WRITE_CMD 0x80000000 253 #define CSIAR_BYTE_ENABLE 0x0000f000 254 #define CSIAR_ADDR_MASK 0x00000fff 255 PMCH = 0x6f, 256 #define D3COLD_NO_PLL_DOWN BIT(7) 257 #define D3HOT_NO_PLL_DOWN BIT(6) 258 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 259 EPHYAR = 0x80, 260 #define EPHYAR_FLAG 0x80000000 261 #define EPHYAR_WRITE_CMD 0x80000000 262 #define EPHYAR_REG_MASK 0x1f 263 #define EPHYAR_REG_SHIFT 16 264 #define EPHYAR_DATA_MASK 0xffff 265 DLLPR = 0xd0, 266 #define PFM_EN (1 << 6) 267 #define TX_10M_PS_EN (1 << 7) 268 DBG_REG = 0xd1, 269 #define FIX_NAK_1 (1 << 4) 270 #define FIX_NAK_2 (1 << 3) 271 TWSI = 0xd2, 272 MCU = 0xd3, 273 #define NOW_IS_OOB (1 << 7) 274 #define TX_EMPTY (1 << 5) 275 #define RX_EMPTY (1 << 4) 276 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 277 #define EN_NDP (1 << 3) 278 #define EN_OOB_RESET (1 << 2) 279 #define LINK_LIST_RDY (1 << 1) 280 EFUSEAR = 0xdc, 281 #define EFUSEAR_FLAG 0x80000000 282 #define EFUSEAR_WRITE_CMD 0x80000000 283 #define EFUSEAR_READ_CMD 0x00000000 284 #define EFUSEAR_REG_MASK 0x03ff 285 #define EFUSEAR_REG_SHIFT 8 286 #define EFUSEAR_DATA_MASK 0xff 287 MISC_1 = 0xf2, 288 #define PFM_D3COLD_EN (1 << 6) 289 }; 290 291 enum rtl8168_registers { 292 LED_FREQ = 0x1a, 293 EEE_LED = 0x1b, 294 ERIDR = 0x70, 295 ERIAR = 0x74, 296 #define ERIAR_FLAG 0x80000000 297 #define ERIAR_WRITE_CMD 0x80000000 298 #define ERIAR_READ_CMD 0x00000000 299 #define ERIAR_ADDR_BYTE_ALIGN 4 300 #define ERIAR_TYPE_SHIFT 16 301 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_MASK_SHIFT 12 306 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 311 EPHY_RXER_NUM = 0x7c, 312 OCPDR = 0xb0, /* OCP GPHY access */ 313 #define OCPDR_WRITE_CMD 0x80000000 314 #define OCPDR_READ_CMD 0x00000000 315 #define OCPDR_REG_MASK 0x7f 316 #define OCPDR_GPHY_REG_SHIFT 16 317 #define OCPDR_DATA_MASK 0xffff 318 OCPAR = 0xb4, 319 #define OCPAR_FLAG 0x80000000 320 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 321 #define OCPAR_GPHY_READ_CMD 0x0000f060 322 GPHY_OCP = 0xb8, 323 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 324 MISC = 0xf0, /* 8168e only. */ 325 #define TXPLA_RST (1 << 29) 326 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 327 #define PWM_EN (1 << 22) 328 #define RXDV_GATED_EN (1 << 19) 329 #define EARLY_TALLY_EN (1 << 16) 330 }; 331 332 enum rtl8125_registers { 333 IntrMask_8125 = 0x38, 334 IntrStatus_8125 = 0x3c, 335 TxPoll_8125 = 0x90, 336 MAC0_BKP = 0x19e0, 337 EEE_TXIDLE_TIMER_8125 = 0x6048, 338 }; 339 340 #define RX_VLAN_INNER_8125 BIT(22) 341 #define RX_VLAN_OUTER_8125 BIT(23) 342 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 343 344 #define RX_FETCH_DFLT_8125 (8 << 27) 345 346 enum rtl_register_content { 347 /* InterruptStatusBits */ 348 SYSErr = 0x8000, 349 PCSTimeout = 0x4000, 350 SWInt = 0x0100, 351 TxDescUnavail = 0x0080, 352 RxFIFOOver = 0x0040, 353 LinkChg = 0x0020, 354 RxOverflow = 0x0010, 355 TxErr = 0x0008, 356 TxOK = 0x0004, 357 RxErr = 0x0002, 358 RxOK = 0x0001, 359 360 /* RxStatusDesc */ 361 RxRWT = (1 << 22), 362 RxRES = (1 << 21), 363 RxRUNT = (1 << 20), 364 RxCRC = (1 << 19), 365 366 /* ChipCmdBits */ 367 StopReq = 0x80, 368 CmdReset = 0x10, 369 CmdRxEnb = 0x08, 370 CmdTxEnb = 0x04, 371 RxBufEmpty = 0x01, 372 373 /* TXPoll register p.5 */ 374 HPQ = 0x80, /* Poll cmd on the high prio queue */ 375 NPQ = 0x40, /* Poll cmd on the low prio queue */ 376 FSWInt = 0x01, /* Forced software interrupt */ 377 378 /* Cfg9346Bits */ 379 Cfg9346_Lock = 0x00, 380 Cfg9346_Unlock = 0xc0, 381 382 /* rx_mode_bits */ 383 AcceptErr = 0x20, 384 AcceptRunt = 0x10, 385 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 386 AcceptBroadcast = 0x08, 387 AcceptMulticast = 0x04, 388 AcceptMyPhys = 0x02, 389 AcceptAllPhys = 0x01, 390 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 391 #define RX_CONFIG_ACCEPT_MASK 0x3f 392 393 /* TxConfigBits */ 394 TxInterFrameGapShift = 24, 395 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 396 397 /* Config1 register p.24 */ 398 LEDS1 = (1 << 7), 399 LEDS0 = (1 << 6), 400 Speed_down = (1 << 4), 401 MEMMAP = (1 << 3), 402 IOMAP = (1 << 2), 403 VPD = (1 << 1), 404 PMEnable = (1 << 0), /* Power Management Enable */ 405 406 /* Config2 register p. 25 */ 407 ClkReqEn = (1 << 7), /* Clock Request Enable */ 408 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 409 PCI_Clock_66MHz = 0x01, 410 PCI_Clock_33MHz = 0x00, 411 412 /* Config3 register p.25 */ 413 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 414 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 415 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 416 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 417 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 418 419 /* Config4 register */ 420 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 421 422 /* Config5 register p.27 */ 423 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 424 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 425 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 426 Spi_en = (1 << 3), 427 LanWake = (1 << 1), /* LanWake enable/disable */ 428 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 429 ASPM_en = (1 << 0), /* ASPM enable */ 430 431 /* CPlusCmd p.31 */ 432 EnableBist = (1 << 15), // 8168 8101 433 Mac_dbgo_oe = (1 << 14), // 8168 8101 434 EnAnaPLL = (1 << 14), // 8169 435 Normal_mode = (1 << 13), // unused 436 Force_half_dup = (1 << 12), // 8168 8101 437 Force_rxflow_en = (1 << 11), // 8168 8101 438 Force_txflow_en = (1 << 10), // 8168 8101 439 Cxpl_dbg_sel = (1 << 9), // 8168 8101 440 ASF = (1 << 8), // 8168 8101 441 PktCntrDisable = (1 << 7), // 8168 8101 442 Mac_dbgo_sel = 0x001c, // 8168 443 RxVlan = (1 << 6), 444 RxChkSum = (1 << 5), 445 PCIDAC = (1 << 4), 446 PCIMulRW = (1 << 3), 447 #define INTT_MASK GENMASK(1, 0) 448 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 449 450 /* rtl8169_PHYstatus */ 451 TBI_Enable = 0x80, 452 TxFlowCtrl = 0x40, 453 RxFlowCtrl = 0x20, 454 _1000bpsF = 0x10, 455 _100bps = 0x08, 456 _10bps = 0x04, 457 LinkStatus = 0x02, 458 FullDup = 0x01, 459 460 /* ResetCounterCommand */ 461 CounterReset = 0x1, 462 463 /* DumpCounterCommand */ 464 CounterDump = 0x8, 465 466 /* magic enable v2 */ 467 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 468 }; 469 470 enum rtl_desc_bit { 471 /* First doubleword. */ 472 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 473 RingEnd = (1 << 30), /* End of descriptor ring */ 474 FirstFrag = (1 << 29), /* First segment of a packet */ 475 LastFrag = (1 << 28), /* Final segment of a packet */ 476 }; 477 478 /* Generic case. */ 479 enum rtl_tx_desc_bit { 480 /* First doubleword. */ 481 TD_LSO = (1 << 27), /* Large Send Offload */ 482 #define TD_MSS_MAX 0x07ffu /* MSS value */ 483 484 /* Second doubleword. */ 485 TxVlanTag = (1 << 17), /* Add VLAN tag */ 486 }; 487 488 /* 8169, 8168b and 810x except 8102e. */ 489 enum rtl_tx_desc_bit_0 { 490 /* First doubleword. */ 491 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 492 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 493 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 494 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 495 }; 496 497 /* 8102e, 8168c and beyond. */ 498 enum rtl_tx_desc_bit_1 { 499 /* First doubleword. */ 500 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 501 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 502 #define GTTCPHO_SHIFT 18 503 #define GTTCPHO_MAX 0x7f 504 505 /* Second doubleword. */ 506 #define TCPHO_SHIFT 18 507 #define TCPHO_MAX 0x3ff 508 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 509 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 510 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 511 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 512 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 513 }; 514 515 enum rtl_rx_desc_bit { 516 /* Rx private */ 517 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 518 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 519 520 #define RxProtoUDP (PID1) 521 #define RxProtoTCP (PID0) 522 #define RxProtoIP (PID1 | PID0) 523 #define RxProtoMask RxProtoIP 524 525 IPFail = (1 << 16), /* IP checksum failed */ 526 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 527 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 528 529 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 530 531 RxVlanTag = (1 << 16), /* VLAN tag available */ 532 }; 533 534 #define RTL_GSO_MAX_SIZE_V1 32000 535 #define RTL_GSO_MAX_SEGS_V1 24 536 #define RTL_GSO_MAX_SIZE_V2 64000 537 #define RTL_GSO_MAX_SEGS_V2 64 538 539 struct TxDesc { 540 __le32 opts1; 541 __le32 opts2; 542 __le64 addr; 543 }; 544 545 struct RxDesc { 546 __le32 opts1; 547 __le32 opts2; 548 __le64 addr; 549 }; 550 551 struct ring_info { 552 struct sk_buff *skb; 553 u32 len; 554 }; 555 556 struct rtl8169_counters { 557 __le64 tx_packets; 558 __le64 rx_packets; 559 __le64 tx_errors; 560 __le32 rx_errors; 561 __le16 rx_missed; 562 __le16 align_errors; 563 __le32 tx_one_collision; 564 __le32 tx_multi_collision; 565 __le64 rx_unicast; 566 __le64 rx_broadcast; 567 __le32 rx_multicast; 568 __le16 tx_aborted; 569 __le16 tx_underun; 570 }; 571 572 struct rtl8169_tc_offsets { 573 bool inited; 574 __le64 tx_errors; 575 __le32 tx_multi_collision; 576 __le16 tx_aborted; 577 __le16 rx_missed; 578 }; 579 580 enum rtl_flag { 581 RTL_FLAG_TASK_ENABLED = 0, 582 RTL_FLAG_TASK_RESET_PENDING, 583 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 584 RTL_FLAG_TASK_TX_TIMEOUT, 585 RTL_FLAG_MAX 586 }; 587 588 enum rtl_dash_type { 589 RTL_DASH_NONE, 590 RTL_DASH_DP, 591 RTL_DASH_EP, 592 }; 593 594 struct rtl8169_private { 595 void __iomem *mmio_addr; /* memory map physical address */ 596 struct pci_dev *pci_dev; 597 struct net_device *dev; 598 struct phy_device *phydev; 599 struct napi_struct napi; 600 enum mac_version mac_version; 601 enum rtl_dash_type dash_type; 602 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 603 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 604 u32 dirty_tx; 605 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 606 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 607 dma_addr_t TxPhyAddr; 608 dma_addr_t RxPhyAddr; 609 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 610 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 611 u16 cp_cmd; 612 u32 irq_mask; 613 int irq; 614 struct clk *clk; 615 616 struct { 617 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 618 struct work_struct work; 619 } wk; 620 621 raw_spinlock_t config25_lock; 622 raw_spinlock_t mac_ocp_lock; 623 624 raw_spinlock_t cfg9346_usage_lock; 625 int cfg9346_usage_count; 626 627 unsigned supports_gmii:1; 628 unsigned aspm_manageable:1; 629 unsigned dash_enabled:1; 630 dma_addr_t counters_phys_addr; 631 struct rtl8169_counters *counters; 632 struct rtl8169_tc_offsets tc_offset; 633 u32 saved_wolopts; 634 int eee_adv; 635 636 const char *fw_name; 637 struct rtl_fw *rtl_fw; 638 639 u32 ocp_base; 640 }; 641 642 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 643 644 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 645 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 646 MODULE_SOFTDEP("pre: realtek"); 647 MODULE_LICENSE("GPL"); 648 MODULE_FIRMWARE(FIRMWARE_8168D_1); 649 MODULE_FIRMWARE(FIRMWARE_8168D_2); 650 MODULE_FIRMWARE(FIRMWARE_8168E_1); 651 MODULE_FIRMWARE(FIRMWARE_8168E_2); 652 MODULE_FIRMWARE(FIRMWARE_8168E_3); 653 MODULE_FIRMWARE(FIRMWARE_8105E_1); 654 MODULE_FIRMWARE(FIRMWARE_8168F_1); 655 MODULE_FIRMWARE(FIRMWARE_8168F_2); 656 MODULE_FIRMWARE(FIRMWARE_8402_1); 657 MODULE_FIRMWARE(FIRMWARE_8411_1); 658 MODULE_FIRMWARE(FIRMWARE_8411_2); 659 MODULE_FIRMWARE(FIRMWARE_8106E_1); 660 MODULE_FIRMWARE(FIRMWARE_8106E_2); 661 MODULE_FIRMWARE(FIRMWARE_8168G_2); 662 MODULE_FIRMWARE(FIRMWARE_8168G_3); 663 MODULE_FIRMWARE(FIRMWARE_8168H_2); 664 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 665 MODULE_FIRMWARE(FIRMWARE_8107E_2); 666 MODULE_FIRMWARE(FIRMWARE_8125A_3); 667 MODULE_FIRMWARE(FIRMWARE_8125B_2); 668 669 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 670 { 671 return &tp->pci_dev->dev; 672 } 673 674 static void rtl_lock_config_regs(struct rtl8169_private *tp) 675 { 676 unsigned long flags; 677 678 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 679 if (!--tp->cfg9346_usage_count) 680 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 681 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 682 } 683 684 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 685 { 686 unsigned long flags; 687 688 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 689 if (!tp->cfg9346_usage_count++) 690 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 691 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 692 } 693 694 static void rtl_pci_commit(struct rtl8169_private *tp) 695 { 696 /* Read an arbitrary register to commit a preceding PCI write */ 697 RTL_R8(tp, ChipCmd); 698 } 699 700 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 701 { 702 unsigned long flags; 703 u8 val; 704 705 raw_spin_lock_irqsave(&tp->config25_lock, flags); 706 val = RTL_R8(tp, Config2); 707 RTL_W8(tp, Config2, (val & ~clear) | set); 708 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 709 } 710 711 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 712 { 713 unsigned long flags; 714 u8 val; 715 716 raw_spin_lock_irqsave(&tp->config25_lock, flags); 717 val = RTL_R8(tp, Config5); 718 RTL_W8(tp, Config5, (val & ~clear) | set); 719 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 720 } 721 722 static bool rtl_is_8125(struct rtl8169_private *tp) 723 { 724 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 725 } 726 727 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 728 { 729 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 730 tp->mac_version != RTL_GIGA_MAC_VER_39 && 731 tp->mac_version <= RTL_GIGA_MAC_VER_53; 732 } 733 734 static bool rtl_supports_eee(struct rtl8169_private *tp) 735 { 736 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 737 tp->mac_version != RTL_GIGA_MAC_VER_37 && 738 tp->mac_version != RTL_GIGA_MAC_VER_39; 739 } 740 741 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 742 { 743 int i; 744 745 for (i = 0; i < ETH_ALEN; i++) 746 mac[i] = RTL_R8(tp, reg + i); 747 } 748 749 struct rtl_cond { 750 bool (*check)(struct rtl8169_private *); 751 const char *msg; 752 }; 753 754 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 755 unsigned long usecs, int n, bool high) 756 { 757 int i; 758 759 for (i = 0; i < n; i++) { 760 if (c->check(tp) == high) 761 return true; 762 fsleep(usecs); 763 } 764 765 if (net_ratelimit()) 766 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 767 c->msg, !high, n, usecs); 768 return false; 769 } 770 771 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 772 const struct rtl_cond *c, 773 unsigned long d, int n) 774 { 775 return rtl_loop_wait(tp, c, d, n, true); 776 } 777 778 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 779 const struct rtl_cond *c, 780 unsigned long d, int n) 781 { 782 return rtl_loop_wait(tp, c, d, n, false); 783 } 784 785 #define DECLARE_RTL_COND(name) \ 786 static bool name ## _check(struct rtl8169_private *); \ 787 \ 788 static const struct rtl_cond name = { \ 789 .check = name ## _check, \ 790 .msg = #name \ 791 }; \ 792 \ 793 static bool name ## _check(struct rtl8169_private *tp) 794 795 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 796 { 797 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 798 if (type == ERIAR_OOB && 799 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 800 tp->mac_version == RTL_GIGA_MAC_VER_53)) 801 *cmd |= 0xf70 << 18; 802 } 803 804 DECLARE_RTL_COND(rtl_eriar_cond) 805 { 806 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 807 } 808 809 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 810 u32 val, int type) 811 { 812 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 813 814 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 815 return; 816 817 RTL_W32(tp, ERIDR, val); 818 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 819 RTL_W32(tp, ERIAR, cmd); 820 821 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 822 } 823 824 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 825 u32 val) 826 { 827 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 828 } 829 830 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 831 { 832 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 833 834 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 835 RTL_W32(tp, ERIAR, cmd); 836 837 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 838 RTL_R32(tp, ERIDR) : ~0; 839 } 840 841 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 842 { 843 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 844 } 845 846 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 847 { 848 u32 val = rtl_eri_read(tp, addr); 849 850 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 851 } 852 853 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 854 { 855 rtl_w0w1_eri(tp, addr, p, 0); 856 } 857 858 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 859 { 860 rtl_w0w1_eri(tp, addr, 0, m); 861 } 862 863 static bool rtl_ocp_reg_failure(u32 reg) 864 { 865 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 866 } 867 868 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 869 { 870 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 871 } 872 873 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 874 { 875 if (rtl_ocp_reg_failure(reg)) 876 return; 877 878 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 879 880 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 881 } 882 883 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 884 { 885 if (rtl_ocp_reg_failure(reg)) 886 return 0; 887 888 RTL_W32(tp, GPHY_OCP, reg << 15); 889 890 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 891 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 892 } 893 894 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 895 { 896 if (rtl_ocp_reg_failure(reg)) 897 return; 898 899 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 900 } 901 902 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 903 { 904 unsigned long flags; 905 906 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 907 __r8168_mac_ocp_write(tp, reg, data); 908 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 909 } 910 911 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 912 { 913 if (rtl_ocp_reg_failure(reg)) 914 return 0; 915 916 RTL_W32(tp, OCPDR, reg << 15); 917 918 return RTL_R32(tp, OCPDR); 919 } 920 921 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 922 { 923 unsigned long flags; 924 u16 val; 925 926 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 927 val = __r8168_mac_ocp_read(tp, reg); 928 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 929 930 return val; 931 } 932 933 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 934 u16 set) 935 { 936 unsigned long flags; 937 u16 data; 938 939 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 940 data = __r8168_mac_ocp_read(tp, reg); 941 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 942 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 943 } 944 945 /* Work around a hw issue with RTL8168g PHY, the quirk disables 946 * PHY MCU interrupts before PHY power-down. 947 */ 948 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 949 { 950 switch (tp->mac_version) { 951 case RTL_GIGA_MAC_VER_40: 952 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 953 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 954 else 955 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 956 break; 957 default: 958 break; 959 } 960 }; 961 962 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 963 { 964 if (reg == 0x1f) { 965 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 966 return; 967 } 968 969 if (tp->ocp_base != OCP_STD_PHY_BASE) 970 reg -= 0x10; 971 972 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 973 rtl8168g_phy_suspend_quirk(tp, value); 974 975 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 976 } 977 978 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 979 { 980 if (reg == 0x1f) 981 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 982 983 if (tp->ocp_base != OCP_STD_PHY_BASE) 984 reg -= 0x10; 985 986 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 987 } 988 989 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 990 { 991 if (reg == 0x1f) { 992 tp->ocp_base = value << 4; 993 return; 994 } 995 996 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 997 } 998 999 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1000 { 1001 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1002 } 1003 1004 DECLARE_RTL_COND(rtl_phyar_cond) 1005 { 1006 return RTL_R32(tp, PHYAR) & 0x80000000; 1007 } 1008 1009 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1010 { 1011 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1012 1013 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1014 /* 1015 * According to hardware specs a 20us delay is required after write 1016 * complete indication, but before sending next command. 1017 */ 1018 udelay(20); 1019 } 1020 1021 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1022 { 1023 int value; 1024 1025 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1026 1027 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1028 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1029 1030 /* 1031 * According to hardware specs a 20us delay is required after read 1032 * complete indication, but before sending next command. 1033 */ 1034 udelay(20); 1035 1036 return value; 1037 } 1038 1039 DECLARE_RTL_COND(rtl_ocpar_cond) 1040 { 1041 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1042 } 1043 1044 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1045 1046 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1047 { 1048 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1049 } 1050 1051 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1052 { 1053 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1054 } 1055 1056 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1057 { 1058 r8168dp_2_mdio_start(tp); 1059 1060 r8169_mdio_write(tp, reg, value); 1061 1062 r8168dp_2_mdio_stop(tp); 1063 } 1064 1065 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1066 { 1067 int value; 1068 1069 /* Work around issue with chip reporting wrong PHY ID */ 1070 if (reg == MII_PHYSID2) 1071 return 0xc912; 1072 1073 r8168dp_2_mdio_start(tp); 1074 1075 value = r8169_mdio_read(tp, reg); 1076 1077 r8168dp_2_mdio_stop(tp); 1078 1079 return value; 1080 } 1081 1082 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1083 { 1084 switch (tp->mac_version) { 1085 case RTL_GIGA_MAC_VER_28: 1086 case RTL_GIGA_MAC_VER_31: 1087 r8168dp_2_mdio_write(tp, location, val); 1088 break; 1089 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1090 r8168g_mdio_write(tp, location, val); 1091 break; 1092 default: 1093 r8169_mdio_write(tp, location, val); 1094 break; 1095 } 1096 } 1097 1098 static int rtl_readphy(struct rtl8169_private *tp, int location) 1099 { 1100 switch (tp->mac_version) { 1101 case RTL_GIGA_MAC_VER_28: 1102 case RTL_GIGA_MAC_VER_31: 1103 return r8168dp_2_mdio_read(tp, location); 1104 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1105 return r8168g_mdio_read(tp, location); 1106 default: 1107 return r8169_mdio_read(tp, location); 1108 } 1109 } 1110 1111 DECLARE_RTL_COND(rtl_ephyar_cond) 1112 { 1113 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1114 } 1115 1116 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1117 { 1118 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1119 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1120 1121 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1122 1123 udelay(10); 1124 } 1125 1126 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1127 { 1128 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1129 1130 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1131 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1132 } 1133 1134 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1135 { 1136 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1137 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1138 RTL_R32(tp, OCPDR) : ~0; 1139 } 1140 1141 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1142 { 1143 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1144 } 1145 1146 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1147 u32 data) 1148 { 1149 RTL_W32(tp, OCPDR, data); 1150 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1151 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1152 } 1153 1154 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1155 u32 data) 1156 { 1157 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1158 data, ERIAR_OOB); 1159 } 1160 1161 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1162 { 1163 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1164 1165 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1166 } 1167 1168 #define OOB_CMD_RESET 0x00 1169 #define OOB_CMD_DRIVER_START 0x05 1170 #define OOB_CMD_DRIVER_STOP 0x06 1171 1172 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1173 { 1174 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1175 } 1176 1177 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1178 { 1179 u16 reg; 1180 1181 reg = rtl8168_get_ocp_reg(tp); 1182 1183 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1184 } 1185 1186 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1187 { 1188 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1189 } 1190 1191 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1192 { 1193 return RTL_R8(tp, IBISR0) & 0x20; 1194 } 1195 1196 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1197 { 1198 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1199 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1200 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1201 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1202 } 1203 1204 static void rtl_dash_loop_wait(struct rtl8169_private *tp, 1205 const struct rtl_cond *c, 1206 unsigned long usecs, int n, bool high) 1207 { 1208 if (!tp->dash_enabled) 1209 return; 1210 rtl_loop_wait(tp, c, usecs, n, high); 1211 } 1212 1213 static void rtl_dash_loop_wait_high(struct rtl8169_private *tp, 1214 const struct rtl_cond *c, 1215 unsigned long d, int n) 1216 { 1217 rtl_dash_loop_wait(tp, c, d, n, true); 1218 } 1219 1220 static void rtl_dash_loop_wait_low(struct rtl8169_private *tp, 1221 const struct rtl_cond *c, 1222 unsigned long d, int n) 1223 { 1224 rtl_dash_loop_wait(tp, c, d, n, false); 1225 } 1226 1227 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1228 { 1229 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1230 rtl_dash_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1231 } 1232 1233 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1234 { 1235 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1236 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1237 rtl_dash_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1238 } 1239 1240 static void rtl8168_driver_start(struct rtl8169_private *tp) 1241 { 1242 if (tp->dash_type == RTL_DASH_DP) 1243 rtl8168dp_driver_start(tp); 1244 else 1245 rtl8168ep_driver_start(tp); 1246 } 1247 1248 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1249 { 1250 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1251 rtl_dash_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1252 } 1253 1254 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1255 { 1256 rtl8168ep_stop_cmac(tp); 1257 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1258 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1259 rtl_dash_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1260 } 1261 1262 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1263 { 1264 if (tp->dash_type == RTL_DASH_DP) 1265 rtl8168dp_driver_stop(tp); 1266 else 1267 rtl8168ep_driver_stop(tp); 1268 } 1269 1270 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1271 { 1272 u16 reg = rtl8168_get_ocp_reg(tp); 1273 1274 return r8168dp_ocp_read(tp, reg) & BIT(15); 1275 } 1276 1277 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1278 { 1279 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1280 } 1281 1282 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1283 { 1284 switch (tp->dash_type) { 1285 case RTL_DASH_DP: 1286 return r8168dp_check_dash(tp); 1287 case RTL_DASH_EP: 1288 return r8168ep_check_dash(tp); 1289 default: 1290 return false; 1291 } 1292 } 1293 1294 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1295 { 1296 switch (tp->mac_version) { 1297 case RTL_GIGA_MAC_VER_28: 1298 case RTL_GIGA_MAC_VER_31: 1299 return RTL_DASH_DP; 1300 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1301 return RTL_DASH_EP; 1302 default: 1303 return RTL_DASH_NONE; 1304 } 1305 } 1306 1307 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1308 { 1309 switch (tp->mac_version) { 1310 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1311 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1312 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1313 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1314 if (enable) 1315 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1316 else 1317 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1318 break; 1319 default: 1320 break; 1321 } 1322 } 1323 1324 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1325 { 1326 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1327 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1328 } 1329 1330 DECLARE_RTL_COND(rtl_efusear_cond) 1331 { 1332 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1333 } 1334 1335 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1336 { 1337 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1338 1339 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1340 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1341 } 1342 1343 static u32 rtl_get_events(struct rtl8169_private *tp) 1344 { 1345 if (rtl_is_8125(tp)) 1346 return RTL_R32(tp, IntrStatus_8125); 1347 else 1348 return RTL_R16(tp, IntrStatus); 1349 } 1350 1351 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1352 { 1353 if (rtl_is_8125(tp)) 1354 RTL_W32(tp, IntrStatus_8125, bits); 1355 else 1356 RTL_W16(tp, IntrStatus, bits); 1357 } 1358 1359 static void rtl_irq_disable(struct rtl8169_private *tp) 1360 { 1361 if (rtl_is_8125(tp)) 1362 RTL_W32(tp, IntrMask_8125, 0); 1363 else 1364 RTL_W16(tp, IntrMask, 0); 1365 } 1366 1367 static void rtl_irq_enable(struct rtl8169_private *tp) 1368 { 1369 if (rtl_is_8125(tp)) 1370 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1371 else 1372 RTL_W16(tp, IntrMask, tp->irq_mask); 1373 } 1374 1375 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1376 { 1377 rtl_irq_disable(tp); 1378 rtl_ack_events(tp, 0xffffffff); 1379 rtl_pci_commit(tp); 1380 } 1381 1382 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1383 { 1384 struct phy_device *phydev = tp->phydev; 1385 1386 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1387 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1388 if (phydev->speed == SPEED_1000) { 1389 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1390 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1391 } else if (phydev->speed == SPEED_100) { 1392 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1393 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1394 } else { 1395 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1396 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1397 } 1398 rtl_reset_packet_filter(tp); 1399 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1400 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1401 if (phydev->speed == SPEED_1000) { 1402 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1403 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1404 } else { 1405 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1406 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1407 } 1408 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1409 if (phydev->speed == SPEED_10) { 1410 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1411 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1412 } else { 1413 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1414 } 1415 } 1416 } 1417 1418 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1419 1420 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1421 { 1422 struct rtl8169_private *tp = netdev_priv(dev); 1423 1424 wol->supported = WAKE_ANY; 1425 wol->wolopts = tp->saved_wolopts; 1426 } 1427 1428 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1429 { 1430 static const struct { 1431 u32 opt; 1432 u16 reg; 1433 u8 mask; 1434 } cfg[] = { 1435 { WAKE_PHY, Config3, LinkUp }, 1436 { WAKE_UCAST, Config5, UWF }, 1437 { WAKE_BCAST, Config5, BWF }, 1438 { WAKE_MCAST, Config5, MWF }, 1439 { WAKE_ANY, Config5, LanWake }, 1440 { WAKE_MAGIC, Config3, MagicPacket } 1441 }; 1442 unsigned int i, tmp = ARRAY_SIZE(cfg); 1443 unsigned long flags; 1444 u8 options; 1445 1446 rtl_unlock_config_regs(tp); 1447 1448 if (rtl_is_8168evl_up(tp)) { 1449 tmp--; 1450 if (wolopts & WAKE_MAGIC) 1451 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1452 else 1453 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1454 } else if (rtl_is_8125(tp)) { 1455 tmp--; 1456 if (wolopts & WAKE_MAGIC) 1457 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1458 else 1459 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1460 } 1461 1462 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1463 for (i = 0; i < tmp; i++) { 1464 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1465 if (wolopts & cfg[i].opt) 1466 options |= cfg[i].mask; 1467 RTL_W8(tp, cfg[i].reg, options); 1468 } 1469 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1470 1471 switch (tp->mac_version) { 1472 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1473 options = RTL_R8(tp, Config1) & ~PMEnable; 1474 if (wolopts) 1475 options |= PMEnable; 1476 RTL_W8(tp, Config1, options); 1477 break; 1478 case RTL_GIGA_MAC_VER_34: 1479 case RTL_GIGA_MAC_VER_37: 1480 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1481 if (wolopts) 1482 rtl_mod_config2(tp, 0, PME_SIGNAL); 1483 else 1484 rtl_mod_config2(tp, PME_SIGNAL, 0); 1485 break; 1486 default: 1487 break; 1488 } 1489 1490 rtl_lock_config_regs(tp); 1491 1492 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1493 1494 if (!tp->dash_enabled) { 1495 rtl_set_d3_pll_down(tp, !wolopts); 1496 tp->dev->wol_enabled = wolopts ? 1 : 0; 1497 } 1498 } 1499 1500 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1501 { 1502 struct rtl8169_private *tp = netdev_priv(dev); 1503 1504 if (wol->wolopts & ~WAKE_ANY) 1505 return -EINVAL; 1506 1507 tp->saved_wolopts = wol->wolopts; 1508 __rtl8169_set_wol(tp, tp->saved_wolopts); 1509 1510 return 0; 1511 } 1512 1513 static void rtl8169_get_drvinfo(struct net_device *dev, 1514 struct ethtool_drvinfo *info) 1515 { 1516 struct rtl8169_private *tp = netdev_priv(dev); 1517 struct rtl_fw *rtl_fw = tp->rtl_fw; 1518 1519 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1520 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1521 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1522 if (rtl_fw) 1523 strscpy(info->fw_version, rtl_fw->version, 1524 sizeof(info->fw_version)); 1525 } 1526 1527 static int rtl8169_get_regs_len(struct net_device *dev) 1528 { 1529 return R8169_REGS_SIZE; 1530 } 1531 1532 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1533 netdev_features_t features) 1534 { 1535 struct rtl8169_private *tp = netdev_priv(dev); 1536 1537 if (dev->mtu > TD_MSS_MAX) 1538 features &= ~NETIF_F_ALL_TSO; 1539 1540 if (dev->mtu > ETH_DATA_LEN && 1541 tp->mac_version > RTL_GIGA_MAC_VER_06) 1542 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1543 1544 return features; 1545 } 1546 1547 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1548 netdev_features_t features) 1549 { 1550 u32 rx_config = RTL_R32(tp, RxConfig); 1551 1552 if (features & NETIF_F_RXALL) 1553 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1554 else 1555 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1556 1557 if (rtl_is_8125(tp)) { 1558 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1559 rx_config |= RX_VLAN_8125; 1560 else 1561 rx_config &= ~RX_VLAN_8125; 1562 } 1563 1564 RTL_W32(tp, RxConfig, rx_config); 1565 } 1566 1567 static int rtl8169_set_features(struct net_device *dev, 1568 netdev_features_t features) 1569 { 1570 struct rtl8169_private *tp = netdev_priv(dev); 1571 1572 rtl_set_rx_config_features(tp, features); 1573 1574 if (features & NETIF_F_RXCSUM) 1575 tp->cp_cmd |= RxChkSum; 1576 else 1577 tp->cp_cmd &= ~RxChkSum; 1578 1579 if (!rtl_is_8125(tp)) { 1580 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1581 tp->cp_cmd |= RxVlan; 1582 else 1583 tp->cp_cmd &= ~RxVlan; 1584 } 1585 1586 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1587 rtl_pci_commit(tp); 1588 1589 return 0; 1590 } 1591 1592 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1593 { 1594 return (skb_vlan_tag_present(skb)) ? 1595 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1596 } 1597 1598 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1599 { 1600 u32 opts2 = le32_to_cpu(desc->opts2); 1601 1602 if (opts2 & RxVlanTag) 1603 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1604 } 1605 1606 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1607 void *p) 1608 { 1609 struct rtl8169_private *tp = netdev_priv(dev); 1610 u32 __iomem *data = tp->mmio_addr; 1611 u32 *dw = p; 1612 int i; 1613 1614 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1615 memcpy_fromio(dw++, data++, 4); 1616 } 1617 1618 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1619 "tx_packets", 1620 "rx_packets", 1621 "tx_errors", 1622 "rx_errors", 1623 "rx_missed", 1624 "align_errors", 1625 "tx_single_collisions", 1626 "tx_multi_collisions", 1627 "unicast", 1628 "broadcast", 1629 "multicast", 1630 "tx_aborted", 1631 "tx_underrun", 1632 }; 1633 1634 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1635 { 1636 switch (sset) { 1637 case ETH_SS_STATS: 1638 return ARRAY_SIZE(rtl8169_gstrings); 1639 default: 1640 return -EOPNOTSUPP; 1641 } 1642 } 1643 1644 DECLARE_RTL_COND(rtl_counters_cond) 1645 { 1646 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1647 } 1648 1649 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1650 { 1651 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1652 1653 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1654 rtl_pci_commit(tp); 1655 RTL_W32(tp, CounterAddrLow, cmd); 1656 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1657 1658 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1659 } 1660 1661 static void rtl8169_update_counters(struct rtl8169_private *tp) 1662 { 1663 u8 val = RTL_R8(tp, ChipCmd); 1664 1665 /* 1666 * Some chips are unable to dump tally counters when the receiver 1667 * is disabled. If 0xff chip may be in a PCI power-save state. 1668 */ 1669 if (val & CmdRxEnb && val != 0xff) 1670 rtl8169_do_counters(tp, CounterDump); 1671 } 1672 1673 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1674 { 1675 struct rtl8169_counters *counters = tp->counters; 1676 1677 /* 1678 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1679 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1680 * reset by a power cycle, while the counter values collected by the 1681 * driver are reset at every driver unload/load cycle. 1682 * 1683 * To make sure the HW values returned by @get_stats64 match the SW 1684 * values, we collect the initial values at first open(*) and use them 1685 * as offsets to normalize the values returned by @get_stats64. 1686 * 1687 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1688 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1689 * set at open time by rtl_hw_start. 1690 */ 1691 1692 if (tp->tc_offset.inited) 1693 return; 1694 1695 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1696 rtl8169_do_counters(tp, CounterReset); 1697 } else { 1698 rtl8169_update_counters(tp); 1699 tp->tc_offset.tx_errors = counters->tx_errors; 1700 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1701 tp->tc_offset.tx_aborted = counters->tx_aborted; 1702 tp->tc_offset.rx_missed = counters->rx_missed; 1703 } 1704 1705 tp->tc_offset.inited = true; 1706 } 1707 1708 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1709 struct ethtool_stats *stats, u64 *data) 1710 { 1711 struct rtl8169_private *tp = netdev_priv(dev); 1712 struct rtl8169_counters *counters; 1713 1714 counters = tp->counters; 1715 rtl8169_update_counters(tp); 1716 1717 data[0] = le64_to_cpu(counters->tx_packets); 1718 data[1] = le64_to_cpu(counters->rx_packets); 1719 data[2] = le64_to_cpu(counters->tx_errors); 1720 data[3] = le32_to_cpu(counters->rx_errors); 1721 data[4] = le16_to_cpu(counters->rx_missed); 1722 data[5] = le16_to_cpu(counters->align_errors); 1723 data[6] = le32_to_cpu(counters->tx_one_collision); 1724 data[7] = le32_to_cpu(counters->tx_multi_collision); 1725 data[8] = le64_to_cpu(counters->rx_unicast); 1726 data[9] = le64_to_cpu(counters->rx_broadcast); 1727 data[10] = le32_to_cpu(counters->rx_multicast); 1728 data[11] = le16_to_cpu(counters->tx_aborted); 1729 data[12] = le16_to_cpu(counters->tx_underun); 1730 } 1731 1732 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1733 { 1734 switch(stringset) { 1735 case ETH_SS_STATS: 1736 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1737 break; 1738 } 1739 } 1740 1741 /* 1742 * Interrupt coalescing 1743 * 1744 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1745 * > 8169, 8168 and 810x line of chipsets 1746 * 1747 * 8169, 8168, and 8136(810x) serial chipsets support it. 1748 * 1749 * > 2 - the Tx timer unit at gigabit speed 1750 * 1751 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1752 * (0xe0) bit 1 and bit 0. 1753 * 1754 * For 8169 1755 * bit[1:0] \ speed 1000M 100M 10M 1756 * 0 0 320ns 2.56us 40.96us 1757 * 0 1 2.56us 20.48us 327.7us 1758 * 1 0 5.12us 40.96us 655.4us 1759 * 1 1 10.24us 81.92us 1.31ms 1760 * 1761 * For the other 1762 * bit[1:0] \ speed 1000M 100M 10M 1763 * 0 0 5us 2.56us 40.96us 1764 * 0 1 40us 20.48us 327.7us 1765 * 1 0 80us 40.96us 655.4us 1766 * 1 1 160us 81.92us 1.31ms 1767 */ 1768 1769 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1770 struct rtl_coalesce_info { 1771 u32 speed; 1772 u32 scale_nsecs[4]; 1773 }; 1774 1775 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1776 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1777 1778 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1779 { SPEED_1000, COALESCE_DELAY(320) }, 1780 { SPEED_100, COALESCE_DELAY(2560) }, 1781 { SPEED_10, COALESCE_DELAY(40960) }, 1782 { 0 }, 1783 }; 1784 1785 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1786 { SPEED_1000, COALESCE_DELAY(5000) }, 1787 { SPEED_100, COALESCE_DELAY(2560) }, 1788 { SPEED_10, COALESCE_DELAY(40960) }, 1789 { 0 }, 1790 }; 1791 #undef COALESCE_DELAY 1792 1793 /* get rx/tx scale vector corresponding to current speed */ 1794 static const struct rtl_coalesce_info * 1795 rtl_coalesce_info(struct rtl8169_private *tp) 1796 { 1797 const struct rtl_coalesce_info *ci; 1798 1799 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1800 ci = rtl_coalesce_info_8169; 1801 else 1802 ci = rtl_coalesce_info_8168_8136; 1803 1804 /* if speed is unknown assume highest one */ 1805 if (tp->phydev->speed == SPEED_UNKNOWN) 1806 return ci; 1807 1808 for (; ci->speed; ci++) { 1809 if (tp->phydev->speed == ci->speed) 1810 return ci; 1811 } 1812 1813 return ERR_PTR(-ELNRNG); 1814 } 1815 1816 static int rtl_get_coalesce(struct net_device *dev, 1817 struct ethtool_coalesce *ec, 1818 struct kernel_ethtool_coalesce *kernel_coal, 1819 struct netlink_ext_ack *extack) 1820 { 1821 struct rtl8169_private *tp = netdev_priv(dev); 1822 const struct rtl_coalesce_info *ci; 1823 u32 scale, c_us, c_fr; 1824 u16 intrmit; 1825 1826 if (rtl_is_8125(tp)) 1827 return -EOPNOTSUPP; 1828 1829 memset(ec, 0, sizeof(*ec)); 1830 1831 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1832 ci = rtl_coalesce_info(tp); 1833 if (IS_ERR(ci)) 1834 return PTR_ERR(ci); 1835 1836 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1837 1838 intrmit = RTL_R16(tp, IntrMitigate); 1839 1840 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1841 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1842 1843 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1844 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1845 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1846 1847 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1848 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1849 1850 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1851 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1852 1853 return 0; 1854 } 1855 1856 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1857 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1858 u16 *cp01) 1859 { 1860 const struct rtl_coalesce_info *ci; 1861 u16 i; 1862 1863 ci = rtl_coalesce_info(tp); 1864 if (IS_ERR(ci)) 1865 return PTR_ERR(ci); 1866 1867 for (i = 0; i < 4; i++) { 1868 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1869 *cp01 = i; 1870 return ci->scale_nsecs[i]; 1871 } 1872 } 1873 1874 return -ERANGE; 1875 } 1876 1877 static int rtl_set_coalesce(struct net_device *dev, 1878 struct ethtool_coalesce *ec, 1879 struct kernel_ethtool_coalesce *kernel_coal, 1880 struct netlink_ext_ack *extack) 1881 { 1882 struct rtl8169_private *tp = netdev_priv(dev); 1883 u32 tx_fr = ec->tx_max_coalesced_frames; 1884 u32 rx_fr = ec->rx_max_coalesced_frames; 1885 u32 coal_usec_max, units; 1886 u16 w = 0, cp01 = 0; 1887 int scale; 1888 1889 if (rtl_is_8125(tp)) 1890 return -EOPNOTSUPP; 1891 1892 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1893 return -ERANGE; 1894 1895 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1896 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1897 if (scale < 0) 1898 return scale; 1899 1900 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1901 * not only when usecs=0 because of e.g. the following scenario: 1902 * 1903 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1904 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1905 * - then user does `ethtool -C eth0 rx-usecs 100` 1906 * 1907 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1908 * if we want to ignore rx_frames then it has to be set to 0. 1909 */ 1910 if (rx_fr == 1) 1911 rx_fr = 0; 1912 if (tx_fr == 1) 1913 tx_fr = 0; 1914 1915 /* HW requires time limit to be set if frame limit is set */ 1916 if ((tx_fr && !ec->tx_coalesce_usecs) || 1917 (rx_fr && !ec->rx_coalesce_usecs)) 1918 return -EINVAL; 1919 1920 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1921 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1922 1923 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1924 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1925 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1926 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1927 1928 RTL_W16(tp, IntrMitigate, w); 1929 1930 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1931 if (rtl_is_8168evl_up(tp)) { 1932 if (!rx_fr && !tx_fr) 1933 /* disable packet counter */ 1934 tp->cp_cmd |= PktCntrDisable; 1935 else 1936 tp->cp_cmd &= ~PktCntrDisable; 1937 } 1938 1939 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1940 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1941 rtl_pci_commit(tp); 1942 1943 return 0; 1944 } 1945 1946 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1947 { 1948 struct rtl8169_private *tp = netdev_priv(dev); 1949 1950 if (!rtl_supports_eee(tp)) 1951 return -EOPNOTSUPP; 1952 1953 return phy_ethtool_get_eee(tp->phydev, data); 1954 } 1955 1956 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1957 { 1958 struct rtl8169_private *tp = netdev_priv(dev); 1959 int ret; 1960 1961 if (!rtl_supports_eee(tp)) 1962 return -EOPNOTSUPP; 1963 1964 ret = phy_ethtool_set_eee(tp->phydev, data); 1965 1966 if (!ret) 1967 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1968 MDIO_AN_EEE_ADV); 1969 return ret; 1970 } 1971 1972 static void rtl8169_get_ringparam(struct net_device *dev, 1973 struct ethtool_ringparam *data, 1974 struct kernel_ethtool_ringparam *kernel_data, 1975 struct netlink_ext_ack *extack) 1976 { 1977 data->rx_max_pending = NUM_RX_DESC; 1978 data->rx_pending = NUM_RX_DESC; 1979 data->tx_max_pending = NUM_TX_DESC; 1980 data->tx_pending = NUM_TX_DESC; 1981 } 1982 1983 static void rtl8169_get_pauseparam(struct net_device *dev, 1984 struct ethtool_pauseparam *data) 1985 { 1986 struct rtl8169_private *tp = netdev_priv(dev); 1987 bool tx_pause, rx_pause; 1988 1989 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1990 1991 data->autoneg = tp->phydev->autoneg; 1992 data->tx_pause = tx_pause ? 1 : 0; 1993 data->rx_pause = rx_pause ? 1 : 0; 1994 } 1995 1996 static int rtl8169_set_pauseparam(struct net_device *dev, 1997 struct ethtool_pauseparam *data) 1998 { 1999 struct rtl8169_private *tp = netdev_priv(dev); 2000 2001 if (dev->mtu > ETH_DATA_LEN) 2002 return -EOPNOTSUPP; 2003 2004 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2005 2006 return 0; 2007 } 2008 2009 static const struct ethtool_ops rtl8169_ethtool_ops = { 2010 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2011 ETHTOOL_COALESCE_MAX_FRAMES, 2012 .get_drvinfo = rtl8169_get_drvinfo, 2013 .get_regs_len = rtl8169_get_regs_len, 2014 .get_link = ethtool_op_get_link, 2015 .get_coalesce = rtl_get_coalesce, 2016 .set_coalesce = rtl_set_coalesce, 2017 .get_regs = rtl8169_get_regs, 2018 .get_wol = rtl8169_get_wol, 2019 .set_wol = rtl8169_set_wol, 2020 .get_strings = rtl8169_get_strings, 2021 .get_sset_count = rtl8169_get_sset_count, 2022 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2023 .get_ts_info = ethtool_op_get_ts_info, 2024 .nway_reset = phy_ethtool_nway_reset, 2025 .get_eee = rtl8169_get_eee, 2026 .set_eee = rtl8169_set_eee, 2027 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2028 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2029 .get_ringparam = rtl8169_get_ringparam, 2030 .get_pauseparam = rtl8169_get_pauseparam, 2031 .set_pauseparam = rtl8169_set_pauseparam, 2032 }; 2033 2034 static void rtl_enable_eee(struct rtl8169_private *tp) 2035 { 2036 struct phy_device *phydev = tp->phydev; 2037 int adv; 2038 2039 /* respect EEE advertisement the user may have set */ 2040 if (tp->eee_adv >= 0) 2041 adv = tp->eee_adv; 2042 else 2043 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2044 2045 if (adv >= 0) 2046 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2047 } 2048 2049 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2050 { 2051 /* 2052 * The driver currently handles the 8168Bf and the 8168Be identically 2053 * but they can be identified more specifically through the test below 2054 * if needed: 2055 * 2056 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2057 * 2058 * Same thing for the 8101Eb and the 8101Ec: 2059 * 2060 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2061 */ 2062 static const struct rtl_mac_info { 2063 u16 mask; 2064 u16 val; 2065 enum mac_version ver; 2066 } mac_info[] = { 2067 /* 8125B family. */ 2068 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2069 2070 /* 8125A family. */ 2071 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2072 /* It seems only XID 609 made it to the mass market. 2073 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2074 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2075 */ 2076 2077 /* RTL8117 */ 2078 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2079 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2080 2081 /* 8168EP family. */ 2082 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2083 /* It seems this chip version never made it to 2084 * the wild. Let's disable detection. 2085 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2086 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2087 */ 2088 2089 /* 8168H family. */ 2090 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2091 /* It seems this chip version never made it to 2092 * the wild. Let's disable detection. 2093 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2094 */ 2095 2096 /* 8168G family. */ 2097 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2098 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2099 /* It seems this chip version never made it to 2100 * the wild. Let's disable detection. 2101 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2102 */ 2103 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2104 2105 /* 8168F family. */ 2106 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2107 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2108 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2109 2110 /* 8168E family. */ 2111 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2112 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2113 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2114 2115 /* 8168D family. */ 2116 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2117 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2118 2119 /* 8168DP family. */ 2120 /* It seems this early RTL8168dp version never made it to 2121 * the wild. Support has been removed. 2122 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2123 */ 2124 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2125 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2126 2127 /* 8168C family. */ 2128 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2129 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2130 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2131 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2132 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2133 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2134 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2135 2136 /* 8168B family. */ 2137 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2138 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2139 2140 /* 8101 family. */ 2141 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2142 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2143 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2144 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2145 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2146 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2147 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2148 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2149 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2150 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2151 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2152 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2153 2154 /* 8110 family. */ 2155 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2156 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2157 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2158 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2159 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2160 2161 /* Catch-all */ 2162 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2163 }; 2164 const struct rtl_mac_info *p = mac_info; 2165 enum mac_version ver; 2166 2167 while ((xid & p->mask) != p->val) 2168 p++; 2169 ver = p->ver; 2170 2171 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2172 if (ver == RTL_GIGA_MAC_VER_42) 2173 ver = RTL_GIGA_MAC_VER_43; 2174 else if (ver == RTL_GIGA_MAC_VER_46) 2175 ver = RTL_GIGA_MAC_VER_48; 2176 } 2177 2178 return ver; 2179 } 2180 2181 static void rtl_release_firmware(struct rtl8169_private *tp) 2182 { 2183 if (tp->rtl_fw) { 2184 rtl_fw_release_firmware(tp->rtl_fw); 2185 kfree(tp->rtl_fw); 2186 tp->rtl_fw = NULL; 2187 } 2188 } 2189 2190 void r8169_apply_firmware(struct rtl8169_private *tp) 2191 { 2192 int val; 2193 2194 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2195 if (tp->rtl_fw) { 2196 rtl_fw_write_firmware(tp, tp->rtl_fw); 2197 /* At least one firmware doesn't reset tp->ocp_base. */ 2198 tp->ocp_base = OCP_STD_PHY_BASE; 2199 2200 /* PHY soft reset may still be in progress */ 2201 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2202 !(val & BMCR_RESET), 2203 50000, 600000, true); 2204 } 2205 } 2206 2207 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2208 { 2209 /* Adjust EEE LED frequency */ 2210 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2211 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2212 2213 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2214 } 2215 2216 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2217 { 2218 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2219 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2220 } 2221 2222 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2223 { 2224 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2225 } 2226 2227 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2228 { 2229 rtl8125_set_eee_txidle_timer(tp); 2230 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2231 } 2232 2233 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2234 { 2235 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2236 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2237 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2238 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2239 } 2240 2241 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2242 { 2243 u16 data1, data2, ioffset; 2244 2245 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2246 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2247 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2248 2249 ioffset = (data2 >> 1) & 0x7ff8; 2250 ioffset |= data2 & 0x0007; 2251 if (data1 & BIT(7)) 2252 ioffset |= BIT(15); 2253 2254 return ioffset; 2255 } 2256 2257 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2258 { 2259 set_bit(flag, tp->wk.flags); 2260 schedule_work(&tp->wk.work); 2261 } 2262 2263 static void rtl8169_init_phy(struct rtl8169_private *tp) 2264 { 2265 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2266 2267 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2268 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2269 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2270 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2271 RTL_W8(tp, 0x82, 0x01); 2272 } 2273 2274 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2275 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2276 tp->pci_dev->subsystem_device == 0xe000) 2277 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2278 2279 /* We may have called phy_speed_down before */ 2280 phy_speed_up(tp->phydev); 2281 2282 if (rtl_supports_eee(tp)) 2283 rtl_enable_eee(tp); 2284 2285 genphy_soft_reset(tp->phydev); 2286 } 2287 2288 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2289 { 2290 rtl_unlock_config_regs(tp); 2291 2292 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2293 rtl_pci_commit(tp); 2294 2295 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2296 rtl_pci_commit(tp); 2297 2298 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2299 rtl_rar_exgmac_set(tp, addr); 2300 2301 rtl_lock_config_regs(tp); 2302 } 2303 2304 static int rtl_set_mac_address(struct net_device *dev, void *p) 2305 { 2306 struct rtl8169_private *tp = netdev_priv(dev); 2307 int ret; 2308 2309 ret = eth_mac_addr(dev, p); 2310 if (ret) 2311 return ret; 2312 2313 rtl_rar_set(tp, dev->dev_addr); 2314 2315 return 0; 2316 } 2317 2318 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2319 { 2320 switch (tp->mac_version) { 2321 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2322 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2323 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2324 break; 2325 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2326 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2327 case RTL_GIGA_MAC_VER_38: 2328 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2329 break; 2330 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2331 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2332 break; 2333 case RTL_GIGA_MAC_VER_61: 2334 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2335 break; 2336 case RTL_GIGA_MAC_VER_63: 2337 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2338 RX_PAUSE_SLOT_ON); 2339 break; 2340 default: 2341 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2342 break; 2343 } 2344 } 2345 2346 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2347 { 2348 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2349 } 2350 2351 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2352 { 2353 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2354 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2355 } 2356 2357 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2358 { 2359 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2360 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2361 } 2362 2363 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2364 { 2365 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2366 } 2367 2368 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2369 { 2370 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2371 } 2372 2373 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2374 { 2375 RTL_W8(tp, MaxTxPacketSize, 0x24); 2376 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2377 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2378 } 2379 2380 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2381 { 2382 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2383 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2384 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2385 } 2386 2387 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2388 { 2389 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2390 } 2391 2392 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2393 { 2394 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2395 } 2396 2397 static void rtl_jumbo_config(struct rtl8169_private *tp) 2398 { 2399 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2400 int readrq = 4096; 2401 2402 rtl_unlock_config_regs(tp); 2403 switch (tp->mac_version) { 2404 case RTL_GIGA_MAC_VER_17: 2405 if (jumbo) { 2406 readrq = 512; 2407 r8168b_1_hw_jumbo_enable(tp); 2408 } else { 2409 r8168b_1_hw_jumbo_disable(tp); 2410 } 2411 break; 2412 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2413 if (jumbo) { 2414 readrq = 512; 2415 r8168c_hw_jumbo_enable(tp); 2416 } else { 2417 r8168c_hw_jumbo_disable(tp); 2418 } 2419 break; 2420 case RTL_GIGA_MAC_VER_28: 2421 if (jumbo) 2422 r8168dp_hw_jumbo_enable(tp); 2423 else 2424 r8168dp_hw_jumbo_disable(tp); 2425 break; 2426 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2427 if (jumbo) 2428 r8168e_hw_jumbo_enable(tp); 2429 else 2430 r8168e_hw_jumbo_disable(tp); 2431 break; 2432 default: 2433 break; 2434 } 2435 rtl_lock_config_regs(tp); 2436 2437 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2438 pcie_set_readrq(tp->pci_dev, readrq); 2439 2440 /* Chip doesn't support pause in jumbo mode */ 2441 if (jumbo) { 2442 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2443 tp->phydev->advertising); 2444 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2445 tp->phydev->advertising); 2446 phy_start_aneg(tp->phydev); 2447 } 2448 } 2449 2450 DECLARE_RTL_COND(rtl_chipcmd_cond) 2451 { 2452 return RTL_R8(tp, ChipCmd) & CmdReset; 2453 } 2454 2455 static void rtl_hw_reset(struct rtl8169_private *tp) 2456 { 2457 RTL_W8(tp, ChipCmd, CmdReset); 2458 2459 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2460 } 2461 2462 static void rtl_request_firmware(struct rtl8169_private *tp) 2463 { 2464 struct rtl_fw *rtl_fw; 2465 2466 /* firmware loaded already or no firmware available */ 2467 if (tp->rtl_fw || !tp->fw_name) 2468 return; 2469 2470 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2471 if (!rtl_fw) 2472 return; 2473 2474 rtl_fw->phy_write = rtl_writephy; 2475 rtl_fw->phy_read = rtl_readphy; 2476 rtl_fw->mac_mcu_write = mac_mcu_write; 2477 rtl_fw->mac_mcu_read = mac_mcu_read; 2478 rtl_fw->fw_name = tp->fw_name; 2479 rtl_fw->dev = tp_to_dev(tp); 2480 2481 if (rtl_fw_request_firmware(rtl_fw)) 2482 kfree(rtl_fw); 2483 else 2484 tp->rtl_fw = rtl_fw; 2485 } 2486 2487 static void rtl_rx_close(struct rtl8169_private *tp) 2488 { 2489 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2490 } 2491 2492 DECLARE_RTL_COND(rtl_npq_cond) 2493 { 2494 return RTL_R8(tp, TxPoll) & NPQ; 2495 } 2496 2497 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2498 { 2499 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2500 } 2501 2502 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2503 { 2504 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2505 } 2506 2507 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2508 { 2509 /* IntrMitigate has new functionality on RTL8125 */ 2510 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2511 } 2512 2513 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2514 { 2515 switch (tp->mac_version) { 2516 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2517 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2518 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2519 break; 2520 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2521 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2522 break; 2523 case RTL_GIGA_MAC_VER_63: 2524 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2525 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2526 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2527 break; 2528 default: 2529 break; 2530 } 2531 } 2532 2533 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2534 { 2535 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2536 } 2537 2538 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2539 { 2540 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2541 fsleep(2000); 2542 rtl_wait_txrx_fifo_empty(tp); 2543 } 2544 2545 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2546 { 2547 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2548 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2549 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2550 2551 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2552 rtl_disable_rxdvgate(tp); 2553 } 2554 2555 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2556 { 2557 if (tp->dash_enabled) 2558 return; 2559 2560 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2561 tp->mac_version == RTL_GIGA_MAC_VER_33) 2562 rtl_ephy_write(tp, 0x19, 0xff64); 2563 2564 if (device_may_wakeup(tp_to_dev(tp))) { 2565 phy_speed_down(tp->phydev, false); 2566 rtl_wol_enable_rx(tp); 2567 } 2568 } 2569 2570 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2571 { 2572 u32 val = TX_DMA_BURST << TxDMAShift | 2573 InterFrameGap << TxInterFrameGapShift; 2574 2575 if (rtl_is_8168evl_up(tp)) 2576 val |= TXCFG_AUTO_FIFO; 2577 2578 RTL_W32(tp, TxConfig, val); 2579 } 2580 2581 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2582 { 2583 /* Low hurts. Let's disable the filtering. */ 2584 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2585 } 2586 2587 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2588 { 2589 /* 2590 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2591 * register to be written before TxDescAddrLow to work. 2592 * Switching from MMIO to I/O access fixes the issue as well. 2593 */ 2594 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2595 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2596 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2597 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2598 } 2599 2600 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2601 { 2602 u32 val; 2603 2604 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2605 val = 0x000fff00; 2606 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2607 val = 0x00ffff00; 2608 else 2609 return; 2610 2611 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2612 val |= 0xff; 2613 2614 RTL_W32(tp, 0x7c, val); 2615 } 2616 2617 static void rtl_set_rx_mode(struct net_device *dev) 2618 { 2619 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2620 /* Multicast hash filter */ 2621 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2622 struct rtl8169_private *tp = netdev_priv(dev); 2623 u32 tmp; 2624 2625 if (dev->flags & IFF_PROMISC) { 2626 rx_mode |= AcceptAllPhys; 2627 } else if (!(dev->flags & IFF_MULTICAST)) { 2628 rx_mode &= ~AcceptMulticast; 2629 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2630 dev->flags & IFF_ALLMULTI || 2631 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2632 /* accept all multicasts */ 2633 } else if (netdev_mc_empty(dev)) { 2634 rx_mode &= ~AcceptMulticast; 2635 } else { 2636 struct netdev_hw_addr *ha; 2637 2638 mc_filter[1] = mc_filter[0] = 0; 2639 netdev_for_each_mc_addr(ha, dev) { 2640 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2641 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2642 } 2643 2644 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2645 tmp = mc_filter[0]; 2646 mc_filter[0] = swab32(mc_filter[1]); 2647 mc_filter[1] = swab32(tmp); 2648 } 2649 } 2650 2651 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2652 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2653 2654 tmp = RTL_R32(tp, RxConfig); 2655 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2656 } 2657 2658 DECLARE_RTL_COND(rtl_csiar_cond) 2659 { 2660 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2661 } 2662 2663 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2664 { 2665 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2666 2667 RTL_W32(tp, CSIDR, value); 2668 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2669 CSIAR_BYTE_ENABLE | func << 16); 2670 2671 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2672 } 2673 2674 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2675 { 2676 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2677 2678 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2679 CSIAR_BYTE_ENABLE); 2680 2681 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2682 RTL_R32(tp, CSIDR) : ~0; 2683 } 2684 2685 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2686 { 2687 struct pci_dev *pdev = tp->pci_dev; 2688 u32 csi; 2689 2690 /* According to Realtek the value at config space address 0x070f 2691 * controls the L0s/L1 entrance latency. We try standard ECAM access 2692 * first and if it fails fall back to CSI. 2693 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2694 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2695 */ 2696 if (pdev->cfg_size > 0x070f && 2697 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2698 return; 2699 2700 netdev_notice_once(tp->dev, 2701 "No native access to PCI extended config space, falling back to CSI\n"); 2702 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2703 rtl_csi_write(tp, 0x070c, csi | val << 24); 2704 } 2705 2706 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2707 { 2708 /* L0 7us, L1 16us */ 2709 rtl_set_aspm_entry_latency(tp, 0x27); 2710 } 2711 2712 struct ephy_info { 2713 unsigned int offset; 2714 u16 mask; 2715 u16 bits; 2716 }; 2717 2718 static void __rtl_ephy_init(struct rtl8169_private *tp, 2719 const struct ephy_info *e, int len) 2720 { 2721 u16 w; 2722 2723 while (len-- > 0) { 2724 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2725 rtl_ephy_write(tp, e->offset, w); 2726 e++; 2727 } 2728 } 2729 2730 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2731 2732 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2733 { 2734 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2735 PCI_EXP_LNKCTL_CLKREQ_EN); 2736 } 2737 2738 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2739 { 2740 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2741 PCI_EXP_LNKCTL_CLKREQ_EN); 2742 } 2743 2744 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2745 { 2746 /* work around an issue when PCI reset occurs during L2/L3 state */ 2747 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2748 } 2749 2750 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2751 { 2752 /* Bits control which events trigger ASPM L1 exit: 2753 * Bit 12: rxdv 2754 * Bit 11: ltr_msg 2755 * Bit 10: txdma_poll 2756 * Bit 9: xadm 2757 * Bit 8: pktavi 2758 * Bit 7: txpla 2759 */ 2760 switch (tp->mac_version) { 2761 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2762 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2763 break; 2764 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2765 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2766 break; 2767 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2768 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2769 break; 2770 default: 2771 break; 2772 } 2773 } 2774 2775 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2776 { 2777 switch (tp->mac_version) { 2778 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2779 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2780 break; 2781 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2782 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2783 break; 2784 default: 2785 break; 2786 } 2787 } 2788 2789 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2790 { 2791 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2792 return; 2793 2794 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2795 if (enable && tp->aspm_manageable) { 2796 /* On these chip versions ASPM can even harm 2797 * bus communication of other PCI devices. 2798 */ 2799 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2800 tp->mac_version == RTL_GIGA_MAC_VER_43) 2801 return; 2802 2803 rtl_mod_config5(tp, 0, ASPM_en); 2804 rtl_mod_config2(tp, 0, ClkReqEn); 2805 2806 switch (tp->mac_version) { 2807 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2808 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2809 /* reset ephy tx/rx disable timer */ 2810 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2811 /* chip can trigger L1.2 */ 2812 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2813 break; 2814 default: 2815 break; 2816 } 2817 } else { 2818 switch (tp->mac_version) { 2819 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2820 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2821 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2822 break; 2823 default: 2824 break; 2825 } 2826 2827 rtl_mod_config2(tp, ClkReqEn, 0); 2828 rtl_mod_config5(tp, ASPM_en, 0); 2829 } 2830 } 2831 2832 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2833 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2834 { 2835 /* Usage of dynamic vs. static FIFO is controlled by bit 2836 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2837 */ 2838 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2839 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2840 } 2841 2842 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2843 u8 low, u8 high) 2844 { 2845 /* FIFO thresholds for pause flow control */ 2846 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2847 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2848 } 2849 2850 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2851 { 2852 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2853 } 2854 2855 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2856 { 2857 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2858 2859 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2860 2861 rtl_disable_clock_request(tp); 2862 } 2863 2864 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2865 { 2866 static const struct ephy_info e_info_8168cp[] = { 2867 { 0x01, 0, 0x0001 }, 2868 { 0x02, 0x0800, 0x1000 }, 2869 { 0x03, 0, 0x0042 }, 2870 { 0x06, 0x0080, 0x0000 }, 2871 { 0x07, 0, 0x2000 } 2872 }; 2873 2874 rtl_set_def_aspm_entry_latency(tp); 2875 2876 rtl_ephy_init(tp, e_info_8168cp); 2877 2878 __rtl_hw_start_8168cp(tp); 2879 } 2880 2881 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2882 { 2883 rtl_set_def_aspm_entry_latency(tp); 2884 2885 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2886 } 2887 2888 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2889 { 2890 rtl_set_def_aspm_entry_latency(tp); 2891 2892 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2893 2894 /* Magic. */ 2895 RTL_W8(tp, DBG_REG, 0x20); 2896 } 2897 2898 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2899 { 2900 static const struct ephy_info e_info_8168c_1[] = { 2901 { 0x02, 0x0800, 0x1000 }, 2902 { 0x03, 0, 0x0002 }, 2903 { 0x06, 0x0080, 0x0000 } 2904 }; 2905 2906 rtl_set_def_aspm_entry_latency(tp); 2907 2908 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2909 2910 rtl_ephy_init(tp, e_info_8168c_1); 2911 2912 __rtl_hw_start_8168cp(tp); 2913 } 2914 2915 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2916 { 2917 static const struct ephy_info e_info_8168c_2[] = { 2918 { 0x01, 0, 0x0001 }, 2919 { 0x03, 0x0400, 0x0020 } 2920 }; 2921 2922 rtl_set_def_aspm_entry_latency(tp); 2923 2924 rtl_ephy_init(tp, e_info_8168c_2); 2925 2926 __rtl_hw_start_8168cp(tp); 2927 } 2928 2929 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2930 { 2931 rtl_set_def_aspm_entry_latency(tp); 2932 2933 __rtl_hw_start_8168cp(tp); 2934 } 2935 2936 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2937 { 2938 rtl_set_def_aspm_entry_latency(tp); 2939 2940 rtl_disable_clock_request(tp); 2941 } 2942 2943 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2944 { 2945 static const struct ephy_info e_info_8168d_4[] = { 2946 { 0x0b, 0x0000, 0x0048 }, 2947 { 0x19, 0x0020, 0x0050 }, 2948 { 0x0c, 0x0100, 0x0020 }, 2949 { 0x10, 0x0004, 0x0000 }, 2950 }; 2951 2952 rtl_set_def_aspm_entry_latency(tp); 2953 2954 rtl_ephy_init(tp, e_info_8168d_4); 2955 2956 rtl_enable_clock_request(tp); 2957 } 2958 2959 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2960 { 2961 static const struct ephy_info e_info_8168e_1[] = { 2962 { 0x00, 0x0200, 0x0100 }, 2963 { 0x00, 0x0000, 0x0004 }, 2964 { 0x06, 0x0002, 0x0001 }, 2965 { 0x06, 0x0000, 0x0030 }, 2966 { 0x07, 0x0000, 0x2000 }, 2967 { 0x00, 0x0000, 0x0020 }, 2968 { 0x03, 0x5800, 0x2000 }, 2969 { 0x03, 0x0000, 0x0001 }, 2970 { 0x01, 0x0800, 0x1000 }, 2971 { 0x07, 0x0000, 0x4000 }, 2972 { 0x1e, 0x0000, 0x2000 }, 2973 { 0x19, 0xffff, 0xfe6c }, 2974 { 0x0a, 0x0000, 0x0040 } 2975 }; 2976 2977 rtl_set_def_aspm_entry_latency(tp); 2978 2979 rtl_ephy_init(tp, e_info_8168e_1); 2980 2981 rtl_disable_clock_request(tp); 2982 2983 /* Reset tx FIFO pointer */ 2984 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2985 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2986 2987 rtl_mod_config5(tp, Spi_en, 0); 2988 } 2989 2990 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2991 { 2992 static const struct ephy_info e_info_8168e_2[] = { 2993 { 0x09, 0x0000, 0x0080 }, 2994 { 0x19, 0x0000, 0x0224 }, 2995 { 0x00, 0x0000, 0x0004 }, 2996 { 0x0c, 0x3df0, 0x0200 }, 2997 }; 2998 2999 rtl_set_def_aspm_entry_latency(tp); 3000 3001 rtl_ephy_init(tp, e_info_8168e_2); 3002 3003 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3004 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3005 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3006 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3007 rtl_reset_packet_filter(tp); 3008 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3009 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3010 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3011 3012 rtl_disable_clock_request(tp); 3013 3014 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3015 3016 rtl8168_config_eee_mac(tp); 3017 3018 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3019 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3020 rtl_mod_config5(tp, Spi_en, 0); 3021 } 3022 3023 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3024 { 3025 rtl_set_def_aspm_entry_latency(tp); 3026 3027 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3028 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3029 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3030 rtl_reset_packet_filter(tp); 3031 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3032 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3033 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3034 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3035 3036 rtl_disable_clock_request(tp); 3037 3038 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3039 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3040 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3041 rtl_mod_config5(tp, Spi_en, 0); 3042 3043 rtl8168_config_eee_mac(tp); 3044 } 3045 3046 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3047 { 3048 static const struct ephy_info e_info_8168f_1[] = { 3049 { 0x06, 0x00c0, 0x0020 }, 3050 { 0x08, 0x0001, 0x0002 }, 3051 { 0x09, 0x0000, 0x0080 }, 3052 { 0x19, 0x0000, 0x0224 }, 3053 { 0x00, 0x0000, 0x0008 }, 3054 { 0x0c, 0x3df0, 0x0200 }, 3055 }; 3056 3057 rtl_hw_start_8168f(tp); 3058 3059 rtl_ephy_init(tp, e_info_8168f_1); 3060 } 3061 3062 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3063 { 3064 static const struct ephy_info e_info_8168f_1[] = { 3065 { 0x06, 0x00c0, 0x0020 }, 3066 { 0x0f, 0xffff, 0x5200 }, 3067 { 0x19, 0x0000, 0x0224 }, 3068 { 0x00, 0x0000, 0x0008 }, 3069 { 0x0c, 0x3df0, 0x0200 }, 3070 }; 3071 3072 rtl_hw_start_8168f(tp); 3073 rtl_pcie_state_l2l3_disable(tp); 3074 3075 rtl_ephy_init(tp, e_info_8168f_1); 3076 } 3077 3078 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3079 { 3080 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3081 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3082 3083 rtl_set_def_aspm_entry_latency(tp); 3084 3085 rtl_reset_packet_filter(tp); 3086 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3087 3088 rtl_disable_rxdvgate(tp); 3089 3090 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3091 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3092 3093 rtl8168_config_eee_mac(tp); 3094 3095 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3096 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3097 3098 rtl_pcie_state_l2l3_disable(tp); 3099 } 3100 3101 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3102 { 3103 static const struct ephy_info e_info_8168g_1[] = { 3104 { 0x00, 0x0008, 0x0000 }, 3105 { 0x0c, 0x3ff0, 0x0820 }, 3106 { 0x1e, 0x0000, 0x0001 }, 3107 { 0x19, 0x8000, 0x0000 } 3108 }; 3109 3110 rtl_hw_start_8168g(tp); 3111 rtl_ephy_init(tp, e_info_8168g_1); 3112 } 3113 3114 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3115 { 3116 static const struct ephy_info e_info_8168g_2[] = { 3117 { 0x00, 0x0008, 0x0000 }, 3118 { 0x0c, 0x3ff0, 0x0820 }, 3119 { 0x19, 0xffff, 0x7c00 }, 3120 { 0x1e, 0xffff, 0x20eb }, 3121 { 0x0d, 0xffff, 0x1666 }, 3122 { 0x00, 0xffff, 0x10a3 }, 3123 { 0x06, 0xffff, 0xf050 }, 3124 { 0x04, 0x0000, 0x0010 }, 3125 { 0x1d, 0x4000, 0x0000 }, 3126 }; 3127 3128 rtl_hw_start_8168g(tp); 3129 rtl_ephy_init(tp, e_info_8168g_2); 3130 } 3131 3132 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3133 { 3134 static const struct ephy_info e_info_8411_2[] = { 3135 { 0x00, 0x0008, 0x0000 }, 3136 { 0x0c, 0x37d0, 0x0820 }, 3137 { 0x1e, 0x0000, 0x0001 }, 3138 { 0x19, 0x8021, 0x0000 }, 3139 { 0x1e, 0x0000, 0x2000 }, 3140 { 0x0d, 0x0100, 0x0200 }, 3141 { 0x00, 0x0000, 0x0080 }, 3142 { 0x06, 0x0000, 0x0010 }, 3143 { 0x04, 0x0000, 0x0010 }, 3144 { 0x1d, 0x0000, 0x4000 }, 3145 }; 3146 3147 rtl_hw_start_8168g(tp); 3148 3149 rtl_ephy_init(tp, e_info_8411_2); 3150 3151 /* The following Realtek-provided magic fixes an issue with the RX unit 3152 * getting confused after the PHY having been powered-down. 3153 */ 3154 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3155 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3156 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3157 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3158 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3159 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3160 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3161 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3162 mdelay(3); 3163 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3164 3165 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3166 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3167 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3168 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3169 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3170 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3171 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3172 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3173 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3174 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3175 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3176 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3177 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3178 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3179 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3180 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3181 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3182 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3183 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3184 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3185 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3186 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3187 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3188 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3189 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3190 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3191 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3192 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3193 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3194 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3195 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3196 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3197 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3198 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3199 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3200 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3201 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3202 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3203 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3204 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3205 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3206 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3207 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3208 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3209 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3210 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3211 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3212 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3213 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3214 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3215 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3216 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3217 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3218 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3219 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3220 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3221 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3222 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3223 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3224 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3225 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3226 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3227 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3228 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3229 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3230 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3231 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3232 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3233 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3234 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3235 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3236 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3237 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3238 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3239 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3240 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3241 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3242 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3243 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3244 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3245 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3246 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3247 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3248 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3249 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3250 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3251 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3252 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3253 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3254 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3255 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3256 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3257 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3258 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3259 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3260 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3261 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3262 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3263 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3264 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3265 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3266 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3267 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3268 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3269 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3270 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3271 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3272 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3273 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3274 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3275 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3276 3277 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3278 3279 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3280 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3281 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3282 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3283 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3284 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3285 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3286 } 3287 3288 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3289 { 3290 static const struct ephy_info e_info_8168h_1[] = { 3291 { 0x1e, 0x0800, 0x0001 }, 3292 { 0x1d, 0x0000, 0x0800 }, 3293 { 0x05, 0xffff, 0x2089 }, 3294 { 0x06, 0xffff, 0x5881 }, 3295 { 0x04, 0xffff, 0x854a }, 3296 { 0x01, 0xffff, 0x068b } 3297 }; 3298 int rg_saw_cnt; 3299 3300 rtl_ephy_init(tp, e_info_8168h_1); 3301 3302 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3303 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3304 3305 rtl_set_def_aspm_entry_latency(tp); 3306 3307 rtl_reset_packet_filter(tp); 3308 3309 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3310 3311 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3312 3313 rtl_disable_rxdvgate(tp); 3314 3315 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3316 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3317 3318 rtl8168_config_eee_mac(tp); 3319 3320 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3321 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3322 3323 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3324 3325 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3326 3327 rtl_pcie_state_l2l3_disable(tp); 3328 3329 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3330 if (rg_saw_cnt > 0) { 3331 u16 sw_cnt_1ms_ini; 3332 3333 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3334 sw_cnt_1ms_ini &= 0x0fff; 3335 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3336 } 3337 3338 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3339 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3340 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3341 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3342 3343 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3344 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3345 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3346 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3347 } 3348 3349 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3350 { 3351 rtl8168ep_stop_cmac(tp); 3352 3353 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3354 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3355 3356 rtl_set_def_aspm_entry_latency(tp); 3357 3358 rtl_reset_packet_filter(tp); 3359 3360 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3361 3362 rtl_disable_rxdvgate(tp); 3363 3364 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3365 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3366 3367 rtl8168_config_eee_mac(tp); 3368 3369 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3370 3371 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3372 3373 rtl_pcie_state_l2l3_disable(tp); 3374 } 3375 3376 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3377 { 3378 static const struct ephy_info e_info_8168ep_3[] = { 3379 { 0x00, 0x0000, 0x0080 }, 3380 { 0x0d, 0x0100, 0x0200 }, 3381 { 0x19, 0x8021, 0x0000 }, 3382 { 0x1e, 0x0000, 0x2000 }, 3383 }; 3384 3385 rtl_ephy_init(tp, e_info_8168ep_3); 3386 3387 rtl_hw_start_8168ep(tp); 3388 3389 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3390 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3391 3392 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3393 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3394 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3395 } 3396 3397 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3398 { 3399 static const struct ephy_info e_info_8117[] = { 3400 { 0x19, 0x0040, 0x1100 }, 3401 { 0x59, 0x0040, 0x1100 }, 3402 }; 3403 int rg_saw_cnt; 3404 3405 rtl8168ep_stop_cmac(tp); 3406 rtl_ephy_init(tp, e_info_8117); 3407 3408 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3409 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3410 3411 rtl_set_def_aspm_entry_latency(tp); 3412 3413 rtl_reset_packet_filter(tp); 3414 3415 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3416 3417 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3418 3419 rtl_disable_rxdvgate(tp); 3420 3421 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3422 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3423 3424 rtl8168_config_eee_mac(tp); 3425 3426 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3427 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3428 3429 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3430 3431 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3432 3433 rtl_pcie_state_l2l3_disable(tp); 3434 3435 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3436 if (rg_saw_cnt > 0) { 3437 u16 sw_cnt_1ms_ini; 3438 3439 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3440 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3441 } 3442 3443 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3444 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3445 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3446 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3447 3448 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3449 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3450 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3451 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3452 3453 /* firmware is for MAC only */ 3454 r8169_apply_firmware(tp); 3455 } 3456 3457 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3458 { 3459 static const struct ephy_info e_info_8102e_1[] = { 3460 { 0x01, 0, 0x6e65 }, 3461 { 0x02, 0, 0x091f }, 3462 { 0x03, 0, 0xc2f9 }, 3463 { 0x06, 0, 0xafb5 }, 3464 { 0x07, 0, 0x0e00 }, 3465 { 0x19, 0, 0xec80 }, 3466 { 0x01, 0, 0x2e65 }, 3467 { 0x01, 0, 0x6e65 } 3468 }; 3469 u8 cfg1; 3470 3471 rtl_set_def_aspm_entry_latency(tp); 3472 3473 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3474 3475 RTL_W8(tp, Config1, 3476 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3477 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3478 3479 cfg1 = RTL_R8(tp, Config1); 3480 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3481 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3482 3483 rtl_ephy_init(tp, e_info_8102e_1); 3484 } 3485 3486 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3487 { 3488 rtl_set_def_aspm_entry_latency(tp); 3489 3490 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3491 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3492 } 3493 3494 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3495 { 3496 rtl_hw_start_8102e_2(tp); 3497 3498 rtl_ephy_write(tp, 0x03, 0xc2f9); 3499 } 3500 3501 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3502 { 3503 static const struct ephy_info e_info_8401[] = { 3504 { 0x01, 0xffff, 0x6fe5 }, 3505 { 0x03, 0xffff, 0x0599 }, 3506 { 0x06, 0xffff, 0xaf25 }, 3507 { 0x07, 0xffff, 0x8e68 }, 3508 }; 3509 3510 rtl_ephy_init(tp, e_info_8401); 3511 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3512 } 3513 3514 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3515 { 3516 static const struct ephy_info e_info_8105e_1[] = { 3517 { 0x07, 0, 0x4000 }, 3518 { 0x19, 0, 0x0200 }, 3519 { 0x19, 0, 0x0020 }, 3520 { 0x1e, 0, 0x2000 }, 3521 { 0x03, 0, 0x0001 }, 3522 { 0x19, 0, 0x0100 }, 3523 { 0x19, 0, 0x0004 }, 3524 { 0x0a, 0, 0x0020 } 3525 }; 3526 3527 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3528 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3529 3530 /* Disable Early Tally Counter */ 3531 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3532 3533 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3534 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3535 3536 rtl_ephy_init(tp, e_info_8105e_1); 3537 3538 rtl_pcie_state_l2l3_disable(tp); 3539 } 3540 3541 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3542 { 3543 rtl_hw_start_8105e_1(tp); 3544 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3545 } 3546 3547 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3548 { 3549 static const struct ephy_info e_info_8402[] = { 3550 { 0x19, 0xffff, 0xff64 }, 3551 { 0x1e, 0, 0x4000 } 3552 }; 3553 3554 rtl_set_def_aspm_entry_latency(tp); 3555 3556 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3557 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3558 3559 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3560 3561 rtl_ephy_init(tp, e_info_8402); 3562 3563 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3564 rtl_reset_packet_filter(tp); 3565 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3566 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3567 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3568 3569 /* disable EEE */ 3570 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3571 3572 rtl_pcie_state_l2l3_disable(tp); 3573 } 3574 3575 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3576 { 3577 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3578 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3579 3580 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3581 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3582 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3583 3584 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3585 rtl_set_aspm_entry_latency(tp, 0x2f); 3586 3587 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3588 3589 /* disable EEE */ 3590 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3591 3592 rtl_pcie_state_l2l3_disable(tp); 3593 } 3594 3595 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3596 { 3597 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3598 } 3599 3600 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3601 { 3602 rtl_pcie_state_l2l3_disable(tp); 3603 3604 RTL_W16(tp, 0x382, 0x221b); 3605 RTL_W8(tp, 0x4500, 0); 3606 RTL_W16(tp, 0x4800, 0); 3607 3608 /* disable UPS */ 3609 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3610 3611 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3612 3613 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3614 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3615 3616 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3617 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3618 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3619 3620 /* disable new tx descriptor format */ 3621 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3622 3623 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3624 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3625 else 3626 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3627 3628 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3629 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3630 else 3631 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3632 3633 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3634 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3635 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3636 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3637 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3638 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3639 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3640 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3641 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3642 3643 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3644 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3645 udelay(1); 3646 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3647 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3648 3649 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3650 3651 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3652 3653 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3654 rtl8125b_config_eee_mac(tp); 3655 else 3656 rtl8125a_config_eee_mac(tp); 3657 3658 rtl_disable_rxdvgate(tp); 3659 } 3660 3661 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3662 { 3663 static const struct ephy_info e_info_8125a_2[] = { 3664 { 0x04, 0xffff, 0xd000 }, 3665 { 0x0a, 0xffff, 0x8653 }, 3666 { 0x23, 0xffff, 0xab66 }, 3667 { 0x20, 0xffff, 0x9455 }, 3668 { 0x21, 0xffff, 0x99ff }, 3669 { 0x29, 0xffff, 0xfe04 }, 3670 3671 { 0x44, 0xffff, 0xd000 }, 3672 { 0x4a, 0xffff, 0x8653 }, 3673 { 0x63, 0xffff, 0xab66 }, 3674 { 0x60, 0xffff, 0x9455 }, 3675 { 0x61, 0xffff, 0x99ff }, 3676 { 0x69, 0xffff, 0xfe04 }, 3677 }; 3678 3679 rtl_set_def_aspm_entry_latency(tp); 3680 rtl_ephy_init(tp, e_info_8125a_2); 3681 rtl_hw_start_8125_common(tp); 3682 } 3683 3684 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3685 { 3686 static const struct ephy_info e_info_8125b[] = { 3687 { 0x0b, 0xffff, 0xa908 }, 3688 { 0x1e, 0xffff, 0x20eb }, 3689 { 0x4b, 0xffff, 0xa908 }, 3690 { 0x5e, 0xffff, 0x20eb }, 3691 { 0x22, 0x0030, 0x0020 }, 3692 { 0x62, 0x0030, 0x0020 }, 3693 }; 3694 3695 rtl_set_def_aspm_entry_latency(tp); 3696 rtl_ephy_init(tp, e_info_8125b); 3697 rtl_hw_start_8125_common(tp); 3698 } 3699 3700 static void rtl_hw_config(struct rtl8169_private *tp) 3701 { 3702 static const rtl_generic_fct hw_configs[] = { 3703 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3704 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3705 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3706 [RTL_GIGA_MAC_VER_10] = NULL, 3707 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3708 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3709 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3710 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3711 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3712 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3713 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3714 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3715 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3716 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3717 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3718 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3719 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3720 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3721 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3722 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3723 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3724 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3725 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3726 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3727 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3728 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3729 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3730 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3731 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3732 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3733 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3734 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3735 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3736 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3737 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3738 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3739 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3740 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3741 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3742 }; 3743 3744 if (hw_configs[tp->mac_version]) 3745 hw_configs[tp->mac_version](tp); 3746 } 3747 3748 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3749 { 3750 int i; 3751 3752 /* disable interrupt coalescing */ 3753 for (i = 0xa00; i < 0xb00; i += 4) 3754 RTL_W32(tp, i, 0); 3755 3756 rtl_hw_config(tp); 3757 } 3758 3759 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3760 { 3761 if (rtl_is_8168evl_up(tp)) 3762 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3763 else 3764 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3765 3766 rtl_hw_config(tp); 3767 3768 /* disable interrupt coalescing */ 3769 RTL_W16(tp, IntrMitigate, 0x0000); 3770 } 3771 3772 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3773 { 3774 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3775 3776 tp->cp_cmd |= PCIMulRW; 3777 3778 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3779 tp->mac_version == RTL_GIGA_MAC_VER_03) 3780 tp->cp_cmd |= EnAnaPLL; 3781 3782 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3783 3784 rtl8169_set_magic_reg(tp); 3785 3786 /* disable interrupt coalescing */ 3787 RTL_W16(tp, IntrMitigate, 0x0000); 3788 } 3789 3790 static void rtl_hw_start(struct rtl8169_private *tp) 3791 { 3792 rtl_unlock_config_regs(tp); 3793 /* disable aspm and clock request before ephy access */ 3794 rtl_hw_aspm_clkreq_enable(tp, false); 3795 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3796 3797 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3798 rtl_hw_start_8169(tp); 3799 else if (rtl_is_8125(tp)) 3800 rtl_hw_start_8125(tp); 3801 else 3802 rtl_hw_start_8168(tp); 3803 3804 rtl_enable_exit_l1(tp); 3805 rtl_hw_aspm_clkreq_enable(tp, true); 3806 rtl_set_rx_max_size(tp); 3807 rtl_set_rx_tx_desc_registers(tp); 3808 rtl_lock_config_regs(tp); 3809 3810 rtl_jumbo_config(tp); 3811 3812 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3813 rtl_pci_commit(tp); 3814 3815 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3816 rtl_init_rxcfg(tp); 3817 rtl_set_tx_config_registers(tp); 3818 rtl_set_rx_config_features(tp, tp->dev->features); 3819 rtl_set_rx_mode(tp->dev); 3820 rtl_irq_enable(tp); 3821 } 3822 3823 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3824 { 3825 struct rtl8169_private *tp = netdev_priv(dev); 3826 3827 dev->mtu = new_mtu; 3828 netdev_update_features(dev); 3829 rtl_jumbo_config(tp); 3830 3831 switch (tp->mac_version) { 3832 case RTL_GIGA_MAC_VER_61: 3833 case RTL_GIGA_MAC_VER_63: 3834 rtl8125_set_eee_txidle_timer(tp); 3835 break; 3836 default: 3837 break; 3838 } 3839 3840 return 0; 3841 } 3842 3843 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3844 { 3845 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3846 3847 desc->opts2 = 0; 3848 /* Force memory writes to complete before releasing descriptor */ 3849 dma_wmb(); 3850 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3851 } 3852 3853 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3854 struct RxDesc *desc) 3855 { 3856 struct device *d = tp_to_dev(tp); 3857 int node = dev_to_node(d); 3858 dma_addr_t mapping; 3859 struct page *data; 3860 3861 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3862 if (!data) 3863 return NULL; 3864 3865 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3866 if (unlikely(dma_mapping_error(d, mapping))) { 3867 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3868 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3869 return NULL; 3870 } 3871 3872 desc->addr = cpu_to_le64(mapping); 3873 rtl8169_mark_to_asic(desc); 3874 3875 return data; 3876 } 3877 3878 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3879 { 3880 int i; 3881 3882 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3883 dma_unmap_page(tp_to_dev(tp), 3884 le64_to_cpu(tp->RxDescArray[i].addr), 3885 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3886 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3887 tp->Rx_databuff[i] = NULL; 3888 tp->RxDescArray[i].addr = 0; 3889 tp->RxDescArray[i].opts1 = 0; 3890 } 3891 } 3892 3893 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3894 { 3895 int i; 3896 3897 for (i = 0; i < NUM_RX_DESC; i++) { 3898 struct page *data; 3899 3900 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3901 if (!data) { 3902 rtl8169_rx_clear(tp); 3903 return -ENOMEM; 3904 } 3905 tp->Rx_databuff[i] = data; 3906 } 3907 3908 /* mark as last descriptor in the ring */ 3909 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3910 3911 return 0; 3912 } 3913 3914 static int rtl8169_init_ring(struct rtl8169_private *tp) 3915 { 3916 rtl8169_init_ring_indexes(tp); 3917 3918 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3919 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3920 3921 return rtl8169_rx_fill(tp); 3922 } 3923 3924 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3925 { 3926 struct ring_info *tx_skb = tp->tx_skb + entry; 3927 struct TxDesc *desc = tp->TxDescArray + entry; 3928 3929 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3930 DMA_TO_DEVICE); 3931 memset(desc, 0, sizeof(*desc)); 3932 memset(tx_skb, 0, sizeof(*tx_skb)); 3933 } 3934 3935 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3936 unsigned int n) 3937 { 3938 unsigned int i; 3939 3940 for (i = 0; i < n; i++) { 3941 unsigned int entry = (start + i) % NUM_TX_DESC; 3942 struct ring_info *tx_skb = tp->tx_skb + entry; 3943 unsigned int len = tx_skb->len; 3944 3945 if (len) { 3946 struct sk_buff *skb = tx_skb->skb; 3947 3948 rtl8169_unmap_tx_skb(tp, entry); 3949 if (skb) 3950 dev_consume_skb_any(skb); 3951 } 3952 } 3953 } 3954 3955 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3956 { 3957 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3958 netdev_reset_queue(tp->dev); 3959 } 3960 3961 static void rtl8169_cleanup(struct rtl8169_private *tp) 3962 { 3963 napi_disable(&tp->napi); 3964 3965 /* Give a racing hard_start_xmit a few cycles to complete. */ 3966 synchronize_net(); 3967 3968 /* Disable interrupts */ 3969 rtl8169_irq_mask_and_ack(tp); 3970 3971 rtl_rx_close(tp); 3972 3973 switch (tp->mac_version) { 3974 case RTL_GIGA_MAC_VER_28: 3975 case RTL_GIGA_MAC_VER_31: 3976 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3977 break; 3978 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3979 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3980 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3981 break; 3982 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3983 rtl_enable_rxdvgate(tp); 3984 fsleep(2000); 3985 break; 3986 default: 3987 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3988 fsleep(100); 3989 break; 3990 } 3991 3992 rtl_hw_reset(tp); 3993 3994 rtl8169_tx_clear(tp); 3995 rtl8169_init_ring_indexes(tp); 3996 } 3997 3998 static void rtl_reset_work(struct rtl8169_private *tp) 3999 { 4000 int i; 4001 4002 netif_stop_queue(tp->dev); 4003 4004 rtl8169_cleanup(tp); 4005 4006 for (i = 0; i < NUM_RX_DESC; i++) 4007 rtl8169_mark_to_asic(tp->RxDescArray + i); 4008 4009 napi_enable(&tp->napi); 4010 rtl_hw_start(tp); 4011 } 4012 4013 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4014 { 4015 struct rtl8169_private *tp = netdev_priv(dev); 4016 4017 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4018 } 4019 4020 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4021 void *addr, unsigned int entry, bool desc_own) 4022 { 4023 struct TxDesc *txd = tp->TxDescArray + entry; 4024 struct device *d = tp_to_dev(tp); 4025 dma_addr_t mapping; 4026 u32 opts1; 4027 int ret; 4028 4029 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4030 ret = dma_mapping_error(d, mapping); 4031 if (unlikely(ret)) { 4032 if (net_ratelimit()) 4033 netdev_err(tp->dev, "Failed to map TX data!\n"); 4034 return ret; 4035 } 4036 4037 txd->addr = cpu_to_le64(mapping); 4038 txd->opts2 = cpu_to_le32(opts[1]); 4039 4040 opts1 = opts[0] | len; 4041 if (entry == NUM_TX_DESC - 1) 4042 opts1 |= RingEnd; 4043 if (desc_own) 4044 opts1 |= DescOwn; 4045 txd->opts1 = cpu_to_le32(opts1); 4046 4047 tp->tx_skb[entry].len = len; 4048 4049 return 0; 4050 } 4051 4052 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4053 const u32 *opts, unsigned int entry) 4054 { 4055 struct skb_shared_info *info = skb_shinfo(skb); 4056 unsigned int cur_frag; 4057 4058 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4059 const skb_frag_t *frag = info->frags + cur_frag; 4060 void *addr = skb_frag_address(frag); 4061 u32 len = skb_frag_size(frag); 4062 4063 entry = (entry + 1) % NUM_TX_DESC; 4064 4065 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4066 goto err_out; 4067 } 4068 4069 return 0; 4070 4071 err_out: 4072 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4073 return -EIO; 4074 } 4075 4076 static bool rtl_skb_is_udp(struct sk_buff *skb) 4077 { 4078 int no = skb_network_offset(skb); 4079 struct ipv6hdr *i6h, _i6h; 4080 struct iphdr *ih, _ih; 4081 4082 switch (vlan_get_protocol(skb)) { 4083 case htons(ETH_P_IP): 4084 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4085 return ih && ih->protocol == IPPROTO_UDP; 4086 case htons(ETH_P_IPV6): 4087 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4088 return i6h && i6h->nexthdr == IPPROTO_UDP; 4089 default: 4090 return false; 4091 } 4092 } 4093 4094 #define RTL_MIN_PATCH_LEN 47 4095 4096 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4097 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4098 struct sk_buff *skb) 4099 { 4100 unsigned int padto = 0, len = skb->len; 4101 4102 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4103 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4104 unsigned int trans_data_len = skb_tail_pointer(skb) - 4105 skb_transport_header(skb); 4106 4107 if (trans_data_len >= offsetof(struct udphdr, len) && 4108 trans_data_len < RTL_MIN_PATCH_LEN) { 4109 u16 dest = ntohs(udp_hdr(skb)->dest); 4110 4111 /* dest is a standard PTP port */ 4112 if (dest == 319 || dest == 320) 4113 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4114 } 4115 4116 if (trans_data_len < sizeof(struct udphdr)) 4117 padto = max_t(unsigned int, padto, 4118 len + sizeof(struct udphdr) - trans_data_len); 4119 } 4120 4121 return padto; 4122 } 4123 4124 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4125 struct sk_buff *skb) 4126 { 4127 unsigned int padto; 4128 4129 padto = rtl8125_quirk_udp_padto(tp, skb); 4130 4131 switch (tp->mac_version) { 4132 case RTL_GIGA_MAC_VER_34: 4133 case RTL_GIGA_MAC_VER_61: 4134 case RTL_GIGA_MAC_VER_63: 4135 padto = max_t(unsigned int, padto, ETH_ZLEN); 4136 break; 4137 default: 4138 break; 4139 } 4140 4141 return padto; 4142 } 4143 4144 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4145 { 4146 u32 mss = skb_shinfo(skb)->gso_size; 4147 4148 if (mss) { 4149 opts[0] |= TD_LSO; 4150 opts[0] |= mss << TD0_MSS_SHIFT; 4151 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4152 const struct iphdr *ip = ip_hdr(skb); 4153 4154 if (ip->protocol == IPPROTO_TCP) 4155 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4156 else if (ip->protocol == IPPROTO_UDP) 4157 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4158 else 4159 WARN_ON_ONCE(1); 4160 } 4161 } 4162 4163 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4164 struct sk_buff *skb, u32 *opts) 4165 { 4166 struct skb_shared_info *shinfo = skb_shinfo(skb); 4167 u32 mss = shinfo->gso_size; 4168 4169 if (mss) { 4170 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4171 opts[0] |= TD1_GTSENV4; 4172 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4173 if (skb_cow_head(skb, 0)) 4174 return false; 4175 4176 tcp_v6_gso_csum_prep(skb); 4177 opts[0] |= TD1_GTSENV6; 4178 } else { 4179 WARN_ON_ONCE(1); 4180 } 4181 4182 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4183 opts[1] |= mss << TD1_MSS_SHIFT; 4184 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4185 u8 ip_protocol; 4186 4187 switch (vlan_get_protocol(skb)) { 4188 case htons(ETH_P_IP): 4189 opts[1] |= TD1_IPv4_CS; 4190 ip_protocol = ip_hdr(skb)->protocol; 4191 break; 4192 4193 case htons(ETH_P_IPV6): 4194 opts[1] |= TD1_IPv6_CS; 4195 ip_protocol = ipv6_hdr(skb)->nexthdr; 4196 break; 4197 4198 default: 4199 ip_protocol = IPPROTO_RAW; 4200 break; 4201 } 4202 4203 if (ip_protocol == IPPROTO_TCP) 4204 opts[1] |= TD1_TCP_CS; 4205 else if (ip_protocol == IPPROTO_UDP) 4206 opts[1] |= TD1_UDP_CS; 4207 else 4208 WARN_ON_ONCE(1); 4209 4210 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4211 } else { 4212 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4213 4214 /* skb_padto would free the skb on error */ 4215 return !__skb_put_padto(skb, padto, false); 4216 } 4217 4218 return true; 4219 } 4220 4221 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4222 { 4223 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4224 } 4225 4226 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4227 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4228 { 4229 switch (tp->mac_version) { 4230 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4231 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4232 return false; 4233 default: 4234 return true; 4235 } 4236 } 4237 4238 static void rtl8169_doorbell(struct rtl8169_private *tp) 4239 { 4240 if (rtl_is_8125(tp)) 4241 RTL_W16(tp, TxPoll_8125, BIT(0)); 4242 else 4243 RTL_W8(tp, TxPoll, NPQ); 4244 } 4245 4246 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4247 struct net_device *dev) 4248 { 4249 struct rtl8169_private *tp = netdev_priv(dev); 4250 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4251 struct TxDesc *txd_first, *txd_last; 4252 bool stop_queue, door_bell; 4253 unsigned int frags; 4254 u32 opts[2]; 4255 4256 if (unlikely(!rtl_tx_slots_avail(tp))) { 4257 if (net_ratelimit()) 4258 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4259 netif_stop_queue(dev); 4260 return NETDEV_TX_BUSY; 4261 } 4262 4263 opts[1] = rtl8169_tx_vlan_tag(skb); 4264 opts[0] = 0; 4265 4266 if (!rtl_chip_supports_csum_v2(tp)) 4267 rtl8169_tso_csum_v1(skb, opts); 4268 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4269 goto err_dma_0; 4270 4271 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4272 entry, false))) 4273 goto err_dma_0; 4274 4275 txd_first = tp->TxDescArray + entry; 4276 4277 frags = skb_shinfo(skb)->nr_frags; 4278 if (frags) { 4279 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4280 goto err_dma_1; 4281 entry = (entry + frags) % NUM_TX_DESC; 4282 } 4283 4284 txd_last = tp->TxDescArray + entry; 4285 txd_last->opts1 |= cpu_to_le32(LastFrag); 4286 tp->tx_skb[entry].skb = skb; 4287 4288 skb_tx_timestamp(skb); 4289 4290 /* Force memory writes to complete before releasing descriptor */ 4291 dma_wmb(); 4292 4293 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4294 4295 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4296 4297 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4298 smp_wmb(); 4299 4300 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4301 4302 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4303 R8169_TX_STOP_THRS, 4304 R8169_TX_START_THRS); 4305 if (door_bell || stop_queue) 4306 rtl8169_doorbell(tp); 4307 4308 return NETDEV_TX_OK; 4309 4310 err_dma_1: 4311 rtl8169_unmap_tx_skb(tp, entry); 4312 err_dma_0: 4313 dev_kfree_skb_any(skb); 4314 dev->stats.tx_dropped++; 4315 return NETDEV_TX_OK; 4316 } 4317 4318 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4319 { 4320 struct skb_shared_info *info = skb_shinfo(skb); 4321 unsigned int nr_frags = info->nr_frags; 4322 4323 if (!nr_frags) 4324 return UINT_MAX; 4325 4326 return skb_frag_size(info->frags + nr_frags - 1); 4327 } 4328 4329 /* Workaround for hw issues with TSO on RTL8168evl */ 4330 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4331 netdev_features_t features) 4332 { 4333 /* IPv4 header has options field */ 4334 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4335 ip_hdrlen(skb) > sizeof(struct iphdr)) 4336 features &= ~NETIF_F_ALL_TSO; 4337 4338 /* IPv4 TCP header has options field */ 4339 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4340 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4341 features &= ~NETIF_F_ALL_TSO; 4342 4343 else if (rtl_last_frag_len(skb) <= 6) 4344 features &= ~NETIF_F_ALL_TSO; 4345 4346 return features; 4347 } 4348 4349 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4350 struct net_device *dev, 4351 netdev_features_t features) 4352 { 4353 struct rtl8169_private *tp = netdev_priv(dev); 4354 4355 if (skb_is_gso(skb)) { 4356 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4357 features = rtl8168evl_fix_tso(skb, features); 4358 4359 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4360 rtl_chip_supports_csum_v2(tp)) 4361 features &= ~NETIF_F_ALL_TSO; 4362 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4363 /* work around hw bug on some chip versions */ 4364 if (skb->len < ETH_ZLEN) 4365 features &= ~NETIF_F_CSUM_MASK; 4366 4367 if (rtl_quirk_packet_padto(tp, skb)) 4368 features &= ~NETIF_F_CSUM_MASK; 4369 4370 if (skb_transport_offset(skb) > TCPHO_MAX && 4371 rtl_chip_supports_csum_v2(tp)) 4372 features &= ~NETIF_F_CSUM_MASK; 4373 } 4374 4375 return vlan_features_check(skb, features); 4376 } 4377 4378 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4379 { 4380 struct rtl8169_private *tp = netdev_priv(dev); 4381 struct pci_dev *pdev = tp->pci_dev; 4382 int pci_status_errs; 4383 u16 pci_cmd; 4384 4385 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4386 4387 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4388 4389 if (net_ratelimit()) 4390 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4391 pci_cmd, pci_status_errs); 4392 4393 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4394 } 4395 4396 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4397 int budget) 4398 { 4399 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4400 struct sk_buff *skb; 4401 4402 dirty_tx = tp->dirty_tx; 4403 4404 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4405 unsigned int entry = dirty_tx % NUM_TX_DESC; 4406 u32 status; 4407 4408 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4409 if (status & DescOwn) 4410 break; 4411 4412 skb = tp->tx_skb[entry].skb; 4413 rtl8169_unmap_tx_skb(tp, entry); 4414 4415 if (skb) { 4416 pkts_compl++; 4417 bytes_compl += skb->len; 4418 napi_consume_skb(skb, budget); 4419 } 4420 dirty_tx++; 4421 } 4422 4423 if (tp->dirty_tx != dirty_tx) { 4424 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4425 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4426 4427 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4428 rtl_tx_slots_avail(tp), 4429 R8169_TX_START_THRS); 4430 /* 4431 * 8168 hack: TxPoll requests are lost when the Tx packets are 4432 * too close. Let's kick an extra TxPoll request when a burst 4433 * of start_xmit activity is detected (if it is not detected, 4434 * it is slow enough). -- FR 4435 * If skb is NULL then we come here again once a tx irq is 4436 * triggered after the last fragment is marked transmitted. 4437 */ 4438 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4439 rtl8169_doorbell(tp); 4440 } 4441 } 4442 4443 static inline int rtl8169_fragmented_frame(u32 status) 4444 { 4445 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4446 } 4447 4448 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4449 { 4450 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4451 4452 if (status == RxProtoTCP || status == RxProtoUDP) 4453 skb->ip_summed = CHECKSUM_UNNECESSARY; 4454 else 4455 skb_checksum_none_assert(skb); 4456 } 4457 4458 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4459 { 4460 struct device *d = tp_to_dev(tp); 4461 int count; 4462 4463 for (count = 0; count < budget; count++, tp->cur_rx++) { 4464 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4465 struct RxDesc *desc = tp->RxDescArray + entry; 4466 struct sk_buff *skb; 4467 const void *rx_buf; 4468 dma_addr_t addr; 4469 u32 status; 4470 4471 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4472 if (status & DescOwn) 4473 break; 4474 4475 /* This barrier is needed to keep us from reading 4476 * any other fields out of the Rx descriptor until 4477 * we know the status of DescOwn 4478 */ 4479 dma_rmb(); 4480 4481 if (unlikely(status & RxRES)) { 4482 if (net_ratelimit()) 4483 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4484 status); 4485 dev->stats.rx_errors++; 4486 if (status & (RxRWT | RxRUNT)) 4487 dev->stats.rx_length_errors++; 4488 if (status & RxCRC) 4489 dev->stats.rx_crc_errors++; 4490 4491 if (!(dev->features & NETIF_F_RXALL)) 4492 goto release_descriptor; 4493 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4494 goto release_descriptor; 4495 } 4496 4497 pkt_size = status & GENMASK(13, 0); 4498 if (likely(!(dev->features & NETIF_F_RXFCS))) 4499 pkt_size -= ETH_FCS_LEN; 4500 4501 /* The driver does not support incoming fragmented frames. 4502 * They are seen as a symptom of over-mtu sized frames. 4503 */ 4504 if (unlikely(rtl8169_fragmented_frame(status))) { 4505 dev->stats.rx_dropped++; 4506 dev->stats.rx_length_errors++; 4507 goto release_descriptor; 4508 } 4509 4510 skb = napi_alloc_skb(&tp->napi, pkt_size); 4511 if (unlikely(!skb)) { 4512 dev->stats.rx_dropped++; 4513 goto release_descriptor; 4514 } 4515 4516 addr = le64_to_cpu(desc->addr); 4517 rx_buf = page_address(tp->Rx_databuff[entry]); 4518 4519 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4520 prefetch(rx_buf); 4521 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4522 skb->tail += pkt_size; 4523 skb->len = pkt_size; 4524 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4525 4526 rtl8169_rx_csum(skb, status); 4527 skb->protocol = eth_type_trans(skb, dev); 4528 4529 rtl8169_rx_vlan_tag(desc, skb); 4530 4531 if (skb->pkt_type == PACKET_MULTICAST) 4532 dev->stats.multicast++; 4533 4534 napi_gro_receive(&tp->napi, skb); 4535 4536 dev_sw_netstats_rx_add(dev, pkt_size); 4537 release_descriptor: 4538 rtl8169_mark_to_asic(desc); 4539 } 4540 4541 return count; 4542 } 4543 4544 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4545 { 4546 struct rtl8169_private *tp = dev_instance; 4547 u32 status = rtl_get_events(tp); 4548 4549 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4550 return IRQ_NONE; 4551 4552 if (unlikely(status & SYSErr)) { 4553 rtl8169_pcierr_interrupt(tp->dev); 4554 goto out; 4555 } 4556 4557 if (status & LinkChg) 4558 phy_mac_interrupt(tp->phydev); 4559 4560 if (unlikely(status & RxFIFOOver && 4561 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4562 netif_stop_queue(tp->dev); 4563 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4564 } 4565 4566 rtl_irq_disable(tp); 4567 napi_schedule(&tp->napi); 4568 out: 4569 rtl_ack_events(tp, status); 4570 4571 return IRQ_HANDLED; 4572 } 4573 4574 static void rtl_task(struct work_struct *work) 4575 { 4576 struct rtl8169_private *tp = 4577 container_of(work, struct rtl8169_private, wk.work); 4578 int ret; 4579 4580 rtnl_lock(); 4581 4582 if (!netif_running(tp->dev) || 4583 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4584 goto out_unlock; 4585 4586 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4587 /* if chip isn't accessible, reset bus to revive it */ 4588 if (RTL_R32(tp, TxConfig) == ~0) { 4589 ret = pci_reset_bus(tp->pci_dev); 4590 if (ret < 0) { 4591 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4592 netif_device_detach(tp->dev); 4593 goto out_unlock; 4594 } 4595 } 4596 4597 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4598 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4599 PCIE_LINK_STATE_L0S); 4600 if (!ret) 4601 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4602 goto reset; 4603 } 4604 4605 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4606 reset: 4607 rtl_reset_work(tp); 4608 netif_wake_queue(tp->dev); 4609 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4610 rtl_reset_work(tp); 4611 } 4612 out_unlock: 4613 rtnl_unlock(); 4614 } 4615 4616 static int rtl8169_poll(struct napi_struct *napi, int budget) 4617 { 4618 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4619 struct net_device *dev = tp->dev; 4620 int work_done; 4621 4622 rtl_tx(dev, tp, budget); 4623 4624 work_done = rtl_rx(dev, tp, budget); 4625 4626 if (work_done < budget && napi_complete_done(napi, work_done)) 4627 rtl_irq_enable(tp); 4628 4629 return work_done; 4630 } 4631 4632 static void r8169_phylink_handler(struct net_device *ndev) 4633 { 4634 struct rtl8169_private *tp = netdev_priv(ndev); 4635 struct device *d = tp_to_dev(tp); 4636 4637 if (netif_carrier_ok(ndev)) { 4638 rtl_link_chg_patch(tp); 4639 pm_request_resume(d); 4640 netif_wake_queue(tp->dev); 4641 } else { 4642 /* In few cases rx is broken after link-down otherwise */ 4643 if (rtl_is_8125(tp)) 4644 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4645 pm_runtime_idle(d); 4646 } 4647 4648 phy_print_status(tp->phydev); 4649 } 4650 4651 static int r8169_phy_connect(struct rtl8169_private *tp) 4652 { 4653 struct phy_device *phydev = tp->phydev; 4654 phy_interface_t phy_mode; 4655 int ret; 4656 4657 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4658 PHY_INTERFACE_MODE_MII; 4659 4660 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4661 phy_mode); 4662 if (ret) 4663 return ret; 4664 4665 if (!tp->supports_gmii) 4666 phy_set_max_speed(phydev, SPEED_100); 4667 4668 phy_attached_info(phydev); 4669 4670 return 0; 4671 } 4672 4673 static void rtl8169_down(struct rtl8169_private *tp) 4674 { 4675 /* Clear all task flags */ 4676 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4677 4678 phy_stop(tp->phydev); 4679 4680 rtl8169_update_counters(tp); 4681 4682 pci_clear_master(tp->pci_dev); 4683 rtl_pci_commit(tp); 4684 4685 rtl8169_cleanup(tp); 4686 rtl_disable_exit_l1(tp); 4687 rtl_prepare_power_down(tp); 4688 4689 if (tp->dash_type != RTL_DASH_NONE) 4690 rtl8168_driver_stop(tp); 4691 } 4692 4693 static void rtl8169_up(struct rtl8169_private *tp) 4694 { 4695 if (tp->dash_type != RTL_DASH_NONE) 4696 rtl8168_driver_start(tp); 4697 4698 pci_set_master(tp->pci_dev); 4699 phy_init_hw(tp->phydev); 4700 phy_resume(tp->phydev); 4701 rtl8169_init_phy(tp); 4702 napi_enable(&tp->napi); 4703 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4704 rtl_reset_work(tp); 4705 4706 phy_start(tp->phydev); 4707 } 4708 4709 static int rtl8169_close(struct net_device *dev) 4710 { 4711 struct rtl8169_private *tp = netdev_priv(dev); 4712 struct pci_dev *pdev = tp->pci_dev; 4713 4714 pm_runtime_get_sync(&pdev->dev); 4715 4716 netif_stop_queue(dev); 4717 rtl8169_down(tp); 4718 rtl8169_rx_clear(tp); 4719 4720 cancel_work(&tp->wk.work); 4721 4722 free_irq(tp->irq, tp); 4723 4724 phy_disconnect(tp->phydev); 4725 4726 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4727 tp->RxPhyAddr); 4728 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4729 tp->TxPhyAddr); 4730 tp->TxDescArray = NULL; 4731 tp->RxDescArray = NULL; 4732 4733 pm_runtime_put_sync(&pdev->dev); 4734 4735 return 0; 4736 } 4737 4738 #ifdef CONFIG_NET_POLL_CONTROLLER 4739 static void rtl8169_netpoll(struct net_device *dev) 4740 { 4741 struct rtl8169_private *tp = netdev_priv(dev); 4742 4743 rtl8169_interrupt(tp->irq, tp); 4744 } 4745 #endif 4746 4747 static int rtl_open(struct net_device *dev) 4748 { 4749 struct rtl8169_private *tp = netdev_priv(dev); 4750 struct pci_dev *pdev = tp->pci_dev; 4751 unsigned long irqflags; 4752 int retval = -ENOMEM; 4753 4754 pm_runtime_get_sync(&pdev->dev); 4755 4756 /* 4757 * Rx and Tx descriptors needs 256 bytes alignment. 4758 * dma_alloc_coherent provides more. 4759 */ 4760 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4761 &tp->TxPhyAddr, GFP_KERNEL); 4762 if (!tp->TxDescArray) 4763 goto out; 4764 4765 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4766 &tp->RxPhyAddr, GFP_KERNEL); 4767 if (!tp->RxDescArray) 4768 goto err_free_tx_0; 4769 4770 retval = rtl8169_init_ring(tp); 4771 if (retval < 0) 4772 goto err_free_rx_1; 4773 4774 rtl_request_firmware(tp); 4775 4776 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4777 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4778 if (retval < 0) 4779 goto err_release_fw_2; 4780 4781 retval = r8169_phy_connect(tp); 4782 if (retval) 4783 goto err_free_irq; 4784 4785 rtl8169_up(tp); 4786 rtl8169_init_counter_offsets(tp); 4787 netif_start_queue(dev); 4788 out: 4789 pm_runtime_put_sync(&pdev->dev); 4790 4791 return retval; 4792 4793 err_free_irq: 4794 free_irq(tp->irq, tp); 4795 err_release_fw_2: 4796 rtl_release_firmware(tp); 4797 rtl8169_rx_clear(tp); 4798 err_free_rx_1: 4799 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4800 tp->RxPhyAddr); 4801 tp->RxDescArray = NULL; 4802 err_free_tx_0: 4803 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4804 tp->TxPhyAddr); 4805 tp->TxDescArray = NULL; 4806 goto out; 4807 } 4808 4809 static void 4810 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4811 { 4812 struct rtl8169_private *tp = netdev_priv(dev); 4813 struct pci_dev *pdev = tp->pci_dev; 4814 struct rtl8169_counters *counters = tp->counters; 4815 4816 pm_runtime_get_noresume(&pdev->dev); 4817 4818 netdev_stats_to_stats64(stats, &dev->stats); 4819 dev_fetch_sw_netstats(stats, dev->tstats); 4820 4821 /* 4822 * Fetch additional counter values missing in stats collected by driver 4823 * from tally counters. 4824 */ 4825 if (pm_runtime_active(&pdev->dev)) 4826 rtl8169_update_counters(tp); 4827 4828 /* 4829 * Subtract values fetched during initalization. 4830 * See rtl8169_init_counter_offsets for a description why we do that. 4831 */ 4832 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4833 le64_to_cpu(tp->tc_offset.tx_errors); 4834 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4835 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4836 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4837 le16_to_cpu(tp->tc_offset.tx_aborted); 4838 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4839 le16_to_cpu(tp->tc_offset.rx_missed); 4840 4841 pm_runtime_put_noidle(&pdev->dev); 4842 } 4843 4844 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4845 { 4846 netif_device_detach(tp->dev); 4847 4848 if (netif_running(tp->dev)) 4849 rtl8169_down(tp); 4850 } 4851 4852 static int rtl8169_runtime_resume(struct device *dev) 4853 { 4854 struct rtl8169_private *tp = dev_get_drvdata(dev); 4855 4856 rtl_rar_set(tp, tp->dev->dev_addr); 4857 __rtl8169_set_wol(tp, tp->saved_wolopts); 4858 4859 if (tp->TxDescArray) 4860 rtl8169_up(tp); 4861 4862 netif_device_attach(tp->dev); 4863 4864 return 0; 4865 } 4866 4867 static int rtl8169_suspend(struct device *device) 4868 { 4869 struct rtl8169_private *tp = dev_get_drvdata(device); 4870 4871 rtnl_lock(); 4872 rtl8169_net_suspend(tp); 4873 if (!device_may_wakeup(tp_to_dev(tp))) 4874 clk_disable_unprepare(tp->clk); 4875 rtnl_unlock(); 4876 4877 return 0; 4878 } 4879 4880 static int rtl8169_resume(struct device *device) 4881 { 4882 struct rtl8169_private *tp = dev_get_drvdata(device); 4883 4884 if (!device_may_wakeup(tp_to_dev(tp))) 4885 clk_prepare_enable(tp->clk); 4886 4887 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4888 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4889 rtl_init_rxcfg(tp); 4890 4891 return rtl8169_runtime_resume(device); 4892 } 4893 4894 static int rtl8169_runtime_suspend(struct device *device) 4895 { 4896 struct rtl8169_private *tp = dev_get_drvdata(device); 4897 4898 if (!tp->TxDescArray) { 4899 netif_device_detach(tp->dev); 4900 return 0; 4901 } 4902 4903 rtnl_lock(); 4904 __rtl8169_set_wol(tp, WAKE_PHY); 4905 rtl8169_net_suspend(tp); 4906 rtnl_unlock(); 4907 4908 return 0; 4909 } 4910 4911 static int rtl8169_runtime_idle(struct device *device) 4912 { 4913 struct rtl8169_private *tp = dev_get_drvdata(device); 4914 4915 if (tp->dash_enabled) 4916 return -EBUSY; 4917 4918 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4919 pm_schedule_suspend(device, 10000); 4920 4921 return -EBUSY; 4922 } 4923 4924 static const struct dev_pm_ops rtl8169_pm_ops = { 4925 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4926 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4927 rtl8169_runtime_idle) 4928 }; 4929 4930 static void rtl_shutdown(struct pci_dev *pdev) 4931 { 4932 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4933 4934 rtnl_lock(); 4935 rtl8169_net_suspend(tp); 4936 rtnl_unlock(); 4937 4938 /* Restore original MAC address */ 4939 rtl_rar_set(tp, tp->dev->perm_addr); 4940 4941 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 4942 pci_wake_from_d3(pdev, tp->saved_wolopts); 4943 pci_set_power_state(pdev, PCI_D3hot); 4944 } 4945 } 4946 4947 static void rtl_remove_one(struct pci_dev *pdev) 4948 { 4949 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4950 4951 if (pci_dev_run_wake(pdev)) 4952 pm_runtime_get_noresume(&pdev->dev); 4953 4954 cancel_work_sync(&tp->wk.work); 4955 4956 unregister_netdev(tp->dev); 4957 4958 if (tp->dash_type != RTL_DASH_NONE) 4959 rtl8168_driver_stop(tp); 4960 4961 rtl_release_firmware(tp); 4962 4963 /* restore original MAC address */ 4964 rtl_rar_set(tp, tp->dev->perm_addr); 4965 } 4966 4967 static const struct net_device_ops rtl_netdev_ops = { 4968 .ndo_open = rtl_open, 4969 .ndo_stop = rtl8169_close, 4970 .ndo_get_stats64 = rtl8169_get_stats64, 4971 .ndo_start_xmit = rtl8169_start_xmit, 4972 .ndo_features_check = rtl8169_features_check, 4973 .ndo_tx_timeout = rtl8169_tx_timeout, 4974 .ndo_validate_addr = eth_validate_addr, 4975 .ndo_change_mtu = rtl8169_change_mtu, 4976 .ndo_fix_features = rtl8169_fix_features, 4977 .ndo_set_features = rtl8169_set_features, 4978 .ndo_set_mac_address = rtl_set_mac_address, 4979 .ndo_eth_ioctl = phy_do_ioctl_running, 4980 .ndo_set_rx_mode = rtl_set_rx_mode, 4981 #ifdef CONFIG_NET_POLL_CONTROLLER 4982 .ndo_poll_controller = rtl8169_netpoll, 4983 #endif 4984 4985 }; 4986 4987 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4988 { 4989 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4990 4991 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4992 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4993 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4994 /* special workaround needed */ 4995 tp->irq_mask |= RxFIFOOver; 4996 else 4997 tp->irq_mask |= RxOverflow; 4998 } 4999 5000 static int rtl_alloc_irq(struct rtl8169_private *tp) 5001 { 5002 unsigned int flags; 5003 5004 switch (tp->mac_version) { 5005 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5006 rtl_unlock_config_regs(tp); 5007 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5008 rtl_lock_config_regs(tp); 5009 fallthrough; 5010 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5011 flags = PCI_IRQ_LEGACY; 5012 break; 5013 default: 5014 flags = PCI_IRQ_ALL_TYPES; 5015 break; 5016 } 5017 5018 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5019 } 5020 5021 static void rtl_read_mac_address(struct rtl8169_private *tp, 5022 u8 mac_addr[ETH_ALEN]) 5023 { 5024 /* Get MAC address */ 5025 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5026 u32 value; 5027 5028 value = rtl_eri_read(tp, 0xe0); 5029 put_unaligned_le32(value, mac_addr); 5030 value = rtl_eri_read(tp, 0xe4); 5031 put_unaligned_le16(value, mac_addr + 4); 5032 } else if (rtl_is_8125(tp)) { 5033 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5034 } 5035 } 5036 5037 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5038 { 5039 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5040 } 5041 5042 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5043 { 5044 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5045 } 5046 5047 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5048 { 5049 struct rtl8169_private *tp = mii_bus->priv; 5050 5051 if (phyaddr > 0) 5052 return -ENODEV; 5053 5054 return rtl_readphy(tp, phyreg); 5055 } 5056 5057 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5058 int phyreg, u16 val) 5059 { 5060 struct rtl8169_private *tp = mii_bus->priv; 5061 5062 if (phyaddr > 0) 5063 return -ENODEV; 5064 5065 rtl_writephy(tp, phyreg, val); 5066 5067 return 0; 5068 } 5069 5070 static int r8169_mdio_register(struct rtl8169_private *tp) 5071 { 5072 struct pci_dev *pdev = tp->pci_dev; 5073 struct mii_bus *new_bus; 5074 int ret; 5075 5076 /* On some boards with this chip version the BIOS is buggy and misses 5077 * to reset the PHY page selector. This results in the PHY ID read 5078 * accessing registers on a different page, returning a more or 5079 * less random value. Fix this by resetting the page selector first. 5080 */ 5081 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5082 tp->mac_version == RTL_GIGA_MAC_VER_26) 5083 r8169_mdio_write(tp, 0x1f, 0); 5084 5085 new_bus = devm_mdiobus_alloc(&pdev->dev); 5086 if (!new_bus) 5087 return -ENOMEM; 5088 5089 new_bus->name = "r8169"; 5090 new_bus->priv = tp; 5091 new_bus->parent = &pdev->dev; 5092 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5093 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5094 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5095 5096 new_bus->read = r8169_mdio_read_reg; 5097 new_bus->write = r8169_mdio_write_reg; 5098 5099 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5100 if (ret) 5101 return ret; 5102 5103 tp->phydev = mdiobus_get_phy(new_bus, 0); 5104 if (!tp->phydev) { 5105 return -ENODEV; 5106 } else if (!tp->phydev->drv) { 5107 /* Most chip versions fail with the genphy driver. 5108 * Therefore ensure that the dedicated PHY driver is loaded. 5109 */ 5110 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5111 tp->phydev->phy_id); 5112 return -EUNATCH; 5113 } 5114 5115 tp->phydev->mac_managed_pm = true; 5116 5117 phy_support_asym_pause(tp->phydev); 5118 5119 /* PHY will be woken up in rtl_open() */ 5120 phy_suspend(tp->phydev); 5121 5122 return 0; 5123 } 5124 5125 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5126 { 5127 rtl_enable_rxdvgate(tp); 5128 5129 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5130 msleep(1); 5131 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5132 5133 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5134 r8168g_wait_ll_share_fifo_ready(tp); 5135 5136 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5137 r8168g_wait_ll_share_fifo_ready(tp); 5138 } 5139 5140 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5141 { 5142 rtl_enable_rxdvgate(tp); 5143 5144 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5145 msleep(1); 5146 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5147 5148 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5149 r8168g_wait_ll_share_fifo_ready(tp); 5150 5151 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5152 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5153 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5154 r8168g_wait_ll_share_fifo_ready(tp); 5155 } 5156 5157 static void rtl_hw_initialize(struct rtl8169_private *tp) 5158 { 5159 switch (tp->mac_version) { 5160 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5161 rtl8168ep_stop_cmac(tp); 5162 fallthrough; 5163 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5164 rtl_hw_init_8168g(tp); 5165 break; 5166 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5167 rtl_hw_init_8125(tp); 5168 break; 5169 default: 5170 break; 5171 } 5172 } 5173 5174 static int rtl_jumbo_max(struct rtl8169_private *tp) 5175 { 5176 /* Non-GBit versions don't support jumbo frames */ 5177 if (!tp->supports_gmii) 5178 return 0; 5179 5180 switch (tp->mac_version) { 5181 /* RTL8169 */ 5182 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5183 return JUMBO_7K; 5184 /* RTL8168b */ 5185 case RTL_GIGA_MAC_VER_11: 5186 case RTL_GIGA_MAC_VER_17: 5187 return JUMBO_4K; 5188 /* RTL8168c */ 5189 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5190 return JUMBO_6K; 5191 default: 5192 return JUMBO_9K; 5193 } 5194 } 5195 5196 static void rtl_init_mac_address(struct rtl8169_private *tp) 5197 { 5198 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5199 struct net_device *dev = tp->dev; 5200 int rc; 5201 5202 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5203 if (!rc) 5204 goto done; 5205 5206 rtl_read_mac_address(tp, mac_addr); 5207 if (is_valid_ether_addr(mac_addr)) 5208 goto done; 5209 5210 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5211 if (is_valid_ether_addr(mac_addr)) 5212 goto done; 5213 5214 eth_random_addr(mac_addr); 5215 dev->addr_assign_type = NET_ADDR_RANDOM; 5216 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5217 done: 5218 eth_hw_addr_set(dev, mac_addr); 5219 rtl_rar_set(tp, mac_addr); 5220 } 5221 5222 /* register is set if system vendor successfully tested ASPM 1.2 */ 5223 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5224 { 5225 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5226 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5227 return true; 5228 5229 return false; 5230 } 5231 5232 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5233 { 5234 struct rtl8169_private *tp; 5235 int jumbo_max, region, rc; 5236 enum mac_version chipset; 5237 struct net_device *dev; 5238 u32 txconfig; 5239 u16 xid; 5240 5241 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5242 if (!dev) 5243 return -ENOMEM; 5244 5245 SET_NETDEV_DEV(dev, &pdev->dev); 5246 dev->netdev_ops = &rtl_netdev_ops; 5247 tp = netdev_priv(dev); 5248 tp->dev = dev; 5249 tp->pci_dev = pdev; 5250 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5251 tp->eee_adv = -1; 5252 tp->ocp_base = OCP_STD_PHY_BASE; 5253 5254 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5255 raw_spin_lock_init(&tp->config25_lock); 5256 raw_spin_lock_init(&tp->mac_ocp_lock); 5257 5258 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5259 struct pcpu_sw_netstats); 5260 if (!dev->tstats) 5261 return -ENOMEM; 5262 5263 /* Get the *optional* external "ether_clk" used on some boards */ 5264 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5265 if (IS_ERR(tp->clk)) 5266 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5267 5268 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5269 rc = pcim_enable_device(pdev); 5270 if (rc < 0) 5271 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5272 5273 if (pcim_set_mwi(pdev) < 0) 5274 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5275 5276 /* use first MMIO region */ 5277 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5278 if (region < 0) 5279 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5280 5281 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5282 if (rc < 0) 5283 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5284 5285 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5286 5287 txconfig = RTL_R32(tp, TxConfig); 5288 if (txconfig == ~0U) 5289 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5290 5291 xid = (txconfig >> 20) & 0xfcf; 5292 5293 /* Identify chip attached to board */ 5294 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5295 if (chipset == RTL_GIGA_MAC_NONE) 5296 return dev_err_probe(&pdev->dev, -ENODEV, 5297 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5298 xid); 5299 tp->mac_version = chipset; 5300 5301 /* Disable ASPM L1 as that cause random device stop working 5302 * problems as well as full system hangs for some PCIe devices users. 5303 */ 5304 if (rtl_aspm_is_safe(tp)) 5305 rc = 0; 5306 else 5307 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5308 tp->aspm_manageable = !rc; 5309 5310 tp->dash_type = rtl_get_dash_type(tp); 5311 tp->dash_enabled = rtl_dash_is_enabled(tp); 5312 5313 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5314 5315 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5316 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5317 dev->features |= NETIF_F_HIGHDMA; 5318 5319 rtl_init_rxcfg(tp); 5320 5321 rtl8169_irq_mask_and_ack(tp); 5322 5323 rtl_hw_initialize(tp); 5324 5325 rtl_hw_reset(tp); 5326 5327 rc = rtl_alloc_irq(tp); 5328 if (rc < 0) 5329 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5330 5331 tp->irq = pci_irq_vector(pdev, 0); 5332 5333 INIT_WORK(&tp->wk.work, rtl_task); 5334 5335 rtl_init_mac_address(tp); 5336 5337 dev->ethtool_ops = &rtl8169_ethtool_ops; 5338 5339 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5340 5341 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5342 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5343 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5344 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5345 5346 /* 5347 * Pretend we are using VLANs; This bypasses a nasty bug where 5348 * Interrupts stop flowing on high load on 8110SCd controllers. 5349 */ 5350 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5351 /* Disallow toggling */ 5352 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5353 5354 if (rtl_chip_supports_csum_v2(tp)) 5355 dev->hw_features |= NETIF_F_IPV6_CSUM; 5356 5357 dev->features |= dev->hw_features; 5358 5359 /* There has been a number of reports that using SG/TSO results in 5360 * tx timeouts. However for a lot of people SG/TSO works fine. 5361 * Therefore disable both features by default, but allow users to 5362 * enable them. Use at own risk! 5363 */ 5364 if (rtl_chip_supports_csum_v2(tp)) { 5365 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5366 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5367 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5368 } else { 5369 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5370 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5371 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5372 } 5373 5374 dev->hw_features |= NETIF_F_RXALL; 5375 dev->hw_features |= NETIF_F_RXFCS; 5376 5377 netdev_sw_irq_coalesce_default_on(dev); 5378 5379 /* configure chip for default features */ 5380 rtl8169_set_features(dev, dev->features); 5381 5382 if (!tp->dash_enabled) { 5383 rtl_set_d3_pll_down(tp, true); 5384 } else { 5385 rtl_set_d3_pll_down(tp, false); 5386 dev->wol_enabled = 1; 5387 } 5388 5389 jumbo_max = rtl_jumbo_max(tp); 5390 if (jumbo_max) 5391 dev->max_mtu = jumbo_max; 5392 5393 rtl_set_irq_mask(tp); 5394 5395 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5396 5397 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5398 &tp->counters_phys_addr, 5399 GFP_KERNEL); 5400 if (!tp->counters) 5401 return -ENOMEM; 5402 5403 pci_set_drvdata(pdev, tp); 5404 5405 rc = r8169_mdio_register(tp); 5406 if (rc) 5407 return rc; 5408 5409 rc = register_netdev(dev); 5410 if (rc) 5411 return rc; 5412 5413 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5414 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5415 5416 if (jumbo_max) 5417 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5418 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5419 "ok" : "ko"); 5420 5421 if (tp->dash_type != RTL_DASH_NONE) { 5422 netdev_info(dev, "DASH %s\n", 5423 tp->dash_enabled ? "enabled" : "disabled"); 5424 rtl8168_driver_start(tp); 5425 } 5426 5427 if (pci_dev_run_wake(pdev)) 5428 pm_runtime_put_sync(&pdev->dev); 5429 5430 return 0; 5431 } 5432 5433 static struct pci_driver rtl8169_pci_driver = { 5434 .name = KBUILD_MODNAME, 5435 .id_table = rtl8169_pci_tbl, 5436 .probe = rtl_init_one, 5437 .remove = rtl_remove_one, 5438 .shutdown = rtl_shutdown, 5439 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5440 }; 5441 5442 module_pci_driver(rtl8169_pci_driver); 5443