1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a8fe65b8SJeff Kirsher /* Linux header file for the ATP pocket ethernet adapter. */
3a8fe65b8SJeff Kirsher /* v1.09 8/9/2000 becker@scyld.com. */
4a8fe65b8SJeff Kirsher
5a8fe65b8SJeff Kirsher #include <linux/if_ether.h>
6a8fe65b8SJeff Kirsher #include <linux/types.h>
7a8fe65b8SJeff Kirsher
8a8fe65b8SJeff Kirsher /* The header prepended to received packets. */
9a8fe65b8SJeff Kirsher struct rx_header {
10a8fe65b8SJeff Kirsher ushort pad; /* Pad. */
11a8fe65b8SJeff Kirsher ushort rx_count;
12a8fe65b8SJeff Kirsher ushort rx_status; /* Unknown bit assignments :-<. */
13a8fe65b8SJeff Kirsher ushort cur_addr; /* Apparently the current buffer address(?) */
14a8fe65b8SJeff Kirsher };
15a8fe65b8SJeff Kirsher
16a8fe65b8SJeff Kirsher #define PAR_DATA 0
17a8fe65b8SJeff Kirsher #define PAR_STATUS 1
18a8fe65b8SJeff Kirsher #define PAR_CONTROL 2
19a8fe65b8SJeff Kirsher
20a8fe65b8SJeff Kirsher #define Ctrl_LNibRead 0x08 /* LP_PSELECP */
21a8fe65b8SJeff Kirsher #define Ctrl_HNibRead 0
22a8fe65b8SJeff Kirsher #define Ctrl_LNibWrite 0x08 /* LP_PSELECP */
23a8fe65b8SJeff Kirsher #define Ctrl_HNibWrite 0
24a8fe65b8SJeff Kirsher #define Ctrl_SelData 0x04 /* LP_PINITP */
25a8fe65b8SJeff Kirsher #define Ctrl_IRQEN 0x10 /* LP_PINTEN */
26a8fe65b8SJeff Kirsher
27a8fe65b8SJeff Kirsher #define EOW 0xE0
28a8fe65b8SJeff Kirsher #define EOC 0xE0
29a8fe65b8SJeff Kirsher #define WrAddr 0x40 /* Set address of EPLC read, write register. */
30a8fe65b8SJeff Kirsher #define RdAddr 0xC0
31a8fe65b8SJeff Kirsher #define HNib 0x10
32a8fe65b8SJeff Kirsher
337aef06dbSRoberto Medina enum page0_regs {
347aef06dbSRoberto Medina /* The first six registers hold
357aef06dbSRoberto Medina * the ethernet physical station address.
367aef06dbSRoberto Medina */
37a8fe65b8SJeff Kirsher PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
38a8fe65b8SJeff Kirsher TxCNT0 = 6, TxCNT1 = 7, /* The transmit byte count. */
39a8fe65b8SJeff Kirsher TxSTAT = 8, RxSTAT = 9, /* Tx and Rx status. */
40a8fe65b8SJeff Kirsher ISR = 10, IMR = 11, /* Interrupt status and mask. */
41a8fe65b8SJeff Kirsher CMR1 = 12, /* Command register 1. */
42a8fe65b8SJeff Kirsher CMR2 = 13, /* Command register 2. */
43a8fe65b8SJeff Kirsher MODSEL = 14, /* Mode select register. */
44a8fe65b8SJeff Kirsher MAR = 14, /* Memory address register (?). */
457aef06dbSRoberto Medina CMR2_h = 0x1d,
467aef06dbSRoberto Medina };
47a8fe65b8SJeff Kirsher
487aef06dbSRoberto Medina enum eepage_regs {
497aef06dbSRoberto Medina PROM_CMD = 6,
507aef06dbSRoberto Medina PROM_DATA = 7 /* Note that PROM_CMD is in the "high" bits. */
517aef06dbSRoberto Medina };
52a8fe65b8SJeff Kirsher
53a8fe65b8SJeff Kirsher #define ISR_TxOK 0x01
54a8fe65b8SJeff Kirsher #define ISR_RxOK 0x04
55a8fe65b8SJeff Kirsher #define ISR_TxErr 0x02
56a8fe65b8SJeff Kirsher #define ISRh_RxErr 0x11 /* ISR, high nibble */
57a8fe65b8SJeff Kirsher
58a8fe65b8SJeff Kirsher #define CMR1h_MUX 0x08 /* Select printer multiplexor on 8012. */
59a8fe65b8SJeff Kirsher #define CMR1h_RESET 0x04 /* Reset. */
60a8fe65b8SJeff Kirsher #define CMR1h_RxENABLE 0x02 /* Rx unit enable. */
61a8fe65b8SJeff Kirsher #define CMR1h_TxENABLE 0x01 /* Tx unit enable. */
62a8fe65b8SJeff Kirsher #define CMR1h_TxRxOFF 0x00
63a8fe65b8SJeff Kirsher #define CMR1_ReXmit 0x08 /* Trigger a retransmit. */
64a8fe65b8SJeff Kirsher #define CMR1_Xmit 0x04 /* Trigger a transmit. */
65a8fe65b8SJeff Kirsher #define CMR1_IRQ 0x02 /* Interrupt active. */
66a8fe65b8SJeff Kirsher #define CMR1_BufEnb 0x01 /* Enable the buffer(?). */
67a8fe65b8SJeff Kirsher #define CMR1_NextPkt 0x01 /* Enable the buffer(?). */
68a8fe65b8SJeff Kirsher
69a8fe65b8SJeff Kirsher #define CMR2_NULL 8
70a8fe65b8SJeff Kirsher #define CMR2_IRQOUT 9
71a8fe65b8SJeff Kirsher #define CMR2_RAMTEST 10
72a8fe65b8SJeff Kirsher #define CMR2_EEPROM 12 /* Set to page 1, for reading the EEPROM. */
73a8fe65b8SJeff Kirsher
74a8fe65b8SJeff Kirsher #define CMR2h_OFF 0 /* No accept mode. */
75a8fe65b8SJeff Kirsher #define CMR2h_Physical 1 /* Accept a physical address match only. */
76a8fe65b8SJeff Kirsher #define CMR2h_Normal 2 /* Accept physical and broadcast address. */
77a8fe65b8SJeff Kirsher #define CMR2h_PROMISC 3 /* Promiscuous mode. */
78a8fe65b8SJeff Kirsher
797aef06dbSRoberto Medina /* An inline function used below: it differs from inb() by explicitly
807aef06dbSRoberto Medina * return an unsigned char, saving a truncation.
817aef06dbSRoberto Medina */
inbyte(unsigned short port)82a8fe65b8SJeff Kirsher static inline unsigned char inbyte(unsigned short port)
83a8fe65b8SJeff Kirsher {
84a8fe65b8SJeff Kirsher unsigned char _v;
857aef06dbSRoberto Medina
86a8fe65b8SJeff Kirsher __asm__ __volatile__ ("inb %w1,%b0" : "=a" (_v) : "d" (port));
87a8fe65b8SJeff Kirsher return _v;
88a8fe65b8SJeff Kirsher }
89a8fe65b8SJeff Kirsher
90a8fe65b8SJeff Kirsher /* Read register OFFSET.
917aef06dbSRoberto Medina * This command should always be terminated with read_end().
927aef06dbSRoberto Medina */
read_nibble(short port,unsigned char offset)93a8fe65b8SJeff Kirsher static inline unsigned char read_nibble(short port, unsigned char offset)
94a8fe65b8SJeff Kirsher {
95a8fe65b8SJeff Kirsher unsigned char retval;
967aef06dbSRoberto Medina
97a8fe65b8SJeff Kirsher outb(EOC+offset, port + PAR_DATA);
98a8fe65b8SJeff Kirsher outb(RdAddr+offset, port + PAR_DATA);
99a8fe65b8SJeff Kirsher inbyte(port + PAR_STATUS); /* Settling time delay */
100a8fe65b8SJeff Kirsher retval = inbyte(port + PAR_STATUS);
101a8fe65b8SJeff Kirsher outb(EOC+offset, port + PAR_DATA);
102a8fe65b8SJeff Kirsher
103a8fe65b8SJeff Kirsher return retval;
104a8fe65b8SJeff Kirsher }
105a8fe65b8SJeff Kirsher
106a8fe65b8SJeff Kirsher /* Functions for bulk data read. The interrupt line is always disabled. */
107a8fe65b8SJeff Kirsher /* Get a byte using read mode 0, reading data from the control lines. */
read_byte_mode0(short ioaddr)108a8fe65b8SJeff Kirsher static inline unsigned char read_byte_mode0(short ioaddr)
109a8fe65b8SJeff Kirsher {
110a8fe65b8SJeff Kirsher unsigned char low_nib;
111a8fe65b8SJeff Kirsher
112a8fe65b8SJeff Kirsher outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
113a8fe65b8SJeff Kirsher inbyte(ioaddr + PAR_STATUS);
114a8fe65b8SJeff Kirsher low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
115a8fe65b8SJeff Kirsher outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
116a8fe65b8SJeff Kirsher inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
117a8fe65b8SJeff Kirsher inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
118a8fe65b8SJeff Kirsher return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
119a8fe65b8SJeff Kirsher }
120a8fe65b8SJeff Kirsher
121a8fe65b8SJeff Kirsher /* The same as read_byte_mode0(), but does multiple inb()s for stability. */
read_byte_mode2(short ioaddr)122a8fe65b8SJeff Kirsher static inline unsigned char read_byte_mode2(short ioaddr)
123a8fe65b8SJeff Kirsher {
124a8fe65b8SJeff Kirsher unsigned char low_nib;
125a8fe65b8SJeff Kirsher
126a8fe65b8SJeff Kirsher outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
127a8fe65b8SJeff Kirsher inbyte(ioaddr + PAR_STATUS);
128a8fe65b8SJeff Kirsher low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
129a8fe65b8SJeff Kirsher outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
130a8fe65b8SJeff Kirsher inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
131a8fe65b8SJeff Kirsher return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
132a8fe65b8SJeff Kirsher }
133a8fe65b8SJeff Kirsher
134a8fe65b8SJeff Kirsher /* Read a byte through the data register. */
read_byte_mode4(short ioaddr)135a8fe65b8SJeff Kirsher static inline unsigned char read_byte_mode4(short ioaddr)
136a8fe65b8SJeff Kirsher {
137a8fe65b8SJeff Kirsher unsigned char low_nib;
138a8fe65b8SJeff Kirsher
139a8fe65b8SJeff Kirsher outb(RdAddr | MAR, ioaddr + PAR_DATA);
140a8fe65b8SJeff Kirsher low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
141a8fe65b8SJeff Kirsher outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
142a8fe65b8SJeff Kirsher return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
143a8fe65b8SJeff Kirsher }
144a8fe65b8SJeff Kirsher
145a8fe65b8SJeff Kirsher /* Read a byte through the data register, double reading to allow settling. */
read_byte_mode6(short ioaddr)146a8fe65b8SJeff Kirsher static inline unsigned char read_byte_mode6(short ioaddr)
147a8fe65b8SJeff Kirsher {
148a8fe65b8SJeff Kirsher unsigned char low_nib;
149a8fe65b8SJeff Kirsher
150a8fe65b8SJeff Kirsher outb(RdAddr | MAR, ioaddr + PAR_DATA);
151a8fe65b8SJeff Kirsher inbyte(ioaddr + PAR_STATUS);
152a8fe65b8SJeff Kirsher low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
153a8fe65b8SJeff Kirsher outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
154a8fe65b8SJeff Kirsher inbyte(ioaddr + PAR_STATUS);
155a8fe65b8SJeff Kirsher return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
156a8fe65b8SJeff Kirsher }
157a8fe65b8SJeff Kirsher
158a8fe65b8SJeff Kirsher static inline void
write_reg(short port,unsigned char reg,unsigned char value)159a8fe65b8SJeff Kirsher write_reg(short port, unsigned char reg, unsigned char value)
160a8fe65b8SJeff Kirsher {
161a8fe65b8SJeff Kirsher unsigned char outval;
1627aef06dbSRoberto Medina
163a8fe65b8SJeff Kirsher outb(EOC | reg, port + PAR_DATA);
164a8fe65b8SJeff Kirsher outval = WrAddr | reg;
165a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
166a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA); /* Double write for PS/2. */
167a8fe65b8SJeff Kirsher
168a8fe65b8SJeff Kirsher outval &= 0xf0;
169a8fe65b8SJeff Kirsher outval |= value;
170a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
171a8fe65b8SJeff Kirsher outval &= 0x1f;
172a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
173a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
174a8fe65b8SJeff Kirsher
175a8fe65b8SJeff Kirsher outb(EOC | outval, port + PAR_DATA);
176a8fe65b8SJeff Kirsher }
177a8fe65b8SJeff Kirsher
178a8fe65b8SJeff Kirsher static inline void
write_reg_high(short port,unsigned char reg,unsigned char value)179a8fe65b8SJeff Kirsher write_reg_high(short port, unsigned char reg, unsigned char value)
180a8fe65b8SJeff Kirsher {
181a8fe65b8SJeff Kirsher unsigned char outval = EOC | HNib | reg;
182a8fe65b8SJeff Kirsher
183a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
184a8fe65b8SJeff Kirsher outval &= WrAddr | HNib | 0x0f;
185a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
186a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA); /* Double write for PS/2. */
187a8fe65b8SJeff Kirsher
188a8fe65b8SJeff Kirsher outval = WrAddr | HNib | value;
189a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
190a8fe65b8SJeff Kirsher outval &= HNib | 0x0f; /* HNib | value */
191a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
192a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
193a8fe65b8SJeff Kirsher
194a8fe65b8SJeff Kirsher outb(EOC | HNib | outval, port + PAR_DATA);
195a8fe65b8SJeff Kirsher }
196a8fe65b8SJeff Kirsher
197a8fe65b8SJeff Kirsher /* Write a byte out using nibble mode. The low nibble is written first. */
198a8fe65b8SJeff Kirsher static inline void
write_reg_byte(short port,unsigned char reg,unsigned char value)199a8fe65b8SJeff Kirsher write_reg_byte(short port, unsigned char reg, unsigned char value)
200a8fe65b8SJeff Kirsher {
201a8fe65b8SJeff Kirsher unsigned char outval;
2027aef06dbSRoberto Medina
203a8fe65b8SJeff Kirsher outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */
204a8fe65b8SJeff Kirsher outval = WrAddr | reg;
205a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA);
206a8fe65b8SJeff Kirsher outb(outval, port + PAR_DATA); /* Double write for PS/2. */
207a8fe65b8SJeff Kirsher
208a8fe65b8SJeff Kirsher outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);
209a8fe65b8SJeff Kirsher outb(value & 0x0f, port + PAR_DATA);
210a8fe65b8SJeff Kirsher value >>= 4;
211a8fe65b8SJeff Kirsher outb(value, port + PAR_DATA);
212a8fe65b8SJeff Kirsher outb(0x10 | value, port + PAR_DATA);
213a8fe65b8SJeff Kirsher outb(0x10 | value, port + PAR_DATA);
214a8fe65b8SJeff Kirsher
215a8fe65b8SJeff Kirsher outb(EOC | value, port + PAR_DATA); /* Reset the address register. */
216a8fe65b8SJeff Kirsher }
217a8fe65b8SJeff Kirsher
2187aef06dbSRoberto Medina /* Bulk data writes to the packet buffer. The interrupt line remains enabled.
219a8fe65b8SJeff Kirsher * The first, faster method uses only the dataport (data modes 0, 2 & 4).
220a8fe65b8SJeff Kirsher * The second (backup) method uses data and control regs (modes 1, 3 & 5).
221a8fe65b8SJeff Kirsher * It should only be needed when there is skew between the individual data
222a8fe65b8SJeff Kirsher * lines.
223a8fe65b8SJeff Kirsher */
write_byte_mode0(short ioaddr,unsigned char value)224a8fe65b8SJeff Kirsher static inline void write_byte_mode0(short ioaddr, unsigned char value)
225a8fe65b8SJeff Kirsher {
226a8fe65b8SJeff Kirsher outb(value & 0x0f, ioaddr + PAR_DATA);
227a8fe65b8SJeff Kirsher outb((value>>4) | 0x10, ioaddr + PAR_DATA);
228a8fe65b8SJeff Kirsher }
229a8fe65b8SJeff Kirsher
write_byte_mode1(short ioaddr,unsigned char value)230a8fe65b8SJeff Kirsher static inline void write_byte_mode1(short ioaddr, unsigned char value)
231a8fe65b8SJeff Kirsher {
232a8fe65b8SJeff Kirsher outb(value & 0x0f, ioaddr + PAR_DATA);
233a8fe65b8SJeff Kirsher outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL);
234a8fe65b8SJeff Kirsher outb((value>>4) | 0x10, ioaddr + PAR_DATA);
235a8fe65b8SJeff Kirsher outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL);
236a8fe65b8SJeff Kirsher }
237a8fe65b8SJeff Kirsher
238a8fe65b8SJeff Kirsher /* Write 16bit VALUE to the packet buffer: the same as above just doubled. */
write_word_mode0(short ioaddr,unsigned short value)239a8fe65b8SJeff Kirsher static inline void write_word_mode0(short ioaddr, unsigned short value)
240a8fe65b8SJeff Kirsher {
241a8fe65b8SJeff Kirsher outb(value & 0x0f, ioaddr + PAR_DATA);
242a8fe65b8SJeff Kirsher value >>= 4;
243a8fe65b8SJeff Kirsher outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
244a8fe65b8SJeff Kirsher value >>= 4;
245a8fe65b8SJeff Kirsher outb(value & 0x0f, ioaddr + PAR_DATA);
246a8fe65b8SJeff Kirsher value >>= 4;
247a8fe65b8SJeff Kirsher outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
248a8fe65b8SJeff Kirsher }
249a8fe65b8SJeff Kirsher
250a8fe65b8SJeff Kirsher /* EEPROM_Ctrl bits. */
251a8fe65b8SJeff Kirsher #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
252a8fe65b8SJeff Kirsher #define EE_CS 0x02 /* EEPROM chip select. */
253a8fe65b8SJeff Kirsher #define EE_CLK_HIGH 0x12
254a8fe65b8SJeff Kirsher #define EE_CLK_LOW 0x16
255a8fe65b8SJeff Kirsher #define EE_DATA_WRITE 0x01 /* EEPROM chip data in. */
256a8fe65b8SJeff Kirsher #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
257a8fe65b8SJeff Kirsher
258a8fe65b8SJeff Kirsher /* The EEPROM commands include the alway-set leading bit. */
259a8fe65b8SJeff Kirsher #define EE_WRITE_CMD(offset) (((5 << 6) + (offset)) << 17)
260a8fe65b8SJeff Kirsher #define EE_READ(offset) (((6 << 6) + (offset)) << 17)
261a8fe65b8SJeff Kirsher #define EE_ERASE(offset) (((7 << 6) + (offset)) << 17)
262a8fe65b8SJeff Kirsher #define EE_CMD_SIZE 27 /* The command+address+data size. */
263