1 /* 2 3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux. 4 5 Maintained by Jeff Garzik <jgarzik@pobox.com> 6 Copyright 2000-2002 Jeff Garzik 7 8 Much code comes from Donald Becker's rtl8139.c driver, 9 versions 1.13 and older. This driver was originally based 10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13: 11 12 -----<snip>----- 13 14 Written 1997-2001 by Donald Becker. 15 This software may be used and distributed according to the 16 terms of the GNU General Public License (GPL), incorporated 17 herein by reference. Drivers based on or derived from this 18 code fall under the GPL and must retain the authorship, 19 copyright and license notice. This file is not a complete 20 program and may only be used when the entire operating 21 system is licensed under the GPL. 22 23 This driver is for boards based on the RTL8129 and RTL8139 24 PCI ethernet chips. 25 26 The author may be reached as becker@scyld.com, or C/O Scyld 27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis 28 MD 21403 29 30 Support and updates available at 31 http://www.scyld.com/network/rtl8139.html 32 33 Twister-tuning table provided by Kinston 34 <shangh@realtek.com.tw>. 35 36 -----<snip>----- 37 38 This software may be used and distributed according to the terms 39 of the GNU General Public License, incorporated herein by reference. 40 41 Contributors: 42 43 Donald Becker - he wrote the original driver, kudos to him! 44 (but please don't e-mail him for support, this isn't his driver) 45 46 Tigran Aivazian - bug fixes, skbuff free cleanup 47 48 Martin Mares - suggestions for PCI cleanup 49 50 David S. Miller - PCI DMA and softnet updates 51 52 Ernst Gill - fixes ported from BSD driver 53 54 Daniel Kobras - identified specific locations of 55 posted MMIO write bugginess 56 57 Gerard Sharp - bug fix, testing and feedback 58 59 David Ford - Rx ring wrap fix 60 61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me 62 to find and fix a crucial bug on older chipsets. 63 64 Donald Becker/Chris Butterworth/Marcus Westergren - 65 Noticed various Rx packet size-related buglets. 66 67 Santiago Garcia Mantinan - testing and feedback 68 69 Jens David - 2.2.x kernel backports 70 71 Martin Dennett - incredibly helpful insight on undocumented 72 features of the 8139 chips 73 74 Jean-Jacques Michel - bug fix 75 76 Tobias Ringström - Rx interrupt status checking suggestion 77 78 Andrew Morton - Clear blocked signals, avoid 79 buffer overrun setting current->comm. 80 81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls 82 83 Robert Kuebel - Save kernel thread from dying on any signal. 84 85 Submitting bug reports: 86 87 "rtl8139-diag -mmmaaavvveefN" output 88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log 89 90 */ 91 92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 93 94 #define DRV_NAME "8139too" 95 #define DRV_VERSION "0.9.28" 96 97 98 #include <linux/module.h> 99 #include <linux/kernel.h> 100 #include <linux/compiler.h> 101 #include <linux/pci.h> 102 #include <linux/init.h> 103 #include <linux/interrupt.h> 104 #include <linux/netdevice.h> 105 #include <linux/etherdevice.h> 106 #include <linux/rtnetlink.h> 107 #include <linux/delay.h> 108 #include <linux/ethtool.h> 109 #include <linux/mii.h> 110 #include <linux/completion.h> 111 #include <linux/crc32.h> 112 #include <linux/io.h> 113 #include <linux/uaccess.h> 114 #include <linux/gfp.h> 115 #include <linux/if_vlan.h> 116 #include <asm/irq.h> 117 118 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION 119 120 /* Default Message level */ 121 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 122 NETIF_MSG_PROBE | \ 123 NETIF_MSG_LINK) 124 125 126 /* define to 1, 2 or 3 to enable copious debugging info */ 127 #define RTL8139_DEBUG 0 128 129 /* define to 1 to disable lightweight runtime debugging checks */ 130 #undef RTL8139_NDEBUG 131 132 133 #ifdef RTL8139_NDEBUG 134 # define assert(expr) do {} while (0) 135 #else 136 # define assert(expr) \ 137 if (unlikely(!(expr))) { \ 138 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \ 139 #expr, __FILE__, __func__, __LINE__); \ 140 } 141 #endif 142 143 144 /* A few user-configurable values. */ 145 /* media options */ 146 #define MAX_UNITS 8 147 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 148 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 149 150 /* Whether to use MMIO or PIO. Default to MMIO. */ 151 #ifdef CONFIG_8139TOO_PIO 152 static bool use_io = true; 153 #else 154 static bool use_io = false; 155 #endif 156 157 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 158 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 159 static int multicast_filter_limit = 32; 160 161 /* bitmapped message enable number */ 162 static int debug = -1; 163 164 /* 165 * Receive ring size 166 * Warning: 64K ring has hardware issues and may lock up. 167 */ 168 #if defined(CONFIG_SH_DREAMCAST) 169 #define RX_BUF_IDX 0 /* 8K ring */ 170 #else 171 #define RX_BUF_IDX 2 /* 32K ring */ 172 #endif 173 #define RX_BUF_LEN (8192 << RX_BUF_IDX) 174 #define RX_BUF_PAD 16 175 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */ 176 177 #if RX_BUF_LEN == 65536 178 #define RX_BUF_TOT_LEN RX_BUF_LEN 179 #else 180 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD) 181 #endif 182 183 /* Number of Tx descriptor registers. */ 184 #define NUM_TX_DESC 4 185 186 /* max supported ethernet frame size -- must be at least (dev->mtu+18+4).*/ 187 #define MAX_ETH_FRAME_SIZE 1792 188 189 /* max supported payload size */ 190 #define MAX_ETH_DATA_SIZE (MAX_ETH_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN) 191 192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+18+4). */ 193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE 194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) 195 196 /* PCI Tuning Parameters 197 Threshold is bytes transferred to chip before transmission starts. */ 198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 199 200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ 201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ 202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */ 203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */ 205 206 /* Operational parameters that usually are not changed. */ 207 /* Time in jiffies before concluding the transmitter is hung. */ 208 #define TX_TIMEOUT (6*HZ) 209 210 211 enum { 212 HAS_MII_XCVR = 0x010000, 213 HAS_CHIP_XCVR = 0x020000, 214 HAS_LNK_CHNG = 0x040000, 215 }; 216 217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */ 218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */ 219 #define RTL_MIN_IO_SIZE 0x80 220 #define RTL8139B_IO_SIZE 256 221 222 #define RTL8129_CAPS HAS_MII_XCVR 223 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG) 224 225 typedef enum { 226 RTL8139 = 0, 227 RTL8129, 228 } board_t; 229 230 231 /* indexed by board_t, above */ 232 static const struct { 233 const char *name; 234 u32 hw_flags; 235 } board_info[] = { 236 { "RealTek RTL8139", RTL8139_CAPS }, 237 { "RealTek RTL8129", RTL8129_CAPS }, 238 }; 239 240 241 static const struct pci_device_id rtl8139_pci_tbl[] = { 242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 261 262 #ifdef CONFIG_SH_SECUREEDGE5410 263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */ 264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 265 #endif 266 #ifdef CONFIG_8139TOO_8129 267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 }, 268 #endif 269 270 /* some crazy cards report invalid vendor ids like 271 * 0x0001 here. The other ids are valid and constant, 272 * so we simply don't match on the main vendor id. 273 */ 274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 }, 275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 }, 276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 }, 277 278 {0,} 279 }; 280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl); 281 282 static struct { 283 const char str[ETH_GSTRING_LEN]; 284 } ethtool_stats_keys[] = { 285 { "early_rx" }, 286 { "tx_buf_mapped" }, 287 { "tx_timeouts" }, 288 { "rx_lost_in_ring" }, 289 }; 290 291 /* The rest of these values should never change. */ 292 293 /* Symbolic offsets to registers. */ 294 enum RTL8139_registers { 295 MAC0 = 0, /* Ethernet hardware address. */ 296 MAR0 = 8, /* Multicast filter. */ 297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ 298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 299 RxBuf = 0x30, 300 ChipCmd = 0x37, 301 RxBufPtr = 0x38, 302 RxBufAddr = 0x3A, 303 IntrMask = 0x3C, 304 IntrStatus = 0x3E, 305 TxConfig = 0x40, 306 RxConfig = 0x44, 307 Timer = 0x48, /* A general-purpose counter. */ 308 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 309 Cfg9346 = 0x50, 310 Config0 = 0x51, 311 Config1 = 0x52, 312 TimerInt = 0x54, 313 MediaStatus = 0x58, 314 Config3 = 0x59, 315 Config4 = 0x5A, /* absent on RTL-8139A */ 316 HltClk = 0x5B, 317 MultiIntr = 0x5C, 318 TxSummary = 0x60, 319 BasicModeCtrl = 0x62, 320 BasicModeStatus = 0x64, 321 NWayAdvert = 0x66, 322 NWayLPAR = 0x68, 323 NWayExpansion = 0x6A, 324 /* Undocumented registers, but required for proper operation. */ 325 FIFOTMS = 0x70, /* FIFO Control and test. */ 326 CSCR = 0x74, /* Chip Status and Configuration Register. */ 327 PARA78 = 0x78, 328 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */ 329 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 330 Config5 = 0xD8, /* absent on RTL-8139A */ 331 }; 332 333 enum ClearBitMasks { 334 MultiIntrClear = 0xF000, 335 ChipCmdClear = 0xE2, 336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 337 }; 338 339 enum ChipCmdBits { 340 CmdReset = 0x10, 341 CmdRxEnb = 0x08, 342 CmdTxEnb = 0x04, 343 RxBufEmpty = 0x01, 344 }; 345 346 /* Interrupt register bits, using my own meaningful names. */ 347 enum IntrStatusBits { 348 PCIErr = 0x8000, 349 PCSTimeout = 0x4000, 350 RxFIFOOver = 0x40, 351 RxUnderrun = 0x20, 352 RxOverflow = 0x10, 353 TxErr = 0x08, 354 TxOK = 0x04, 355 RxErr = 0x02, 356 RxOK = 0x01, 357 358 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 359 }; 360 361 enum TxStatusBits { 362 TxHostOwns = 0x2000, 363 TxUnderrun = 0x4000, 364 TxStatOK = 0x8000, 365 TxOutOfWindow = 0x20000000, 366 TxAborted = 0x40000000, 367 TxCarrierLost = 0x80000000, 368 }; 369 enum RxStatusBits { 370 RxMulticast = 0x8000, 371 RxPhysical = 0x4000, 372 RxBroadcast = 0x2000, 373 RxBadSymbol = 0x0020, 374 RxRunt = 0x0010, 375 RxTooLong = 0x0008, 376 RxCRCErr = 0x0004, 377 RxBadAlign = 0x0002, 378 RxStatusOK = 0x0001, 379 }; 380 381 /* Bits in RxConfig. */ 382 enum rx_mode_bits { 383 AcceptErr = 0x20, 384 AcceptRunt = 0x10, 385 AcceptBroadcast = 0x08, 386 AcceptMulticast = 0x04, 387 AcceptMyPhys = 0x02, 388 AcceptAllPhys = 0x01, 389 }; 390 391 /* Bits in TxConfig. */ 392 enum tx_config_bits { 393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 394 TxIFGShift = 24, 395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 399 400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 401 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */ 402 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */ 404 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */ 405 406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 407 }; 408 409 /* Bits in Config1 */ 410 enum Config1Bits { 411 Cfg1_PM_Enable = 0x01, 412 Cfg1_VPD_Enable = 0x02, 413 Cfg1_PIO = 0x04, 414 Cfg1_MMIO = 0x08, 415 LWAKE = 0x10, /* not on 8139, 8139A */ 416 Cfg1_Driver_Load = 0x20, 417 Cfg1_LED0 = 0x40, 418 Cfg1_LED1 = 0x80, 419 SLEEP = (1 << 1), /* only on 8139, 8139A */ 420 PWRDN = (1 << 0), /* only on 8139, 8139A */ 421 }; 422 423 /* Bits in Config3 */ 424 enum Config3Bits { 425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 433 }; 434 435 /* Bits in Config4 */ 436 enum Config4Bits { 437 LWPTN = (1 << 2), /* not on 8139, 8139A */ 438 }; 439 440 /* Bits in Config5 */ 441 enum Config5Bits { 442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 445 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */ 446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 449 }; 450 451 enum RxConfigBits { 452 /* rx fifo threshold */ 453 RxCfgFIFOShift = 13, 454 RxCfgFIFONone = (7 << RxCfgFIFOShift), 455 456 /* Max DMA burst */ 457 RxCfgDMAShift = 8, 458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 459 460 /* rx ring buffer length */ 461 RxCfgRcv8K = 0, 462 RxCfgRcv16K = (1 << 11), 463 RxCfgRcv32K = (1 << 12), 464 RxCfgRcv64K = (1 << 11) | (1 << 12), 465 466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 467 RxNoWrap = (1 << 7), 468 }; 469 470 /* Twister tuning parameters from RealTek. 471 Completely undocumented, but required to tune bad links on some boards. */ 472 enum CSCRBits { 473 CSCR_LinkOKBit = 0x0400, 474 CSCR_LinkChangeBit = 0x0800, 475 CSCR_LinkStatusBits = 0x0f000, 476 CSCR_LinkDownOffCmd = 0x003c0, 477 CSCR_LinkDownCmd = 0x0f3c0, 478 }; 479 480 enum Cfg9346Bits { 481 Cfg9346_Lock = 0x00, 482 Cfg9346_Unlock = 0xC0, 483 }; 484 485 typedef enum { 486 CH_8139 = 0, 487 CH_8139_K, 488 CH_8139A, 489 CH_8139A_G, 490 CH_8139B, 491 CH_8130, 492 CH_8139C, 493 CH_8100, 494 CH_8100B_8139D, 495 CH_8101, 496 } chip_t; 497 498 enum chip_flags { 499 HasHltClk = (1 << 0), 500 HasLWake = (1 << 1), 501 }; 502 503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 506 507 /* directly indexed by chip_t, above */ 508 static const struct { 509 const char *name; 510 u32 version; /* from RTL8139C/RTL8139D docs */ 511 u32 flags; 512 } rtl_chip_info[] = { 513 { "RTL-8139", 514 HW_REVID(1, 0, 0, 0, 0, 0, 0), 515 HasHltClk, 516 }, 517 518 { "RTL-8139 rev K", 519 HW_REVID(1, 1, 0, 0, 0, 0, 0), 520 HasHltClk, 521 }, 522 523 { "RTL-8139A", 524 HW_REVID(1, 1, 1, 0, 0, 0, 0), 525 HasHltClk, /* XXX undocumented? */ 526 }, 527 528 { "RTL-8139A rev G", 529 HW_REVID(1, 1, 1, 0, 0, 1, 0), 530 HasHltClk, /* XXX undocumented? */ 531 }, 532 533 { "RTL-8139B", 534 HW_REVID(1, 1, 1, 1, 0, 0, 0), 535 HasLWake, 536 }, 537 538 { "RTL-8130", 539 HW_REVID(1, 1, 1, 1, 1, 0, 0), 540 HasLWake, 541 }, 542 543 { "RTL-8139C", 544 HW_REVID(1, 1, 1, 0, 1, 0, 0), 545 HasLWake, 546 }, 547 548 { "RTL-8100", 549 HW_REVID(1, 1, 1, 1, 0, 1, 0), 550 HasLWake, 551 }, 552 553 { "RTL-8100B/8139D", 554 HW_REVID(1, 1, 1, 0, 1, 0, 1), 555 HasHltClk /* XXX undocumented? */ 556 | HasLWake, 557 }, 558 559 { "RTL-8101", 560 HW_REVID(1, 1, 1, 0, 1, 1, 1), 561 HasLWake, 562 }, 563 }; 564 565 struct rtl_extra_stats { 566 unsigned long early_rx; 567 unsigned long tx_buf_mapped; 568 unsigned long tx_timeouts; 569 unsigned long rx_lost_in_ring; 570 }; 571 572 struct rtl8139_stats { 573 u64 packets; 574 u64 bytes; 575 struct u64_stats_sync syncp; 576 }; 577 578 struct rtl8139_private { 579 void __iomem *mmio_addr; 580 int drv_flags; 581 struct pci_dev *pci_dev; 582 u32 msg_enable; 583 struct napi_struct napi; 584 struct net_device *dev; 585 586 unsigned char *rx_ring; 587 unsigned int cur_rx; /* RX buf index of next pkt */ 588 struct rtl8139_stats rx_stats; 589 dma_addr_t rx_ring_dma; 590 591 unsigned int tx_flag; 592 unsigned long cur_tx; 593 unsigned long dirty_tx; 594 struct rtl8139_stats tx_stats; 595 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */ 596 unsigned char *tx_bufs; /* Tx bounce buffer region. */ 597 dma_addr_t tx_bufs_dma; 598 599 signed char phys[4]; /* MII device addresses. */ 600 601 /* Twister tune state. */ 602 char twistie, twist_row, twist_col; 603 604 unsigned int watchdog_fired : 1; 605 unsigned int default_port : 4; /* Last dev->if_port value. */ 606 unsigned int have_thread : 1; 607 608 spinlock_t lock; 609 spinlock_t rx_lock; 610 611 chip_t chipset; 612 u32 rx_config; 613 struct rtl_extra_stats xstats; 614 615 struct delayed_work thread; 616 617 struct mii_if_info mii; 618 unsigned int regs_len; 619 unsigned long fifo_copy_timeout; 620 }; 621 622 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>"); 623 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver"); 624 MODULE_LICENSE("GPL"); 625 MODULE_VERSION(DRV_VERSION); 626 627 module_param(use_io, bool, 0); 628 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO"); 629 module_param(multicast_filter_limit, int, 0); 630 module_param_array(media, int, NULL, 0); 631 module_param_array(full_duplex, int, NULL, 0); 632 module_param(debug, int, 0); 633 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number"); 634 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses"); 635 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps"); 636 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)"); 637 638 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len); 639 static int rtl8139_open (struct net_device *dev); 640 static int mdio_read (struct net_device *dev, int phy_id, int location); 641 static void mdio_write (struct net_device *dev, int phy_id, int location, 642 int val); 643 static void rtl8139_start_thread(struct rtl8139_private *tp); 644 static void rtl8139_tx_timeout (struct net_device *dev); 645 static void rtl8139_init_ring (struct net_device *dev); 646 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 647 struct net_device *dev); 648 #ifdef CONFIG_NET_POLL_CONTROLLER 649 static void rtl8139_poll_controller(struct net_device *dev); 650 #endif 651 static int rtl8139_set_mac_address(struct net_device *dev, void *p); 652 static int rtl8139_poll(struct napi_struct *napi, int budget); 653 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance); 654 static int rtl8139_close (struct net_device *dev); 655 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 656 static void rtl8139_get_stats64(struct net_device *dev, 657 struct rtnl_link_stats64 *stats); 658 static void rtl8139_set_rx_mode (struct net_device *dev); 659 static void __set_rx_mode (struct net_device *dev); 660 static void rtl8139_hw_start (struct net_device *dev); 661 static void rtl8139_thread (struct work_struct *work); 662 static void rtl8139_tx_timeout_task(struct work_struct *work); 663 static const struct ethtool_ops rtl8139_ethtool_ops; 664 665 /* write MMIO register, with flush */ 666 /* Flush avoids rtl8139 bug w/ posted MMIO writes */ 667 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0) 668 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0) 669 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0) 670 671 /* write MMIO register */ 672 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg)) 673 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg)) 674 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg)) 675 676 /* read MMIO register */ 677 #define RTL_R8(reg) ioread8 (ioaddr + (reg)) 678 #define RTL_R16(reg) ioread16 (ioaddr + (reg)) 679 #define RTL_R32(reg) ioread32 (ioaddr + (reg)) 680 681 682 static const u16 rtl8139_intr_mask = 683 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | 684 TxErr | TxOK | RxErr | RxOK; 685 686 static const u16 rtl8139_norx_intr_mask = 687 PCIErr | PCSTimeout | RxUnderrun | 688 TxErr | TxOK | RxErr ; 689 690 #if RX_BUF_IDX == 0 691 static const unsigned int rtl8139_rx_config = 692 RxCfgRcv8K | RxNoWrap | 693 (RX_FIFO_THRESH << RxCfgFIFOShift) | 694 (RX_DMA_BURST << RxCfgDMAShift); 695 #elif RX_BUF_IDX == 1 696 static const unsigned int rtl8139_rx_config = 697 RxCfgRcv16K | RxNoWrap | 698 (RX_FIFO_THRESH << RxCfgFIFOShift) | 699 (RX_DMA_BURST << RxCfgDMAShift); 700 #elif RX_BUF_IDX == 2 701 static const unsigned int rtl8139_rx_config = 702 RxCfgRcv32K | RxNoWrap | 703 (RX_FIFO_THRESH << RxCfgFIFOShift) | 704 (RX_DMA_BURST << RxCfgDMAShift); 705 #elif RX_BUF_IDX == 3 706 static const unsigned int rtl8139_rx_config = 707 RxCfgRcv64K | 708 (RX_FIFO_THRESH << RxCfgFIFOShift) | 709 (RX_DMA_BURST << RxCfgDMAShift); 710 #else 711 #error "Invalid configuration for 8139_RXBUF_IDX" 712 #endif 713 714 static const unsigned int rtl8139_tx_config = 715 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift); 716 717 static void __rtl8139_cleanup_dev (struct net_device *dev) 718 { 719 struct rtl8139_private *tp = netdev_priv(dev); 720 struct pci_dev *pdev; 721 722 assert (dev != NULL); 723 assert (tp->pci_dev != NULL); 724 pdev = tp->pci_dev; 725 726 if (tp->mmio_addr) 727 pci_iounmap (pdev, tp->mmio_addr); 728 729 /* it's ok to call this even if we have no regions to free */ 730 pci_release_regions (pdev); 731 732 free_netdev(dev); 733 } 734 735 736 static void rtl8139_chip_reset (void __iomem *ioaddr) 737 { 738 int i; 739 740 /* Soft reset the chip. */ 741 RTL_W8 (ChipCmd, CmdReset); 742 743 /* Check that the chip has finished the reset. */ 744 for (i = 1000; i > 0; i--) { 745 barrier(); 746 if ((RTL_R8 (ChipCmd) & CmdReset) == 0) 747 break; 748 udelay (10); 749 } 750 } 751 752 753 static struct net_device *rtl8139_init_board(struct pci_dev *pdev) 754 { 755 struct device *d = &pdev->dev; 756 void __iomem *ioaddr; 757 struct net_device *dev; 758 struct rtl8139_private *tp; 759 u8 tmp8; 760 int rc, disable_dev_on_err = 0; 761 unsigned int i, bar; 762 unsigned long io_len; 763 u32 version; 764 static const struct { 765 unsigned long mask; 766 char *type; 767 } res[] = { 768 { IORESOURCE_IO, "PIO" }, 769 { IORESOURCE_MEM, "MMIO" } 770 }; 771 772 assert (pdev != NULL); 773 774 /* dev and priv zeroed in alloc_etherdev */ 775 dev = alloc_etherdev (sizeof (*tp)); 776 if (dev == NULL) 777 return ERR_PTR(-ENOMEM); 778 779 SET_NETDEV_DEV(dev, &pdev->dev); 780 781 tp = netdev_priv(dev); 782 tp->pci_dev = pdev; 783 784 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 785 rc = pci_enable_device (pdev); 786 if (rc) 787 goto err_out; 788 789 disable_dev_on_err = 1; 790 rc = pci_request_regions (pdev, DRV_NAME); 791 if (rc) 792 goto err_out; 793 794 pci_set_master (pdev); 795 796 u64_stats_init(&tp->rx_stats.syncp); 797 u64_stats_init(&tp->tx_stats.syncp); 798 799 retry: 800 /* PIO bar register comes first. */ 801 bar = !use_io; 802 803 io_len = pci_resource_len(pdev, bar); 804 805 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len); 806 807 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) { 808 dev_err(d, "region #%d not a %s resource, aborting\n", bar, 809 res[bar].type); 810 rc = -ENODEV; 811 goto err_out; 812 } 813 if (io_len < RTL_MIN_IO_SIZE) { 814 dev_err(d, "Invalid PCI %s region size(s), aborting\n", 815 res[bar].type); 816 rc = -ENODEV; 817 goto err_out; 818 } 819 820 ioaddr = pci_iomap(pdev, bar, 0); 821 if (!ioaddr) { 822 dev_err(d, "cannot map %s\n", res[bar].type); 823 if (!use_io) { 824 use_io = true; 825 goto retry; 826 } 827 rc = -ENODEV; 828 goto err_out; 829 } 830 tp->regs_len = io_len; 831 tp->mmio_addr = ioaddr; 832 833 /* Bring old chips out of low-power mode. */ 834 RTL_W8 (HltClk, 'R'); 835 836 /* check for missing/broken hardware */ 837 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) { 838 dev_err(&pdev->dev, "Chip not responding, ignoring board\n"); 839 rc = -EIO; 840 goto err_out; 841 } 842 843 /* identify chip attached to board */ 844 version = RTL_R32 (TxConfig) & HW_REVID_MASK; 845 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++) 846 if (version == rtl_chip_info[i].version) { 847 tp->chipset = i; 848 goto match; 849 } 850 851 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ 852 i = 0; 853 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); 854 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); 855 tp->chipset = 0; 856 857 match: 858 pr_debug("chipset id (%d) == index %d, '%s'\n", 859 version, i, rtl_chip_info[i].name); 860 861 if (tp->chipset >= CH_8139B) { 862 u8 new_tmp8 = tmp8 = RTL_R8 (Config1); 863 pr_debug("PCI PM wakeup\n"); 864 if ((rtl_chip_info[tp->chipset].flags & HasLWake) && 865 (tmp8 & LWAKE)) 866 new_tmp8 &= ~LWAKE; 867 new_tmp8 |= Cfg1_PM_Enable; 868 if (new_tmp8 != tmp8) { 869 RTL_W8 (Cfg9346, Cfg9346_Unlock); 870 RTL_W8 (Config1, tmp8); 871 RTL_W8 (Cfg9346, Cfg9346_Lock); 872 } 873 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 874 tmp8 = RTL_R8 (Config4); 875 if (tmp8 & LWPTN) { 876 RTL_W8 (Cfg9346, Cfg9346_Unlock); 877 RTL_W8 (Config4, tmp8 & ~LWPTN); 878 RTL_W8 (Cfg9346, Cfg9346_Lock); 879 } 880 } 881 } else { 882 pr_debug("Old chip wakeup\n"); 883 tmp8 = RTL_R8 (Config1); 884 tmp8 &= ~(SLEEP | PWRDN); 885 RTL_W8 (Config1, tmp8); 886 } 887 888 rtl8139_chip_reset (ioaddr); 889 890 return dev; 891 892 err_out: 893 __rtl8139_cleanup_dev (dev); 894 if (disable_dev_on_err) 895 pci_disable_device (pdev); 896 return ERR_PTR(rc); 897 } 898 899 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features) 900 { 901 struct rtl8139_private *tp = netdev_priv(dev); 902 unsigned long flags; 903 netdev_features_t changed = features ^ dev->features; 904 void __iomem *ioaddr = tp->mmio_addr; 905 906 if (!(changed & (NETIF_F_RXALL))) 907 return 0; 908 909 spin_lock_irqsave(&tp->lock, flags); 910 911 if (changed & NETIF_F_RXALL) { 912 int rx_mode = tp->rx_config; 913 if (features & NETIF_F_RXALL) 914 rx_mode |= (AcceptErr | AcceptRunt); 915 else 916 rx_mode &= ~(AcceptErr | AcceptRunt); 917 tp->rx_config = rtl8139_rx_config | rx_mode; 918 RTL_W32_F(RxConfig, tp->rx_config); 919 } 920 921 spin_unlock_irqrestore(&tp->lock, flags); 922 923 return 0; 924 } 925 926 static const struct net_device_ops rtl8139_netdev_ops = { 927 .ndo_open = rtl8139_open, 928 .ndo_stop = rtl8139_close, 929 .ndo_get_stats64 = rtl8139_get_stats64, 930 .ndo_validate_addr = eth_validate_addr, 931 .ndo_set_mac_address = rtl8139_set_mac_address, 932 .ndo_start_xmit = rtl8139_start_xmit, 933 .ndo_set_rx_mode = rtl8139_set_rx_mode, 934 .ndo_do_ioctl = netdev_ioctl, 935 .ndo_tx_timeout = rtl8139_tx_timeout, 936 #ifdef CONFIG_NET_POLL_CONTROLLER 937 .ndo_poll_controller = rtl8139_poll_controller, 938 #endif 939 .ndo_set_features = rtl8139_set_features, 940 }; 941 942 static int rtl8139_init_one(struct pci_dev *pdev, 943 const struct pci_device_id *ent) 944 { 945 struct net_device *dev = NULL; 946 struct rtl8139_private *tp; 947 int i, addr_len, option; 948 void __iomem *ioaddr; 949 static int board_idx = -1; 950 951 assert (pdev != NULL); 952 assert (ent != NULL); 953 954 board_idx++; 955 956 /* when we're built into the kernel, the driver version message 957 * is only printed if at least one 8139 board has been found 958 */ 959 #ifndef MODULE 960 { 961 static int printed_version; 962 if (!printed_version++) 963 pr_info(RTL8139_DRIVER_NAME "\n"); 964 } 965 #endif 966 967 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 968 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) { 969 dev_info(&pdev->dev, 970 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n", 971 pdev->vendor, pdev->device, pdev->revision); 972 return -ENODEV; 973 } 974 975 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 976 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && 977 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS && 978 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) { 979 pr_info("OQO Model 2 detected. Forcing PIO\n"); 980 use_io = 1; 981 } 982 983 dev = rtl8139_init_board (pdev); 984 if (IS_ERR(dev)) 985 return PTR_ERR(dev); 986 987 assert (dev != NULL); 988 tp = netdev_priv(dev); 989 tp->dev = dev; 990 991 ioaddr = tp->mmio_addr; 992 assert (ioaddr != NULL); 993 994 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6; 995 for (i = 0; i < 3; i++) 996 ((__le16 *) (dev->dev_addr))[i] = 997 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len)); 998 999 /* The Rtl8139-specific entries in the device structure. */ 1000 dev->netdev_ops = &rtl8139_netdev_ops; 1001 dev->ethtool_ops = &rtl8139_ethtool_ops; 1002 dev->watchdog_timeo = TX_TIMEOUT; 1003 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64); 1004 1005 /* note: the hardware is not capable of sg/csum/highdma, however 1006 * through the use of skb_copy_and_csum_dev we enable these 1007 * features 1008 */ 1009 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA; 1010 dev->vlan_features = dev->features; 1011 1012 dev->hw_features |= NETIF_F_RXALL; 1013 dev->hw_features |= NETIF_F_RXFCS; 1014 1015 /* MTU range: 68 - 1770 */ 1016 dev->min_mtu = ETH_MIN_MTU; 1017 dev->max_mtu = MAX_ETH_DATA_SIZE; 1018 1019 /* tp zeroed and aligned in alloc_etherdev */ 1020 tp = netdev_priv(dev); 1021 1022 /* note: tp->chipset set in rtl8139_init_board */ 1023 tp->drv_flags = board_info[ent->driver_data].hw_flags; 1024 tp->mmio_addr = ioaddr; 1025 tp->msg_enable = 1026 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1)); 1027 spin_lock_init (&tp->lock); 1028 spin_lock_init (&tp->rx_lock); 1029 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1030 tp->mii.dev = dev; 1031 tp->mii.mdio_read = mdio_read; 1032 tp->mii.mdio_write = mdio_write; 1033 tp->mii.phy_id_mask = 0x3f; 1034 tp->mii.reg_num_mask = 0x1f; 1035 1036 /* dev is fully set up and ready to use now */ 1037 pr_debug("about to register device named %s (%p)...\n", 1038 dev->name, dev); 1039 i = register_netdev (dev); 1040 if (i) goto err_out; 1041 1042 pci_set_drvdata (pdev, dev); 1043 1044 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n", 1045 board_info[ent->driver_data].name, 1046 ioaddr, dev->dev_addr, pdev->irq); 1047 1048 netdev_dbg(dev, "Identified 8139 chip type '%s'\n", 1049 rtl_chip_info[tp->chipset].name); 1050 1051 /* Find the connected MII xcvrs. 1052 Doing this in open() would allow detecting external xcvrs later, but 1053 takes too much time. */ 1054 #ifdef CONFIG_8139TOO_8129 1055 if (tp->drv_flags & HAS_MII_XCVR) { 1056 int phy, phy_idx = 0; 1057 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) { 1058 int mii_status = mdio_read(dev, phy, 1); 1059 if (mii_status != 0xffff && mii_status != 0x0000) { 1060 u16 advertising = mdio_read(dev, phy, 4); 1061 tp->phys[phy_idx++] = phy; 1062 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n", 1063 phy, mii_status, advertising); 1064 } 1065 } 1066 if (phy_idx == 0) { 1067 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n"); 1068 tp->phys[0] = 32; 1069 } 1070 } else 1071 #endif 1072 tp->phys[0] = 32; 1073 tp->mii.phy_id = tp->phys[0]; 1074 1075 /* The lower four bits are the media type. */ 1076 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 1077 if (option > 0) { 1078 tp->mii.full_duplex = (option & 0x210) ? 1 : 0; 1079 tp->default_port = option & 0xFF; 1080 if (tp->default_port) 1081 tp->mii.force_media = 1; 1082 } 1083 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0) 1084 tp->mii.full_duplex = full_duplex[board_idx]; 1085 if (tp->mii.full_duplex) { 1086 netdev_info(dev, "Media type forced to Full Duplex\n"); 1087 /* Changing the MII-advertised media because might prevent 1088 re-connection. */ 1089 tp->mii.force_media = 1; 1090 } 1091 if (tp->default_port) { 1092 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n", 1093 (option & 0x20 ? 100 : 10), 1094 (option & 0x10 ? "full" : "half")); 1095 mdio_write(dev, tp->phys[0], 0, 1096 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */ 1097 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */ 1098 } 1099 1100 /* Put the chip into low-power mode. */ 1101 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1102 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 1103 1104 return 0; 1105 1106 err_out: 1107 __rtl8139_cleanup_dev (dev); 1108 pci_disable_device (pdev); 1109 return i; 1110 } 1111 1112 1113 static void rtl8139_remove_one(struct pci_dev *pdev) 1114 { 1115 struct net_device *dev = pci_get_drvdata (pdev); 1116 struct rtl8139_private *tp = netdev_priv(dev); 1117 1118 assert (dev != NULL); 1119 1120 cancel_delayed_work_sync(&tp->thread); 1121 1122 unregister_netdev (dev); 1123 1124 __rtl8139_cleanup_dev (dev); 1125 pci_disable_device (pdev); 1126 } 1127 1128 1129 /* Serial EEPROM section. */ 1130 1131 /* EEPROM_Ctrl bits. */ 1132 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 1133 #define EE_CS 0x08 /* EEPROM chip select. */ 1134 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 1135 #define EE_WRITE_0 0x00 1136 #define EE_WRITE_1 0x02 1137 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 1138 #define EE_ENB (0x80 | EE_CS) 1139 1140 /* Delay between EEPROM clock transitions. 1141 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 1142 */ 1143 1144 #define eeprom_delay() (void)RTL_R8(Cfg9346) 1145 1146 /* The EEPROM commands include the alway-set leading bit. */ 1147 #define EE_WRITE_CMD (5) 1148 #define EE_READ_CMD (6) 1149 #define EE_ERASE_CMD (7) 1150 1151 static int read_eeprom(void __iomem *ioaddr, int location, int addr_len) 1152 { 1153 int i; 1154 unsigned retval = 0; 1155 int read_cmd = location | (EE_READ_CMD << addr_len); 1156 1157 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS); 1158 RTL_W8 (Cfg9346, EE_ENB); 1159 eeprom_delay (); 1160 1161 /* Shift the read command bits out. */ 1162 for (i = 4 + addr_len; i >= 0; i--) { 1163 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 1164 RTL_W8 (Cfg9346, EE_ENB | dataval); 1165 eeprom_delay (); 1166 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK); 1167 eeprom_delay (); 1168 } 1169 RTL_W8 (Cfg9346, EE_ENB); 1170 eeprom_delay (); 1171 1172 for (i = 16; i > 0; i--) { 1173 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK); 1174 eeprom_delay (); 1175 retval = 1176 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 : 1177 0); 1178 RTL_W8 (Cfg9346, EE_ENB); 1179 eeprom_delay (); 1180 } 1181 1182 /* Terminate the EEPROM access. */ 1183 RTL_W8(Cfg9346, 0); 1184 eeprom_delay (); 1185 1186 return retval; 1187 } 1188 1189 /* MII serial management: mostly bogus for now. */ 1190 /* Read and write the MII management registers using software-generated 1191 serial MDIO protocol. 1192 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 1193 met by back-to-back PCI I/O cycles, but we insert a delay to avoid 1194 "overclocking" issues. */ 1195 #define MDIO_DIR 0x80 1196 #define MDIO_DATA_OUT 0x04 1197 #define MDIO_DATA_IN 0x02 1198 #define MDIO_CLK 0x01 1199 #define MDIO_WRITE0 (MDIO_DIR) 1200 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT) 1201 1202 #define mdio_delay() RTL_R8(Config4) 1203 1204 1205 static const char mii_2_8139_map[8] = { 1206 BasicModeCtrl, 1207 BasicModeStatus, 1208 0, 1209 0, 1210 NWayAdvert, 1211 NWayLPAR, 1212 NWayExpansion, 1213 0 1214 }; 1215 1216 1217 #ifdef CONFIG_8139TOO_8129 1218 /* Syncronize the MII management interface by shifting 32 one bits out. */ 1219 static void mdio_sync (void __iomem *ioaddr) 1220 { 1221 int i; 1222 1223 for (i = 32; i >= 0; i--) { 1224 RTL_W8 (Config4, MDIO_WRITE1); 1225 mdio_delay (); 1226 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK); 1227 mdio_delay (); 1228 } 1229 } 1230 #endif 1231 1232 static int mdio_read (struct net_device *dev, int phy_id, int location) 1233 { 1234 struct rtl8139_private *tp = netdev_priv(dev); 1235 int retval = 0; 1236 #ifdef CONFIG_8139TOO_8129 1237 void __iomem *ioaddr = tp->mmio_addr; 1238 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; 1239 int i; 1240 #endif 1241 1242 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1243 void __iomem *ioaddr = tp->mmio_addr; 1244 return location < 8 && mii_2_8139_map[location] ? 1245 RTL_R16 (mii_2_8139_map[location]) : 0; 1246 } 1247 1248 #ifdef CONFIG_8139TOO_8129 1249 mdio_sync (ioaddr); 1250 /* Shift the read command bits out. */ 1251 for (i = 15; i >= 0; i--) { 1252 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0; 1253 1254 RTL_W8 (Config4, MDIO_DIR | dataval); 1255 mdio_delay (); 1256 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK); 1257 mdio_delay (); 1258 } 1259 1260 /* Read the two transition, 16 data, and wire-idle bits. */ 1261 for (i = 19; i > 0; i--) { 1262 RTL_W8 (Config4, 0); 1263 mdio_delay (); 1264 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0); 1265 RTL_W8 (Config4, MDIO_CLK); 1266 mdio_delay (); 1267 } 1268 #endif 1269 1270 return (retval >> 1) & 0xffff; 1271 } 1272 1273 1274 static void mdio_write (struct net_device *dev, int phy_id, int location, 1275 int value) 1276 { 1277 struct rtl8139_private *tp = netdev_priv(dev); 1278 #ifdef CONFIG_8139TOO_8129 1279 void __iomem *ioaddr = tp->mmio_addr; 1280 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; 1281 int i; 1282 #endif 1283 1284 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1285 void __iomem *ioaddr = tp->mmio_addr; 1286 if (location == 0) { 1287 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1288 RTL_W16 (BasicModeCtrl, value); 1289 RTL_W8 (Cfg9346, Cfg9346_Lock); 1290 } else if (location < 8 && mii_2_8139_map[location]) 1291 RTL_W16 (mii_2_8139_map[location], value); 1292 return; 1293 } 1294 1295 #ifdef CONFIG_8139TOO_8129 1296 mdio_sync (ioaddr); 1297 1298 /* Shift the command bits out. */ 1299 for (i = 31; i >= 0; i--) { 1300 int dataval = 1301 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 1302 RTL_W8 (Config4, dataval); 1303 mdio_delay (); 1304 RTL_W8 (Config4, dataval | MDIO_CLK); 1305 mdio_delay (); 1306 } 1307 /* Clear out extra bits. */ 1308 for (i = 2; i > 0; i--) { 1309 RTL_W8 (Config4, 0); 1310 mdio_delay (); 1311 RTL_W8 (Config4, MDIO_CLK); 1312 mdio_delay (); 1313 } 1314 #endif 1315 } 1316 1317 1318 static int rtl8139_open (struct net_device *dev) 1319 { 1320 struct rtl8139_private *tp = netdev_priv(dev); 1321 void __iomem *ioaddr = tp->mmio_addr; 1322 const int irq = tp->pci_dev->irq; 1323 int retval; 1324 1325 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev); 1326 if (retval) 1327 return retval; 1328 1329 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1330 &tp->tx_bufs_dma, GFP_KERNEL); 1331 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1332 &tp->rx_ring_dma, GFP_KERNEL); 1333 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) { 1334 free_irq(irq, dev); 1335 1336 if (tp->tx_bufs) 1337 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1338 tp->tx_bufs, tp->tx_bufs_dma); 1339 if (tp->rx_ring) 1340 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1341 tp->rx_ring, tp->rx_ring_dma); 1342 1343 return -ENOMEM; 1344 1345 } 1346 1347 napi_enable(&tp->napi); 1348 1349 tp->mii.full_duplex = tp->mii.force_media; 1350 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000; 1351 1352 rtl8139_init_ring (dev); 1353 rtl8139_hw_start (dev); 1354 netif_start_queue (dev); 1355 1356 netif_dbg(tp, ifup, dev, 1357 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n", 1358 __func__, 1359 (unsigned long long)pci_resource_start (tp->pci_dev, 1), 1360 irq, RTL_R8 (MediaStatus), 1361 tp->mii.full_duplex ? "full" : "half"); 1362 1363 rtl8139_start_thread(tp); 1364 1365 return 0; 1366 } 1367 1368 1369 static void rtl_check_media (struct net_device *dev, unsigned int init_media) 1370 { 1371 struct rtl8139_private *tp = netdev_priv(dev); 1372 1373 if (tp->phys[0] >= 0) { 1374 mii_check_media(&tp->mii, netif_msg_link(tp), init_media); 1375 } 1376 } 1377 1378 /* Start the hardware at open or resume. */ 1379 static void rtl8139_hw_start (struct net_device *dev) 1380 { 1381 struct rtl8139_private *tp = netdev_priv(dev); 1382 void __iomem *ioaddr = tp->mmio_addr; 1383 u32 i; 1384 u8 tmp; 1385 1386 /* Bring old chips out of low-power mode. */ 1387 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1388 RTL_W8 (HltClk, 'R'); 1389 1390 rtl8139_chip_reset (ioaddr); 1391 1392 /* unlock Config[01234] and BMCR register writes */ 1393 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1394 /* Restore our idea of the MAC address. */ 1395 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); 1396 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4))); 1397 1398 tp->cur_rx = 0; 1399 1400 /* init Rx ring buffer DMA address */ 1401 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1402 1403 /* Must enable Tx/Rx before setting transfer thresholds! */ 1404 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1405 1406 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1407 RTL_W32 (RxConfig, tp->rx_config); 1408 RTL_W32 (TxConfig, rtl8139_tx_config); 1409 1410 rtl_check_media (dev, 1); 1411 1412 if (tp->chipset >= CH_8139B) { 1413 /* Disable magic packet scanning, which is enabled 1414 * when PM is enabled in Config1. It can be reenabled 1415 * via ETHTOOL_SWOL if desired. */ 1416 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic); 1417 } 1418 1419 netdev_dbg(dev, "init buffer addresses\n"); 1420 1421 /* Lock Config[01234] and BMCR register writes */ 1422 RTL_W8 (Cfg9346, Cfg9346_Lock); 1423 1424 /* init Tx buffer DMA addresses */ 1425 for (i = 0; i < NUM_TX_DESC; i++) 1426 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs)); 1427 1428 RTL_W32 (RxMissed, 0); 1429 1430 rtl8139_set_rx_mode (dev); 1431 1432 /* no early-rx interrupts */ 1433 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear); 1434 1435 /* make sure RxTx has started */ 1436 tmp = RTL_R8 (ChipCmd); 1437 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb))) 1438 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1439 1440 /* Enable all known interrupts by setting the interrupt mask. */ 1441 RTL_W16 (IntrMask, rtl8139_intr_mask); 1442 } 1443 1444 1445 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1446 static void rtl8139_init_ring (struct net_device *dev) 1447 { 1448 struct rtl8139_private *tp = netdev_priv(dev); 1449 int i; 1450 1451 tp->cur_rx = 0; 1452 tp->cur_tx = 0; 1453 tp->dirty_tx = 0; 1454 1455 for (i = 0; i < NUM_TX_DESC; i++) 1456 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE]; 1457 } 1458 1459 1460 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */ 1461 static int next_tick = 3 * HZ; 1462 1463 #ifndef CONFIG_8139TOO_TUNE_TWISTER 1464 static inline void rtl8139_tune_twister (struct net_device *dev, 1465 struct rtl8139_private *tp) {} 1466 #else 1467 enum TwisterParamVals { 1468 PARA78_default = 0x78fa8388, 1469 PARA7c_default = 0xcb38de43, /* param[0][3] */ 1470 PARA7c_xxx = 0xcb38de43, 1471 }; 1472 1473 static const unsigned long param[4][4] = { 1474 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1475 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1476 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1477 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1478 }; 1479 1480 static void rtl8139_tune_twister (struct net_device *dev, 1481 struct rtl8139_private *tp) 1482 { 1483 int linkcase; 1484 void __iomem *ioaddr = tp->mmio_addr; 1485 1486 /* This is a complicated state machine to configure the "twister" for 1487 impedance/echos based on the cable length. 1488 All of this is magic and undocumented. 1489 */ 1490 switch (tp->twistie) { 1491 case 1: 1492 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) { 1493 /* We have link beat, let us tune the twister. */ 1494 RTL_W16 (CSCR, CSCR_LinkDownOffCmd); 1495 tp->twistie = 2; /* Change to state 2. */ 1496 next_tick = HZ / 10; 1497 } else { 1498 /* Just put in some reasonable defaults for when beat returns. */ 1499 RTL_W16 (CSCR, CSCR_LinkDownCmd); 1500 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */ 1501 RTL_W32 (PARA78, PARA78_default); 1502 RTL_W32 (PARA7c, PARA7c_default); 1503 tp->twistie = 0; /* Bail from future actions. */ 1504 } 1505 break; 1506 case 2: 1507 /* Read how long it took to hear the echo. */ 1508 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits; 1509 if (linkcase == 0x7000) 1510 tp->twist_row = 3; 1511 else if (linkcase == 0x3000) 1512 tp->twist_row = 2; 1513 else if (linkcase == 0x1000) 1514 tp->twist_row = 1; 1515 else 1516 tp->twist_row = 0; 1517 tp->twist_col = 0; 1518 tp->twistie = 3; /* Change to state 2. */ 1519 next_tick = HZ / 10; 1520 break; 1521 case 3: 1522 /* Put out four tuning parameters, one per 100msec. */ 1523 if (tp->twist_col == 0) 1524 RTL_W16 (FIFOTMS, 0); 1525 RTL_W32 (PARA7c, param[(int) tp->twist_row] 1526 [(int) tp->twist_col]); 1527 next_tick = HZ / 10; 1528 if (++tp->twist_col >= 4) { 1529 /* For short cables we are done. 1530 For long cables (row == 3) check for mistune. */ 1531 tp->twistie = 1532 (tp->twist_row == 3) ? 4 : 0; 1533 } 1534 break; 1535 case 4: 1536 /* Special case for long cables: check for mistune. */ 1537 if ((RTL_R16 (CSCR) & 1538 CSCR_LinkStatusBits) == 0x7000) { 1539 tp->twistie = 0; 1540 break; 1541 } else { 1542 RTL_W32 (PARA7c, 0xfb38de03); 1543 tp->twistie = 5; 1544 next_tick = HZ / 10; 1545 } 1546 break; 1547 case 5: 1548 /* Retune for shorter cable (column 2). */ 1549 RTL_W32 (FIFOTMS, 0x20); 1550 RTL_W32 (PARA78, PARA78_default); 1551 RTL_W32 (PARA7c, PARA7c_default); 1552 RTL_W32 (FIFOTMS, 0x00); 1553 tp->twist_row = 2; 1554 tp->twist_col = 0; 1555 tp->twistie = 3; 1556 next_tick = HZ / 10; 1557 break; 1558 1559 default: 1560 /* do nothing */ 1561 break; 1562 } 1563 } 1564 #endif /* CONFIG_8139TOO_TUNE_TWISTER */ 1565 1566 static inline void rtl8139_thread_iter (struct net_device *dev, 1567 struct rtl8139_private *tp, 1568 void __iomem *ioaddr) 1569 { 1570 int mii_lpa; 1571 1572 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA); 1573 1574 if (!tp->mii.force_media && mii_lpa != 0xffff) { 1575 int duplex = ((mii_lpa & LPA_100FULL) || 1576 (mii_lpa & 0x01C0) == 0x0040); 1577 if (tp->mii.full_duplex != duplex) { 1578 tp->mii.full_duplex = duplex; 1579 1580 if (mii_lpa) { 1581 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n", 1582 tp->mii.full_duplex ? "full" : "half", 1583 tp->phys[0], mii_lpa); 1584 } else { 1585 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n"); 1586 } 1587 #if 0 1588 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1589 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20); 1590 RTL_W8 (Cfg9346, Cfg9346_Lock); 1591 #endif 1592 } 1593 } 1594 1595 next_tick = HZ * 60; 1596 1597 rtl8139_tune_twister (dev, tp); 1598 1599 netdev_dbg(dev, "Media selection tick, Link partner %04x\n", 1600 RTL_R16(NWayLPAR)); 1601 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n", 1602 RTL_R16(IntrMask), RTL_R16(IntrStatus)); 1603 netdev_dbg(dev, "Chip config %02x %02x\n", 1604 RTL_R8(Config0), RTL_R8(Config1)); 1605 } 1606 1607 static void rtl8139_thread (struct work_struct *work) 1608 { 1609 struct rtl8139_private *tp = 1610 container_of(work, struct rtl8139_private, thread.work); 1611 struct net_device *dev = tp->mii.dev; 1612 unsigned long thr_delay = next_tick; 1613 1614 rtnl_lock(); 1615 1616 if (!netif_running(dev)) 1617 goto out_unlock; 1618 1619 if (tp->watchdog_fired) { 1620 tp->watchdog_fired = 0; 1621 rtl8139_tx_timeout_task(work); 1622 } else 1623 rtl8139_thread_iter(dev, tp, tp->mmio_addr); 1624 1625 if (tp->have_thread) 1626 schedule_delayed_work(&tp->thread, thr_delay); 1627 out_unlock: 1628 rtnl_unlock (); 1629 } 1630 1631 static void rtl8139_start_thread(struct rtl8139_private *tp) 1632 { 1633 tp->twistie = 0; 1634 if (tp->chipset == CH_8139_K) 1635 tp->twistie = 1; 1636 else if (tp->drv_flags & HAS_LNK_CHNG) 1637 return; 1638 1639 tp->have_thread = 1; 1640 tp->watchdog_fired = 0; 1641 1642 schedule_delayed_work(&tp->thread, next_tick); 1643 } 1644 1645 static inline void rtl8139_tx_clear (struct rtl8139_private *tp) 1646 { 1647 tp->cur_tx = 0; 1648 tp->dirty_tx = 0; 1649 1650 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */ 1651 } 1652 1653 static void rtl8139_tx_timeout_task (struct work_struct *work) 1654 { 1655 struct rtl8139_private *tp = 1656 container_of(work, struct rtl8139_private, thread.work); 1657 struct net_device *dev = tp->mii.dev; 1658 void __iomem *ioaddr = tp->mmio_addr; 1659 int i; 1660 u8 tmp8; 1661 1662 napi_disable(&tp->napi); 1663 netif_stop_queue(dev); 1664 synchronize_sched(); 1665 1666 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n", 1667 RTL_R8(ChipCmd), RTL_R16(IntrStatus), 1668 RTL_R16(IntrMask), RTL_R8(MediaStatus)); 1669 /* Emit info to figure out what went wrong. */ 1670 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n", 1671 tp->cur_tx, tp->dirty_tx); 1672 for (i = 0; i < NUM_TX_DESC; i++) 1673 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n", 1674 i, RTL_R32(TxStatus0 + (i * 4)), 1675 i == tp->dirty_tx % NUM_TX_DESC ? 1676 " (queue head)" : ""); 1677 1678 tp->xstats.tx_timeouts++; 1679 1680 /* disable Tx ASAP, if not already */ 1681 tmp8 = RTL_R8 (ChipCmd); 1682 if (tmp8 & CmdTxEnb) 1683 RTL_W8 (ChipCmd, CmdRxEnb); 1684 1685 spin_lock_bh(&tp->rx_lock); 1686 /* Disable interrupts by clearing the interrupt mask. */ 1687 RTL_W16 (IntrMask, 0x0000); 1688 1689 /* Stop a shared interrupt from scavenging while we are. */ 1690 spin_lock_irq(&tp->lock); 1691 rtl8139_tx_clear (tp); 1692 spin_unlock_irq(&tp->lock); 1693 1694 /* ...and finally, reset everything */ 1695 napi_enable(&tp->napi); 1696 rtl8139_hw_start(dev); 1697 netif_wake_queue(dev); 1698 1699 spin_unlock_bh(&tp->rx_lock); 1700 } 1701 1702 static void rtl8139_tx_timeout (struct net_device *dev) 1703 { 1704 struct rtl8139_private *tp = netdev_priv(dev); 1705 1706 tp->watchdog_fired = 1; 1707 if (!tp->have_thread) { 1708 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1709 schedule_delayed_work(&tp->thread, next_tick); 1710 } 1711 } 1712 1713 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 1714 struct net_device *dev) 1715 { 1716 struct rtl8139_private *tp = netdev_priv(dev); 1717 void __iomem *ioaddr = tp->mmio_addr; 1718 unsigned int entry; 1719 unsigned int len = skb->len; 1720 unsigned long flags; 1721 1722 /* Calculate the next Tx descriptor entry. */ 1723 entry = tp->cur_tx % NUM_TX_DESC; 1724 1725 /* Note: the chip doesn't have auto-pad! */ 1726 if (likely(len < TX_BUF_SIZE)) { 1727 if (len < ETH_ZLEN) 1728 memset(tp->tx_buf[entry], 0, ETH_ZLEN); 1729 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]); 1730 dev_kfree_skb_any(skb); 1731 } else { 1732 dev_kfree_skb_any(skb); 1733 dev->stats.tx_dropped++; 1734 return NETDEV_TX_OK; 1735 } 1736 1737 spin_lock_irqsave(&tp->lock, flags); 1738 /* 1739 * Writing to TxStatus triggers a DMA transfer of the data 1740 * copied to tp->tx_buf[entry] above. Use a memory barrier 1741 * to make sure that the device sees the updated data. 1742 */ 1743 wmb(); 1744 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)), 1745 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN)); 1746 1747 tp->cur_tx++; 1748 1749 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) 1750 netif_stop_queue (dev); 1751 spin_unlock_irqrestore(&tp->lock, flags); 1752 1753 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n", 1754 len, entry); 1755 1756 return NETDEV_TX_OK; 1757 } 1758 1759 1760 static void rtl8139_tx_interrupt (struct net_device *dev, 1761 struct rtl8139_private *tp, 1762 void __iomem *ioaddr) 1763 { 1764 unsigned long dirty_tx, tx_left; 1765 1766 assert (dev != NULL); 1767 assert (ioaddr != NULL); 1768 1769 dirty_tx = tp->dirty_tx; 1770 tx_left = tp->cur_tx - dirty_tx; 1771 while (tx_left > 0) { 1772 int entry = dirty_tx % NUM_TX_DESC; 1773 int txstatus; 1774 1775 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); 1776 1777 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted))) 1778 break; /* It still hasn't been Txed */ 1779 1780 /* Note: TxCarrierLost is always asserted at 100mbps. */ 1781 if (txstatus & (TxOutOfWindow | TxAborted)) { 1782 /* There was an major error, log it. */ 1783 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n", 1784 txstatus); 1785 dev->stats.tx_errors++; 1786 if (txstatus & TxAborted) { 1787 dev->stats.tx_aborted_errors++; 1788 RTL_W32 (TxConfig, TxClearAbt); 1789 RTL_W16 (IntrStatus, TxErr); 1790 wmb(); 1791 } 1792 if (txstatus & TxCarrierLost) 1793 dev->stats.tx_carrier_errors++; 1794 if (txstatus & TxOutOfWindow) 1795 dev->stats.tx_window_errors++; 1796 } else { 1797 if (txstatus & TxUnderrun) { 1798 /* Add 64 to the Tx FIFO threshold. */ 1799 if (tp->tx_flag < 0x00300000) 1800 tp->tx_flag += 0x00020000; 1801 dev->stats.tx_fifo_errors++; 1802 } 1803 dev->stats.collisions += (txstatus >> 24) & 15; 1804 u64_stats_update_begin(&tp->tx_stats.syncp); 1805 tp->tx_stats.packets++; 1806 tp->tx_stats.bytes += txstatus & 0x7ff; 1807 u64_stats_update_end(&tp->tx_stats.syncp); 1808 } 1809 1810 dirty_tx++; 1811 tx_left--; 1812 } 1813 1814 #ifndef RTL8139_NDEBUG 1815 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) { 1816 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n", 1817 dirty_tx, tp->cur_tx); 1818 dirty_tx += NUM_TX_DESC; 1819 } 1820 #endif /* RTL8139_NDEBUG */ 1821 1822 /* only wake the queue if we did work, and the queue is stopped */ 1823 if (tp->dirty_tx != dirty_tx) { 1824 tp->dirty_tx = dirty_tx; 1825 mb(); 1826 netif_wake_queue (dev); 1827 } 1828 } 1829 1830 1831 /* TODO: clean this up! Rx reset need not be this intensive */ 1832 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev, 1833 struct rtl8139_private *tp, void __iomem *ioaddr) 1834 { 1835 u8 tmp8; 1836 #ifdef CONFIG_8139_OLD_RX_RESET 1837 int tmp_work; 1838 #endif 1839 1840 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n", 1841 rx_status); 1842 dev->stats.rx_errors++; 1843 if (!(rx_status & RxStatusOK)) { 1844 if (rx_status & RxTooLong) { 1845 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n", 1846 rx_status); 1847 /* A.C.: The chip hangs here. */ 1848 } 1849 if (rx_status & (RxBadSymbol | RxBadAlign)) 1850 dev->stats.rx_frame_errors++; 1851 if (rx_status & (RxRunt | RxTooLong)) 1852 dev->stats.rx_length_errors++; 1853 if (rx_status & RxCRCErr) 1854 dev->stats.rx_crc_errors++; 1855 } else { 1856 tp->xstats.rx_lost_in_ring++; 1857 } 1858 1859 #ifndef CONFIG_8139_OLD_RX_RESET 1860 tmp8 = RTL_R8 (ChipCmd); 1861 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb); 1862 RTL_W8 (ChipCmd, tmp8); 1863 RTL_W32 (RxConfig, tp->rx_config); 1864 tp->cur_rx = 0; 1865 #else 1866 /* Reset the receiver, based on RealTek recommendation. (Bug?) */ 1867 1868 /* disable receive */ 1869 RTL_W8_F (ChipCmd, CmdTxEnb); 1870 tmp_work = 200; 1871 while (--tmp_work > 0) { 1872 udelay(1); 1873 tmp8 = RTL_R8 (ChipCmd); 1874 if (!(tmp8 & CmdRxEnb)) 1875 break; 1876 } 1877 if (tmp_work <= 0) 1878 netdev_warn(dev, "rx stop wait too long\n"); 1879 /* restart receive */ 1880 tmp_work = 200; 1881 while (--tmp_work > 0) { 1882 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb); 1883 udelay(1); 1884 tmp8 = RTL_R8 (ChipCmd); 1885 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb)) 1886 break; 1887 } 1888 if (tmp_work <= 0) 1889 netdev_warn(dev, "tx/rx enable wait too long\n"); 1890 1891 /* and reinitialize all rx related registers */ 1892 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1893 /* Must enable Tx/Rx before setting transfer thresholds! */ 1894 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1895 1896 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1897 RTL_W32 (RxConfig, tp->rx_config); 1898 tp->cur_rx = 0; 1899 1900 netdev_dbg(dev, "init buffer addresses\n"); 1901 1902 /* Lock Config[01234] and BMCR register writes */ 1903 RTL_W8 (Cfg9346, Cfg9346_Lock); 1904 1905 /* init Rx ring buffer DMA address */ 1906 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1907 1908 /* A.C.: Reset the multicast list. */ 1909 __set_rx_mode (dev); 1910 #endif 1911 } 1912 1913 #if RX_BUF_IDX == 3 1914 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring, 1915 u32 offset, unsigned int size) 1916 { 1917 u32 left = RX_BUF_LEN - offset; 1918 1919 if (size > left) { 1920 skb_copy_to_linear_data(skb, ring + offset, left); 1921 skb_copy_to_linear_data_offset(skb, left, ring, size - left); 1922 } else 1923 skb_copy_to_linear_data(skb, ring + offset, size); 1924 } 1925 #endif 1926 1927 static void rtl8139_isr_ack(struct rtl8139_private *tp) 1928 { 1929 void __iomem *ioaddr = tp->mmio_addr; 1930 u16 status; 1931 1932 status = RTL_R16 (IntrStatus) & RxAckBits; 1933 1934 /* Clear out errors and receive interrupts */ 1935 if (likely(status != 0)) { 1936 if (unlikely(status & (RxFIFOOver | RxOverflow))) { 1937 tp->dev->stats.rx_errors++; 1938 if (status & RxFIFOOver) 1939 tp->dev->stats.rx_fifo_errors++; 1940 } 1941 RTL_W16_F (IntrStatus, RxAckBits); 1942 } 1943 } 1944 1945 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp, 1946 int budget) 1947 { 1948 void __iomem *ioaddr = tp->mmio_addr; 1949 int received = 0; 1950 unsigned char *rx_ring = tp->rx_ring; 1951 unsigned int cur_rx = tp->cur_rx; 1952 unsigned int rx_size = 0; 1953 1954 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 1955 __func__, (u16)cur_rx, 1956 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 1957 1958 while (netif_running(dev) && received < budget && 1959 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { 1960 u32 ring_offset = cur_rx % RX_BUF_LEN; 1961 u32 rx_status; 1962 unsigned int pkt_size; 1963 struct sk_buff *skb; 1964 1965 rmb(); 1966 1967 /* read size+status of next frame from DMA ring buffer */ 1968 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset)); 1969 rx_size = rx_status >> 16; 1970 if (likely(!(dev->features & NETIF_F_RXFCS))) 1971 pkt_size = rx_size - 4; 1972 else 1973 pkt_size = rx_size; 1974 1975 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n", 1976 __func__, rx_status, rx_size, cur_rx); 1977 #if RTL8139_DEBUG > 2 1978 print_hex_dump(KERN_DEBUG, "Frame contents: ", 1979 DUMP_PREFIX_OFFSET, 16, 1, 1980 &rx_ring[ring_offset], 70, true); 1981 #endif 1982 1983 /* Packet copy from FIFO still in progress. 1984 * Theoretically, this should never happen 1985 * since EarlyRx is disabled. 1986 */ 1987 if (unlikely(rx_size == 0xfff0)) { 1988 if (!tp->fifo_copy_timeout) 1989 tp->fifo_copy_timeout = jiffies + 2; 1990 else if (time_after(jiffies, tp->fifo_copy_timeout)) { 1991 netdev_dbg(dev, "hung FIFO. Reset\n"); 1992 rx_size = 0; 1993 goto no_early_rx; 1994 } 1995 netif_dbg(tp, intr, dev, "fifo copy in progress\n"); 1996 tp->xstats.early_rx++; 1997 break; 1998 } 1999 2000 no_early_rx: 2001 tp->fifo_copy_timeout = 0; 2002 2003 /* If Rx err or invalid rx_size/rx_status received 2004 * (which happens if we get lost in the ring), 2005 * Rx process gets reset, so we abort any further 2006 * Rx processing. 2007 */ 2008 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) || 2009 (rx_size < 8) || 2010 (!(rx_status & RxStatusOK)))) { 2011 if ((dev->features & NETIF_F_RXALL) && 2012 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) && 2013 (rx_size >= 8) && 2014 (!(rx_status & RxStatusOK))) { 2015 /* Length is at least mostly OK, but pkt has 2016 * error. I'm hoping we can handle some of these 2017 * errors without resetting the chip. --Ben 2018 */ 2019 dev->stats.rx_errors++; 2020 if (rx_status & RxCRCErr) { 2021 dev->stats.rx_crc_errors++; 2022 goto keep_pkt; 2023 } 2024 if (rx_status & RxRunt) { 2025 dev->stats.rx_length_errors++; 2026 goto keep_pkt; 2027 } 2028 } 2029 rtl8139_rx_err (rx_status, dev, tp, ioaddr); 2030 received = -1; 2031 goto out; 2032 } 2033 2034 keep_pkt: 2035 /* Malloc up new buffer, compatible with net-2e. */ 2036 /* Omit the four octet CRC from the length. */ 2037 2038 skb = napi_alloc_skb(&tp->napi, pkt_size); 2039 if (likely(skb)) { 2040 #if RX_BUF_IDX == 3 2041 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size); 2042 #else 2043 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size); 2044 #endif 2045 skb_put (skb, pkt_size); 2046 2047 skb->protocol = eth_type_trans (skb, dev); 2048 2049 u64_stats_update_begin(&tp->rx_stats.syncp); 2050 tp->rx_stats.packets++; 2051 tp->rx_stats.bytes += pkt_size; 2052 u64_stats_update_end(&tp->rx_stats.syncp); 2053 2054 netif_receive_skb (skb); 2055 } else { 2056 dev->stats.rx_dropped++; 2057 } 2058 received++; 2059 2060 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 2061 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16)); 2062 2063 rtl8139_isr_ack(tp); 2064 } 2065 2066 if (unlikely(!received || rx_size == 0xfff0)) 2067 rtl8139_isr_ack(tp); 2068 2069 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 2070 __func__, cur_rx, 2071 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 2072 2073 tp->cur_rx = cur_rx; 2074 2075 /* 2076 * The receive buffer should be mostly empty. 2077 * Tell NAPI to reenable the Rx irq. 2078 */ 2079 if (tp->fifo_copy_timeout) 2080 received = budget; 2081 2082 out: 2083 return received; 2084 } 2085 2086 2087 static void rtl8139_weird_interrupt (struct net_device *dev, 2088 struct rtl8139_private *tp, 2089 void __iomem *ioaddr, 2090 int status, int link_changed) 2091 { 2092 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status); 2093 2094 assert (dev != NULL); 2095 assert (tp != NULL); 2096 assert (ioaddr != NULL); 2097 2098 /* Update the error count. */ 2099 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2100 RTL_W32 (RxMissed, 0); 2101 2102 if ((status & RxUnderrun) && link_changed && 2103 (tp->drv_flags & HAS_LNK_CHNG)) { 2104 rtl_check_media(dev, 0); 2105 status &= ~RxUnderrun; 2106 } 2107 2108 if (status & (RxUnderrun | RxErr)) 2109 dev->stats.rx_errors++; 2110 2111 if (status & PCSTimeout) 2112 dev->stats.rx_length_errors++; 2113 if (status & RxUnderrun) 2114 dev->stats.rx_fifo_errors++; 2115 if (status & PCIErr) { 2116 u16 pci_cmd_status; 2117 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status); 2118 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status); 2119 2120 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status); 2121 } 2122 } 2123 2124 static int rtl8139_poll(struct napi_struct *napi, int budget) 2125 { 2126 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi); 2127 struct net_device *dev = tp->dev; 2128 void __iomem *ioaddr = tp->mmio_addr; 2129 int work_done; 2130 2131 spin_lock(&tp->rx_lock); 2132 work_done = 0; 2133 if (likely(RTL_R16(IntrStatus) & RxAckBits)) 2134 work_done += rtl8139_rx(dev, tp, budget); 2135 2136 if (work_done < budget) { 2137 unsigned long flags; 2138 2139 spin_lock_irqsave(&tp->lock, flags); 2140 if (napi_complete_done(napi, work_done)) 2141 RTL_W16_F(IntrMask, rtl8139_intr_mask); 2142 spin_unlock_irqrestore(&tp->lock, flags); 2143 } 2144 spin_unlock(&tp->rx_lock); 2145 2146 return work_done; 2147 } 2148 2149 /* The interrupt handler does all of the Rx thread work and cleans up 2150 after the Tx thread. */ 2151 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance) 2152 { 2153 struct net_device *dev = (struct net_device *) dev_instance; 2154 struct rtl8139_private *tp = netdev_priv(dev); 2155 void __iomem *ioaddr = tp->mmio_addr; 2156 u16 status, ackstat; 2157 int link_changed = 0; /* avoid bogus "uninit" warning */ 2158 int handled = 0; 2159 2160 spin_lock (&tp->lock); 2161 status = RTL_R16 (IntrStatus); 2162 2163 /* shared irq? */ 2164 if (unlikely((status & rtl8139_intr_mask) == 0)) 2165 goto out; 2166 2167 handled = 1; 2168 2169 /* h/w no longer present (hotplug?) or major error, bail */ 2170 if (unlikely(status == 0xFFFF)) 2171 goto out; 2172 2173 /* close possible race's with dev_close */ 2174 if (unlikely(!netif_running(dev))) { 2175 RTL_W16 (IntrMask, 0); 2176 goto out; 2177 } 2178 2179 /* Acknowledge all of the current interrupt sources ASAP, but 2180 an first get an additional status bit from CSCR. */ 2181 if (unlikely(status & RxUnderrun)) 2182 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit; 2183 2184 ackstat = status & ~(RxAckBits | TxErr); 2185 if (ackstat) 2186 RTL_W16 (IntrStatus, ackstat); 2187 2188 /* Receive packets are processed by poll routine. 2189 If not running start it now. */ 2190 if (status & RxAckBits){ 2191 if (napi_schedule_prep(&tp->napi)) { 2192 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask); 2193 __napi_schedule(&tp->napi); 2194 } 2195 } 2196 2197 /* Check uncommon events with one test. */ 2198 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr))) 2199 rtl8139_weird_interrupt (dev, tp, ioaddr, 2200 status, link_changed); 2201 2202 if (status & (TxOK | TxErr)) { 2203 rtl8139_tx_interrupt (dev, tp, ioaddr); 2204 if (status & TxErr) 2205 RTL_W16 (IntrStatus, TxErr); 2206 } 2207 out: 2208 spin_unlock (&tp->lock); 2209 2210 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n", 2211 RTL_R16(IntrStatus)); 2212 return IRQ_RETVAL(handled); 2213 } 2214 2215 #ifdef CONFIG_NET_POLL_CONTROLLER 2216 /* 2217 * Polling receive - used by netconsole and other diagnostic tools 2218 * to allow network i/o with interrupts disabled. 2219 */ 2220 static void rtl8139_poll_controller(struct net_device *dev) 2221 { 2222 struct rtl8139_private *tp = netdev_priv(dev); 2223 const int irq = tp->pci_dev->irq; 2224 2225 disable_irq_nosync(irq); 2226 rtl8139_interrupt(irq, dev); 2227 enable_irq(irq); 2228 } 2229 #endif 2230 2231 static int rtl8139_set_mac_address(struct net_device *dev, void *p) 2232 { 2233 struct rtl8139_private *tp = netdev_priv(dev); 2234 void __iomem *ioaddr = tp->mmio_addr; 2235 struct sockaddr *addr = p; 2236 2237 if (!is_valid_ether_addr(addr->sa_data)) 2238 return -EADDRNOTAVAIL; 2239 2240 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2241 2242 spin_lock_irq(&tp->lock); 2243 2244 RTL_W8_F(Cfg9346, Cfg9346_Unlock); 2245 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0))); 2246 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4))); 2247 RTL_W8_F(Cfg9346, Cfg9346_Lock); 2248 2249 spin_unlock_irq(&tp->lock); 2250 2251 return 0; 2252 } 2253 2254 static int rtl8139_close (struct net_device *dev) 2255 { 2256 struct rtl8139_private *tp = netdev_priv(dev); 2257 void __iomem *ioaddr = tp->mmio_addr; 2258 unsigned long flags; 2259 2260 netif_stop_queue(dev); 2261 napi_disable(&tp->napi); 2262 2263 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n", 2264 RTL_R16(IntrStatus)); 2265 2266 spin_lock_irqsave (&tp->lock, flags); 2267 2268 /* Stop the chip's Tx and Rx DMA processes. */ 2269 RTL_W8 (ChipCmd, 0); 2270 2271 /* Disable interrupts by clearing the interrupt mask. */ 2272 RTL_W16 (IntrMask, 0); 2273 2274 /* Update the error counts. */ 2275 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2276 RTL_W32 (RxMissed, 0); 2277 2278 spin_unlock_irqrestore (&tp->lock, flags); 2279 2280 free_irq(tp->pci_dev->irq, dev); 2281 2282 rtl8139_tx_clear (tp); 2283 2284 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 2285 tp->rx_ring, tp->rx_ring_dma); 2286 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 2287 tp->tx_bufs, tp->tx_bufs_dma); 2288 tp->rx_ring = NULL; 2289 tp->tx_bufs = NULL; 2290 2291 /* Green! Put the chip in low-power mode. */ 2292 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2293 2294 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 2295 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 2296 2297 return 0; 2298 } 2299 2300 2301 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to 2302 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and 2303 other threads or interrupts aren't messing with the 8139. */ 2304 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2305 { 2306 struct rtl8139_private *tp = netdev_priv(dev); 2307 void __iomem *ioaddr = tp->mmio_addr; 2308 2309 spin_lock_irq(&tp->lock); 2310 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 2311 u8 cfg3 = RTL_R8 (Config3); 2312 u8 cfg5 = RTL_R8 (Config5); 2313 2314 wol->supported = WAKE_PHY | WAKE_MAGIC 2315 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; 2316 2317 wol->wolopts = 0; 2318 if (cfg3 & Cfg3_LinkUp) 2319 wol->wolopts |= WAKE_PHY; 2320 if (cfg3 & Cfg3_Magic) 2321 wol->wolopts |= WAKE_MAGIC; 2322 /* (KON)FIXME: See how netdev_set_wol() handles the 2323 following constants. */ 2324 if (cfg5 & Cfg5_UWF) 2325 wol->wolopts |= WAKE_UCAST; 2326 if (cfg5 & Cfg5_MWF) 2327 wol->wolopts |= WAKE_MCAST; 2328 if (cfg5 & Cfg5_BWF) 2329 wol->wolopts |= WAKE_BCAST; 2330 } 2331 spin_unlock_irq(&tp->lock); 2332 } 2333 2334 2335 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes 2336 that wol points to kernel memory and other threads or interrupts 2337 aren't messing with the 8139. */ 2338 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2339 { 2340 struct rtl8139_private *tp = netdev_priv(dev); 2341 void __iomem *ioaddr = tp->mmio_addr; 2342 u32 support; 2343 u8 cfg3, cfg5; 2344 2345 support = ((rtl_chip_info[tp->chipset].flags & HasLWake) 2346 ? (WAKE_PHY | WAKE_MAGIC 2347 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST) 2348 : 0); 2349 if (wol->wolopts & ~support) 2350 return -EINVAL; 2351 2352 spin_lock_irq(&tp->lock); 2353 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic); 2354 if (wol->wolopts & WAKE_PHY) 2355 cfg3 |= Cfg3_LinkUp; 2356 if (wol->wolopts & WAKE_MAGIC) 2357 cfg3 |= Cfg3_Magic; 2358 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2359 RTL_W8 (Config3, cfg3); 2360 RTL_W8 (Cfg9346, Cfg9346_Lock); 2361 2362 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF); 2363 /* (KON)FIXME: These are untested. We may have to set the 2364 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no 2365 documentation. */ 2366 if (wol->wolopts & WAKE_UCAST) 2367 cfg5 |= Cfg5_UWF; 2368 if (wol->wolopts & WAKE_MCAST) 2369 cfg5 |= Cfg5_MWF; 2370 if (wol->wolopts & WAKE_BCAST) 2371 cfg5 |= Cfg5_BWF; 2372 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */ 2373 spin_unlock_irq(&tp->lock); 2374 2375 return 0; 2376 } 2377 2378 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2379 { 2380 struct rtl8139_private *tp = netdev_priv(dev); 2381 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2382 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2383 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 2384 } 2385 2386 static int rtl8139_get_link_ksettings(struct net_device *dev, 2387 struct ethtool_link_ksettings *cmd) 2388 { 2389 struct rtl8139_private *tp = netdev_priv(dev); 2390 spin_lock_irq(&tp->lock); 2391 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 2392 spin_unlock_irq(&tp->lock); 2393 return 0; 2394 } 2395 2396 static int rtl8139_set_link_ksettings(struct net_device *dev, 2397 const struct ethtool_link_ksettings *cmd) 2398 { 2399 struct rtl8139_private *tp = netdev_priv(dev); 2400 int rc; 2401 spin_lock_irq(&tp->lock); 2402 rc = mii_ethtool_set_link_ksettings(&tp->mii, cmd); 2403 spin_unlock_irq(&tp->lock); 2404 return rc; 2405 } 2406 2407 static int rtl8139_nway_reset(struct net_device *dev) 2408 { 2409 struct rtl8139_private *tp = netdev_priv(dev); 2410 return mii_nway_restart(&tp->mii); 2411 } 2412 2413 static u32 rtl8139_get_link(struct net_device *dev) 2414 { 2415 struct rtl8139_private *tp = netdev_priv(dev); 2416 return mii_link_ok(&tp->mii); 2417 } 2418 2419 static u32 rtl8139_get_msglevel(struct net_device *dev) 2420 { 2421 struct rtl8139_private *tp = netdev_priv(dev); 2422 return tp->msg_enable; 2423 } 2424 2425 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum) 2426 { 2427 struct rtl8139_private *tp = netdev_priv(dev); 2428 tp->msg_enable = datum; 2429 } 2430 2431 static int rtl8139_get_regs_len(struct net_device *dev) 2432 { 2433 struct rtl8139_private *tp; 2434 /* TODO: we are too slack to do reg dumping for pio, for now */ 2435 if (use_io) 2436 return 0; 2437 tp = netdev_priv(dev); 2438 return tp->regs_len; 2439 } 2440 2441 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) 2442 { 2443 struct rtl8139_private *tp; 2444 2445 /* TODO: we are too slack to do reg dumping for pio, for now */ 2446 if (use_io) 2447 return; 2448 tp = netdev_priv(dev); 2449 2450 regs->version = RTL_REGS_VER; 2451 2452 spin_lock_irq(&tp->lock); 2453 memcpy_fromio(regbuf, tp->mmio_addr, regs->len); 2454 spin_unlock_irq(&tp->lock); 2455 } 2456 2457 static int rtl8139_get_sset_count(struct net_device *dev, int sset) 2458 { 2459 switch (sset) { 2460 case ETH_SS_STATS: 2461 return RTL_NUM_STATS; 2462 default: 2463 return -EOPNOTSUPP; 2464 } 2465 } 2466 2467 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2468 { 2469 struct rtl8139_private *tp = netdev_priv(dev); 2470 2471 data[0] = tp->xstats.early_rx; 2472 data[1] = tp->xstats.tx_buf_mapped; 2473 data[2] = tp->xstats.tx_timeouts; 2474 data[3] = tp->xstats.rx_lost_in_ring; 2475 } 2476 2477 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2478 { 2479 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2480 } 2481 2482 static const struct ethtool_ops rtl8139_ethtool_ops = { 2483 .get_drvinfo = rtl8139_get_drvinfo, 2484 .get_regs_len = rtl8139_get_regs_len, 2485 .get_regs = rtl8139_get_regs, 2486 .nway_reset = rtl8139_nway_reset, 2487 .get_link = rtl8139_get_link, 2488 .get_msglevel = rtl8139_get_msglevel, 2489 .set_msglevel = rtl8139_set_msglevel, 2490 .get_wol = rtl8139_get_wol, 2491 .set_wol = rtl8139_set_wol, 2492 .get_strings = rtl8139_get_strings, 2493 .get_sset_count = rtl8139_get_sset_count, 2494 .get_ethtool_stats = rtl8139_get_ethtool_stats, 2495 .get_link_ksettings = rtl8139_get_link_ksettings, 2496 .set_link_ksettings = rtl8139_set_link_ksettings, 2497 }; 2498 2499 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2500 { 2501 struct rtl8139_private *tp = netdev_priv(dev); 2502 int rc; 2503 2504 if (!netif_running(dev)) 2505 return -EINVAL; 2506 2507 spin_lock_irq(&tp->lock); 2508 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL); 2509 spin_unlock_irq(&tp->lock); 2510 2511 return rc; 2512 } 2513 2514 2515 static void 2516 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 2517 { 2518 struct rtl8139_private *tp = netdev_priv(dev); 2519 void __iomem *ioaddr = tp->mmio_addr; 2520 unsigned long flags; 2521 unsigned int start; 2522 2523 if (netif_running(dev)) { 2524 spin_lock_irqsave (&tp->lock, flags); 2525 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2526 RTL_W32 (RxMissed, 0); 2527 spin_unlock_irqrestore (&tp->lock, flags); 2528 } 2529 2530 netdev_stats_to_stats64(stats, &dev->stats); 2531 2532 do { 2533 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 2534 stats->rx_packets = tp->rx_stats.packets; 2535 stats->rx_bytes = tp->rx_stats.bytes; 2536 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 2537 2538 do { 2539 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 2540 stats->tx_packets = tp->tx_stats.packets; 2541 stats->tx_bytes = tp->tx_stats.bytes; 2542 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 2543 } 2544 2545 /* Set or clear the multicast filter for this adaptor. 2546 This routine is not state sensitive and need not be SMP locked. */ 2547 2548 static void __set_rx_mode (struct net_device *dev) 2549 { 2550 struct rtl8139_private *tp = netdev_priv(dev); 2551 void __iomem *ioaddr = tp->mmio_addr; 2552 u32 mc_filter[2]; /* Multicast hash filter */ 2553 int rx_mode; 2554 u32 tmp; 2555 2556 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n", 2557 dev->flags, RTL_R32(RxConfig)); 2558 2559 /* Note: do not reorder, GCC is clever about common statements. */ 2560 if (dev->flags & IFF_PROMISC) { 2561 rx_mode = 2562 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 2563 AcceptAllPhys; 2564 mc_filter[1] = mc_filter[0] = 0xffffffff; 2565 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2566 (dev->flags & IFF_ALLMULTI)) { 2567 /* Too many to filter perfectly -- accept all multicasts. */ 2568 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 2569 mc_filter[1] = mc_filter[0] = 0xffffffff; 2570 } else { 2571 struct netdev_hw_addr *ha; 2572 rx_mode = AcceptBroadcast | AcceptMyPhys; 2573 mc_filter[1] = mc_filter[0] = 0; 2574 netdev_for_each_mc_addr(ha, dev) { 2575 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2576 2577 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2578 rx_mode |= AcceptMulticast; 2579 } 2580 } 2581 2582 if (dev->features & NETIF_F_RXALL) 2583 rx_mode |= (AcceptErr | AcceptRunt); 2584 2585 /* We can safely update without stopping the chip. */ 2586 tmp = rtl8139_rx_config | rx_mode; 2587 if (tp->rx_config != tmp) { 2588 RTL_W32_F (RxConfig, tmp); 2589 tp->rx_config = tmp; 2590 } 2591 RTL_W32_F (MAR0 + 0, mc_filter[0]); 2592 RTL_W32_F (MAR0 + 4, mc_filter[1]); 2593 } 2594 2595 static void rtl8139_set_rx_mode (struct net_device *dev) 2596 { 2597 unsigned long flags; 2598 struct rtl8139_private *tp = netdev_priv(dev); 2599 2600 spin_lock_irqsave (&tp->lock, flags); 2601 __set_rx_mode(dev); 2602 spin_unlock_irqrestore (&tp->lock, flags); 2603 } 2604 2605 #ifdef CONFIG_PM 2606 2607 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state) 2608 { 2609 struct net_device *dev = pci_get_drvdata (pdev); 2610 struct rtl8139_private *tp = netdev_priv(dev); 2611 void __iomem *ioaddr = tp->mmio_addr; 2612 unsigned long flags; 2613 2614 pci_save_state (pdev); 2615 2616 if (!netif_running (dev)) 2617 return 0; 2618 2619 netif_device_detach (dev); 2620 2621 spin_lock_irqsave (&tp->lock, flags); 2622 2623 /* Disable interrupts, stop Tx and Rx. */ 2624 RTL_W16 (IntrMask, 0); 2625 RTL_W8 (ChipCmd, 0); 2626 2627 /* Update the error counts. */ 2628 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2629 RTL_W32 (RxMissed, 0); 2630 2631 spin_unlock_irqrestore (&tp->lock, flags); 2632 2633 pci_set_power_state (pdev, PCI_D3hot); 2634 2635 return 0; 2636 } 2637 2638 2639 static int rtl8139_resume (struct pci_dev *pdev) 2640 { 2641 struct net_device *dev = pci_get_drvdata (pdev); 2642 2643 pci_restore_state (pdev); 2644 if (!netif_running (dev)) 2645 return 0; 2646 pci_set_power_state (pdev, PCI_D0); 2647 rtl8139_init_ring (dev); 2648 rtl8139_hw_start (dev); 2649 netif_device_attach (dev); 2650 return 0; 2651 } 2652 2653 #endif /* CONFIG_PM */ 2654 2655 2656 static struct pci_driver rtl8139_pci_driver = { 2657 .name = DRV_NAME, 2658 .id_table = rtl8139_pci_tbl, 2659 .probe = rtl8139_init_one, 2660 .remove = rtl8139_remove_one, 2661 #ifdef CONFIG_PM 2662 .suspend = rtl8139_suspend, 2663 .resume = rtl8139_resume, 2664 #endif /* CONFIG_PM */ 2665 }; 2666 2667 2668 static int __init rtl8139_init_module (void) 2669 { 2670 /* when we're a module, we always print a version message, 2671 * even if no 8139 board is found. 2672 */ 2673 #ifdef MODULE 2674 pr_info(RTL8139_DRIVER_NAME "\n"); 2675 #endif 2676 2677 return pci_register_driver(&rtl8139_pci_driver); 2678 } 2679 2680 2681 static void __exit rtl8139_cleanup_module (void) 2682 { 2683 pci_unregister_driver (&rtl8139_pci_driver); 2684 } 2685 2686 2687 module_init(rtl8139_init_module); 2688 module_exit(rtl8139_cleanup_module); 2689