1 /* 2 3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux. 4 5 Maintained by Jeff Garzik <jgarzik@pobox.com> 6 Copyright 2000-2002 Jeff Garzik 7 8 Much code comes from Donald Becker's rtl8139.c driver, 9 versions 1.13 and older. This driver was originally based 10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13: 11 12 -----<snip>----- 13 14 Written 1997-2001 by Donald Becker. 15 This software may be used and distributed according to the 16 terms of the GNU General Public License (GPL), incorporated 17 herein by reference. Drivers based on or derived from this 18 code fall under the GPL and must retain the authorship, 19 copyright and license notice. This file is not a complete 20 program and may only be used when the entire operating 21 system is licensed under the GPL. 22 23 This driver is for boards based on the RTL8129 and RTL8139 24 PCI ethernet chips. 25 26 The author may be reached as becker@scyld.com, or C/O Scyld 27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis 28 MD 21403 29 30 Support and updates available at 31 http://www.scyld.com/network/rtl8139.html 32 33 Twister-tuning table provided by Kinston 34 <shangh@realtek.com.tw>. 35 36 -----<snip>----- 37 38 This software may be used and distributed according to the terms 39 of the GNU General Public License, incorporated herein by reference. 40 41 Contributors: 42 43 Donald Becker - he wrote the original driver, kudos to him! 44 (but please don't e-mail him for support, this isn't his driver) 45 46 Tigran Aivazian - bug fixes, skbuff free cleanup 47 48 Martin Mares - suggestions for PCI cleanup 49 50 David S. Miller - PCI DMA and softnet updates 51 52 Ernst Gill - fixes ported from BSD driver 53 54 Daniel Kobras - identified specific locations of 55 posted MMIO write bugginess 56 57 Gerard Sharp - bug fix, testing and feedback 58 59 David Ford - Rx ring wrap fix 60 61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me 62 to find and fix a crucial bug on older chipsets. 63 64 Donald Becker/Chris Butterworth/Marcus Westergren - 65 Noticed various Rx packet size-related buglets. 66 67 Santiago Garcia Mantinan - testing and feedback 68 69 Jens David - 2.2.x kernel backports 70 71 Martin Dennett - incredibly helpful insight on undocumented 72 features of the 8139 chips 73 74 Jean-Jacques Michel - bug fix 75 76 Tobias Ringström - Rx interrupt status checking suggestion 77 78 Andrew Morton - Clear blocked signals, avoid 79 buffer overrun setting current->comm. 80 81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls 82 83 Robert Kuebel - Save kernel thread from dying on any signal. 84 85 Submitting bug reports: 86 87 "rtl8139-diag -mmmaaavvveefN" output 88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log 89 90 */ 91 92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 93 94 #define DRV_NAME "8139too" 95 #define DRV_VERSION "0.9.28" 96 97 98 #include <linux/module.h> 99 #include <linux/kernel.h> 100 #include <linux/compiler.h> 101 #include <linux/pci.h> 102 #include <linux/init.h> 103 #include <linux/interrupt.h> 104 #include <linux/netdevice.h> 105 #include <linux/etherdevice.h> 106 #include <linux/rtnetlink.h> 107 #include <linux/delay.h> 108 #include <linux/ethtool.h> 109 #include <linux/mii.h> 110 #include <linux/completion.h> 111 #include <linux/crc32.h> 112 #include <linux/io.h> 113 #include <linux/uaccess.h> 114 #include <linux/gfp.h> 115 #include <linux/if_vlan.h> 116 #include <asm/irq.h> 117 118 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION 119 120 /* Default Message level */ 121 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 122 NETIF_MSG_PROBE | \ 123 NETIF_MSG_LINK) 124 125 126 /* define to 1, 2 or 3 to enable copious debugging info */ 127 #define RTL8139_DEBUG 0 128 129 /* define to 1 to disable lightweight runtime debugging checks */ 130 #undef RTL8139_NDEBUG 131 132 133 #ifdef RTL8139_NDEBUG 134 # define assert(expr) do {} while (0) 135 #else 136 # define assert(expr) \ 137 if (unlikely(!(expr))) { \ 138 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \ 139 #expr, __FILE__, __func__, __LINE__); \ 140 } 141 #endif 142 143 144 /* A few user-configurable values. */ 145 /* media options */ 146 #define MAX_UNITS 8 147 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 148 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 149 150 /* Whether to use MMIO or PIO. Default to MMIO. */ 151 #ifdef CONFIG_8139TOO_PIO 152 static bool use_io = true; 153 #else 154 static bool use_io = false; 155 #endif 156 157 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 158 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 159 static int multicast_filter_limit = 32; 160 161 /* bitmapped message enable number */ 162 static int debug = -1; 163 164 /* 165 * Receive ring size 166 * Warning: 64K ring has hardware issues and may lock up. 167 */ 168 #if defined(CONFIG_SH_DREAMCAST) 169 #define RX_BUF_IDX 0 /* 8K ring */ 170 #else 171 #define RX_BUF_IDX 2 /* 32K ring */ 172 #endif 173 #define RX_BUF_LEN (8192 << RX_BUF_IDX) 174 #define RX_BUF_PAD 16 175 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */ 176 177 #if RX_BUF_LEN == 65536 178 #define RX_BUF_TOT_LEN RX_BUF_LEN 179 #else 180 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD) 181 #endif 182 183 /* Number of Tx descriptor registers. */ 184 #define NUM_TX_DESC 4 185 186 /* max supported ethernet frame size -- must be at least (dev->mtu+18+4).*/ 187 #define MAX_ETH_FRAME_SIZE 1792 188 189 /* max supported payload size */ 190 #define MAX_ETH_DATA_SIZE (MAX_ETH_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN) 191 192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+18+4). */ 193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE 194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) 195 196 /* PCI Tuning Parameters 197 Threshold is bytes transferred to chip before transmission starts. */ 198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 199 200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ 201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ 202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */ 203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */ 205 206 /* Operational parameters that usually are not changed. */ 207 /* Time in jiffies before concluding the transmitter is hung. */ 208 #define TX_TIMEOUT (6*HZ) 209 210 211 enum { 212 HAS_MII_XCVR = 0x010000, 213 HAS_CHIP_XCVR = 0x020000, 214 HAS_LNK_CHNG = 0x040000, 215 }; 216 217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */ 218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */ 219 #define RTL_MIN_IO_SIZE 0x80 220 #define RTL8139B_IO_SIZE 256 221 222 #define RTL8129_CAPS HAS_MII_XCVR 223 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG) 224 225 typedef enum { 226 RTL8139 = 0, 227 RTL8129, 228 } board_t; 229 230 231 /* indexed by board_t, above */ 232 static const struct { 233 const char *name; 234 u32 hw_flags; 235 } board_info[] = { 236 { "RealTek RTL8139", RTL8139_CAPS }, 237 { "RealTek RTL8129", RTL8129_CAPS }, 238 }; 239 240 241 static const struct pci_device_id rtl8139_pci_tbl[] = { 242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 261 262 #ifdef CONFIG_SH_SECUREEDGE5410 263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */ 264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 265 #endif 266 #ifdef CONFIG_8139TOO_8129 267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 }, 268 #endif 269 270 /* some crazy cards report invalid vendor ids like 271 * 0x0001 here. The other ids are valid and constant, 272 * so we simply don't match on the main vendor id. 273 */ 274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 }, 275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 }, 276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 }, 277 278 {0,} 279 }; 280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl); 281 282 static struct { 283 const char str[ETH_GSTRING_LEN]; 284 } ethtool_stats_keys[] = { 285 { "early_rx" }, 286 { "tx_buf_mapped" }, 287 { "tx_timeouts" }, 288 { "rx_lost_in_ring" }, 289 }; 290 291 /* The rest of these values should never change. */ 292 293 /* Symbolic offsets to registers. */ 294 enum RTL8139_registers { 295 MAC0 = 0, /* Ethernet hardware address. */ 296 MAR0 = 8, /* Multicast filter. */ 297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ 298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 299 RxBuf = 0x30, 300 ChipCmd = 0x37, 301 RxBufPtr = 0x38, 302 RxBufAddr = 0x3A, 303 IntrMask = 0x3C, 304 IntrStatus = 0x3E, 305 TxConfig = 0x40, 306 RxConfig = 0x44, 307 Timer = 0x48, /* A general-purpose counter. */ 308 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 309 Cfg9346 = 0x50, 310 Config0 = 0x51, 311 Config1 = 0x52, 312 TimerInt = 0x54, 313 MediaStatus = 0x58, 314 Config3 = 0x59, 315 Config4 = 0x5A, /* absent on RTL-8139A */ 316 HltClk = 0x5B, 317 MultiIntr = 0x5C, 318 TxSummary = 0x60, 319 BasicModeCtrl = 0x62, 320 BasicModeStatus = 0x64, 321 NWayAdvert = 0x66, 322 NWayLPAR = 0x68, 323 NWayExpansion = 0x6A, 324 /* Undocumented registers, but required for proper operation. */ 325 FIFOTMS = 0x70, /* FIFO Control and test. */ 326 CSCR = 0x74, /* Chip Status and Configuration Register. */ 327 PARA78 = 0x78, 328 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */ 329 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 330 Config5 = 0xD8, /* absent on RTL-8139A */ 331 }; 332 333 enum ClearBitMasks { 334 MultiIntrClear = 0xF000, 335 ChipCmdClear = 0xE2, 336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 337 }; 338 339 enum ChipCmdBits { 340 CmdReset = 0x10, 341 CmdRxEnb = 0x08, 342 CmdTxEnb = 0x04, 343 RxBufEmpty = 0x01, 344 }; 345 346 /* Interrupt register bits, using my own meaningful names. */ 347 enum IntrStatusBits { 348 PCIErr = 0x8000, 349 PCSTimeout = 0x4000, 350 RxFIFOOver = 0x40, 351 RxUnderrun = 0x20, 352 RxOverflow = 0x10, 353 TxErr = 0x08, 354 TxOK = 0x04, 355 RxErr = 0x02, 356 RxOK = 0x01, 357 358 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 359 }; 360 361 enum TxStatusBits { 362 TxHostOwns = 0x2000, 363 TxUnderrun = 0x4000, 364 TxStatOK = 0x8000, 365 TxOutOfWindow = 0x20000000, 366 TxAborted = 0x40000000, 367 TxCarrierLost = 0x80000000, 368 }; 369 enum RxStatusBits { 370 RxMulticast = 0x8000, 371 RxPhysical = 0x4000, 372 RxBroadcast = 0x2000, 373 RxBadSymbol = 0x0020, 374 RxRunt = 0x0010, 375 RxTooLong = 0x0008, 376 RxCRCErr = 0x0004, 377 RxBadAlign = 0x0002, 378 RxStatusOK = 0x0001, 379 }; 380 381 /* Bits in RxConfig. */ 382 enum rx_mode_bits { 383 AcceptErr = 0x20, 384 AcceptRunt = 0x10, 385 AcceptBroadcast = 0x08, 386 AcceptMulticast = 0x04, 387 AcceptMyPhys = 0x02, 388 AcceptAllPhys = 0x01, 389 }; 390 391 /* Bits in TxConfig. */ 392 enum tx_config_bits { 393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 394 TxIFGShift = 24, 395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 399 400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 401 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */ 402 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */ 404 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */ 405 406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 407 }; 408 409 /* Bits in Config1 */ 410 enum Config1Bits { 411 Cfg1_PM_Enable = 0x01, 412 Cfg1_VPD_Enable = 0x02, 413 Cfg1_PIO = 0x04, 414 Cfg1_MMIO = 0x08, 415 LWAKE = 0x10, /* not on 8139, 8139A */ 416 Cfg1_Driver_Load = 0x20, 417 Cfg1_LED0 = 0x40, 418 Cfg1_LED1 = 0x80, 419 SLEEP = (1 << 1), /* only on 8139, 8139A */ 420 PWRDN = (1 << 0), /* only on 8139, 8139A */ 421 }; 422 423 /* Bits in Config3 */ 424 enum Config3Bits { 425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 433 }; 434 435 /* Bits in Config4 */ 436 enum Config4Bits { 437 LWPTN = (1 << 2), /* not on 8139, 8139A */ 438 }; 439 440 /* Bits in Config5 */ 441 enum Config5Bits { 442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 445 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */ 446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 449 }; 450 451 enum RxConfigBits { 452 /* rx fifo threshold */ 453 RxCfgFIFOShift = 13, 454 RxCfgFIFONone = (7 << RxCfgFIFOShift), 455 456 /* Max DMA burst */ 457 RxCfgDMAShift = 8, 458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 459 460 /* rx ring buffer length */ 461 RxCfgRcv8K = 0, 462 RxCfgRcv16K = (1 << 11), 463 RxCfgRcv32K = (1 << 12), 464 RxCfgRcv64K = (1 << 11) | (1 << 12), 465 466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 467 RxNoWrap = (1 << 7), 468 }; 469 470 /* Twister tuning parameters from RealTek. 471 Completely undocumented, but required to tune bad links on some boards. */ 472 enum CSCRBits { 473 CSCR_LinkOKBit = 0x0400, 474 CSCR_LinkChangeBit = 0x0800, 475 CSCR_LinkStatusBits = 0x0f000, 476 CSCR_LinkDownOffCmd = 0x003c0, 477 CSCR_LinkDownCmd = 0x0f3c0, 478 }; 479 480 enum Cfg9346Bits { 481 Cfg9346_Lock = 0x00, 482 Cfg9346_Unlock = 0xC0, 483 }; 484 485 typedef enum { 486 CH_8139 = 0, 487 CH_8139_K, 488 CH_8139A, 489 CH_8139A_G, 490 CH_8139B, 491 CH_8130, 492 CH_8139C, 493 CH_8100, 494 CH_8100B_8139D, 495 CH_8101, 496 } chip_t; 497 498 enum chip_flags { 499 HasHltClk = (1 << 0), 500 HasLWake = (1 << 1), 501 }; 502 503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 506 507 /* directly indexed by chip_t, above */ 508 static const struct { 509 const char *name; 510 u32 version; /* from RTL8139C/RTL8139D docs */ 511 u32 flags; 512 } rtl_chip_info[] = { 513 { "RTL-8139", 514 HW_REVID(1, 0, 0, 0, 0, 0, 0), 515 HasHltClk, 516 }, 517 518 { "RTL-8139 rev K", 519 HW_REVID(1, 1, 0, 0, 0, 0, 0), 520 HasHltClk, 521 }, 522 523 { "RTL-8139A", 524 HW_REVID(1, 1, 1, 0, 0, 0, 0), 525 HasHltClk, /* XXX undocumented? */ 526 }, 527 528 { "RTL-8139A rev G", 529 HW_REVID(1, 1, 1, 0, 0, 1, 0), 530 HasHltClk, /* XXX undocumented? */ 531 }, 532 533 { "RTL-8139B", 534 HW_REVID(1, 1, 1, 1, 0, 0, 0), 535 HasLWake, 536 }, 537 538 { "RTL-8130", 539 HW_REVID(1, 1, 1, 1, 1, 0, 0), 540 HasLWake, 541 }, 542 543 { "RTL-8139C", 544 HW_REVID(1, 1, 1, 0, 1, 0, 0), 545 HasLWake, 546 }, 547 548 { "RTL-8100", 549 HW_REVID(1, 1, 1, 1, 0, 1, 0), 550 HasLWake, 551 }, 552 553 { "RTL-8100B/8139D", 554 HW_REVID(1, 1, 1, 0, 1, 0, 1), 555 HasHltClk /* XXX undocumented? */ 556 | HasLWake, 557 }, 558 559 { "RTL-8101", 560 HW_REVID(1, 1, 1, 0, 1, 1, 1), 561 HasLWake, 562 }, 563 }; 564 565 struct rtl_extra_stats { 566 unsigned long early_rx; 567 unsigned long tx_buf_mapped; 568 unsigned long tx_timeouts; 569 unsigned long rx_lost_in_ring; 570 }; 571 572 struct rtl8139_stats { 573 u64 packets; 574 u64 bytes; 575 struct u64_stats_sync syncp; 576 }; 577 578 struct rtl8139_private { 579 void __iomem *mmio_addr; 580 int drv_flags; 581 struct pci_dev *pci_dev; 582 u32 msg_enable; 583 struct napi_struct napi; 584 struct net_device *dev; 585 586 unsigned char *rx_ring; 587 unsigned int cur_rx; /* RX buf index of next pkt */ 588 struct rtl8139_stats rx_stats; 589 dma_addr_t rx_ring_dma; 590 591 unsigned int tx_flag; 592 unsigned long cur_tx; 593 unsigned long dirty_tx; 594 struct rtl8139_stats tx_stats; 595 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */ 596 unsigned char *tx_bufs; /* Tx bounce buffer region. */ 597 dma_addr_t tx_bufs_dma; 598 599 signed char phys[4]; /* MII device addresses. */ 600 601 /* Twister tune state. */ 602 char twistie, twist_row, twist_col; 603 604 unsigned int watchdog_fired : 1; 605 unsigned int default_port : 4; /* Last dev->if_port value. */ 606 unsigned int have_thread : 1; 607 608 spinlock_t lock; 609 spinlock_t rx_lock; 610 611 chip_t chipset; 612 u32 rx_config; 613 struct rtl_extra_stats xstats; 614 615 struct delayed_work thread; 616 617 struct mii_if_info mii; 618 unsigned int regs_len; 619 unsigned long fifo_copy_timeout; 620 }; 621 622 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>"); 623 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver"); 624 MODULE_LICENSE("GPL"); 625 MODULE_VERSION(DRV_VERSION); 626 627 module_param(use_io, bool, 0); 628 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO"); 629 module_param(multicast_filter_limit, int, 0); 630 module_param_array(media, int, NULL, 0); 631 module_param_array(full_duplex, int, NULL, 0); 632 module_param(debug, int, 0); 633 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number"); 634 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses"); 635 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps"); 636 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)"); 637 638 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len); 639 static int rtl8139_open (struct net_device *dev); 640 static int mdio_read (struct net_device *dev, int phy_id, int location); 641 static void mdio_write (struct net_device *dev, int phy_id, int location, 642 int val); 643 static void rtl8139_start_thread(struct rtl8139_private *tp); 644 static void rtl8139_tx_timeout (struct net_device *dev); 645 static void rtl8139_init_ring (struct net_device *dev); 646 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 647 struct net_device *dev); 648 #ifdef CONFIG_NET_POLL_CONTROLLER 649 static void rtl8139_poll_controller(struct net_device *dev); 650 #endif 651 static int rtl8139_set_mac_address(struct net_device *dev, void *p); 652 static int rtl8139_poll(struct napi_struct *napi, int budget); 653 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance); 654 static int rtl8139_close (struct net_device *dev); 655 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 656 static void rtl8139_get_stats64(struct net_device *dev, 657 struct rtnl_link_stats64 *stats); 658 static void rtl8139_set_rx_mode (struct net_device *dev); 659 static void __set_rx_mode (struct net_device *dev); 660 static void rtl8139_hw_start (struct net_device *dev); 661 static void rtl8139_thread (struct work_struct *work); 662 static void rtl8139_tx_timeout_task(struct work_struct *work); 663 static const struct ethtool_ops rtl8139_ethtool_ops; 664 665 /* write MMIO register, with flush */ 666 /* Flush avoids rtl8139 bug w/ posted MMIO writes */ 667 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0) 668 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0) 669 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0) 670 671 /* write MMIO register */ 672 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg)) 673 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg)) 674 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg)) 675 676 /* read MMIO register */ 677 #define RTL_R8(reg) ioread8 (ioaddr + (reg)) 678 #define RTL_R16(reg) ioread16 (ioaddr + (reg)) 679 #define RTL_R32(reg) ioread32 (ioaddr + (reg)) 680 681 682 static const u16 rtl8139_intr_mask = 683 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | 684 TxErr | TxOK | RxErr | RxOK; 685 686 static const u16 rtl8139_norx_intr_mask = 687 PCIErr | PCSTimeout | RxUnderrun | 688 TxErr | TxOK | RxErr ; 689 690 #if RX_BUF_IDX == 0 691 static const unsigned int rtl8139_rx_config = 692 RxCfgRcv8K | RxNoWrap | 693 (RX_FIFO_THRESH << RxCfgFIFOShift) | 694 (RX_DMA_BURST << RxCfgDMAShift); 695 #elif RX_BUF_IDX == 1 696 static const unsigned int rtl8139_rx_config = 697 RxCfgRcv16K | RxNoWrap | 698 (RX_FIFO_THRESH << RxCfgFIFOShift) | 699 (RX_DMA_BURST << RxCfgDMAShift); 700 #elif RX_BUF_IDX == 2 701 static const unsigned int rtl8139_rx_config = 702 RxCfgRcv32K | RxNoWrap | 703 (RX_FIFO_THRESH << RxCfgFIFOShift) | 704 (RX_DMA_BURST << RxCfgDMAShift); 705 #elif RX_BUF_IDX == 3 706 static const unsigned int rtl8139_rx_config = 707 RxCfgRcv64K | 708 (RX_FIFO_THRESH << RxCfgFIFOShift) | 709 (RX_DMA_BURST << RxCfgDMAShift); 710 #else 711 #error "Invalid configuration for 8139_RXBUF_IDX" 712 #endif 713 714 static const unsigned int rtl8139_tx_config = 715 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift); 716 717 static void __rtl8139_cleanup_dev (struct net_device *dev) 718 { 719 struct rtl8139_private *tp = netdev_priv(dev); 720 struct pci_dev *pdev; 721 722 assert (dev != NULL); 723 assert (tp->pci_dev != NULL); 724 pdev = tp->pci_dev; 725 726 if (tp->mmio_addr) 727 pci_iounmap (pdev, tp->mmio_addr); 728 729 /* it's ok to call this even if we have no regions to free */ 730 pci_release_regions (pdev); 731 732 free_netdev(dev); 733 } 734 735 736 static void rtl8139_chip_reset (void __iomem *ioaddr) 737 { 738 int i; 739 740 /* Soft reset the chip. */ 741 RTL_W8 (ChipCmd, CmdReset); 742 743 /* Check that the chip has finished the reset. */ 744 for (i = 1000; i > 0; i--) { 745 barrier(); 746 if ((RTL_R8 (ChipCmd) & CmdReset) == 0) 747 break; 748 udelay (10); 749 } 750 } 751 752 753 static struct net_device *rtl8139_init_board(struct pci_dev *pdev) 754 { 755 struct device *d = &pdev->dev; 756 void __iomem *ioaddr; 757 struct net_device *dev; 758 struct rtl8139_private *tp; 759 u8 tmp8; 760 int rc, disable_dev_on_err = 0; 761 unsigned int i, bar; 762 unsigned long io_len; 763 u32 version; 764 static const struct { 765 unsigned long mask; 766 char *type; 767 } res[] = { 768 { IORESOURCE_IO, "PIO" }, 769 { IORESOURCE_MEM, "MMIO" } 770 }; 771 772 assert (pdev != NULL); 773 774 /* dev and priv zeroed in alloc_etherdev */ 775 dev = alloc_etherdev (sizeof (*tp)); 776 if (dev == NULL) 777 return ERR_PTR(-ENOMEM); 778 779 SET_NETDEV_DEV(dev, &pdev->dev); 780 781 tp = netdev_priv(dev); 782 tp->pci_dev = pdev; 783 784 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 785 rc = pci_enable_device (pdev); 786 if (rc) 787 goto err_out; 788 789 disable_dev_on_err = 1; 790 rc = pci_request_regions (pdev, DRV_NAME); 791 if (rc) 792 goto err_out; 793 794 pci_set_master (pdev); 795 796 u64_stats_init(&tp->rx_stats.syncp); 797 u64_stats_init(&tp->tx_stats.syncp); 798 799 retry: 800 /* PIO bar register comes first. */ 801 bar = !use_io; 802 803 io_len = pci_resource_len(pdev, bar); 804 805 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len); 806 807 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) { 808 dev_err(d, "region #%d not a %s resource, aborting\n", bar, 809 res[bar].type); 810 rc = -ENODEV; 811 goto err_out; 812 } 813 if (io_len < RTL_MIN_IO_SIZE) { 814 dev_err(d, "Invalid PCI %s region size(s), aborting\n", 815 res[bar].type); 816 rc = -ENODEV; 817 goto err_out; 818 } 819 820 ioaddr = pci_iomap(pdev, bar, 0); 821 if (!ioaddr) { 822 dev_err(d, "cannot map %s\n", res[bar].type); 823 if (!use_io) { 824 use_io = true; 825 goto retry; 826 } 827 rc = -ENODEV; 828 goto err_out; 829 } 830 tp->regs_len = io_len; 831 tp->mmio_addr = ioaddr; 832 833 /* Bring old chips out of low-power mode. */ 834 RTL_W8 (HltClk, 'R'); 835 836 /* check for missing/broken hardware */ 837 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) { 838 dev_err(&pdev->dev, "Chip not responding, ignoring board\n"); 839 rc = -EIO; 840 goto err_out; 841 } 842 843 /* identify chip attached to board */ 844 version = RTL_R32 (TxConfig) & HW_REVID_MASK; 845 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++) 846 if (version == rtl_chip_info[i].version) { 847 tp->chipset = i; 848 goto match; 849 } 850 851 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ 852 i = 0; 853 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); 854 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); 855 tp->chipset = 0; 856 857 match: 858 pr_debug("chipset id (%d) == index %d, '%s'\n", 859 version, i, rtl_chip_info[i].name); 860 861 if (tp->chipset >= CH_8139B) { 862 u8 new_tmp8 = tmp8 = RTL_R8 (Config1); 863 pr_debug("PCI PM wakeup\n"); 864 if ((rtl_chip_info[tp->chipset].flags & HasLWake) && 865 (tmp8 & LWAKE)) 866 new_tmp8 &= ~LWAKE; 867 new_tmp8 |= Cfg1_PM_Enable; 868 if (new_tmp8 != tmp8) { 869 RTL_W8 (Cfg9346, Cfg9346_Unlock); 870 RTL_W8 (Config1, tmp8); 871 RTL_W8 (Cfg9346, Cfg9346_Lock); 872 } 873 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 874 tmp8 = RTL_R8 (Config4); 875 if (tmp8 & LWPTN) { 876 RTL_W8 (Cfg9346, Cfg9346_Unlock); 877 RTL_W8 (Config4, tmp8 & ~LWPTN); 878 RTL_W8 (Cfg9346, Cfg9346_Lock); 879 } 880 } 881 } else { 882 pr_debug("Old chip wakeup\n"); 883 tmp8 = RTL_R8 (Config1); 884 tmp8 &= ~(SLEEP | PWRDN); 885 RTL_W8 (Config1, tmp8); 886 } 887 888 rtl8139_chip_reset (ioaddr); 889 890 return dev; 891 892 err_out: 893 __rtl8139_cleanup_dev (dev); 894 if (disable_dev_on_err) 895 pci_disable_device (pdev); 896 return ERR_PTR(rc); 897 } 898 899 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features) 900 { 901 struct rtl8139_private *tp = netdev_priv(dev); 902 unsigned long flags; 903 netdev_features_t changed = features ^ dev->features; 904 void __iomem *ioaddr = tp->mmio_addr; 905 906 if (!(changed & (NETIF_F_RXALL))) 907 return 0; 908 909 spin_lock_irqsave(&tp->lock, flags); 910 911 if (changed & NETIF_F_RXALL) { 912 int rx_mode = tp->rx_config; 913 if (features & NETIF_F_RXALL) 914 rx_mode |= (AcceptErr | AcceptRunt); 915 else 916 rx_mode &= ~(AcceptErr | AcceptRunt); 917 tp->rx_config = rtl8139_rx_config | rx_mode; 918 RTL_W32_F(RxConfig, tp->rx_config); 919 } 920 921 spin_unlock_irqrestore(&tp->lock, flags); 922 923 return 0; 924 } 925 926 static const struct net_device_ops rtl8139_netdev_ops = { 927 .ndo_open = rtl8139_open, 928 .ndo_stop = rtl8139_close, 929 .ndo_get_stats64 = rtl8139_get_stats64, 930 .ndo_validate_addr = eth_validate_addr, 931 .ndo_set_mac_address = rtl8139_set_mac_address, 932 .ndo_start_xmit = rtl8139_start_xmit, 933 .ndo_set_rx_mode = rtl8139_set_rx_mode, 934 .ndo_do_ioctl = netdev_ioctl, 935 .ndo_tx_timeout = rtl8139_tx_timeout, 936 #ifdef CONFIG_NET_POLL_CONTROLLER 937 .ndo_poll_controller = rtl8139_poll_controller, 938 #endif 939 .ndo_set_features = rtl8139_set_features, 940 }; 941 942 static int rtl8139_init_one(struct pci_dev *pdev, 943 const struct pci_device_id *ent) 944 { 945 struct net_device *dev = NULL; 946 struct rtl8139_private *tp; 947 int i, addr_len, option; 948 void __iomem *ioaddr; 949 static int board_idx = -1; 950 951 assert (pdev != NULL); 952 assert (ent != NULL); 953 954 board_idx++; 955 956 /* when we're built into the kernel, the driver version message 957 * is only printed if at least one 8139 board has been found 958 */ 959 #ifndef MODULE 960 { 961 static int printed_version; 962 if (!printed_version++) 963 pr_info(RTL8139_DRIVER_NAME "\n"); 964 } 965 #endif 966 967 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 968 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) { 969 dev_info(&pdev->dev, 970 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n", 971 pdev->vendor, pdev->device, pdev->revision); 972 return -ENODEV; 973 } 974 975 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 976 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && 977 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS && 978 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) { 979 pr_info("OQO Model 2 detected. Forcing PIO\n"); 980 use_io = 1; 981 } 982 983 dev = rtl8139_init_board (pdev); 984 if (IS_ERR(dev)) 985 return PTR_ERR(dev); 986 987 assert (dev != NULL); 988 tp = netdev_priv(dev); 989 tp->dev = dev; 990 991 ioaddr = tp->mmio_addr; 992 assert (ioaddr != NULL); 993 994 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6; 995 for (i = 0; i < 3; i++) 996 ((__le16 *) (dev->dev_addr))[i] = 997 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len)); 998 999 /* The Rtl8139-specific entries in the device structure. */ 1000 dev->netdev_ops = &rtl8139_netdev_ops; 1001 dev->ethtool_ops = &rtl8139_ethtool_ops; 1002 dev->watchdog_timeo = TX_TIMEOUT; 1003 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64); 1004 1005 /* note: the hardware is not capable of sg/csum/highdma, however 1006 * through the use of skb_copy_and_csum_dev we enable these 1007 * features 1008 */ 1009 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA; 1010 dev->vlan_features = dev->features; 1011 1012 dev->hw_features |= NETIF_F_RXALL; 1013 dev->hw_features |= NETIF_F_RXFCS; 1014 1015 /* MTU range: 68 - 1770 */ 1016 dev->min_mtu = ETH_MIN_MTU; 1017 dev->max_mtu = MAX_ETH_DATA_SIZE; 1018 1019 /* tp zeroed and aligned in alloc_etherdev */ 1020 tp = netdev_priv(dev); 1021 1022 /* note: tp->chipset set in rtl8139_init_board */ 1023 tp->drv_flags = board_info[ent->driver_data].hw_flags; 1024 tp->mmio_addr = ioaddr; 1025 tp->msg_enable = 1026 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1)); 1027 spin_lock_init (&tp->lock); 1028 spin_lock_init (&tp->rx_lock); 1029 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1030 tp->mii.dev = dev; 1031 tp->mii.mdio_read = mdio_read; 1032 tp->mii.mdio_write = mdio_write; 1033 tp->mii.phy_id_mask = 0x3f; 1034 tp->mii.reg_num_mask = 0x1f; 1035 1036 /* dev is fully set up and ready to use now */ 1037 pr_debug("about to register device named %s (%p)...\n", 1038 dev->name, dev); 1039 i = register_netdev (dev); 1040 if (i) goto err_out; 1041 1042 pci_set_drvdata (pdev, dev); 1043 1044 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n", 1045 board_info[ent->driver_data].name, 1046 ioaddr, dev->dev_addr, pdev->irq); 1047 1048 netdev_dbg(dev, "Identified 8139 chip type '%s'\n", 1049 rtl_chip_info[tp->chipset].name); 1050 1051 /* Find the connected MII xcvrs. 1052 Doing this in open() would allow detecting external xcvrs later, but 1053 takes too much time. */ 1054 #ifdef CONFIG_8139TOO_8129 1055 if (tp->drv_flags & HAS_MII_XCVR) { 1056 int phy, phy_idx = 0; 1057 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) { 1058 int mii_status = mdio_read(dev, phy, 1); 1059 if (mii_status != 0xffff && mii_status != 0x0000) { 1060 u16 advertising = mdio_read(dev, phy, 4); 1061 tp->phys[phy_idx++] = phy; 1062 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n", 1063 phy, mii_status, advertising); 1064 } 1065 } 1066 if (phy_idx == 0) { 1067 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n"); 1068 tp->phys[0] = 32; 1069 } 1070 } else 1071 #endif 1072 tp->phys[0] = 32; 1073 tp->mii.phy_id = tp->phys[0]; 1074 1075 /* The lower four bits are the media type. */ 1076 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 1077 if (option > 0) { 1078 tp->mii.full_duplex = (option & 0x210) ? 1 : 0; 1079 tp->default_port = option & 0xFF; 1080 if (tp->default_port) 1081 tp->mii.force_media = 1; 1082 } 1083 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0) 1084 tp->mii.full_duplex = full_duplex[board_idx]; 1085 if (tp->mii.full_duplex) { 1086 netdev_info(dev, "Media type forced to Full Duplex\n"); 1087 /* Changing the MII-advertised media because might prevent 1088 re-connection. */ 1089 tp->mii.force_media = 1; 1090 } 1091 if (tp->default_port) { 1092 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n", 1093 (option & 0x20 ? 100 : 10), 1094 (option & 0x10 ? "full" : "half")); 1095 mdio_write(dev, tp->phys[0], 0, 1096 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */ 1097 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */ 1098 } 1099 1100 /* Put the chip into low-power mode. */ 1101 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1102 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 1103 1104 return 0; 1105 1106 err_out: 1107 netif_napi_del(&tp->napi); 1108 __rtl8139_cleanup_dev (dev); 1109 pci_disable_device (pdev); 1110 return i; 1111 } 1112 1113 1114 static void rtl8139_remove_one(struct pci_dev *pdev) 1115 { 1116 struct net_device *dev = pci_get_drvdata (pdev); 1117 struct rtl8139_private *tp = netdev_priv(dev); 1118 1119 assert (dev != NULL); 1120 1121 cancel_delayed_work_sync(&tp->thread); 1122 netif_napi_del(&tp->napi); 1123 1124 unregister_netdev (dev); 1125 1126 __rtl8139_cleanup_dev (dev); 1127 pci_disable_device (pdev); 1128 } 1129 1130 1131 /* Serial EEPROM section. */ 1132 1133 /* EEPROM_Ctrl bits. */ 1134 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 1135 #define EE_CS 0x08 /* EEPROM chip select. */ 1136 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 1137 #define EE_WRITE_0 0x00 1138 #define EE_WRITE_1 0x02 1139 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 1140 #define EE_ENB (0x80 | EE_CS) 1141 1142 /* Delay between EEPROM clock transitions. 1143 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 1144 */ 1145 1146 #define eeprom_delay() (void)RTL_R8(Cfg9346) 1147 1148 /* The EEPROM commands include the alway-set leading bit. */ 1149 #define EE_WRITE_CMD (5) 1150 #define EE_READ_CMD (6) 1151 #define EE_ERASE_CMD (7) 1152 1153 static int read_eeprom(void __iomem *ioaddr, int location, int addr_len) 1154 { 1155 int i; 1156 unsigned retval = 0; 1157 int read_cmd = location | (EE_READ_CMD << addr_len); 1158 1159 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS); 1160 RTL_W8 (Cfg9346, EE_ENB); 1161 eeprom_delay (); 1162 1163 /* Shift the read command bits out. */ 1164 for (i = 4 + addr_len; i >= 0; i--) { 1165 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 1166 RTL_W8 (Cfg9346, EE_ENB | dataval); 1167 eeprom_delay (); 1168 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK); 1169 eeprom_delay (); 1170 } 1171 RTL_W8 (Cfg9346, EE_ENB); 1172 eeprom_delay (); 1173 1174 for (i = 16; i > 0; i--) { 1175 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK); 1176 eeprom_delay (); 1177 retval = 1178 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 : 1179 0); 1180 RTL_W8 (Cfg9346, EE_ENB); 1181 eeprom_delay (); 1182 } 1183 1184 /* Terminate the EEPROM access. */ 1185 RTL_W8(Cfg9346, 0); 1186 eeprom_delay (); 1187 1188 return retval; 1189 } 1190 1191 /* MII serial management: mostly bogus for now. */ 1192 /* Read and write the MII management registers using software-generated 1193 serial MDIO protocol. 1194 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 1195 met by back-to-back PCI I/O cycles, but we insert a delay to avoid 1196 "overclocking" issues. */ 1197 #define MDIO_DIR 0x80 1198 #define MDIO_DATA_OUT 0x04 1199 #define MDIO_DATA_IN 0x02 1200 #define MDIO_CLK 0x01 1201 #define MDIO_WRITE0 (MDIO_DIR) 1202 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT) 1203 1204 #define mdio_delay() RTL_R8(Config4) 1205 1206 1207 static const char mii_2_8139_map[8] = { 1208 BasicModeCtrl, 1209 BasicModeStatus, 1210 0, 1211 0, 1212 NWayAdvert, 1213 NWayLPAR, 1214 NWayExpansion, 1215 0 1216 }; 1217 1218 1219 #ifdef CONFIG_8139TOO_8129 1220 /* Syncronize the MII management interface by shifting 32 one bits out. */ 1221 static void mdio_sync (void __iomem *ioaddr) 1222 { 1223 int i; 1224 1225 for (i = 32; i >= 0; i--) { 1226 RTL_W8 (Config4, MDIO_WRITE1); 1227 mdio_delay (); 1228 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK); 1229 mdio_delay (); 1230 } 1231 } 1232 #endif 1233 1234 static int mdio_read (struct net_device *dev, int phy_id, int location) 1235 { 1236 struct rtl8139_private *tp = netdev_priv(dev); 1237 int retval = 0; 1238 #ifdef CONFIG_8139TOO_8129 1239 void __iomem *ioaddr = tp->mmio_addr; 1240 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; 1241 int i; 1242 #endif 1243 1244 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1245 void __iomem *ioaddr = tp->mmio_addr; 1246 return location < 8 && mii_2_8139_map[location] ? 1247 RTL_R16 (mii_2_8139_map[location]) : 0; 1248 } 1249 1250 #ifdef CONFIG_8139TOO_8129 1251 mdio_sync (ioaddr); 1252 /* Shift the read command bits out. */ 1253 for (i = 15; i >= 0; i--) { 1254 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0; 1255 1256 RTL_W8 (Config4, MDIO_DIR | dataval); 1257 mdio_delay (); 1258 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK); 1259 mdio_delay (); 1260 } 1261 1262 /* Read the two transition, 16 data, and wire-idle bits. */ 1263 for (i = 19; i > 0; i--) { 1264 RTL_W8 (Config4, 0); 1265 mdio_delay (); 1266 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0); 1267 RTL_W8 (Config4, MDIO_CLK); 1268 mdio_delay (); 1269 } 1270 #endif 1271 1272 return (retval >> 1) & 0xffff; 1273 } 1274 1275 1276 static void mdio_write (struct net_device *dev, int phy_id, int location, 1277 int value) 1278 { 1279 struct rtl8139_private *tp = netdev_priv(dev); 1280 #ifdef CONFIG_8139TOO_8129 1281 void __iomem *ioaddr = tp->mmio_addr; 1282 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; 1283 int i; 1284 #endif 1285 1286 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1287 void __iomem *ioaddr = tp->mmio_addr; 1288 if (location == 0) { 1289 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1290 RTL_W16 (BasicModeCtrl, value); 1291 RTL_W8 (Cfg9346, Cfg9346_Lock); 1292 } else if (location < 8 && mii_2_8139_map[location]) 1293 RTL_W16 (mii_2_8139_map[location], value); 1294 return; 1295 } 1296 1297 #ifdef CONFIG_8139TOO_8129 1298 mdio_sync (ioaddr); 1299 1300 /* Shift the command bits out. */ 1301 for (i = 31; i >= 0; i--) { 1302 int dataval = 1303 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 1304 RTL_W8 (Config4, dataval); 1305 mdio_delay (); 1306 RTL_W8 (Config4, dataval | MDIO_CLK); 1307 mdio_delay (); 1308 } 1309 /* Clear out extra bits. */ 1310 for (i = 2; i > 0; i--) { 1311 RTL_W8 (Config4, 0); 1312 mdio_delay (); 1313 RTL_W8 (Config4, MDIO_CLK); 1314 mdio_delay (); 1315 } 1316 #endif 1317 } 1318 1319 1320 static int rtl8139_open (struct net_device *dev) 1321 { 1322 struct rtl8139_private *tp = netdev_priv(dev); 1323 void __iomem *ioaddr = tp->mmio_addr; 1324 const int irq = tp->pci_dev->irq; 1325 int retval; 1326 1327 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev); 1328 if (retval) 1329 return retval; 1330 1331 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1332 &tp->tx_bufs_dma, GFP_KERNEL); 1333 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1334 &tp->rx_ring_dma, GFP_KERNEL); 1335 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) { 1336 free_irq(irq, dev); 1337 1338 if (tp->tx_bufs) 1339 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1340 tp->tx_bufs, tp->tx_bufs_dma); 1341 if (tp->rx_ring) 1342 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1343 tp->rx_ring, tp->rx_ring_dma); 1344 1345 return -ENOMEM; 1346 1347 } 1348 1349 napi_enable(&tp->napi); 1350 1351 tp->mii.full_duplex = tp->mii.force_media; 1352 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000; 1353 1354 rtl8139_init_ring (dev); 1355 rtl8139_hw_start (dev); 1356 netif_start_queue (dev); 1357 1358 netif_dbg(tp, ifup, dev, 1359 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n", 1360 __func__, 1361 (unsigned long long)pci_resource_start (tp->pci_dev, 1), 1362 irq, RTL_R8 (MediaStatus), 1363 tp->mii.full_duplex ? "full" : "half"); 1364 1365 rtl8139_start_thread(tp); 1366 1367 return 0; 1368 } 1369 1370 1371 static void rtl_check_media (struct net_device *dev, unsigned int init_media) 1372 { 1373 struct rtl8139_private *tp = netdev_priv(dev); 1374 1375 if (tp->phys[0] >= 0) { 1376 mii_check_media(&tp->mii, netif_msg_link(tp), init_media); 1377 } 1378 } 1379 1380 /* Start the hardware at open or resume. */ 1381 static void rtl8139_hw_start (struct net_device *dev) 1382 { 1383 struct rtl8139_private *tp = netdev_priv(dev); 1384 void __iomem *ioaddr = tp->mmio_addr; 1385 u32 i; 1386 u8 tmp; 1387 1388 /* Bring old chips out of low-power mode. */ 1389 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1390 RTL_W8 (HltClk, 'R'); 1391 1392 rtl8139_chip_reset (ioaddr); 1393 1394 /* unlock Config[01234] and BMCR register writes */ 1395 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1396 /* Restore our idea of the MAC address. */ 1397 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); 1398 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4))); 1399 1400 tp->cur_rx = 0; 1401 1402 /* init Rx ring buffer DMA address */ 1403 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1404 1405 /* Must enable Tx/Rx before setting transfer thresholds! */ 1406 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1407 1408 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1409 RTL_W32 (RxConfig, tp->rx_config); 1410 RTL_W32 (TxConfig, rtl8139_tx_config); 1411 1412 rtl_check_media (dev, 1); 1413 1414 if (tp->chipset >= CH_8139B) { 1415 /* Disable magic packet scanning, which is enabled 1416 * when PM is enabled in Config1. It can be reenabled 1417 * via ETHTOOL_SWOL if desired. */ 1418 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic); 1419 } 1420 1421 netdev_dbg(dev, "init buffer addresses\n"); 1422 1423 /* Lock Config[01234] and BMCR register writes */ 1424 RTL_W8 (Cfg9346, Cfg9346_Lock); 1425 1426 /* init Tx buffer DMA addresses */ 1427 for (i = 0; i < NUM_TX_DESC; i++) 1428 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs)); 1429 1430 RTL_W32 (RxMissed, 0); 1431 1432 rtl8139_set_rx_mode (dev); 1433 1434 /* no early-rx interrupts */ 1435 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear); 1436 1437 /* make sure RxTx has started */ 1438 tmp = RTL_R8 (ChipCmd); 1439 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb))) 1440 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1441 1442 /* Enable all known interrupts by setting the interrupt mask. */ 1443 RTL_W16 (IntrMask, rtl8139_intr_mask); 1444 } 1445 1446 1447 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1448 static void rtl8139_init_ring (struct net_device *dev) 1449 { 1450 struct rtl8139_private *tp = netdev_priv(dev); 1451 int i; 1452 1453 tp->cur_rx = 0; 1454 tp->cur_tx = 0; 1455 tp->dirty_tx = 0; 1456 1457 for (i = 0; i < NUM_TX_DESC; i++) 1458 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE]; 1459 } 1460 1461 1462 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */ 1463 static int next_tick = 3 * HZ; 1464 1465 #ifndef CONFIG_8139TOO_TUNE_TWISTER 1466 static inline void rtl8139_tune_twister (struct net_device *dev, 1467 struct rtl8139_private *tp) {} 1468 #else 1469 enum TwisterParamVals { 1470 PARA78_default = 0x78fa8388, 1471 PARA7c_default = 0xcb38de43, /* param[0][3] */ 1472 PARA7c_xxx = 0xcb38de43, 1473 }; 1474 1475 static const unsigned long param[4][4] = { 1476 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1477 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1478 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1479 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1480 }; 1481 1482 static void rtl8139_tune_twister (struct net_device *dev, 1483 struct rtl8139_private *tp) 1484 { 1485 int linkcase; 1486 void __iomem *ioaddr = tp->mmio_addr; 1487 1488 /* This is a complicated state machine to configure the "twister" for 1489 impedance/echos based on the cable length. 1490 All of this is magic and undocumented. 1491 */ 1492 switch (tp->twistie) { 1493 case 1: 1494 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) { 1495 /* We have link beat, let us tune the twister. */ 1496 RTL_W16 (CSCR, CSCR_LinkDownOffCmd); 1497 tp->twistie = 2; /* Change to state 2. */ 1498 next_tick = HZ / 10; 1499 } else { 1500 /* Just put in some reasonable defaults for when beat returns. */ 1501 RTL_W16 (CSCR, CSCR_LinkDownCmd); 1502 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */ 1503 RTL_W32 (PARA78, PARA78_default); 1504 RTL_W32 (PARA7c, PARA7c_default); 1505 tp->twistie = 0; /* Bail from future actions. */ 1506 } 1507 break; 1508 case 2: 1509 /* Read how long it took to hear the echo. */ 1510 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits; 1511 if (linkcase == 0x7000) 1512 tp->twist_row = 3; 1513 else if (linkcase == 0x3000) 1514 tp->twist_row = 2; 1515 else if (linkcase == 0x1000) 1516 tp->twist_row = 1; 1517 else 1518 tp->twist_row = 0; 1519 tp->twist_col = 0; 1520 tp->twistie = 3; /* Change to state 2. */ 1521 next_tick = HZ / 10; 1522 break; 1523 case 3: 1524 /* Put out four tuning parameters, one per 100msec. */ 1525 if (tp->twist_col == 0) 1526 RTL_W16 (FIFOTMS, 0); 1527 RTL_W32 (PARA7c, param[(int) tp->twist_row] 1528 [(int) tp->twist_col]); 1529 next_tick = HZ / 10; 1530 if (++tp->twist_col >= 4) { 1531 /* For short cables we are done. 1532 For long cables (row == 3) check for mistune. */ 1533 tp->twistie = 1534 (tp->twist_row == 3) ? 4 : 0; 1535 } 1536 break; 1537 case 4: 1538 /* Special case for long cables: check for mistune. */ 1539 if ((RTL_R16 (CSCR) & 1540 CSCR_LinkStatusBits) == 0x7000) { 1541 tp->twistie = 0; 1542 break; 1543 } else { 1544 RTL_W32 (PARA7c, 0xfb38de03); 1545 tp->twistie = 5; 1546 next_tick = HZ / 10; 1547 } 1548 break; 1549 case 5: 1550 /* Retune for shorter cable (column 2). */ 1551 RTL_W32 (FIFOTMS, 0x20); 1552 RTL_W32 (PARA78, PARA78_default); 1553 RTL_W32 (PARA7c, PARA7c_default); 1554 RTL_W32 (FIFOTMS, 0x00); 1555 tp->twist_row = 2; 1556 tp->twist_col = 0; 1557 tp->twistie = 3; 1558 next_tick = HZ / 10; 1559 break; 1560 1561 default: 1562 /* do nothing */ 1563 break; 1564 } 1565 } 1566 #endif /* CONFIG_8139TOO_TUNE_TWISTER */ 1567 1568 static inline void rtl8139_thread_iter (struct net_device *dev, 1569 struct rtl8139_private *tp, 1570 void __iomem *ioaddr) 1571 { 1572 int mii_lpa; 1573 1574 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA); 1575 1576 if (!tp->mii.force_media && mii_lpa != 0xffff) { 1577 int duplex = ((mii_lpa & LPA_100FULL) || 1578 (mii_lpa & 0x01C0) == 0x0040); 1579 if (tp->mii.full_duplex != duplex) { 1580 tp->mii.full_duplex = duplex; 1581 1582 if (mii_lpa) { 1583 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n", 1584 tp->mii.full_duplex ? "full" : "half", 1585 tp->phys[0], mii_lpa); 1586 } else { 1587 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n"); 1588 } 1589 #if 0 1590 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1591 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20); 1592 RTL_W8 (Cfg9346, Cfg9346_Lock); 1593 #endif 1594 } 1595 } 1596 1597 next_tick = HZ * 60; 1598 1599 rtl8139_tune_twister (dev, tp); 1600 1601 netdev_dbg(dev, "Media selection tick, Link partner %04x\n", 1602 RTL_R16(NWayLPAR)); 1603 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n", 1604 RTL_R16(IntrMask), RTL_R16(IntrStatus)); 1605 netdev_dbg(dev, "Chip config %02x %02x\n", 1606 RTL_R8(Config0), RTL_R8(Config1)); 1607 } 1608 1609 static void rtl8139_thread (struct work_struct *work) 1610 { 1611 struct rtl8139_private *tp = 1612 container_of(work, struct rtl8139_private, thread.work); 1613 struct net_device *dev = tp->mii.dev; 1614 unsigned long thr_delay = next_tick; 1615 1616 rtnl_lock(); 1617 1618 if (!netif_running(dev)) 1619 goto out_unlock; 1620 1621 if (tp->watchdog_fired) { 1622 tp->watchdog_fired = 0; 1623 rtl8139_tx_timeout_task(work); 1624 } else 1625 rtl8139_thread_iter(dev, tp, tp->mmio_addr); 1626 1627 if (tp->have_thread) 1628 schedule_delayed_work(&tp->thread, thr_delay); 1629 out_unlock: 1630 rtnl_unlock (); 1631 } 1632 1633 static void rtl8139_start_thread(struct rtl8139_private *tp) 1634 { 1635 tp->twistie = 0; 1636 if (tp->chipset == CH_8139_K) 1637 tp->twistie = 1; 1638 else if (tp->drv_flags & HAS_LNK_CHNG) 1639 return; 1640 1641 tp->have_thread = 1; 1642 tp->watchdog_fired = 0; 1643 1644 schedule_delayed_work(&tp->thread, next_tick); 1645 } 1646 1647 static inline void rtl8139_tx_clear (struct rtl8139_private *tp) 1648 { 1649 tp->cur_tx = 0; 1650 tp->dirty_tx = 0; 1651 1652 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */ 1653 } 1654 1655 static void rtl8139_tx_timeout_task (struct work_struct *work) 1656 { 1657 struct rtl8139_private *tp = 1658 container_of(work, struct rtl8139_private, thread.work); 1659 struct net_device *dev = tp->mii.dev; 1660 void __iomem *ioaddr = tp->mmio_addr; 1661 int i; 1662 u8 tmp8; 1663 1664 napi_disable(&tp->napi); 1665 netif_stop_queue(dev); 1666 synchronize_sched(); 1667 1668 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n", 1669 RTL_R8(ChipCmd), RTL_R16(IntrStatus), 1670 RTL_R16(IntrMask), RTL_R8(MediaStatus)); 1671 /* Emit info to figure out what went wrong. */ 1672 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n", 1673 tp->cur_tx, tp->dirty_tx); 1674 for (i = 0; i < NUM_TX_DESC; i++) 1675 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n", 1676 i, RTL_R32(TxStatus0 + (i * 4)), 1677 i == tp->dirty_tx % NUM_TX_DESC ? 1678 " (queue head)" : ""); 1679 1680 tp->xstats.tx_timeouts++; 1681 1682 /* disable Tx ASAP, if not already */ 1683 tmp8 = RTL_R8 (ChipCmd); 1684 if (tmp8 & CmdTxEnb) 1685 RTL_W8 (ChipCmd, CmdRxEnb); 1686 1687 spin_lock_bh(&tp->rx_lock); 1688 /* Disable interrupts by clearing the interrupt mask. */ 1689 RTL_W16 (IntrMask, 0x0000); 1690 1691 /* Stop a shared interrupt from scavenging while we are. */ 1692 spin_lock_irq(&tp->lock); 1693 rtl8139_tx_clear (tp); 1694 spin_unlock_irq(&tp->lock); 1695 1696 /* ...and finally, reset everything */ 1697 napi_enable(&tp->napi); 1698 rtl8139_hw_start(dev); 1699 netif_wake_queue(dev); 1700 1701 spin_unlock_bh(&tp->rx_lock); 1702 } 1703 1704 static void rtl8139_tx_timeout (struct net_device *dev) 1705 { 1706 struct rtl8139_private *tp = netdev_priv(dev); 1707 1708 tp->watchdog_fired = 1; 1709 if (!tp->have_thread) { 1710 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1711 schedule_delayed_work(&tp->thread, next_tick); 1712 } 1713 } 1714 1715 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 1716 struct net_device *dev) 1717 { 1718 struct rtl8139_private *tp = netdev_priv(dev); 1719 void __iomem *ioaddr = tp->mmio_addr; 1720 unsigned int entry; 1721 unsigned int len = skb->len; 1722 unsigned long flags; 1723 1724 /* Calculate the next Tx descriptor entry. */ 1725 entry = tp->cur_tx % NUM_TX_DESC; 1726 1727 /* Note: the chip doesn't have auto-pad! */ 1728 if (likely(len < TX_BUF_SIZE)) { 1729 if (len < ETH_ZLEN) 1730 memset(tp->tx_buf[entry], 0, ETH_ZLEN); 1731 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]); 1732 dev_kfree_skb_any(skb); 1733 } else { 1734 dev_kfree_skb_any(skb); 1735 dev->stats.tx_dropped++; 1736 return NETDEV_TX_OK; 1737 } 1738 1739 spin_lock_irqsave(&tp->lock, flags); 1740 /* 1741 * Writing to TxStatus triggers a DMA transfer of the data 1742 * copied to tp->tx_buf[entry] above. Use a memory barrier 1743 * to make sure that the device sees the updated data. 1744 */ 1745 wmb(); 1746 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)), 1747 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN)); 1748 1749 tp->cur_tx++; 1750 1751 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) 1752 netif_stop_queue (dev); 1753 spin_unlock_irqrestore(&tp->lock, flags); 1754 1755 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n", 1756 len, entry); 1757 1758 return NETDEV_TX_OK; 1759 } 1760 1761 1762 static void rtl8139_tx_interrupt (struct net_device *dev, 1763 struct rtl8139_private *tp, 1764 void __iomem *ioaddr) 1765 { 1766 unsigned long dirty_tx, tx_left; 1767 1768 assert (dev != NULL); 1769 assert (ioaddr != NULL); 1770 1771 dirty_tx = tp->dirty_tx; 1772 tx_left = tp->cur_tx - dirty_tx; 1773 while (tx_left > 0) { 1774 int entry = dirty_tx % NUM_TX_DESC; 1775 int txstatus; 1776 1777 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); 1778 1779 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted))) 1780 break; /* It still hasn't been Txed */ 1781 1782 /* Note: TxCarrierLost is always asserted at 100mbps. */ 1783 if (txstatus & (TxOutOfWindow | TxAborted)) { 1784 /* There was an major error, log it. */ 1785 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n", 1786 txstatus); 1787 dev->stats.tx_errors++; 1788 if (txstatus & TxAborted) { 1789 dev->stats.tx_aborted_errors++; 1790 RTL_W32 (TxConfig, TxClearAbt); 1791 RTL_W16 (IntrStatus, TxErr); 1792 wmb(); 1793 } 1794 if (txstatus & TxCarrierLost) 1795 dev->stats.tx_carrier_errors++; 1796 if (txstatus & TxOutOfWindow) 1797 dev->stats.tx_window_errors++; 1798 } else { 1799 if (txstatus & TxUnderrun) { 1800 /* Add 64 to the Tx FIFO threshold. */ 1801 if (tp->tx_flag < 0x00300000) 1802 tp->tx_flag += 0x00020000; 1803 dev->stats.tx_fifo_errors++; 1804 } 1805 dev->stats.collisions += (txstatus >> 24) & 15; 1806 u64_stats_update_begin(&tp->tx_stats.syncp); 1807 tp->tx_stats.packets++; 1808 tp->tx_stats.bytes += txstatus & 0x7ff; 1809 u64_stats_update_end(&tp->tx_stats.syncp); 1810 } 1811 1812 dirty_tx++; 1813 tx_left--; 1814 } 1815 1816 #ifndef RTL8139_NDEBUG 1817 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) { 1818 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n", 1819 dirty_tx, tp->cur_tx); 1820 dirty_tx += NUM_TX_DESC; 1821 } 1822 #endif /* RTL8139_NDEBUG */ 1823 1824 /* only wake the queue if we did work, and the queue is stopped */ 1825 if (tp->dirty_tx != dirty_tx) { 1826 tp->dirty_tx = dirty_tx; 1827 mb(); 1828 netif_wake_queue (dev); 1829 } 1830 } 1831 1832 1833 /* TODO: clean this up! Rx reset need not be this intensive */ 1834 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev, 1835 struct rtl8139_private *tp, void __iomem *ioaddr) 1836 { 1837 u8 tmp8; 1838 #ifdef CONFIG_8139_OLD_RX_RESET 1839 int tmp_work; 1840 #endif 1841 1842 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n", 1843 rx_status); 1844 dev->stats.rx_errors++; 1845 if (!(rx_status & RxStatusOK)) { 1846 if (rx_status & RxTooLong) { 1847 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n", 1848 rx_status); 1849 /* A.C.: The chip hangs here. */ 1850 } 1851 if (rx_status & (RxBadSymbol | RxBadAlign)) 1852 dev->stats.rx_frame_errors++; 1853 if (rx_status & (RxRunt | RxTooLong)) 1854 dev->stats.rx_length_errors++; 1855 if (rx_status & RxCRCErr) 1856 dev->stats.rx_crc_errors++; 1857 } else { 1858 tp->xstats.rx_lost_in_ring++; 1859 } 1860 1861 #ifndef CONFIG_8139_OLD_RX_RESET 1862 tmp8 = RTL_R8 (ChipCmd); 1863 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb); 1864 RTL_W8 (ChipCmd, tmp8); 1865 RTL_W32 (RxConfig, tp->rx_config); 1866 tp->cur_rx = 0; 1867 #else 1868 /* Reset the receiver, based on RealTek recommendation. (Bug?) */ 1869 1870 /* disable receive */ 1871 RTL_W8_F (ChipCmd, CmdTxEnb); 1872 tmp_work = 200; 1873 while (--tmp_work > 0) { 1874 udelay(1); 1875 tmp8 = RTL_R8 (ChipCmd); 1876 if (!(tmp8 & CmdRxEnb)) 1877 break; 1878 } 1879 if (tmp_work <= 0) 1880 netdev_warn(dev, "rx stop wait too long\n"); 1881 /* restart receive */ 1882 tmp_work = 200; 1883 while (--tmp_work > 0) { 1884 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb); 1885 udelay(1); 1886 tmp8 = RTL_R8 (ChipCmd); 1887 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb)) 1888 break; 1889 } 1890 if (tmp_work <= 0) 1891 netdev_warn(dev, "tx/rx enable wait too long\n"); 1892 1893 /* and reinitialize all rx related registers */ 1894 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1895 /* Must enable Tx/Rx before setting transfer thresholds! */ 1896 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1897 1898 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1899 RTL_W32 (RxConfig, tp->rx_config); 1900 tp->cur_rx = 0; 1901 1902 netdev_dbg(dev, "init buffer addresses\n"); 1903 1904 /* Lock Config[01234] and BMCR register writes */ 1905 RTL_W8 (Cfg9346, Cfg9346_Lock); 1906 1907 /* init Rx ring buffer DMA address */ 1908 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1909 1910 /* A.C.: Reset the multicast list. */ 1911 __set_rx_mode (dev); 1912 #endif 1913 } 1914 1915 #if RX_BUF_IDX == 3 1916 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring, 1917 u32 offset, unsigned int size) 1918 { 1919 u32 left = RX_BUF_LEN - offset; 1920 1921 if (size > left) { 1922 skb_copy_to_linear_data(skb, ring + offset, left); 1923 skb_copy_to_linear_data_offset(skb, left, ring, size - left); 1924 } else 1925 skb_copy_to_linear_data(skb, ring + offset, size); 1926 } 1927 #endif 1928 1929 static void rtl8139_isr_ack(struct rtl8139_private *tp) 1930 { 1931 void __iomem *ioaddr = tp->mmio_addr; 1932 u16 status; 1933 1934 status = RTL_R16 (IntrStatus) & RxAckBits; 1935 1936 /* Clear out errors and receive interrupts */ 1937 if (likely(status != 0)) { 1938 if (unlikely(status & (RxFIFOOver | RxOverflow))) { 1939 tp->dev->stats.rx_errors++; 1940 if (status & RxFIFOOver) 1941 tp->dev->stats.rx_fifo_errors++; 1942 } 1943 RTL_W16_F (IntrStatus, RxAckBits); 1944 } 1945 } 1946 1947 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp, 1948 int budget) 1949 { 1950 void __iomem *ioaddr = tp->mmio_addr; 1951 int received = 0; 1952 unsigned char *rx_ring = tp->rx_ring; 1953 unsigned int cur_rx = tp->cur_rx; 1954 unsigned int rx_size = 0; 1955 1956 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 1957 __func__, (u16)cur_rx, 1958 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 1959 1960 while (netif_running(dev) && received < budget && 1961 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { 1962 u32 ring_offset = cur_rx % RX_BUF_LEN; 1963 u32 rx_status; 1964 unsigned int pkt_size; 1965 struct sk_buff *skb; 1966 1967 rmb(); 1968 1969 /* read size+status of next frame from DMA ring buffer */ 1970 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset)); 1971 rx_size = rx_status >> 16; 1972 if (likely(!(dev->features & NETIF_F_RXFCS))) 1973 pkt_size = rx_size - 4; 1974 else 1975 pkt_size = rx_size; 1976 1977 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n", 1978 __func__, rx_status, rx_size, cur_rx); 1979 #if RTL8139_DEBUG > 2 1980 print_hex_dump(KERN_DEBUG, "Frame contents: ", 1981 DUMP_PREFIX_OFFSET, 16, 1, 1982 &rx_ring[ring_offset], 70, true); 1983 #endif 1984 1985 /* Packet copy from FIFO still in progress. 1986 * Theoretically, this should never happen 1987 * since EarlyRx is disabled. 1988 */ 1989 if (unlikely(rx_size == 0xfff0)) { 1990 if (!tp->fifo_copy_timeout) 1991 tp->fifo_copy_timeout = jiffies + 2; 1992 else if (time_after(jiffies, tp->fifo_copy_timeout)) { 1993 netdev_dbg(dev, "hung FIFO. Reset\n"); 1994 rx_size = 0; 1995 goto no_early_rx; 1996 } 1997 netif_dbg(tp, intr, dev, "fifo copy in progress\n"); 1998 tp->xstats.early_rx++; 1999 break; 2000 } 2001 2002 no_early_rx: 2003 tp->fifo_copy_timeout = 0; 2004 2005 /* If Rx err or invalid rx_size/rx_status received 2006 * (which happens if we get lost in the ring), 2007 * Rx process gets reset, so we abort any further 2008 * Rx processing. 2009 */ 2010 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) || 2011 (rx_size < 8) || 2012 (!(rx_status & RxStatusOK)))) { 2013 if ((dev->features & NETIF_F_RXALL) && 2014 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) && 2015 (rx_size >= 8) && 2016 (!(rx_status & RxStatusOK))) { 2017 /* Length is at least mostly OK, but pkt has 2018 * error. I'm hoping we can handle some of these 2019 * errors without resetting the chip. --Ben 2020 */ 2021 dev->stats.rx_errors++; 2022 if (rx_status & RxCRCErr) { 2023 dev->stats.rx_crc_errors++; 2024 goto keep_pkt; 2025 } 2026 if (rx_status & RxRunt) { 2027 dev->stats.rx_length_errors++; 2028 goto keep_pkt; 2029 } 2030 } 2031 rtl8139_rx_err (rx_status, dev, tp, ioaddr); 2032 received = -1; 2033 goto out; 2034 } 2035 2036 keep_pkt: 2037 /* Malloc up new buffer, compatible with net-2e. */ 2038 /* Omit the four octet CRC from the length. */ 2039 2040 skb = napi_alloc_skb(&tp->napi, pkt_size); 2041 if (likely(skb)) { 2042 #if RX_BUF_IDX == 3 2043 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size); 2044 #else 2045 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size); 2046 #endif 2047 skb_put (skb, pkt_size); 2048 2049 skb->protocol = eth_type_trans (skb, dev); 2050 2051 u64_stats_update_begin(&tp->rx_stats.syncp); 2052 tp->rx_stats.packets++; 2053 tp->rx_stats.bytes += pkt_size; 2054 u64_stats_update_end(&tp->rx_stats.syncp); 2055 2056 netif_receive_skb (skb); 2057 } else { 2058 dev->stats.rx_dropped++; 2059 } 2060 received++; 2061 2062 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 2063 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16)); 2064 2065 rtl8139_isr_ack(tp); 2066 } 2067 2068 if (unlikely(!received || rx_size == 0xfff0)) 2069 rtl8139_isr_ack(tp); 2070 2071 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 2072 __func__, cur_rx, 2073 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 2074 2075 tp->cur_rx = cur_rx; 2076 2077 /* 2078 * The receive buffer should be mostly empty. 2079 * Tell NAPI to reenable the Rx irq. 2080 */ 2081 if (tp->fifo_copy_timeout) 2082 received = budget; 2083 2084 out: 2085 return received; 2086 } 2087 2088 2089 static void rtl8139_weird_interrupt (struct net_device *dev, 2090 struct rtl8139_private *tp, 2091 void __iomem *ioaddr, 2092 int status, int link_changed) 2093 { 2094 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status); 2095 2096 assert (dev != NULL); 2097 assert (tp != NULL); 2098 assert (ioaddr != NULL); 2099 2100 /* Update the error count. */ 2101 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2102 RTL_W32 (RxMissed, 0); 2103 2104 if ((status & RxUnderrun) && link_changed && 2105 (tp->drv_flags & HAS_LNK_CHNG)) { 2106 rtl_check_media(dev, 0); 2107 status &= ~RxUnderrun; 2108 } 2109 2110 if (status & (RxUnderrun | RxErr)) 2111 dev->stats.rx_errors++; 2112 2113 if (status & PCSTimeout) 2114 dev->stats.rx_length_errors++; 2115 if (status & RxUnderrun) 2116 dev->stats.rx_fifo_errors++; 2117 if (status & PCIErr) { 2118 u16 pci_cmd_status; 2119 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status); 2120 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status); 2121 2122 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status); 2123 } 2124 } 2125 2126 static int rtl8139_poll(struct napi_struct *napi, int budget) 2127 { 2128 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi); 2129 struct net_device *dev = tp->dev; 2130 void __iomem *ioaddr = tp->mmio_addr; 2131 int work_done; 2132 2133 spin_lock(&tp->rx_lock); 2134 work_done = 0; 2135 if (likely(RTL_R16(IntrStatus) & RxAckBits)) 2136 work_done += rtl8139_rx(dev, tp, budget); 2137 2138 if (work_done < budget && napi_complete_done(napi, work_done)) { 2139 unsigned long flags; 2140 2141 spin_lock_irqsave(&tp->lock, flags); 2142 RTL_W16_F(IntrMask, rtl8139_intr_mask); 2143 spin_unlock_irqrestore(&tp->lock, flags); 2144 } 2145 spin_unlock(&tp->rx_lock); 2146 2147 return work_done; 2148 } 2149 2150 /* The interrupt handler does all of the Rx thread work and cleans up 2151 after the Tx thread. */ 2152 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance) 2153 { 2154 struct net_device *dev = (struct net_device *) dev_instance; 2155 struct rtl8139_private *tp = netdev_priv(dev); 2156 void __iomem *ioaddr = tp->mmio_addr; 2157 u16 status, ackstat; 2158 int link_changed = 0; /* avoid bogus "uninit" warning */ 2159 int handled = 0; 2160 2161 spin_lock (&tp->lock); 2162 status = RTL_R16 (IntrStatus); 2163 2164 /* shared irq? */ 2165 if (unlikely((status & rtl8139_intr_mask) == 0)) 2166 goto out; 2167 2168 handled = 1; 2169 2170 /* h/w no longer present (hotplug?) or major error, bail */ 2171 if (unlikely(status == 0xFFFF)) 2172 goto out; 2173 2174 /* close possible race's with dev_close */ 2175 if (unlikely(!netif_running(dev))) { 2176 RTL_W16 (IntrMask, 0); 2177 goto out; 2178 } 2179 2180 /* Acknowledge all of the current interrupt sources ASAP, but 2181 an first get an additional status bit from CSCR. */ 2182 if (unlikely(status & RxUnderrun)) 2183 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit; 2184 2185 ackstat = status & ~(RxAckBits | TxErr); 2186 if (ackstat) 2187 RTL_W16 (IntrStatus, ackstat); 2188 2189 /* Receive packets are processed by poll routine. 2190 If not running start it now. */ 2191 if (status & RxAckBits){ 2192 if (napi_schedule_prep(&tp->napi)) { 2193 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask); 2194 __napi_schedule(&tp->napi); 2195 } 2196 } 2197 2198 /* Check uncommon events with one test. */ 2199 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr))) 2200 rtl8139_weird_interrupt (dev, tp, ioaddr, 2201 status, link_changed); 2202 2203 if (status & (TxOK | TxErr)) { 2204 rtl8139_tx_interrupt (dev, tp, ioaddr); 2205 if (status & TxErr) 2206 RTL_W16 (IntrStatus, TxErr); 2207 } 2208 out: 2209 spin_unlock (&tp->lock); 2210 2211 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n", 2212 RTL_R16(IntrStatus)); 2213 return IRQ_RETVAL(handled); 2214 } 2215 2216 #ifdef CONFIG_NET_POLL_CONTROLLER 2217 /* 2218 * Polling receive - used by netconsole and other diagnostic tools 2219 * to allow network i/o with interrupts disabled. 2220 */ 2221 static void rtl8139_poll_controller(struct net_device *dev) 2222 { 2223 struct rtl8139_private *tp = netdev_priv(dev); 2224 const int irq = tp->pci_dev->irq; 2225 2226 disable_irq(irq); 2227 rtl8139_interrupt(irq, dev); 2228 enable_irq(irq); 2229 } 2230 #endif 2231 2232 static int rtl8139_set_mac_address(struct net_device *dev, void *p) 2233 { 2234 struct rtl8139_private *tp = netdev_priv(dev); 2235 void __iomem *ioaddr = tp->mmio_addr; 2236 struct sockaddr *addr = p; 2237 2238 if (!is_valid_ether_addr(addr->sa_data)) 2239 return -EADDRNOTAVAIL; 2240 2241 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2242 2243 spin_lock_irq(&tp->lock); 2244 2245 RTL_W8_F(Cfg9346, Cfg9346_Unlock); 2246 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0))); 2247 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4))); 2248 RTL_W8_F(Cfg9346, Cfg9346_Lock); 2249 2250 spin_unlock_irq(&tp->lock); 2251 2252 return 0; 2253 } 2254 2255 static int rtl8139_close (struct net_device *dev) 2256 { 2257 struct rtl8139_private *tp = netdev_priv(dev); 2258 void __iomem *ioaddr = tp->mmio_addr; 2259 unsigned long flags; 2260 2261 netif_stop_queue(dev); 2262 napi_disable(&tp->napi); 2263 2264 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n", 2265 RTL_R16(IntrStatus)); 2266 2267 spin_lock_irqsave (&tp->lock, flags); 2268 2269 /* Stop the chip's Tx and Rx DMA processes. */ 2270 RTL_W8 (ChipCmd, 0); 2271 2272 /* Disable interrupts by clearing the interrupt mask. */ 2273 RTL_W16 (IntrMask, 0); 2274 2275 /* Update the error counts. */ 2276 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2277 RTL_W32 (RxMissed, 0); 2278 2279 spin_unlock_irqrestore (&tp->lock, flags); 2280 2281 free_irq(tp->pci_dev->irq, dev); 2282 2283 rtl8139_tx_clear (tp); 2284 2285 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 2286 tp->rx_ring, tp->rx_ring_dma); 2287 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 2288 tp->tx_bufs, tp->tx_bufs_dma); 2289 tp->rx_ring = NULL; 2290 tp->tx_bufs = NULL; 2291 2292 /* Green! Put the chip in low-power mode. */ 2293 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2294 2295 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 2296 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 2297 2298 return 0; 2299 } 2300 2301 2302 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to 2303 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and 2304 other threads or interrupts aren't messing with the 8139. */ 2305 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2306 { 2307 struct rtl8139_private *tp = netdev_priv(dev); 2308 void __iomem *ioaddr = tp->mmio_addr; 2309 2310 spin_lock_irq(&tp->lock); 2311 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 2312 u8 cfg3 = RTL_R8 (Config3); 2313 u8 cfg5 = RTL_R8 (Config5); 2314 2315 wol->supported = WAKE_PHY | WAKE_MAGIC 2316 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; 2317 2318 wol->wolopts = 0; 2319 if (cfg3 & Cfg3_LinkUp) 2320 wol->wolopts |= WAKE_PHY; 2321 if (cfg3 & Cfg3_Magic) 2322 wol->wolopts |= WAKE_MAGIC; 2323 /* (KON)FIXME: See how netdev_set_wol() handles the 2324 following constants. */ 2325 if (cfg5 & Cfg5_UWF) 2326 wol->wolopts |= WAKE_UCAST; 2327 if (cfg5 & Cfg5_MWF) 2328 wol->wolopts |= WAKE_MCAST; 2329 if (cfg5 & Cfg5_BWF) 2330 wol->wolopts |= WAKE_BCAST; 2331 } 2332 spin_unlock_irq(&tp->lock); 2333 } 2334 2335 2336 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes 2337 that wol points to kernel memory and other threads or interrupts 2338 aren't messing with the 8139. */ 2339 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2340 { 2341 struct rtl8139_private *tp = netdev_priv(dev); 2342 void __iomem *ioaddr = tp->mmio_addr; 2343 u32 support; 2344 u8 cfg3, cfg5; 2345 2346 support = ((rtl_chip_info[tp->chipset].flags & HasLWake) 2347 ? (WAKE_PHY | WAKE_MAGIC 2348 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST) 2349 : 0); 2350 if (wol->wolopts & ~support) 2351 return -EINVAL; 2352 2353 spin_lock_irq(&tp->lock); 2354 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic); 2355 if (wol->wolopts & WAKE_PHY) 2356 cfg3 |= Cfg3_LinkUp; 2357 if (wol->wolopts & WAKE_MAGIC) 2358 cfg3 |= Cfg3_Magic; 2359 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2360 RTL_W8 (Config3, cfg3); 2361 RTL_W8 (Cfg9346, Cfg9346_Lock); 2362 2363 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF); 2364 /* (KON)FIXME: These are untested. We may have to set the 2365 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no 2366 documentation. */ 2367 if (wol->wolopts & WAKE_UCAST) 2368 cfg5 |= Cfg5_UWF; 2369 if (wol->wolopts & WAKE_MCAST) 2370 cfg5 |= Cfg5_MWF; 2371 if (wol->wolopts & WAKE_BCAST) 2372 cfg5 |= Cfg5_BWF; 2373 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */ 2374 spin_unlock_irq(&tp->lock); 2375 2376 return 0; 2377 } 2378 2379 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2380 { 2381 struct rtl8139_private *tp = netdev_priv(dev); 2382 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2383 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2384 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 2385 } 2386 2387 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2388 { 2389 struct rtl8139_private *tp = netdev_priv(dev); 2390 spin_lock_irq(&tp->lock); 2391 mii_ethtool_gset(&tp->mii, cmd); 2392 spin_unlock_irq(&tp->lock); 2393 return 0; 2394 } 2395 2396 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2397 { 2398 struct rtl8139_private *tp = netdev_priv(dev); 2399 int rc; 2400 spin_lock_irq(&tp->lock); 2401 rc = mii_ethtool_sset(&tp->mii, cmd); 2402 spin_unlock_irq(&tp->lock); 2403 return rc; 2404 } 2405 2406 static int rtl8139_nway_reset(struct net_device *dev) 2407 { 2408 struct rtl8139_private *tp = netdev_priv(dev); 2409 return mii_nway_restart(&tp->mii); 2410 } 2411 2412 static u32 rtl8139_get_link(struct net_device *dev) 2413 { 2414 struct rtl8139_private *tp = netdev_priv(dev); 2415 return mii_link_ok(&tp->mii); 2416 } 2417 2418 static u32 rtl8139_get_msglevel(struct net_device *dev) 2419 { 2420 struct rtl8139_private *tp = netdev_priv(dev); 2421 return tp->msg_enable; 2422 } 2423 2424 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum) 2425 { 2426 struct rtl8139_private *tp = netdev_priv(dev); 2427 tp->msg_enable = datum; 2428 } 2429 2430 static int rtl8139_get_regs_len(struct net_device *dev) 2431 { 2432 struct rtl8139_private *tp; 2433 /* TODO: we are too slack to do reg dumping for pio, for now */ 2434 if (use_io) 2435 return 0; 2436 tp = netdev_priv(dev); 2437 return tp->regs_len; 2438 } 2439 2440 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) 2441 { 2442 struct rtl8139_private *tp; 2443 2444 /* TODO: we are too slack to do reg dumping for pio, for now */ 2445 if (use_io) 2446 return; 2447 tp = netdev_priv(dev); 2448 2449 regs->version = RTL_REGS_VER; 2450 2451 spin_lock_irq(&tp->lock); 2452 memcpy_fromio(regbuf, tp->mmio_addr, regs->len); 2453 spin_unlock_irq(&tp->lock); 2454 } 2455 2456 static int rtl8139_get_sset_count(struct net_device *dev, int sset) 2457 { 2458 switch (sset) { 2459 case ETH_SS_STATS: 2460 return RTL_NUM_STATS; 2461 default: 2462 return -EOPNOTSUPP; 2463 } 2464 } 2465 2466 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2467 { 2468 struct rtl8139_private *tp = netdev_priv(dev); 2469 2470 data[0] = tp->xstats.early_rx; 2471 data[1] = tp->xstats.tx_buf_mapped; 2472 data[2] = tp->xstats.tx_timeouts; 2473 data[3] = tp->xstats.rx_lost_in_ring; 2474 } 2475 2476 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2477 { 2478 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2479 } 2480 2481 static const struct ethtool_ops rtl8139_ethtool_ops = { 2482 .get_drvinfo = rtl8139_get_drvinfo, 2483 .get_settings = rtl8139_get_settings, 2484 .set_settings = rtl8139_set_settings, 2485 .get_regs_len = rtl8139_get_regs_len, 2486 .get_regs = rtl8139_get_regs, 2487 .nway_reset = rtl8139_nway_reset, 2488 .get_link = rtl8139_get_link, 2489 .get_msglevel = rtl8139_get_msglevel, 2490 .set_msglevel = rtl8139_set_msglevel, 2491 .get_wol = rtl8139_get_wol, 2492 .set_wol = rtl8139_set_wol, 2493 .get_strings = rtl8139_get_strings, 2494 .get_sset_count = rtl8139_get_sset_count, 2495 .get_ethtool_stats = rtl8139_get_ethtool_stats, 2496 }; 2497 2498 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2499 { 2500 struct rtl8139_private *tp = netdev_priv(dev); 2501 int rc; 2502 2503 if (!netif_running(dev)) 2504 return -EINVAL; 2505 2506 spin_lock_irq(&tp->lock); 2507 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL); 2508 spin_unlock_irq(&tp->lock); 2509 2510 return rc; 2511 } 2512 2513 2514 static void 2515 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 2516 { 2517 struct rtl8139_private *tp = netdev_priv(dev); 2518 void __iomem *ioaddr = tp->mmio_addr; 2519 unsigned long flags; 2520 unsigned int start; 2521 2522 if (netif_running(dev)) { 2523 spin_lock_irqsave (&tp->lock, flags); 2524 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2525 RTL_W32 (RxMissed, 0); 2526 spin_unlock_irqrestore (&tp->lock, flags); 2527 } 2528 2529 netdev_stats_to_stats64(stats, &dev->stats); 2530 2531 do { 2532 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 2533 stats->rx_packets = tp->rx_stats.packets; 2534 stats->rx_bytes = tp->rx_stats.bytes; 2535 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 2536 2537 do { 2538 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 2539 stats->tx_packets = tp->tx_stats.packets; 2540 stats->tx_bytes = tp->tx_stats.bytes; 2541 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 2542 } 2543 2544 /* Set or clear the multicast filter for this adaptor. 2545 This routine is not state sensitive and need not be SMP locked. */ 2546 2547 static void __set_rx_mode (struct net_device *dev) 2548 { 2549 struct rtl8139_private *tp = netdev_priv(dev); 2550 void __iomem *ioaddr = tp->mmio_addr; 2551 u32 mc_filter[2]; /* Multicast hash filter */ 2552 int rx_mode; 2553 u32 tmp; 2554 2555 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n", 2556 dev->flags, RTL_R32(RxConfig)); 2557 2558 /* Note: do not reorder, GCC is clever about common statements. */ 2559 if (dev->flags & IFF_PROMISC) { 2560 rx_mode = 2561 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 2562 AcceptAllPhys; 2563 mc_filter[1] = mc_filter[0] = 0xffffffff; 2564 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2565 (dev->flags & IFF_ALLMULTI)) { 2566 /* Too many to filter perfectly -- accept all multicasts. */ 2567 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 2568 mc_filter[1] = mc_filter[0] = 0xffffffff; 2569 } else { 2570 struct netdev_hw_addr *ha; 2571 rx_mode = AcceptBroadcast | AcceptMyPhys; 2572 mc_filter[1] = mc_filter[0] = 0; 2573 netdev_for_each_mc_addr(ha, dev) { 2574 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2575 2576 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2577 rx_mode |= AcceptMulticast; 2578 } 2579 } 2580 2581 if (dev->features & NETIF_F_RXALL) 2582 rx_mode |= (AcceptErr | AcceptRunt); 2583 2584 /* We can safely update without stopping the chip. */ 2585 tmp = rtl8139_rx_config | rx_mode; 2586 if (tp->rx_config != tmp) { 2587 RTL_W32_F (RxConfig, tmp); 2588 tp->rx_config = tmp; 2589 } 2590 RTL_W32_F (MAR0 + 0, mc_filter[0]); 2591 RTL_W32_F (MAR0 + 4, mc_filter[1]); 2592 } 2593 2594 static void rtl8139_set_rx_mode (struct net_device *dev) 2595 { 2596 unsigned long flags; 2597 struct rtl8139_private *tp = netdev_priv(dev); 2598 2599 spin_lock_irqsave (&tp->lock, flags); 2600 __set_rx_mode(dev); 2601 spin_unlock_irqrestore (&tp->lock, flags); 2602 } 2603 2604 #ifdef CONFIG_PM 2605 2606 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state) 2607 { 2608 struct net_device *dev = pci_get_drvdata (pdev); 2609 struct rtl8139_private *tp = netdev_priv(dev); 2610 void __iomem *ioaddr = tp->mmio_addr; 2611 unsigned long flags; 2612 2613 pci_save_state (pdev); 2614 2615 if (!netif_running (dev)) 2616 return 0; 2617 2618 netif_device_detach (dev); 2619 2620 spin_lock_irqsave (&tp->lock, flags); 2621 2622 /* Disable interrupts, stop Tx and Rx. */ 2623 RTL_W16 (IntrMask, 0); 2624 RTL_W8 (ChipCmd, 0); 2625 2626 /* Update the error counts. */ 2627 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2628 RTL_W32 (RxMissed, 0); 2629 2630 spin_unlock_irqrestore (&tp->lock, flags); 2631 2632 pci_set_power_state (pdev, PCI_D3hot); 2633 2634 return 0; 2635 } 2636 2637 2638 static int rtl8139_resume (struct pci_dev *pdev) 2639 { 2640 struct net_device *dev = pci_get_drvdata (pdev); 2641 2642 pci_restore_state (pdev); 2643 if (!netif_running (dev)) 2644 return 0; 2645 pci_set_power_state (pdev, PCI_D0); 2646 rtl8139_init_ring (dev); 2647 rtl8139_hw_start (dev); 2648 netif_device_attach (dev); 2649 return 0; 2650 } 2651 2652 #endif /* CONFIG_PM */ 2653 2654 2655 static struct pci_driver rtl8139_pci_driver = { 2656 .name = DRV_NAME, 2657 .id_table = rtl8139_pci_tbl, 2658 .probe = rtl8139_init_one, 2659 .remove = rtl8139_remove_one, 2660 #ifdef CONFIG_PM 2661 .suspend = rtl8139_suspend, 2662 .resume = rtl8139_resume, 2663 #endif /* CONFIG_PM */ 2664 }; 2665 2666 2667 static int __init rtl8139_init_module (void) 2668 { 2669 /* when we're a module, we always print a version message, 2670 * even if no 8139 board is found. 2671 */ 2672 #ifdef MODULE 2673 pr_info(RTL8139_DRIVER_NAME "\n"); 2674 #endif 2675 2676 return pci_register_driver(&rtl8139_pci_driver); 2677 } 2678 2679 2680 static void __exit rtl8139_cleanup_module (void) 2681 { 2682 pci_unregister_driver (&rtl8139_pci_driver); 2683 } 2684 2685 2686 module_init(rtl8139_init_module); 2687 module_exit(rtl8139_cleanup_module); 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