1 /* 2 3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux. 4 5 Maintained by Jeff Garzik <jgarzik@pobox.com> 6 Copyright 2000-2002 Jeff Garzik 7 8 Much code comes from Donald Becker's rtl8139.c driver, 9 versions 1.13 and older. This driver was originally based 10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13: 11 12 -----<snip>----- 13 14 Written 1997-2001 by Donald Becker. 15 This software may be used and distributed according to the 16 terms of the GNU General Public License (GPL), incorporated 17 herein by reference. Drivers based on or derived from this 18 code fall under the GPL and must retain the authorship, 19 copyright and license notice. This file is not a complete 20 program and may only be used when the entire operating 21 system is licensed under the GPL. 22 23 This driver is for boards based on the RTL8129 and RTL8139 24 PCI ethernet chips. 25 26 The author may be reached as becker@scyld.com, or C/O Scyld 27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis 28 MD 21403 29 30 Support and updates available at 31 http://www.scyld.com/network/rtl8139.html 32 33 Twister-tuning table provided by Kinston 34 <shangh@realtek.com.tw>. 35 36 -----<snip>----- 37 38 This software may be used and distributed according to the terms 39 of the GNU General Public License, incorporated herein by reference. 40 41 Contributors: 42 43 Donald Becker - he wrote the original driver, kudos to him! 44 (but please don't e-mail him for support, this isn't his driver) 45 46 Tigran Aivazian - bug fixes, skbuff free cleanup 47 48 Martin Mares - suggestions for PCI cleanup 49 50 David S. Miller - PCI DMA and softnet updates 51 52 Ernst Gill - fixes ported from BSD driver 53 54 Daniel Kobras - identified specific locations of 55 posted MMIO write bugginess 56 57 Gerard Sharp - bug fix, testing and feedback 58 59 David Ford - Rx ring wrap fix 60 61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me 62 to find and fix a crucial bug on older chipsets. 63 64 Donald Becker/Chris Butterworth/Marcus Westergren - 65 Noticed various Rx packet size-related buglets. 66 67 Santiago Garcia Mantinan - testing and feedback 68 69 Jens David - 2.2.x kernel backports 70 71 Martin Dennett - incredibly helpful insight on undocumented 72 features of the 8139 chips 73 74 Jean-Jacques Michel - bug fix 75 76 Tobias Ringström - Rx interrupt status checking suggestion 77 78 Andrew Morton - Clear blocked signals, avoid 79 buffer overrun setting current->comm. 80 81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls 82 83 Robert Kuebel - Save kernel thread from dying on any signal. 84 85 Submitting bug reports: 86 87 "rtl8139-diag -mmmaaavvveefN" output 88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log 89 90 */ 91 92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 93 94 #define DRV_NAME "8139too" 95 #define DRV_VERSION "0.9.28" 96 97 98 #include <linux/module.h> 99 #include <linux/kernel.h> 100 #include <linux/compiler.h> 101 #include <linux/pci.h> 102 #include <linux/init.h> 103 #include <linux/interrupt.h> 104 #include <linux/netdevice.h> 105 #include <linux/etherdevice.h> 106 #include <linux/rtnetlink.h> 107 #include <linux/delay.h> 108 #include <linux/ethtool.h> 109 #include <linux/mii.h> 110 #include <linux/completion.h> 111 #include <linux/crc32.h> 112 #include <linux/io.h> 113 #include <linux/uaccess.h> 114 #include <linux/gfp.h> 115 #include <linux/if_vlan.h> 116 #include <asm/irq.h> 117 118 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION 119 120 /* Default Message level */ 121 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 122 NETIF_MSG_PROBE | \ 123 NETIF_MSG_LINK) 124 125 126 /* define to 1, 2 or 3 to enable copious debugging info */ 127 #define RTL8139_DEBUG 0 128 129 /* define to 1 to disable lightweight runtime debugging checks */ 130 #undef RTL8139_NDEBUG 131 132 133 #ifdef RTL8139_NDEBUG 134 # define assert(expr) do {} while (0) 135 #else 136 # define assert(expr) \ 137 if (unlikely(!(expr))) { \ 138 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \ 139 #expr, __FILE__, __func__, __LINE__); \ 140 } 141 #endif 142 143 144 /* A few user-configurable values. */ 145 /* media options */ 146 #define MAX_UNITS 8 147 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 148 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 149 150 /* Whether to use MMIO or PIO. Default to MMIO. */ 151 #ifdef CONFIG_8139TOO_PIO 152 static bool use_io = true; 153 #else 154 static bool use_io = false; 155 #endif 156 157 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 158 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 159 static int multicast_filter_limit = 32; 160 161 /* bitmapped message enable number */ 162 static int debug = -1; 163 164 /* 165 * Receive ring size 166 * Warning: 64K ring has hardware issues and may lock up. 167 */ 168 #if defined(CONFIG_SH_DREAMCAST) 169 #define RX_BUF_IDX 0 /* 8K ring */ 170 #else 171 #define RX_BUF_IDX 2 /* 32K ring */ 172 #endif 173 #define RX_BUF_LEN (8192 << RX_BUF_IDX) 174 #define RX_BUF_PAD 16 175 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */ 176 177 #if RX_BUF_LEN == 65536 178 #define RX_BUF_TOT_LEN RX_BUF_LEN 179 #else 180 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD) 181 #endif 182 183 /* Number of Tx descriptor registers. */ 184 #define NUM_TX_DESC 4 185 186 /* max supported ethernet frame size -- must be at least (dev->mtu+18+4).*/ 187 #define MAX_ETH_FRAME_SIZE 1792 188 189 /* max supported payload size */ 190 #define MAX_ETH_DATA_SIZE (MAX_ETH_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN) 191 192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+18+4). */ 193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE 194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) 195 196 /* PCI Tuning Parameters 197 Threshold is bytes transferred to chip before transmission starts. */ 198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 199 200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ 201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ 202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */ 203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */ 205 206 /* Operational parameters that usually are not changed. */ 207 /* Time in jiffies before concluding the transmitter is hung. */ 208 #define TX_TIMEOUT (6*HZ) 209 210 211 enum { 212 HAS_MII_XCVR = 0x010000, 213 HAS_CHIP_XCVR = 0x020000, 214 HAS_LNK_CHNG = 0x040000, 215 }; 216 217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */ 218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */ 219 #define RTL_MIN_IO_SIZE 0x80 220 #define RTL8139B_IO_SIZE 256 221 222 #define RTL8129_CAPS HAS_MII_XCVR 223 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG) 224 225 typedef enum { 226 RTL8139 = 0, 227 RTL8129, 228 } board_t; 229 230 231 /* indexed by board_t, above */ 232 static const struct { 233 const char *name; 234 u32 hw_flags; 235 } board_info[] = { 236 { "RealTek RTL8139", RTL8139_CAPS }, 237 { "RealTek RTL8129", RTL8129_CAPS }, 238 }; 239 240 241 static const struct pci_device_id rtl8139_pci_tbl[] = { 242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 261 262 #ifdef CONFIG_SH_SECUREEDGE5410 263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */ 264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 265 #endif 266 #ifdef CONFIG_8139TOO_8129 267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 }, 268 #endif 269 270 /* some crazy cards report invalid vendor ids like 271 * 0x0001 here. The other ids are valid and constant, 272 * so we simply don't match on the main vendor id. 273 */ 274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 }, 275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 }, 276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 }, 277 278 {0,} 279 }; 280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl); 281 282 static struct { 283 const char str[ETH_GSTRING_LEN]; 284 } ethtool_stats_keys[] = { 285 { "early_rx" }, 286 { "tx_buf_mapped" }, 287 { "tx_timeouts" }, 288 { "rx_lost_in_ring" }, 289 }; 290 291 /* The rest of these values should never change. */ 292 293 /* Symbolic offsets to registers. */ 294 enum RTL8139_registers { 295 MAC0 = 0, /* Ethernet hardware address. */ 296 MAR0 = 8, /* Multicast filter. */ 297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ 298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 299 RxBuf = 0x30, 300 ChipCmd = 0x37, 301 RxBufPtr = 0x38, 302 RxBufAddr = 0x3A, 303 IntrMask = 0x3C, 304 IntrStatus = 0x3E, 305 TxConfig = 0x40, 306 RxConfig = 0x44, 307 Timer = 0x48, /* A general-purpose counter. */ 308 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 309 Cfg9346 = 0x50, 310 Config0 = 0x51, 311 Config1 = 0x52, 312 TimerInt = 0x54, 313 MediaStatus = 0x58, 314 Config3 = 0x59, 315 Config4 = 0x5A, /* absent on RTL-8139A */ 316 HltClk = 0x5B, 317 MultiIntr = 0x5C, 318 TxSummary = 0x60, 319 BasicModeCtrl = 0x62, 320 BasicModeStatus = 0x64, 321 NWayAdvert = 0x66, 322 NWayLPAR = 0x68, 323 NWayExpansion = 0x6A, 324 /* Undocumented registers, but required for proper operation. */ 325 FIFOTMS = 0x70, /* FIFO Control and test. */ 326 CSCR = 0x74, /* Chip Status and Configuration Register. */ 327 PARA78 = 0x78, 328 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */ 329 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 330 Config5 = 0xD8, /* absent on RTL-8139A */ 331 }; 332 333 enum ClearBitMasks { 334 MultiIntrClear = 0xF000, 335 ChipCmdClear = 0xE2, 336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 337 }; 338 339 enum ChipCmdBits { 340 CmdReset = 0x10, 341 CmdRxEnb = 0x08, 342 CmdTxEnb = 0x04, 343 RxBufEmpty = 0x01, 344 }; 345 346 /* Interrupt register bits, using my own meaningful names. */ 347 enum IntrStatusBits { 348 PCIErr = 0x8000, 349 PCSTimeout = 0x4000, 350 RxFIFOOver = 0x40, 351 RxUnderrun = 0x20, 352 RxOverflow = 0x10, 353 TxErr = 0x08, 354 TxOK = 0x04, 355 RxErr = 0x02, 356 RxOK = 0x01, 357 358 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 359 }; 360 361 enum TxStatusBits { 362 TxHostOwns = 0x2000, 363 TxUnderrun = 0x4000, 364 TxStatOK = 0x8000, 365 TxOutOfWindow = 0x20000000, 366 TxAborted = 0x40000000, 367 TxCarrierLost = 0x80000000, 368 }; 369 enum RxStatusBits { 370 RxMulticast = 0x8000, 371 RxPhysical = 0x4000, 372 RxBroadcast = 0x2000, 373 RxBadSymbol = 0x0020, 374 RxRunt = 0x0010, 375 RxTooLong = 0x0008, 376 RxCRCErr = 0x0004, 377 RxBadAlign = 0x0002, 378 RxStatusOK = 0x0001, 379 }; 380 381 /* Bits in RxConfig. */ 382 enum rx_mode_bits { 383 AcceptErr = 0x20, 384 AcceptRunt = 0x10, 385 AcceptBroadcast = 0x08, 386 AcceptMulticast = 0x04, 387 AcceptMyPhys = 0x02, 388 AcceptAllPhys = 0x01, 389 }; 390 391 /* Bits in TxConfig. */ 392 enum tx_config_bits { 393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 394 TxIFGShift = 24, 395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 399 400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 401 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */ 402 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */ 404 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */ 405 406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 407 }; 408 409 /* Bits in Config1 */ 410 enum Config1Bits { 411 Cfg1_PM_Enable = 0x01, 412 Cfg1_VPD_Enable = 0x02, 413 Cfg1_PIO = 0x04, 414 Cfg1_MMIO = 0x08, 415 LWAKE = 0x10, /* not on 8139, 8139A */ 416 Cfg1_Driver_Load = 0x20, 417 Cfg1_LED0 = 0x40, 418 Cfg1_LED1 = 0x80, 419 SLEEP = (1 << 1), /* only on 8139, 8139A */ 420 PWRDN = (1 << 0), /* only on 8139, 8139A */ 421 }; 422 423 /* Bits in Config3 */ 424 enum Config3Bits { 425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 433 }; 434 435 /* Bits in Config4 */ 436 enum Config4Bits { 437 LWPTN = (1 << 2), /* not on 8139, 8139A */ 438 }; 439 440 /* Bits in Config5 */ 441 enum Config5Bits { 442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 445 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */ 446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 449 }; 450 451 enum RxConfigBits { 452 /* rx fifo threshold */ 453 RxCfgFIFOShift = 13, 454 RxCfgFIFONone = (7 << RxCfgFIFOShift), 455 456 /* Max DMA burst */ 457 RxCfgDMAShift = 8, 458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 459 460 /* rx ring buffer length */ 461 RxCfgRcv8K = 0, 462 RxCfgRcv16K = (1 << 11), 463 RxCfgRcv32K = (1 << 12), 464 RxCfgRcv64K = (1 << 11) | (1 << 12), 465 466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 467 RxNoWrap = (1 << 7), 468 }; 469 470 /* Twister tuning parameters from RealTek. 471 Completely undocumented, but required to tune bad links on some boards. */ 472 enum CSCRBits { 473 CSCR_LinkOKBit = 0x0400, 474 CSCR_LinkChangeBit = 0x0800, 475 CSCR_LinkStatusBits = 0x0f000, 476 CSCR_LinkDownOffCmd = 0x003c0, 477 CSCR_LinkDownCmd = 0x0f3c0, 478 }; 479 480 enum Cfg9346Bits { 481 Cfg9346_Lock = 0x00, 482 Cfg9346_Unlock = 0xC0, 483 }; 484 485 typedef enum { 486 CH_8139 = 0, 487 CH_8139_K, 488 CH_8139A, 489 CH_8139A_G, 490 CH_8139B, 491 CH_8130, 492 CH_8139C, 493 CH_8100, 494 CH_8100B_8139D, 495 CH_8101, 496 } chip_t; 497 498 enum chip_flags { 499 HasHltClk = (1 << 0), 500 HasLWake = (1 << 1), 501 }; 502 503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 506 507 /* directly indexed by chip_t, above */ 508 static const struct { 509 const char *name; 510 u32 version; /* from RTL8139C/RTL8139D docs */ 511 u32 flags; 512 } rtl_chip_info[] = { 513 { "RTL-8139", 514 HW_REVID(1, 0, 0, 0, 0, 0, 0), 515 HasHltClk, 516 }, 517 518 { "RTL-8139 rev K", 519 HW_REVID(1, 1, 0, 0, 0, 0, 0), 520 HasHltClk, 521 }, 522 523 { "RTL-8139A", 524 HW_REVID(1, 1, 1, 0, 0, 0, 0), 525 HasHltClk, /* XXX undocumented? */ 526 }, 527 528 { "RTL-8139A rev G", 529 HW_REVID(1, 1, 1, 0, 0, 1, 0), 530 HasHltClk, /* XXX undocumented? */ 531 }, 532 533 { "RTL-8139B", 534 HW_REVID(1, 1, 1, 1, 0, 0, 0), 535 HasLWake, 536 }, 537 538 { "RTL-8130", 539 HW_REVID(1, 1, 1, 1, 1, 0, 0), 540 HasLWake, 541 }, 542 543 { "RTL-8139C", 544 HW_REVID(1, 1, 1, 0, 1, 0, 0), 545 HasLWake, 546 }, 547 548 { "RTL-8100", 549 HW_REVID(1, 1, 1, 1, 0, 1, 0), 550 HasLWake, 551 }, 552 553 { "RTL-8100B/8139D", 554 HW_REVID(1, 1, 1, 0, 1, 0, 1), 555 HasHltClk /* XXX undocumented? */ 556 | HasLWake, 557 }, 558 559 { "RTL-8101", 560 HW_REVID(1, 1, 1, 0, 1, 1, 1), 561 HasLWake, 562 }, 563 }; 564 565 struct rtl_extra_stats { 566 unsigned long early_rx; 567 unsigned long tx_buf_mapped; 568 unsigned long tx_timeouts; 569 unsigned long rx_lost_in_ring; 570 }; 571 572 struct rtl8139_stats { 573 u64 packets; 574 u64 bytes; 575 struct u64_stats_sync syncp; 576 }; 577 578 struct rtl8139_private { 579 void __iomem *mmio_addr; 580 int drv_flags; 581 struct pci_dev *pci_dev; 582 u32 msg_enable; 583 struct napi_struct napi; 584 struct net_device *dev; 585 586 unsigned char *rx_ring; 587 unsigned int cur_rx; /* RX buf index of next pkt */ 588 struct rtl8139_stats rx_stats; 589 dma_addr_t rx_ring_dma; 590 591 unsigned int tx_flag; 592 unsigned long cur_tx; 593 unsigned long dirty_tx; 594 struct rtl8139_stats tx_stats; 595 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */ 596 unsigned char *tx_bufs; /* Tx bounce buffer region. */ 597 dma_addr_t tx_bufs_dma; 598 599 signed char phys[4]; /* MII device addresses. */ 600 601 /* Twister tune state. */ 602 char twistie, twist_row, twist_col; 603 604 unsigned int watchdog_fired : 1; 605 unsigned int default_port : 4; /* Last dev->if_port value. */ 606 unsigned int have_thread : 1; 607 608 spinlock_t lock; 609 spinlock_t rx_lock; 610 611 chip_t chipset; 612 u32 rx_config; 613 struct rtl_extra_stats xstats; 614 615 struct delayed_work thread; 616 617 struct mii_if_info mii; 618 unsigned int regs_len; 619 unsigned long fifo_copy_timeout; 620 }; 621 622 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>"); 623 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver"); 624 MODULE_LICENSE("GPL"); 625 MODULE_VERSION(DRV_VERSION); 626 627 module_param(use_io, bool, 0); 628 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO"); 629 module_param(multicast_filter_limit, int, 0); 630 module_param_array(media, int, NULL, 0); 631 module_param_array(full_duplex, int, NULL, 0); 632 module_param(debug, int, 0); 633 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number"); 634 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses"); 635 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps"); 636 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)"); 637 638 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len); 639 static int rtl8139_open (struct net_device *dev); 640 static int mdio_read (struct net_device *dev, int phy_id, int location); 641 static void mdio_write (struct net_device *dev, int phy_id, int location, 642 int val); 643 static void rtl8139_start_thread(struct rtl8139_private *tp); 644 static void rtl8139_tx_timeout (struct net_device *dev); 645 static void rtl8139_init_ring (struct net_device *dev); 646 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 647 struct net_device *dev); 648 #ifdef CONFIG_NET_POLL_CONTROLLER 649 static void rtl8139_poll_controller(struct net_device *dev); 650 #endif 651 static int rtl8139_set_mac_address(struct net_device *dev, void *p); 652 static int rtl8139_poll(struct napi_struct *napi, int budget); 653 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance); 654 static int rtl8139_close (struct net_device *dev); 655 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 656 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev, 657 struct rtnl_link_stats64 658 *stats); 659 static void rtl8139_set_rx_mode (struct net_device *dev); 660 static void __set_rx_mode (struct net_device *dev); 661 static void rtl8139_hw_start (struct net_device *dev); 662 static void rtl8139_thread (struct work_struct *work); 663 static void rtl8139_tx_timeout_task(struct work_struct *work); 664 static const struct ethtool_ops rtl8139_ethtool_ops; 665 666 /* write MMIO register, with flush */ 667 /* Flush avoids rtl8139 bug w/ posted MMIO writes */ 668 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0) 669 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0) 670 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0) 671 672 /* write MMIO register */ 673 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg)) 674 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg)) 675 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg)) 676 677 /* read MMIO register */ 678 #define RTL_R8(reg) ioread8 (ioaddr + (reg)) 679 #define RTL_R16(reg) ioread16 (ioaddr + (reg)) 680 #define RTL_R32(reg) ioread32 (ioaddr + (reg)) 681 682 683 static const u16 rtl8139_intr_mask = 684 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | 685 TxErr | TxOK | RxErr | RxOK; 686 687 static const u16 rtl8139_norx_intr_mask = 688 PCIErr | PCSTimeout | RxUnderrun | 689 TxErr | TxOK | RxErr ; 690 691 #if RX_BUF_IDX == 0 692 static const unsigned int rtl8139_rx_config = 693 RxCfgRcv8K | RxNoWrap | 694 (RX_FIFO_THRESH << RxCfgFIFOShift) | 695 (RX_DMA_BURST << RxCfgDMAShift); 696 #elif RX_BUF_IDX == 1 697 static const unsigned int rtl8139_rx_config = 698 RxCfgRcv16K | RxNoWrap | 699 (RX_FIFO_THRESH << RxCfgFIFOShift) | 700 (RX_DMA_BURST << RxCfgDMAShift); 701 #elif RX_BUF_IDX == 2 702 static const unsigned int rtl8139_rx_config = 703 RxCfgRcv32K | RxNoWrap | 704 (RX_FIFO_THRESH << RxCfgFIFOShift) | 705 (RX_DMA_BURST << RxCfgDMAShift); 706 #elif RX_BUF_IDX == 3 707 static const unsigned int rtl8139_rx_config = 708 RxCfgRcv64K | 709 (RX_FIFO_THRESH << RxCfgFIFOShift) | 710 (RX_DMA_BURST << RxCfgDMAShift); 711 #else 712 #error "Invalid configuration for 8139_RXBUF_IDX" 713 #endif 714 715 static const unsigned int rtl8139_tx_config = 716 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift); 717 718 static void __rtl8139_cleanup_dev (struct net_device *dev) 719 { 720 struct rtl8139_private *tp = netdev_priv(dev); 721 struct pci_dev *pdev; 722 723 assert (dev != NULL); 724 assert (tp->pci_dev != NULL); 725 pdev = tp->pci_dev; 726 727 if (tp->mmio_addr) 728 pci_iounmap (pdev, tp->mmio_addr); 729 730 /* it's ok to call this even if we have no regions to free */ 731 pci_release_regions (pdev); 732 733 free_netdev(dev); 734 } 735 736 737 static void rtl8139_chip_reset (void __iomem *ioaddr) 738 { 739 int i; 740 741 /* Soft reset the chip. */ 742 RTL_W8 (ChipCmd, CmdReset); 743 744 /* Check that the chip has finished the reset. */ 745 for (i = 1000; i > 0; i--) { 746 barrier(); 747 if ((RTL_R8 (ChipCmd) & CmdReset) == 0) 748 break; 749 udelay (10); 750 } 751 } 752 753 754 static struct net_device *rtl8139_init_board(struct pci_dev *pdev) 755 { 756 struct device *d = &pdev->dev; 757 void __iomem *ioaddr; 758 struct net_device *dev; 759 struct rtl8139_private *tp; 760 u8 tmp8; 761 int rc, disable_dev_on_err = 0; 762 unsigned int i, bar; 763 unsigned long io_len; 764 u32 version; 765 static const struct { 766 unsigned long mask; 767 char *type; 768 } res[] = { 769 { IORESOURCE_IO, "PIO" }, 770 { IORESOURCE_MEM, "MMIO" } 771 }; 772 773 assert (pdev != NULL); 774 775 /* dev and priv zeroed in alloc_etherdev */ 776 dev = alloc_etherdev (sizeof (*tp)); 777 if (dev == NULL) 778 return ERR_PTR(-ENOMEM); 779 780 SET_NETDEV_DEV(dev, &pdev->dev); 781 782 tp = netdev_priv(dev); 783 tp->pci_dev = pdev; 784 785 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 786 rc = pci_enable_device (pdev); 787 if (rc) 788 goto err_out; 789 790 disable_dev_on_err = 1; 791 rc = pci_request_regions (pdev, DRV_NAME); 792 if (rc) 793 goto err_out; 794 795 pci_set_master (pdev); 796 797 u64_stats_init(&tp->rx_stats.syncp); 798 u64_stats_init(&tp->tx_stats.syncp); 799 800 retry: 801 /* PIO bar register comes first. */ 802 bar = !use_io; 803 804 io_len = pci_resource_len(pdev, bar); 805 806 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len); 807 808 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) { 809 dev_err(d, "region #%d not a %s resource, aborting\n", bar, 810 res[bar].type); 811 rc = -ENODEV; 812 goto err_out; 813 } 814 if (io_len < RTL_MIN_IO_SIZE) { 815 dev_err(d, "Invalid PCI %s region size(s), aborting\n", 816 res[bar].type); 817 rc = -ENODEV; 818 goto err_out; 819 } 820 821 ioaddr = pci_iomap(pdev, bar, 0); 822 if (!ioaddr) { 823 dev_err(d, "cannot map %s\n", res[bar].type); 824 if (!use_io) { 825 use_io = true; 826 goto retry; 827 } 828 rc = -ENODEV; 829 goto err_out; 830 } 831 tp->regs_len = io_len; 832 tp->mmio_addr = ioaddr; 833 834 /* Bring old chips out of low-power mode. */ 835 RTL_W8 (HltClk, 'R'); 836 837 /* check for missing/broken hardware */ 838 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) { 839 dev_err(&pdev->dev, "Chip not responding, ignoring board\n"); 840 rc = -EIO; 841 goto err_out; 842 } 843 844 /* identify chip attached to board */ 845 version = RTL_R32 (TxConfig) & HW_REVID_MASK; 846 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++) 847 if (version == rtl_chip_info[i].version) { 848 tp->chipset = i; 849 goto match; 850 } 851 852 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ 853 i = 0; 854 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); 855 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); 856 tp->chipset = 0; 857 858 match: 859 pr_debug("chipset id (%d) == index %d, '%s'\n", 860 version, i, rtl_chip_info[i].name); 861 862 if (tp->chipset >= CH_8139B) { 863 u8 new_tmp8 = tmp8 = RTL_R8 (Config1); 864 pr_debug("PCI PM wakeup\n"); 865 if ((rtl_chip_info[tp->chipset].flags & HasLWake) && 866 (tmp8 & LWAKE)) 867 new_tmp8 &= ~LWAKE; 868 new_tmp8 |= Cfg1_PM_Enable; 869 if (new_tmp8 != tmp8) { 870 RTL_W8 (Cfg9346, Cfg9346_Unlock); 871 RTL_W8 (Config1, tmp8); 872 RTL_W8 (Cfg9346, Cfg9346_Lock); 873 } 874 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 875 tmp8 = RTL_R8 (Config4); 876 if (tmp8 & LWPTN) { 877 RTL_W8 (Cfg9346, Cfg9346_Unlock); 878 RTL_W8 (Config4, tmp8 & ~LWPTN); 879 RTL_W8 (Cfg9346, Cfg9346_Lock); 880 } 881 } 882 } else { 883 pr_debug("Old chip wakeup\n"); 884 tmp8 = RTL_R8 (Config1); 885 tmp8 &= ~(SLEEP | PWRDN); 886 RTL_W8 (Config1, tmp8); 887 } 888 889 rtl8139_chip_reset (ioaddr); 890 891 return dev; 892 893 err_out: 894 __rtl8139_cleanup_dev (dev); 895 if (disable_dev_on_err) 896 pci_disable_device (pdev); 897 return ERR_PTR(rc); 898 } 899 900 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features) 901 { 902 struct rtl8139_private *tp = netdev_priv(dev); 903 unsigned long flags; 904 netdev_features_t changed = features ^ dev->features; 905 void __iomem *ioaddr = tp->mmio_addr; 906 907 if (!(changed & (NETIF_F_RXALL))) 908 return 0; 909 910 spin_lock_irqsave(&tp->lock, flags); 911 912 if (changed & NETIF_F_RXALL) { 913 int rx_mode = tp->rx_config; 914 if (features & NETIF_F_RXALL) 915 rx_mode |= (AcceptErr | AcceptRunt); 916 else 917 rx_mode &= ~(AcceptErr | AcceptRunt); 918 tp->rx_config = rtl8139_rx_config | rx_mode; 919 RTL_W32_F(RxConfig, tp->rx_config); 920 } 921 922 spin_unlock_irqrestore(&tp->lock, flags); 923 924 return 0; 925 } 926 927 static int rtl8139_change_mtu(struct net_device *dev, int new_mtu) 928 { 929 if (new_mtu < 68 || new_mtu > MAX_ETH_DATA_SIZE) 930 return -EINVAL; 931 dev->mtu = new_mtu; 932 return 0; 933 } 934 935 static const struct net_device_ops rtl8139_netdev_ops = { 936 .ndo_open = rtl8139_open, 937 .ndo_stop = rtl8139_close, 938 .ndo_get_stats64 = rtl8139_get_stats64, 939 .ndo_change_mtu = rtl8139_change_mtu, 940 .ndo_validate_addr = eth_validate_addr, 941 .ndo_set_mac_address = rtl8139_set_mac_address, 942 .ndo_start_xmit = rtl8139_start_xmit, 943 .ndo_set_rx_mode = rtl8139_set_rx_mode, 944 .ndo_do_ioctl = netdev_ioctl, 945 .ndo_tx_timeout = rtl8139_tx_timeout, 946 #ifdef CONFIG_NET_POLL_CONTROLLER 947 .ndo_poll_controller = rtl8139_poll_controller, 948 #endif 949 .ndo_set_features = rtl8139_set_features, 950 }; 951 952 static int rtl8139_init_one(struct pci_dev *pdev, 953 const struct pci_device_id *ent) 954 { 955 struct net_device *dev = NULL; 956 struct rtl8139_private *tp; 957 int i, addr_len, option; 958 void __iomem *ioaddr; 959 static int board_idx = -1; 960 961 assert (pdev != NULL); 962 assert (ent != NULL); 963 964 board_idx++; 965 966 /* when we're built into the kernel, the driver version message 967 * is only printed if at least one 8139 board has been found 968 */ 969 #ifndef MODULE 970 { 971 static int printed_version; 972 if (!printed_version++) 973 pr_info(RTL8139_DRIVER_NAME "\n"); 974 } 975 #endif 976 977 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 978 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) { 979 dev_info(&pdev->dev, 980 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n", 981 pdev->vendor, pdev->device, pdev->revision); 982 return -ENODEV; 983 } 984 985 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 986 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && 987 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS && 988 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) { 989 pr_info("OQO Model 2 detected. Forcing PIO\n"); 990 use_io = 1; 991 } 992 993 dev = rtl8139_init_board (pdev); 994 if (IS_ERR(dev)) 995 return PTR_ERR(dev); 996 997 assert (dev != NULL); 998 tp = netdev_priv(dev); 999 tp->dev = dev; 1000 1001 ioaddr = tp->mmio_addr; 1002 assert (ioaddr != NULL); 1003 1004 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6; 1005 for (i = 0; i < 3; i++) 1006 ((__le16 *) (dev->dev_addr))[i] = 1007 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len)); 1008 1009 /* The Rtl8139-specific entries in the device structure. */ 1010 dev->netdev_ops = &rtl8139_netdev_ops; 1011 dev->ethtool_ops = &rtl8139_ethtool_ops; 1012 dev->watchdog_timeo = TX_TIMEOUT; 1013 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64); 1014 1015 /* note: the hardware is not capable of sg/csum/highdma, however 1016 * through the use of skb_copy_and_csum_dev we enable these 1017 * features 1018 */ 1019 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA; 1020 dev->vlan_features = dev->features; 1021 1022 dev->hw_features |= NETIF_F_RXALL; 1023 dev->hw_features |= NETIF_F_RXFCS; 1024 1025 /* tp zeroed and aligned in alloc_etherdev */ 1026 tp = netdev_priv(dev); 1027 1028 /* note: tp->chipset set in rtl8139_init_board */ 1029 tp->drv_flags = board_info[ent->driver_data].hw_flags; 1030 tp->mmio_addr = ioaddr; 1031 tp->msg_enable = 1032 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1)); 1033 spin_lock_init (&tp->lock); 1034 spin_lock_init (&tp->rx_lock); 1035 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1036 tp->mii.dev = dev; 1037 tp->mii.mdio_read = mdio_read; 1038 tp->mii.mdio_write = mdio_write; 1039 tp->mii.phy_id_mask = 0x3f; 1040 tp->mii.reg_num_mask = 0x1f; 1041 1042 /* dev is fully set up and ready to use now */ 1043 pr_debug("about to register device named %s (%p)...\n", 1044 dev->name, dev); 1045 i = register_netdev (dev); 1046 if (i) goto err_out; 1047 1048 pci_set_drvdata (pdev, dev); 1049 1050 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n", 1051 board_info[ent->driver_data].name, 1052 ioaddr, dev->dev_addr, pdev->irq); 1053 1054 netdev_dbg(dev, "Identified 8139 chip type '%s'\n", 1055 rtl_chip_info[tp->chipset].name); 1056 1057 /* Find the connected MII xcvrs. 1058 Doing this in open() would allow detecting external xcvrs later, but 1059 takes too much time. */ 1060 #ifdef CONFIG_8139TOO_8129 1061 if (tp->drv_flags & HAS_MII_XCVR) { 1062 int phy, phy_idx = 0; 1063 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) { 1064 int mii_status = mdio_read(dev, phy, 1); 1065 if (mii_status != 0xffff && mii_status != 0x0000) { 1066 u16 advertising = mdio_read(dev, phy, 4); 1067 tp->phys[phy_idx++] = phy; 1068 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n", 1069 phy, mii_status, advertising); 1070 } 1071 } 1072 if (phy_idx == 0) { 1073 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n"); 1074 tp->phys[0] = 32; 1075 } 1076 } else 1077 #endif 1078 tp->phys[0] = 32; 1079 tp->mii.phy_id = tp->phys[0]; 1080 1081 /* The lower four bits are the media type. */ 1082 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 1083 if (option > 0) { 1084 tp->mii.full_duplex = (option & 0x210) ? 1 : 0; 1085 tp->default_port = option & 0xFF; 1086 if (tp->default_port) 1087 tp->mii.force_media = 1; 1088 } 1089 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0) 1090 tp->mii.full_duplex = full_duplex[board_idx]; 1091 if (tp->mii.full_duplex) { 1092 netdev_info(dev, "Media type forced to Full Duplex\n"); 1093 /* Changing the MII-advertised media because might prevent 1094 re-connection. */ 1095 tp->mii.force_media = 1; 1096 } 1097 if (tp->default_port) { 1098 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n", 1099 (option & 0x20 ? 100 : 10), 1100 (option & 0x10 ? "full" : "half")); 1101 mdio_write(dev, tp->phys[0], 0, 1102 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */ 1103 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */ 1104 } 1105 1106 /* Put the chip into low-power mode. */ 1107 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1108 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 1109 1110 return 0; 1111 1112 err_out: 1113 netif_napi_del(&tp->napi); 1114 __rtl8139_cleanup_dev (dev); 1115 pci_disable_device (pdev); 1116 return i; 1117 } 1118 1119 1120 static void rtl8139_remove_one(struct pci_dev *pdev) 1121 { 1122 struct net_device *dev = pci_get_drvdata (pdev); 1123 struct rtl8139_private *tp = netdev_priv(dev); 1124 1125 assert (dev != NULL); 1126 1127 cancel_delayed_work_sync(&tp->thread); 1128 netif_napi_del(&tp->napi); 1129 1130 unregister_netdev (dev); 1131 1132 __rtl8139_cleanup_dev (dev); 1133 pci_disable_device (pdev); 1134 } 1135 1136 1137 /* Serial EEPROM section. */ 1138 1139 /* EEPROM_Ctrl bits. */ 1140 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 1141 #define EE_CS 0x08 /* EEPROM chip select. */ 1142 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 1143 #define EE_WRITE_0 0x00 1144 #define EE_WRITE_1 0x02 1145 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 1146 #define EE_ENB (0x80 | EE_CS) 1147 1148 /* Delay between EEPROM clock transitions. 1149 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 1150 */ 1151 1152 #define eeprom_delay() (void)RTL_R8(Cfg9346) 1153 1154 /* The EEPROM commands include the alway-set leading bit. */ 1155 #define EE_WRITE_CMD (5) 1156 #define EE_READ_CMD (6) 1157 #define EE_ERASE_CMD (7) 1158 1159 static int read_eeprom(void __iomem *ioaddr, int location, int addr_len) 1160 { 1161 int i; 1162 unsigned retval = 0; 1163 int read_cmd = location | (EE_READ_CMD << addr_len); 1164 1165 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS); 1166 RTL_W8 (Cfg9346, EE_ENB); 1167 eeprom_delay (); 1168 1169 /* Shift the read command bits out. */ 1170 for (i = 4 + addr_len; i >= 0; i--) { 1171 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 1172 RTL_W8 (Cfg9346, EE_ENB | dataval); 1173 eeprom_delay (); 1174 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK); 1175 eeprom_delay (); 1176 } 1177 RTL_W8 (Cfg9346, EE_ENB); 1178 eeprom_delay (); 1179 1180 for (i = 16; i > 0; i--) { 1181 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK); 1182 eeprom_delay (); 1183 retval = 1184 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 : 1185 0); 1186 RTL_W8 (Cfg9346, EE_ENB); 1187 eeprom_delay (); 1188 } 1189 1190 /* Terminate the EEPROM access. */ 1191 RTL_W8(Cfg9346, 0); 1192 eeprom_delay (); 1193 1194 return retval; 1195 } 1196 1197 /* MII serial management: mostly bogus for now. */ 1198 /* Read and write the MII management registers using software-generated 1199 serial MDIO protocol. 1200 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 1201 met by back-to-back PCI I/O cycles, but we insert a delay to avoid 1202 "overclocking" issues. */ 1203 #define MDIO_DIR 0x80 1204 #define MDIO_DATA_OUT 0x04 1205 #define MDIO_DATA_IN 0x02 1206 #define MDIO_CLK 0x01 1207 #define MDIO_WRITE0 (MDIO_DIR) 1208 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT) 1209 1210 #define mdio_delay() RTL_R8(Config4) 1211 1212 1213 static const char mii_2_8139_map[8] = { 1214 BasicModeCtrl, 1215 BasicModeStatus, 1216 0, 1217 0, 1218 NWayAdvert, 1219 NWayLPAR, 1220 NWayExpansion, 1221 0 1222 }; 1223 1224 1225 #ifdef CONFIG_8139TOO_8129 1226 /* Syncronize the MII management interface by shifting 32 one bits out. */ 1227 static void mdio_sync (void __iomem *ioaddr) 1228 { 1229 int i; 1230 1231 for (i = 32; i >= 0; i--) { 1232 RTL_W8 (Config4, MDIO_WRITE1); 1233 mdio_delay (); 1234 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK); 1235 mdio_delay (); 1236 } 1237 } 1238 #endif 1239 1240 static int mdio_read (struct net_device *dev, int phy_id, int location) 1241 { 1242 struct rtl8139_private *tp = netdev_priv(dev); 1243 int retval = 0; 1244 #ifdef CONFIG_8139TOO_8129 1245 void __iomem *ioaddr = tp->mmio_addr; 1246 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; 1247 int i; 1248 #endif 1249 1250 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1251 void __iomem *ioaddr = tp->mmio_addr; 1252 return location < 8 && mii_2_8139_map[location] ? 1253 RTL_R16 (mii_2_8139_map[location]) : 0; 1254 } 1255 1256 #ifdef CONFIG_8139TOO_8129 1257 mdio_sync (ioaddr); 1258 /* Shift the read command bits out. */ 1259 for (i = 15; i >= 0; i--) { 1260 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0; 1261 1262 RTL_W8 (Config4, MDIO_DIR | dataval); 1263 mdio_delay (); 1264 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK); 1265 mdio_delay (); 1266 } 1267 1268 /* Read the two transition, 16 data, and wire-idle bits. */ 1269 for (i = 19; i > 0; i--) { 1270 RTL_W8 (Config4, 0); 1271 mdio_delay (); 1272 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0); 1273 RTL_W8 (Config4, MDIO_CLK); 1274 mdio_delay (); 1275 } 1276 #endif 1277 1278 return (retval >> 1) & 0xffff; 1279 } 1280 1281 1282 static void mdio_write (struct net_device *dev, int phy_id, int location, 1283 int value) 1284 { 1285 struct rtl8139_private *tp = netdev_priv(dev); 1286 #ifdef CONFIG_8139TOO_8129 1287 void __iomem *ioaddr = tp->mmio_addr; 1288 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; 1289 int i; 1290 #endif 1291 1292 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1293 void __iomem *ioaddr = tp->mmio_addr; 1294 if (location == 0) { 1295 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1296 RTL_W16 (BasicModeCtrl, value); 1297 RTL_W8 (Cfg9346, Cfg9346_Lock); 1298 } else if (location < 8 && mii_2_8139_map[location]) 1299 RTL_W16 (mii_2_8139_map[location], value); 1300 return; 1301 } 1302 1303 #ifdef CONFIG_8139TOO_8129 1304 mdio_sync (ioaddr); 1305 1306 /* Shift the command bits out. */ 1307 for (i = 31; i >= 0; i--) { 1308 int dataval = 1309 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 1310 RTL_W8 (Config4, dataval); 1311 mdio_delay (); 1312 RTL_W8 (Config4, dataval | MDIO_CLK); 1313 mdio_delay (); 1314 } 1315 /* Clear out extra bits. */ 1316 for (i = 2; i > 0; i--) { 1317 RTL_W8 (Config4, 0); 1318 mdio_delay (); 1319 RTL_W8 (Config4, MDIO_CLK); 1320 mdio_delay (); 1321 } 1322 #endif 1323 } 1324 1325 1326 static int rtl8139_open (struct net_device *dev) 1327 { 1328 struct rtl8139_private *tp = netdev_priv(dev); 1329 void __iomem *ioaddr = tp->mmio_addr; 1330 const int irq = tp->pci_dev->irq; 1331 int retval; 1332 1333 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev); 1334 if (retval) 1335 return retval; 1336 1337 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1338 &tp->tx_bufs_dma, GFP_KERNEL); 1339 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1340 &tp->rx_ring_dma, GFP_KERNEL); 1341 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) { 1342 free_irq(irq, dev); 1343 1344 if (tp->tx_bufs) 1345 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1346 tp->tx_bufs, tp->tx_bufs_dma); 1347 if (tp->rx_ring) 1348 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1349 tp->rx_ring, tp->rx_ring_dma); 1350 1351 return -ENOMEM; 1352 1353 } 1354 1355 napi_enable(&tp->napi); 1356 1357 tp->mii.full_duplex = tp->mii.force_media; 1358 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000; 1359 1360 rtl8139_init_ring (dev); 1361 rtl8139_hw_start (dev); 1362 netif_start_queue (dev); 1363 1364 netif_dbg(tp, ifup, dev, 1365 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n", 1366 __func__, 1367 (unsigned long long)pci_resource_start (tp->pci_dev, 1), 1368 irq, RTL_R8 (MediaStatus), 1369 tp->mii.full_duplex ? "full" : "half"); 1370 1371 rtl8139_start_thread(tp); 1372 1373 return 0; 1374 } 1375 1376 1377 static void rtl_check_media (struct net_device *dev, unsigned int init_media) 1378 { 1379 struct rtl8139_private *tp = netdev_priv(dev); 1380 1381 if (tp->phys[0] >= 0) { 1382 mii_check_media(&tp->mii, netif_msg_link(tp), init_media); 1383 } 1384 } 1385 1386 /* Start the hardware at open or resume. */ 1387 static void rtl8139_hw_start (struct net_device *dev) 1388 { 1389 struct rtl8139_private *tp = netdev_priv(dev); 1390 void __iomem *ioaddr = tp->mmio_addr; 1391 u32 i; 1392 u8 tmp; 1393 1394 /* Bring old chips out of low-power mode. */ 1395 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1396 RTL_W8 (HltClk, 'R'); 1397 1398 rtl8139_chip_reset (ioaddr); 1399 1400 /* unlock Config[01234] and BMCR register writes */ 1401 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1402 /* Restore our idea of the MAC address. */ 1403 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); 1404 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4))); 1405 1406 tp->cur_rx = 0; 1407 1408 /* init Rx ring buffer DMA address */ 1409 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1410 1411 /* Must enable Tx/Rx before setting transfer thresholds! */ 1412 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1413 1414 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1415 RTL_W32 (RxConfig, tp->rx_config); 1416 RTL_W32 (TxConfig, rtl8139_tx_config); 1417 1418 rtl_check_media (dev, 1); 1419 1420 if (tp->chipset >= CH_8139B) { 1421 /* Disable magic packet scanning, which is enabled 1422 * when PM is enabled in Config1. It can be reenabled 1423 * via ETHTOOL_SWOL if desired. */ 1424 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic); 1425 } 1426 1427 netdev_dbg(dev, "init buffer addresses\n"); 1428 1429 /* Lock Config[01234] and BMCR register writes */ 1430 RTL_W8 (Cfg9346, Cfg9346_Lock); 1431 1432 /* init Tx buffer DMA addresses */ 1433 for (i = 0; i < NUM_TX_DESC; i++) 1434 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs)); 1435 1436 RTL_W32 (RxMissed, 0); 1437 1438 rtl8139_set_rx_mode (dev); 1439 1440 /* no early-rx interrupts */ 1441 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear); 1442 1443 /* make sure RxTx has started */ 1444 tmp = RTL_R8 (ChipCmd); 1445 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb))) 1446 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1447 1448 /* Enable all known interrupts by setting the interrupt mask. */ 1449 RTL_W16 (IntrMask, rtl8139_intr_mask); 1450 } 1451 1452 1453 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1454 static void rtl8139_init_ring (struct net_device *dev) 1455 { 1456 struct rtl8139_private *tp = netdev_priv(dev); 1457 int i; 1458 1459 tp->cur_rx = 0; 1460 tp->cur_tx = 0; 1461 tp->dirty_tx = 0; 1462 1463 for (i = 0; i < NUM_TX_DESC; i++) 1464 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE]; 1465 } 1466 1467 1468 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */ 1469 static int next_tick = 3 * HZ; 1470 1471 #ifndef CONFIG_8139TOO_TUNE_TWISTER 1472 static inline void rtl8139_tune_twister (struct net_device *dev, 1473 struct rtl8139_private *tp) {} 1474 #else 1475 enum TwisterParamVals { 1476 PARA78_default = 0x78fa8388, 1477 PARA7c_default = 0xcb38de43, /* param[0][3] */ 1478 PARA7c_xxx = 0xcb38de43, 1479 }; 1480 1481 static const unsigned long param[4][4] = { 1482 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1483 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1484 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1485 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1486 }; 1487 1488 static void rtl8139_tune_twister (struct net_device *dev, 1489 struct rtl8139_private *tp) 1490 { 1491 int linkcase; 1492 void __iomem *ioaddr = tp->mmio_addr; 1493 1494 /* This is a complicated state machine to configure the "twister" for 1495 impedance/echos based on the cable length. 1496 All of this is magic and undocumented. 1497 */ 1498 switch (tp->twistie) { 1499 case 1: 1500 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) { 1501 /* We have link beat, let us tune the twister. */ 1502 RTL_W16 (CSCR, CSCR_LinkDownOffCmd); 1503 tp->twistie = 2; /* Change to state 2. */ 1504 next_tick = HZ / 10; 1505 } else { 1506 /* Just put in some reasonable defaults for when beat returns. */ 1507 RTL_W16 (CSCR, CSCR_LinkDownCmd); 1508 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */ 1509 RTL_W32 (PARA78, PARA78_default); 1510 RTL_W32 (PARA7c, PARA7c_default); 1511 tp->twistie = 0; /* Bail from future actions. */ 1512 } 1513 break; 1514 case 2: 1515 /* Read how long it took to hear the echo. */ 1516 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits; 1517 if (linkcase == 0x7000) 1518 tp->twist_row = 3; 1519 else if (linkcase == 0x3000) 1520 tp->twist_row = 2; 1521 else if (linkcase == 0x1000) 1522 tp->twist_row = 1; 1523 else 1524 tp->twist_row = 0; 1525 tp->twist_col = 0; 1526 tp->twistie = 3; /* Change to state 2. */ 1527 next_tick = HZ / 10; 1528 break; 1529 case 3: 1530 /* Put out four tuning parameters, one per 100msec. */ 1531 if (tp->twist_col == 0) 1532 RTL_W16 (FIFOTMS, 0); 1533 RTL_W32 (PARA7c, param[(int) tp->twist_row] 1534 [(int) tp->twist_col]); 1535 next_tick = HZ / 10; 1536 if (++tp->twist_col >= 4) { 1537 /* For short cables we are done. 1538 For long cables (row == 3) check for mistune. */ 1539 tp->twistie = 1540 (tp->twist_row == 3) ? 4 : 0; 1541 } 1542 break; 1543 case 4: 1544 /* Special case for long cables: check for mistune. */ 1545 if ((RTL_R16 (CSCR) & 1546 CSCR_LinkStatusBits) == 0x7000) { 1547 tp->twistie = 0; 1548 break; 1549 } else { 1550 RTL_W32 (PARA7c, 0xfb38de03); 1551 tp->twistie = 5; 1552 next_tick = HZ / 10; 1553 } 1554 break; 1555 case 5: 1556 /* Retune for shorter cable (column 2). */ 1557 RTL_W32 (FIFOTMS, 0x20); 1558 RTL_W32 (PARA78, PARA78_default); 1559 RTL_W32 (PARA7c, PARA7c_default); 1560 RTL_W32 (FIFOTMS, 0x00); 1561 tp->twist_row = 2; 1562 tp->twist_col = 0; 1563 tp->twistie = 3; 1564 next_tick = HZ / 10; 1565 break; 1566 1567 default: 1568 /* do nothing */ 1569 break; 1570 } 1571 } 1572 #endif /* CONFIG_8139TOO_TUNE_TWISTER */ 1573 1574 static inline void rtl8139_thread_iter (struct net_device *dev, 1575 struct rtl8139_private *tp, 1576 void __iomem *ioaddr) 1577 { 1578 int mii_lpa; 1579 1580 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA); 1581 1582 if (!tp->mii.force_media && mii_lpa != 0xffff) { 1583 int duplex = ((mii_lpa & LPA_100FULL) || 1584 (mii_lpa & 0x01C0) == 0x0040); 1585 if (tp->mii.full_duplex != duplex) { 1586 tp->mii.full_duplex = duplex; 1587 1588 if (mii_lpa) { 1589 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n", 1590 tp->mii.full_duplex ? "full" : "half", 1591 tp->phys[0], mii_lpa); 1592 } else { 1593 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n"); 1594 } 1595 #if 0 1596 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1597 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20); 1598 RTL_W8 (Cfg9346, Cfg9346_Lock); 1599 #endif 1600 } 1601 } 1602 1603 next_tick = HZ * 60; 1604 1605 rtl8139_tune_twister (dev, tp); 1606 1607 netdev_dbg(dev, "Media selection tick, Link partner %04x\n", 1608 RTL_R16(NWayLPAR)); 1609 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n", 1610 RTL_R16(IntrMask), RTL_R16(IntrStatus)); 1611 netdev_dbg(dev, "Chip config %02x %02x\n", 1612 RTL_R8(Config0), RTL_R8(Config1)); 1613 } 1614 1615 static void rtl8139_thread (struct work_struct *work) 1616 { 1617 struct rtl8139_private *tp = 1618 container_of(work, struct rtl8139_private, thread.work); 1619 struct net_device *dev = tp->mii.dev; 1620 unsigned long thr_delay = next_tick; 1621 1622 rtnl_lock(); 1623 1624 if (!netif_running(dev)) 1625 goto out_unlock; 1626 1627 if (tp->watchdog_fired) { 1628 tp->watchdog_fired = 0; 1629 rtl8139_tx_timeout_task(work); 1630 } else 1631 rtl8139_thread_iter(dev, tp, tp->mmio_addr); 1632 1633 if (tp->have_thread) 1634 schedule_delayed_work(&tp->thread, thr_delay); 1635 out_unlock: 1636 rtnl_unlock (); 1637 } 1638 1639 static void rtl8139_start_thread(struct rtl8139_private *tp) 1640 { 1641 tp->twistie = 0; 1642 if (tp->chipset == CH_8139_K) 1643 tp->twistie = 1; 1644 else if (tp->drv_flags & HAS_LNK_CHNG) 1645 return; 1646 1647 tp->have_thread = 1; 1648 tp->watchdog_fired = 0; 1649 1650 schedule_delayed_work(&tp->thread, next_tick); 1651 } 1652 1653 static inline void rtl8139_tx_clear (struct rtl8139_private *tp) 1654 { 1655 tp->cur_tx = 0; 1656 tp->dirty_tx = 0; 1657 1658 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */ 1659 } 1660 1661 static void rtl8139_tx_timeout_task (struct work_struct *work) 1662 { 1663 struct rtl8139_private *tp = 1664 container_of(work, struct rtl8139_private, thread.work); 1665 struct net_device *dev = tp->mii.dev; 1666 void __iomem *ioaddr = tp->mmio_addr; 1667 int i; 1668 u8 tmp8; 1669 1670 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n", 1671 RTL_R8(ChipCmd), RTL_R16(IntrStatus), 1672 RTL_R16(IntrMask), RTL_R8(MediaStatus)); 1673 /* Emit info to figure out what went wrong. */ 1674 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n", 1675 tp->cur_tx, tp->dirty_tx); 1676 for (i = 0; i < NUM_TX_DESC; i++) 1677 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n", 1678 i, RTL_R32(TxStatus0 + (i * 4)), 1679 i == tp->dirty_tx % NUM_TX_DESC ? 1680 " (queue head)" : ""); 1681 1682 tp->xstats.tx_timeouts++; 1683 1684 /* disable Tx ASAP, if not already */ 1685 tmp8 = RTL_R8 (ChipCmd); 1686 if (tmp8 & CmdTxEnb) 1687 RTL_W8 (ChipCmd, CmdRxEnb); 1688 1689 spin_lock_bh(&tp->rx_lock); 1690 /* Disable interrupts by clearing the interrupt mask. */ 1691 RTL_W16 (IntrMask, 0x0000); 1692 1693 /* Stop a shared interrupt from scavenging while we are. */ 1694 spin_lock_irq(&tp->lock); 1695 rtl8139_tx_clear (tp); 1696 spin_unlock_irq(&tp->lock); 1697 1698 /* ...and finally, reset everything */ 1699 if (netif_running(dev)) { 1700 rtl8139_hw_start (dev); 1701 netif_wake_queue (dev); 1702 } 1703 spin_unlock_bh(&tp->rx_lock); 1704 } 1705 1706 static void rtl8139_tx_timeout (struct net_device *dev) 1707 { 1708 struct rtl8139_private *tp = netdev_priv(dev); 1709 1710 tp->watchdog_fired = 1; 1711 if (!tp->have_thread) { 1712 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1713 schedule_delayed_work(&tp->thread, next_tick); 1714 } 1715 } 1716 1717 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 1718 struct net_device *dev) 1719 { 1720 struct rtl8139_private *tp = netdev_priv(dev); 1721 void __iomem *ioaddr = tp->mmio_addr; 1722 unsigned int entry; 1723 unsigned int len = skb->len; 1724 unsigned long flags; 1725 1726 /* Calculate the next Tx descriptor entry. */ 1727 entry = tp->cur_tx % NUM_TX_DESC; 1728 1729 /* Note: the chip doesn't have auto-pad! */ 1730 if (likely(len < TX_BUF_SIZE)) { 1731 if (len < ETH_ZLEN) 1732 memset(tp->tx_buf[entry], 0, ETH_ZLEN); 1733 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]); 1734 dev_kfree_skb_any(skb); 1735 } else { 1736 dev_kfree_skb_any(skb); 1737 dev->stats.tx_dropped++; 1738 return NETDEV_TX_OK; 1739 } 1740 1741 spin_lock_irqsave(&tp->lock, flags); 1742 /* 1743 * Writing to TxStatus triggers a DMA transfer of the data 1744 * copied to tp->tx_buf[entry] above. Use a memory barrier 1745 * to make sure that the device sees the updated data. 1746 */ 1747 wmb(); 1748 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)), 1749 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN)); 1750 1751 tp->cur_tx++; 1752 1753 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) 1754 netif_stop_queue (dev); 1755 spin_unlock_irqrestore(&tp->lock, flags); 1756 1757 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n", 1758 len, entry); 1759 1760 return NETDEV_TX_OK; 1761 } 1762 1763 1764 static void rtl8139_tx_interrupt (struct net_device *dev, 1765 struct rtl8139_private *tp, 1766 void __iomem *ioaddr) 1767 { 1768 unsigned long dirty_tx, tx_left; 1769 1770 assert (dev != NULL); 1771 assert (ioaddr != NULL); 1772 1773 dirty_tx = tp->dirty_tx; 1774 tx_left = tp->cur_tx - dirty_tx; 1775 while (tx_left > 0) { 1776 int entry = dirty_tx % NUM_TX_DESC; 1777 int txstatus; 1778 1779 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); 1780 1781 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted))) 1782 break; /* It still hasn't been Txed */ 1783 1784 /* Note: TxCarrierLost is always asserted at 100mbps. */ 1785 if (txstatus & (TxOutOfWindow | TxAborted)) { 1786 /* There was an major error, log it. */ 1787 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n", 1788 txstatus); 1789 dev->stats.tx_errors++; 1790 if (txstatus & TxAborted) { 1791 dev->stats.tx_aborted_errors++; 1792 RTL_W32 (TxConfig, TxClearAbt); 1793 RTL_W16 (IntrStatus, TxErr); 1794 wmb(); 1795 } 1796 if (txstatus & TxCarrierLost) 1797 dev->stats.tx_carrier_errors++; 1798 if (txstatus & TxOutOfWindow) 1799 dev->stats.tx_window_errors++; 1800 } else { 1801 if (txstatus & TxUnderrun) { 1802 /* Add 64 to the Tx FIFO threshold. */ 1803 if (tp->tx_flag < 0x00300000) 1804 tp->tx_flag += 0x00020000; 1805 dev->stats.tx_fifo_errors++; 1806 } 1807 dev->stats.collisions += (txstatus >> 24) & 15; 1808 u64_stats_update_begin(&tp->tx_stats.syncp); 1809 tp->tx_stats.packets++; 1810 tp->tx_stats.bytes += txstatus & 0x7ff; 1811 u64_stats_update_end(&tp->tx_stats.syncp); 1812 } 1813 1814 dirty_tx++; 1815 tx_left--; 1816 } 1817 1818 #ifndef RTL8139_NDEBUG 1819 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) { 1820 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n", 1821 dirty_tx, tp->cur_tx); 1822 dirty_tx += NUM_TX_DESC; 1823 } 1824 #endif /* RTL8139_NDEBUG */ 1825 1826 /* only wake the queue if we did work, and the queue is stopped */ 1827 if (tp->dirty_tx != dirty_tx) { 1828 tp->dirty_tx = dirty_tx; 1829 mb(); 1830 netif_wake_queue (dev); 1831 } 1832 } 1833 1834 1835 /* TODO: clean this up! Rx reset need not be this intensive */ 1836 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev, 1837 struct rtl8139_private *tp, void __iomem *ioaddr) 1838 { 1839 u8 tmp8; 1840 #ifdef CONFIG_8139_OLD_RX_RESET 1841 int tmp_work; 1842 #endif 1843 1844 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n", 1845 rx_status); 1846 dev->stats.rx_errors++; 1847 if (!(rx_status & RxStatusOK)) { 1848 if (rx_status & RxTooLong) { 1849 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n", 1850 rx_status); 1851 /* A.C.: The chip hangs here. */ 1852 } 1853 if (rx_status & (RxBadSymbol | RxBadAlign)) 1854 dev->stats.rx_frame_errors++; 1855 if (rx_status & (RxRunt | RxTooLong)) 1856 dev->stats.rx_length_errors++; 1857 if (rx_status & RxCRCErr) 1858 dev->stats.rx_crc_errors++; 1859 } else { 1860 tp->xstats.rx_lost_in_ring++; 1861 } 1862 1863 #ifndef CONFIG_8139_OLD_RX_RESET 1864 tmp8 = RTL_R8 (ChipCmd); 1865 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb); 1866 RTL_W8 (ChipCmd, tmp8); 1867 RTL_W32 (RxConfig, tp->rx_config); 1868 tp->cur_rx = 0; 1869 #else 1870 /* Reset the receiver, based on RealTek recommendation. (Bug?) */ 1871 1872 /* disable receive */ 1873 RTL_W8_F (ChipCmd, CmdTxEnb); 1874 tmp_work = 200; 1875 while (--tmp_work > 0) { 1876 udelay(1); 1877 tmp8 = RTL_R8 (ChipCmd); 1878 if (!(tmp8 & CmdRxEnb)) 1879 break; 1880 } 1881 if (tmp_work <= 0) 1882 netdev_warn(dev, "rx stop wait too long\n"); 1883 /* restart receive */ 1884 tmp_work = 200; 1885 while (--tmp_work > 0) { 1886 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb); 1887 udelay(1); 1888 tmp8 = RTL_R8 (ChipCmd); 1889 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb)) 1890 break; 1891 } 1892 if (tmp_work <= 0) 1893 netdev_warn(dev, "tx/rx enable wait too long\n"); 1894 1895 /* and reinitialize all rx related registers */ 1896 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1897 /* Must enable Tx/Rx before setting transfer thresholds! */ 1898 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1899 1900 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1901 RTL_W32 (RxConfig, tp->rx_config); 1902 tp->cur_rx = 0; 1903 1904 netdev_dbg(dev, "init buffer addresses\n"); 1905 1906 /* Lock Config[01234] and BMCR register writes */ 1907 RTL_W8 (Cfg9346, Cfg9346_Lock); 1908 1909 /* init Rx ring buffer DMA address */ 1910 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1911 1912 /* A.C.: Reset the multicast list. */ 1913 __set_rx_mode (dev); 1914 #endif 1915 } 1916 1917 #if RX_BUF_IDX == 3 1918 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring, 1919 u32 offset, unsigned int size) 1920 { 1921 u32 left = RX_BUF_LEN - offset; 1922 1923 if (size > left) { 1924 skb_copy_to_linear_data(skb, ring + offset, left); 1925 skb_copy_to_linear_data_offset(skb, left, ring, size - left); 1926 } else 1927 skb_copy_to_linear_data(skb, ring + offset, size); 1928 } 1929 #endif 1930 1931 static void rtl8139_isr_ack(struct rtl8139_private *tp) 1932 { 1933 void __iomem *ioaddr = tp->mmio_addr; 1934 u16 status; 1935 1936 status = RTL_R16 (IntrStatus) & RxAckBits; 1937 1938 /* Clear out errors and receive interrupts */ 1939 if (likely(status != 0)) { 1940 if (unlikely(status & (RxFIFOOver | RxOverflow))) { 1941 tp->dev->stats.rx_errors++; 1942 if (status & RxFIFOOver) 1943 tp->dev->stats.rx_fifo_errors++; 1944 } 1945 RTL_W16_F (IntrStatus, RxAckBits); 1946 } 1947 } 1948 1949 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp, 1950 int budget) 1951 { 1952 void __iomem *ioaddr = tp->mmio_addr; 1953 int received = 0; 1954 unsigned char *rx_ring = tp->rx_ring; 1955 unsigned int cur_rx = tp->cur_rx; 1956 unsigned int rx_size = 0; 1957 1958 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 1959 __func__, (u16)cur_rx, 1960 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 1961 1962 while (netif_running(dev) && received < budget && 1963 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { 1964 u32 ring_offset = cur_rx % RX_BUF_LEN; 1965 u32 rx_status; 1966 unsigned int pkt_size; 1967 struct sk_buff *skb; 1968 1969 rmb(); 1970 1971 /* read size+status of next frame from DMA ring buffer */ 1972 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset)); 1973 rx_size = rx_status >> 16; 1974 if (likely(!(dev->features & NETIF_F_RXFCS))) 1975 pkt_size = rx_size - 4; 1976 else 1977 pkt_size = rx_size; 1978 1979 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n", 1980 __func__, rx_status, rx_size, cur_rx); 1981 #if RTL8139_DEBUG > 2 1982 print_hex_dump(KERN_DEBUG, "Frame contents: ", 1983 DUMP_PREFIX_OFFSET, 16, 1, 1984 &rx_ring[ring_offset], 70, true); 1985 #endif 1986 1987 /* Packet copy from FIFO still in progress. 1988 * Theoretically, this should never happen 1989 * since EarlyRx is disabled. 1990 */ 1991 if (unlikely(rx_size == 0xfff0)) { 1992 if (!tp->fifo_copy_timeout) 1993 tp->fifo_copy_timeout = jiffies + 2; 1994 else if (time_after(jiffies, tp->fifo_copy_timeout)) { 1995 netdev_dbg(dev, "hung FIFO. Reset\n"); 1996 rx_size = 0; 1997 goto no_early_rx; 1998 } 1999 netif_dbg(tp, intr, dev, "fifo copy in progress\n"); 2000 tp->xstats.early_rx++; 2001 break; 2002 } 2003 2004 no_early_rx: 2005 tp->fifo_copy_timeout = 0; 2006 2007 /* If Rx err or invalid rx_size/rx_status received 2008 * (which happens if we get lost in the ring), 2009 * Rx process gets reset, so we abort any further 2010 * Rx processing. 2011 */ 2012 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) || 2013 (rx_size < 8) || 2014 (!(rx_status & RxStatusOK)))) { 2015 if ((dev->features & NETIF_F_RXALL) && 2016 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) && 2017 (rx_size >= 8) && 2018 (!(rx_status & RxStatusOK))) { 2019 /* Length is at least mostly OK, but pkt has 2020 * error. I'm hoping we can handle some of these 2021 * errors without resetting the chip. --Ben 2022 */ 2023 dev->stats.rx_errors++; 2024 if (rx_status & RxCRCErr) { 2025 dev->stats.rx_crc_errors++; 2026 goto keep_pkt; 2027 } 2028 if (rx_status & RxRunt) { 2029 dev->stats.rx_length_errors++; 2030 goto keep_pkt; 2031 } 2032 } 2033 rtl8139_rx_err (rx_status, dev, tp, ioaddr); 2034 received = -1; 2035 goto out; 2036 } 2037 2038 keep_pkt: 2039 /* Malloc up new buffer, compatible with net-2e. */ 2040 /* Omit the four octet CRC from the length. */ 2041 2042 skb = napi_alloc_skb(&tp->napi, pkt_size); 2043 if (likely(skb)) { 2044 #if RX_BUF_IDX == 3 2045 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size); 2046 #else 2047 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size); 2048 #endif 2049 skb_put (skb, pkt_size); 2050 2051 skb->protocol = eth_type_trans (skb, dev); 2052 2053 u64_stats_update_begin(&tp->rx_stats.syncp); 2054 tp->rx_stats.packets++; 2055 tp->rx_stats.bytes += pkt_size; 2056 u64_stats_update_end(&tp->rx_stats.syncp); 2057 2058 netif_receive_skb (skb); 2059 } else { 2060 dev->stats.rx_dropped++; 2061 } 2062 received++; 2063 2064 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 2065 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16)); 2066 2067 rtl8139_isr_ack(tp); 2068 } 2069 2070 if (unlikely(!received || rx_size == 0xfff0)) 2071 rtl8139_isr_ack(tp); 2072 2073 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 2074 __func__, cur_rx, 2075 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 2076 2077 tp->cur_rx = cur_rx; 2078 2079 /* 2080 * The receive buffer should be mostly empty. 2081 * Tell NAPI to reenable the Rx irq. 2082 */ 2083 if (tp->fifo_copy_timeout) 2084 received = budget; 2085 2086 out: 2087 return received; 2088 } 2089 2090 2091 static void rtl8139_weird_interrupt (struct net_device *dev, 2092 struct rtl8139_private *tp, 2093 void __iomem *ioaddr, 2094 int status, int link_changed) 2095 { 2096 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status); 2097 2098 assert (dev != NULL); 2099 assert (tp != NULL); 2100 assert (ioaddr != NULL); 2101 2102 /* Update the error count. */ 2103 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2104 RTL_W32 (RxMissed, 0); 2105 2106 if ((status & RxUnderrun) && link_changed && 2107 (tp->drv_flags & HAS_LNK_CHNG)) { 2108 rtl_check_media(dev, 0); 2109 status &= ~RxUnderrun; 2110 } 2111 2112 if (status & (RxUnderrun | RxErr)) 2113 dev->stats.rx_errors++; 2114 2115 if (status & PCSTimeout) 2116 dev->stats.rx_length_errors++; 2117 if (status & RxUnderrun) 2118 dev->stats.rx_fifo_errors++; 2119 if (status & PCIErr) { 2120 u16 pci_cmd_status; 2121 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status); 2122 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status); 2123 2124 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status); 2125 } 2126 } 2127 2128 static int rtl8139_poll(struct napi_struct *napi, int budget) 2129 { 2130 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi); 2131 struct net_device *dev = tp->dev; 2132 void __iomem *ioaddr = tp->mmio_addr; 2133 int work_done; 2134 2135 spin_lock(&tp->rx_lock); 2136 work_done = 0; 2137 if (likely(RTL_R16(IntrStatus) & RxAckBits)) 2138 work_done += rtl8139_rx(dev, tp, budget); 2139 2140 if (work_done < budget) { 2141 unsigned long flags; 2142 /* 2143 * Order is important since data can get interrupted 2144 * again when we think we are done. 2145 */ 2146 spin_lock_irqsave(&tp->lock, flags); 2147 __napi_complete(napi); 2148 RTL_W16_F(IntrMask, rtl8139_intr_mask); 2149 spin_unlock_irqrestore(&tp->lock, flags); 2150 } 2151 spin_unlock(&tp->rx_lock); 2152 2153 return work_done; 2154 } 2155 2156 /* The interrupt handler does all of the Rx thread work and cleans up 2157 after the Tx thread. */ 2158 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance) 2159 { 2160 struct net_device *dev = (struct net_device *) dev_instance; 2161 struct rtl8139_private *tp = netdev_priv(dev); 2162 void __iomem *ioaddr = tp->mmio_addr; 2163 u16 status, ackstat; 2164 int link_changed = 0; /* avoid bogus "uninit" warning */ 2165 int handled = 0; 2166 2167 spin_lock (&tp->lock); 2168 status = RTL_R16 (IntrStatus); 2169 2170 /* shared irq? */ 2171 if (unlikely((status & rtl8139_intr_mask) == 0)) 2172 goto out; 2173 2174 handled = 1; 2175 2176 /* h/w no longer present (hotplug?) or major error, bail */ 2177 if (unlikely(status == 0xFFFF)) 2178 goto out; 2179 2180 /* close possible race's with dev_close */ 2181 if (unlikely(!netif_running(dev))) { 2182 RTL_W16 (IntrMask, 0); 2183 goto out; 2184 } 2185 2186 /* Acknowledge all of the current interrupt sources ASAP, but 2187 an first get an additional status bit from CSCR. */ 2188 if (unlikely(status & RxUnderrun)) 2189 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit; 2190 2191 ackstat = status & ~(RxAckBits | TxErr); 2192 if (ackstat) 2193 RTL_W16 (IntrStatus, ackstat); 2194 2195 /* Receive packets are processed by poll routine. 2196 If not running start it now. */ 2197 if (status & RxAckBits){ 2198 if (napi_schedule_prep(&tp->napi)) { 2199 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask); 2200 __napi_schedule(&tp->napi); 2201 } 2202 } 2203 2204 /* Check uncommon events with one test. */ 2205 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr))) 2206 rtl8139_weird_interrupt (dev, tp, ioaddr, 2207 status, link_changed); 2208 2209 if (status & (TxOK | TxErr)) { 2210 rtl8139_tx_interrupt (dev, tp, ioaddr); 2211 if (status & TxErr) 2212 RTL_W16 (IntrStatus, TxErr); 2213 } 2214 out: 2215 spin_unlock (&tp->lock); 2216 2217 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n", 2218 RTL_R16(IntrStatus)); 2219 return IRQ_RETVAL(handled); 2220 } 2221 2222 #ifdef CONFIG_NET_POLL_CONTROLLER 2223 /* 2224 * Polling receive - used by netconsole and other diagnostic tools 2225 * to allow network i/o with interrupts disabled. 2226 */ 2227 static void rtl8139_poll_controller(struct net_device *dev) 2228 { 2229 struct rtl8139_private *tp = netdev_priv(dev); 2230 const int irq = tp->pci_dev->irq; 2231 2232 disable_irq(irq); 2233 rtl8139_interrupt(irq, dev); 2234 enable_irq(irq); 2235 } 2236 #endif 2237 2238 static int rtl8139_set_mac_address(struct net_device *dev, void *p) 2239 { 2240 struct rtl8139_private *tp = netdev_priv(dev); 2241 void __iomem *ioaddr = tp->mmio_addr; 2242 struct sockaddr *addr = p; 2243 2244 if (!is_valid_ether_addr(addr->sa_data)) 2245 return -EADDRNOTAVAIL; 2246 2247 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2248 2249 spin_lock_irq(&tp->lock); 2250 2251 RTL_W8_F(Cfg9346, Cfg9346_Unlock); 2252 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0))); 2253 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4))); 2254 RTL_W8_F(Cfg9346, Cfg9346_Lock); 2255 2256 spin_unlock_irq(&tp->lock); 2257 2258 return 0; 2259 } 2260 2261 static int rtl8139_close (struct net_device *dev) 2262 { 2263 struct rtl8139_private *tp = netdev_priv(dev); 2264 void __iomem *ioaddr = tp->mmio_addr; 2265 unsigned long flags; 2266 2267 netif_stop_queue(dev); 2268 napi_disable(&tp->napi); 2269 2270 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n", 2271 RTL_R16(IntrStatus)); 2272 2273 spin_lock_irqsave (&tp->lock, flags); 2274 2275 /* Stop the chip's Tx and Rx DMA processes. */ 2276 RTL_W8 (ChipCmd, 0); 2277 2278 /* Disable interrupts by clearing the interrupt mask. */ 2279 RTL_W16 (IntrMask, 0); 2280 2281 /* Update the error counts. */ 2282 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2283 RTL_W32 (RxMissed, 0); 2284 2285 spin_unlock_irqrestore (&tp->lock, flags); 2286 2287 free_irq(tp->pci_dev->irq, dev); 2288 2289 rtl8139_tx_clear (tp); 2290 2291 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 2292 tp->rx_ring, tp->rx_ring_dma); 2293 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 2294 tp->tx_bufs, tp->tx_bufs_dma); 2295 tp->rx_ring = NULL; 2296 tp->tx_bufs = NULL; 2297 2298 /* Green! Put the chip in low-power mode. */ 2299 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2300 2301 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 2302 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 2303 2304 return 0; 2305 } 2306 2307 2308 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to 2309 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and 2310 other threads or interrupts aren't messing with the 8139. */ 2311 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2312 { 2313 struct rtl8139_private *tp = netdev_priv(dev); 2314 void __iomem *ioaddr = tp->mmio_addr; 2315 2316 spin_lock_irq(&tp->lock); 2317 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 2318 u8 cfg3 = RTL_R8 (Config3); 2319 u8 cfg5 = RTL_R8 (Config5); 2320 2321 wol->supported = WAKE_PHY | WAKE_MAGIC 2322 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; 2323 2324 wol->wolopts = 0; 2325 if (cfg3 & Cfg3_LinkUp) 2326 wol->wolopts |= WAKE_PHY; 2327 if (cfg3 & Cfg3_Magic) 2328 wol->wolopts |= WAKE_MAGIC; 2329 /* (KON)FIXME: See how netdev_set_wol() handles the 2330 following constants. */ 2331 if (cfg5 & Cfg5_UWF) 2332 wol->wolopts |= WAKE_UCAST; 2333 if (cfg5 & Cfg5_MWF) 2334 wol->wolopts |= WAKE_MCAST; 2335 if (cfg5 & Cfg5_BWF) 2336 wol->wolopts |= WAKE_BCAST; 2337 } 2338 spin_unlock_irq(&tp->lock); 2339 } 2340 2341 2342 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes 2343 that wol points to kernel memory and other threads or interrupts 2344 aren't messing with the 8139. */ 2345 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2346 { 2347 struct rtl8139_private *tp = netdev_priv(dev); 2348 void __iomem *ioaddr = tp->mmio_addr; 2349 u32 support; 2350 u8 cfg3, cfg5; 2351 2352 support = ((rtl_chip_info[tp->chipset].flags & HasLWake) 2353 ? (WAKE_PHY | WAKE_MAGIC 2354 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST) 2355 : 0); 2356 if (wol->wolopts & ~support) 2357 return -EINVAL; 2358 2359 spin_lock_irq(&tp->lock); 2360 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic); 2361 if (wol->wolopts & WAKE_PHY) 2362 cfg3 |= Cfg3_LinkUp; 2363 if (wol->wolopts & WAKE_MAGIC) 2364 cfg3 |= Cfg3_Magic; 2365 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2366 RTL_W8 (Config3, cfg3); 2367 RTL_W8 (Cfg9346, Cfg9346_Lock); 2368 2369 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF); 2370 /* (KON)FIXME: These are untested. We may have to set the 2371 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no 2372 documentation. */ 2373 if (wol->wolopts & WAKE_UCAST) 2374 cfg5 |= Cfg5_UWF; 2375 if (wol->wolopts & WAKE_MCAST) 2376 cfg5 |= Cfg5_MWF; 2377 if (wol->wolopts & WAKE_BCAST) 2378 cfg5 |= Cfg5_BWF; 2379 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */ 2380 spin_unlock_irq(&tp->lock); 2381 2382 return 0; 2383 } 2384 2385 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2386 { 2387 struct rtl8139_private *tp = netdev_priv(dev); 2388 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2389 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2390 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 2391 } 2392 2393 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2394 { 2395 struct rtl8139_private *tp = netdev_priv(dev); 2396 spin_lock_irq(&tp->lock); 2397 mii_ethtool_gset(&tp->mii, cmd); 2398 spin_unlock_irq(&tp->lock); 2399 return 0; 2400 } 2401 2402 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2403 { 2404 struct rtl8139_private *tp = netdev_priv(dev); 2405 int rc; 2406 spin_lock_irq(&tp->lock); 2407 rc = mii_ethtool_sset(&tp->mii, cmd); 2408 spin_unlock_irq(&tp->lock); 2409 return rc; 2410 } 2411 2412 static int rtl8139_nway_reset(struct net_device *dev) 2413 { 2414 struct rtl8139_private *tp = netdev_priv(dev); 2415 return mii_nway_restart(&tp->mii); 2416 } 2417 2418 static u32 rtl8139_get_link(struct net_device *dev) 2419 { 2420 struct rtl8139_private *tp = netdev_priv(dev); 2421 return mii_link_ok(&tp->mii); 2422 } 2423 2424 static u32 rtl8139_get_msglevel(struct net_device *dev) 2425 { 2426 struct rtl8139_private *tp = netdev_priv(dev); 2427 return tp->msg_enable; 2428 } 2429 2430 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum) 2431 { 2432 struct rtl8139_private *tp = netdev_priv(dev); 2433 tp->msg_enable = datum; 2434 } 2435 2436 static int rtl8139_get_regs_len(struct net_device *dev) 2437 { 2438 struct rtl8139_private *tp; 2439 /* TODO: we are too slack to do reg dumping for pio, for now */ 2440 if (use_io) 2441 return 0; 2442 tp = netdev_priv(dev); 2443 return tp->regs_len; 2444 } 2445 2446 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) 2447 { 2448 struct rtl8139_private *tp; 2449 2450 /* TODO: we are too slack to do reg dumping for pio, for now */ 2451 if (use_io) 2452 return; 2453 tp = netdev_priv(dev); 2454 2455 regs->version = RTL_REGS_VER; 2456 2457 spin_lock_irq(&tp->lock); 2458 memcpy_fromio(regbuf, tp->mmio_addr, regs->len); 2459 spin_unlock_irq(&tp->lock); 2460 } 2461 2462 static int rtl8139_get_sset_count(struct net_device *dev, int sset) 2463 { 2464 switch (sset) { 2465 case ETH_SS_STATS: 2466 return RTL_NUM_STATS; 2467 default: 2468 return -EOPNOTSUPP; 2469 } 2470 } 2471 2472 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2473 { 2474 struct rtl8139_private *tp = netdev_priv(dev); 2475 2476 data[0] = tp->xstats.early_rx; 2477 data[1] = tp->xstats.tx_buf_mapped; 2478 data[2] = tp->xstats.tx_timeouts; 2479 data[3] = tp->xstats.rx_lost_in_ring; 2480 } 2481 2482 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2483 { 2484 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2485 } 2486 2487 static const struct ethtool_ops rtl8139_ethtool_ops = { 2488 .get_drvinfo = rtl8139_get_drvinfo, 2489 .get_settings = rtl8139_get_settings, 2490 .set_settings = rtl8139_set_settings, 2491 .get_regs_len = rtl8139_get_regs_len, 2492 .get_regs = rtl8139_get_regs, 2493 .nway_reset = rtl8139_nway_reset, 2494 .get_link = rtl8139_get_link, 2495 .get_msglevel = rtl8139_get_msglevel, 2496 .set_msglevel = rtl8139_set_msglevel, 2497 .get_wol = rtl8139_get_wol, 2498 .set_wol = rtl8139_set_wol, 2499 .get_strings = rtl8139_get_strings, 2500 .get_sset_count = rtl8139_get_sset_count, 2501 .get_ethtool_stats = rtl8139_get_ethtool_stats, 2502 }; 2503 2504 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2505 { 2506 struct rtl8139_private *tp = netdev_priv(dev); 2507 int rc; 2508 2509 if (!netif_running(dev)) 2510 return -EINVAL; 2511 2512 spin_lock_irq(&tp->lock); 2513 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL); 2514 spin_unlock_irq(&tp->lock); 2515 2516 return rc; 2517 } 2518 2519 2520 static struct rtnl_link_stats64 * 2521 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 2522 { 2523 struct rtl8139_private *tp = netdev_priv(dev); 2524 void __iomem *ioaddr = tp->mmio_addr; 2525 unsigned long flags; 2526 unsigned int start; 2527 2528 if (netif_running(dev)) { 2529 spin_lock_irqsave (&tp->lock, flags); 2530 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2531 RTL_W32 (RxMissed, 0); 2532 spin_unlock_irqrestore (&tp->lock, flags); 2533 } 2534 2535 netdev_stats_to_stats64(stats, &dev->stats); 2536 2537 do { 2538 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 2539 stats->rx_packets = tp->rx_stats.packets; 2540 stats->rx_bytes = tp->rx_stats.bytes; 2541 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 2542 2543 do { 2544 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 2545 stats->tx_packets = tp->tx_stats.packets; 2546 stats->tx_bytes = tp->tx_stats.bytes; 2547 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 2548 2549 return stats; 2550 } 2551 2552 /* Set or clear the multicast filter for this adaptor. 2553 This routine is not state sensitive and need not be SMP locked. */ 2554 2555 static void __set_rx_mode (struct net_device *dev) 2556 { 2557 struct rtl8139_private *tp = netdev_priv(dev); 2558 void __iomem *ioaddr = tp->mmio_addr; 2559 u32 mc_filter[2]; /* Multicast hash filter */ 2560 int rx_mode; 2561 u32 tmp; 2562 2563 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n", 2564 dev->flags, RTL_R32(RxConfig)); 2565 2566 /* Note: do not reorder, GCC is clever about common statements. */ 2567 if (dev->flags & IFF_PROMISC) { 2568 rx_mode = 2569 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 2570 AcceptAllPhys; 2571 mc_filter[1] = mc_filter[0] = 0xffffffff; 2572 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2573 (dev->flags & IFF_ALLMULTI)) { 2574 /* Too many to filter perfectly -- accept all multicasts. */ 2575 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 2576 mc_filter[1] = mc_filter[0] = 0xffffffff; 2577 } else { 2578 struct netdev_hw_addr *ha; 2579 rx_mode = AcceptBroadcast | AcceptMyPhys; 2580 mc_filter[1] = mc_filter[0] = 0; 2581 netdev_for_each_mc_addr(ha, dev) { 2582 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2583 2584 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2585 rx_mode |= AcceptMulticast; 2586 } 2587 } 2588 2589 if (dev->features & NETIF_F_RXALL) 2590 rx_mode |= (AcceptErr | AcceptRunt); 2591 2592 /* We can safely update without stopping the chip. */ 2593 tmp = rtl8139_rx_config | rx_mode; 2594 if (tp->rx_config != tmp) { 2595 RTL_W32_F (RxConfig, tmp); 2596 tp->rx_config = tmp; 2597 } 2598 RTL_W32_F (MAR0 + 0, mc_filter[0]); 2599 RTL_W32_F (MAR0 + 4, mc_filter[1]); 2600 } 2601 2602 static void rtl8139_set_rx_mode (struct net_device *dev) 2603 { 2604 unsigned long flags; 2605 struct rtl8139_private *tp = netdev_priv(dev); 2606 2607 spin_lock_irqsave (&tp->lock, flags); 2608 __set_rx_mode(dev); 2609 spin_unlock_irqrestore (&tp->lock, flags); 2610 } 2611 2612 #ifdef CONFIG_PM 2613 2614 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state) 2615 { 2616 struct net_device *dev = pci_get_drvdata (pdev); 2617 struct rtl8139_private *tp = netdev_priv(dev); 2618 void __iomem *ioaddr = tp->mmio_addr; 2619 unsigned long flags; 2620 2621 pci_save_state (pdev); 2622 2623 if (!netif_running (dev)) 2624 return 0; 2625 2626 netif_device_detach (dev); 2627 2628 spin_lock_irqsave (&tp->lock, flags); 2629 2630 /* Disable interrupts, stop Tx and Rx. */ 2631 RTL_W16 (IntrMask, 0); 2632 RTL_W8 (ChipCmd, 0); 2633 2634 /* Update the error counts. */ 2635 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2636 RTL_W32 (RxMissed, 0); 2637 2638 spin_unlock_irqrestore (&tp->lock, flags); 2639 2640 pci_set_power_state (pdev, PCI_D3hot); 2641 2642 return 0; 2643 } 2644 2645 2646 static int rtl8139_resume (struct pci_dev *pdev) 2647 { 2648 struct net_device *dev = pci_get_drvdata (pdev); 2649 2650 pci_restore_state (pdev); 2651 if (!netif_running (dev)) 2652 return 0; 2653 pci_set_power_state (pdev, PCI_D0); 2654 rtl8139_init_ring (dev); 2655 rtl8139_hw_start (dev); 2656 netif_device_attach (dev); 2657 return 0; 2658 } 2659 2660 #endif /* CONFIG_PM */ 2661 2662 2663 static struct pci_driver rtl8139_pci_driver = { 2664 .name = DRV_NAME, 2665 .id_table = rtl8139_pci_tbl, 2666 .probe = rtl8139_init_one, 2667 .remove = rtl8139_remove_one, 2668 #ifdef CONFIG_PM 2669 .suspend = rtl8139_suspend, 2670 .resume = rtl8139_resume, 2671 #endif /* CONFIG_PM */ 2672 }; 2673 2674 2675 static int __init rtl8139_init_module (void) 2676 { 2677 /* when we're a module, we always print a version message, 2678 * even if no 8139 board is found. 2679 */ 2680 #ifdef MODULE 2681 pr_info(RTL8139_DRIVER_NAME "\n"); 2682 #endif 2683 2684 return pci_register_driver(&rtl8139_pci_driver); 2685 } 2686 2687 2688 static void __exit rtl8139_cleanup_module (void) 2689 { 2690 pci_unregister_driver (&rtl8139_pci_driver); 2691 } 2692 2693 2694 module_init(rtl8139_init_module); 2695 module_exit(rtl8139_cleanup_module); 2696