1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */ 2 /* 3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com> 4 5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c] 6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c] 7 Copyright 2001 Manfred Spraul [natsemi.c] 8 Copyright 1999-2001 by Donald Becker. [natsemi.c] 9 Written 1997-2001 by Donald Becker. [8139too.c] 10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c] 11 12 This software may be used and distributed according to the terms of 13 the GNU General Public License (GPL), incorporated herein by reference. 14 Drivers based on or derived from this code fall under the GPL and must 15 retain the authorship, copyright and license notice. This file is not 16 a complete program and may only be used when the entire operating 17 system is licensed under the GPL. 18 19 See the file COPYING in this distribution for more information. 20 21 Contributors: 22 23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br> 24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br> 25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br> 26 27 TODO: 28 * Test Tx checksumming thoroughly 29 30 Low priority TODO: 31 * Complete reset on PciErr 32 * Consider Rx interrupt mitigation using TimerIntr 33 * Investigate using skb->priority with h/w VLAN priority 34 * Investigate using High Priority Tx Queue with skb->priority 35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error 36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error 37 * Implement Tx software interrupt mitigation via 38 Tx descriptor bit 39 * The real minimum of CP_MIN_MTU is 4 bytes. However, 40 for this to be supported, one must(?) turn on packet padding. 41 * Support external MII transceivers (patch available) 42 43 NOTES: 44 * TX checksumming is considered experimental. It is off by 45 default, use ethtool to turn it on. 46 47 */ 48 49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 50 51 #define DRV_NAME "8139cp" 52 #define DRV_VERSION "1.3" 53 #define DRV_RELDATE "Mar 22, 2004" 54 55 56 #include <linux/module.h> 57 #include <linux/moduleparam.h> 58 #include <linux/kernel.h> 59 #include <linux/compiler.h> 60 #include <linux/netdevice.h> 61 #include <linux/etherdevice.h> 62 #include <linux/init.h> 63 #include <linux/interrupt.h> 64 #include <linux/pci.h> 65 #include <linux/dma-mapping.h> 66 #include <linux/delay.h> 67 #include <linux/ethtool.h> 68 #include <linux/gfp.h> 69 #include <linux/mii.h> 70 #include <linux/if_vlan.h> 71 #include <linux/crc32.h> 72 #include <linux/in.h> 73 #include <linux/ip.h> 74 #include <linux/tcp.h> 75 #include <linux/udp.h> 76 #include <linux/cache.h> 77 #include <asm/io.h> 78 #include <asm/irq.h> 79 #include <asm/uaccess.h> 80 81 /* These identify the driver base version and may not be removed. */ 82 static char version[] = 83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n"; 84 85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); 86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver"); 87 MODULE_VERSION(DRV_VERSION); 88 MODULE_LICENSE("GPL"); 89 90 static int debug = -1; 91 module_param(debug, int, 0); 92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number"); 93 94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 96 static int multicast_filter_limit = 32; 97 module_param(multicast_filter_limit, int, 0); 98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses"); 99 100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 101 NETIF_MSG_PROBE | \ 102 NETIF_MSG_LINK) 103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */ 104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */ 105 #define CP_REGS_SIZE (0xff + 1) 106 #define CP_REGS_VER 1 /* version 1 */ 107 #define CP_RX_RING_SIZE 64 108 #define CP_TX_RING_SIZE 64 109 #define CP_RING_BYTES \ 110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \ 111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \ 112 CP_STATS_SIZE) 113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1)) 114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1)) 115 #define TX_BUFFS_AVAIL(CP) \ 116 (((CP)->tx_tail <= (CP)->tx_head) ? \ 117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \ 118 (CP)->tx_tail - (CP)->tx_head - 1) 119 120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ 121 #define CP_INTERNAL_PHY 32 122 123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ 124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */ 125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */ 126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */ 128 129 /* Time in jiffies before concluding the transmitter is hung. */ 130 #define TX_TIMEOUT (6*HZ) 131 132 /* hardware minimum and maximum for a single frame's data payload */ 133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */ 134 #define CP_MAX_MTU 4096 135 136 enum { 137 /* NIC register offsets */ 138 MAC0 = 0x00, /* Ethernet hardware address. */ 139 MAR0 = 0x08, /* Multicast filter. */ 140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */ 141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */ 142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */ 143 Cmd = 0x37, /* Command register */ 144 IntrMask = 0x3C, /* Interrupt mask */ 145 IntrStatus = 0x3E, /* Interrupt status */ 146 TxConfig = 0x40, /* Tx configuration */ 147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */ 148 RxConfig = 0x44, /* Rx configuration */ 149 RxMissed = 0x4C, /* 24 bits valid, write clears */ 150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */ 151 Config1 = 0x52, /* Config1 */ 152 Config3 = 0x59, /* Config3 */ 153 Config4 = 0x5A, /* Config4 */ 154 MultiIntr = 0x5C, /* Multiple interrupt select */ 155 BasicModeCtrl = 0x62, /* MII BMCR */ 156 BasicModeStatus = 0x64, /* MII BMSR */ 157 NWayAdvert = 0x66, /* MII ADVERTISE */ 158 NWayLPAR = 0x68, /* MII LPA */ 159 NWayExpansion = 0x6A, /* MII Expansion */ 160 Config5 = 0xD8, /* Config5 */ 161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ 162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ 163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ 164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ 165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */ 166 TxThresh = 0xEC, /* Early Tx threshold */ 167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */ 168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */ 169 170 /* Tx and Rx status descriptors */ 171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 172 RingEnd = (1 << 30), /* End of descriptor ring */ 173 FirstFrag = (1 << 29), /* First segment of a packet */ 174 LastFrag = (1 << 28), /* Final segment of a packet */ 175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ 176 MSSShift = 16, /* MSS value position */ 177 MSSMask = 0xfff, /* MSS value: 11 bits */ 178 TxError = (1 << 23), /* Tx error summary */ 179 RxError = (1 << 20), /* Rx error summary */ 180 IPCS = (1 << 18), /* Calculate IP checksum */ 181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ 182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ 183 TxVlanTag = (1 << 17), /* Add VLAN tag */ 184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */ 185 IPFail = (1 << 15), /* IP checksum failed */ 186 UDPFail = (1 << 14), /* UDP/IP checksum failed */ 187 TCPFail = (1 << 13), /* TCP/IP checksum failed */ 188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */ 189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */ 190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */ 191 RxProtoTCP = 1, 192 RxProtoUDP = 2, 193 RxProtoIP = 3, 194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */ 195 TxOWC = (1 << 22), /* Tx Out-of-window collision */ 196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */ 197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */ 198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */ 199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */ 200 RxErrFrame = (1 << 27), /* Rx frame alignment error */ 201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */ 202 RxErrCRC = (1 << 18), /* Rx CRC error */ 203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */ 204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */ 205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */ 206 207 /* StatsAddr register */ 208 DumpStats = (1 << 3), /* Begin stats dump */ 209 210 /* RxConfig register */ 211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */ 212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */ 213 AcceptErr = 0x20, /* Accept packets with CRC errors */ 214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */ 215 AcceptBroadcast = 0x08, /* Accept broadcast packets */ 216 AcceptMulticast = 0x04, /* Accept multicast packets */ 217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */ 218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */ 219 220 /* IntrMask / IntrStatus registers */ 221 PciErr = (1 << 15), /* System error on the PCI bus */ 222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */ 223 LenChg = (1 << 13), /* Cable length change */ 224 SWInt = (1 << 8), /* Software-requested interrupt */ 225 TxEmpty = (1 << 7), /* No Tx descriptors available */ 226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */ 227 LinkChg = (1 << 5), /* Packet underrun, or link change */ 228 RxEmpty = (1 << 4), /* No Rx descriptors available */ 229 TxErr = (1 << 3), /* Tx error */ 230 TxOK = (1 << 2), /* Tx packet sent */ 231 RxErr = (1 << 1), /* Rx error */ 232 RxOK = (1 << 0), /* Rx packet received */ 233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers, 234 but hardware likes to raise it */ 235 236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty | 237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK | 238 RxErr | RxOK | IntrResvd, 239 240 /* C mode command register */ 241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */ 242 RxOn = (1 << 3), /* Rx mode enable */ 243 TxOn = (1 << 2), /* Tx mode enable */ 244 245 /* C+ mode command register */ 246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */ 247 RxChkSum = (1 << 5), /* Rx checksum offload enable */ 248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */ 249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */ 250 CpRxOn = (1 << 1), /* Rx mode enable */ 251 CpTxOn = (1 << 0), /* Tx mode enable */ 252 253 /* Cfg9436 EEPROM control register */ 254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */ 255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */ 256 257 /* TxConfig register */ 258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */ 259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 260 261 /* Early Tx Threshold register */ 262 TxThreshMask = 0x3f, /* Mask bits 5-0 */ 263 TxThreshMax = 2048, /* Max early Tx threshold */ 264 265 /* Config1 register */ 266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */ 267 LWACT = (1 << 4), /* LWAKE active mode */ 268 PMEnable = (1 << 0), /* Enable various PM features of chip */ 269 270 /* Config3 register */ 271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */ 272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 274 275 /* Config4 register */ 276 LWPTN = (1 << 1), /* LWAKE Pattern */ 277 LWPME = (1 << 4), /* LANWAKE vs PMEB */ 278 279 /* Config5 register */ 280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 281 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 282 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 283 LANWake = (1 << 1), /* Enable LANWake signal */ 284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 285 286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty, 287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr, 288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask, 289 }; 290 291 static const unsigned int cp_rx_config = 292 (RX_FIFO_THRESH << RxCfgFIFOShift) | 293 (RX_DMA_BURST << RxCfgDMAShift); 294 295 struct cp_desc { 296 __le32 opts1; 297 __le32 opts2; 298 __le64 addr; 299 }; 300 301 struct cp_dma_stats { 302 __le64 tx_ok; 303 __le64 rx_ok; 304 __le64 tx_err; 305 __le32 rx_err; 306 __le16 rx_fifo; 307 __le16 frame_align; 308 __le32 tx_ok_1col; 309 __le32 tx_ok_mcol; 310 __le64 rx_ok_phys; 311 __le64 rx_ok_bcast; 312 __le32 rx_ok_mcast; 313 __le16 tx_abort; 314 __le16 tx_underrun; 315 } __packed; 316 317 struct cp_extra_stats { 318 unsigned long rx_frags; 319 }; 320 321 struct cp_private { 322 void __iomem *regs; 323 struct net_device *dev; 324 spinlock_t lock; 325 u32 msg_enable; 326 327 struct napi_struct napi; 328 329 struct pci_dev *pdev; 330 u32 rx_config; 331 u16 cpcmd; 332 333 struct cp_extra_stats cp_stats; 334 335 unsigned rx_head ____cacheline_aligned; 336 unsigned rx_tail; 337 struct cp_desc *rx_ring; 338 struct sk_buff *rx_skb[CP_RX_RING_SIZE]; 339 340 unsigned tx_head ____cacheline_aligned; 341 unsigned tx_tail; 342 struct cp_desc *tx_ring; 343 struct sk_buff *tx_skb[CP_TX_RING_SIZE]; 344 345 unsigned rx_buf_sz; 346 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */ 347 348 dma_addr_t ring_dma; 349 350 struct mii_if_info mii_if; 351 }; 352 353 #define cpr8(reg) readb(cp->regs + (reg)) 354 #define cpr16(reg) readw(cp->regs + (reg)) 355 #define cpr32(reg) readl(cp->regs + (reg)) 356 #define cpw8(reg,val) writeb((val), cp->regs + (reg)) 357 #define cpw16(reg,val) writew((val), cp->regs + (reg)) 358 #define cpw32(reg,val) writel((val), cp->regs + (reg)) 359 #define cpw8_f(reg,val) do { \ 360 writeb((val), cp->regs + (reg)); \ 361 readb(cp->regs + (reg)); \ 362 } while (0) 363 #define cpw16_f(reg,val) do { \ 364 writew((val), cp->regs + (reg)); \ 365 readw(cp->regs + (reg)); \ 366 } while (0) 367 #define cpw32_f(reg,val) do { \ 368 writel((val), cp->regs + (reg)); \ 369 readl(cp->regs + (reg)); \ 370 } while (0) 371 372 373 static void __cp_set_rx_mode (struct net_device *dev); 374 static void cp_tx (struct cp_private *cp); 375 static void cp_clean_rings (struct cp_private *cp); 376 #ifdef CONFIG_NET_POLL_CONTROLLER 377 static void cp_poll_controller(struct net_device *dev); 378 #endif 379 static int cp_get_eeprom_len(struct net_device *dev); 380 static int cp_get_eeprom(struct net_device *dev, 381 struct ethtool_eeprom *eeprom, u8 *data); 382 static int cp_set_eeprom(struct net_device *dev, 383 struct ethtool_eeprom *eeprom, u8 *data); 384 385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = { 386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), }, 387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), }, 388 { }, 389 }; 390 MODULE_DEVICE_TABLE(pci, cp_pci_tbl); 391 392 static struct { 393 const char str[ETH_GSTRING_LEN]; 394 } ethtool_stats_keys[] = { 395 { "tx_ok" }, 396 { "rx_ok" }, 397 { "tx_err" }, 398 { "rx_err" }, 399 { "rx_fifo" }, 400 { "frame_align" }, 401 { "tx_ok_1col" }, 402 { "tx_ok_mcol" }, 403 { "rx_ok_phys" }, 404 { "rx_ok_bcast" }, 405 { "rx_ok_mcast" }, 406 { "tx_abort" }, 407 { "tx_underrun" }, 408 { "rx_frags" }, 409 }; 410 411 412 static inline void cp_set_rxbufsize (struct cp_private *cp) 413 { 414 unsigned int mtu = cp->dev->mtu; 415 416 if (mtu > ETH_DATA_LEN) 417 /* MTU + ethernet header + FCS + optional VLAN tag */ 418 cp->rx_buf_sz = mtu + ETH_HLEN + 8; 419 else 420 cp->rx_buf_sz = PKT_BUF_SZ; 421 } 422 423 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb, 424 struct cp_desc *desc) 425 { 426 u32 opts2 = le32_to_cpu(desc->opts2); 427 428 skb->protocol = eth_type_trans (skb, cp->dev); 429 430 cp->dev->stats.rx_packets++; 431 cp->dev->stats.rx_bytes += skb->len; 432 433 if (opts2 & RxVlanTagged) 434 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 435 436 napi_gro_receive(&cp->napi, skb); 437 } 438 439 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail, 440 u32 status, u32 len) 441 { 442 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n", 443 rx_tail, status, len); 444 cp->dev->stats.rx_errors++; 445 if (status & RxErrFrame) 446 cp->dev->stats.rx_frame_errors++; 447 if (status & RxErrCRC) 448 cp->dev->stats.rx_crc_errors++; 449 if ((status & RxErrRunt) || (status & RxErrLong)) 450 cp->dev->stats.rx_length_errors++; 451 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) 452 cp->dev->stats.rx_length_errors++; 453 if (status & RxErrFIFO) 454 cp->dev->stats.rx_fifo_errors++; 455 } 456 457 static inline unsigned int cp_rx_csum_ok (u32 status) 458 { 459 unsigned int protocol = (status >> 16) & 0x3; 460 461 if (((protocol == RxProtoTCP) && !(status & TCPFail)) || 462 ((protocol == RxProtoUDP) && !(status & UDPFail))) 463 return 1; 464 else 465 return 0; 466 } 467 468 static int cp_rx_poll(struct napi_struct *napi, int budget) 469 { 470 struct cp_private *cp = container_of(napi, struct cp_private, napi); 471 struct net_device *dev = cp->dev; 472 unsigned int rx_tail = cp->rx_tail; 473 int rx; 474 475 rx_status_loop: 476 rx = 0; 477 cpw16(IntrStatus, cp_rx_intr_mask); 478 479 while (rx < budget) { 480 u32 status, len; 481 dma_addr_t mapping, new_mapping; 482 struct sk_buff *skb, *new_skb; 483 struct cp_desc *desc; 484 const unsigned buflen = cp->rx_buf_sz; 485 486 skb = cp->rx_skb[rx_tail]; 487 BUG_ON(!skb); 488 489 desc = &cp->rx_ring[rx_tail]; 490 status = le32_to_cpu(desc->opts1); 491 if (status & DescOwn) 492 break; 493 494 len = (status & 0x1fff) - 4; 495 mapping = le64_to_cpu(desc->addr); 496 497 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) { 498 /* we don't support incoming fragmented frames. 499 * instead, we attempt to ensure that the 500 * pre-allocated RX skbs are properly sized such 501 * that RX fragments are never encountered 502 */ 503 cp_rx_err_acct(cp, rx_tail, status, len); 504 dev->stats.rx_dropped++; 505 cp->cp_stats.rx_frags++; 506 goto rx_next; 507 } 508 509 if (status & (RxError | RxErrFIFO)) { 510 cp_rx_err_acct(cp, rx_tail, status, len); 511 goto rx_next; 512 } 513 514 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n", 515 rx_tail, status, len); 516 517 new_skb = netdev_alloc_skb_ip_align(dev, buflen); 518 if (!new_skb) { 519 dev->stats.rx_dropped++; 520 goto rx_next; 521 } 522 523 new_mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen, 524 PCI_DMA_FROMDEVICE); 525 if (dma_mapping_error(&cp->pdev->dev, new_mapping)) { 526 dev->stats.rx_dropped++; 527 kfree_skb(new_skb); 528 goto rx_next; 529 } 530 531 dma_unmap_single(&cp->pdev->dev, mapping, 532 buflen, PCI_DMA_FROMDEVICE); 533 534 /* Handle checksum offloading for incoming packets. */ 535 if (cp_rx_csum_ok(status)) 536 skb->ip_summed = CHECKSUM_UNNECESSARY; 537 else 538 skb_checksum_none_assert(skb); 539 540 skb_put(skb, len); 541 542 cp->rx_skb[rx_tail] = new_skb; 543 544 cp_rx_skb(cp, skb, desc); 545 rx++; 546 mapping = new_mapping; 547 548 rx_next: 549 cp->rx_ring[rx_tail].opts2 = 0; 550 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping); 551 if (rx_tail == (CP_RX_RING_SIZE - 1)) 552 desc->opts1 = cpu_to_le32(DescOwn | RingEnd | 553 cp->rx_buf_sz); 554 else 555 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz); 556 rx_tail = NEXT_RX(rx_tail); 557 } 558 559 cp->rx_tail = rx_tail; 560 561 /* if we did not reach work limit, then we're done with 562 * this round of polling 563 */ 564 if (rx < budget) { 565 unsigned long flags; 566 567 if (cpr16(IntrStatus) & cp_rx_intr_mask) 568 goto rx_status_loop; 569 570 napi_gro_flush(napi, false); 571 spin_lock_irqsave(&cp->lock, flags); 572 __napi_complete(napi); 573 cpw16_f(IntrMask, cp_intr_mask); 574 spin_unlock_irqrestore(&cp->lock, flags); 575 } 576 577 return rx; 578 } 579 580 static irqreturn_t cp_interrupt (int irq, void *dev_instance) 581 { 582 struct net_device *dev = dev_instance; 583 struct cp_private *cp; 584 int handled = 0; 585 u16 status; 586 587 if (unlikely(dev == NULL)) 588 return IRQ_NONE; 589 cp = netdev_priv(dev); 590 591 spin_lock(&cp->lock); 592 593 status = cpr16(IntrStatus); 594 if (!status || (status == 0xFFFF)) 595 goto out_unlock; 596 597 handled = 1; 598 599 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n", 600 status, cpr8(Cmd), cpr16(CpCmd)); 601 602 cpw16(IntrStatus, status & ~cp_rx_intr_mask); 603 604 /* close possible race's with dev_close */ 605 if (unlikely(!netif_running(dev))) { 606 cpw16(IntrMask, 0); 607 goto out_unlock; 608 } 609 610 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr)) 611 if (napi_schedule_prep(&cp->napi)) { 612 cpw16_f(IntrMask, cp_norx_intr_mask); 613 __napi_schedule(&cp->napi); 614 } 615 616 if (status & (TxOK | TxErr | TxEmpty | SWInt)) 617 cp_tx(cp); 618 if (status & LinkChg) 619 mii_check_media(&cp->mii_if, netif_msg_link(cp), false); 620 621 622 if (status & PciErr) { 623 u16 pci_status; 624 625 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status); 626 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status); 627 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n", 628 status, pci_status); 629 630 /* TODO: reset hardware */ 631 } 632 633 out_unlock: 634 spin_unlock(&cp->lock); 635 636 return IRQ_RETVAL(handled); 637 } 638 639 #ifdef CONFIG_NET_POLL_CONTROLLER 640 /* 641 * Polling receive - used by netconsole and other diagnostic tools 642 * to allow network i/o with interrupts disabled. 643 */ 644 static void cp_poll_controller(struct net_device *dev) 645 { 646 struct cp_private *cp = netdev_priv(dev); 647 const int irq = cp->pdev->irq; 648 649 disable_irq(irq); 650 cp_interrupt(irq, dev); 651 enable_irq(irq); 652 } 653 #endif 654 655 static void cp_tx (struct cp_private *cp) 656 { 657 unsigned tx_head = cp->tx_head; 658 unsigned tx_tail = cp->tx_tail; 659 unsigned bytes_compl = 0, pkts_compl = 0; 660 661 while (tx_tail != tx_head) { 662 struct cp_desc *txd = cp->tx_ring + tx_tail; 663 struct sk_buff *skb; 664 u32 status; 665 666 rmb(); 667 status = le32_to_cpu(txd->opts1); 668 if (status & DescOwn) 669 break; 670 671 skb = cp->tx_skb[tx_tail]; 672 BUG_ON(!skb); 673 674 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr), 675 le32_to_cpu(txd->opts1) & 0xffff, 676 PCI_DMA_TODEVICE); 677 678 if (status & LastFrag) { 679 if (status & (TxError | TxFIFOUnder)) { 680 netif_dbg(cp, tx_err, cp->dev, 681 "tx err, status 0x%x\n", status); 682 cp->dev->stats.tx_errors++; 683 if (status & TxOWC) 684 cp->dev->stats.tx_window_errors++; 685 if (status & TxMaxCol) 686 cp->dev->stats.tx_aborted_errors++; 687 if (status & TxLinkFail) 688 cp->dev->stats.tx_carrier_errors++; 689 if (status & TxFIFOUnder) 690 cp->dev->stats.tx_fifo_errors++; 691 } else { 692 cp->dev->stats.collisions += 693 ((status >> TxColCntShift) & TxColCntMask); 694 cp->dev->stats.tx_packets++; 695 cp->dev->stats.tx_bytes += skb->len; 696 netif_dbg(cp, tx_done, cp->dev, 697 "tx done, slot %d\n", tx_tail); 698 } 699 bytes_compl += skb->len; 700 pkts_compl++; 701 dev_kfree_skb_irq(skb); 702 } 703 704 cp->tx_skb[tx_tail] = NULL; 705 706 tx_tail = NEXT_TX(tx_tail); 707 } 708 709 cp->tx_tail = tx_tail; 710 711 netdev_completed_queue(cp->dev, pkts_compl, bytes_compl); 712 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1)) 713 netif_wake_queue(cp->dev); 714 } 715 716 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb) 717 { 718 return vlan_tx_tag_present(skb) ? 719 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; 720 } 721 722 static void unwind_tx_frag_mapping(struct cp_private *cp, struct sk_buff *skb, 723 int first, int entry_last) 724 { 725 int frag, index; 726 struct cp_desc *txd; 727 skb_frag_t *this_frag; 728 for (frag = 0; frag+first < entry_last; frag++) { 729 index = first+frag; 730 cp->tx_skb[index] = NULL; 731 txd = &cp->tx_ring[index]; 732 this_frag = &skb_shinfo(skb)->frags[frag]; 733 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr), 734 skb_frag_size(this_frag), PCI_DMA_TODEVICE); 735 } 736 } 737 738 static netdev_tx_t cp_start_xmit (struct sk_buff *skb, 739 struct net_device *dev) 740 { 741 struct cp_private *cp = netdev_priv(dev); 742 unsigned entry; 743 u32 eor, flags; 744 unsigned long intr_flags; 745 __le32 opts2; 746 int mss = 0; 747 748 spin_lock_irqsave(&cp->lock, intr_flags); 749 750 /* This is a hard error, log it. */ 751 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) { 752 netif_stop_queue(dev); 753 spin_unlock_irqrestore(&cp->lock, intr_flags); 754 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 755 return NETDEV_TX_BUSY; 756 } 757 758 entry = cp->tx_head; 759 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; 760 mss = skb_shinfo(skb)->gso_size; 761 762 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb)); 763 764 if (skb_shinfo(skb)->nr_frags == 0) { 765 struct cp_desc *txd = &cp->tx_ring[entry]; 766 u32 len; 767 dma_addr_t mapping; 768 769 len = skb->len; 770 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE); 771 if (dma_mapping_error(&cp->pdev->dev, mapping)) 772 goto out_dma_error; 773 774 txd->opts2 = opts2; 775 txd->addr = cpu_to_le64(mapping); 776 wmb(); 777 778 flags = eor | len | DescOwn | FirstFrag | LastFrag; 779 780 if (mss) 781 flags |= LargeSend | ((mss & MSSMask) << MSSShift); 782 else if (skb->ip_summed == CHECKSUM_PARTIAL) { 783 const struct iphdr *ip = ip_hdr(skb); 784 if (ip->protocol == IPPROTO_TCP) 785 flags |= IPCS | TCPCS; 786 else if (ip->protocol == IPPROTO_UDP) 787 flags |= IPCS | UDPCS; 788 else 789 WARN_ON(1); /* we need a WARN() */ 790 } 791 792 txd->opts1 = cpu_to_le32(flags); 793 wmb(); 794 795 cp->tx_skb[entry] = skb; 796 entry = NEXT_TX(entry); 797 } else { 798 struct cp_desc *txd; 799 u32 first_len, first_eor; 800 dma_addr_t first_mapping; 801 int frag, first_entry = entry; 802 const struct iphdr *ip = ip_hdr(skb); 803 804 /* We must give this initial chunk to the device last. 805 * Otherwise we could race with the device. 806 */ 807 first_eor = eor; 808 first_len = skb_headlen(skb); 809 first_mapping = dma_map_single(&cp->pdev->dev, skb->data, 810 first_len, PCI_DMA_TODEVICE); 811 if (dma_mapping_error(&cp->pdev->dev, first_mapping)) 812 goto out_dma_error; 813 814 cp->tx_skb[entry] = skb; 815 entry = NEXT_TX(entry); 816 817 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 818 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; 819 u32 len; 820 u32 ctrl; 821 dma_addr_t mapping; 822 823 len = skb_frag_size(this_frag); 824 mapping = dma_map_single(&cp->pdev->dev, 825 skb_frag_address(this_frag), 826 len, PCI_DMA_TODEVICE); 827 if (dma_mapping_error(&cp->pdev->dev, mapping)) { 828 unwind_tx_frag_mapping(cp, skb, first_entry, entry); 829 goto out_dma_error; 830 } 831 832 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; 833 834 ctrl = eor | len | DescOwn; 835 836 if (mss) 837 ctrl |= LargeSend | 838 ((mss & MSSMask) << MSSShift); 839 else if (skb->ip_summed == CHECKSUM_PARTIAL) { 840 if (ip->protocol == IPPROTO_TCP) 841 ctrl |= IPCS | TCPCS; 842 else if (ip->protocol == IPPROTO_UDP) 843 ctrl |= IPCS | UDPCS; 844 else 845 BUG(); 846 } 847 848 if (frag == skb_shinfo(skb)->nr_frags - 1) 849 ctrl |= LastFrag; 850 851 txd = &cp->tx_ring[entry]; 852 txd->opts2 = opts2; 853 txd->addr = cpu_to_le64(mapping); 854 wmb(); 855 856 txd->opts1 = cpu_to_le32(ctrl); 857 wmb(); 858 859 cp->tx_skb[entry] = skb; 860 entry = NEXT_TX(entry); 861 } 862 863 txd = &cp->tx_ring[first_entry]; 864 txd->opts2 = opts2; 865 txd->addr = cpu_to_le64(first_mapping); 866 wmb(); 867 868 if (skb->ip_summed == CHECKSUM_PARTIAL) { 869 if (ip->protocol == IPPROTO_TCP) 870 txd->opts1 = cpu_to_le32(first_eor | first_len | 871 FirstFrag | DescOwn | 872 IPCS | TCPCS); 873 else if (ip->protocol == IPPROTO_UDP) 874 txd->opts1 = cpu_to_le32(first_eor | first_len | 875 FirstFrag | DescOwn | 876 IPCS | UDPCS); 877 else 878 BUG(); 879 } else 880 txd->opts1 = cpu_to_le32(first_eor | first_len | 881 FirstFrag | DescOwn); 882 wmb(); 883 } 884 cp->tx_head = entry; 885 886 netdev_sent_queue(dev, skb->len); 887 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n", 888 entry, skb->len); 889 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1)) 890 netif_stop_queue(dev); 891 892 out_unlock: 893 spin_unlock_irqrestore(&cp->lock, intr_flags); 894 895 cpw8(TxPoll, NormalTxPoll); 896 897 return NETDEV_TX_OK; 898 out_dma_error: 899 dev_kfree_skb_any(skb); 900 cp->dev->stats.tx_dropped++; 901 goto out_unlock; 902 } 903 904 /* Set or clear the multicast filter for this adaptor. 905 This routine is not state sensitive and need not be SMP locked. */ 906 907 static void __cp_set_rx_mode (struct net_device *dev) 908 { 909 struct cp_private *cp = netdev_priv(dev); 910 u32 mc_filter[2]; /* Multicast hash filter */ 911 int rx_mode; 912 913 /* Note: do not reorder, GCC is clever about common statements. */ 914 if (dev->flags & IFF_PROMISC) { 915 /* Unconditionally log net taps. */ 916 rx_mode = 917 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 918 AcceptAllPhys; 919 mc_filter[1] = mc_filter[0] = 0xffffffff; 920 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 921 (dev->flags & IFF_ALLMULTI)) { 922 /* Too many to filter perfectly -- accept all multicasts. */ 923 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 924 mc_filter[1] = mc_filter[0] = 0xffffffff; 925 } else { 926 struct netdev_hw_addr *ha; 927 rx_mode = AcceptBroadcast | AcceptMyPhys; 928 mc_filter[1] = mc_filter[0] = 0; 929 netdev_for_each_mc_addr(ha, dev) { 930 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 931 932 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 933 rx_mode |= AcceptMulticast; 934 } 935 } 936 937 /* We can safely update without stopping the chip. */ 938 cp->rx_config = cp_rx_config | rx_mode; 939 cpw32_f(RxConfig, cp->rx_config); 940 941 cpw32_f (MAR0 + 0, mc_filter[0]); 942 cpw32_f (MAR0 + 4, mc_filter[1]); 943 } 944 945 static void cp_set_rx_mode (struct net_device *dev) 946 { 947 unsigned long flags; 948 struct cp_private *cp = netdev_priv(dev); 949 950 spin_lock_irqsave (&cp->lock, flags); 951 __cp_set_rx_mode(dev); 952 spin_unlock_irqrestore (&cp->lock, flags); 953 } 954 955 static void __cp_get_stats(struct cp_private *cp) 956 { 957 /* only lower 24 bits valid; write any value to clear */ 958 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff); 959 cpw32 (RxMissed, 0); 960 } 961 962 static struct net_device_stats *cp_get_stats(struct net_device *dev) 963 { 964 struct cp_private *cp = netdev_priv(dev); 965 unsigned long flags; 966 967 /* The chip only need report frame silently dropped. */ 968 spin_lock_irqsave(&cp->lock, flags); 969 if (netif_running(dev) && netif_device_present(dev)) 970 __cp_get_stats(cp); 971 spin_unlock_irqrestore(&cp->lock, flags); 972 973 return &dev->stats; 974 } 975 976 static void cp_stop_hw (struct cp_private *cp) 977 { 978 cpw16(IntrStatus, ~(cpr16(IntrStatus))); 979 cpw16_f(IntrMask, 0); 980 cpw8(Cmd, 0); 981 cpw16_f(CpCmd, 0); 982 cpw16_f(IntrStatus, ~(cpr16(IntrStatus))); 983 984 cp->rx_tail = 0; 985 cp->tx_head = cp->tx_tail = 0; 986 987 netdev_reset_queue(cp->dev); 988 } 989 990 static void cp_reset_hw (struct cp_private *cp) 991 { 992 unsigned work = 1000; 993 994 cpw8(Cmd, CmdReset); 995 996 while (work--) { 997 if (!(cpr8(Cmd) & CmdReset)) 998 return; 999 1000 schedule_timeout_uninterruptible(10); 1001 } 1002 1003 netdev_err(cp->dev, "hardware reset timeout\n"); 1004 } 1005 1006 static inline void cp_start_hw (struct cp_private *cp) 1007 { 1008 dma_addr_t ring_dma; 1009 1010 cpw16(CpCmd, cp->cpcmd); 1011 1012 /* 1013 * These (at least TxRingAddr) need to be configured after the 1014 * corresponding bits in CpCmd are enabled. Datasheet v1.6 §6.33 1015 * (C+ Command Register) recommends that these and more be configured 1016 * *after* the [RT]xEnable bits in CpCmd are set. And on some hardware 1017 * it's been observed that the TxRingAddr is actually reset to garbage 1018 * when C+ mode Tx is enabled in CpCmd. 1019 */ 1020 cpw32_f(HiTxRingAddr, 0); 1021 cpw32_f(HiTxRingAddr + 4, 0); 1022 1023 ring_dma = cp->ring_dma; 1024 cpw32_f(RxRingAddr, ring_dma & 0xffffffff); 1025 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16); 1026 1027 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE; 1028 cpw32_f(TxRingAddr, ring_dma & 0xffffffff); 1029 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16); 1030 1031 /* 1032 * Strictly speaking, the datasheet says this should be enabled 1033 * *before* setting the descriptor addresses. But what, then, would 1034 * prevent it from doing DMA to random unconfigured addresses? 1035 * This variant appears to work fine. 1036 */ 1037 cpw8(Cmd, RxOn | TxOn); 1038 1039 netdev_reset_queue(cp->dev); 1040 } 1041 1042 static void cp_enable_irq(struct cp_private *cp) 1043 { 1044 cpw16_f(IntrMask, cp_intr_mask); 1045 } 1046 1047 static void cp_init_hw (struct cp_private *cp) 1048 { 1049 struct net_device *dev = cp->dev; 1050 1051 cp_reset_hw(cp); 1052 1053 cpw8_f (Cfg9346, Cfg9346_Unlock); 1054 1055 /* Restore our idea of the MAC address. */ 1056 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); 1057 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4))); 1058 1059 cp_start_hw(cp); 1060 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */ 1061 1062 __cp_set_rx_mode(dev); 1063 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift)); 1064 1065 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable); 1066 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */ 1067 cpw8(Config3, PARMEnable); 1068 cp->wol_enabled = 0; 1069 1070 cpw8(Config5, cpr8(Config5) & PMEStatus); 1071 1072 cpw16(MultiIntr, 0); 1073 1074 cpw8_f(Cfg9346, Cfg9346_Lock); 1075 } 1076 1077 static int cp_refill_rx(struct cp_private *cp) 1078 { 1079 struct net_device *dev = cp->dev; 1080 unsigned i; 1081 1082 for (i = 0; i < CP_RX_RING_SIZE; i++) { 1083 struct sk_buff *skb; 1084 dma_addr_t mapping; 1085 1086 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz); 1087 if (!skb) 1088 goto err_out; 1089 1090 mapping = dma_map_single(&cp->pdev->dev, skb->data, 1091 cp->rx_buf_sz, PCI_DMA_FROMDEVICE); 1092 if (dma_mapping_error(&cp->pdev->dev, mapping)) { 1093 kfree_skb(skb); 1094 goto err_out; 1095 } 1096 cp->rx_skb[i] = skb; 1097 1098 cp->rx_ring[i].opts2 = 0; 1099 cp->rx_ring[i].addr = cpu_to_le64(mapping); 1100 if (i == (CP_RX_RING_SIZE - 1)) 1101 cp->rx_ring[i].opts1 = 1102 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz); 1103 else 1104 cp->rx_ring[i].opts1 = 1105 cpu_to_le32(DescOwn | cp->rx_buf_sz); 1106 } 1107 1108 return 0; 1109 1110 err_out: 1111 cp_clean_rings(cp); 1112 return -ENOMEM; 1113 } 1114 1115 static void cp_init_rings_index (struct cp_private *cp) 1116 { 1117 cp->rx_tail = 0; 1118 cp->tx_head = cp->tx_tail = 0; 1119 } 1120 1121 static int cp_init_rings (struct cp_private *cp) 1122 { 1123 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); 1124 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd); 1125 1126 cp_init_rings_index(cp); 1127 1128 return cp_refill_rx (cp); 1129 } 1130 1131 static int cp_alloc_rings (struct cp_private *cp) 1132 { 1133 struct device *d = &cp->pdev->dev; 1134 void *mem; 1135 int rc; 1136 1137 mem = dma_alloc_coherent(d, CP_RING_BYTES, &cp->ring_dma, GFP_KERNEL); 1138 if (!mem) 1139 return -ENOMEM; 1140 1141 cp->rx_ring = mem; 1142 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE]; 1143 1144 rc = cp_init_rings(cp); 1145 if (rc < 0) 1146 dma_free_coherent(d, CP_RING_BYTES, cp->rx_ring, cp->ring_dma); 1147 1148 return rc; 1149 } 1150 1151 static void cp_clean_rings (struct cp_private *cp) 1152 { 1153 struct cp_desc *desc; 1154 unsigned i; 1155 1156 for (i = 0; i < CP_RX_RING_SIZE; i++) { 1157 if (cp->rx_skb[i]) { 1158 desc = cp->rx_ring + i; 1159 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr), 1160 cp->rx_buf_sz, PCI_DMA_FROMDEVICE); 1161 dev_kfree_skb(cp->rx_skb[i]); 1162 } 1163 } 1164 1165 for (i = 0; i < CP_TX_RING_SIZE; i++) { 1166 if (cp->tx_skb[i]) { 1167 struct sk_buff *skb = cp->tx_skb[i]; 1168 1169 desc = cp->tx_ring + i; 1170 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr), 1171 le32_to_cpu(desc->opts1) & 0xffff, 1172 PCI_DMA_TODEVICE); 1173 if (le32_to_cpu(desc->opts1) & LastFrag) 1174 dev_kfree_skb(skb); 1175 cp->dev->stats.tx_dropped++; 1176 } 1177 } 1178 netdev_reset_queue(cp->dev); 1179 1180 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE); 1181 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); 1182 1183 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE); 1184 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE); 1185 } 1186 1187 static void cp_free_rings (struct cp_private *cp) 1188 { 1189 cp_clean_rings(cp); 1190 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring, 1191 cp->ring_dma); 1192 cp->rx_ring = NULL; 1193 cp->tx_ring = NULL; 1194 } 1195 1196 static int cp_open (struct net_device *dev) 1197 { 1198 struct cp_private *cp = netdev_priv(dev); 1199 const int irq = cp->pdev->irq; 1200 int rc; 1201 1202 netif_dbg(cp, ifup, dev, "enabling interface\n"); 1203 1204 rc = cp_alloc_rings(cp); 1205 if (rc) 1206 return rc; 1207 1208 napi_enable(&cp->napi); 1209 1210 cp_init_hw(cp); 1211 1212 rc = request_irq(irq, cp_interrupt, IRQF_SHARED, dev->name, dev); 1213 if (rc) 1214 goto err_out_hw; 1215 1216 cp_enable_irq(cp); 1217 1218 netif_carrier_off(dev); 1219 mii_check_media(&cp->mii_if, netif_msg_link(cp), true); 1220 netif_start_queue(dev); 1221 1222 return 0; 1223 1224 err_out_hw: 1225 napi_disable(&cp->napi); 1226 cp_stop_hw(cp); 1227 cp_free_rings(cp); 1228 return rc; 1229 } 1230 1231 static int cp_close (struct net_device *dev) 1232 { 1233 struct cp_private *cp = netdev_priv(dev); 1234 unsigned long flags; 1235 1236 napi_disable(&cp->napi); 1237 1238 netif_dbg(cp, ifdown, dev, "disabling interface\n"); 1239 1240 spin_lock_irqsave(&cp->lock, flags); 1241 1242 netif_stop_queue(dev); 1243 netif_carrier_off(dev); 1244 1245 cp_stop_hw(cp); 1246 1247 spin_unlock_irqrestore(&cp->lock, flags); 1248 1249 free_irq(cp->pdev->irq, dev); 1250 1251 cp_free_rings(cp); 1252 return 0; 1253 } 1254 1255 static void cp_tx_timeout(struct net_device *dev) 1256 { 1257 struct cp_private *cp = netdev_priv(dev); 1258 unsigned long flags; 1259 int rc; 1260 1261 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n", 1262 cpr8(Cmd), cpr16(CpCmd), 1263 cpr16(IntrStatus), cpr16(IntrMask)); 1264 1265 spin_lock_irqsave(&cp->lock, flags); 1266 1267 cp_stop_hw(cp); 1268 cp_clean_rings(cp); 1269 rc = cp_init_rings(cp); 1270 cp_start_hw(cp); 1271 cp_enable_irq(cp); 1272 1273 netif_wake_queue(dev); 1274 1275 spin_unlock_irqrestore(&cp->lock, flags); 1276 } 1277 1278 static int cp_change_mtu(struct net_device *dev, int new_mtu) 1279 { 1280 struct cp_private *cp = netdev_priv(dev); 1281 1282 /* check for invalid MTU, according to hardware limits */ 1283 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU) 1284 return -EINVAL; 1285 1286 /* if network interface not up, no need for complexity */ 1287 if (!netif_running(dev)) { 1288 dev->mtu = new_mtu; 1289 cp_set_rxbufsize(cp); /* set new rx buf size */ 1290 return 0; 1291 } 1292 1293 /* network IS up, close it, reset MTU, and come up again. */ 1294 cp_close(dev); 1295 dev->mtu = new_mtu; 1296 cp_set_rxbufsize(cp); 1297 return cp_open(dev); 1298 } 1299 1300 static const char mii_2_8139_map[8] = { 1301 BasicModeCtrl, 1302 BasicModeStatus, 1303 0, 1304 0, 1305 NWayAdvert, 1306 NWayLPAR, 1307 NWayExpansion, 1308 0 1309 }; 1310 1311 static int mdio_read(struct net_device *dev, int phy_id, int location) 1312 { 1313 struct cp_private *cp = netdev_priv(dev); 1314 1315 return location < 8 && mii_2_8139_map[location] ? 1316 readw(cp->regs + mii_2_8139_map[location]) : 0; 1317 } 1318 1319 1320 static void mdio_write(struct net_device *dev, int phy_id, int location, 1321 int value) 1322 { 1323 struct cp_private *cp = netdev_priv(dev); 1324 1325 if (location == 0) { 1326 cpw8(Cfg9346, Cfg9346_Unlock); 1327 cpw16(BasicModeCtrl, value); 1328 cpw8(Cfg9346, Cfg9346_Lock); 1329 } else if (location < 8 && mii_2_8139_map[location]) 1330 cpw16(mii_2_8139_map[location], value); 1331 } 1332 1333 /* Set the ethtool Wake-on-LAN settings */ 1334 static int netdev_set_wol (struct cp_private *cp, 1335 const struct ethtool_wolinfo *wol) 1336 { 1337 u8 options; 1338 1339 options = cpr8 (Config3) & ~(LinkUp | MagicPacket); 1340 /* If WOL is being disabled, no need for complexity */ 1341 if (wol->wolopts) { 1342 if (wol->wolopts & WAKE_PHY) options |= LinkUp; 1343 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket; 1344 } 1345 1346 cpw8 (Cfg9346, Cfg9346_Unlock); 1347 cpw8 (Config3, options); 1348 cpw8 (Cfg9346, Cfg9346_Lock); 1349 1350 options = 0; /* Paranoia setting */ 1351 options = cpr8 (Config5) & ~(UWF | MWF | BWF); 1352 /* If WOL is being disabled, no need for complexity */ 1353 if (wol->wolopts) { 1354 if (wol->wolopts & WAKE_UCAST) options |= UWF; 1355 if (wol->wolopts & WAKE_BCAST) options |= BWF; 1356 if (wol->wolopts & WAKE_MCAST) options |= MWF; 1357 } 1358 1359 cpw8 (Config5, options); 1360 1361 cp->wol_enabled = (wol->wolopts) ? 1 : 0; 1362 1363 return 0; 1364 } 1365 1366 /* Get the ethtool Wake-on-LAN settings */ 1367 static void netdev_get_wol (struct cp_private *cp, 1368 struct ethtool_wolinfo *wol) 1369 { 1370 u8 options; 1371 1372 wol->wolopts = 0; /* Start from scratch */ 1373 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC | 1374 WAKE_MCAST | WAKE_UCAST; 1375 /* We don't need to go on if WOL is disabled */ 1376 if (!cp->wol_enabled) return; 1377 1378 options = cpr8 (Config3); 1379 if (options & LinkUp) wol->wolopts |= WAKE_PHY; 1380 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC; 1381 1382 options = 0; /* Paranoia setting */ 1383 options = cpr8 (Config5); 1384 if (options & UWF) wol->wolopts |= WAKE_UCAST; 1385 if (options & BWF) wol->wolopts |= WAKE_BCAST; 1386 if (options & MWF) wol->wolopts |= WAKE_MCAST; 1387 } 1388 1389 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info) 1390 { 1391 struct cp_private *cp = netdev_priv(dev); 1392 1393 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1394 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1395 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info)); 1396 } 1397 1398 static void cp_get_ringparam(struct net_device *dev, 1399 struct ethtool_ringparam *ring) 1400 { 1401 ring->rx_max_pending = CP_RX_RING_SIZE; 1402 ring->tx_max_pending = CP_TX_RING_SIZE; 1403 ring->rx_pending = CP_RX_RING_SIZE; 1404 ring->tx_pending = CP_TX_RING_SIZE; 1405 } 1406 1407 static int cp_get_regs_len(struct net_device *dev) 1408 { 1409 return CP_REGS_SIZE; 1410 } 1411 1412 static int cp_get_sset_count (struct net_device *dev, int sset) 1413 { 1414 switch (sset) { 1415 case ETH_SS_STATS: 1416 return CP_NUM_STATS; 1417 default: 1418 return -EOPNOTSUPP; 1419 } 1420 } 1421 1422 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1423 { 1424 struct cp_private *cp = netdev_priv(dev); 1425 int rc; 1426 unsigned long flags; 1427 1428 spin_lock_irqsave(&cp->lock, flags); 1429 rc = mii_ethtool_gset(&cp->mii_if, cmd); 1430 spin_unlock_irqrestore(&cp->lock, flags); 1431 1432 return rc; 1433 } 1434 1435 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1436 { 1437 struct cp_private *cp = netdev_priv(dev); 1438 int rc; 1439 unsigned long flags; 1440 1441 spin_lock_irqsave(&cp->lock, flags); 1442 rc = mii_ethtool_sset(&cp->mii_if, cmd); 1443 spin_unlock_irqrestore(&cp->lock, flags); 1444 1445 return rc; 1446 } 1447 1448 static int cp_nway_reset(struct net_device *dev) 1449 { 1450 struct cp_private *cp = netdev_priv(dev); 1451 return mii_nway_restart(&cp->mii_if); 1452 } 1453 1454 static u32 cp_get_msglevel(struct net_device *dev) 1455 { 1456 struct cp_private *cp = netdev_priv(dev); 1457 return cp->msg_enable; 1458 } 1459 1460 static void cp_set_msglevel(struct net_device *dev, u32 value) 1461 { 1462 struct cp_private *cp = netdev_priv(dev); 1463 cp->msg_enable = value; 1464 } 1465 1466 static int cp_set_features(struct net_device *dev, netdev_features_t features) 1467 { 1468 struct cp_private *cp = netdev_priv(dev); 1469 unsigned long flags; 1470 1471 if (!((dev->features ^ features) & NETIF_F_RXCSUM)) 1472 return 0; 1473 1474 spin_lock_irqsave(&cp->lock, flags); 1475 1476 if (features & NETIF_F_RXCSUM) 1477 cp->cpcmd |= RxChkSum; 1478 else 1479 cp->cpcmd &= ~RxChkSum; 1480 1481 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1482 cp->cpcmd |= RxVlanOn; 1483 else 1484 cp->cpcmd &= ~RxVlanOn; 1485 1486 cpw16_f(CpCmd, cp->cpcmd); 1487 spin_unlock_irqrestore(&cp->lock, flags); 1488 1489 return 0; 1490 } 1491 1492 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1493 void *p) 1494 { 1495 struct cp_private *cp = netdev_priv(dev); 1496 unsigned long flags; 1497 1498 if (regs->len < CP_REGS_SIZE) 1499 return /* -EINVAL */; 1500 1501 regs->version = CP_REGS_VER; 1502 1503 spin_lock_irqsave(&cp->lock, flags); 1504 memcpy_fromio(p, cp->regs, CP_REGS_SIZE); 1505 spin_unlock_irqrestore(&cp->lock, flags); 1506 } 1507 1508 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol) 1509 { 1510 struct cp_private *cp = netdev_priv(dev); 1511 unsigned long flags; 1512 1513 spin_lock_irqsave (&cp->lock, flags); 1514 netdev_get_wol (cp, wol); 1515 spin_unlock_irqrestore (&cp->lock, flags); 1516 } 1517 1518 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol) 1519 { 1520 struct cp_private *cp = netdev_priv(dev); 1521 unsigned long flags; 1522 int rc; 1523 1524 spin_lock_irqsave (&cp->lock, flags); 1525 rc = netdev_set_wol (cp, wol); 1526 spin_unlock_irqrestore (&cp->lock, flags); 1527 1528 return rc; 1529 } 1530 1531 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf) 1532 { 1533 switch (stringset) { 1534 case ETH_SS_STATS: 1535 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); 1536 break; 1537 default: 1538 BUG(); 1539 break; 1540 } 1541 } 1542 1543 static void cp_get_ethtool_stats (struct net_device *dev, 1544 struct ethtool_stats *estats, u64 *tmp_stats) 1545 { 1546 struct cp_private *cp = netdev_priv(dev); 1547 struct cp_dma_stats *nic_stats; 1548 dma_addr_t dma; 1549 int i; 1550 1551 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats), 1552 &dma, GFP_KERNEL); 1553 if (!nic_stats) 1554 return; 1555 1556 /* begin NIC statistics dump */ 1557 cpw32(StatsAddr + 4, (u64)dma >> 32); 1558 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats); 1559 cpr32(StatsAddr); 1560 1561 for (i = 0; i < 1000; i++) { 1562 if ((cpr32(StatsAddr) & DumpStats) == 0) 1563 break; 1564 udelay(10); 1565 } 1566 cpw32(StatsAddr, 0); 1567 cpw32(StatsAddr + 4, 0); 1568 cpr32(StatsAddr); 1569 1570 i = 0; 1571 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok); 1572 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok); 1573 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err); 1574 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err); 1575 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo); 1576 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align); 1577 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col); 1578 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol); 1579 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys); 1580 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast); 1581 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast); 1582 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort); 1583 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun); 1584 tmp_stats[i++] = cp->cp_stats.rx_frags; 1585 BUG_ON(i != CP_NUM_STATS); 1586 1587 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma); 1588 } 1589 1590 static const struct ethtool_ops cp_ethtool_ops = { 1591 .get_drvinfo = cp_get_drvinfo, 1592 .get_regs_len = cp_get_regs_len, 1593 .get_sset_count = cp_get_sset_count, 1594 .get_settings = cp_get_settings, 1595 .set_settings = cp_set_settings, 1596 .nway_reset = cp_nway_reset, 1597 .get_link = ethtool_op_get_link, 1598 .get_msglevel = cp_get_msglevel, 1599 .set_msglevel = cp_set_msglevel, 1600 .get_regs = cp_get_regs, 1601 .get_wol = cp_get_wol, 1602 .set_wol = cp_set_wol, 1603 .get_strings = cp_get_strings, 1604 .get_ethtool_stats = cp_get_ethtool_stats, 1605 .get_eeprom_len = cp_get_eeprom_len, 1606 .get_eeprom = cp_get_eeprom, 1607 .set_eeprom = cp_set_eeprom, 1608 .get_ringparam = cp_get_ringparam, 1609 }; 1610 1611 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) 1612 { 1613 struct cp_private *cp = netdev_priv(dev); 1614 int rc; 1615 unsigned long flags; 1616 1617 if (!netif_running(dev)) 1618 return -EINVAL; 1619 1620 spin_lock_irqsave(&cp->lock, flags); 1621 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL); 1622 spin_unlock_irqrestore(&cp->lock, flags); 1623 return rc; 1624 } 1625 1626 static int cp_set_mac_address(struct net_device *dev, void *p) 1627 { 1628 struct cp_private *cp = netdev_priv(dev); 1629 struct sockaddr *addr = p; 1630 1631 if (!is_valid_ether_addr(addr->sa_data)) 1632 return -EADDRNOTAVAIL; 1633 1634 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1635 1636 spin_lock_irq(&cp->lock); 1637 1638 cpw8_f(Cfg9346, Cfg9346_Unlock); 1639 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); 1640 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4))); 1641 cpw8_f(Cfg9346, Cfg9346_Lock); 1642 1643 spin_unlock_irq(&cp->lock); 1644 1645 return 0; 1646 } 1647 1648 /* Serial EEPROM section. */ 1649 1650 /* EEPROM_Ctrl bits. */ 1651 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 1652 #define EE_CS 0x08 /* EEPROM chip select. */ 1653 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 1654 #define EE_WRITE_0 0x00 1655 #define EE_WRITE_1 0x02 1656 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 1657 #define EE_ENB (0x80 | EE_CS) 1658 1659 /* Delay between EEPROM clock transitions. 1660 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 1661 */ 1662 1663 #define eeprom_delay() readb(ee_addr) 1664 1665 /* The EEPROM commands include the alway-set leading bit. */ 1666 #define EE_EXTEND_CMD (4) 1667 #define EE_WRITE_CMD (5) 1668 #define EE_READ_CMD (6) 1669 #define EE_ERASE_CMD (7) 1670 1671 #define EE_EWDS_ADDR (0) 1672 #define EE_WRAL_ADDR (1) 1673 #define EE_ERAL_ADDR (2) 1674 #define EE_EWEN_ADDR (3) 1675 1676 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139 1677 1678 static void eeprom_cmd_start(void __iomem *ee_addr) 1679 { 1680 writeb (EE_ENB & ~EE_CS, ee_addr); 1681 writeb (EE_ENB, ee_addr); 1682 eeprom_delay (); 1683 } 1684 1685 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len) 1686 { 1687 int i; 1688 1689 /* Shift the command bits out. */ 1690 for (i = cmd_len - 1; i >= 0; i--) { 1691 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0; 1692 writeb (EE_ENB | dataval, ee_addr); 1693 eeprom_delay (); 1694 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 1695 eeprom_delay (); 1696 } 1697 writeb (EE_ENB, ee_addr); 1698 eeprom_delay (); 1699 } 1700 1701 static void eeprom_cmd_end(void __iomem *ee_addr) 1702 { 1703 writeb(0, ee_addr); 1704 eeprom_delay (); 1705 } 1706 1707 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd, 1708 int addr_len) 1709 { 1710 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2)); 1711 1712 eeprom_cmd_start(ee_addr); 1713 eeprom_cmd(ee_addr, cmd, 3 + addr_len); 1714 eeprom_cmd_end(ee_addr); 1715 } 1716 1717 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len) 1718 { 1719 int i; 1720 u16 retval = 0; 1721 void __iomem *ee_addr = ioaddr + Cfg9346; 1722 int read_cmd = location | (EE_READ_CMD << addr_len); 1723 1724 eeprom_cmd_start(ee_addr); 1725 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len); 1726 1727 for (i = 16; i > 0; i--) { 1728 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr); 1729 eeprom_delay (); 1730 retval = 1731 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 : 1732 0); 1733 writeb (EE_ENB, ee_addr); 1734 eeprom_delay (); 1735 } 1736 1737 eeprom_cmd_end(ee_addr); 1738 1739 return retval; 1740 } 1741 1742 static void write_eeprom(void __iomem *ioaddr, int location, u16 val, 1743 int addr_len) 1744 { 1745 int i; 1746 void __iomem *ee_addr = ioaddr + Cfg9346; 1747 int write_cmd = location | (EE_WRITE_CMD << addr_len); 1748 1749 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len); 1750 1751 eeprom_cmd_start(ee_addr); 1752 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len); 1753 eeprom_cmd(ee_addr, val, 16); 1754 eeprom_cmd_end(ee_addr); 1755 1756 eeprom_cmd_start(ee_addr); 1757 for (i = 0; i < 20000; i++) 1758 if (readb(ee_addr) & EE_DATA_READ) 1759 break; 1760 eeprom_cmd_end(ee_addr); 1761 1762 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len); 1763 } 1764 1765 static int cp_get_eeprom_len(struct net_device *dev) 1766 { 1767 struct cp_private *cp = netdev_priv(dev); 1768 int size; 1769 1770 spin_lock_irq(&cp->lock); 1771 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128; 1772 spin_unlock_irq(&cp->lock); 1773 1774 return size; 1775 } 1776 1777 static int cp_get_eeprom(struct net_device *dev, 1778 struct ethtool_eeprom *eeprom, u8 *data) 1779 { 1780 struct cp_private *cp = netdev_priv(dev); 1781 unsigned int addr_len; 1782 u16 val; 1783 u32 offset = eeprom->offset >> 1; 1784 u32 len = eeprom->len; 1785 u32 i = 0; 1786 1787 eeprom->magic = CP_EEPROM_MAGIC; 1788 1789 spin_lock_irq(&cp->lock); 1790 1791 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6; 1792 1793 if (eeprom->offset & 1) { 1794 val = read_eeprom(cp->regs, offset, addr_len); 1795 data[i++] = (u8)(val >> 8); 1796 offset++; 1797 } 1798 1799 while (i < len - 1) { 1800 val = read_eeprom(cp->regs, offset, addr_len); 1801 data[i++] = (u8)val; 1802 data[i++] = (u8)(val >> 8); 1803 offset++; 1804 } 1805 1806 if (i < len) { 1807 val = read_eeprom(cp->regs, offset, addr_len); 1808 data[i] = (u8)val; 1809 } 1810 1811 spin_unlock_irq(&cp->lock); 1812 return 0; 1813 } 1814 1815 static int cp_set_eeprom(struct net_device *dev, 1816 struct ethtool_eeprom *eeprom, u8 *data) 1817 { 1818 struct cp_private *cp = netdev_priv(dev); 1819 unsigned int addr_len; 1820 u16 val; 1821 u32 offset = eeprom->offset >> 1; 1822 u32 len = eeprom->len; 1823 u32 i = 0; 1824 1825 if (eeprom->magic != CP_EEPROM_MAGIC) 1826 return -EINVAL; 1827 1828 spin_lock_irq(&cp->lock); 1829 1830 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6; 1831 1832 if (eeprom->offset & 1) { 1833 val = read_eeprom(cp->regs, offset, addr_len) & 0xff; 1834 val |= (u16)data[i++] << 8; 1835 write_eeprom(cp->regs, offset, val, addr_len); 1836 offset++; 1837 } 1838 1839 while (i < len - 1) { 1840 val = (u16)data[i++]; 1841 val |= (u16)data[i++] << 8; 1842 write_eeprom(cp->regs, offset, val, addr_len); 1843 offset++; 1844 } 1845 1846 if (i < len) { 1847 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00; 1848 val |= (u16)data[i]; 1849 write_eeprom(cp->regs, offset, val, addr_len); 1850 } 1851 1852 spin_unlock_irq(&cp->lock); 1853 return 0; 1854 } 1855 1856 /* Put the board into D3cold state and wait for WakeUp signal */ 1857 static void cp_set_d3_state (struct cp_private *cp) 1858 { 1859 pci_enable_wake(cp->pdev, PCI_D0, 1); /* Enable PME# generation */ 1860 pci_set_power_state (cp->pdev, PCI_D3hot); 1861 } 1862 1863 static const struct net_device_ops cp_netdev_ops = { 1864 .ndo_open = cp_open, 1865 .ndo_stop = cp_close, 1866 .ndo_validate_addr = eth_validate_addr, 1867 .ndo_set_mac_address = cp_set_mac_address, 1868 .ndo_set_rx_mode = cp_set_rx_mode, 1869 .ndo_get_stats = cp_get_stats, 1870 .ndo_do_ioctl = cp_ioctl, 1871 .ndo_start_xmit = cp_start_xmit, 1872 .ndo_tx_timeout = cp_tx_timeout, 1873 .ndo_set_features = cp_set_features, 1874 .ndo_change_mtu = cp_change_mtu, 1875 1876 #ifdef CONFIG_NET_POLL_CONTROLLER 1877 .ndo_poll_controller = cp_poll_controller, 1878 #endif 1879 }; 1880 1881 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1882 { 1883 struct net_device *dev; 1884 struct cp_private *cp; 1885 int rc; 1886 void __iomem *regs; 1887 resource_size_t pciaddr; 1888 unsigned int addr_len, i, pci_using_dac; 1889 1890 #ifndef MODULE 1891 static int version_printed; 1892 if (version_printed++ == 0) 1893 pr_info("%s", version); 1894 #endif 1895 1896 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 1897 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) { 1898 dev_info(&pdev->dev, 1899 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n", 1900 pdev->vendor, pdev->device, pdev->revision); 1901 return -ENODEV; 1902 } 1903 1904 dev = alloc_etherdev(sizeof(struct cp_private)); 1905 if (!dev) 1906 return -ENOMEM; 1907 SET_NETDEV_DEV(dev, &pdev->dev); 1908 1909 cp = netdev_priv(dev); 1910 cp->pdev = pdev; 1911 cp->dev = dev; 1912 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug); 1913 spin_lock_init (&cp->lock); 1914 cp->mii_if.dev = dev; 1915 cp->mii_if.mdio_read = mdio_read; 1916 cp->mii_if.mdio_write = mdio_write; 1917 cp->mii_if.phy_id = CP_INTERNAL_PHY; 1918 cp->mii_if.phy_id_mask = 0x1f; 1919 cp->mii_if.reg_num_mask = 0x1f; 1920 cp_set_rxbufsize(cp); 1921 1922 rc = pci_enable_device(pdev); 1923 if (rc) 1924 goto err_out_free; 1925 1926 rc = pci_set_mwi(pdev); 1927 if (rc) 1928 goto err_out_disable; 1929 1930 rc = pci_request_regions(pdev, DRV_NAME); 1931 if (rc) 1932 goto err_out_mwi; 1933 1934 pciaddr = pci_resource_start(pdev, 1); 1935 if (!pciaddr) { 1936 rc = -EIO; 1937 dev_err(&pdev->dev, "no MMIO resource\n"); 1938 goto err_out_res; 1939 } 1940 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) { 1941 rc = -EIO; 1942 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n", 1943 (unsigned long long)pci_resource_len(pdev, 1)); 1944 goto err_out_res; 1945 } 1946 1947 /* Configure DMA attributes. */ 1948 if ((sizeof(dma_addr_t) > 4) && 1949 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) && 1950 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 1951 pci_using_dac = 1; 1952 } else { 1953 pci_using_dac = 0; 1954 1955 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1956 if (rc) { 1957 dev_err(&pdev->dev, 1958 "No usable DMA configuration, aborting\n"); 1959 goto err_out_res; 1960 } 1961 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1962 if (rc) { 1963 dev_err(&pdev->dev, 1964 "No usable consistent DMA configuration, aborting\n"); 1965 goto err_out_res; 1966 } 1967 } 1968 1969 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) | 1970 PCIMulRW | RxChkSum | CpRxOn | CpTxOn; 1971 1972 dev->features |= NETIF_F_RXCSUM; 1973 dev->hw_features |= NETIF_F_RXCSUM; 1974 1975 regs = ioremap(pciaddr, CP_REGS_SIZE); 1976 if (!regs) { 1977 rc = -EIO; 1978 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n", 1979 (unsigned long long)pci_resource_len(pdev, 1), 1980 (unsigned long long)pciaddr); 1981 goto err_out_res; 1982 } 1983 cp->regs = regs; 1984 1985 cp_stop_hw(cp); 1986 1987 /* read MAC address from EEPROM */ 1988 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6; 1989 for (i = 0; i < 3; i++) 1990 ((__le16 *) (dev->dev_addr))[i] = 1991 cpu_to_le16(read_eeprom (regs, i + 7, addr_len)); 1992 1993 dev->netdev_ops = &cp_netdev_ops; 1994 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16); 1995 dev->ethtool_ops = &cp_ethtool_ops; 1996 dev->watchdog_timeo = TX_TIMEOUT; 1997 1998 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 1999 2000 if (pci_using_dac) 2001 dev->features |= NETIF_F_HIGHDMA; 2002 2003 /* disabled by default until verified */ 2004 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 2005 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 2006 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 2007 NETIF_F_HIGHDMA; 2008 2009 rc = register_netdev(dev); 2010 if (rc) 2011 goto err_out_iomap; 2012 2013 netdev_info(dev, "RTL-8139C+ at 0x%p, %pM, IRQ %d\n", 2014 regs, dev->dev_addr, pdev->irq); 2015 2016 pci_set_drvdata(pdev, dev); 2017 2018 /* enable busmastering and memory-write-invalidate */ 2019 pci_set_master(pdev); 2020 2021 if (cp->wol_enabled) 2022 cp_set_d3_state (cp); 2023 2024 return 0; 2025 2026 err_out_iomap: 2027 iounmap(regs); 2028 err_out_res: 2029 pci_release_regions(pdev); 2030 err_out_mwi: 2031 pci_clear_mwi(pdev); 2032 err_out_disable: 2033 pci_disable_device(pdev); 2034 err_out_free: 2035 free_netdev(dev); 2036 return rc; 2037 } 2038 2039 static void cp_remove_one (struct pci_dev *pdev) 2040 { 2041 struct net_device *dev = pci_get_drvdata(pdev); 2042 struct cp_private *cp = netdev_priv(dev); 2043 2044 unregister_netdev(dev); 2045 iounmap(cp->regs); 2046 if (cp->wol_enabled) 2047 pci_set_power_state (pdev, PCI_D0); 2048 pci_release_regions(pdev); 2049 pci_clear_mwi(pdev); 2050 pci_disable_device(pdev); 2051 free_netdev(dev); 2052 } 2053 2054 #ifdef CONFIG_PM 2055 static int cp_suspend (struct pci_dev *pdev, pm_message_t state) 2056 { 2057 struct net_device *dev = pci_get_drvdata(pdev); 2058 struct cp_private *cp = netdev_priv(dev); 2059 unsigned long flags; 2060 2061 if (!netif_running(dev)) 2062 return 0; 2063 2064 netif_device_detach (dev); 2065 netif_stop_queue (dev); 2066 2067 spin_lock_irqsave (&cp->lock, flags); 2068 2069 /* Disable Rx and Tx */ 2070 cpw16 (IntrMask, 0); 2071 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn)); 2072 2073 spin_unlock_irqrestore (&cp->lock, flags); 2074 2075 pci_save_state(pdev); 2076 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled); 2077 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 2078 2079 return 0; 2080 } 2081 2082 static int cp_resume (struct pci_dev *pdev) 2083 { 2084 struct net_device *dev = pci_get_drvdata (pdev); 2085 struct cp_private *cp = netdev_priv(dev); 2086 unsigned long flags; 2087 2088 if (!netif_running(dev)) 2089 return 0; 2090 2091 netif_device_attach (dev); 2092 2093 pci_set_power_state(pdev, PCI_D0); 2094 pci_restore_state(pdev); 2095 pci_enable_wake(pdev, PCI_D0, 0); 2096 2097 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */ 2098 cp_init_rings_index (cp); 2099 cp_init_hw (cp); 2100 cp_enable_irq(cp); 2101 netif_start_queue (dev); 2102 2103 spin_lock_irqsave (&cp->lock, flags); 2104 2105 mii_check_media(&cp->mii_if, netif_msg_link(cp), false); 2106 2107 spin_unlock_irqrestore (&cp->lock, flags); 2108 2109 return 0; 2110 } 2111 #endif /* CONFIG_PM */ 2112 2113 static struct pci_driver cp_driver = { 2114 .name = DRV_NAME, 2115 .id_table = cp_pci_tbl, 2116 .probe = cp_init_one, 2117 .remove = cp_remove_one, 2118 #ifdef CONFIG_PM 2119 .resume = cp_resume, 2120 .suspend = cp_suspend, 2121 #endif 2122 }; 2123 2124 static int __init cp_init (void) 2125 { 2126 #ifdef MODULE 2127 pr_info("%s", version); 2128 #endif 2129 return pci_register_driver(&cp_driver); 2130 } 2131 2132 static void __exit cp_exit (void) 2133 { 2134 pci_unregister_driver (&cp_driver); 2135 } 2136 2137 module_init(cp_init); 2138 module_exit(cp_exit); 2139