1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef _EMAC_H_ 14 #define _EMAC_H_ 15 16 #include <linux/irqreturn.h> 17 #include <linux/netdevice.h> 18 #include <linux/clk.h> 19 #include <linux/platform_device.h> 20 #include "emac-mac.h" 21 #include "emac-phy.h" 22 #include "emac-sgmii.h" 23 24 /* EMAC base register offsets */ 25 #define EMAC_DMA_MAS_CTRL 0x1400 26 #define EMAC_IRQ_MOD_TIM_INIT 0x1408 27 #define EMAC_BLK_IDLE_STS 0x140c 28 #define EMAC_PHY_LINK_DELAY 0x141c 29 #define EMAC_SYS_ALIV_CTRL 0x1434 30 #define EMAC_MAC_CTRL 0x1480 31 #define EMAC_MAC_IPGIFG_CTRL 0x1484 32 #define EMAC_MAC_STA_ADDR0 0x1488 33 #define EMAC_MAC_STA_ADDR1 0x148c 34 #define EMAC_HASH_TAB_REG0 0x1490 35 #define EMAC_HASH_TAB_REG1 0x1494 36 #define EMAC_MAC_HALF_DPLX_CTRL 0x1498 37 #define EMAC_MAX_FRAM_LEN_CTRL 0x149c 38 #define EMAC_WOL_CTRL0 0x14a0 39 #define EMAC_RSS_KEY0 0x14b0 40 #define EMAC_H1TPD_BASE_ADDR_LO 0x14e0 41 #define EMAC_H2TPD_BASE_ADDR_LO 0x14e4 42 #define EMAC_H3TPD_BASE_ADDR_LO 0x14e8 43 #define EMAC_INTER_SRAM_PART9 0x1534 44 #define EMAC_DESC_CTRL_0 0x1540 45 #define EMAC_DESC_CTRL_1 0x1544 46 #define EMAC_DESC_CTRL_2 0x1550 47 #define EMAC_DESC_CTRL_10 0x1554 48 #define EMAC_DESC_CTRL_12 0x1558 49 #define EMAC_DESC_CTRL_13 0x155c 50 #define EMAC_DESC_CTRL_3 0x1560 51 #define EMAC_DESC_CTRL_4 0x1564 52 #define EMAC_DESC_CTRL_5 0x1568 53 #define EMAC_DESC_CTRL_14 0x156c 54 #define EMAC_DESC_CTRL_15 0x1570 55 #define EMAC_DESC_CTRL_16 0x1574 56 #define EMAC_DESC_CTRL_6 0x1578 57 #define EMAC_DESC_CTRL_8 0x1580 58 #define EMAC_DESC_CTRL_9 0x1584 59 #define EMAC_DESC_CTRL_11 0x1588 60 #define EMAC_TXQ_CTRL_0 0x1590 61 #define EMAC_TXQ_CTRL_1 0x1594 62 #define EMAC_TXQ_CTRL_2 0x1598 63 #define EMAC_RXQ_CTRL_0 0x15a0 64 #define EMAC_RXQ_CTRL_1 0x15a4 65 #define EMAC_RXQ_CTRL_2 0x15a8 66 #define EMAC_RXQ_CTRL_3 0x15ac 67 #define EMAC_BASE_CPU_NUMBER 0x15b8 68 #define EMAC_DMA_CTRL 0x15c0 69 #define EMAC_MAILBOX_0 0x15e0 70 #define EMAC_MAILBOX_5 0x15e4 71 #define EMAC_MAILBOX_6 0x15e8 72 #define EMAC_MAILBOX_13 0x15ec 73 #define EMAC_MAILBOX_2 0x15f4 74 #define EMAC_MAILBOX_3 0x15f8 75 #define EMAC_INT_STATUS 0x1600 76 #define EMAC_INT_MASK 0x1604 77 #define EMAC_MAILBOX_11 0x160c 78 #define EMAC_AXI_MAST_CTRL 0x1610 79 #define EMAC_MAILBOX_12 0x1614 80 #define EMAC_MAILBOX_9 0x1618 81 #define EMAC_MAILBOX_10 0x161c 82 #define EMAC_ATHR_HEADER_CTRL 0x1620 83 #define EMAC_RXMAC_STATC_REG0 0x1700 84 #define EMAC_RXMAC_STATC_REG22 0x1758 85 #define EMAC_TXMAC_STATC_REG0 0x1760 86 #define EMAC_TXMAC_STATC_REG24 0x17c0 87 #define EMAC_CLK_GATE_CTRL 0x1814 88 #define EMAC_CORE_HW_VERSION 0x1974 89 #define EMAC_MISC_CTRL 0x1990 90 #define EMAC_MAILBOX_7 0x19e0 91 #define EMAC_MAILBOX_8 0x19e4 92 #define EMAC_IDT_TABLE0 0x1b00 93 #define EMAC_RXMAC_STATC_REG23 0x1bc8 94 #define EMAC_RXMAC_STATC_REG24 0x1bcc 95 #define EMAC_TXMAC_STATC_REG25 0x1bd0 96 #define EMAC_MAILBOX_15 0x1bd4 97 #define EMAC_MAILBOX_16 0x1bd8 98 #define EMAC_INT1_MASK 0x1bf0 99 #define EMAC_INT1_STATUS 0x1bf4 100 #define EMAC_INT2_MASK 0x1bf8 101 #define EMAC_INT2_STATUS 0x1bfc 102 #define EMAC_INT3_MASK 0x1c00 103 #define EMAC_INT3_STATUS 0x1c04 104 105 /* EMAC_DMA_MAS_CTRL */ 106 #define DEV_ID_NUM_BMSK 0x7f000000 107 #define DEV_ID_NUM_SHFT 24 108 #define DEV_REV_NUM_BMSK 0xff0000 109 #define DEV_REV_NUM_SHFT 16 110 #define INT_RD_CLR_EN 0x4000 111 #define IRQ_MODERATOR2_EN 0x800 112 #define IRQ_MODERATOR_EN 0x400 113 #define LPW_CLK_SEL 0x80 114 #define LPW_STATE 0x20 115 #define LPW_MODE 0x10 116 #define SOFT_RST 0x1 117 118 /* EMAC_IRQ_MOD_TIM_INIT */ 119 #define IRQ_MODERATOR2_INIT_BMSK 0xffff0000 120 #define IRQ_MODERATOR2_INIT_SHFT 16 121 #define IRQ_MODERATOR_INIT_BMSK 0xffff 122 #define IRQ_MODERATOR_INIT_SHFT 0 123 124 /* EMAC_INT_STATUS */ 125 #define DIS_INT BIT(31) 126 #define PTP_INT BIT(30) 127 #define RFD4_UR_INT BIT(29) 128 #define TX_PKT_INT3 BIT(26) 129 #define TX_PKT_INT2 BIT(25) 130 #define TX_PKT_INT1 BIT(24) 131 #define RX_PKT_INT3 BIT(19) 132 #define RX_PKT_INT2 BIT(18) 133 #define RX_PKT_INT1 BIT(17) 134 #define RX_PKT_INT0 BIT(16) 135 #define TX_PKT_INT BIT(15) 136 #define TXQ_TO_INT BIT(14) 137 #define GPHY_WAKEUP_INT BIT(13) 138 #define GPHY_LINK_DOWN_INT BIT(12) 139 #define GPHY_LINK_UP_INT BIT(11) 140 #define DMAW_TO_INT BIT(10) 141 #define DMAR_TO_INT BIT(9) 142 #define TXF_UR_INT BIT(8) 143 #define RFD3_UR_INT BIT(7) 144 #define RFD2_UR_INT BIT(6) 145 #define RFD1_UR_INT BIT(5) 146 #define RFD0_UR_INT BIT(4) 147 #define RXF_OF_INT BIT(3) 148 #define SW_MAN_INT BIT(2) 149 150 /* EMAC_MAILBOX_6 */ 151 #define RFD2_PROC_IDX_BMSK 0xfff0000 152 #define RFD2_PROC_IDX_SHFT 16 153 #define RFD2_PROD_IDX_BMSK 0xfff 154 #define RFD2_PROD_IDX_SHFT 0 155 156 /* EMAC_CORE_HW_VERSION */ 157 #define MAJOR_BMSK 0xf0000000 158 #define MAJOR_SHFT 28 159 #define MINOR_BMSK 0xfff0000 160 #define MINOR_SHFT 16 161 #define STEP_BMSK 0xffff 162 #define STEP_SHFT 0 163 164 /* EMAC_EMAC_WRAPPER_CSR1 */ 165 #define TX_INDX_FIFO_SYNC_RST BIT(23) 166 #define TX_TS_FIFO_SYNC_RST BIT(22) 167 #define RX_TS_FIFO2_SYNC_RST BIT(21) 168 #define RX_TS_FIFO1_SYNC_RST BIT(20) 169 #define TX_TS_ENABLE BIT(16) 170 #define DIS_1588_CLKS BIT(11) 171 #define FREQ_MODE BIT(9) 172 #define ENABLE_RRD_TIMESTAMP BIT(3) 173 174 /* EMAC_EMAC_WRAPPER_CSR2 */ 175 #define HDRIVE_BMSK 0x3000 176 #define HDRIVE_SHFT 12 177 #define SLB_EN BIT(9) 178 #define PLB_EN BIT(8) 179 #define WOL_EN BIT(3) 180 #define PHY_RESET BIT(0) 181 182 #define EMAC_DEV_ID 0x0040 183 184 /* SGMII v2 per lane registers */ 185 #define SGMII_LN_RSM_START 0x029C 186 187 /* SGMII v2 PHY common registers */ 188 #define SGMII_PHY_CMN_CTRL 0x0408 189 #define SGMII_PHY_CMN_RESET_CTRL 0x0410 190 191 /* SGMII v2 PHY registers per lane */ 192 #define SGMII_PHY_LN_OFFSET 0x0400 193 #define SGMII_PHY_LN_LANE_STATUS 0x00DC 194 #define SGMII_PHY_LN_BIST_GEN0 0x008C 195 #define SGMII_PHY_LN_BIST_GEN1 0x0090 196 #define SGMII_PHY_LN_BIST_GEN2 0x0094 197 #define SGMII_PHY_LN_BIST_GEN3 0x0098 198 #define SGMII_PHY_LN_CDR_CTRL1 0x005C 199 200 enum emac_clk_id { 201 EMAC_CLK_AXI, 202 EMAC_CLK_CFG_AHB, 203 EMAC_CLK_HIGH_SPEED, 204 EMAC_CLK_MDIO, 205 EMAC_CLK_TX, 206 EMAC_CLK_RX, 207 EMAC_CLK_SYS, 208 EMAC_CLK_CNT 209 }; 210 211 #define EMAC_LINK_SPEED_UNKNOWN 0x0 212 #define EMAC_LINK_SPEED_10_HALF BIT(0) 213 #define EMAC_LINK_SPEED_10_FULL BIT(1) 214 #define EMAC_LINK_SPEED_100_HALF BIT(2) 215 #define EMAC_LINK_SPEED_100_FULL BIT(3) 216 #define EMAC_LINK_SPEED_1GB_FULL BIT(5) 217 218 #define EMAC_MAX_SETUP_LNK_CYCLE 100 219 220 struct emac_stats { 221 /* rx */ 222 u64 rx_ok; /* good packets */ 223 u64 rx_bcast; /* good broadcast packets */ 224 u64 rx_mcast; /* good multicast packets */ 225 u64 rx_pause; /* pause packet */ 226 u64 rx_ctrl; /* control packets other than pause frame. */ 227 u64 rx_fcs_err; /* packets with bad FCS. */ 228 u64 rx_len_err; /* packets with length mismatch */ 229 u64 rx_byte_cnt; /* good bytes count (without FCS) */ 230 u64 rx_runt; /* runt packets */ 231 u64 rx_frag; /* fragment count */ 232 u64 rx_sz_64; /* packets that are 64 bytes */ 233 u64 rx_sz_65_127; /* packets that are 65-127 bytes */ 234 u64 rx_sz_128_255; /* packets that are 128-255 bytes */ 235 u64 rx_sz_256_511; /* packets that are 256-511 bytes */ 236 u64 rx_sz_512_1023; /* packets that are 512-1023 bytes */ 237 u64 rx_sz_1024_1518; /* packets that are 1024-1518 bytes */ 238 u64 rx_sz_1519_max; /* packets that are 1519-MTU bytes*/ 239 u64 rx_sz_ov; /* packets that are >MTU bytes (truncated) */ 240 u64 rx_rxf_ov; /* packets dropped due to RX FIFO overflow */ 241 u64 rx_align_err; /* alignment errors */ 242 u64 rx_bcast_byte_cnt; /* broadcast packets byte count (without FCS) */ 243 u64 rx_mcast_byte_cnt; /* multicast packets byte count (without FCS) */ 244 u64 rx_err_addr; /* packets dropped due to address filtering */ 245 u64 rx_crc_align; /* CRC align errors */ 246 u64 rx_jabbers; /* jabbers */ 247 248 /* tx */ 249 u64 tx_ok; /* good packets */ 250 u64 tx_bcast; /* good broadcast packets */ 251 u64 tx_mcast; /* good multicast packets */ 252 u64 tx_pause; /* pause packets */ 253 u64 tx_exc_defer; /* packets with excessive deferral */ 254 u64 tx_ctrl; /* control packets other than pause frame */ 255 u64 tx_defer; /* packets that are deferred. */ 256 u64 tx_byte_cnt; /* good bytes count (without FCS) */ 257 u64 tx_sz_64; /* packets that are 64 bytes */ 258 u64 tx_sz_65_127; /* packets that are 65-127 bytes */ 259 u64 tx_sz_128_255; /* packets that are 128-255 bytes */ 260 u64 tx_sz_256_511; /* packets that are 256-511 bytes */ 261 u64 tx_sz_512_1023; /* packets that are 512-1023 bytes */ 262 u64 tx_sz_1024_1518; /* packets that are 1024-1518 bytes */ 263 u64 tx_sz_1519_max; /* packets that are 1519-MTU bytes */ 264 u64 tx_1_col; /* packets single prior collision */ 265 u64 tx_2_col; /* packets with multiple prior collisions */ 266 u64 tx_late_col; /* packets with late collisions */ 267 u64 tx_abort_col; /* packets aborted due to excess collisions */ 268 u64 tx_underrun; /* packets aborted due to FIFO underrun */ 269 u64 tx_rd_eop; /* count of reads beyond EOP */ 270 u64 tx_len_err; /* packets with length mismatch */ 271 u64 tx_trunc; /* packets truncated due to size >MTU */ 272 u64 tx_bcast_byte; /* broadcast packets byte count (without FCS) */ 273 u64 tx_mcast_byte; /* multicast packets byte count (without FCS) */ 274 u64 tx_col; /* collisions */ 275 276 spinlock_t lock; /* prevent multiple simultaneous readers */ 277 }; 278 279 /* RSS hstype Definitions */ 280 #define EMAC_RSS_HSTYP_IPV4_EN 0x00000001 281 #define EMAC_RSS_HSTYP_TCP4_EN 0x00000002 282 #define EMAC_RSS_HSTYP_IPV6_EN 0x00000004 283 #define EMAC_RSS_HSTYP_TCP6_EN 0x00000008 284 #define EMAC_RSS_HSTYP_ALL_EN (\ 285 EMAC_RSS_HSTYP_IPV4_EN |\ 286 EMAC_RSS_HSTYP_TCP4_EN |\ 287 EMAC_RSS_HSTYP_IPV6_EN |\ 288 EMAC_RSS_HSTYP_TCP6_EN) 289 290 #define EMAC_VLAN_TO_TAG(_vlan, _tag) \ 291 (_tag = ((((_vlan) >> 8) & 0xFF) | (((_vlan) & 0xFF) << 8))) 292 293 #define EMAC_TAG_TO_VLAN(_tag, _vlan) \ 294 (_vlan = ((((_tag) >> 8) & 0xFF) | (((_tag) & 0xFF) << 8))) 295 296 #define EMAC_DEF_RX_BUF_SIZE 1536 297 #define EMAC_MAX_JUMBO_PKT_SIZE (9 * 1024) 298 #define EMAC_MAX_TX_OFFLOAD_THRESH (9 * 1024) 299 300 #define EMAC_MAX_ETH_FRAME_SIZE EMAC_MAX_JUMBO_PKT_SIZE 301 #define EMAC_MIN_ETH_FRAME_SIZE 68 302 303 #define EMAC_DEF_TX_QUEUES 1 304 #define EMAC_DEF_RX_QUEUES 1 305 306 #define EMAC_MIN_TX_DESCS 128 307 #define EMAC_MIN_RX_DESCS 128 308 309 #define EMAC_MAX_TX_DESCS 16383 310 #define EMAC_MAX_RX_DESCS 2047 311 312 #define EMAC_DEF_TX_DESCS 512 313 #define EMAC_DEF_RX_DESCS 256 314 315 #define EMAC_DEF_RX_IRQ_MOD 250 316 #define EMAC_DEF_TX_IRQ_MOD 250 317 318 #define EMAC_WATCHDOG_TIME (5 * HZ) 319 320 /* by default check link every 4 seconds */ 321 #define EMAC_TRY_LINK_TIMEOUT (4 * HZ) 322 323 /* emac_irq per-device (per-adapter) irq properties. 324 * @irq: irq number. 325 * @mask mask to use over status register. 326 */ 327 struct emac_irq { 328 unsigned int irq; 329 u32 mask; 330 }; 331 332 /* The device's main data structure */ 333 struct emac_adapter { 334 struct net_device *netdev; 335 struct mii_bus *mii_bus; 336 struct phy_device *phydev; 337 338 void __iomem *base; 339 void __iomem *csr; 340 341 struct emac_sgmii phy; 342 struct emac_stats stats; 343 344 struct emac_irq irq; 345 struct clk *clk[EMAC_CLK_CNT]; 346 347 /* All Descriptor memory */ 348 struct emac_ring_header ring_header; 349 struct emac_tx_queue tx_q; 350 struct emac_rx_queue rx_q; 351 unsigned int tx_desc_cnt; 352 unsigned int rx_desc_cnt; 353 unsigned int rrd_size; /* in quad words */ 354 unsigned int rfd_size; /* in quad words */ 355 unsigned int tpd_size; /* in quad words */ 356 357 unsigned int rxbuf_size; 358 359 /* Flow control / pause frames support. If automatic=True, do whatever 360 * the PHY does. Otherwise, use tx_flow_control and rx_flow_control. 361 */ 362 bool automatic; 363 bool tx_flow_control; 364 bool rx_flow_control; 365 366 /* True == use single-pause-frame mode. */ 367 bool single_pause_mode; 368 369 /* Ring parameter */ 370 u8 tpd_burst; 371 u8 rfd_burst; 372 unsigned int dmaw_dly_cnt; 373 unsigned int dmar_dly_cnt; 374 enum emac_dma_req_block dmar_block; 375 enum emac_dma_req_block dmaw_block; 376 enum emac_dma_order dma_order; 377 378 u32 irq_mod; 379 u32 preamble; 380 381 struct work_struct work_thread; 382 383 u16 msg_enable; 384 385 struct mutex reset_lock; 386 }; 387 388 int emac_reinit_locked(struct emac_adapter *adpt); 389 void emac_reg_update32(void __iomem *addr, u32 mask, u32 val); 390 391 void emac_set_ethtool_ops(struct net_device *netdev); 392 void emac_update_hw_stats(struct emac_adapter *adpt); 393 394 #endif /* _EMAC_H_ */ 395