1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
2  *
3  * This program is free software; you can redistribute it and/or modify
4  * it under the terms of the GNU General Public License version 2 and
5  * only version 2 as published by the Free Software Foundation.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  */
12 
13 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
14  */
15 
16 #include <linux/iopoll.h>
17 #include <linux/acpi.h>
18 #include <linux/of_device.h>
19 #include "emac.h"
20 #include "emac-mac.h"
21 #include "emac-sgmii.h"
22 
23 /* EMAC_SGMII register offsets */
24 #define EMAC_SGMII_PHY_AUTONEG_CFG2		0x0048
25 #define EMAC_SGMII_PHY_SPEED_CFG1		0x0074
26 #define EMAC_SGMII_PHY_IRQ_CMD			0x00ac
27 #define EMAC_SGMII_PHY_INTERRUPT_CLEAR		0x00b0
28 #define EMAC_SGMII_PHY_INTERRUPT_STATUS		0x00b8
29 
30 #define FORCE_AN_TX_CFG				BIT(5)
31 #define FORCE_AN_RX_CFG				BIT(4)
32 #define AN_ENABLE				BIT(0)
33 
34 #define DUPLEX_MODE				BIT(4)
35 #define SPDMODE_1000				BIT(1)
36 #define SPDMODE_100				BIT(0)
37 #define SPDMODE_10				0
38 
39 #define IRQ_GLOBAL_CLEAR			BIT(0)
40 
41 #define DECODE_CODE_ERR				BIT(7)
42 #define DECODE_DISP_ERR				BIT(6)
43 
44 #define SGMII_PHY_IRQ_CLR_WAIT_TIME		10
45 
46 #define SGMII_PHY_INTERRUPT_ERR		(DECODE_CODE_ERR | DECODE_DISP_ERR)
47 
48 #define SERDES_START_WAIT_TIMES			100
49 
50 static int emac_sgmii_link_init(struct emac_adapter *adpt)
51 {
52 	struct phy_device *phydev = adpt->phydev;
53 	struct emac_phy *phy = &adpt->phy;
54 	u32 val;
55 
56 	val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
57 
58 	if (phydev->autoneg == AUTONEG_ENABLE) {
59 		val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG);
60 		val |= AN_ENABLE;
61 		writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
62 	} else {
63 		u32 speed_cfg;
64 
65 		switch (phydev->speed) {
66 		case SPEED_10:
67 			speed_cfg = SPDMODE_10;
68 			break;
69 		case SPEED_100:
70 			speed_cfg = SPDMODE_100;
71 			break;
72 		case SPEED_1000:
73 			speed_cfg = SPDMODE_1000;
74 			break;
75 		default:
76 			return -EINVAL;
77 		}
78 
79 		if (phydev->duplex == DUPLEX_FULL)
80 			speed_cfg |= DUPLEX_MODE;
81 
82 		val &= ~AN_ENABLE;
83 		writel(speed_cfg, phy->base + EMAC_SGMII_PHY_SPEED_CFG1);
84 		writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
85 	}
86 
87 	return 0;
88 }
89 
90 static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u32 irq_bits)
91 {
92 	struct emac_phy *phy = &adpt->phy;
93 	u32 status;
94 
95 	writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
96 	writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
97 	/* Ensure interrupt clear command is written to HW */
98 	wmb();
99 
100 	/* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must
101 	 * be confirmed before clearing the bits in other registers.
102 	 * It takes a few cycles for hw to clear the interrupt status.
103 	 */
104 	if (readl_poll_timeout_atomic(phy->base +
105 				      EMAC_SGMII_PHY_INTERRUPT_STATUS,
106 				      status, !(status & irq_bits), 1,
107 				      SGMII_PHY_IRQ_CLR_WAIT_TIME)) {
108 		netdev_err(adpt->netdev,
109 			   "error: failed clear SGMII irq: status:0x%x bits:0x%x\n",
110 			   status, irq_bits);
111 		return -EIO;
112 	}
113 
114 	/* Finalize clearing procedure */
115 	writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD);
116 	writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
117 
118 	/* Ensure that clearing procedure finalization is written to HW */
119 	wmb();
120 
121 	return 0;
122 }
123 
124 static void emac_sgmii_reset_prepare(struct emac_adapter *adpt)
125 {
126 	struct emac_phy *phy = &adpt->phy;
127 	u32 val;
128 
129 	/* Reset PHY */
130 	val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
131 	writel(((val & ~PHY_RESET) | PHY_RESET), phy->base +
132 	       EMAC_EMAC_WRAPPER_CSR2);
133 	/* Ensure phy-reset command is written to HW before the release cmd */
134 	msleep(50);
135 	val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2);
136 	writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2);
137 	/* Ensure phy-reset release command is written to HW before initializing
138 	 * SGMII
139 	 */
140 	msleep(50);
141 }
142 
143 void emac_sgmii_reset(struct emac_adapter *adpt)
144 {
145 	int ret;
146 
147 	emac_sgmii_reset_prepare(adpt);
148 
149 	ret = emac_sgmii_link_init(adpt);
150 	if (ret) {
151 		netdev_err(adpt->netdev, "unsupported link speed\n");
152 		return;
153 	}
154 
155 	ret = adpt->phy.initialize(adpt);
156 	if (ret)
157 		netdev_err(adpt->netdev,
158 			   "could not reinitialize internal PHY (error=%i)\n",
159 			   ret);
160 }
161 
162 static int emac_sgmii_acpi_match(struct device *dev, void *data)
163 {
164 #ifdef CONFIG_ACPI
165 	static const struct acpi_device_id match_table[] = {
166 		{
167 			.id = "QCOM8071",
168 		},
169 		{}
170 	};
171 	const struct acpi_device_id *id = acpi_match_device(match_table, dev);
172 	emac_sgmii_initialize *initialize = data;
173 
174 	if (id) {
175 		acpi_handle handle = ACPI_HANDLE(dev);
176 		unsigned long long hrv;
177 		acpi_status status;
178 
179 		status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
180 		if (status) {
181 			if (status == AE_NOT_FOUND)
182 				/* Older versions of the QDF2432 ACPI tables do
183 				 * not have an _HRV property.
184 				 */
185 				hrv = 1;
186 			else
187 				/* Something is wrong with the tables */
188 				return 0;
189 		}
190 
191 		switch (hrv) {
192 		case 1:
193 			*initialize = emac_sgmii_init_qdf2432;
194 			return 1;
195 		case 2:
196 			*initialize = emac_sgmii_init_qdf2400;
197 			return 1;
198 		}
199 	}
200 #endif
201 
202 	return 0;
203 }
204 
205 static const struct of_device_id emac_sgmii_dt_match[] = {
206 	{
207 		.compatible = "qcom,fsm9900-emac-sgmii",
208 		.data = emac_sgmii_init_fsm9900,
209 	},
210 	{
211 		.compatible = "qcom,qdf2432-emac-sgmii",
212 		.data = emac_sgmii_init_qdf2432,
213 	},
214 	{}
215 };
216 
217 int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
218 {
219 	struct platform_device *sgmii_pdev = NULL;
220 	struct emac_phy *phy = &adpt->phy;
221 	struct resource *res;
222 	int ret;
223 
224 	if (has_acpi_companion(&pdev->dev)) {
225 		struct device *dev;
226 
227 		dev = device_find_child(&pdev->dev, &phy->initialize,
228 					emac_sgmii_acpi_match);
229 
230 		if (!dev) {
231 			dev_err(&pdev->dev, "cannot find internal phy node\n");
232 			return -ENODEV;
233 		}
234 
235 		sgmii_pdev = to_platform_device(dev);
236 	} else {
237 		const struct of_device_id *match;
238 		struct device_node *np;
239 
240 		np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0);
241 		if (!np) {
242 			dev_err(&pdev->dev, "missing internal-phy property\n");
243 			return -ENODEV;
244 		}
245 
246 		sgmii_pdev = of_find_device_by_node(np);
247 		if (!sgmii_pdev) {
248 			dev_err(&pdev->dev, "invalid internal-phy property\n");
249 			return -ENODEV;
250 		}
251 
252 		match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev);
253 		if (!match) {
254 			dev_err(&pdev->dev, "unrecognized internal phy node\n");
255 			ret = -ENODEV;
256 			goto error_put_device;
257 		}
258 
259 		phy->initialize = (emac_sgmii_initialize)match->data;
260 	}
261 
262 	/* Base address is the first address */
263 	res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0);
264 	if (!res) {
265 		ret = -EINVAL;
266 		goto error_put_device;
267 	}
268 
269 	phy->base = ioremap(res->start, resource_size(res));
270 	if (!phy->base) {
271 		ret = -ENOMEM;
272 		goto error_put_device;
273 	}
274 
275 	/* v2 SGMII has a per-lane digital digital, so parse it if it exists */
276 	res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 1);
277 	if (res) {
278 		phy->digital = ioremap(res->start, resource_size(res));
279 		if (!phy->digital) {
280 			ret = -ENOMEM;
281 			goto error_unmap_base;
282 		}
283 	}
284 
285 	ret = phy->initialize(adpt);
286 	if (ret)
287 		goto error;
288 
289 	emac_sgmii_irq_clear(adpt, SGMII_PHY_INTERRUPT_ERR);
290 
291 	/* We've remapped the addresses, so we don't need the device any
292 	 * more.  of_find_device_by_node() says we should release it.
293 	 */
294 	put_device(&sgmii_pdev->dev);
295 
296 	return 0;
297 
298 error:
299 	if (phy->digital)
300 		iounmap(phy->digital);
301 error_unmap_base:
302 	iounmap(phy->base);
303 error_put_device:
304 	put_device(&sgmii_pdev->dev);
305 
306 	return ret;
307 }
308