1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
2  *
3  * This program is free software; you can redistribute it and/or modify
4  * it under the terms of the GNU General Public License version 2 and
5  * only version 2 as published by the Free Software Foundation.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  */
12 
13 /* Qualcomm Technologies, Inc. QDF2432 EMAC SGMII Controller driver.
14  */
15 
16 #include <linux/iopoll.h>
17 #include "emac.h"
18 
19 /* EMAC_SGMII register offsets */
20 #define EMAC_SGMII_PHY_TX_PWR_CTRL		0x000C
21 #define EMAC_SGMII_PHY_LANE_CTRL1		0x0018
22 #define EMAC_SGMII_PHY_CDR_CTRL0		0x0058
23 #define EMAC_SGMII_PHY_POW_DWN_CTRL0		0x0080
24 #define EMAC_SGMII_PHY_RESET_CTRL		0x00a8
25 #define EMAC_SGMII_PHY_INTERRUPT_MASK		0x00b4
26 
27 /* SGMII digital lane registers */
28 #define EMAC_SGMII_LN_DRVR_CTRL0		0x000C
29 #define EMAC_SGMII_LN_DRVR_TAP_EN		0x0018
30 #define EMAC_SGMII_LN_TX_MARGINING		0x001C
31 #define EMAC_SGMII_LN_TX_PRE			0x0020
32 #define EMAC_SGMII_LN_TX_POST			0x0024
33 #define EMAC_SGMII_LN_TX_BAND_MODE		0x0060
34 #define EMAC_SGMII_LN_LANE_MODE			0x0064
35 #define EMAC_SGMII_LN_PARALLEL_RATE		0x0078
36 #define EMAC_SGMII_LN_CML_CTRL_MODE0		0x00B8
37 #define EMAC_SGMII_LN_MIXER_CTRL_MODE0		0x00D0
38 #define EMAC_SGMII_LN_VGA_INITVAL		0x0134
39 #define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0	0x017C
40 #define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0	0x0188
41 #define EMAC_SGMII_LN_UCDR_SO_CONFIG		0x0194
42 #define EMAC_SGMII_LN_RX_BAND			0x019C
43 #define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0	0x01B8
44 #define EMAC_SGMII_LN_RSM_CONFIG		0x01F0
45 #define EMAC_SGMII_LN_SIGDET_ENABLES		0x0224
46 #define EMAC_SGMII_LN_SIGDET_CNTRL		0x0228
47 #define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL	0x022C
48 #define EMAC_SGMII_LN_RX_EN_SIGNAL		0x02A0
49 #define EMAC_SGMII_LN_RX_MISC_CNTRL0		0x02AC
50 #define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV		0x02BC
51 
52 /* SGMII digital lane register values */
53 #define UCDR_STEP_BY_TWO_MODE0			BIT(7)
54 #define UCDR_xO_GAIN_MODE(x)			((x) & 0x7f)
55 #define UCDR_ENABLE				BIT(6)
56 #define UCDR_SO_SATURATION(x)			((x) & 0x3f)
57 
58 #define SIGDET_LP_BYP_PS4			BIT(7)
59 #define SIGDET_EN_PS0_TO_PS2			BIT(6)
60 
61 #define TXVAL_VALID_INIT			BIT(4)
62 #define KR_PCIGEN3_MODE				BIT(0)
63 
64 #define MAIN_EN					BIT(0)
65 
66 #define TX_MARGINING_MUX			BIT(6)
67 #define TX_MARGINING(x)				((x) & 0x3f)
68 
69 #define TX_PRE_MUX				BIT(6)
70 
71 #define TX_POST_MUX				BIT(6)
72 
73 #define CML_GEAR_MODE(x)			(((x) & 7) << 3)
74 #define CML2CMOS_IBOOST_MODE(x)			((x) & 7)
75 
76 #define MIXER_LOADB_MODE(x)			(((x) & 0xf) << 2)
77 #define MIXER_DATARATE_MODE(x)			((x) & 3)
78 
79 #define VGA_THRESH_DFE(x)			((x) & 0x3f)
80 
81 #define SIGDET_LP_BYP_PS0_TO_PS2		BIT(5)
82 #define SIGDET_FLT_BYP				BIT(0)
83 
84 #define SIGDET_LVL(x)				(((x) & 0xf) << 4)
85 
86 #define SIGDET_DEGLITCH_CTRL(x)			(((x) & 0xf) << 1)
87 
88 #define DRVR_LOGIC_CLK_EN			BIT(4)
89 #define DRVR_LOGIC_CLK_DIV(x)			((x) & 0xf)
90 
91 #define PARALLEL_RATE_MODE0(x)			((x) & 0x3)
92 
93 #define BAND_MODE0(x)				((x) & 0x3)
94 
95 #define LANE_MODE(x)				((x) & 0x1f)
96 
97 #define CDR_PD_SEL_MODE0(x)			(((x) & 0x3) << 5)
98 #define BYPASS_RSM_SAMP_CAL			BIT(1)
99 #define BYPASS_RSM_DLL_CAL			BIT(0)
100 
101 #define L0_RX_EQUALIZE_ENABLE			BIT(6)
102 
103 #define PWRDN_B					BIT(0)
104 
105 #define CDR_MAX_CNT(x)				((x) & 0xff)
106 
107 #define SERDES_START_WAIT_TIMES			100
108 
109 struct emac_reg_write {
110 	unsigned int offset;
111 	u32 val;
112 };
113 
114 static void emac_reg_write_all(void __iomem *base,
115 			       const struct emac_reg_write *itr, size_t size)
116 {
117 	size_t i;
118 
119 	for (i = 0; i < size; ++itr, ++i)
120 		writel(itr->val, base + itr->offset);
121 }
122 
123 static const struct emac_reg_write sgmii_laned[] = {
124 	/* CDR Settings */
125 	{EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0,
126 		UCDR_STEP_BY_TWO_MODE0 | UCDR_xO_GAIN_MODE(10)},
127 	{EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)},
128 	{EMAC_SGMII_LN_UCDR_SO_CONFIG, UCDR_ENABLE | UCDR_SO_SATURATION(12)},
129 
130 	/* TX/RX Settings */
131 	{EMAC_SGMII_LN_RX_EN_SIGNAL, SIGDET_LP_BYP_PS4 | SIGDET_EN_PS0_TO_PS2},
132 
133 	{EMAC_SGMII_LN_DRVR_CTRL0, TXVAL_VALID_INIT | KR_PCIGEN3_MODE},
134 	{EMAC_SGMII_LN_DRVR_TAP_EN, MAIN_EN},
135 	{EMAC_SGMII_LN_TX_MARGINING, TX_MARGINING_MUX | TX_MARGINING(25)},
136 	{EMAC_SGMII_LN_TX_PRE, TX_PRE_MUX},
137 	{EMAC_SGMII_LN_TX_POST, TX_POST_MUX},
138 
139 	{EMAC_SGMII_LN_CML_CTRL_MODE0,
140 		CML_GEAR_MODE(1) | CML2CMOS_IBOOST_MODE(1)},
141 	{EMAC_SGMII_LN_MIXER_CTRL_MODE0,
142 		MIXER_LOADB_MODE(12) | MIXER_DATARATE_MODE(1)},
143 	{EMAC_SGMII_LN_VGA_INITVAL, VGA_THRESH_DFE(31)},
144 	{EMAC_SGMII_LN_SIGDET_ENABLES,
145 		SIGDET_LP_BYP_PS0_TO_PS2 | SIGDET_FLT_BYP},
146 	{EMAC_SGMII_LN_SIGDET_CNTRL, SIGDET_LVL(8)},
147 
148 	{EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL, SIGDET_DEGLITCH_CTRL(4)},
149 	{EMAC_SGMII_LN_RX_MISC_CNTRL0, 0},
150 	{EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV,
151 		DRVR_LOGIC_CLK_EN | DRVR_LOGIC_CLK_DIV(4)},
152 
153 	{EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)},
154 	{EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(2)},
155 	{EMAC_SGMII_LN_RX_BAND, BAND_MODE0(3)},
156 	{EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)},
157 	{EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(3)},
158 	{EMAC_SGMII_LN_RSM_CONFIG, BYPASS_RSM_SAMP_CAL | BYPASS_RSM_DLL_CAL},
159 };
160 
161 static const struct emac_reg_write physical_coding_sublayer_programming[] = {
162 	{EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
163 	{EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
164 	{EMAC_SGMII_PHY_TX_PWR_CTRL, 0},
165 	{EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQUALIZE_ENABLE},
166 };
167 
168 int emac_sgmii_init_qdf2432(struct emac_adapter *adpt)
169 {
170 	struct emac_sgmii *phy = &adpt->phy;
171 	void __iomem *phy_regs = phy->base;
172 	void __iomem *laned = phy->digital;
173 	unsigned int i;
174 	u32 lnstatus;
175 
176 	/* PCS lane-x init */
177 	emac_reg_write_all(phy->base, physical_coding_sublayer_programming,
178 			   ARRAY_SIZE(physical_coding_sublayer_programming));
179 
180 	/* SGMII lane-x init */
181 	emac_reg_write_all(phy->digital, sgmii_laned, ARRAY_SIZE(sgmii_laned));
182 
183 	/* Power up PCS and start reset lane state machine */
184 
185 	writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL);
186 	writel(1, laned + SGMII_LN_RSM_START);
187 
188 	/* Wait for c_ready assertion */
189 	for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
190 		lnstatus = readl(phy_regs + SGMII_PHY_LN_LANE_STATUS);
191 		if (lnstatus & BIT(1))
192 			break;
193 		usleep_range(100, 200);
194 	}
195 
196 	if (i == SERDES_START_WAIT_TIMES) {
197 		netdev_err(adpt->netdev, "SGMII failed to start\n");
198 		return -EIO;
199 	}
200 
201 	/* Disable digital and SERDES loopback */
202 	writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0);
203 	writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2);
204 	writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1);
205 
206 	/* Mask out all the SGMII Interrupt */
207 	writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK);
208 
209 	return 0;
210 }
211