1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
2  *
3  * This program is free software; you can redistribute it and/or modify
4  * it under the terms of the GNU General Public License version 2 and
5  * only version 2 as published by the Free Software Foundation.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  */
12 
13 /* Qualcomm Technologies, Inc. QDF2400 EMAC SGMII Controller driver.
14  */
15 
16 #include <linux/iopoll.h>
17 #include "emac.h"
18 
19 /* EMAC_SGMII register offsets */
20 #define EMAC_SGMII_PHY_TX_PWR_CTRL		0x000C
21 #define EMAC_SGMII_PHY_LANE_CTRL1		0x0018
22 #define EMAC_SGMII_PHY_CDR_CTRL0		0x0058
23 #define EMAC_SGMII_PHY_POW_DWN_CTRL0		0x0080
24 #define EMAC_SGMII_PHY_RESET_CTRL		0x00a8
25 #define EMAC_SGMII_PHY_INTERRUPT_MASK		0x00b4
26 
27 /* SGMII digital lane registers */
28 #define EMAC_SGMII_LN_DRVR_CTRL0		0x000C
29 #define EMAC_SGMII_LN_DRVR_CTRL1		0x0010
30 #define EMAC_SGMII_LN_DRVR_TAP_EN		0x0018
31 #define EMAC_SGMII_LN_TX_MARGINING		0x001C
32 #define EMAC_SGMII_LN_TX_PRE			0x0020
33 #define EMAC_SGMII_LN_TX_POST			0x0024
34 #define EMAC_SGMII_LN_TX_BAND_MODE		0x0060
35 #define EMAC_SGMII_LN_LANE_MODE			0x0064
36 #define EMAC_SGMII_LN_PARALLEL_RATE		0x007C
37 #define EMAC_SGMII_LN_CML_CTRL_MODE0		0x00C0
38 #define EMAC_SGMII_LN_MIXER_CTRL_MODE0		0x00D8
39 #define EMAC_SGMII_LN_VGA_INITVAL		0x013C
40 #define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0	0x0184
41 #define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0	0x0190
42 #define EMAC_SGMII_LN_UCDR_SO_CONFIG		0x019C
43 #define EMAC_SGMII_LN_RX_BAND			0x01A4
44 #define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0	0x01C0
45 #define EMAC_SGMII_LN_RSM_CONFIG		0x01F8
46 #define EMAC_SGMII_LN_SIGDET_ENABLES		0x0230
47 #define EMAC_SGMII_LN_SIGDET_CNTRL		0x0234
48 #define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL	0x0238
49 #define EMAC_SGMII_LN_RX_EN_SIGNAL		0x02AC
50 #define EMAC_SGMII_LN_RX_MISC_CNTRL0		0x02B8
51 #define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV		0x02C8
52 #define EMAC_SGMII_LN_RX_RESECODE_OFFSET	0x02CC
53 
54 /* SGMII digital lane register values */
55 #define UCDR_STEP_BY_TWO_MODE0			BIT(7)
56 #define UCDR_xO_GAIN_MODE(x)			((x) & 0x7f)
57 #define UCDR_ENABLE				BIT(6)
58 #define UCDR_SO_SATURATION(x)			((x) & 0x3f)
59 
60 #define SIGDET_LP_BYP_PS4			BIT(7)
61 #define SIGDET_EN_PS0_TO_PS2			BIT(6)
62 
63 #define TXVAL_VALID_INIT			BIT(4)
64 #define KR_PCIGEN3_MODE				BIT(0)
65 
66 #define MAIN_EN					BIT(0)
67 
68 #define TX_MARGINING_MUX			BIT(6)
69 #define TX_MARGINING(x)				((x) & 0x3f)
70 
71 #define TX_PRE_MUX				BIT(6)
72 
73 #define TX_POST_MUX				BIT(6)
74 
75 #define CML_GEAR_MODE(x)			(((x) & 7) << 3)
76 #define CML2CMOS_IBOOST_MODE(x)			((x) & 7)
77 
78 #define RESCODE_OFFSET(x)			((x) & 0x1f)
79 
80 #define MIXER_LOADB_MODE(x)			(((x) & 0xf) << 2)
81 #define MIXER_DATARATE_MODE(x)			((x) & 3)
82 
83 #define VGA_THRESH_DFE(x)			((x) & 0x3f)
84 
85 #define SIGDET_LP_BYP_PS0_TO_PS2		BIT(5)
86 #define SIGDET_FLT_BYP				BIT(0)
87 
88 #define SIGDET_LVL(x)				(((x) & 0xf) << 4)
89 
90 #define SIGDET_DEGLITCH_CTRL(x)			(((x) & 0xf) << 1)
91 
92 #define INVERT_PCS_RX_CLK			BIT(7)
93 
94 #define DRVR_LOGIC_CLK_EN			BIT(4)
95 #define DRVR_LOGIC_CLK_DIV(x)			((x) & 0xf)
96 
97 #define PARALLEL_RATE_MODE0(x)			((x) & 0x3)
98 
99 #define BAND_MODE0(x)				((x) & 0x3)
100 
101 #define LANE_MODE(x)				((x) & 0x1f)
102 
103 #define CDR_PD_SEL_MODE0(x)			(((x) & 0x3) << 5)
104 #define EN_DLL_MODE0				BIT(4)
105 #define EN_IQ_DCC_MODE0				BIT(3)
106 #define EN_IQCAL_MODE0				BIT(2)
107 
108 #define BYPASS_RSM_SAMP_CAL			BIT(1)
109 #define BYPASS_RSM_DLL_CAL			BIT(0)
110 
111 #define L0_RX_EQUALIZE_ENABLE			BIT(6)
112 
113 #define PWRDN_B					BIT(0)
114 
115 #define CDR_MAX_CNT(x)				((x) & 0xff)
116 
117 #define SERDES_START_WAIT_TIMES			100
118 
119 struct emac_reg_write {
120 	unsigned int offset;
121 	u32 val;
122 };
123 
124 static void emac_reg_write_all(void __iomem *base,
125 			       const struct emac_reg_write *itr, size_t size)
126 {
127 	size_t i;
128 
129 	for (i = 0; i < size; ++itr, ++i)
130 		writel(itr->val, base + itr->offset);
131 }
132 
133 static const struct emac_reg_write sgmii_laned[] = {
134 	/* CDR Settings */
135 	{EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0,
136 		UCDR_STEP_BY_TWO_MODE0 | UCDR_xO_GAIN_MODE(10)},
137 	{EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)},
138 	{EMAC_SGMII_LN_UCDR_SO_CONFIG, UCDR_ENABLE | UCDR_SO_SATURATION(12)},
139 
140 	/* TX/RX Settings */
141 	{EMAC_SGMII_LN_RX_EN_SIGNAL, SIGDET_LP_BYP_PS4 | SIGDET_EN_PS0_TO_PS2},
142 
143 	{EMAC_SGMII_LN_DRVR_CTRL0, TXVAL_VALID_INIT | KR_PCIGEN3_MODE},
144 	{EMAC_SGMII_LN_DRVR_TAP_EN, MAIN_EN},
145 	{EMAC_SGMII_LN_TX_MARGINING, TX_MARGINING_MUX | TX_MARGINING(25)},
146 	{EMAC_SGMII_LN_TX_PRE, TX_PRE_MUX},
147 	{EMAC_SGMII_LN_TX_POST, TX_POST_MUX},
148 
149 	{EMAC_SGMII_LN_CML_CTRL_MODE0,
150 		CML_GEAR_MODE(1) | CML2CMOS_IBOOST_MODE(1)},
151 	{EMAC_SGMII_LN_MIXER_CTRL_MODE0,
152 		MIXER_LOADB_MODE(12) | MIXER_DATARATE_MODE(1)},
153 	{EMAC_SGMII_LN_VGA_INITVAL, VGA_THRESH_DFE(31)},
154 	{EMAC_SGMII_LN_SIGDET_ENABLES,
155 		SIGDET_LP_BYP_PS0_TO_PS2 | SIGDET_FLT_BYP},
156 	{EMAC_SGMII_LN_SIGDET_CNTRL, SIGDET_LVL(8)},
157 
158 	{EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL, SIGDET_DEGLITCH_CTRL(4)},
159 	{EMAC_SGMII_LN_RX_MISC_CNTRL0, INVERT_PCS_RX_CLK},
160 	{EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV,
161 		DRVR_LOGIC_CLK_EN | DRVR_LOGIC_CLK_DIV(4)},
162 
163 	{EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)},
164 	{EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(1)},
165 	{EMAC_SGMII_LN_RX_BAND, BAND_MODE0(2)},
166 	{EMAC_SGMII_LN_DRVR_CTRL1, RESCODE_OFFSET(7)},
167 	{EMAC_SGMII_LN_RX_RESECODE_OFFSET, RESCODE_OFFSET(9)},
168 	{EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)},
169 	{EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(2) |
170 		EN_DLL_MODE0 | EN_IQ_DCC_MODE0 | EN_IQCAL_MODE0},
171 	{EMAC_SGMII_LN_RSM_CONFIG, BYPASS_RSM_SAMP_CAL | BYPASS_RSM_DLL_CAL},
172 };
173 
174 static const struct emac_reg_write physical_coding_sublayer_programming[] = {
175 	{EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
176 	{EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
177 	{EMAC_SGMII_PHY_TX_PWR_CTRL, 0},
178 	{EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQUALIZE_ENABLE},
179 };
180 
181 int emac_sgmii_init_qdf2400(struct emac_adapter *adpt)
182 {
183 	struct emac_sgmii *phy = &adpt->phy;
184 	void __iomem *phy_regs = phy->base;
185 	void __iomem *laned = phy->digital;
186 	unsigned int i;
187 	u32 lnstatus;
188 
189 	/* PCS lane-x init */
190 	emac_reg_write_all(phy->base, physical_coding_sublayer_programming,
191 			   ARRAY_SIZE(physical_coding_sublayer_programming));
192 
193 	/* SGMII lane-x init */
194 	emac_reg_write_all(phy->digital, sgmii_laned, ARRAY_SIZE(sgmii_laned));
195 
196 	/* Power up PCS and start reset lane state machine */
197 
198 	writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL);
199 	writel(1, laned + SGMII_LN_RSM_START);
200 
201 	/* Wait for c_ready assertion */
202 	for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
203 		lnstatus = readl(phy_regs + SGMII_PHY_LN_LANE_STATUS);
204 		if (lnstatus & BIT(1))
205 			break;
206 		usleep_range(100, 200);
207 	}
208 
209 	if (i == SERDES_START_WAIT_TIMES) {
210 		netdev_err(adpt->netdev, "SGMII failed to start\n");
211 		return -EIO;
212 	}
213 
214 	/* Disable digital and SERDES loopback */
215 	writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0);
216 	writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2);
217 	writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1);
218 
219 	/* Mask out all the SGMII Interrupt */
220 	writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK);
221 
222 	return 0;
223 }
224