1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
2  *
3  * This program is free software; you can redistribute it and/or modify
4  * it under the terms of the GNU General Public License version 2 and
5  * only version 2 as published by the Free Software Foundation.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  */
12 
13 /* Qualcomm Technologies, Inc. FSM9900 EMAC SGMII Controller driver.
14  */
15 
16 #include <linux/iopoll.h>
17 #include "emac.h"
18 
19 /* EMAC_QSERDES register offsets */
20 #define EMAC_QSERDES_COM_SYS_CLK_CTRL		0x0000
21 #define EMAC_QSERDES_COM_PLL_CNTRL		0x0014
22 #define EMAC_QSERDES_COM_PLL_IP_SETI		0x0018
23 #define EMAC_QSERDES_COM_PLL_CP_SETI		0x0024
24 #define EMAC_QSERDES_COM_PLL_IP_SETP		0x0028
25 #define EMAC_QSERDES_COM_PLL_CP_SETP		0x002c
26 #define EMAC_QSERDES_COM_SYSCLK_EN_SEL		0x0038
27 #define EMAC_QSERDES_COM_RESETSM_CNTRL		0x0040
28 #define EMAC_QSERDES_COM_PLLLOCK_CMP1		0x0044
29 #define EMAC_QSERDES_COM_PLLLOCK_CMP2		0x0048
30 #define EMAC_QSERDES_COM_PLLLOCK_CMP3		0x004c
31 #define EMAC_QSERDES_COM_PLLLOCK_CMP_EN		0x0050
32 #define EMAC_QSERDES_COM_DEC_START1		0x0064
33 #define EMAC_QSERDES_COM_DIV_FRAC_START1	0x0098
34 #define EMAC_QSERDES_COM_DIV_FRAC_START2	0x009c
35 #define EMAC_QSERDES_COM_DIV_FRAC_START3	0x00a0
36 #define EMAC_QSERDES_COM_DEC_START2		0x00a4
37 #define EMAC_QSERDES_COM_PLL_CRCTRL		0x00ac
38 #define EMAC_QSERDES_COM_RESET_SM		0x00bc
39 #define EMAC_QSERDES_TX_BIST_MODE_LANENO	0x0100
40 #define EMAC_QSERDES_TX_TX_EMP_POST1_LVL	0x0108
41 #define EMAC_QSERDES_TX_TX_DRV_LVL		0x010c
42 #define EMAC_QSERDES_TX_LANE_MODE		0x0150
43 #define EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN	0x0170
44 #define EMAC_QSERDES_RX_CDR_CONTROL		0x0200
45 #define EMAC_QSERDES_RX_CDR_CONTROL2		0x0210
46 #define EMAC_QSERDES_RX_RX_EQ_GAIN12		0x0230
47 
48 /* EMAC_SGMII register offsets */
49 #define EMAC_SGMII_PHY_SERDES_START		0x0000
50 #define EMAC_SGMII_PHY_CMN_PWR_CTRL		0x0004
51 #define EMAC_SGMII_PHY_RX_PWR_CTRL		0x0008
52 #define EMAC_SGMII_PHY_TX_PWR_CTRL		0x000C
53 #define EMAC_SGMII_PHY_LANE_CTRL1		0x0018
54 #define EMAC_SGMII_PHY_CDR_CTRL0		0x0058
55 #define EMAC_SGMII_PHY_POW_DWN_CTRL0		0x0080
56 #define EMAC_SGMII_PHY_INTERRUPT_MASK		0x00b4
57 
58 #define PLL_IPSETI(x)				((x) & 0x3f)
59 
60 #define PLL_CPSETI(x)				((x) & 0xff)
61 
62 #define PLL_IPSETP(x)				((x) & 0x3f)
63 
64 #define PLL_CPSETP(x)				((x) & 0x1f)
65 
66 #define PLL_RCTRL(x)				(((x) & 0xf) << 4)
67 #define PLL_CCTRL(x)				((x) & 0xf)
68 
69 #define LANE_MODE(x)				((x) & 0x1f)
70 
71 #define SYSCLK_CM				BIT(4)
72 #define SYSCLK_AC_COUPLE			BIT(3)
73 
74 #define OCP_EN					BIT(5)
75 #define PLL_DIV_FFEN				BIT(2)
76 #define PLL_DIV_ORD				BIT(1)
77 
78 #define SYSCLK_SEL_CMOS				BIT(3)
79 
80 #define FRQ_TUNE_MODE				BIT(4)
81 
82 #define PLLLOCK_CMP_EN				BIT(0)
83 
84 #define DEC_START1_MUX				BIT(7)
85 #define DEC_START1(x)				((x) & 0x7f)
86 
87 #define DIV_FRAC_START_MUX			BIT(7)
88 #define DIV_FRAC_START(x)			((x) & 0x7f)
89 
90 #define DIV_FRAC_START3_MUX			BIT(4)
91 #define DIV_FRAC_START3(x)			((x) & 0xf)
92 
93 #define DEC_START2_MUX				BIT(1)
94 #define DEC_START2				BIT(0)
95 
96 #define READY					BIT(5)
97 
98 #define TX_EMP_POST1_LVL_MUX			BIT(5)
99 #define TX_EMP_POST1_LVL(x)			((x) & 0x1f)
100 
101 #define TX_DRV_LVL_MUX				BIT(4)
102 #define TX_DRV_LVL(x)				((x) & 0xf)
103 
104 #define EMP_EN_MUX				BIT(1)
105 #define EMP_EN					BIT(0)
106 
107 #define SECONDORDERENABLE			BIT(6)
108 #define FIRSTORDER_THRESH(x)			(((x) & 0x7) << 3)
109 #define SECONDORDERGAIN(x)			((x) & 0x7)
110 
111 #define RX_EQ_GAIN2(x)				(((x) & 0xf) << 4)
112 #define RX_EQ_GAIN1(x)				((x) & 0xf)
113 
114 #define SERDES_START				BIT(0)
115 
116 #define BIAS_EN					BIT(6)
117 #define PLL_EN					BIT(5)
118 #define SYSCLK_EN				BIT(4)
119 #define CLKBUF_L_EN				BIT(3)
120 #define PLL_TXCLK_EN				BIT(1)
121 #define PLL_RXCLK_EN				BIT(0)
122 
123 #define L0_RX_SIGDET_EN				BIT(7)
124 #define L0_RX_TERM_MODE(x)			(((x) & 3) << 4)
125 #define L0_RX_I_EN				BIT(1)
126 
127 #define L0_TX_EN				BIT(5)
128 #define L0_CLKBUF_EN				BIT(4)
129 #define L0_TRAN_BIAS_EN				BIT(1)
130 
131 #define L0_RX_EQUALIZE_ENABLE			BIT(6)
132 #define L0_RESET_TSYNC_EN			BIT(4)
133 #define L0_DRV_LVL(x)				((x) & 0xf)
134 
135 #define PWRDN_B					BIT(0)
136 #define CDR_MAX_CNT(x)				((x) & 0xff)
137 
138 #define PLLLOCK_CMP(x)				((x) & 0xff)
139 
140 #define SERDES_START_WAIT_TIMES			100
141 
142 struct emac_reg_write {
143 	unsigned int offset;
144 	u32 val;
145 };
146 
147 static void emac_reg_write_all(void __iomem *base,
148 			       const struct emac_reg_write *itr, size_t size)
149 {
150 	size_t i;
151 
152 	for (i = 0; i < size; ++itr, ++i)
153 		writel(itr->val, base + itr->offset);
154 }
155 
156 static const struct emac_reg_write physical_coding_sublayer_programming[] = {
157 	{EMAC_SGMII_PHY_CDR_CTRL0, CDR_MAX_CNT(15)},
158 	{EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
159 	{EMAC_SGMII_PHY_CMN_PWR_CTRL,
160 		BIAS_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN | PLL_RXCLK_EN},
161 	{EMAC_SGMII_PHY_TX_PWR_CTRL, L0_TX_EN | L0_CLKBUF_EN | L0_TRAN_BIAS_EN},
162 	{EMAC_SGMII_PHY_RX_PWR_CTRL,
163 		L0_RX_SIGDET_EN | L0_RX_TERM_MODE(1) | L0_RX_I_EN},
164 	{EMAC_SGMII_PHY_CMN_PWR_CTRL,
165 		BIAS_EN | PLL_EN | SYSCLK_EN | CLKBUF_L_EN | PLL_TXCLK_EN |
166 		PLL_RXCLK_EN},
167 	{EMAC_SGMII_PHY_LANE_CTRL1,
168 		L0_RX_EQUALIZE_ENABLE | L0_RESET_TSYNC_EN | L0_DRV_LVL(15)},
169 };
170 
171 static const struct emac_reg_write sysclk_refclk_setting[] = {
172 	{EMAC_QSERDES_COM_SYSCLK_EN_SEL, SYSCLK_SEL_CMOS},
173 	{EMAC_QSERDES_COM_SYS_CLK_CTRL,	SYSCLK_CM | SYSCLK_AC_COUPLE},
174 };
175 
176 static const struct emac_reg_write pll_setting[] = {
177 	{EMAC_QSERDES_COM_PLL_IP_SETI, PLL_IPSETI(1)},
178 	{EMAC_QSERDES_COM_PLL_CP_SETI, PLL_CPSETI(59)},
179 	{EMAC_QSERDES_COM_PLL_IP_SETP, PLL_IPSETP(10)},
180 	{EMAC_QSERDES_COM_PLL_CP_SETP, PLL_CPSETP(9)},
181 	{EMAC_QSERDES_COM_PLL_CRCTRL, PLL_RCTRL(15) | PLL_CCTRL(11)},
182 	{EMAC_QSERDES_COM_PLL_CNTRL, OCP_EN | PLL_DIV_FFEN | PLL_DIV_ORD},
183 	{EMAC_QSERDES_COM_DEC_START1, DEC_START1_MUX | DEC_START1(2)},
184 	{EMAC_QSERDES_COM_DEC_START2, DEC_START2_MUX | DEC_START2},
185 	{EMAC_QSERDES_COM_DIV_FRAC_START1,
186 		DIV_FRAC_START_MUX | DIV_FRAC_START(85)},
187 	{EMAC_QSERDES_COM_DIV_FRAC_START2,
188 		DIV_FRAC_START_MUX | DIV_FRAC_START(42)},
189 	{EMAC_QSERDES_COM_DIV_FRAC_START3,
190 		DIV_FRAC_START3_MUX | DIV_FRAC_START3(3)},
191 	{EMAC_QSERDES_COM_PLLLOCK_CMP1, PLLLOCK_CMP(43)},
192 	{EMAC_QSERDES_COM_PLLLOCK_CMP2, PLLLOCK_CMP(104)},
193 	{EMAC_QSERDES_COM_PLLLOCK_CMP3, PLLLOCK_CMP(0)},
194 	{EMAC_QSERDES_COM_PLLLOCK_CMP_EN, PLLLOCK_CMP_EN},
195 	{EMAC_QSERDES_COM_RESETSM_CNTRL, FRQ_TUNE_MODE},
196 };
197 
198 static const struct emac_reg_write cdr_setting[] = {
199 	{EMAC_QSERDES_RX_CDR_CONTROL,
200 		SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(2)},
201 	{EMAC_QSERDES_RX_CDR_CONTROL2,
202 		SECONDORDERENABLE | FIRSTORDER_THRESH(3) | SECONDORDERGAIN(4)},
203 };
204 
205 static const struct emac_reg_write tx_rx_setting[] = {
206 	{EMAC_QSERDES_TX_BIST_MODE_LANENO, 0},
207 	{EMAC_QSERDES_TX_TX_DRV_LVL, TX_DRV_LVL_MUX | TX_DRV_LVL(15)},
208 	{EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN, EMP_EN_MUX | EMP_EN},
209 	{EMAC_QSERDES_TX_TX_EMP_POST1_LVL,
210 		TX_EMP_POST1_LVL_MUX | TX_EMP_POST1_LVL(1)},
211 	{EMAC_QSERDES_RX_RX_EQ_GAIN12, RX_EQ_GAIN2(15) | RX_EQ_GAIN1(15)},
212 	{EMAC_QSERDES_TX_LANE_MODE, LANE_MODE(8)},
213 };
214 
215 int emac_sgmii_init_fsm9900(struct emac_adapter *adpt)
216 {
217 	struct emac_sgmii *phy = &adpt->phy;
218 	unsigned int i;
219 
220 	emac_reg_write_all(phy->base, physical_coding_sublayer_programming,
221 			   ARRAY_SIZE(physical_coding_sublayer_programming));
222 	emac_reg_write_all(phy->base, sysclk_refclk_setting,
223 			   ARRAY_SIZE(sysclk_refclk_setting));
224 	emac_reg_write_all(phy->base, pll_setting, ARRAY_SIZE(pll_setting));
225 	emac_reg_write_all(phy->base, cdr_setting, ARRAY_SIZE(cdr_setting));
226 	emac_reg_write_all(phy->base, tx_rx_setting, ARRAY_SIZE(tx_rx_setting));
227 
228 	/* Power up the Ser/Des engine */
229 	writel(SERDES_START, phy->base + EMAC_SGMII_PHY_SERDES_START);
230 
231 	for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
232 		if (readl(phy->base + EMAC_QSERDES_COM_RESET_SM) & READY)
233 			break;
234 		usleep_range(100, 200);
235 	}
236 
237 	if (i == SERDES_START_WAIT_TIMES) {
238 		netdev_err(adpt->netdev, "error: ser/des failed to start\n");
239 		return -EIO;
240 	}
241 	/* Mask out all the SGMII Interrupt */
242 	writel(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
243 
244 	return 0;
245 }
246