1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
2  *
3  * This program is free software; you can redistribute it and/or modify
4  * it under the terms of the GNU General Public License version 2 and
5  * only version 2 as published by the Free Software Foundation.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  */
12 
13 /* Qualcomm Technologies, Inc. EMAC PHY Controller driver.
14  */
15 
16 #include <linux/of_mdio.h>
17 #include <linux/phy.h>
18 #include <linux/iopoll.h>
19 #include <linux/acpi.h>
20 #include "emac.h"
21 
22 /* EMAC base register offsets */
23 #define EMAC_MDIO_CTRL                                        0x001414
24 #define EMAC_PHY_STS                                          0x001418
25 #define EMAC_MDIO_EX_CTRL                                     0x001440
26 
27 /* EMAC_MDIO_CTRL */
28 #define MDIO_MODE                                              BIT(30)
29 #define MDIO_PR                                                BIT(29)
30 #define MDIO_AP_EN                                             BIT(28)
31 #define MDIO_BUSY                                              BIT(27)
32 #define MDIO_CLK_SEL_BMSK                                    0x7000000
33 #define MDIO_CLK_SEL_SHFT                                           24
34 #define MDIO_START                                             BIT(23)
35 #define SUP_PREAMBLE                                           BIT(22)
36 #define MDIO_RD_NWR                                            BIT(21)
37 #define MDIO_REG_ADDR_BMSK                                    0x1f0000
38 #define MDIO_REG_ADDR_SHFT                                          16
39 #define MDIO_DATA_BMSK                                          0xffff
40 #define MDIO_DATA_SHFT                                               0
41 
42 /* EMAC_PHY_STS */
43 #define PHY_ADDR_BMSK                                         0x1f0000
44 #define PHY_ADDR_SHFT                                               16
45 
46 #define MDIO_CLK_25_4                                                0
47 #define MDIO_CLK_25_28                                               7
48 
49 #define MDIO_WAIT_TIMES                                           1000
50 #define MDIO_STATUS_DELAY_TIME                                       1
51 
52 static int emac_mdio_read(struct mii_bus *bus, int addr, int regnum)
53 {
54 	struct emac_adapter *adpt = bus->priv;
55 	u32 reg;
56 
57 	emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK,
58 			  (addr << PHY_ADDR_SHFT));
59 
60 	reg = SUP_PREAMBLE |
61 	      ((MDIO_CLK_25_4 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) |
62 	      ((regnum << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) |
63 	      MDIO_START | MDIO_RD_NWR;
64 
65 	writel(reg, adpt->base + EMAC_MDIO_CTRL);
66 
67 	if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg,
68 			       !(reg & (MDIO_START | MDIO_BUSY)),
69 			       MDIO_STATUS_DELAY_TIME, MDIO_WAIT_TIMES * 100))
70 		return -EIO;
71 
72 	return (reg >> MDIO_DATA_SHFT) & MDIO_DATA_BMSK;
73 }
74 
75 static int emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
76 {
77 	struct emac_adapter *adpt = bus->priv;
78 	u32 reg;
79 
80 	emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK,
81 			  (addr << PHY_ADDR_SHFT));
82 
83 	reg = SUP_PREAMBLE |
84 		((MDIO_CLK_25_4 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) |
85 		((regnum << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) |
86 		((val << MDIO_DATA_SHFT) & MDIO_DATA_BMSK) |
87 		MDIO_START;
88 
89 	writel(reg, adpt->base + EMAC_MDIO_CTRL);
90 
91 	if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg,
92 			       !(reg & (MDIO_START | MDIO_BUSY)),
93 			       MDIO_STATUS_DELAY_TIME, MDIO_WAIT_TIMES * 100))
94 		return -EIO;
95 
96 	return 0;
97 }
98 
99 /* Configure the MDIO bus and connect the external PHY */
100 int emac_phy_config(struct platform_device *pdev, struct emac_adapter *adpt)
101 {
102 	struct device_node *np = pdev->dev.of_node;
103 	struct mii_bus *mii_bus;
104 	int ret;
105 
106 	/* Create the mii_bus object for talking to the MDIO bus */
107 	adpt->mii_bus = mii_bus = devm_mdiobus_alloc(&pdev->dev);
108 	if (!mii_bus)
109 		return -ENOMEM;
110 
111 	mii_bus->name = "emac-mdio";
112 	snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
113 	mii_bus->read = emac_mdio_read;
114 	mii_bus->write = emac_mdio_write;
115 	mii_bus->parent = &pdev->dev;
116 	mii_bus->priv = adpt;
117 
118 	if (has_acpi_companion(&pdev->dev)) {
119 		u32 phy_addr;
120 
121 		ret = mdiobus_register(mii_bus);
122 		if (ret) {
123 			dev_err(&pdev->dev, "could not register mdio bus\n");
124 			return ret;
125 		}
126 		ret = device_property_read_u32(&pdev->dev, "phy-channel",
127 					       &phy_addr);
128 		if (ret)
129 			/* If we can't read a valid phy address, then assume
130 			 * that there is only one phy on this mdio bus.
131 			 */
132 			adpt->phydev = phy_find_first(mii_bus);
133 		else
134 			adpt->phydev = mdiobus_get_phy(mii_bus, phy_addr);
135 
136 		/* of_phy_find_device() claims a reference to the phydev,
137 		 * so we do that here manually as well. When the driver
138 		 * later unloads, it can unilaterally drop the reference
139 		 * without worrying about ACPI vs DT.
140 		 */
141 		if (adpt->phydev)
142 			get_device(&adpt->phydev->mdio.dev);
143 	} else {
144 		struct device_node *phy_np;
145 
146 		ret = of_mdiobus_register(mii_bus, np);
147 		if (ret) {
148 			dev_err(&pdev->dev, "could not register mdio bus\n");
149 			return ret;
150 		}
151 
152 		phy_np = of_parse_phandle(np, "phy-handle", 0);
153 		adpt->phydev = of_phy_find_device(phy_np);
154 		of_node_put(phy_np);
155 	}
156 
157 	if (!adpt->phydev) {
158 		dev_err(&pdev->dev, "could not find external phy\n");
159 		mdiobus_unregister(mii_bus);
160 		return -ENODEV;
161 	}
162 
163 	return 0;
164 }
165