1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
2  *
3  * This program is free software; you can redistribute it and/or modify
4  * it under the terms of the GNU General Public License version 2 and
5  * only version 2 as published by the Free Software Foundation.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  */
12 
13 /* Qualcomm Technologies, Inc. EMAC PHY Controller driver.
14  */
15 
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_net.h>
19 #include <linux/of_mdio.h>
20 #include <linux/phy.h>
21 #include <linux/iopoll.h>
22 #include <linux/acpi.h>
23 #include "emac.h"
24 #include "emac-mac.h"
25 #include "emac-phy.h"
26 #include "emac-sgmii.h"
27 
28 /* EMAC base register offsets */
29 #define EMAC_MDIO_CTRL                                        0x001414
30 #define EMAC_PHY_STS                                          0x001418
31 #define EMAC_MDIO_EX_CTRL                                     0x001440
32 
33 /* EMAC_MDIO_CTRL */
34 #define MDIO_MODE                                              BIT(30)
35 #define MDIO_PR                                                BIT(29)
36 #define MDIO_AP_EN                                             BIT(28)
37 #define MDIO_BUSY                                              BIT(27)
38 #define MDIO_CLK_SEL_BMSK                                    0x7000000
39 #define MDIO_CLK_SEL_SHFT                                           24
40 #define MDIO_START                                             BIT(23)
41 #define SUP_PREAMBLE                                           BIT(22)
42 #define MDIO_RD_NWR                                            BIT(21)
43 #define MDIO_REG_ADDR_BMSK                                    0x1f0000
44 #define MDIO_REG_ADDR_SHFT                                          16
45 #define MDIO_DATA_BMSK                                          0xffff
46 #define MDIO_DATA_SHFT                                               0
47 
48 /* EMAC_PHY_STS */
49 #define PHY_ADDR_BMSK                                         0x1f0000
50 #define PHY_ADDR_SHFT                                               16
51 
52 #define MDIO_CLK_25_4                                                0
53 #define MDIO_CLK_25_28                                               7
54 
55 #define MDIO_WAIT_TIMES                                           1000
56 
57 #define EMAC_LINK_SPEED_DEFAULT (\
58 		EMAC_LINK_SPEED_10_HALF  |\
59 		EMAC_LINK_SPEED_10_FULL  |\
60 		EMAC_LINK_SPEED_100_HALF |\
61 		EMAC_LINK_SPEED_100_FULL |\
62 		EMAC_LINK_SPEED_1GB_FULL)
63 
64 /**
65  * emac_phy_mdio_autopoll_disable() - disable mdio autopoll
66  * @adpt: the emac adapter
67  *
68  * The autopoll feature takes over the MDIO bus.  In order for
69  * the PHY driver to be able to talk to the PHY over the MDIO
70  * bus, we need to temporarily disable the autopoll feature.
71  */
72 static int emac_phy_mdio_autopoll_disable(struct emac_adapter *adpt)
73 {
74 	u32 val;
75 
76 	/* disable autopoll */
77 	emac_reg_update32(adpt->base + EMAC_MDIO_CTRL, MDIO_AP_EN, 0);
78 
79 	/* wait for any mdio polling to complete */
80 	if (!readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, val,
81 				!(val & MDIO_BUSY), 100, MDIO_WAIT_TIMES * 100))
82 		return 0;
83 
84 	/* failed to disable; ensure it is enabled before returning */
85 	emac_reg_update32(adpt->base + EMAC_MDIO_CTRL, 0, MDIO_AP_EN);
86 
87 	return -EBUSY;
88 }
89 
90 /**
91  * emac_phy_mdio_autopoll_disable() - disable mdio autopoll
92  * @adpt: the emac adapter
93  *
94  * The EMAC has the ability to poll the external PHY on the MDIO
95  * bus for link state changes.  This eliminates the need for the
96  * driver to poll the phy.  If if the link state does change,
97  * the EMAC issues an interrupt on behalf of the PHY.
98  */
99 static void emac_phy_mdio_autopoll_enable(struct emac_adapter *adpt)
100 {
101 	emac_reg_update32(adpt->base + EMAC_MDIO_CTRL, 0, MDIO_AP_EN);
102 }
103 
104 static int emac_mdio_read(struct mii_bus *bus, int addr, int regnum)
105 {
106 	struct emac_adapter *adpt = bus->priv;
107 	u32 reg;
108 	int ret;
109 
110 	ret = emac_phy_mdio_autopoll_disable(adpt);
111 	if (ret)
112 		return ret;
113 
114 	emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK,
115 			  (addr << PHY_ADDR_SHFT));
116 
117 	reg = SUP_PREAMBLE |
118 	      ((MDIO_CLK_25_4 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) |
119 	      ((regnum << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) |
120 	      MDIO_START | MDIO_RD_NWR;
121 
122 	writel(reg, adpt->base + EMAC_MDIO_CTRL);
123 
124 	if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg,
125 			       !(reg & (MDIO_START | MDIO_BUSY)),
126 			       100, MDIO_WAIT_TIMES * 100))
127 		ret = -EIO;
128 	else
129 		ret = (reg >> MDIO_DATA_SHFT) & MDIO_DATA_BMSK;
130 
131 	emac_phy_mdio_autopoll_enable(adpt);
132 
133 	return ret;
134 }
135 
136 static int emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
137 {
138 	struct emac_adapter *adpt = bus->priv;
139 	u32 reg;
140 	int ret;
141 
142 	ret = emac_phy_mdio_autopoll_disable(adpt);
143 	if (ret)
144 		return ret;
145 
146 	emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK,
147 			  (addr << PHY_ADDR_SHFT));
148 
149 	reg = SUP_PREAMBLE |
150 		((MDIO_CLK_25_4 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) |
151 		((regnum << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) |
152 		((val << MDIO_DATA_SHFT) & MDIO_DATA_BMSK) |
153 		MDIO_START;
154 
155 	writel(reg, adpt->base + EMAC_MDIO_CTRL);
156 
157 	if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg,
158 			       !(reg & (MDIO_START | MDIO_BUSY)), 100,
159 			       MDIO_WAIT_TIMES * 100))
160 		ret = -EIO;
161 
162 	emac_phy_mdio_autopoll_enable(adpt);
163 
164 	return ret;
165 }
166 
167 /* Configure the MDIO bus and connect the external PHY */
168 int emac_phy_config(struct platform_device *pdev, struct emac_adapter *adpt)
169 {
170 	struct device_node *np = pdev->dev.of_node;
171 	struct mii_bus *mii_bus;
172 	int ret;
173 
174 	/* Create the mii_bus object for talking to the MDIO bus */
175 	adpt->mii_bus = mii_bus = devm_mdiobus_alloc(&pdev->dev);
176 	if (!mii_bus)
177 		return -ENOMEM;
178 
179 	mii_bus->name = "emac-mdio";
180 	snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
181 	mii_bus->read = emac_mdio_read;
182 	mii_bus->write = emac_mdio_write;
183 	mii_bus->parent = &pdev->dev;
184 	mii_bus->priv = adpt;
185 
186 	if (has_acpi_companion(&pdev->dev)) {
187 		u32 phy_addr;
188 
189 		ret = mdiobus_register(mii_bus);
190 		if (ret) {
191 			dev_err(&pdev->dev, "could not register mdio bus\n");
192 			return ret;
193 		}
194 		ret = device_property_read_u32(&pdev->dev, "phy-channel",
195 					       &phy_addr);
196 		if (ret)
197 			/* If we can't read a valid phy address, then assume
198 			 * that there is only one phy on this mdio bus.
199 			 */
200 			adpt->phydev = phy_find_first(mii_bus);
201 		else
202 			adpt->phydev = mdiobus_get_phy(mii_bus, phy_addr);
203 
204 	} else {
205 		struct device_node *phy_np;
206 
207 		ret = of_mdiobus_register(mii_bus, np);
208 		if (ret) {
209 			dev_err(&pdev->dev, "could not register mdio bus\n");
210 			return ret;
211 		}
212 
213 		phy_np = of_parse_phandle(np, "phy-handle", 0);
214 		adpt->phydev = of_phy_find_device(phy_np);
215 		of_node_put(phy_np);
216 	}
217 
218 	if (!adpt->phydev) {
219 		dev_err(&pdev->dev, "could not find external phy\n");
220 		mdiobus_unregister(mii_bus);
221 		return -ENODEV;
222 	}
223 
224 	if (adpt->phydev->drv)
225 		phy_attached_print(adpt->phydev, NULL);
226 
227 	return 0;
228 }
229