1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic.h" 9 #include "qlcnic_hdr.h" 10 #include "qlcnic_83xx_hw.h" 11 #include "qlcnic_hw.h" 12 13 #include <net/ip.h> 14 15 #define QLC_83XX_MINIDUMP_FLASH 0x520000 16 #define QLC_83XX_OCM_INDEX 3 17 #define QLC_83XX_PCI_INDEX 0 18 #define QLC_83XX_DMA_ENGINE_INDEX 8 19 20 static const u32 qlcnic_ms_read_data[] = { 21 0x410000A8, 0x410000AC, 0x410000B8, 0x410000BC 22 }; 23 24 #define QLCNIC_DUMP_WCRB BIT_0 25 #define QLCNIC_DUMP_RWCRB BIT_1 26 #define QLCNIC_DUMP_ANDCRB BIT_2 27 #define QLCNIC_DUMP_ORCRB BIT_3 28 #define QLCNIC_DUMP_POLLCRB BIT_4 29 #define QLCNIC_DUMP_RD_SAVE BIT_5 30 #define QLCNIC_DUMP_WRT_SAVED BIT_6 31 #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7 32 #define QLCNIC_DUMP_SKIP BIT_7 33 34 #define QLCNIC_DUMP_MASK_MAX 0xff 35 36 struct qlcnic_pex_dma_descriptor { 37 u32 read_data_size; 38 u32 dma_desc_cmd; 39 u32 src_addr_low; 40 u32 src_addr_high; 41 u32 dma_bus_addr_low; 42 u32 dma_bus_addr_high; 43 u32 rsvd[6]; 44 } __packed; 45 46 struct qlcnic_common_entry_hdr { 47 u32 type; 48 u32 offset; 49 u32 cap_size; 50 u8 mask; 51 u8 rsvd[2]; 52 u8 flags; 53 } __packed; 54 55 struct __crb { 56 u32 addr; 57 u8 stride; 58 u8 rsvd1[3]; 59 u32 data_size; 60 u32 no_ops; 61 u32 rsvd2[4]; 62 } __packed; 63 64 struct __ctrl { 65 u32 addr; 66 u8 stride; 67 u8 index_a; 68 u16 timeout; 69 u32 data_size; 70 u32 no_ops; 71 u8 opcode; 72 u8 index_v; 73 u8 shl_val; 74 u8 shr_val; 75 u32 val1; 76 u32 val2; 77 u32 val3; 78 } __packed; 79 80 struct __cache { 81 u32 addr; 82 u16 stride; 83 u16 init_tag_val; 84 u32 size; 85 u32 no_ops; 86 u32 ctrl_addr; 87 u32 ctrl_val; 88 u32 read_addr; 89 u8 read_addr_stride; 90 u8 read_addr_num; 91 u8 rsvd1[2]; 92 } __packed; 93 94 struct __ocm { 95 u8 rsvd[8]; 96 u32 size; 97 u32 no_ops; 98 u8 rsvd1[8]; 99 u32 read_addr; 100 u32 read_addr_stride; 101 } __packed; 102 103 struct __mem { 104 u32 desc_card_addr; 105 u32 dma_desc_cmd; 106 u32 start_dma_cmd; 107 u32 rsvd[3]; 108 u32 addr; 109 u32 size; 110 } __packed; 111 112 struct __mux { 113 u32 addr; 114 u8 rsvd[4]; 115 u32 size; 116 u32 no_ops; 117 u32 val; 118 u32 val_stride; 119 u32 read_addr; 120 u8 rsvd2[4]; 121 } __packed; 122 123 struct __queue { 124 u32 sel_addr; 125 u16 stride; 126 u8 rsvd[2]; 127 u32 size; 128 u32 no_ops; 129 u8 rsvd2[8]; 130 u32 read_addr; 131 u8 read_addr_stride; 132 u8 read_addr_cnt; 133 u8 rsvd3[2]; 134 } __packed; 135 136 struct __pollrd { 137 u32 sel_addr; 138 u32 read_addr; 139 u32 sel_val; 140 u16 sel_val_stride; 141 u16 no_ops; 142 u32 poll_wait; 143 u32 poll_mask; 144 u32 data_size; 145 u8 rsvd[4]; 146 } __packed; 147 148 struct __mux2 { 149 u32 sel_addr1; 150 u32 sel_addr2; 151 u32 sel_val1; 152 u32 sel_val2; 153 u32 no_ops; 154 u32 sel_val_mask; 155 u32 read_addr; 156 u8 sel_val_stride; 157 u8 data_size; 158 u8 rsvd[2]; 159 } __packed; 160 161 struct __pollrdmwr { 162 u32 addr1; 163 u32 addr2; 164 u32 val1; 165 u32 val2; 166 u32 poll_wait; 167 u32 poll_mask; 168 u32 mod_mask; 169 u32 data_size; 170 } __packed; 171 172 struct qlcnic_dump_entry { 173 struct qlcnic_common_entry_hdr hdr; 174 union { 175 struct __crb crb; 176 struct __cache cache; 177 struct __ocm ocm; 178 struct __mem mem; 179 struct __mux mux; 180 struct __queue que; 181 struct __ctrl ctrl; 182 struct __pollrdmwr pollrdmwr; 183 struct __mux2 mux2; 184 struct __pollrd pollrd; 185 } region; 186 } __packed; 187 188 enum qlcnic_minidump_opcode { 189 QLCNIC_DUMP_NOP = 0, 190 QLCNIC_DUMP_READ_CRB = 1, 191 QLCNIC_DUMP_READ_MUX = 2, 192 QLCNIC_DUMP_QUEUE = 3, 193 QLCNIC_DUMP_BRD_CONFIG = 4, 194 QLCNIC_DUMP_READ_OCM = 6, 195 QLCNIC_DUMP_PEG_REG = 7, 196 QLCNIC_DUMP_L1_DTAG = 8, 197 QLCNIC_DUMP_L1_ITAG = 9, 198 QLCNIC_DUMP_L1_DATA = 11, 199 QLCNIC_DUMP_L1_INST = 12, 200 QLCNIC_DUMP_L2_DTAG = 21, 201 QLCNIC_DUMP_L2_ITAG = 22, 202 QLCNIC_DUMP_L2_DATA = 23, 203 QLCNIC_DUMP_L2_INST = 24, 204 QLCNIC_DUMP_POLL_RD = 35, 205 QLCNIC_READ_MUX2 = 36, 206 QLCNIC_READ_POLLRDMWR = 37, 207 QLCNIC_DUMP_READ_ROM = 71, 208 QLCNIC_DUMP_READ_MEM = 72, 209 QLCNIC_DUMP_READ_CTRL = 98, 210 QLCNIC_DUMP_TLHDR = 99, 211 QLCNIC_DUMP_RDEND = 255 212 }; 213 214 inline u32 qlcnic_82xx_get_saved_state(void *t_hdr, u32 index) 215 { 216 struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr; 217 218 return hdr->saved_state[index]; 219 } 220 221 inline void qlcnic_82xx_set_saved_state(void *t_hdr, u32 index, 222 u32 value) 223 { 224 struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr; 225 226 hdr->saved_state[index] = value; 227 } 228 229 void qlcnic_82xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *fw_dump) 230 { 231 struct qlcnic_82xx_dump_template_hdr *hdr; 232 233 hdr = fw_dump->tmpl_hdr; 234 fw_dump->tmpl_hdr_size = hdr->size; 235 fw_dump->version = hdr->version; 236 fw_dump->num_entries = hdr->num_entries; 237 fw_dump->offset = hdr->offset; 238 239 hdr->drv_cap_mask = hdr->cap_mask; 240 fw_dump->cap_mask = hdr->cap_mask; 241 } 242 243 inline u32 qlcnic_82xx_get_cap_size(void *t_hdr, int index) 244 { 245 struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr; 246 247 return hdr->cap_sizes[index]; 248 } 249 250 void qlcnic_82xx_set_sys_info(void *t_hdr, int idx, u32 value) 251 { 252 struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr; 253 254 hdr->sys_info[idx] = value; 255 } 256 257 void qlcnic_82xx_store_cap_mask(void *tmpl_hdr, u32 mask) 258 { 259 struct qlcnic_82xx_dump_template_hdr *hdr = tmpl_hdr; 260 261 hdr->drv_cap_mask = mask; 262 } 263 264 inline u32 qlcnic_83xx_get_saved_state(void *t_hdr, u32 index) 265 { 266 struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr; 267 268 return hdr->saved_state[index]; 269 } 270 271 inline void qlcnic_83xx_set_saved_state(void *t_hdr, u32 index, 272 u32 value) 273 { 274 struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr; 275 276 hdr->saved_state[index] = value; 277 } 278 279 void qlcnic_83xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *fw_dump) 280 { 281 struct qlcnic_83xx_dump_template_hdr *hdr; 282 283 hdr = fw_dump->tmpl_hdr; 284 fw_dump->tmpl_hdr_size = hdr->size; 285 fw_dump->version = hdr->version; 286 fw_dump->num_entries = hdr->num_entries; 287 fw_dump->offset = hdr->offset; 288 289 hdr->drv_cap_mask = hdr->cap_mask; 290 fw_dump->cap_mask = hdr->cap_mask; 291 } 292 293 inline u32 qlcnic_83xx_get_cap_size(void *t_hdr, int index) 294 { 295 struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr; 296 297 return hdr->cap_sizes[index]; 298 } 299 300 void qlcnic_83xx_set_sys_info(void *t_hdr, int idx, u32 value) 301 { 302 struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr; 303 304 hdr->sys_info[idx] = value; 305 } 306 307 void qlcnic_83xx_store_cap_mask(void *tmpl_hdr, u32 mask) 308 { 309 struct qlcnic_83xx_dump_template_hdr *hdr; 310 311 hdr = tmpl_hdr; 312 hdr->drv_cap_mask = mask; 313 } 314 315 struct qlcnic_dump_operations { 316 enum qlcnic_minidump_opcode opcode; 317 u32 (*handler)(struct qlcnic_adapter *, struct qlcnic_dump_entry *, 318 __le32 *); 319 }; 320 321 static u32 qlcnic_dump_crb(struct qlcnic_adapter *adapter, 322 struct qlcnic_dump_entry *entry, __le32 *buffer) 323 { 324 int i; 325 u32 addr, data; 326 struct __crb *crb = &entry->region.crb; 327 328 addr = crb->addr; 329 330 for (i = 0; i < crb->no_ops; i++) { 331 data = qlcnic_ind_rd(adapter, addr); 332 *buffer++ = cpu_to_le32(addr); 333 *buffer++ = cpu_to_le32(data); 334 addr += crb->stride; 335 } 336 return crb->no_ops * 2 * sizeof(u32); 337 } 338 339 static u32 qlcnic_dump_ctrl(struct qlcnic_adapter *adapter, 340 struct qlcnic_dump_entry *entry, __le32 *buffer) 341 { 342 void *hdr = adapter->ahw->fw_dump.tmpl_hdr; 343 struct __ctrl *ctr = &entry->region.ctrl; 344 int i, k, timeout = 0; 345 u32 addr, data, temp; 346 u8 no_ops; 347 348 addr = ctr->addr; 349 no_ops = ctr->no_ops; 350 351 for (i = 0; i < no_ops; i++) { 352 k = 0; 353 for (k = 0; k < 8; k++) { 354 if (!(ctr->opcode & (1 << k))) 355 continue; 356 switch (1 << k) { 357 case QLCNIC_DUMP_WCRB: 358 qlcnic_ind_wr(adapter, addr, ctr->val1); 359 break; 360 case QLCNIC_DUMP_RWCRB: 361 data = qlcnic_ind_rd(adapter, addr); 362 qlcnic_ind_wr(adapter, addr, data); 363 break; 364 case QLCNIC_DUMP_ANDCRB: 365 data = qlcnic_ind_rd(adapter, addr); 366 qlcnic_ind_wr(adapter, addr, 367 (data & ctr->val2)); 368 break; 369 case QLCNIC_DUMP_ORCRB: 370 data = qlcnic_ind_rd(adapter, addr); 371 qlcnic_ind_wr(adapter, addr, 372 (data | ctr->val3)); 373 break; 374 case QLCNIC_DUMP_POLLCRB: 375 while (timeout <= ctr->timeout) { 376 data = qlcnic_ind_rd(adapter, addr); 377 if ((data & ctr->val2) == ctr->val1) 378 break; 379 usleep_range(1000, 2000); 380 timeout++; 381 } 382 if (timeout > ctr->timeout) { 383 dev_info(&adapter->pdev->dev, 384 "Timed out, aborting poll CRB\n"); 385 return -EINVAL; 386 } 387 break; 388 case QLCNIC_DUMP_RD_SAVE: 389 temp = ctr->index_a; 390 if (temp) 391 addr = qlcnic_get_saved_state(adapter, 392 hdr, 393 temp); 394 data = qlcnic_ind_rd(adapter, addr); 395 qlcnic_set_saved_state(adapter, hdr, 396 ctr->index_v, data); 397 break; 398 case QLCNIC_DUMP_WRT_SAVED: 399 temp = ctr->index_v; 400 if (temp) 401 data = qlcnic_get_saved_state(adapter, 402 hdr, 403 temp); 404 else 405 data = ctr->val1; 406 407 temp = ctr->index_a; 408 if (temp) 409 addr = qlcnic_get_saved_state(adapter, 410 hdr, 411 temp); 412 qlcnic_ind_wr(adapter, addr, data); 413 break; 414 case QLCNIC_DUMP_MOD_SAVE_ST: 415 data = qlcnic_get_saved_state(adapter, hdr, 416 ctr->index_v); 417 data <<= ctr->shl_val; 418 data >>= ctr->shr_val; 419 if (ctr->val2) 420 data &= ctr->val2; 421 data |= ctr->val3; 422 data += ctr->val1; 423 qlcnic_set_saved_state(adapter, hdr, 424 ctr->index_v, data); 425 break; 426 default: 427 dev_info(&adapter->pdev->dev, 428 "Unknown opcode\n"); 429 break; 430 } 431 } 432 addr += ctr->stride; 433 } 434 return 0; 435 } 436 437 static u32 qlcnic_dump_mux(struct qlcnic_adapter *adapter, 438 struct qlcnic_dump_entry *entry, __le32 *buffer) 439 { 440 int loop; 441 u32 val, data = 0; 442 struct __mux *mux = &entry->region.mux; 443 444 val = mux->val; 445 for (loop = 0; loop < mux->no_ops; loop++) { 446 qlcnic_ind_wr(adapter, mux->addr, val); 447 data = qlcnic_ind_rd(adapter, mux->read_addr); 448 *buffer++ = cpu_to_le32(val); 449 *buffer++ = cpu_to_le32(data); 450 val += mux->val_stride; 451 } 452 return 2 * mux->no_ops * sizeof(u32); 453 } 454 455 static u32 qlcnic_dump_que(struct qlcnic_adapter *adapter, 456 struct qlcnic_dump_entry *entry, __le32 *buffer) 457 { 458 int i, loop; 459 u32 cnt, addr, data, que_id = 0; 460 struct __queue *que = &entry->region.que; 461 462 addr = que->read_addr; 463 cnt = que->read_addr_cnt; 464 465 for (loop = 0; loop < que->no_ops; loop++) { 466 qlcnic_ind_wr(adapter, que->sel_addr, que_id); 467 addr = que->read_addr; 468 for (i = 0; i < cnt; i++) { 469 data = qlcnic_ind_rd(adapter, addr); 470 *buffer++ = cpu_to_le32(data); 471 addr += que->read_addr_stride; 472 } 473 que_id += que->stride; 474 } 475 return que->no_ops * cnt * sizeof(u32); 476 } 477 478 static u32 qlcnic_dump_ocm(struct qlcnic_adapter *adapter, 479 struct qlcnic_dump_entry *entry, __le32 *buffer) 480 { 481 int i; 482 u32 data; 483 void __iomem *addr; 484 struct __ocm *ocm = &entry->region.ocm; 485 486 addr = adapter->ahw->pci_base0 + ocm->read_addr; 487 for (i = 0; i < ocm->no_ops; i++) { 488 data = readl(addr); 489 *buffer++ = cpu_to_le32(data); 490 addr += ocm->read_addr_stride; 491 } 492 return ocm->no_ops * sizeof(u32); 493 } 494 495 static u32 qlcnic_read_rom(struct qlcnic_adapter *adapter, 496 struct qlcnic_dump_entry *entry, __le32 *buffer) 497 { 498 int i, count = 0; 499 u32 fl_addr, size, val, lck_val, addr; 500 struct __mem *rom = &entry->region.mem; 501 502 fl_addr = rom->addr; 503 size = rom->size / 4; 504 lock_try: 505 lck_val = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK); 506 if (!lck_val && count < MAX_CTL_CHECK) { 507 usleep_range(10000, 11000); 508 count++; 509 goto lock_try; 510 } 511 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 512 adapter->ahw->pci_func); 513 for (i = 0; i < size; i++) { 514 addr = fl_addr & 0xFFFF0000; 515 qlcnic_ind_wr(adapter, FLASH_ROM_WINDOW, addr); 516 addr = LSW(fl_addr) + FLASH_ROM_DATA; 517 val = qlcnic_ind_rd(adapter, addr); 518 fl_addr += 4; 519 *buffer++ = cpu_to_le32(val); 520 } 521 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK); 522 return rom->size; 523 } 524 525 static u32 qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter, 526 struct qlcnic_dump_entry *entry, __le32 *buffer) 527 { 528 int i; 529 u32 cnt, val, data, addr; 530 struct __cache *l1 = &entry->region.cache; 531 532 val = l1->init_tag_val; 533 534 for (i = 0; i < l1->no_ops; i++) { 535 qlcnic_ind_wr(adapter, l1->addr, val); 536 qlcnic_ind_wr(adapter, l1->ctrl_addr, LSW(l1->ctrl_val)); 537 addr = l1->read_addr; 538 cnt = l1->read_addr_num; 539 while (cnt) { 540 data = qlcnic_ind_rd(adapter, addr); 541 *buffer++ = cpu_to_le32(data); 542 addr += l1->read_addr_stride; 543 cnt--; 544 } 545 val += l1->stride; 546 } 547 return l1->no_ops * l1->read_addr_num * sizeof(u32); 548 } 549 550 static u32 qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter, 551 struct qlcnic_dump_entry *entry, __le32 *buffer) 552 { 553 int i; 554 u32 cnt, val, data, addr; 555 u8 poll_mask, poll_to, time_out = 0; 556 struct __cache *l2 = &entry->region.cache; 557 558 val = l2->init_tag_val; 559 poll_mask = LSB(MSW(l2->ctrl_val)); 560 poll_to = MSB(MSW(l2->ctrl_val)); 561 562 for (i = 0; i < l2->no_ops; i++) { 563 qlcnic_ind_wr(adapter, l2->addr, val); 564 if (LSW(l2->ctrl_val)) 565 qlcnic_ind_wr(adapter, l2->ctrl_addr, 566 LSW(l2->ctrl_val)); 567 if (!poll_mask) 568 goto skip_poll; 569 do { 570 data = qlcnic_ind_rd(adapter, l2->ctrl_addr); 571 if (!(data & poll_mask)) 572 break; 573 usleep_range(1000, 2000); 574 time_out++; 575 } while (time_out <= poll_to); 576 577 if (time_out > poll_to) { 578 dev_err(&adapter->pdev->dev, 579 "Timeout exceeded in %s, aborting dump\n", 580 __func__); 581 return -EINVAL; 582 } 583 skip_poll: 584 addr = l2->read_addr; 585 cnt = l2->read_addr_num; 586 while (cnt) { 587 data = qlcnic_ind_rd(adapter, addr); 588 *buffer++ = cpu_to_le32(data); 589 addr += l2->read_addr_stride; 590 cnt--; 591 } 592 val += l2->stride; 593 } 594 return l2->no_ops * l2->read_addr_num * sizeof(u32); 595 } 596 597 static u32 qlcnic_read_memory_test_agent(struct qlcnic_adapter *adapter, 598 struct __mem *mem, __le32 *buffer, 599 int *ret) 600 { 601 u32 addr, data, test; 602 int i, reg_read; 603 604 reg_read = mem->size; 605 addr = mem->addr; 606 /* check for data size of multiple of 16 and 16 byte alignment */ 607 if ((addr & 0xf) || (reg_read%16)) { 608 dev_info(&adapter->pdev->dev, 609 "Unaligned memory addr:0x%x size:0x%x\n", 610 addr, reg_read); 611 *ret = -EINVAL; 612 return 0; 613 } 614 615 mutex_lock(&adapter->ahw->mem_lock); 616 617 while (reg_read != 0) { 618 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr); 619 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0); 620 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_START_ENABLE); 621 622 for (i = 0; i < MAX_CTL_CHECK; i++) { 623 test = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL); 624 if (!(test & TA_CTL_BUSY)) 625 break; 626 } 627 if (i == MAX_CTL_CHECK) { 628 if (printk_ratelimit()) { 629 dev_err(&adapter->pdev->dev, 630 "failed to read through agent\n"); 631 *ret = -EIO; 632 goto out; 633 } 634 } 635 for (i = 0; i < 4; i++) { 636 data = qlcnic_ind_rd(adapter, qlcnic_ms_read_data[i]); 637 *buffer++ = cpu_to_le32(data); 638 } 639 addr += 16; 640 reg_read -= 16; 641 ret += 16; 642 } 643 out: 644 mutex_unlock(&adapter->ahw->mem_lock); 645 return mem->size; 646 } 647 648 /* DMA register base address */ 649 #define QLC_DMA_REG_BASE_ADDR(dma_no) (0x77320000 + (dma_no * 0x10000)) 650 651 /* DMA register offsets w.r.t base address */ 652 #define QLC_DMA_CMD_BUFF_ADDR_LOW 0 653 #define QLC_DMA_CMD_BUFF_ADDR_HI 4 654 #define QLC_DMA_CMD_STATUS_CTRL 8 655 656 #define QLC_PEX_DMA_READ_SIZE (PAGE_SIZE * 16) 657 658 static int qlcnic_start_pex_dma(struct qlcnic_adapter *adapter, 659 struct __mem *mem) 660 { 661 struct qlcnic_83xx_dump_template_hdr *tmpl_hdr; 662 struct device *dev = &adapter->pdev->dev; 663 u32 dma_no, dma_base_addr, temp_addr; 664 int i, ret, dma_sts; 665 666 tmpl_hdr = adapter->ahw->fw_dump.tmpl_hdr; 667 dma_no = tmpl_hdr->saved_state[QLC_83XX_DMA_ENGINE_INDEX]; 668 dma_base_addr = QLC_DMA_REG_BASE_ADDR(dma_no); 669 670 temp_addr = dma_base_addr + QLC_DMA_CMD_BUFF_ADDR_LOW; 671 ret = qlcnic_83xx_wrt_reg_indirect(adapter, temp_addr, 672 mem->desc_card_addr); 673 if (ret) 674 return ret; 675 676 temp_addr = dma_base_addr + QLC_DMA_CMD_BUFF_ADDR_HI; 677 ret = qlcnic_83xx_wrt_reg_indirect(adapter, temp_addr, 0); 678 if (ret) 679 return ret; 680 681 temp_addr = dma_base_addr + QLC_DMA_CMD_STATUS_CTRL; 682 ret = qlcnic_83xx_wrt_reg_indirect(adapter, temp_addr, 683 mem->start_dma_cmd); 684 if (ret) 685 return ret; 686 687 /* Wait for DMA to complete */ 688 temp_addr = dma_base_addr + QLC_DMA_CMD_STATUS_CTRL; 689 for (i = 0; i < 400; i++) { 690 dma_sts = qlcnic_ind_rd(adapter, temp_addr); 691 692 if (dma_sts & BIT_1) 693 usleep_range(250, 500); 694 else 695 break; 696 } 697 698 if (i >= 400) { 699 dev_info(dev, "PEX DMA operation timed out"); 700 ret = -EIO; 701 } 702 703 return ret; 704 } 705 706 static u32 qlcnic_read_memory_pexdma(struct qlcnic_adapter *adapter, 707 struct __mem *mem, 708 __le32 *buffer, int *ret) 709 { 710 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump; 711 u32 temp, dma_base_addr, size = 0, read_size = 0; 712 struct qlcnic_pex_dma_descriptor *dma_descr; 713 struct qlcnic_83xx_dump_template_hdr *tmpl_hdr; 714 struct device *dev = &adapter->pdev->dev; 715 dma_addr_t dma_phys_addr; 716 void *dma_buffer; 717 718 tmpl_hdr = fw_dump->tmpl_hdr; 719 720 /* Check if DMA engine is available */ 721 temp = tmpl_hdr->saved_state[QLC_83XX_DMA_ENGINE_INDEX]; 722 dma_base_addr = QLC_DMA_REG_BASE_ADDR(temp); 723 temp = qlcnic_ind_rd(adapter, 724 dma_base_addr + QLC_DMA_CMD_STATUS_CTRL); 725 726 if (!(temp & BIT_31)) { 727 dev_info(dev, "%s: DMA engine is not available\n", __func__); 728 *ret = -EIO; 729 return 0; 730 } 731 732 /* Create DMA descriptor */ 733 dma_descr = kzalloc(sizeof(struct qlcnic_pex_dma_descriptor), 734 GFP_KERNEL); 735 if (!dma_descr) { 736 *ret = -ENOMEM; 737 return 0; 738 } 739 740 /* dma_desc_cmd 0:15 = 0 741 * dma_desc_cmd 16:19 = mem->dma_desc_cmd 0:3 742 * dma_desc_cmd 20:23 = pci function number 743 * dma_desc_cmd 24:31 = mem->dma_desc_cmd 8:15 744 */ 745 dma_phys_addr = fw_dump->phys_addr; 746 dma_buffer = fw_dump->dma_buffer; 747 temp = 0; 748 temp = mem->dma_desc_cmd & 0xff0f; 749 temp |= (adapter->ahw->pci_func & 0xf) << 4; 750 dma_descr->dma_desc_cmd = (temp << 16) & 0xffff0000; 751 dma_descr->dma_bus_addr_low = LSD(dma_phys_addr); 752 dma_descr->dma_bus_addr_high = MSD(dma_phys_addr); 753 dma_descr->src_addr_high = 0; 754 755 /* Collect memory dump using multiple DMA operations if required */ 756 while (read_size < mem->size) { 757 if (mem->size - read_size >= QLC_PEX_DMA_READ_SIZE) 758 size = QLC_PEX_DMA_READ_SIZE; 759 else 760 size = mem->size - read_size; 761 762 dma_descr->src_addr_low = mem->addr + read_size; 763 dma_descr->read_data_size = size; 764 765 /* Write DMA descriptor to MS memory*/ 766 temp = sizeof(struct qlcnic_pex_dma_descriptor) / 16; 767 *ret = qlcnic_83xx_ms_mem_write128(adapter, mem->desc_card_addr, 768 (u32 *)dma_descr, temp); 769 if (*ret) { 770 dev_info(dev, "Failed to write DMA descriptor to MS memory at address 0x%x\n", 771 mem->desc_card_addr); 772 goto free_dma_descr; 773 } 774 775 *ret = qlcnic_start_pex_dma(adapter, mem); 776 if (*ret) { 777 dev_info(dev, "Failed to start PEX DMA operation\n"); 778 goto free_dma_descr; 779 } 780 781 memcpy(buffer, dma_buffer, size); 782 buffer += size / 4; 783 read_size += size; 784 } 785 786 free_dma_descr: 787 kfree(dma_descr); 788 789 return read_size; 790 } 791 792 static u32 qlcnic_read_memory(struct qlcnic_adapter *adapter, 793 struct qlcnic_dump_entry *entry, __le32 *buffer) 794 { 795 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump; 796 struct device *dev = &adapter->pdev->dev; 797 struct __mem *mem = &entry->region.mem; 798 u32 data_size; 799 int ret = 0; 800 801 if (fw_dump->use_pex_dma) { 802 data_size = qlcnic_read_memory_pexdma(adapter, mem, buffer, 803 &ret); 804 if (ret) 805 dev_info(dev, 806 "Failed to read memory dump using PEX DMA: mask[0x%x]\n", 807 entry->hdr.mask); 808 else 809 return data_size; 810 } 811 812 data_size = qlcnic_read_memory_test_agent(adapter, mem, buffer, &ret); 813 if (ret) { 814 dev_info(dev, 815 "Failed to read memory dump using test agent method: mask[0x%x]\n", 816 entry->hdr.mask); 817 return 0; 818 } else { 819 return data_size; 820 } 821 } 822 823 static u32 qlcnic_dump_nop(struct qlcnic_adapter *adapter, 824 struct qlcnic_dump_entry *entry, __le32 *buffer) 825 { 826 entry->hdr.flags |= QLCNIC_DUMP_SKIP; 827 return 0; 828 } 829 830 static int qlcnic_valid_dump_entry(struct device *dev, 831 struct qlcnic_dump_entry *entry, u32 size) 832 { 833 int ret = 1; 834 if (size != entry->hdr.cap_size) { 835 dev_err(dev, 836 "Invalid entry, Type:%d\tMask:%d\tSize:%dCap_size:%d\n", 837 entry->hdr.type, entry->hdr.mask, size, 838 entry->hdr.cap_size); 839 ret = 0; 840 } 841 return ret; 842 } 843 844 static u32 qlcnic_read_pollrdmwr(struct qlcnic_adapter *adapter, 845 struct qlcnic_dump_entry *entry, 846 __le32 *buffer) 847 { 848 struct __pollrdmwr *poll = &entry->region.pollrdmwr; 849 u32 data, wait_count, poll_wait, temp; 850 851 poll_wait = poll->poll_wait; 852 853 qlcnic_ind_wr(adapter, poll->addr1, poll->val1); 854 wait_count = 0; 855 856 while (wait_count < poll_wait) { 857 data = qlcnic_ind_rd(adapter, poll->addr1); 858 if ((data & poll->poll_mask) != 0) 859 break; 860 wait_count++; 861 } 862 863 if (wait_count == poll_wait) { 864 dev_err(&adapter->pdev->dev, 865 "Timeout exceeded in %s, aborting dump\n", 866 __func__); 867 return 0; 868 } 869 870 data = qlcnic_ind_rd(adapter, poll->addr2) & poll->mod_mask; 871 qlcnic_ind_wr(adapter, poll->addr2, data); 872 qlcnic_ind_wr(adapter, poll->addr1, poll->val2); 873 wait_count = 0; 874 875 while (wait_count < poll_wait) { 876 temp = qlcnic_ind_rd(adapter, poll->addr1); 877 if ((temp & poll->poll_mask) != 0) 878 break; 879 wait_count++; 880 } 881 882 *buffer++ = cpu_to_le32(poll->addr2); 883 *buffer++ = cpu_to_le32(data); 884 885 return 2 * sizeof(u32); 886 887 } 888 889 static u32 qlcnic_read_pollrd(struct qlcnic_adapter *adapter, 890 struct qlcnic_dump_entry *entry, __le32 *buffer) 891 { 892 struct __pollrd *pollrd = &entry->region.pollrd; 893 u32 data, wait_count, poll_wait, sel_val; 894 int i; 895 896 poll_wait = pollrd->poll_wait; 897 sel_val = pollrd->sel_val; 898 899 for (i = 0; i < pollrd->no_ops; i++) { 900 qlcnic_ind_wr(adapter, pollrd->sel_addr, sel_val); 901 wait_count = 0; 902 while (wait_count < poll_wait) { 903 data = qlcnic_ind_rd(adapter, pollrd->sel_addr); 904 if ((data & pollrd->poll_mask) != 0) 905 break; 906 wait_count++; 907 } 908 909 if (wait_count == poll_wait) { 910 dev_err(&adapter->pdev->dev, 911 "Timeout exceeded in %s, aborting dump\n", 912 __func__); 913 return 0; 914 } 915 916 data = qlcnic_ind_rd(adapter, pollrd->read_addr); 917 *buffer++ = cpu_to_le32(sel_val); 918 *buffer++ = cpu_to_le32(data); 919 sel_val += pollrd->sel_val_stride; 920 } 921 return pollrd->no_ops * (2 * sizeof(u32)); 922 } 923 924 static u32 qlcnic_read_mux2(struct qlcnic_adapter *adapter, 925 struct qlcnic_dump_entry *entry, __le32 *buffer) 926 { 927 struct __mux2 *mux2 = &entry->region.mux2; 928 u32 data; 929 u32 t_sel_val, sel_val1, sel_val2; 930 int i; 931 932 sel_val1 = mux2->sel_val1; 933 sel_val2 = mux2->sel_val2; 934 935 for (i = 0; i < mux2->no_ops; i++) { 936 qlcnic_ind_wr(adapter, mux2->sel_addr1, sel_val1); 937 t_sel_val = sel_val1 & mux2->sel_val_mask; 938 qlcnic_ind_wr(adapter, mux2->sel_addr2, t_sel_val); 939 data = qlcnic_ind_rd(adapter, mux2->read_addr); 940 *buffer++ = cpu_to_le32(t_sel_val); 941 *buffer++ = cpu_to_le32(data); 942 qlcnic_ind_wr(adapter, mux2->sel_addr1, sel_val2); 943 t_sel_val = sel_val2 & mux2->sel_val_mask; 944 qlcnic_ind_wr(adapter, mux2->sel_addr2, t_sel_val); 945 data = qlcnic_ind_rd(adapter, mux2->read_addr); 946 *buffer++ = cpu_to_le32(t_sel_val); 947 *buffer++ = cpu_to_le32(data); 948 sel_val1 += mux2->sel_val_stride; 949 sel_val2 += mux2->sel_val_stride; 950 } 951 952 return mux2->no_ops * (4 * sizeof(u32)); 953 } 954 955 static u32 qlcnic_83xx_dump_rom(struct qlcnic_adapter *adapter, 956 struct qlcnic_dump_entry *entry, __le32 *buffer) 957 { 958 u32 fl_addr, size; 959 struct __mem *rom = &entry->region.mem; 960 961 fl_addr = rom->addr; 962 size = rom->size / 4; 963 964 if (!qlcnic_83xx_lockless_flash_read32(adapter, fl_addr, 965 (u8 *)buffer, size)) 966 return rom->size; 967 968 return 0; 969 } 970 971 static const struct qlcnic_dump_operations qlcnic_fw_dump_ops[] = { 972 {QLCNIC_DUMP_NOP, qlcnic_dump_nop}, 973 {QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb}, 974 {QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux}, 975 {QLCNIC_DUMP_QUEUE, qlcnic_dump_que}, 976 {QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom}, 977 {QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm}, 978 {QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl}, 979 {QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache}, 980 {QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache}, 981 {QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache}, 982 {QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache}, 983 {QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache}, 984 {QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache}, 985 {QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache}, 986 {QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache}, 987 {QLCNIC_DUMP_READ_ROM, qlcnic_read_rom}, 988 {QLCNIC_DUMP_READ_MEM, qlcnic_read_memory}, 989 {QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl}, 990 {QLCNIC_DUMP_TLHDR, qlcnic_dump_nop}, 991 {QLCNIC_DUMP_RDEND, qlcnic_dump_nop}, 992 }; 993 994 static const struct qlcnic_dump_operations qlcnic_83xx_fw_dump_ops[] = { 995 {QLCNIC_DUMP_NOP, qlcnic_dump_nop}, 996 {QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb}, 997 {QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux}, 998 {QLCNIC_DUMP_QUEUE, qlcnic_dump_que}, 999 {QLCNIC_DUMP_BRD_CONFIG, qlcnic_83xx_dump_rom}, 1000 {QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm}, 1001 {QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl}, 1002 {QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache}, 1003 {QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache}, 1004 {QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache}, 1005 {QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache}, 1006 {QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache}, 1007 {QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache}, 1008 {QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache}, 1009 {QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache}, 1010 {QLCNIC_DUMP_POLL_RD, qlcnic_read_pollrd}, 1011 {QLCNIC_READ_MUX2, qlcnic_read_mux2}, 1012 {QLCNIC_READ_POLLRDMWR, qlcnic_read_pollrdmwr}, 1013 {QLCNIC_DUMP_READ_ROM, qlcnic_83xx_dump_rom}, 1014 {QLCNIC_DUMP_READ_MEM, qlcnic_read_memory}, 1015 {QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl}, 1016 {QLCNIC_DUMP_TLHDR, qlcnic_dump_nop}, 1017 {QLCNIC_DUMP_RDEND, qlcnic_dump_nop}, 1018 }; 1019 1020 static uint32_t qlcnic_temp_checksum(uint32_t *temp_buffer, u32 temp_size) 1021 { 1022 uint64_t sum = 0; 1023 int count = temp_size / sizeof(uint32_t); 1024 while (count-- > 0) 1025 sum += *temp_buffer++; 1026 while (sum >> 32) 1027 sum = (sum & 0xFFFFFFFF) + (sum >> 32); 1028 return ~sum; 1029 } 1030 1031 static int qlcnic_fw_flash_get_minidump_temp(struct qlcnic_adapter *adapter, 1032 u8 *buffer, u32 size) 1033 { 1034 int ret = 0; 1035 1036 if (qlcnic_82xx_check(adapter)) 1037 return -EIO; 1038 1039 if (qlcnic_83xx_lock_flash(adapter)) 1040 return -EIO; 1041 1042 ret = qlcnic_83xx_lockless_flash_read32(adapter, 1043 QLC_83XX_MINIDUMP_FLASH, 1044 buffer, size / sizeof(u32)); 1045 1046 qlcnic_83xx_unlock_flash(adapter); 1047 1048 return ret; 1049 } 1050 1051 static int 1052 qlcnic_fw_flash_get_minidump_temp_size(struct qlcnic_adapter *adapter, 1053 struct qlcnic_cmd_args *cmd) 1054 { 1055 struct qlcnic_83xx_dump_template_hdr tmp_hdr; 1056 u32 size = sizeof(tmp_hdr) / sizeof(u32); 1057 int ret = 0; 1058 1059 if (qlcnic_82xx_check(adapter)) 1060 return -EIO; 1061 1062 if (qlcnic_83xx_lock_flash(adapter)) 1063 return -EIO; 1064 1065 ret = qlcnic_83xx_lockless_flash_read32(adapter, 1066 QLC_83XX_MINIDUMP_FLASH, 1067 (u8 *)&tmp_hdr, size); 1068 1069 qlcnic_83xx_unlock_flash(adapter); 1070 1071 cmd->rsp.arg[2] = tmp_hdr.size; 1072 cmd->rsp.arg[3] = tmp_hdr.version; 1073 1074 return ret; 1075 } 1076 1077 static int qlcnic_fw_get_minidump_temp_size(struct qlcnic_adapter *adapter, 1078 u32 *version, u32 *temp_size, 1079 u8 *use_flash_temp) 1080 { 1081 int err = 0; 1082 struct qlcnic_cmd_args cmd; 1083 1084 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TEMP_SIZE)) 1085 return -ENOMEM; 1086 1087 err = qlcnic_issue_cmd(adapter, &cmd); 1088 if (err != QLCNIC_RCODE_SUCCESS) { 1089 if (qlcnic_fw_flash_get_minidump_temp_size(adapter, &cmd)) { 1090 qlcnic_free_mbx_args(&cmd); 1091 return -EIO; 1092 } 1093 *use_flash_temp = 1; 1094 } 1095 1096 *temp_size = cmd.rsp.arg[2]; 1097 *version = cmd.rsp.arg[3]; 1098 qlcnic_free_mbx_args(&cmd); 1099 1100 if (!(*temp_size)) 1101 return -EIO; 1102 1103 return 0; 1104 } 1105 1106 static int __qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter, 1107 u32 *buffer, u32 temp_size) 1108 { 1109 int err = 0, i; 1110 void *tmp_addr; 1111 __le32 *tmp_buf; 1112 struct qlcnic_cmd_args cmd; 1113 dma_addr_t tmp_addr_t = 0; 1114 1115 tmp_addr = dma_alloc_coherent(&adapter->pdev->dev, temp_size, 1116 &tmp_addr_t, GFP_KERNEL); 1117 if (!tmp_addr) 1118 return -ENOMEM; 1119 1120 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_TEMP_HDR)) { 1121 err = -ENOMEM; 1122 goto free_mem; 1123 } 1124 1125 cmd.req.arg[1] = LSD(tmp_addr_t); 1126 cmd.req.arg[2] = MSD(tmp_addr_t); 1127 cmd.req.arg[3] = temp_size; 1128 err = qlcnic_issue_cmd(adapter, &cmd); 1129 1130 tmp_buf = tmp_addr; 1131 if (err == QLCNIC_RCODE_SUCCESS) { 1132 for (i = 0; i < temp_size / sizeof(u32); i++) 1133 *buffer++ = __le32_to_cpu(*tmp_buf++); 1134 } 1135 1136 qlcnic_free_mbx_args(&cmd); 1137 1138 free_mem: 1139 dma_free_coherent(&adapter->pdev->dev, temp_size, tmp_addr, tmp_addr_t); 1140 1141 return err; 1142 } 1143 1144 #define QLCNIC_TEMPLATE_VERSION (0x20001) 1145 1146 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter) 1147 { 1148 struct qlcnic_hardware_context *ahw; 1149 struct qlcnic_fw_dump *fw_dump; 1150 u32 version, csum, *tmp_buf; 1151 u8 use_flash_temp = 0; 1152 u32 temp_size = 0; 1153 int err; 1154 1155 ahw = adapter->ahw; 1156 fw_dump = &ahw->fw_dump; 1157 err = qlcnic_fw_get_minidump_temp_size(adapter, &version, &temp_size, 1158 &use_flash_temp); 1159 if (err) { 1160 dev_err(&adapter->pdev->dev, 1161 "Can't get template size %d\n", err); 1162 return -EIO; 1163 } 1164 1165 fw_dump->tmpl_hdr = vzalloc(temp_size); 1166 if (!fw_dump->tmpl_hdr) 1167 return -ENOMEM; 1168 1169 tmp_buf = (u32 *)fw_dump->tmpl_hdr; 1170 if (use_flash_temp) 1171 goto flash_temp; 1172 1173 err = __qlcnic_fw_cmd_get_minidump_temp(adapter, tmp_buf, temp_size); 1174 1175 if (err) { 1176 flash_temp: 1177 err = qlcnic_fw_flash_get_minidump_temp(adapter, (u8 *)tmp_buf, 1178 temp_size); 1179 1180 if (err) { 1181 dev_err(&adapter->pdev->dev, 1182 "Failed to get minidump template header %d\n", 1183 err); 1184 vfree(fw_dump->tmpl_hdr); 1185 fw_dump->tmpl_hdr = NULL; 1186 return -EIO; 1187 } 1188 } 1189 1190 csum = qlcnic_temp_checksum((uint32_t *)tmp_buf, temp_size); 1191 1192 if (csum) { 1193 dev_err(&adapter->pdev->dev, 1194 "Template header checksum validation failed\n"); 1195 vfree(fw_dump->tmpl_hdr); 1196 fw_dump->tmpl_hdr = NULL; 1197 return -EIO; 1198 } 1199 1200 qlcnic_cache_tmpl_hdr_values(adapter, fw_dump); 1201 1202 dev_info(&adapter->pdev->dev, 1203 "Default minidump capture mask 0x%x\n", 1204 fw_dump->cap_mask); 1205 1206 if (qlcnic_83xx_check(adapter) && 1207 (fw_dump->version & 0xfffff) >= QLCNIC_TEMPLATE_VERSION) 1208 fw_dump->use_pex_dma = true; 1209 else 1210 fw_dump->use_pex_dma = false; 1211 1212 qlcnic_enable_fw_dump_state(adapter); 1213 1214 return 0; 1215 } 1216 1217 int qlcnic_dump_fw(struct qlcnic_adapter *adapter) 1218 { 1219 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump; 1220 static const struct qlcnic_dump_operations *fw_dump_ops; 1221 struct qlcnic_83xx_dump_template_hdr *hdr_83xx; 1222 u32 entry_offset, dump, no_entries, buf_offset = 0; 1223 int i, k, ops_cnt, ops_index, dump_size = 0; 1224 struct device *dev = &adapter->pdev->dev; 1225 struct qlcnic_hardware_context *ahw; 1226 struct qlcnic_dump_entry *entry; 1227 void *temp_buffer, *tmpl_hdr; 1228 u32 ocm_window; 1229 __le32 *buffer; 1230 char mesg[64]; 1231 char *msg[] = {mesg, NULL}; 1232 1233 ahw = adapter->ahw; 1234 tmpl_hdr = fw_dump->tmpl_hdr; 1235 1236 /* Return if we don't have firmware dump template header */ 1237 if (!tmpl_hdr) 1238 return -EIO; 1239 1240 if (!qlcnic_check_fw_dump_state(adapter)) { 1241 dev_info(&adapter->pdev->dev, "Dump not enabled\n"); 1242 return -EIO; 1243 } 1244 1245 if (fw_dump->clr) { 1246 dev_info(&adapter->pdev->dev, 1247 "Previous dump not cleared, not capturing dump\n"); 1248 return -EIO; 1249 } 1250 1251 netif_info(adapter->ahw, drv, adapter->netdev, "Take FW dump\n"); 1252 /* Calculate the size for dump data area only */ 1253 for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++) 1254 if (i & fw_dump->cap_mask) 1255 dump_size += qlcnic_get_cap_size(adapter, tmpl_hdr, k); 1256 1257 if (!dump_size) 1258 return -EIO; 1259 1260 fw_dump->data = vzalloc(dump_size); 1261 if (!fw_dump->data) 1262 return -ENOMEM; 1263 1264 buffer = fw_dump->data; 1265 fw_dump->size = dump_size; 1266 no_entries = fw_dump->num_entries; 1267 entry_offset = fw_dump->offset; 1268 qlcnic_set_sys_info(adapter, tmpl_hdr, 0, QLCNIC_DRIVER_VERSION); 1269 qlcnic_set_sys_info(adapter, tmpl_hdr, 1, adapter->fw_version); 1270 1271 if (fw_dump->use_pex_dma) { 1272 temp_buffer = dma_alloc_coherent(dev, QLC_PEX_DMA_READ_SIZE, 1273 &fw_dump->phys_addr, 1274 GFP_KERNEL); 1275 if (!temp_buffer) 1276 fw_dump->use_pex_dma = false; 1277 else 1278 fw_dump->dma_buffer = temp_buffer; 1279 } 1280 1281 if (qlcnic_82xx_check(adapter)) { 1282 ops_cnt = ARRAY_SIZE(qlcnic_fw_dump_ops); 1283 fw_dump_ops = qlcnic_fw_dump_ops; 1284 } else { 1285 hdr_83xx = tmpl_hdr; 1286 ops_cnt = ARRAY_SIZE(qlcnic_83xx_fw_dump_ops); 1287 fw_dump_ops = qlcnic_83xx_fw_dump_ops; 1288 ocm_window = hdr_83xx->ocm_wnd_reg[ahw->pci_func]; 1289 hdr_83xx->saved_state[QLC_83XX_OCM_INDEX] = ocm_window; 1290 hdr_83xx->saved_state[QLC_83XX_PCI_INDEX] = ahw->pci_func; 1291 } 1292 1293 for (i = 0; i < no_entries; i++) { 1294 entry = tmpl_hdr + entry_offset; 1295 if (!(entry->hdr.mask & fw_dump->cap_mask)) { 1296 entry->hdr.flags |= QLCNIC_DUMP_SKIP; 1297 entry_offset += entry->hdr.offset; 1298 continue; 1299 } 1300 1301 /* Find the handler for this entry */ 1302 ops_index = 0; 1303 while (ops_index < ops_cnt) { 1304 if (entry->hdr.type == fw_dump_ops[ops_index].opcode) 1305 break; 1306 ops_index++; 1307 } 1308 1309 if (ops_index == ops_cnt) { 1310 dev_info(dev, "Skipping unknown entry opcode %d\n", 1311 entry->hdr.type); 1312 entry->hdr.flags |= QLCNIC_DUMP_SKIP; 1313 entry_offset += entry->hdr.offset; 1314 continue; 1315 } 1316 1317 /* Collect dump for this entry */ 1318 dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer); 1319 if (!qlcnic_valid_dump_entry(dev, entry, dump)) { 1320 entry->hdr.flags |= QLCNIC_DUMP_SKIP; 1321 entry_offset += entry->hdr.offset; 1322 continue; 1323 } 1324 1325 buf_offset += entry->hdr.cap_size; 1326 entry_offset += entry->hdr.offset; 1327 buffer = fw_dump->data + buf_offset; 1328 } 1329 1330 fw_dump->clr = 1; 1331 snprintf(mesg, sizeof(mesg), "FW_DUMP=%s", adapter->netdev->name); 1332 netdev_info(adapter->netdev, 1333 "Dump data %d bytes captured, template header size %d bytes\n", 1334 fw_dump->size, fw_dump->tmpl_hdr_size); 1335 /* Send a udev event to notify availability of FW dump */ 1336 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, msg); 1337 1338 if (fw_dump->use_pex_dma) 1339 dma_free_coherent(dev, QLC_PEX_DMA_READ_SIZE, 1340 fw_dump->dma_buffer, fw_dump->phys_addr); 1341 1342 return 0; 1343 } 1344 1345 void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *adapter) 1346 { 1347 u32 prev_version, current_version; 1348 struct qlcnic_hardware_context *ahw = adapter->ahw; 1349 struct qlcnic_fw_dump *fw_dump = &ahw->fw_dump; 1350 struct pci_dev *pdev = adapter->pdev; 1351 1352 prev_version = adapter->fw_version; 1353 current_version = qlcnic_83xx_get_fw_version(adapter); 1354 1355 if (fw_dump->tmpl_hdr == NULL || current_version > prev_version) { 1356 if (fw_dump->tmpl_hdr) 1357 vfree(fw_dump->tmpl_hdr); 1358 if (!qlcnic_fw_cmd_get_minidump_temp(adapter)) 1359 dev_info(&pdev->dev, "Supports FW dump capability\n"); 1360 } 1361 } 1362