1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2010 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic.h" 9 #include "qlcnic_hdr.h" 10 11 #include <linux/slab.h> 12 #include <net/ip.h> 13 #include <linux/bitops.h> 14 15 #define MASK(n) ((1ULL<<(n))-1) 16 #define OCM_WIN_P3P(addr) (addr & 0xffc0000) 17 18 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 19 20 #define CRB_BLK(off) ((off >> 20) & 0x3f) 21 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 22 #define CRB_WINDOW_2M (0x130060) 23 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) 24 #define CRB_INDIRECT_2M (0x1e0000UL) 25 26 struct qlcnic_ms_reg_ctrl { 27 u32 ocm_window; 28 u32 control; 29 u32 hi; 30 u32 low; 31 u32 rd[4]; 32 u32 wd[4]; 33 u64 off; 34 }; 35 36 #ifndef readq 37 static inline u64 readq(void __iomem *addr) 38 { 39 return readl(addr) | (((u64) readl(addr + 4)) << 32LL); 40 } 41 #endif 42 43 #ifndef writeq 44 static inline void writeq(u64 val, void __iomem *addr) 45 { 46 writel(((u32) (val)), (addr)); 47 writel(((u32) (val >> 32)), (addr + 4)); 48 } 49 #endif 50 51 static struct crb_128M_2M_block_map 52 crb_128M_2M_map[64] __cacheline_aligned_in_smp = { 53 {{{0, 0, 0, 0} } }, /* 0: PCI */ 54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 55 {1, 0x0110000, 0x0120000, 0x130000}, 56 {1, 0x0120000, 0x0122000, 0x124000}, 57 {1, 0x0130000, 0x0132000, 0x126000}, 58 {1, 0x0140000, 0x0142000, 0x128000}, 59 {1, 0x0150000, 0x0152000, 0x12a000}, 60 {1, 0x0160000, 0x0170000, 0x110000}, 61 {1, 0x0170000, 0x0172000, 0x12e000}, 62 {0, 0x0000000, 0x0000000, 0x000000}, 63 {0, 0x0000000, 0x0000000, 0x000000}, 64 {0, 0x0000000, 0x0000000, 0x000000}, 65 {0, 0x0000000, 0x0000000, 0x000000}, 66 {0, 0x0000000, 0x0000000, 0x000000}, 67 {0, 0x0000000, 0x0000000, 0x000000}, 68 {1, 0x01e0000, 0x01e0800, 0x122000}, 69 {0, 0x0000000, 0x0000000, 0x000000} } }, 70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 71 {{{0, 0, 0, 0} } }, /* 3: */ 72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 77 {0, 0x0000000, 0x0000000, 0x000000}, 78 {0, 0x0000000, 0x0000000, 0x000000}, 79 {0, 0x0000000, 0x0000000, 0x000000}, 80 {0, 0x0000000, 0x0000000, 0x000000}, 81 {0, 0x0000000, 0x0000000, 0x000000}, 82 {0, 0x0000000, 0x0000000, 0x000000}, 83 {0, 0x0000000, 0x0000000, 0x000000}, 84 {0, 0x0000000, 0x0000000, 0x000000}, 85 {0, 0x0000000, 0x0000000, 0x000000}, 86 {0, 0x0000000, 0x0000000, 0x000000}, 87 {0, 0x0000000, 0x0000000, 0x000000}, 88 {0, 0x0000000, 0x0000000, 0x000000}, 89 {0, 0x0000000, 0x0000000, 0x000000}, 90 {0, 0x0000000, 0x0000000, 0x000000}, 91 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 93 {0, 0x0000000, 0x0000000, 0x000000}, 94 {0, 0x0000000, 0x0000000, 0x000000}, 95 {0, 0x0000000, 0x0000000, 0x000000}, 96 {0, 0x0000000, 0x0000000, 0x000000}, 97 {0, 0x0000000, 0x0000000, 0x000000}, 98 {0, 0x0000000, 0x0000000, 0x000000}, 99 {0, 0x0000000, 0x0000000, 0x000000}, 100 {0, 0x0000000, 0x0000000, 0x000000}, 101 {0, 0x0000000, 0x0000000, 0x000000}, 102 {0, 0x0000000, 0x0000000, 0x000000}, 103 {0, 0x0000000, 0x0000000, 0x000000}, 104 {0, 0x0000000, 0x0000000, 0x000000}, 105 {0, 0x0000000, 0x0000000, 0x000000}, 106 {0, 0x0000000, 0x0000000, 0x000000}, 107 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 109 {0, 0x0000000, 0x0000000, 0x000000}, 110 {0, 0x0000000, 0x0000000, 0x000000}, 111 {0, 0x0000000, 0x0000000, 0x000000}, 112 {0, 0x0000000, 0x0000000, 0x000000}, 113 {0, 0x0000000, 0x0000000, 0x000000}, 114 {0, 0x0000000, 0x0000000, 0x000000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {0, 0x0000000, 0x0000000, 0x000000}, 127 {0, 0x0000000, 0x0000000, 0x000000}, 128 {0, 0x0000000, 0x0000000, 0x000000}, 129 {0, 0x0000000, 0x0000000, 0x000000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 151 {{{0, 0, 0, 0} } }, /* 23: */ 152 {{{0, 0, 0, 0} } }, /* 24: */ 153 {{{0, 0, 0, 0} } }, /* 25: */ 154 {{{0, 0, 0, 0} } }, /* 26: */ 155 {{{0, 0, 0, 0} } }, /* 27: */ 156 {{{0, 0, 0, 0} } }, /* 28: */ 157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 160 {{{0} } }, /* 32: PCI */ 161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 162 {1, 0x2110000, 0x2120000, 0x130000}, 163 {1, 0x2120000, 0x2122000, 0x124000}, 164 {1, 0x2130000, 0x2132000, 0x126000}, 165 {1, 0x2140000, 0x2142000, 0x128000}, 166 {1, 0x2150000, 0x2152000, 0x12a000}, 167 {1, 0x2160000, 0x2170000, 0x110000}, 168 {1, 0x2170000, 0x2172000, 0x12e000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000} } }, 177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 178 {{{0} } }, /* 35: */ 179 {{{0} } }, /* 36: */ 180 {{{0} } }, /* 37: */ 181 {{{0} } }, /* 38: */ 182 {{{0} } }, /* 39: */ 183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 195 {{{0} } }, /* 52: */ 196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 202 {{{0} } }, /* 59: I2C0 */ 203 {{{0} } }, /* 60: I2C1 */ 204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ 205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 207 }; 208 209 /* 210 * top 12 bits of crb internal address (hub, agent) 211 */ 212 static const unsigned crb_hub_agt[64] = { 213 0, 214 QLCNIC_HW_CRB_HUB_AGT_ADR_PS, 215 QLCNIC_HW_CRB_HUB_AGT_ADR_MN, 216 QLCNIC_HW_CRB_HUB_AGT_ADR_MS, 217 0, 218 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE, 219 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU, 220 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN, 221 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0, 222 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1, 223 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2, 224 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3, 225 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q, 226 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR, 227 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB, 228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4, 229 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA, 230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0, 231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1, 232 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2, 233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3, 234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND, 235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI, 236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0, 237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1, 238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2, 239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3, 240 0, 241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI, 242 QLCNIC_HW_CRB_HUB_AGT_ADR_SN, 243 0, 244 QLCNIC_HW_CRB_HUB_AGT_ADR_EG, 245 0, 246 QLCNIC_HW_CRB_HUB_AGT_ADR_PS, 247 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM, 248 0, 249 0, 250 0, 251 0, 252 0, 253 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR, 254 0, 255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1, 256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2, 257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3, 258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4, 259 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5, 260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6, 261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7, 262 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA, 263 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q, 264 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB, 265 0, 266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0, 267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8, 268 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9, 269 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0, 270 0, 271 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB, 272 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0, 273 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1, 274 0, 275 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC, 276 0, 277 }; 278 279 static const u32 msi_tgt_status[8] = { 280 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, 281 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, 282 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, 283 ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7 284 }; 285 286 /* PCI Windowing for DDR regions. */ 287 288 #define QLCNIC_PCIE_SEM_TIMEOUT 10000 289 290 static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data) 291 { 292 u32 dest; 293 void __iomem *val; 294 295 dest = addr & 0xFFFF0000; 296 val = bar0 + QLCNIC_FW_DUMP_REG1; 297 writel(dest, val); 298 readl(val); 299 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr); 300 *data = readl(val); 301 } 302 303 static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data) 304 { 305 u32 dest; 306 void __iomem *val; 307 308 dest = addr & 0xFFFF0000; 309 val = bar0 + QLCNIC_FW_DUMP_REG1; 310 writel(dest, val); 311 readl(val); 312 val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr); 313 writel(data, val); 314 readl(val); 315 } 316 317 int 318 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg) 319 { 320 int done = 0, timeout = 0; 321 322 while (!done) { 323 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem))); 324 if (done == 1) 325 break; 326 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) { 327 dev_err(&adapter->pdev->dev, 328 "Failed to acquire sem=%d lock; holdby=%d\n", 329 sem, id_reg ? QLCRD32(adapter, id_reg) : -1); 330 return -EIO; 331 } 332 msleep(1); 333 } 334 335 if (id_reg) 336 QLCWR32(adapter, id_reg, adapter->portnum); 337 338 return 0; 339 } 340 341 void 342 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem) 343 { 344 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem))); 345 } 346 347 static int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr) 348 { 349 u32 data; 350 351 if (qlcnic_82xx_check(adapter)) 352 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data); 353 else 354 return -EIO; 355 return data; 356 } 357 358 static void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data) 359 { 360 if (qlcnic_82xx_check(adapter)) 361 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data); 362 } 363 364 static int 365 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter, 366 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) 367 { 368 u32 i, producer; 369 struct qlcnic_cmd_buffer *pbuf; 370 struct cmd_desc_type0 *cmd_desc; 371 struct qlcnic_host_tx_ring *tx_ring; 372 373 i = 0; 374 375 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 376 return -EIO; 377 378 tx_ring = adapter->tx_ring; 379 __netif_tx_lock_bh(tx_ring->txq); 380 381 producer = tx_ring->producer; 382 383 if (nr_desc >= qlcnic_tx_avail(tx_ring)) { 384 netif_tx_stop_queue(tx_ring->txq); 385 smp_mb(); 386 if (qlcnic_tx_avail(tx_ring) > nr_desc) { 387 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH) 388 netif_tx_wake_queue(tx_ring->txq); 389 } else { 390 adapter->stats.xmit_off++; 391 __netif_tx_unlock_bh(tx_ring->txq); 392 return -EBUSY; 393 } 394 } 395 396 do { 397 cmd_desc = &cmd_desc_arr[i]; 398 399 pbuf = &tx_ring->cmd_buf_arr[producer]; 400 pbuf->skb = NULL; 401 pbuf->frag_count = 0; 402 403 memcpy(&tx_ring->desc_head[producer], 404 cmd_desc, sizeof(struct cmd_desc_type0)); 405 406 producer = get_next_index(producer, tx_ring->num_desc); 407 i++; 408 409 } while (i != nr_desc); 410 411 tx_ring->producer = producer; 412 413 qlcnic_update_cmd_producer(tx_ring); 414 415 __netif_tx_unlock_bh(tx_ring->txq); 416 417 return 0; 418 } 419 420 static int 421 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr, 422 __le16 vlan_id, unsigned op) 423 { 424 struct qlcnic_nic_req req; 425 struct qlcnic_mac_req *mac_req; 426 struct qlcnic_vlan_req *vlan_req; 427 u64 word; 428 429 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 430 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23); 431 432 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16); 433 req.req_hdr = cpu_to_le64(word); 434 435 mac_req = (struct qlcnic_mac_req *)&req.words[0]; 436 mac_req->op = op; 437 memcpy(mac_req->mac_addr, addr, 6); 438 439 vlan_req = (struct qlcnic_vlan_req *)&req.words[1]; 440 vlan_req->vlan_id = vlan_id; 441 442 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 443 } 444 445 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr) 446 { 447 struct list_head *head; 448 struct qlcnic_mac_list_s *cur; 449 450 /* look up if already exists */ 451 list_for_each(head, &adapter->mac_list) { 452 cur = list_entry(head, struct qlcnic_mac_list_s, list); 453 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) 454 return 0; 455 } 456 457 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC); 458 if (cur == NULL) { 459 dev_err(&adapter->netdev->dev, 460 "failed to add mac address filter\n"); 461 return -ENOMEM; 462 } 463 memcpy(cur->mac_addr, addr, ETH_ALEN); 464 465 if (qlcnic_sre_macaddr_change(adapter, 466 cur->mac_addr, 0, QLCNIC_MAC_ADD)) { 467 kfree(cur); 468 return -EIO; 469 } 470 471 list_add_tail(&cur->list, &adapter->mac_list); 472 return 0; 473 } 474 475 void qlcnic_set_multi(struct net_device *netdev) 476 { 477 struct qlcnic_adapter *adapter = netdev_priv(netdev); 478 struct netdev_hw_addr *ha; 479 static const u8 bcast_addr[ETH_ALEN] = { 480 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 481 }; 482 u32 mode = VPORT_MISS_MODE_DROP; 483 484 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 485 return; 486 487 qlcnic_nic_add_mac(adapter, adapter->mac_addr); 488 qlcnic_nic_add_mac(adapter, bcast_addr); 489 490 if (netdev->flags & IFF_PROMISC) { 491 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED)) 492 mode = VPORT_MISS_MODE_ACCEPT_ALL; 493 goto send_fw_cmd; 494 } 495 496 if ((netdev->flags & IFF_ALLMULTI) || 497 (netdev_mc_count(netdev) > adapter->ahw->max_mc_count)) { 498 mode = VPORT_MISS_MODE_ACCEPT_MULTI; 499 goto send_fw_cmd; 500 } 501 502 if (!netdev_mc_empty(netdev)) { 503 netdev_for_each_mc_addr(ha, netdev) { 504 qlcnic_nic_add_mac(adapter, ha->addr); 505 } 506 } 507 508 send_fw_cmd: 509 if (mode == VPORT_MISS_MODE_ACCEPT_ALL) { 510 qlcnic_alloc_lb_filters_mem(adapter); 511 adapter->mac_learn = 1; 512 } else { 513 adapter->mac_learn = 0; 514 } 515 516 qlcnic_nic_set_promisc(adapter, mode); 517 } 518 519 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode) 520 { 521 struct qlcnic_nic_req req; 522 u64 word; 523 524 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 525 526 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 527 528 word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE | 529 ((u64)adapter->portnum << 16); 530 req.req_hdr = cpu_to_le64(word); 531 532 req.words[0] = cpu_to_le64(mode); 533 534 return qlcnic_send_cmd_descs(adapter, 535 (struct cmd_desc_type0 *)&req, 1); 536 } 537 538 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) 539 { 540 struct qlcnic_mac_list_s *cur; 541 struct list_head *head = &adapter->mac_list; 542 543 while (!list_empty(head)) { 544 cur = list_entry(head->next, struct qlcnic_mac_list_s, list); 545 qlcnic_sre_macaddr_change(adapter, 546 cur->mac_addr, 0, QLCNIC_MAC_DEL); 547 list_del(&cur->list); 548 kfree(cur); 549 } 550 } 551 552 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter) 553 { 554 struct qlcnic_filter *tmp_fil; 555 struct hlist_node *tmp_hnode, *n; 556 struct hlist_head *head; 557 int i; 558 559 for (i = 0; i < adapter->fhash.fmax; i++) { 560 head = &(adapter->fhash.fhead[i]); 561 562 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) 563 { 564 if (jiffies > 565 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) { 566 qlcnic_sre_macaddr_change(adapter, 567 tmp_fil->faddr, tmp_fil->vlan_id, 568 tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL : 569 QLCNIC_MAC_DEL); 570 spin_lock_bh(&adapter->mac_learn_lock); 571 adapter->fhash.fnum--; 572 hlist_del(&tmp_fil->fnode); 573 spin_unlock_bh(&adapter->mac_learn_lock); 574 kfree(tmp_fil); 575 } 576 } 577 } 578 } 579 580 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter) 581 { 582 struct qlcnic_filter *tmp_fil; 583 struct hlist_node *tmp_hnode, *n; 584 struct hlist_head *head; 585 int i; 586 587 for (i = 0; i < adapter->fhash.fmax; i++) { 588 head = &(adapter->fhash.fhead[i]); 589 590 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) { 591 qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr, 592 tmp_fil->vlan_id, tmp_fil->vlan_id ? 593 QLCNIC_MAC_VLAN_DEL : QLCNIC_MAC_DEL); 594 spin_lock_bh(&adapter->mac_learn_lock); 595 adapter->fhash.fnum--; 596 hlist_del(&tmp_fil->fnode); 597 spin_unlock_bh(&adapter->mac_learn_lock); 598 kfree(tmp_fil); 599 } 600 } 601 } 602 603 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag) 604 { 605 struct qlcnic_nic_req req; 606 int rv; 607 608 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 609 610 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 611 req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK | 612 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32)); 613 614 req.words[0] = cpu_to_le64(flag); 615 616 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 617 if (rv != 0) 618 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n", 619 flag ? "Set" : "Reset"); 620 return rv; 621 } 622 623 int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 624 { 625 if (qlcnic_set_fw_loopback(adapter, mode)) 626 return -EIO; 627 628 if (qlcnic_nic_set_promisc(adapter, VPORT_MISS_MODE_ACCEPT_ALL)) { 629 qlcnic_set_fw_loopback(adapter, 0); 630 return -EIO; 631 } 632 633 msleep(1000); 634 return 0; 635 } 636 637 void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter) 638 { 639 int mode = VPORT_MISS_MODE_DROP; 640 struct net_device *netdev = adapter->netdev; 641 642 qlcnic_set_fw_loopback(adapter, 0); 643 644 if (netdev->flags & IFF_PROMISC) 645 mode = VPORT_MISS_MODE_ACCEPT_ALL; 646 else if (netdev->flags & IFF_ALLMULTI) 647 mode = VPORT_MISS_MODE_ACCEPT_MULTI; 648 649 qlcnic_nic_set_promisc(adapter, mode); 650 msleep(1000); 651 } 652 653 /* 654 * Send the interrupt coalescing parameter set by ethtool to the card. 655 */ 656 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter) 657 { 658 struct qlcnic_nic_req req; 659 int rv; 660 661 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 662 663 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 664 665 req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE | 666 ((u64) adapter->portnum << 16)); 667 668 req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32); 669 req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets | 670 ((u64) adapter->ahw->coal.rx_time_us) << 16); 671 req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out | 672 ((u64) adapter->ahw->coal.type) << 32 | 673 ((u64) adapter->ahw->coal.sts_ring_mask) << 40); 674 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 675 if (rv != 0) 676 dev_err(&adapter->netdev->dev, 677 "Could not send interrupt coalescing parameters\n"); 678 return rv; 679 } 680 681 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable) 682 { 683 struct qlcnic_nic_req req; 684 u64 word; 685 int rv; 686 687 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 688 return 0; 689 690 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 691 692 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 693 694 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16); 695 req.req_hdr = cpu_to_le64(word); 696 697 req.words[0] = cpu_to_le64(enable); 698 699 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 700 if (rv != 0) 701 dev_err(&adapter->netdev->dev, 702 "Could not send configure hw lro request\n"); 703 704 return rv; 705 } 706 707 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable) 708 { 709 struct qlcnic_nic_req req; 710 u64 word; 711 int rv; 712 713 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable) 714 return 0; 715 716 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 717 718 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 719 720 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING | 721 ((u64)adapter->portnum << 16); 722 req.req_hdr = cpu_to_le64(word); 723 724 req.words[0] = cpu_to_le64(enable); 725 726 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 727 if (rv != 0) 728 dev_err(&adapter->netdev->dev, 729 "Could not send configure bridge mode request\n"); 730 731 adapter->flags ^= QLCNIC_BRIDGE_ENABLED; 732 733 return rv; 734 } 735 736 737 #define RSS_HASHTYPE_IP_TCP 0x3 738 739 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) 740 { 741 struct qlcnic_nic_req req; 742 u64 word; 743 int i, rv; 744 745 static const u64 key[] = { 746 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, 747 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 748 0x255b0ec26d5a56daULL 749 }; 750 751 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 752 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 753 754 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); 755 req.req_hdr = cpu_to_le64(word); 756 757 /* 758 * RSS request: 759 * bits 3-0: hash_method 760 * 5-4: hash_type_ipv4 761 * 7-6: hash_type_ipv6 762 * 8: enable 763 * 9: use indirection table 764 * 47-10: reserved 765 * 63-48: indirection table mask 766 */ 767 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | 768 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | 769 ((u64)(enable & 0x1) << 8) | 770 ((0x7ULL) << 48); 771 req.words[0] = cpu_to_le64(word); 772 for (i = 0; i < 5; i++) 773 req.words[i+1] = cpu_to_le64(key[i]); 774 775 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 776 if (rv != 0) 777 dev_err(&adapter->netdev->dev, "could not configure RSS\n"); 778 779 return rv; 780 } 781 782 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd) 783 { 784 struct qlcnic_nic_req req; 785 struct qlcnic_ipaddr *ipa; 786 u64 word; 787 int rv; 788 789 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 790 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 791 792 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16); 793 req.req_hdr = cpu_to_le64(word); 794 795 req.words[0] = cpu_to_le64(cmd); 796 ipa = (struct qlcnic_ipaddr *)&req.words[1]; 797 ipa->ipv4 = ip; 798 799 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 800 if (rv != 0) 801 dev_err(&adapter->netdev->dev, 802 "could not notify %s IP 0x%x reuqest\n", 803 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip); 804 805 return rv; 806 } 807 808 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable) 809 { 810 struct qlcnic_nic_req req; 811 u64 word; 812 int rv; 813 814 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 815 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 816 817 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); 818 req.req_hdr = cpu_to_le64(word); 819 req.words[0] = cpu_to_le64(enable | (enable << 8)); 820 821 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 822 if (rv != 0) 823 dev_err(&adapter->netdev->dev, 824 "could not configure link notification\n"); 825 826 return rv; 827 } 828 829 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter) 830 { 831 struct qlcnic_nic_req req; 832 u64 word; 833 int rv; 834 835 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 836 return 0; 837 838 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 839 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 840 841 word = QLCNIC_H2C_OPCODE_LRO_REQUEST | 842 ((u64)adapter->portnum << 16) | 843 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ; 844 845 req.req_hdr = cpu_to_le64(word); 846 847 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 848 if (rv != 0) 849 dev_err(&adapter->netdev->dev, 850 "could not cleanup lro flows\n"); 851 852 return rv; 853 } 854 855 /* 856 * qlcnic_change_mtu - Change the Maximum Transfer Unit 857 * @returns 0 on success, negative on failure 858 */ 859 860 int qlcnic_change_mtu(struct net_device *netdev, int mtu) 861 { 862 struct qlcnic_adapter *adapter = netdev_priv(netdev); 863 int rc = 0; 864 865 if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) { 866 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes" 867 " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU); 868 return -EINVAL; 869 } 870 871 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu); 872 873 if (!rc) 874 netdev->mtu = mtu; 875 876 return rc; 877 } 878 879 880 netdev_features_t qlcnic_fix_features(struct net_device *netdev, 881 netdev_features_t features) 882 { 883 struct qlcnic_adapter *adapter = netdev_priv(netdev); 884 885 if ((adapter->flags & QLCNIC_ESWITCH_ENABLED)) { 886 netdev_features_t changed = features ^ netdev->features; 887 features ^= changed & (NETIF_F_ALL_CSUM | NETIF_F_RXCSUM); 888 } 889 890 if (!(features & NETIF_F_RXCSUM)) 891 features &= ~NETIF_F_LRO; 892 893 return features; 894 } 895 896 897 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features) 898 { 899 struct qlcnic_adapter *adapter = netdev_priv(netdev); 900 netdev_features_t changed = netdev->features ^ features; 901 int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0; 902 903 if (!(changed & NETIF_F_LRO)) 904 return 0; 905 906 netdev->features = features ^ NETIF_F_LRO; 907 908 if (qlcnic_config_hw_lro(adapter, hw_lro)) 909 return -EIO; 910 911 if ((hw_lro == 0) && qlcnic_send_lro_cleanup(adapter)) 912 return -EIO; 913 914 return 0; 915 } 916 917 /* 918 * Changes the CRB window to the specified window. 919 */ 920 /* Returns < 0 if off is not valid, 921 * 1 if window access is needed. 'off' is set to offset from 922 * CRB space in 128M pci map 923 * 0 if no window access is needed. 'off' is set to 2M addr 924 * In: 'off' is offset from base in 128M pci map 925 */ 926 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw, 927 ulong off, void __iomem **addr) 928 { 929 const struct crb_128M_2M_sub_block_map *m; 930 931 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE)) 932 return -EINVAL; 933 934 off -= QLCNIC_PCI_CRBSPACE; 935 936 /* 937 * Try direct map 938 */ 939 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)]; 940 941 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) { 942 *addr = ahw->pci_base0 + m->start_2M + 943 (off - m->start_128M); 944 return 0; 945 } 946 947 /* 948 * Not in direct map, use crb window 949 */ 950 *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16)); 951 return 1; 952 } 953 954 /* 955 * In: 'off' is offset from CRB space in 128M pci map 956 * Out: 'off' is 2M pci map addr 957 * side effect: lock crb window 958 */ 959 static int 960 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off) 961 { 962 u32 window; 963 void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M; 964 965 off -= QLCNIC_PCI_CRBSPACE; 966 967 window = CRB_HI(off); 968 if (window == 0) { 969 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off); 970 return -EIO; 971 } 972 973 writel(window, addr); 974 if (readl(addr) != window) { 975 if (printk_ratelimit()) 976 dev_warn(&adapter->pdev->dev, 977 "failed to set CRB window to %d off 0x%lx\n", 978 window, off); 979 return -EIO; 980 } 981 return 0; 982 } 983 984 int 985 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data) 986 { 987 unsigned long flags; 988 int rv; 989 void __iomem *addr = NULL; 990 991 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr); 992 993 if (rv == 0) { 994 writel(data, addr); 995 return 0; 996 } 997 998 if (rv > 0) { 999 /* indirect access */ 1000 write_lock_irqsave(&adapter->ahw->crb_lock, flags); 1001 crb_win_lock(adapter); 1002 rv = qlcnic_pci_set_crbwindow_2M(adapter, off); 1003 if (!rv) 1004 writel(data, addr); 1005 crb_win_unlock(adapter); 1006 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags); 1007 return rv; 1008 } 1009 1010 dev_err(&adapter->pdev->dev, 1011 "%s: invalid offset: 0x%016lx\n", __func__, off); 1012 dump_stack(); 1013 return -EIO; 1014 } 1015 1016 int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off) 1017 { 1018 unsigned long flags; 1019 int rv; 1020 u32 data = -1; 1021 void __iomem *addr = NULL; 1022 1023 rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr); 1024 1025 if (rv == 0) 1026 return readl(addr); 1027 1028 if (rv > 0) { 1029 /* indirect access */ 1030 write_lock_irqsave(&adapter->ahw->crb_lock, flags); 1031 crb_win_lock(adapter); 1032 if (!qlcnic_pci_set_crbwindow_2M(adapter, off)) 1033 data = readl(addr); 1034 crb_win_unlock(adapter); 1035 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags); 1036 return data; 1037 } 1038 1039 dev_err(&adapter->pdev->dev, 1040 "%s: invalid offset: 0x%016lx\n", __func__, off); 1041 dump_stack(); 1042 return -1; 1043 } 1044 1045 1046 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw, 1047 u32 offset) 1048 { 1049 void __iomem *addr = NULL; 1050 1051 WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr)); 1052 1053 return addr; 1054 } 1055 1056 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, 1057 u32 window, u64 off, u64 *data, int op) 1058 { 1059 void __iomem *addr; 1060 u32 start; 1061 1062 mutex_lock(&adapter->ahw->mem_lock); 1063 1064 writel(window, adapter->ahw->ocm_win_crb); 1065 /* read back to flush */ 1066 readl(adapter->ahw->ocm_win_crb); 1067 start = QLCNIC_PCI_OCM0_2M + off; 1068 1069 addr = adapter->ahw->pci_base0 + start; 1070 1071 if (op == 0) /* read */ 1072 *data = readq(addr); 1073 else /* write */ 1074 writeq(*data, addr); 1075 1076 /* Set window to 0 */ 1077 writel(0, adapter->ahw->ocm_win_crb); 1078 readl(adapter->ahw->ocm_win_crb); 1079 1080 mutex_unlock(&adapter->ahw->mem_lock); 1081 return 0; 1082 } 1083 1084 void 1085 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data) 1086 { 1087 void __iomem *addr = adapter->ahw->pci_base0 + 1088 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM); 1089 1090 mutex_lock(&adapter->ahw->mem_lock); 1091 *data = readq(addr); 1092 mutex_unlock(&adapter->ahw->mem_lock); 1093 } 1094 1095 void 1096 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data) 1097 { 1098 void __iomem *addr = adapter->ahw->pci_base0 + 1099 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM); 1100 1101 mutex_lock(&adapter->ahw->mem_lock); 1102 writeq(data, addr); 1103 mutex_unlock(&adapter->ahw->mem_lock); 1104 } 1105 1106 1107 1108 /* Set MS memory control data for different adapters */ 1109 static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off, 1110 struct qlcnic_ms_reg_ctrl *ms) 1111 { 1112 ms->control = QLCNIC_MS_CTRL; 1113 ms->low = QLCNIC_MS_ADDR_LO; 1114 ms->hi = QLCNIC_MS_ADDR_HI; 1115 if (off & 0xf) { 1116 ms->wd[0] = QLCNIC_MS_WRTDATA_LO; 1117 ms->rd[0] = QLCNIC_MS_RDDATA_LO; 1118 ms->wd[1] = QLCNIC_MS_WRTDATA_HI; 1119 ms->rd[1] = QLCNIC_MS_RDDATA_HI; 1120 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO; 1121 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI; 1122 ms->rd[2] = QLCNIC_MS_RDDATA_ULO; 1123 ms->rd[3] = QLCNIC_MS_RDDATA_UHI; 1124 } else { 1125 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO; 1126 ms->rd[0] = QLCNIC_MS_RDDATA_ULO; 1127 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI; 1128 ms->rd[1] = QLCNIC_MS_RDDATA_UHI; 1129 ms->wd[2] = QLCNIC_MS_WRTDATA_LO; 1130 ms->wd[3] = QLCNIC_MS_WRTDATA_HI; 1131 ms->rd[2] = QLCNIC_MS_RDDATA_LO; 1132 ms->rd[3] = QLCNIC_MS_RDDATA_HI; 1133 } 1134 1135 ms->ocm_window = OCM_WIN_P3P(off); 1136 ms->off = GET_MEM_OFFS_2M(off); 1137 } 1138 1139 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data) 1140 { 1141 int j, ret = 0; 1142 u32 temp, off8; 1143 struct qlcnic_ms_reg_ctrl ms; 1144 1145 /* Only 64-bit aligned access */ 1146 if (off & 7) 1147 return -EIO; 1148 1149 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl)); 1150 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET, 1151 QLCNIC_ADDR_QDR_NET_MAX) || 1152 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, 1153 QLCNIC_ADDR_DDR_NET_MAX))) 1154 return -EIO; 1155 1156 qlcnic_set_ms_controls(adapter, off, &ms); 1157 1158 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) 1159 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window, 1160 ms.off, &data, 1); 1161 1162 off8 = off & ~0xf; 1163 1164 mutex_lock(&adapter->ahw->mem_lock); 1165 1166 qlcnic_ind_wr(adapter, ms.low, off8); 1167 qlcnic_ind_wr(adapter, ms.hi, 0); 1168 1169 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE); 1170 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE); 1171 1172 for (j = 0; j < MAX_CTL_CHECK; j++) { 1173 temp = qlcnic_ind_rd(adapter, ms.control); 1174 if ((temp & TA_CTL_BUSY) == 0) 1175 break; 1176 } 1177 1178 if (j >= MAX_CTL_CHECK) { 1179 ret = -EIO; 1180 goto done; 1181 } 1182 1183 /* This is the modify part of read-modify-write */ 1184 qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0])); 1185 qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1])); 1186 /* This is the write part of read-modify-write */ 1187 qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff); 1188 qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff); 1189 1190 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE); 1191 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START); 1192 1193 for (j = 0; j < MAX_CTL_CHECK; j++) { 1194 temp = qlcnic_ind_rd(adapter, ms.control); 1195 if ((temp & TA_CTL_BUSY) == 0) 1196 break; 1197 } 1198 1199 if (j >= MAX_CTL_CHECK) { 1200 if (printk_ratelimit()) 1201 dev_err(&adapter->pdev->dev, 1202 "failed to write through agent\n"); 1203 ret = -EIO; 1204 } else 1205 ret = 0; 1206 1207 done: 1208 mutex_unlock(&adapter->ahw->mem_lock); 1209 1210 return ret; 1211 } 1212 1213 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data) 1214 { 1215 int j, ret; 1216 u32 temp, off8; 1217 u64 val; 1218 struct qlcnic_ms_reg_ctrl ms; 1219 1220 /* Only 64-bit aligned access */ 1221 if (off & 7) 1222 return -EIO; 1223 if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET, 1224 QLCNIC_ADDR_QDR_NET_MAX) || 1225 ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, 1226 QLCNIC_ADDR_DDR_NET_MAX))) 1227 return -EIO; 1228 1229 memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl)); 1230 qlcnic_set_ms_controls(adapter, off, &ms); 1231 1232 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) 1233 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window, 1234 ms.off, data, 0); 1235 1236 mutex_lock(&adapter->ahw->mem_lock); 1237 1238 off8 = off & ~0xf; 1239 1240 qlcnic_ind_wr(adapter, ms.low, off8); 1241 qlcnic_ind_wr(adapter, ms.hi, 0); 1242 1243 qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE); 1244 qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE); 1245 1246 for (j = 0; j < MAX_CTL_CHECK; j++) { 1247 temp = qlcnic_ind_rd(adapter, ms.control); 1248 if ((temp & TA_CTL_BUSY) == 0) 1249 break; 1250 } 1251 1252 if (j >= MAX_CTL_CHECK) { 1253 if (printk_ratelimit()) 1254 dev_err(&adapter->pdev->dev, 1255 "failed to read through agent\n"); 1256 ret = -EIO; 1257 } else { 1258 1259 temp = qlcnic_ind_rd(adapter, ms.rd[3]); 1260 val = (u64)temp << 32; 1261 val |= qlcnic_ind_rd(adapter, ms.rd[2]); 1262 *data = val; 1263 ret = 0; 1264 } 1265 1266 mutex_unlock(&adapter->ahw->mem_lock); 1267 1268 return ret; 1269 } 1270 1271 int qlcnic_get_board_info(struct qlcnic_adapter *adapter) 1272 { 1273 int offset, board_type, magic; 1274 struct pci_dev *pdev = adapter->pdev; 1275 1276 offset = QLCNIC_FW_MAGIC_OFFSET; 1277 if (qlcnic_rom_fast_read(adapter, offset, &magic)) 1278 return -EIO; 1279 1280 if (magic != QLCNIC_BDINFO_MAGIC) { 1281 dev_err(&pdev->dev, "invalid board config, magic=%08x\n", 1282 magic); 1283 return -EIO; 1284 } 1285 1286 offset = QLCNIC_BRDTYPE_OFFSET; 1287 if (qlcnic_rom_fast_read(adapter, offset, &board_type)) 1288 return -EIO; 1289 1290 adapter->ahw->board_type = board_type; 1291 1292 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) { 1293 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I); 1294 if ((gpio & 0x8000) == 0) 1295 board_type = QLCNIC_BRDTYPE_P3P_10G_TP; 1296 } 1297 1298 switch (board_type) { 1299 case QLCNIC_BRDTYPE_P3P_HMEZ: 1300 case QLCNIC_BRDTYPE_P3P_XG_LOM: 1301 case QLCNIC_BRDTYPE_P3P_10G_CX4: 1302 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP: 1303 case QLCNIC_BRDTYPE_P3P_IMEZ: 1304 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS: 1305 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT: 1306 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT: 1307 case QLCNIC_BRDTYPE_P3P_10G_XFP: 1308 case QLCNIC_BRDTYPE_P3P_10000_BASE_T: 1309 adapter->ahw->port_type = QLCNIC_XGBE; 1310 break; 1311 case QLCNIC_BRDTYPE_P3P_REF_QG: 1312 case QLCNIC_BRDTYPE_P3P_4_GB: 1313 case QLCNIC_BRDTYPE_P3P_4_GB_MM: 1314 adapter->ahw->port_type = QLCNIC_GBE; 1315 break; 1316 case QLCNIC_BRDTYPE_P3P_10G_TP: 1317 adapter->ahw->port_type = (adapter->portnum < 2) ? 1318 QLCNIC_XGBE : QLCNIC_GBE; 1319 break; 1320 default: 1321 dev_err(&pdev->dev, "unknown board type %x\n", board_type); 1322 adapter->ahw->port_type = QLCNIC_XGBE; 1323 break; 1324 } 1325 1326 return 0; 1327 } 1328 1329 int 1330 qlcnic_wol_supported(struct qlcnic_adapter *adapter) 1331 { 1332 u32 wol_cfg; 1333 1334 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV); 1335 if (wol_cfg & (1UL << adapter->portnum)) { 1336 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG); 1337 if (wol_cfg & (1 << adapter->portnum)) 1338 return 1; 1339 } 1340 1341 return 0; 1342 } 1343 1344 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate) 1345 { 1346 struct qlcnic_nic_req req; 1347 int rv; 1348 u64 word; 1349 1350 memset(&req, 0, sizeof(struct qlcnic_nic_req)); 1351 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23); 1352 1353 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16); 1354 req.req_hdr = cpu_to_le64(word); 1355 1356 req.words[0] = cpu_to_le64((u64)rate << 32); 1357 req.words[1] = cpu_to_le64(state); 1358 1359 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 1360 if (rv) 1361 dev_err(&adapter->pdev->dev, "LED configuration failed.\n"); 1362 1363 return rv; 1364 } 1365