1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic qlcnic NIC Driver 4 * Copyright (c) 2009-2013 QLogic Corporation 5 */ 6 7 #ifndef __QLCNIC_HDR_H_ 8 #define __QLCNIC_HDR_H_ 9 10 #include <linux/kernel.h> 11 #include <linux/types.h> 12 13 #include "qlcnic_hw.h" 14 15 /* 16 * The basic unit of access when reading/writing control registers. 17 */ 18 19 enum { 20 QLCNIC_HW_H0_CH_HUB_ADR = 0x05, 21 QLCNIC_HW_H1_CH_HUB_ADR = 0x0E, 22 QLCNIC_HW_H2_CH_HUB_ADR = 0x03, 23 QLCNIC_HW_H3_CH_HUB_ADR = 0x01, 24 QLCNIC_HW_H4_CH_HUB_ADR = 0x06, 25 QLCNIC_HW_H5_CH_HUB_ADR = 0x07, 26 QLCNIC_HW_H6_CH_HUB_ADR = 0x08 27 }; 28 29 /* Hub 0 */ 30 enum { 31 QLCNIC_HW_MN_CRB_AGT_ADR = 0x15, 32 QLCNIC_HW_MS_CRB_AGT_ADR = 0x25 33 }; 34 35 /* Hub 1 */ 36 enum { 37 QLCNIC_HW_PS_CRB_AGT_ADR = 0x73, 38 QLCNIC_HW_SS_CRB_AGT_ADR = 0x20, 39 QLCNIC_HW_RPMX3_CRB_AGT_ADR = 0x0b, 40 QLCNIC_HW_QMS_CRB_AGT_ADR = 0x00, 41 QLCNIC_HW_SQGS0_CRB_AGT_ADR = 0x01, 42 QLCNIC_HW_SQGS1_CRB_AGT_ADR = 0x02, 43 QLCNIC_HW_SQGS2_CRB_AGT_ADR = 0x03, 44 QLCNIC_HW_SQGS3_CRB_AGT_ADR = 0x04, 45 QLCNIC_HW_C2C0_CRB_AGT_ADR = 0x58, 46 QLCNIC_HW_C2C1_CRB_AGT_ADR = 0x59, 47 QLCNIC_HW_C2C2_CRB_AGT_ADR = 0x5a, 48 QLCNIC_HW_RPMX2_CRB_AGT_ADR = 0x0a, 49 QLCNIC_HW_RPMX4_CRB_AGT_ADR = 0x0c, 50 QLCNIC_HW_RPMX7_CRB_AGT_ADR = 0x0f, 51 QLCNIC_HW_RPMX9_CRB_AGT_ADR = 0x12, 52 QLCNIC_HW_SMB_CRB_AGT_ADR = 0x18 53 }; 54 55 /* Hub 2 */ 56 enum { 57 QLCNIC_HW_NIU_CRB_AGT_ADR = 0x31, 58 QLCNIC_HW_I2C0_CRB_AGT_ADR = 0x19, 59 QLCNIC_HW_I2C1_CRB_AGT_ADR = 0x29, 60 61 QLCNIC_HW_SN_CRB_AGT_ADR = 0x10, 62 QLCNIC_HW_I2Q_CRB_AGT_ADR = 0x20, 63 QLCNIC_HW_LPC_CRB_AGT_ADR = 0x22, 64 QLCNIC_HW_ROMUSB_CRB_AGT_ADR = 0x21, 65 QLCNIC_HW_QM_CRB_AGT_ADR = 0x66, 66 QLCNIC_HW_SQG0_CRB_AGT_ADR = 0x60, 67 QLCNIC_HW_SQG1_CRB_AGT_ADR = 0x61, 68 QLCNIC_HW_SQG2_CRB_AGT_ADR = 0x62, 69 QLCNIC_HW_SQG3_CRB_AGT_ADR = 0x63, 70 QLCNIC_HW_RPMX1_CRB_AGT_ADR = 0x09, 71 QLCNIC_HW_RPMX5_CRB_AGT_ADR = 0x0d, 72 QLCNIC_HW_RPMX6_CRB_AGT_ADR = 0x0e, 73 QLCNIC_HW_RPMX8_CRB_AGT_ADR = 0x11 74 }; 75 76 /* Hub 3 */ 77 enum { 78 QLCNIC_HW_PH_CRB_AGT_ADR = 0x1A, 79 QLCNIC_HW_SRE_CRB_AGT_ADR = 0x50, 80 QLCNIC_HW_EG_CRB_AGT_ADR = 0x51, 81 QLCNIC_HW_RPMX0_CRB_AGT_ADR = 0x08 82 }; 83 84 /* Hub 4 */ 85 enum { 86 QLCNIC_HW_PEGN0_CRB_AGT_ADR = 0x40, 87 QLCNIC_HW_PEGN1_CRB_AGT_ADR, 88 QLCNIC_HW_PEGN2_CRB_AGT_ADR, 89 QLCNIC_HW_PEGN3_CRB_AGT_ADR, 90 QLCNIC_HW_PEGNI_CRB_AGT_ADR, 91 QLCNIC_HW_PEGND_CRB_AGT_ADR, 92 QLCNIC_HW_PEGNC_CRB_AGT_ADR, 93 QLCNIC_HW_PEGR0_CRB_AGT_ADR, 94 QLCNIC_HW_PEGR1_CRB_AGT_ADR, 95 QLCNIC_HW_PEGR2_CRB_AGT_ADR, 96 QLCNIC_HW_PEGR3_CRB_AGT_ADR, 97 QLCNIC_HW_PEGN4_CRB_AGT_ADR 98 }; 99 100 /* Hub 5 */ 101 enum { 102 QLCNIC_HW_PEGS0_CRB_AGT_ADR = 0x40, 103 QLCNIC_HW_PEGS1_CRB_AGT_ADR, 104 QLCNIC_HW_PEGS2_CRB_AGT_ADR, 105 QLCNIC_HW_PEGS3_CRB_AGT_ADR, 106 QLCNIC_HW_PEGSI_CRB_AGT_ADR, 107 QLCNIC_HW_PEGSD_CRB_AGT_ADR, 108 QLCNIC_HW_PEGSC_CRB_AGT_ADR 109 }; 110 111 /* Hub 6 */ 112 enum { 113 QLCNIC_HW_CAS0_CRB_AGT_ADR = 0x46, 114 QLCNIC_HW_CAS1_CRB_AGT_ADR = 0x47, 115 QLCNIC_HW_CAS2_CRB_AGT_ADR = 0x48, 116 QLCNIC_HW_CAS3_CRB_AGT_ADR = 0x49, 117 QLCNIC_HW_NCM_CRB_AGT_ADR = 0x16, 118 QLCNIC_HW_TMR_CRB_AGT_ADR = 0x17, 119 QLCNIC_HW_XDMA_CRB_AGT_ADR = 0x05, 120 QLCNIC_HW_OCM0_CRB_AGT_ADR = 0x06, 121 QLCNIC_HW_OCM1_CRB_AGT_ADR = 0x07 122 }; 123 124 /* Floaters - non existent modules */ 125 #define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR 0x67 126 127 /* This field defines PCI/X adr [25:20] of agents on the CRB */ 128 enum { 129 QLCNIC_HW_PX_MAP_CRB_PH = 0, 130 QLCNIC_HW_PX_MAP_CRB_PS, 131 QLCNIC_HW_PX_MAP_CRB_MN, 132 QLCNIC_HW_PX_MAP_CRB_MS, 133 QLCNIC_HW_PX_MAP_CRB_PGR1, 134 QLCNIC_HW_PX_MAP_CRB_SRE, 135 QLCNIC_HW_PX_MAP_CRB_NIU, 136 QLCNIC_HW_PX_MAP_CRB_QMN, 137 QLCNIC_HW_PX_MAP_CRB_SQN0, 138 QLCNIC_HW_PX_MAP_CRB_SQN1, 139 QLCNIC_HW_PX_MAP_CRB_SQN2, 140 QLCNIC_HW_PX_MAP_CRB_SQN3, 141 QLCNIC_HW_PX_MAP_CRB_QMS, 142 QLCNIC_HW_PX_MAP_CRB_SQS0, 143 QLCNIC_HW_PX_MAP_CRB_SQS1, 144 QLCNIC_HW_PX_MAP_CRB_SQS2, 145 QLCNIC_HW_PX_MAP_CRB_SQS3, 146 QLCNIC_HW_PX_MAP_CRB_PGN0, 147 QLCNIC_HW_PX_MAP_CRB_PGN1, 148 QLCNIC_HW_PX_MAP_CRB_PGN2, 149 QLCNIC_HW_PX_MAP_CRB_PGN3, 150 QLCNIC_HW_PX_MAP_CRB_PGND, 151 QLCNIC_HW_PX_MAP_CRB_PGNI, 152 QLCNIC_HW_PX_MAP_CRB_PGS0, 153 QLCNIC_HW_PX_MAP_CRB_PGS1, 154 QLCNIC_HW_PX_MAP_CRB_PGS2, 155 QLCNIC_HW_PX_MAP_CRB_PGS3, 156 QLCNIC_HW_PX_MAP_CRB_PGSD, 157 QLCNIC_HW_PX_MAP_CRB_PGSI, 158 QLCNIC_HW_PX_MAP_CRB_SN, 159 QLCNIC_HW_PX_MAP_CRB_PGR2, 160 QLCNIC_HW_PX_MAP_CRB_EG, 161 QLCNIC_HW_PX_MAP_CRB_PH2, 162 QLCNIC_HW_PX_MAP_CRB_PS2, 163 QLCNIC_HW_PX_MAP_CRB_CAM, 164 QLCNIC_HW_PX_MAP_CRB_CAS0, 165 QLCNIC_HW_PX_MAP_CRB_CAS1, 166 QLCNIC_HW_PX_MAP_CRB_CAS2, 167 QLCNIC_HW_PX_MAP_CRB_C2C0, 168 QLCNIC_HW_PX_MAP_CRB_C2C1, 169 QLCNIC_HW_PX_MAP_CRB_TIMR, 170 QLCNIC_HW_PX_MAP_CRB_PGR3, 171 QLCNIC_HW_PX_MAP_CRB_RPMX1, 172 QLCNIC_HW_PX_MAP_CRB_RPMX2, 173 QLCNIC_HW_PX_MAP_CRB_RPMX3, 174 QLCNIC_HW_PX_MAP_CRB_RPMX4, 175 QLCNIC_HW_PX_MAP_CRB_RPMX5, 176 QLCNIC_HW_PX_MAP_CRB_RPMX6, 177 QLCNIC_HW_PX_MAP_CRB_RPMX7, 178 QLCNIC_HW_PX_MAP_CRB_XDMA, 179 QLCNIC_HW_PX_MAP_CRB_I2Q, 180 QLCNIC_HW_PX_MAP_CRB_ROMUSB, 181 QLCNIC_HW_PX_MAP_CRB_CAS3, 182 QLCNIC_HW_PX_MAP_CRB_RPMX0, 183 QLCNIC_HW_PX_MAP_CRB_RPMX8, 184 QLCNIC_HW_PX_MAP_CRB_RPMX9, 185 QLCNIC_HW_PX_MAP_CRB_OCM0, 186 QLCNIC_HW_PX_MAP_CRB_OCM1, 187 QLCNIC_HW_PX_MAP_CRB_SMB, 188 QLCNIC_HW_PX_MAP_CRB_I2C0, 189 QLCNIC_HW_PX_MAP_CRB_I2C1, 190 QLCNIC_HW_PX_MAP_CRB_LPC, 191 QLCNIC_HW_PX_MAP_CRB_PGNC, 192 QLCNIC_HW_PX_MAP_CRB_PGR0 193 }; 194 195 #define BIT_0 0x1 196 #define BIT_1 0x2 197 #define BIT_2 0x4 198 #define BIT_3 0x8 199 #define BIT_4 0x10 200 #define BIT_5 0x20 201 #define BIT_6 0x40 202 #define BIT_7 0x80 203 #define BIT_8 0x100 204 #define BIT_9 0x200 205 #define BIT_10 0x400 206 #define BIT_11 0x800 207 #define BIT_12 0x1000 208 #define BIT_13 0x2000 209 #define BIT_14 0x4000 210 #define BIT_15 0x8000 211 #define BIT_16 0x10000 212 #define BIT_17 0x20000 213 #define BIT_18 0x40000 214 #define BIT_19 0x80000 215 #define BIT_20 0x100000 216 #define BIT_21 0x200000 217 #define BIT_22 0x400000 218 #define BIT_23 0x800000 219 #define BIT_24 0x1000000 220 #define BIT_25 0x2000000 221 #define BIT_26 0x4000000 222 #define BIT_27 0x8000000 223 #define BIT_28 0x10000000 224 #define BIT_29 0x20000000 225 #define BIT_30 0x40000000 226 #define BIT_31 0x80000000 227 228 /* This field defines CRB adr [31:20] of the agents */ 229 230 #define QLCNIC_HW_CRB_HUB_AGT_ADR_MN \ 231 ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR) 232 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PH \ 233 ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR) 234 #define QLCNIC_HW_CRB_HUB_AGT_ADR_MS \ 235 ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR) 236 237 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PS \ 238 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR) 239 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SS \ 240 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR) 241 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3 \ 242 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR) 243 #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS \ 244 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR) 245 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0 \ 246 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR) 247 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1 \ 248 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR) 249 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2 \ 250 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR) 251 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3 \ 252 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR) 253 #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0 \ 254 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR) 255 #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1 \ 256 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR) 257 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2 \ 258 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR) 259 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4 \ 260 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR) 261 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7 \ 262 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR) 263 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9 \ 264 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR) 265 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB \ 266 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR) 267 268 #define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU \ 269 ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR) 270 #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0 \ 271 ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR) 272 #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1 \ 273 ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR) 274 275 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE \ 276 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR) 277 #define QLCNIC_HW_CRB_HUB_AGT_ADR_EG \ 278 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR) 279 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0 \ 280 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR) 281 #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN \ 282 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR) 283 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0 \ 284 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR) 285 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1 \ 286 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR) 287 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2 \ 288 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR) 289 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3 \ 290 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR) 291 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1 \ 292 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR) 293 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5 \ 294 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR) 295 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6 \ 296 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR) 297 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8 \ 298 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR) 299 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0 \ 300 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR) 301 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1 \ 302 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR) 303 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2 \ 304 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR) 305 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3 \ 306 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR) 307 308 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI \ 309 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR) 310 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND \ 311 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR) 312 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0 \ 313 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR) 314 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1 \ 315 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR) 316 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2 \ 317 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR) 318 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3 \ 319 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR) 320 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4 \ 321 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR) 322 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC \ 323 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR) 324 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0 \ 325 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR) 326 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1 \ 327 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR) 328 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2 \ 329 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR) 330 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3 \ 331 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR) 332 333 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI \ 334 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR) 335 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD \ 336 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR) 337 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0 \ 338 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR) 339 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1 \ 340 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR) 341 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2 \ 342 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR) 343 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3 \ 344 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR) 345 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC \ 346 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR) 347 348 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM \ 349 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR) 350 #define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR \ 351 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR) 352 #define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA \ 353 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR) 354 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SN \ 355 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR) 356 #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q \ 357 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR) 358 #define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB \ 359 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR) 360 #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0 \ 361 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR) 362 #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1 \ 363 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR) 364 #define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC \ 365 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR) 366 367 #define QLCNIC_SRE_MISC (QLCNIC_CRB_SRE + 0x0002c) 368 369 #define QLCNIC_I2Q_CLR_PCI_HI (QLCNIC_CRB_I2Q + 0x00034) 370 371 #define ROMUSB_GLB (QLCNIC_CRB_ROMUSB + 0x00000) 372 #define ROMUSB_ROM (QLCNIC_CRB_ROMUSB + 0x10000) 373 374 #define QLCNIC_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) 375 #define QLCNIC_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) 376 #define QLCNIC_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c) 377 #define QLCNIC_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) 378 #define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044) 379 #define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) 380 #define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8) 381 382 #define QLCNIC_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n))) 383 384 #define QLCNIC_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) 385 #define QLCNIC_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) 386 #define QLCNIC_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) 387 #define QLCNIC_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) 388 #define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) 389 #define QLCNIC_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) 390 391 /****************************************************************************** 392 * 393 * Definitions specific to M25P flash 394 * 395 ******************************************************************************* 396 */ 397 398 /* all are 1MB windows */ 399 400 #define QLCNIC_PCI_CRB_WINDOWSIZE 0x00100000 401 #define QLCNIC_PCI_CRB_WINDOW(A) \ 402 (QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE) 403 404 #define QLCNIC_CRB_NIU QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU) 405 #define QLCNIC_CRB_SRE QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE) 406 #define QLCNIC_CRB_ROMUSB \ 407 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB) 408 #define QLCNIC_CRB_EPG QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_EG) 409 #define QLCNIC_CRB_I2Q QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q) 410 #define QLCNIC_CRB_TIMER QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_TIMR) 411 #define QLCNIC_CRB_I2C0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0) 412 #define QLCNIC_CRB_SMB QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB) 413 #define QLCNIC_CRB_MAX QLCNIC_PCI_CRB_WINDOW(64) 414 415 #define QLCNIC_CRB_PCIX_HOST QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH) 416 #define QLCNIC_CRB_PCIX_HOST2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2) 417 #define QLCNIC_CRB_PEG_NET_0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0) 418 #define QLCNIC_CRB_PEG_NET_1 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1) 419 #define QLCNIC_CRB_PEG_NET_2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2) 420 #define QLCNIC_CRB_PEG_NET_3 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3) 421 #define QLCNIC_CRB_PEG_NET_4 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2) 422 #define QLCNIC_CRB_PEG_NET_D QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND) 423 #define QLCNIC_CRB_PEG_NET_I QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI) 424 #define QLCNIC_CRB_DDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN) 425 #define QLCNIC_CRB_QDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN) 426 427 #define QLCNIC_CRB_PCIX_MD QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS) 428 #define QLCNIC_CRB_PCIE QLCNIC_CRB_PCIX_MD 429 430 #define ISR_INT_VECTOR (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR)) 431 #define ISR_INT_MASK (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK)) 432 #define ISR_INT_MASK_SLOW (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK)) 433 #define ISR_INT_TARGET_STATUS (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS)) 434 #define ISR_INT_TARGET_MASK (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK)) 435 #define ISR_INT_TARGET_STATUS_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) 436 #define ISR_INT_TARGET_MASK_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) 437 #define ISR_INT_TARGET_STATUS_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) 438 #define ISR_INT_TARGET_MASK_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) 439 #define ISR_INT_TARGET_STATUS_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) 440 #define ISR_INT_TARGET_MASK_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) 441 #define ISR_INT_TARGET_STATUS_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) 442 #define ISR_INT_TARGET_MASK_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) 443 #define ISR_INT_TARGET_STATUS_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) 444 #define ISR_INT_TARGET_MASK_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) 445 #define ISR_INT_TARGET_STATUS_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) 446 #define ISR_INT_TARGET_MASK_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) 447 #define ISR_INT_TARGET_STATUS_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) 448 #define ISR_INT_TARGET_MASK_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) 449 450 #define QLCNIC_PCI_OCM0_2M (0x000c0000UL) 451 #define QLCNIC_PCI_CRBSPACE (0x06000000UL) 452 #define QLCNIC_PCI_CAMQM (0x04800000UL) 453 #define QLCNIC_PCI_CAMQM_END (0x04800800UL) 454 #define QLCNIC_PCI_CAMQM_2M_BASE (0x000ff800UL) 455 456 #define QLCNIC_CRB_CAM QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM) 457 458 #define QLCNIC_ADDR_DDR_NET (0x0000000000000000ULL) 459 #define QLCNIC_ADDR_DDR_NET_MAX (0x000000000fffffffULL) 460 #define QLCNIC_ADDR_OCM0 (0x0000000200000000ULL) 461 #define QLCNIC_ADDR_OCM0_MAX (0x00000002000fffffULL) 462 #define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL) 463 #define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL) 464 #define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL) 465 #define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL) 466 467 /* 468 * Register offsets for MN 469 */ 470 #define QLCNIC_MIU_CONTROL (0x000) 471 #define QLCNIC_MIU_MN_CONTROL (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL) 472 473 /* 200ms delay in each loop */ 474 #define QLCNIC_NIU_PHY_WAITLEN 200000 475 /* 10 seconds before we give up */ 476 #define QLCNIC_NIU_PHY_WAITMAX 50 477 #define QLCNIC_NIU_MAX_GBE_PORTS 4 478 #define QLCNIC_NIU_MAX_XG_PORTS 2 479 480 #define QLCNIC_NIU_MODE (QLCNIC_CRB_NIU + 0x00000) 481 #define QLCNIC_NIU_GB_PAUSE_CTL (QLCNIC_CRB_NIU + 0x0030c) 482 #define QLCNIC_NIU_XG_PAUSE_CTL (QLCNIC_CRB_NIU + 0x00098) 483 484 #define QLCNIC_NIU_GB_MAC_CONFIG_0(I) \ 485 (QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000) 486 #define QLCNIC_NIU_GB_MAC_CONFIG_1(I) \ 487 (QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000) 488 489 #define MAX_CTL_CHECK 1000 490 #define TEST_AGT_CTRL (0x00) 491 492 #define TA_CTL_START BIT_0 493 #define TA_CTL_ENABLE BIT_1 494 #define TA_CTL_WRITE BIT_2 495 #define TA_CTL_BUSY BIT_3 496 497 /* XG Link status */ 498 #define XG_LINK_UP 0x10 499 #define XG_LINK_DOWN 0x20 500 501 #define XG_LINK_UP_P3P 0x01 502 #define XG_LINK_DOWN_P3P 0x02 503 #define XG_LINK_STATE_P3P_MASK 0xf 504 #define XG_LINK_STATE_P3P(pcifn, val) \ 505 (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3P_MASK) 506 507 #define P3P_LINK_SPEED_MHZ 100 508 #define P3P_LINK_SPEED_MASK 0xff 509 #define P3P_LINK_SPEED_REG(pcifn) \ 510 (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4)) 511 #define P3P_LINK_SPEED_VAL(pcifn, reg) \ 512 (((reg) >> (8 * ((pcifn) & 0x3))) & P3P_LINK_SPEED_MASK) 513 514 #define QLCNIC_CAM_RAM_BASE (QLCNIC_CRB_CAM + 0x02000) 515 #define QLCNIC_CAM_RAM(reg) (QLCNIC_CAM_RAM_BASE + (reg)) 516 #define QLCNIC_ROM_LOCK_ID (QLCNIC_CAM_RAM(0x100)) 517 #define QLCNIC_PHY_LOCK_ID (QLCNIC_CAM_RAM(0x120)) 518 #define QLCNIC_CRB_WIN_LOCK_ID (QLCNIC_CAM_RAM(0x124)) 519 520 #define NIC_CRB_BASE (QLCNIC_CAM_RAM(0x200)) 521 #define NIC_CRB_BASE_2 (QLCNIC_CAM_RAM(0x700)) 522 #define QLCNIC_REG(X) (NIC_CRB_BASE+(X)) 523 #define QLCNIC_REG_2(X) (NIC_CRB_BASE_2+(X)) 524 525 #define QLCNIC_CDRP_MAX_ARGS 4 526 #define QLCNIC_CDRP_ARG(i) (QLCNIC_REG(0x18 + ((i) * 4))) 527 528 #define QLCNIC_CDRP_CRB_OFFSET (QLCNIC_REG(0x18)) 529 #define QLCNIC_SIGN_CRB_OFFSET (QLCNIC_REG(0x28)) 530 531 #define CRB_XG_STATE_P3P (QLCNIC_REG(0x98)) 532 #define CRB_PF_LINK_SPEED_1 (QLCNIC_REG(0xe8)) 533 #define CRB_DRIVER_VERSION (QLCNIC_REG(0x2a0)) 534 535 #define CRB_FW_CAPABILITIES_2 (QLCNIC_CAM_RAM(0x12c)) 536 537 /* 538 * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address 539 * which can be read by the Phantom host to get producer/consumer indexes from 540 * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following 541 * registers will be used for the addresses of the ring's shared memory 542 * on the Phantom. 543 */ 544 545 #define qlcnic_get_temp_val(x) ((x) >> 16) 546 #define qlcnic_get_temp_state(x) ((x) & 0xffff) 547 #define qlcnic_encode_temp(val, state) (((val) << 16) | (state)) 548 549 /* 550 * Temperature control. 551 */ 552 enum { 553 QLCNIC_TEMP_NORMAL = 0x1, /* Normal operating range */ 554 QLCNIC_TEMP_WARN, /* Sound alert, temperature getting high */ 555 QLCNIC_TEMP_PANIC /* Fatal error, hardware has shut down. */ 556 }; 557 558 559 /* Lock IDs for PHY lock */ 560 #define PHY_LOCK_DRIVER 0x44524956 561 562 #define PCIX_INT_VECTOR (0x10100) 563 #define PCIX_INT_MASK (0x10104) 564 565 #define PCIX_OCM_WINDOW (0x10800) 566 #define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x4 * (func)) 567 568 #define PCIX_TARGET_STATUS (0x10118) 569 #define PCIX_TARGET_STATUS_F1 (0x10160) 570 #define PCIX_TARGET_STATUS_F2 (0x10164) 571 #define PCIX_TARGET_STATUS_F3 (0x10168) 572 #define PCIX_TARGET_STATUS_F4 (0x10360) 573 #define PCIX_TARGET_STATUS_F5 (0x10364) 574 #define PCIX_TARGET_STATUS_F6 (0x10368) 575 #define PCIX_TARGET_STATUS_F7 (0x1036c) 576 577 #define PCIX_TARGET_MASK (0x10128) 578 #define PCIX_TARGET_MASK_F1 (0x10170) 579 #define PCIX_TARGET_MASK_F2 (0x10174) 580 #define PCIX_TARGET_MASK_F3 (0x10178) 581 #define PCIX_TARGET_MASK_F4 (0x10370) 582 #define PCIX_TARGET_MASK_F5 (0x10374) 583 #define PCIX_TARGET_MASK_F6 (0x10378) 584 #define PCIX_TARGET_MASK_F7 (0x1037c) 585 586 #define PCIX_MSI_F(i) (0x13000+((i)*4)) 587 588 #define QLCNIC_PCIX_PH_REG(reg) (QLCNIC_CRB_PCIE + (reg)) 589 #define QLCNIC_PCIX_PS_REG(reg) (QLCNIC_CRB_PCIX_MD + (reg)) 590 #define QLCNIC_PCIE_REG(reg) (QLCNIC_CRB_PCIE + (reg)) 591 592 #define PCIE_SEM0_LOCK (0x1c000) 593 #define PCIE_SEM0_UNLOCK (0x1c004) 594 #define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N)) 595 #define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N)) 596 597 #define PCIE_SETUP_FUNCTION (0x12040) 598 #define PCIE_SETUP_FUNCTION2 (0x12048) 599 #define PCIE_MISCCFG_RC (0x1206c) 600 #define PCIE_TGT_SPLIT_CHICKEN (0x12080) 601 #define PCIE_CHICKEN3 (0x120c8) 602 603 #define ISR_INT_STATE_REG (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC)) 604 #define PCIE_MAX_MASTER_SPLIT (0x14048) 605 606 #define QLCNIC_PORT_MODE_NONE 0 607 #define QLCNIC_PORT_MODE_XG 1 608 #define QLCNIC_PORT_MODE_GB 2 609 #define QLCNIC_PORT_MODE_802_3_AP 3 610 #define QLCNIC_PORT_MODE_AUTO_NEG 4 611 #define QLCNIC_PORT_MODE_AUTO_NEG_1G 5 612 #define QLCNIC_PORT_MODE_AUTO_NEG_XG 6 613 #define QLCNIC_PORT_MODE_ADDR (QLCNIC_CAM_RAM(0x24)) 614 #define QLCNIC_WOL_PORT_MODE (QLCNIC_CAM_RAM(0x198)) 615 616 #define QLCNIC_WOL_CONFIG_NV (QLCNIC_CAM_RAM(0x184)) 617 #define QLCNIC_WOL_CONFIG (QLCNIC_CAM_RAM(0x188)) 618 619 #define QLCNIC_PEG_TUNE_MN_PRESENT 0x1 620 #define QLCNIC_PEG_TUNE_CAPABILITY (QLCNIC_CAM_RAM(0x02c)) 621 622 #define QLCNIC_DMA_WATCHDOG_CTRL (QLCNIC_CAM_RAM(0x14)) 623 #define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c) 624 #define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860) 625 626 /* Device State */ 627 #define QLCNIC_DEV_COLD 0x1 628 #define QLCNIC_DEV_INITIALIZING 0x2 629 #define QLCNIC_DEV_READY 0x3 630 #define QLCNIC_DEV_NEED_RESET 0x4 631 #define QLCNIC_DEV_NEED_QUISCENT 0x5 632 #define QLCNIC_DEV_FAILED 0x6 633 #define QLCNIC_DEV_QUISCENT 0x7 634 635 #define QLCNIC_DEV_BADBAD 0xbad0bad0 636 637 #define QLCNIC_DEV_NPAR_NON_OPER 0 /* NON Operational */ 638 #define QLCNIC_DEV_NPAR_OPER 1 /* NPAR Operational */ 639 #define QLCNIC_DEV_NPAR_OPER_TIMEO 30 /* Operational time out */ 640 641 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) 642 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) 643 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) 644 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) 645 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) 646 647 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) 648 #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) 649 650 #define QLCNIC_TYPE_NIC 1 651 #define QLCNIC_TYPE_FCOE 2 652 #define QLCNIC_TYPE_ISCSI 3 653 654 #define QLCNIC_RCODE_DRIVER_INFO 0x20000000 655 #define QLCNIC_RCODE_DRIVER_CAN_RELOAD BIT_30 656 #define QLCNIC_RCODE_FATAL_ERROR BIT_31 657 #define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff) 658 #define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0x1fffff) 659 #define QLCNIC_FWERROR_FAN_FAILURE 0x16 660 661 #define FW_POLL_DELAY (1 * HZ) 662 #define FW_FAIL_THRESH 2 663 664 #define QLCNIC_RESET_TIMEOUT_SECS 10 665 #define QLCNIC_INIT_TIMEOUT_SECS 30 666 #define QLCNIC_RCVPEG_CHECK_RETRY_COUNT 2000 667 #define QLCNIC_RCVPEG_CHECK_DELAY 10 668 #define QLCNIC_CMDPEG_CHECK_RETRY_COUNT 60 669 #define QLCNIC_CMDPEG_CHECK_DELAY 500 670 #define QLCNIC_HEARTBEAT_PERIOD_MSECS 200 671 #define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT 10 672 673 #define QLCNIC_MAX_MC_COUNT 38 674 #define QLCNIC_MAX_UC_COUNT 512 675 #define QLCNIC_WATCHDOG_TIMEOUTVALUE 5 676 677 #define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC))) 678 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) 679 680 /* 681 * PCI Interrupt Vector Values. 682 */ 683 #define PCIX_INT_VECTOR_BIT_F0 0x0080 684 #define PCIX_INT_VECTOR_BIT_F1 0x0100 685 #define PCIX_INT_VECTOR_BIT_F2 0x0200 686 #define PCIX_INT_VECTOR_BIT_F3 0x0400 687 #define PCIX_INT_VECTOR_BIT_F4 0x0800 688 #define PCIX_INT_VECTOR_BIT_F5 0x1000 689 #define PCIX_INT_VECTOR_BIT_F6 0x2000 690 #define PCIX_INT_VECTOR_BIT_F7 0x4000 691 692 struct qlcnic_legacy_intr_set { 693 u32 int_vec_bit; 694 u32 tgt_status_reg; 695 u32 tgt_mask_reg; 696 u32 pci_int_reg; 697 }; 698 699 #define QLCNIC_MSIX_BASE 0x132110 700 #define QLCNIC_MAX_VLAN_FILTERS 64 701 702 #define FLASH_ROM_WINDOW 0x42110030 703 #define FLASH_ROM_DATA 0x42150000 704 705 #define QLCNIC_FW_DUMP_REG1 0x00130060 706 #define QLCNIC_FW_DUMP_REG2 0x001e0000 707 #define QLCNIC_FLASH_SEM2_LK 0x0013C010 708 #define QLCNIC_FLASH_SEM2_ULK 0x0013C014 709 #define QLCNIC_FLASH_LOCK_ID 0x001B2100 710 711 /* PCI function operational mode */ 712 enum { 713 QLCNIC_MGMT_FUNC = 0, 714 QLCNIC_PRIV_FUNC = 1, 715 QLCNIC_NON_PRIV_FUNC = 2, 716 QLCNIC_SRIOV_PF_FUNC = 3, 717 QLCNIC_SRIOV_VF_FUNC = 4, 718 QLCNIC_UNKNOWN_FUNC_MODE = 5 719 }; 720 721 enum { 722 QLCNIC_PORT_DEFAULTS = 0, 723 QLCNIC_ADD_VLAN = 1, 724 QLCNIC_DEL_VLAN = 2 725 }; 726 727 #define QLC_DEV_DRV_DEFAULT 0x11111111 728 729 #define LSB(x) ((uint8_t)(x)) 730 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 731 732 #define LSW(x) ((uint16_t)((uint32_t)(x))) 733 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 734 735 #define LSD(x) ((uint32_t)((uint64_t)(x))) 736 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 737 738 #define QLCNIC_MS_CTRL 0x41000090 739 #define QLCNIC_MS_ADDR_LO 0x41000094 740 #define QLCNIC_MS_ADDR_HI 0x41000098 741 #define QLCNIC_MS_WRTDATA_LO 0x410000A0 742 #define QLCNIC_MS_WRTDATA_HI 0x410000A4 743 #define QLCNIC_MS_WRTDATA_ULO 0x410000B0 744 #define QLCNIC_MS_WRTDATA_UHI 0x410000B4 745 #define QLCNIC_MS_RDDATA_LO 0x410000A8 746 #define QLCNIC_MS_RDDATA_HI 0x410000AC 747 #define QLCNIC_MS_RDDATA_ULO 0x410000B8 748 #define QLCNIC_MS_RDDATA_UHI 0x410000BC 749 750 #define QLCNIC_TA_WRITE_ENABLE (TA_CTL_ENABLE | TA_CTL_WRITE) 751 #define QLCNIC_TA_WRITE_START (TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE) 752 #define QLCNIC_TA_START_ENABLE (TA_CTL_START | TA_CTL_ENABLE) 753 754 #define QLCNIC_LEGACY_INTR_CONFIG \ 755 { \ 756 { \ 757 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ 758 .tgt_status_reg = ISR_INT_TARGET_STATUS, \ 759 .tgt_mask_reg = ISR_INT_TARGET_MASK, }, \ 760 \ 761 { \ 762 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ 763 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ 764 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, }, \ 765 \ 766 { \ 767 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ 768 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ 769 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, }, \ 770 \ 771 { \ 772 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ 773 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ 774 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, }, \ 775 \ 776 { \ 777 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ 778 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ 779 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, }, \ 780 \ 781 { \ 782 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ 783 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ 784 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, }, \ 785 \ 786 { \ 787 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ 788 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ 789 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, }, \ 790 \ 791 { \ 792 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ 793 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ 794 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, }, \ 795 } 796 797 /* NIU REGS */ 798 799 #define _qlcnic_crb_get_bit(var, bit) ((var >> bit) & 0x1) 800 801 /* 802 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3) 803 * 804 * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable 805 * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream 806 * Bit 2 : enable_rx => 1:enable frame recv, 0:disable 807 * Bit 3 : rx_synced => R/O: recv enable synched to recv stream 808 * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable 809 * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore 810 * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal 811 * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op 812 * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op 813 * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op 814 * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op 815 * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op 816 */ 817 #define qlcnic_gb_rx_flowctl(config_word) \ 818 ((config_word) |= 1 << 5) 819 #define qlcnic_gb_get_rx_flowctl(config_word) \ 820 _qlcnic_crb_get_bit((config_word), 5) 821 #define qlcnic_gb_unset_rx_flowctl(config_word) \ 822 ((config_word) &= ~(1 << 5)) 823 824 /* 825 * NIU GB Pause Ctl Register 826 */ 827 828 #define qlcnic_gb_set_gb0_mask(config_word) \ 829 ((config_word) |= 1 << 0) 830 #define qlcnic_gb_set_gb1_mask(config_word) \ 831 ((config_word) |= 1 << 2) 832 #define qlcnic_gb_set_gb2_mask(config_word) \ 833 ((config_word) |= 1 << 4) 834 #define qlcnic_gb_set_gb3_mask(config_word) \ 835 ((config_word) |= 1 << 6) 836 837 #define qlcnic_gb_get_gb0_mask(config_word) \ 838 _qlcnic_crb_get_bit((config_word), 0) 839 #define qlcnic_gb_get_gb1_mask(config_word) \ 840 _qlcnic_crb_get_bit((config_word), 2) 841 #define qlcnic_gb_get_gb2_mask(config_word) \ 842 _qlcnic_crb_get_bit((config_word), 4) 843 #define qlcnic_gb_get_gb3_mask(config_word) \ 844 _qlcnic_crb_get_bit((config_word), 6) 845 846 #define qlcnic_gb_unset_gb0_mask(config_word) \ 847 ((config_word) &= ~(1 << 0)) 848 #define qlcnic_gb_unset_gb1_mask(config_word) \ 849 ((config_word) &= ~(1 << 2)) 850 #define qlcnic_gb_unset_gb2_mask(config_word) \ 851 ((config_word) &= ~(1 << 4)) 852 #define qlcnic_gb_unset_gb3_mask(config_word) \ 853 ((config_word) &= ~(1 << 6)) 854 855 /* 856 * NIU XG Pause Ctl Register 857 * 858 * Bit 0 : xg0_mask => 1:disable tx pause frames 859 * Bit 1 : xg0_request => 1:request single pause frame 860 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off 861 * Bit 3 : xg1_mask => 1:disable tx pause frames 862 * Bit 4 : xg1_request => 1:request single pause frame 863 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off 864 */ 865 866 #define qlcnic_xg_set_xg0_mask(config_word) \ 867 ((config_word) |= 1 << 0) 868 #define qlcnic_xg_set_xg1_mask(config_word) \ 869 ((config_word) |= 1 << 3) 870 871 #define qlcnic_xg_get_xg0_mask(config_word) \ 872 _qlcnic_crb_get_bit((config_word), 0) 873 #define qlcnic_xg_get_xg1_mask(config_word) \ 874 _qlcnic_crb_get_bit((config_word), 3) 875 876 #define qlcnic_xg_unset_xg0_mask(config_word) \ 877 ((config_word) &= ~(1 << 0)) 878 #define qlcnic_xg_unset_xg1_mask(config_word) \ 879 ((config_word) &= ~(1 << 3)) 880 881 /* 882 * NIU XG Pause Ctl Register 883 * 884 * Bit 0 : xg0_mask => 1:disable tx pause frames 885 * Bit 1 : xg0_request => 1:request single pause frame 886 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off 887 * Bit 3 : xg1_mask => 1:disable tx pause frames 888 * Bit 4 : xg1_request => 1:request single pause frame 889 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off 890 */ 891 892 /* 893 * PHY-Specific MII control/status registers. 894 */ 895 #define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG 4 896 #define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17 897 898 /* 899 * PHY-Specific Status Register (reg 17). 900 * 901 * Bit 0 : jabber => 1:jabber detected, 0:not 902 * Bit 1 : polarity => 1:polarity reversed, 0:normal 903 * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled 904 * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled 905 * Bit 4 : energydetect => 1:sleep, 0:active 906 * Bit 5 : downshift => 1:downshift, 0:no downshift 907 * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover) 908 * Bits 7-9 : cablelen => not valid in 10Mb/s mode 909 * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m 910 * Bit 10 : link => 1:link up, 0:link down 911 * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet 912 * Bit 12 : pagercvd => 1:page received, 0:page not received 913 * Bit 13 : duplex => 1:full duplex, 0:half duplex 914 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd 915 */ 916 917 #define qlcnic_get_phy_speed(config_word) (((config_word) >> 14) & 0x03) 918 919 #define qlcnic_set_phy_speed(config_word, val) \ 920 ((config_word) |= ((val & 0x03) << 14)) 921 #define qlcnic_set_phy_duplex(config_word) \ 922 ((config_word) |= 1 << 13) 923 #define qlcnic_clear_phy_duplex(config_word) \ 924 ((config_word) &= ~(1 << 13)) 925 926 #define qlcnic_get_phy_link(config_word) \ 927 _qlcnic_crb_get_bit(config_word, 10) 928 #define qlcnic_get_phy_duplex(config_word) \ 929 _qlcnic_crb_get_bit(config_word, 13) 930 931 #define QLCNIC_NIU_NON_PROMISC_MODE 0 932 #define QLCNIC_NIU_PROMISC_MODE 1 933 #define QLCNIC_NIU_ALLMULTI_MODE 2 934 935 #define QLCNIC_PCIE_SEM_TIMEOUT 10000 936 937 struct crb_128M_2M_sub_block_map { 938 unsigned valid; 939 unsigned start_128M; 940 unsigned end_128M; 941 unsigned start_2M; 942 }; 943 944 struct crb_128M_2M_block_map{ 945 struct crb_128M_2M_sub_block_map sub_block[16]; 946 }; 947 #endif /* __QLCNIC_HDR_H_ */ 948