1 /*
2  * QLogic qlcnic NIC Driver
3  * Copyright (c) 2009-2013 QLogic Corporation
4  *
5  * See LICENSE.qlcnic for copyright and licensing details.
6  */
7 
8 #include "qlcnic_sriov.h"
9 #include "qlcnic.h"
10 #include "qlcnic_hw.h"
11 
12 /* Reset template definitions */
13 #define QLC_83XX_RESTART_TEMPLATE_SIZE		0x2000
14 #define QLC_83XX_RESET_TEMPLATE_ADDR		0x4F0000
15 #define QLC_83XX_RESET_SEQ_VERSION		0x0101
16 
17 #define QLC_83XX_OPCODE_NOP			0x0000
18 #define QLC_83XX_OPCODE_WRITE_LIST		0x0001
19 #define QLC_83XX_OPCODE_READ_WRITE_LIST		0x0002
20 #define QLC_83XX_OPCODE_POLL_LIST		0x0004
21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST		0x0008
22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE	0x0010
23 #define QLC_83XX_OPCODE_SEQ_PAUSE		0x0020
24 #define QLC_83XX_OPCODE_SEQ_END			0x0040
25 #define QLC_83XX_OPCODE_TMPL_END		0x0080
26 #define QLC_83XX_OPCODE_POLL_READ_LIST		0x0100
27 
28 /* EPORT control registers */
29 #define QLC_83XX_RESET_CONTROL			0x28084E50
30 #define QLC_83XX_RESET_REG			0x28084E60
31 #define QLC_83XX_RESET_PORT0			0x28084E70
32 #define QLC_83XX_RESET_PORT1			0x28084E80
33 #define QLC_83XX_RESET_PORT2			0x28084E90
34 #define QLC_83XX_RESET_PORT3			0x28084EA0
35 #define QLC_83XX_RESET_SRESHIM			0x28084EB0
36 #define QLC_83XX_RESET_EPGSHIM			0x28084EC0
37 #define QLC_83XX_RESET_ETHERPCS			0x28084ED0
38 
39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
42 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev);
43 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *);
44 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *);
45 
46 /* Template header */
47 struct qlc_83xx_reset_hdr {
48 #if defined(__LITTLE_ENDIAN)
49 	u16	version;
50 	u16	signature;
51 	u16	size;
52 	u16	entries;
53 	u16	hdr_size;
54 	u16	checksum;
55 	u16	init_offset;
56 	u16	start_offset;
57 #elif defined(__BIG_ENDIAN)
58 	u16	signature;
59 	u16	version;
60 	u16	entries;
61 	u16	size;
62 	u16	checksum;
63 	u16	hdr_size;
64 	u16	start_offset;
65 	u16	init_offset;
66 #endif
67 } __packed;
68 
69 /* Command entry header. */
70 struct qlc_83xx_entry_hdr {
71 #if defined(__LITTLE_ENDIAN)
72 	u16	cmd;
73 	u16	size;
74 	u16	count;
75 	u16	delay;
76 #elif defined(__BIG_ENDIAN)
77 	u16	size;
78 	u16	cmd;
79 	u16	delay;
80 	u16	count;
81 #endif
82 } __packed;
83 
84 /* Generic poll command */
85 struct qlc_83xx_poll {
86 	u32	mask;
87 	u32	status;
88 } __packed;
89 
90 /* Read modify write command */
91 struct qlc_83xx_rmw {
92 	u32	mask;
93 	u32	xor_value;
94 	u32	or_value;
95 #if defined(__LITTLE_ENDIAN)
96 	u8	shl;
97 	u8	shr;
98 	u8	index_a;
99 	u8	rsvd;
100 #elif defined(__BIG_ENDIAN)
101 	u8	rsvd;
102 	u8	index_a;
103 	u8	shr;
104 	u8	shl;
105 #endif
106 } __packed;
107 
108 /* Generic command with 2 DWORD */
109 struct qlc_83xx_entry {
110 	u32 arg1;
111 	u32 arg2;
112 } __packed;
113 
114 /* Generic command with 4 DWORD */
115 struct qlc_83xx_quad_entry {
116 	u32 dr_addr;
117 	u32 dr_value;
118 	u32 ar_addr;
119 	u32 ar_value;
120 } __packed;
121 static const char *const qlc_83xx_idc_states[] = {
122 	"Unknown",
123 	"Cold",
124 	"Init",
125 	"Ready",
126 	"Need Reset",
127 	"Need Quiesce",
128 	"Failed",
129 	"Quiesce"
130 };
131 
132 static int
133 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
134 {
135 	u32 val;
136 
137 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
138 	if ((val & 0xFFFF))
139 		return 1;
140 	else
141 		return 0;
142 }
143 
144 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
145 {
146 	u32 cur, prev;
147 	cur = adapter->ahw->idc.curr_state;
148 	prev = adapter->ahw->idc.prev_state;
149 
150 	dev_info(&adapter->pdev->dev,
151 		 "current state  = %s,  prev state = %s\n",
152 		 adapter->ahw->idc.name[cur],
153 		 adapter->ahw->idc.name[prev]);
154 }
155 
156 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
157 					    u8 mode, int lock)
158 {
159 	u32 val;
160 	int seconds;
161 
162 	if (lock) {
163 		if (qlcnic_83xx_lock_driver(adapter))
164 			return -EBUSY;
165 	}
166 
167 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
168 	val |= (adapter->portnum & 0xf);
169 	val |= mode << 7;
170 	if (mode)
171 		seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
172 	else
173 		seconds = jiffies / HZ;
174 
175 	val |= seconds << 8;
176 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
177 	adapter->ahw->idc.sec_counter = jiffies / HZ;
178 
179 	if (lock)
180 		qlcnic_83xx_unlock_driver(adapter);
181 
182 	return 0;
183 }
184 
185 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
186 {
187 	u32 val;
188 
189 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
190 	val = val & ~(0x3 << (adapter->portnum * 2));
191 	val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
192 	QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
193 }
194 
195 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
196 						int lock)
197 {
198 	u32 val;
199 
200 	if (lock) {
201 		if (qlcnic_83xx_lock_driver(adapter))
202 			return -EBUSY;
203 	}
204 
205 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
206 	val = val & ~0xFF;
207 	val = val | QLC_83XX_IDC_MAJOR_VERSION;
208 	QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
209 
210 	if (lock)
211 		qlcnic_83xx_unlock_driver(adapter);
212 
213 	return 0;
214 }
215 
216 static int
217 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
218 					int status, int lock)
219 {
220 	u32 val;
221 
222 	if (lock) {
223 		if (qlcnic_83xx_lock_driver(adapter))
224 			return -EBUSY;
225 	}
226 
227 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
228 
229 	if (status)
230 		val = val | (1 << adapter->portnum);
231 	else
232 		val = val & ~(1 << adapter->portnum);
233 
234 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
235 	qlcnic_83xx_idc_update_minor_version(adapter);
236 
237 	if (lock)
238 		qlcnic_83xx_unlock_driver(adapter);
239 
240 	return 0;
241 }
242 
243 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
244 {
245 	u32 val;
246 	u8 version;
247 
248 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
249 	version = val & 0xFF;
250 
251 	if (version != QLC_83XX_IDC_MAJOR_VERSION) {
252 		dev_info(&adapter->pdev->dev,
253 			 "%s:mismatch. version 0x%x, expected version 0x%x\n",
254 			 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
255 		return -EIO;
256 	}
257 
258 	return 0;
259 }
260 
261 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
262 					   int lock)
263 {
264 	u32 val;
265 
266 	if (lock) {
267 		if (qlcnic_83xx_lock_driver(adapter))
268 			return -EBUSY;
269 	}
270 
271 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
272 	/* Clear graceful reset bit */
273 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
274 	val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
275 	QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
276 
277 	if (lock)
278 		qlcnic_83xx_unlock_driver(adapter);
279 
280 	return 0;
281 }
282 
283 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
284 					      int flag, int lock)
285 {
286 	u32 val;
287 
288 	if (lock) {
289 		if (qlcnic_83xx_lock_driver(adapter))
290 			return -EBUSY;
291 	}
292 
293 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
294 	if (flag)
295 		val = val | (1 << adapter->portnum);
296 	else
297 		val = val & ~(1 << adapter->portnum);
298 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
299 
300 	if (lock)
301 		qlcnic_83xx_unlock_driver(adapter);
302 
303 	return 0;
304 }
305 
306 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
307 					 int time_limit)
308 {
309 	u64 seconds;
310 
311 	seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
312 	if (seconds <= time_limit)
313 		return 0;
314 	else
315 		return -EBUSY;
316 }
317 
318 /**
319  * qlcnic_83xx_idc_check_reset_ack_reg
320  *
321  * @adapter: adapter structure
322  *
323  * Check ACK wait limit and clear the functions which failed to ACK
324  *
325  * Return 0 if all functions have acknowledged the reset request.
326  **/
327 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
328 {
329 	int timeout;
330 	u32 ack, presence, val;
331 
332 	timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
333 	ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
334 	presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
335 	dev_info(&adapter->pdev->dev,
336 		 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
337 	if (!((ack & presence) == presence)) {
338 		if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
339 			/* Clear functions which failed to ACK */
340 			dev_info(&adapter->pdev->dev,
341 				 "%s: ACK wait exceeds time limit\n", __func__);
342 			val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
343 			val = val & ~(ack ^ presence);
344 			if (qlcnic_83xx_lock_driver(adapter))
345 				return -EBUSY;
346 			QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
347 			dev_info(&adapter->pdev->dev,
348 				 "%s: updated drv presence reg = 0x%x\n",
349 				 __func__, val);
350 			qlcnic_83xx_unlock_driver(adapter);
351 			return 0;
352 
353 		} else {
354 			return 1;
355 		}
356 	} else {
357 		dev_info(&adapter->pdev->dev,
358 			 "%s: Reset ACK received from all functions\n",
359 			 __func__);
360 		return 0;
361 	}
362 }
363 
364 /**
365  * qlcnic_83xx_idc_tx_soft_reset
366  *
367  * @adapter: adapter structure
368  *
369  * Handle context deletion and recreation request from transmit routine
370  *
371  * Returns -EBUSY  or Success (0)
372  *
373  **/
374 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
375 {
376 	struct net_device *netdev = adapter->netdev;
377 
378 	if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
379 		return -EBUSY;
380 
381 	netif_device_detach(netdev);
382 	qlcnic_down(adapter, netdev);
383 	qlcnic_up(adapter, netdev);
384 	netif_device_attach(netdev);
385 	clear_bit(__QLCNIC_RESETTING, &adapter->state);
386 	netdev_info(adapter->netdev, "%s: soft reset complete.\n", __func__);
387 
388 	return 0;
389 }
390 
391 /**
392  * qlcnic_83xx_idc_detach_driver
393  *
394  * @adapter: adapter structure
395  * Detach net interface, stop TX and cleanup resources before the HW reset.
396  * Returns: None
397  *
398  **/
399 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
400 {
401 	int i;
402 	struct net_device *netdev = adapter->netdev;
403 
404 	netif_device_detach(netdev);
405 	qlcnic_83xx_detach_mailbox_work(adapter);
406 
407 	/* Disable mailbox interrupt */
408 	qlcnic_83xx_disable_mbx_intr(adapter);
409 	qlcnic_down(adapter, netdev);
410 	for (i = 0; i < adapter->ahw->num_msix; i++) {
411 		adapter->ahw->intr_tbl[i].id = i;
412 		adapter->ahw->intr_tbl[i].enabled = 0;
413 		adapter->ahw->intr_tbl[i].src = 0;
414 	}
415 
416 	if (qlcnic_sriov_pf_check(adapter))
417 		qlcnic_sriov_pf_reset(adapter);
418 }
419 
420 /**
421  * qlcnic_83xx_idc_attach_driver
422  *
423  * @adapter: adapter structure
424  *
425  * Re-attach and re-enable net interface
426  * Returns: None
427  *
428  **/
429 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
430 {
431 	struct net_device *netdev = adapter->netdev;
432 
433 	if (netif_running(netdev)) {
434 		if (qlcnic_up(adapter, netdev))
435 			goto done;
436 		qlcnic_restore_indev_addr(netdev, NETDEV_UP);
437 	}
438 done:
439 	netif_device_attach(netdev);
440 }
441 
442 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
443 					      int lock)
444 {
445 	if (lock) {
446 		if (qlcnic_83xx_lock_driver(adapter))
447 			return -EBUSY;
448 	}
449 
450 	qlcnic_83xx_idc_clear_registers(adapter, 0);
451 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
452 	if (lock)
453 		qlcnic_83xx_unlock_driver(adapter);
454 
455 	qlcnic_83xx_idc_log_state_history(adapter);
456 	dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
457 
458 	return 0;
459 }
460 
461 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
462 					    int lock)
463 {
464 	if (lock) {
465 		if (qlcnic_83xx_lock_driver(adapter))
466 			return -EBUSY;
467 	}
468 
469 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
470 
471 	if (lock)
472 		qlcnic_83xx_unlock_driver(adapter);
473 
474 	return 0;
475 }
476 
477 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
478 					      int lock)
479 {
480 	if (lock) {
481 		if (qlcnic_83xx_lock_driver(adapter))
482 			return -EBUSY;
483 	}
484 
485 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
486 	       QLC_83XX_IDC_DEV_NEED_QUISCENT);
487 
488 	if (lock)
489 		qlcnic_83xx_unlock_driver(adapter);
490 
491 	return 0;
492 }
493 
494 static int
495 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
496 {
497 	if (lock) {
498 		if (qlcnic_83xx_lock_driver(adapter))
499 			return -EBUSY;
500 	}
501 
502 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
503 	       QLC_83XX_IDC_DEV_NEED_RESET);
504 
505 	if (lock)
506 		qlcnic_83xx_unlock_driver(adapter);
507 
508 	return 0;
509 }
510 
511 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
512 					     int lock)
513 {
514 	if (lock) {
515 		if (qlcnic_83xx_lock_driver(adapter))
516 			return -EBUSY;
517 	}
518 
519 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
520 	if (lock)
521 		qlcnic_83xx_unlock_driver(adapter);
522 
523 	return 0;
524 }
525 
526 /**
527  * qlcnic_83xx_idc_find_reset_owner_id
528  *
529  * @adapter: adapter structure
530  *
531  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
532  * Within the same class, function with lowest PCI ID assumes ownership
533  *
534  * Returns: reset owner id or failure indication (-EIO)
535  *
536  **/
537 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
538 {
539 	u32 reg, reg1, reg2, i, j, owner, class;
540 
541 	reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
542 	reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
543 	owner = QLCNIC_TYPE_NIC;
544 	i = 0;
545 	j = 0;
546 	reg = reg1;
547 
548 	do {
549 		class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
550 		if (class == owner)
551 			break;
552 		if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
553 			reg = reg2;
554 			j = 0;
555 		} else {
556 			j++;
557 		}
558 
559 		if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
560 			if (owner == QLCNIC_TYPE_NIC)
561 				owner = QLCNIC_TYPE_ISCSI;
562 			else if (owner == QLCNIC_TYPE_ISCSI)
563 				owner = QLCNIC_TYPE_FCOE;
564 			else if (owner == QLCNIC_TYPE_FCOE)
565 				return -EIO;
566 			reg = reg1;
567 			j = 0;
568 			i = 0;
569 		}
570 	} while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
571 
572 	return i;
573 }
574 
575 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
576 {
577 	int ret = 0;
578 
579 	ret = qlcnic_83xx_restart_hw(adapter);
580 
581 	if (ret) {
582 		qlcnic_83xx_idc_enter_failed_state(adapter, lock);
583 	} else {
584 		qlcnic_83xx_idc_clear_registers(adapter, lock);
585 		ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
586 	}
587 
588 	return ret;
589 }
590 
591 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
592 {
593 	u32 status;
594 
595 	status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
596 
597 	if (status & QLCNIC_RCODE_FATAL_ERROR) {
598 		dev_err(&adapter->pdev->dev,
599 			"peg halt status1=0x%x\n", status);
600 		if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
601 			dev_err(&adapter->pdev->dev,
602 				"On board active cooling fan failed. "
603 				"Device has been halted.\n");
604 			dev_err(&adapter->pdev->dev,
605 				"Replace the adapter.\n");
606 			return -EIO;
607 		}
608 	}
609 
610 	return 0;
611 }
612 
613 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
614 {
615 	int err;
616 
617 	qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
618 	qlcnic_83xx_enable_mbx_interrupt(adapter);
619 
620 	qlcnic_83xx_initialize_nic(adapter, 1);
621 
622 	err = qlcnic_sriov_pf_reinit(adapter);
623 	if (err)
624 		return err;
625 
626 	qlcnic_83xx_enable_mbx_interrupt(adapter);
627 
628 	if (qlcnic_83xx_configure_opmode(adapter)) {
629 		qlcnic_83xx_idc_enter_failed_state(adapter, 1);
630 		return -EIO;
631 	}
632 
633 	if (adapter->nic_ops->init_driver(adapter)) {
634 		qlcnic_83xx_idc_enter_failed_state(adapter, 1);
635 		return -EIO;
636 	}
637 
638 	if (adapter->portnum == 0)
639 		qlcnic_set_drv_version(adapter);
640 
641 	qlcnic_dcb_get_info(adapter->dcb);
642 	qlcnic_83xx_idc_attach_driver(adapter);
643 
644 	return 0;
645 }
646 
647 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
648 {
649 	struct qlcnic_hardware_context *ahw = adapter->ahw;
650 
651 	qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
652 	qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
653 	set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
654 
655 	ahw->idc.quiesce_req = 0;
656 	ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
657 	ahw->idc.err_code = 0;
658 	ahw->idc.collect_dump = 0;
659 	ahw->reset_context = 0;
660 	adapter->tx_timeo_cnt = 0;
661 	ahw->idc.delay_reset = 0;
662 
663 	clear_bit(__QLCNIC_RESETTING, &adapter->state);
664 }
665 
666 /**
667  * qlcnic_83xx_idc_ready_state_entry
668  *
669  * @adapter: adapter structure
670  *
671  * Perform ready state initialization, this routine will get invoked only
672  * once from READY state.
673  *
674  * Returns: Error code or Success(0)
675  *
676  **/
677 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
678 {
679 	struct qlcnic_hardware_context *ahw = adapter->ahw;
680 
681 	if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
682 		qlcnic_83xx_idc_update_idc_params(adapter);
683 		/* Re-attach the device if required */
684 		if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
685 		    (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
686 			if (qlcnic_83xx_idc_reattach_driver(adapter))
687 				return -EIO;
688 		}
689 	}
690 
691 	return 0;
692 }
693 
694 /**
695  * qlcnic_83xx_idc_vnic_pf_entry
696  *
697  * @adapter: adapter structure
698  *
699  * Ensure vNIC mode privileged function starts only after vNIC mode is
700  * enabled by management function.
701  * If vNIC mode is ready, start initialization.
702  *
703  * Returns: -EIO or 0
704  *
705  **/
706 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
707 {
708 	u32 state;
709 	struct qlcnic_hardware_context *ahw = adapter->ahw;
710 
711 	/* Privileged function waits till mgmt function enables VNIC mode */
712 	state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
713 	if (state != QLCNIC_DEV_NPAR_OPER) {
714 		if (!ahw->idc.vnic_wait_limit--) {
715 			qlcnic_83xx_idc_enter_failed_state(adapter, 1);
716 			return -EIO;
717 		}
718 		dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
719 		return -EIO;
720 
721 	} else {
722 		/* Perform one time initialization from ready state */
723 		if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
724 			qlcnic_83xx_idc_update_idc_params(adapter);
725 
726 			/* If the previous state is UNKNOWN, device will be
727 			   already attached properly by Init routine*/
728 			if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
729 				if (qlcnic_83xx_idc_reattach_driver(adapter))
730 					return -EIO;
731 			}
732 			adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
733 			dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
734 		}
735 	}
736 
737 	return 0;
738 }
739 
740 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
741 {
742 	adapter->ahw->idc.err_code = -EIO;
743 	dev_err(&adapter->pdev->dev,
744 		"%s: Device in unknown state\n", __func__);
745 	clear_bit(__QLCNIC_RESETTING, &adapter->state);
746 	return 0;
747 }
748 
749 /**
750  * qlcnic_83xx_idc_cold_state
751  *
752  * @adapter: adapter structure
753  *
754  * If HW is up and running device will enter READY state.
755  * If firmware image from host needs to be loaded, device is
756  * forced to start with the file firmware image.
757  *
758  * Returns: Error code or Success(0)
759  *
760  **/
761 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
762 {
763 	qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
764 	qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
765 
766 	if (qlcnic_load_fw_file) {
767 		qlcnic_83xx_idc_restart_hw(adapter, 0);
768 	} else {
769 		if (qlcnic_83xx_check_hw_status(adapter)) {
770 			qlcnic_83xx_idc_enter_failed_state(adapter, 0);
771 			return -EIO;
772 		} else {
773 			qlcnic_83xx_idc_enter_ready_state(adapter, 0);
774 		}
775 	}
776 	return 0;
777 }
778 
779 /**
780  * qlcnic_83xx_idc_init_state
781  *
782  * @adapter: adapter structure
783  *
784  * Reset owner will restart the device from this state.
785  * Device will enter failed state if it remains
786  * in this state for more than DEV_INIT time limit.
787  *
788  * Returns: Error code or Success(0)
789  *
790  **/
791 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
792 {
793 	int timeout, ret = 0;
794 	u32 owner;
795 
796 	timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
797 	if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
798 		owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
799 		if (adapter->ahw->pci_func == owner)
800 			ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
801 	} else {
802 		ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
803 	}
804 
805 	return ret;
806 }
807 
808 /**
809  * qlcnic_83xx_idc_ready_state
810  *
811  * @adapter: adapter structure
812  *
813  * Perform IDC protocol specicifed actions after monitoring device state and
814  * events.
815  *
816  * Returns: Error code or Success(0)
817  *
818  **/
819 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
820 {
821 	struct qlcnic_hardware_context *ahw = adapter->ahw;
822 	struct qlcnic_mailbox *mbx = ahw->mailbox;
823 	int ret = 0;
824 	u32 val;
825 
826 	/* Perform NIC configuration based ready state entry actions */
827 	if (ahw->idc.state_entry(adapter))
828 		return -EIO;
829 
830 	if (qlcnic_check_temp(adapter)) {
831 		if (ahw->temp == QLCNIC_TEMP_PANIC) {
832 			qlcnic_83xx_idc_check_fan_failure(adapter);
833 			dev_err(&adapter->pdev->dev,
834 				"Error: device temperature %d above limits\n",
835 				adapter->ahw->temp);
836 			clear_bit(QLC_83XX_MBX_READY, &mbx->status);
837 			set_bit(__QLCNIC_RESETTING, &adapter->state);
838 			qlcnic_83xx_idc_detach_driver(adapter);
839 			qlcnic_83xx_idc_enter_failed_state(adapter, 1);
840 			return -EIO;
841 		}
842 	}
843 
844 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
845 	ret = qlcnic_83xx_check_heartbeat(adapter);
846 	if (ret) {
847 		adapter->flags |= QLCNIC_FW_HANG;
848 		if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
849 			clear_bit(QLC_83XX_MBX_READY, &mbx->status);
850 			set_bit(__QLCNIC_RESETTING, &adapter->state);
851 			qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
852 		}  else {
853 			netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
854 				    __func__);
855 			qlcnic_83xx_idc_enter_failed_state(adapter, 1);
856 		}
857 		return -EIO;
858 	}
859 
860 	if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
861 		clear_bit(QLC_83XX_MBX_READY, &mbx->status);
862 
863 		/* Move to need reset state and prepare for reset */
864 		qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
865 		return ret;
866 	}
867 
868 	/* Check for soft reset request */
869 	if (ahw->reset_context &&
870 	    !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
871 		adapter->ahw->reset_context = 0;
872 		qlcnic_83xx_idc_tx_soft_reset(adapter);
873 		return ret;
874 	}
875 
876 	/* Move to need quiesce state if requested */
877 	if (adapter->ahw->idc.quiesce_req) {
878 		qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
879 		qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
880 		return ret;
881 	}
882 
883 	return ret;
884 }
885 
886 /**
887  * qlcnic_83xx_idc_need_reset_state
888  *
889  * @adapter: adapter structure
890  *
891  * Device will remain in this state until:
892  *	Reset request ACK's are received from all the functions
893  *	Wait time exceeds max time limit
894  *
895  * Returns: Error code or Success(0)
896  *
897  **/
898 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
899 {
900 	struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
901 	int ret = 0;
902 
903 	if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
904 		qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
905 		set_bit(__QLCNIC_RESETTING, &adapter->state);
906 		clear_bit(QLC_83XX_MBX_READY, &mbx->status);
907 		if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE)
908 			qlcnic_83xx_disable_vnic_mode(adapter, 1);
909 
910 		if (qlcnic_check_diag_status(adapter)) {
911 			dev_info(&adapter->pdev->dev,
912 				 "%s: Wait for diag completion\n", __func__);
913 			adapter->ahw->idc.delay_reset = 1;
914 			return 0;
915 		} else {
916 			qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
917 			qlcnic_83xx_idc_detach_driver(adapter);
918 		}
919 	}
920 
921 	if (qlcnic_check_diag_status(adapter)) {
922 		dev_info(&adapter->pdev->dev,
923 			 "%s: Wait for diag completion\n", __func__);
924 		return  -1;
925 	} else {
926 		if (adapter->ahw->idc.delay_reset) {
927 			qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
928 			qlcnic_83xx_idc_detach_driver(adapter);
929 			adapter->ahw->idc.delay_reset = 0;
930 		}
931 
932 		/* Check for ACK from other functions */
933 		ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
934 		if (ret) {
935 			dev_info(&adapter->pdev->dev,
936 				 "%s: Waiting for reset ACK\n", __func__);
937 			return -1;
938 		}
939 	}
940 
941 	/* Transit to INIT state and restart the HW */
942 	qlcnic_83xx_idc_enter_init_state(adapter, 1);
943 
944 	return ret;
945 }
946 
947 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
948 {
949 	dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
950 	return 0;
951 }
952 
953 static void qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
954 {
955 	struct qlcnic_hardware_context *ahw = adapter->ahw;
956 	u32 val, owner;
957 
958 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
959 	if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
960 		owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
961 		if (ahw->pci_func == owner) {
962 			qlcnic_83xx_stop_hw(adapter);
963 			qlcnic_dump_fw(adapter);
964 		}
965 	}
966 
967 	netdev_warn(adapter->netdev, "%s: Reboot will be required to recover the adapter!!\n",
968 		    __func__);
969 	clear_bit(__QLCNIC_RESETTING, &adapter->state);
970 	ahw->idc.err_code = -EIO;
971 
972 	return;
973 }
974 
975 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
976 {
977 	dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
978 	return 0;
979 }
980 
981 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
982 						u32 state)
983 {
984 	u32 cur, prev, next;
985 
986 	cur = adapter->ahw->idc.curr_state;
987 	prev = adapter->ahw->idc.prev_state;
988 	next = state;
989 
990 	if ((next < QLC_83XX_IDC_DEV_COLD) ||
991 	    (next > QLC_83XX_IDC_DEV_QUISCENT)) {
992 		dev_err(&adapter->pdev->dev,
993 			"%s: curr %d, prev %d, next state %d is  invalid\n",
994 			__func__, cur, prev, state);
995 		return 1;
996 	}
997 
998 	if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
999 	    (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
1000 		if ((next != QLC_83XX_IDC_DEV_COLD) &&
1001 		    (next != QLC_83XX_IDC_DEV_READY)) {
1002 			dev_err(&adapter->pdev->dev,
1003 				"%s: failed, cur %d prev %d next %d\n",
1004 				__func__, cur, prev, next);
1005 			return 1;
1006 		}
1007 	}
1008 
1009 	if (next == QLC_83XX_IDC_DEV_INIT) {
1010 		if ((prev != QLC_83XX_IDC_DEV_INIT) &&
1011 		    (prev != QLC_83XX_IDC_DEV_COLD) &&
1012 		    (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
1013 			dev_err(&adapter->pdev->dev,
1014 				"%s: failed, cur %d prev %d next %d\n",
1015 				__func__, cur, prev, next);
1016 			return 1;
1017 		}
1018 	}
1019 
1020 	return 0;
1021 }
1022 
1023 #define QLC_83XX_ENCAP_TYPE_VXLAN	BIT_1
1024 #define QLC_83XX_MATCH_ENCAP_ID		BIT_2
1025 #define QLC_83XX_SET_VXLAN_UDP_DPORT	BIT_3
1026 #define QLC_83XX_VXLAN_UDP_DPORT(PORT)	((PORT & 0xffff) << 16)
1027 
1028 #define QLCNIC_ENABLE_INGRESS_ENCAP_PARSING 1
1029 #define QLCNIC_DISABLE_INGRESS_ENCAP_PARSING 0
1030 
1031 static int qlcnic_set_vxlan_port(struct qlcnic_adapter *adapter)
1032 {
1033 	u16 port = adapter->ahw->vxlan_port;
1034 	struct qlcnic_cmd_args cmd;
1035 	int ret = 0;
1036 
1037 	memset(&cmd, 0, sizeof(cmd));
1038 
1039 	ret = qlcnic_alloc_mbx_args(&cmd, adapter,
1040 				    QLCNIC_CMD_INIT_NIC_FUNC);
1041 	if (ret)
1042 		return ret;
1043 
1044 	cmd.req.arg[1] = QLC_83XX_MULTI_TENANCY_INFO;
1045 	cmd.req.arg[2] = QLC_83XX_ENCAP_TYPE_VXLAN |
1046 			 QLC_83XX_SET_VXLAN_UDP_DPORT |
1047 			 QLC_83XX_VXLAN_UDP_DPORT(port);
1048 
1049 	ret = qlcnic_issue_cmd(adapter, &cmd);
1050 	if (ret)
1051 		netdev_err(adapter->netdev,
1052 			   "Failed to set VXLAN port %d in adapter\n",
1053 			   port);
1054 
1055 	qlcnic_free_mbx_args(&cmd);
1056 
1057 	return ret;
1058 }
1059 
1060 static int qlcnic_set_vxlan_parsing(struct qlcnic_adapter *adapter,
1061 				    bool state)
1062 {
1063 	u16 vxlan_port = adapter->ahw->vxlan_port;
1064 	struct qlcnic_cmd_args cmd;
1065 	int ret = 0;
1066 
1067 	memset(&cmd, 0, sizeof(cmd));
1068 
1069 	ret = qlcnic_alloc_mbx_args(&cmd, adapter,
1070 				    QLCNIC_CMD_SET_INGRESS_ENCAP);
1071 	if (ret)
1072 		return ret;
1073 
1074 	cmd.req.arg[1] = state ? QLCNIC_ENABLE_INGRESS_ENCAP_PARSING :
1075 				 QLCNIC_DISABLE_INGRESS_ENCAP_PARSING;
1076 
1077 	ret = qlcnic_issue_cmd(adapter, &cmd);
1078 	if (ret)
1079 		netdev_err(adapter->netdev,
1080 			   "Failed to %s VXLAN parsing for port %d\n",
1081 			   state ? "enable" : "disable", vxlan_port);
1082 	else
1083 		netdev_info(adapter->netdev,
1084 			    "%s VXLAN parsing for port %d\n",
1085 			    state ? "Enabled" : "Disabled", vxlan_port);
1086 
1087 	qlcnic_free_mbx_args(&cmd);
1088 
1089 	return ret;
1090 }
1091 
1092 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1093 {
1094 	if (adapter->fhash.fnum)
1095 		qlcnic_prune_lb_filters(adapter);
1096 
1097 	if (adapter->flags & QLCNIC_ADD_VXLAN_PORT) {
1098 		if (qlcnic_set_vxlan_port(adapter))
1099 			return;
1100 
1101 		if (qlcnic_set_vxlan_parsing(adapter, true))
1102 			return;
1103 
1104 		adapter->flags &= ~QLCNIC_ADD_VXLAN_PORT;
1105 	} else if (adapter->flags & QLCNIC_DEL_VXLAN_PORT) {
1106 		if (qlcnic_set_vxlan_parsing(adapter, false))
1107 			return;
1108 
1109 		adapter->ahw->vxlan_port = 0;
1110 		adapter->flags &= ~QLCNIC_DEL_VXLAN_PORT;
1111 	}
1112 }
1113 
1114 /**
1115  * qlcnic_83xx_idc_poll_dev_state
1116  *
1117  * @work: kernel work queue structure used to schedule the function
1118  *
1119  * Poll device state periodically and perform state specific
1120  * actions defined by Inter Driver Communication (IDC) protocol.
1121  *
1122  * Returns: None
1123  *
1124  **/
1125 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1126 {
1127 	struct qlcnic_adapter *adapter;
1128 	u32 state;
1129 
1130 	adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1131 	state =	QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1132 
1133 	if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1134 		qlcnic_83xx_idc_log_state_history(adapter);
1135 		adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1136 	} else {
1137 		adapter->ahw->idc.curr_state = state;
1138 	}
1139 
1140 	switch (adapter->ahw->idc.curr_state) {
1141 	case QLC_83XX_IDC_DEV_READY:
1142 		qlcnic_83xx_idc_ready_state(adapter);
1143 		break;
1144 	case QLC_83XX_IDC_DEV_NEED_RESET:
1145 		qlcnic_83xx_idc_need_reset_state(adapter);
1146 		break;
1147 	case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1148 		qlcnic_83xx_idc_need_quiesce_state(adapter);
1149 		break;
1150 	case QLC_83XX_IDC_DEV_FAILED:
1151 		qlcnic_83xx_idc_failed_state(adapter);
1152 		return;
1153 	case QLC_83XX_IDC_DEV_INIT:
1154 		qlcnic_83xx_idc_init_state(adapter);
1155 		break;
1156 	case QLC_83XX_IDC_DEV_QUISCENT:
1157 		qlcnic_83xx_idc_quiesce_state(adapter);
1158 		break;
1159 	default:
1160 		qlcnic_83xx_idc_unknown_state(adapter);
1161 		return;
1162 	}
1163 	adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1164 	qlcnic_83xx_periodic_tasks(adapter);
1165 
1166 	/* Re-schedule the function */
1167 	if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1168 		qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1169 				     adapter->ahw->idc.delay);
1170 }
1171 
1172 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1173 {
1174 	u32 idc_params, val;
1175 
1176 	if (qlcnic_83xx_flash_read32(adapter, QLC_83XX_IDC_FLASH_PARAM_ADDR,
1177 				     (u8 *)&idc_params, 1)) {
1178 		dev_info(&adapter->pdev->dev,
1179 			 "%s:failed to get IDC params from flash\n", __func__);
1180 		adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1181 		adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1182 	} else {
1183 		adapter->dev_init_timeo = idc_params & 0xFFFF;
1184 		adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1185 	}
1186 
1187 	adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1188 	adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1189 	adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1190 	adapter->ahw->idc.err_code = 0;
1191 	adapter->ahw->idc.collect_dump = 0;
1192 	adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1193 
1194 	clear_bit(__QLCNIC_RESETTING, &adapter->state);
1195 	set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1196 
1197 	/* Check if reset recovery is disabled */
1198 	if (!qlcnic_auto_fw_reset) {
1199 		/* Propagate do not reset request to other functions */
1200 		val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1201 		val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1202 		QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1203 	}
1204 }
1205 
1206 static int
1207 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1208 {
1209 	u32 state, val;
1210 
1211 	if (qlcnic_83xx_lock_driver(adapter))
1212 		return -EIO;
1213 
1214 	/* Clear driver lock register */
1215 	QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1216 	if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1217 		qlcnic_83xx_unlock_driver(adapter);
1218 		return -EIO;
1219 	}
1220 
1221 	state =	QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1222 	if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1223 		qlcnic_83xx_unlock_driver(adapter);
1224 		return -EIO;
1225 	}
1226 
1227 	if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1228 		QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1229 		       QLC_83XX_IDC_DEV_COLD);
1230 		state = QLC_83XX_IDC_DEV_COLD;
1231 	}
1232 
1233 	adapter->ahw->idc.curr_state = state;
1234 	/* First to load function should cold boot the device */
1235 	if (state == QLC_83XX_IDC_DEV_COLD)
1236 		qlcnic_83xx_idc_cold_state_handler(adapter);
1237 
1238 	/* Check if reset recovery is enabled */
1239 	if (qlcnic_auto_fw_reset) {
1240 		val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1241 		val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1242 		QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1243 	}
1244 
1245 	qlcnic_83xx_unlock_driver(adapter);
1246 
1247 	return 0;
1248 }
1249 
1250 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1251 {
1252 	int ret = -EIO;
1253 
1254 	qlcnic_83xx_setup_idc_parameters(adapter);
1255 
1256 	if (qlcnic_83xx_get_reset_instruction_template(adapter))
1257 		return ret;
1258 
1259 	if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1260 		if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1261 			return -EIO;
1262 	} else {
1263 		if (qlcnic_83xx_idc_check_major_version(adapter))
1264 			return -EIO;
1265 	}
1266 
1267 	qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1268 
1269 	return 0;
1270 }
1271 
1272 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1273 {
1274 	int id;
1275 	u32 val;
1276 
1277 	while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1278 		usleep_range(10000, 11000);
1279 
1280 	id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1281 	id = id & 0xFF;
1282 
1283 	if (id == adapter->portnum) {
1284 		dev_err(&adapter->pdev->dev,
1285 			"%s: wait for lock recovery.. %d\n", __func__, id);
1286 		msleep(20);
1287 		id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1288 		id = id & 0xFF;
1289 	}
1290 
1291 	/* Clear driver presence bit */
1292 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1293 	val = val & ~(1 << adapter->portnum);
1294 	QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1295 	clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1296 	clear_bit(__QLCNIC_RESETTING, &adapter->state);
1297 
1298 	cancel_delayed_work_sync(&adapter->fw_work);
1299 }
1300 
1301 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1302 {
1303 	u32 val;
1304 
1305 	if (qlcnic_sriov_vf_check(adapter))
1306 		return;
1307 
1308 	if (qlcnic_83xx_lock_driver(adapter)) {
1309 		dev_err(&adapter->pdev->dev,
1310 			"%s:failed, please retry\n", __func__);
1311 		return;
1312 	}
1313 
1314 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1315 	if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
1316 		netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
1317 			    __func__);
1318 		qlcnic_83xx_idc_enter_failed_state(adapter, 0);
1319 		qlcnic_83xx_unlock_driver(adapter);
1320 		return;
1321 	}
1322 
1323 	if (key == QLCNIC_FORCE_FW_RESET) {
1324 		val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1325 		val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1326 		QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1327 	} else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1328 		adapter->ahw->idc.collect_dump = 1;
1329 	}
1330 
1331 	qlcnic_83xx_unlock_driver(adapter);
1332 	return;
1333 }
1334 
1335 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1336 {
1337 	u8 *p_cache;
1338 	u32 src, size;
1339 	u64 dest;
1340 	int ret = -EIO;
1341 
1342 	src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1343 	dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1344 	size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1345 
1346 	/* alignment check */
1347 	if (size & 0xF)
1348 		size = (size + 16) & ~0xF;
1349 
1350 	p_cache = vzalloc(size);
1351 	if (p_cache == NULL)
1352 		return -ENOMEM;
1353 
1354 	ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1355 						size / sizeof(u32));
1356 	if (ret) {
1357 		vfree(p_cache);
1358 		return ret;
1359 	}
1360 	/* 16 byte write to MS memory */
1361 	ret = qlcnic_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1362 				     size / 16);
1363 	if (ret) {
1364 		vfree(p_cache);
1365 		return ret;
1366 	}
1367 	vfree(p_cache);
1368 
1369 	return ret;
1370 }
1371 
1372 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1373 {
1374 	struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
1375 	const struct firmware *fw = fw_info->fw;
1376 	u32 dest, *p_cache, *temp;
1377 	int i, ret = -EIO;
1378 	__le32 *temp_le;
1379 	u8 data[16];
1380 	size_t size;
1381 	u64 addr;
1382 
1383 	temp = vzalloc(fw->size);
1384 	if (!temp) {
1385 		release_firmware(fw);
1386 		fw_info->fw = NULL;
1387 		return -ENOMEM;
1388 	}
1389 
1390 	temp_le = (__le32 *)fw->data;
1391 
1392 	/* FW image in file is in little endian, swap the data to nullify
1393 	 * the effect of writel() operation on big endian platform.
1394 	 */
1395 	for (i = 0; i < fw->size / sizeof(u32); i++)
1396 		temp[i] = __le32_to_cpu(temp_le[i]);
1397 
1398 	dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1399 	size = (fw->size & ~0xF);
1400 	p_cache = temp;
1401 	addr = (u64)dest;
1402 
1403 	ret = qlcnic_ms_mem_write128(adapter, addr,
1404 				     p_cache, size / 16);
1405 	if (ret) {
1406 		dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1407 		goto exit;
1408 	}
1409 
1410 	/* alignment check */
1411 	if (fw->size & 0xF) {
1412 		addr = dest + size;
1413 		for (i = 0; i < (fw->size & 0xF); i++)
1414 			data[i] = ((u8 *)temp)[size + i];
1415 		for (; i < 16; i++)
1416 			data[i] = 0;
1417 		ret = qlcnic_ms_mem_write128(adapter, addr,
1418 					     (u32 *)data, 1);
1419 		if (ret) {
1420 			dev_err(&adapter->pdev->dev,
1421 				"MS memory write failed\n");
1422 			goto exit;
1423 		}
1424 	}
1425 
1426 exit:
1427 	release_firmware(fw);
1428 	fw_info->fw = NULL;
1429 	vfree(temp);
1430 
1431 	return ret;
1432 }
1433 
1434 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1435 {
1436 	int i, j;
1437 	u32 val = 0, val1 = 0, reg = 0;
1438 	int err = 0;
1439 
1440 	val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1441 	if (err == -EIO)
1442 		return;
1443 	dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1444 
1445 	for (j = 0; j < 2; j++) {
1446 		if (j == 0) {
1447 			dev_info(&adapter->pdev->dev,
1448 				 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1449 			reg = QLC_83XX_PORT0_THRESHOLD;
1450 		} else if (j == 1) {
1451 			dev_info(&adapter->pdev->dev,
1452 				 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1453 			reg = QLC_83XX_PORT1_THRESHOLD;
1454 		}
1455 		for (i = 0; i < 8; i++) {
1456 			val = QLCRD32(adapter, reg + (i * 0x4), &err);
1457 			if (err == -EIO)
1458 				return;
1459 			dev_info(&adapter->pdev->dev, "0x%x  ", val);
1460 		}
1461 		dev_info(&adapter->pdev->dev, "\n");
1462 	}
1463 
1464 	for (j = 0; j < 2; j++) {
1465 		if (j == 0) {
1466 			dev_info(&adapter->pdev->dev,
1467 				 "Port 0 RxB TC Max Cell Registers[4..1]:");
1468 			reg = QLC_83XX_PORT0_TC_MC_REG;
1469 		} else if (j == 1) {
1470 			dev_info(&adapter->pdev->dev,
1471 				 "Port 1 RxB TC Max Cell Registers[4..1]:");
1472 			reg = QLC_83XX_PORT1_TC_MC_REG;
1473 		}
1474 		for (i = 0; i < 4; i++) {
1475 			val = QLCRD32(adapter, reg + (i * 0x4), &err);
1476 			if (err == -EIO)
1477 				return;
1478 			dev_info(&adapter->pdev->dev, "0x%x  ", val);
1479 		}
1480 		dev_info(&adapter->pdev->dev, "\n");
1481 	}
1482 
1483 	for (j = 0; j < 2; j++) {
1484 		if (j == 0) {
1485 			dev_info(&adapter->pdev->dev,
1486 				 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1487 			reg = QLC_83XX_PORT0_TC_STATS;
1488 		} else if (j == 1) {
1489 			dev_info(&adapter->pdev->dev,
1490 				 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1491 			reg = QLC_83XX_PORT1_TC_STATS;
1492 		}
1493 		for (i = 7; i >= 0; i--) {
1494 			val = QLCRD32(adapter, reg, &err);
1495 			if (err == -EIO)
1496 				return;
1497 			val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1498 			QLCWR32(adapter, reg, (val | (i << 29)));
1499 			val = QLCRD32(adapter, reg, &err);
1500 			if (err == -EIO)
1501 				return;
1502 			dev_info(&adapter->pdev->dev, "0x%x  ", val);
1503 		}
1504 		dev_info(&adapter->pdev->dev, "\n");
1505 	}
1506 
1507 	val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1508 	if (err == -EIO)
1509 		return;
1510 	val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1511 	if (err == -EIO)
1512 		return;
1513 	dev_info(&adapter->pdev->dev,
1514 		 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1515 		 val, val1);
1516 }
1517 
1518 
1519 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1520 {
1521 	u32 reg = 0, i, j;
1522 
1523 	if (qlcnic_83xx_lock_driver(adapter)) {
1524 		dev_err(&adapter->pdev->dev,
1525 			"%s:failed to acquire driver lock\n", __func__);
1526 		return;
1527 	}
1528 
1529 	qlcnic_83xx_dump_pause_control_regs(adapter);
1530 	QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1531 
1532 	for (j = 0; j < 2; j++) {
1533 		if (j == 0)
1534 			reg = QLC_83XX_PORT0_THRESHOLD;
1535 		else if (j == 1)
1536 			reg = QLC_83XX_PORT1_THRESHOLD;
1537 
1538 		for (i = 0; i < 8; i++)
1539 			QLCWR32(adapter, reg + (i * 0x4), 0x0);
1540 	}
1541 
1542 	for (j = 0; j < 2; j++) {
1543 		if (j == 0)
1544 			reg = QLC_83XX_PORT0_TC_MC_REG;
1545 		else if (j == 1)
1546 			reg = QLC_83XX_PORT1_TC_MC_REG;
1547 
1548 		for (i = 0; i < 4; i++)
1549 			QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1550 	}
1551 
1552 	QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1553 	QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1554 	dev_info(&adapter->pdev->dev,
1555 		 "Disabled pause frames successfully on all ports\n");
1556 	qlcnic_83xx_unlock_driver(adapter);
1557 }
1558 
1559 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1560 {
1561 	QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1562 	QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1563 	QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1564 	QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1565 	QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1566 	QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1567 	QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1568 	QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1569 	QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1570 }
1571 
1572 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1573 {
1574 	u32 heartbeat, peg_status;
1575 	int retries, ret = -EIO, err = 0;
1576 
1577 	retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1578 	p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1579 					       QLCNIC_PEG_ALIVE_COUNTER);
1580 
1581 	do {
1582 		msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1583 		heartbeat = QLC_SHARED_REG_RD32(p_dev,
1584 						QLCNIC_PEG_ALIVE_COUNTER);
1585 		if (heartbeat != p_dev->heartbeat) {
1586 			ret = QLCNIC_RCODE_SUCCESS;
1587 			break;
1588 		}
1589 	} while (--retries);
1590 
1591 	if (ret) {
1592 		dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1593 		qlcnic_83xx_take_eport_out_of_reset(p_dev);
1594 		qlcnic_83xx_disable_pause_frames(p_dev);
1595 		peg_status = QLC_SHARED_REG_RD32(p_dev,
1596 						 QLCNIC_PEG_HALT_STATUS1);
1597 		dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1598 			 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1599 			 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1600 			 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1601 			 "PEG_NET_4_PC: 0x%x\n", peg_status,
1602 			 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1603 			 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1604 			 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1605 			 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1606 			 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1607 			 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
1608 
1609 		if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1610 			dev_err(&p_dev->pdev->dev,
1611 				"Device is being reset err code 0x00006700.\n");
1612 	}
1613 
1614 	return ret;
1615 }
1616 
1617 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1618 {
1619 	int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1620 	u32 val;
1621 
1622 	do {
1623 		val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1624 		if (val == QLC_83XX_CMDPEG_COMPLETE)
1625 			return 0;
1626 		msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1627 	} while (--retries);
1628 
1629 	dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1630 	return -EIO;
1631 }
1632 
1633 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1634 {
1635 	int err;
1636 
1637 	err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1638 	if (err)
1639 		return err;
1640 
1641 	err = qlcnic_83xx_check_heartbeat(p_dev);
1642 	if (err)
1643 		return err;
1644 
1645 	return err;
1646 }
1647 
1648 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1649 				int duration, u32 mask, u32 status)
1650 {
1651 	int timeout_error, err = 0;
1652 	u32 value;
1653 	u8 retries;
1654 
1655 	value = QLCRD32(p_dev, addr, &err);
1656 	if (err == -EIO)
1657 		return err;
1658 	retries = duration / 10;
1659 
1660 	do {
1661 		if ((value & mask) != status) {
1662 			timeout_error = 1;
1663 			msleep(duration / 10);
1664 			value = QLCRD32(p_dev, addr, &err);
1665 			if (err == -EIO)
1666 				return err;
1667 		} else {
1668 			timeout_error = 0;
1669 			break;
1670 		}
1671 	} while (retries--);
1672 
1673 	if (timeout_error) {
1674 		p_dev->ahw->reset.seq_error++;
1675 		dev_err(&p_dev->pdev->dev,
1676 			"%s: Timeout Err, entry_num = %d\n",
1677 			__func__, p_dev->ahw->reset.seq_index);
1678 		dev_err(&p_dev->pdev->dev,
1679 			"0x%08x 0x%08x 0x%08x\n",
1680 			value, mask, status);
1681 	}
1682 
1683 	return timeout_error;
1684 }
1685 
1686 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1687 {
1688 	u32 sum = 0;
1689 	u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1690 	int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1691 
1692 	while (count-- > 0)
1693 		sum += *buff++;
1694 
1695 	while (sum >> 16)
1696 		sum = (sum & 0xFFFF) + (sum >> 16);
1697 
1698 	if (~sum) {
1699 		return 0;
1700 	} else {
1701 		dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1702 		return -1;
1703 	}
1704 }
1705 
1706 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1707 {
1708 	struct qlcnic_hardware_context *ahw = p_dev->ahw;
1709 	u32 addr, count, prev_ver, curr_ver;
1710 	u8 *p_buff;
1711 
1712 	if (ahw->reset.buff != NULL) {
1713 		prev_ver = p_dev->fw_version;
1714 		curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1715 		if (curr_ver > prev_ver)
1716 			kfree(ahw->reset.buff);
1717 		else
1718 			return 0;
1719 	}
1720 
1721 	ahw->reset.seq_error = 0;
1722 	ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1723 	if (p_dev->ahw->reset.buff == NULL)
1724 		return -ENOMEM;
1725 
1726 	p_buff = p_dev->ahw->reset.buff;
1727 	addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1728 	count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1729 
1730 	/* Copy template header from flash */
1731 	if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1732 		dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1733 		return -EIO;
1734 	}
1735 	ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1736 	addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1737 	p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1738 	count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1739 
1740 	/* Copy rest of the template */
1741 	if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1742 		dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1743 		return -EIO;
1744 	}
1745 
1746 	if (qlcnic_83xx_reset_template_checksum(p_dev))
1747 		return -EIO;
1748 	/* Get Stop, Start and Init command offsets */
1749 	ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1750 	ahw->reset.start_offset = ahw->reset.buff +
1751 				  ahw->reset.hdr->start_offset;
1752 	ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1753 	return 0;
1754 }
1755 
1756 /* Read Write HW register command */
1757 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1758 					   u32 raddr, u32 waddr)
1759 {
1760 	int err = 0;
1761 	u32 value;
1762 
1763 	value = QLCRD32(p_dev, raddr, &err);
1764 	if (err == -EIO)
1765 		return;
1766 	qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1767 }
1768 
1769 /* Read Modify Write HW register command */
1770 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1771 				    u32 raddr, u32 waddr,
1772 				    struct qlc_83xx_rmw *p_rmw_hdr)
1773 {
1774 	int err = 0;
1775 	u32 value;
1776 
1777 	if (p_rmw_hdr->index_a) {
1778 		value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1779 	} else {
1780 		value = QLCRD32(p_dev, raddr, &err);
1781 		if (err == -EIO)
1782 			return;
1783 	}
1784 
1785 	value &= p_rmw_hdr->mask;
1786 	value <<= p_rmw_hdr->shl;
1787 	value >>= p_rmw_hdr->shr;
1788 	value |= p_rmw_hdr->or_value;
1789 	value ^= p_rmw_hdr->xor_value;
1790 	qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1791 }
1792 
1793 /* Write HW register command */
1794 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1795 				   struct qlc_83xx_entry_hdr *p_hdr)
1796 {
1797 	int i;
1798 	struct qlc_83xx_entry *entry;
1799 
1800 	entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1801 					  sizeof(struct qlc_83xx_entry_hdr));
1802 
1803 	for (i = 0; i < p_hdr->count; i++, entry++) {
1804 		qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1805 					     entry->arg2);
1806 		if (p_hdr->delay)
1807 			udelay((u32)(p_hdr->delay));
1808 	}
1809 }
1810 
1811 /* Read and Write instruction */
1812 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1813 					struct qlc_83xx_entry_hdr *p_hdr)
1814 {
1815 	int i;
1816 	struct qlc_83xx_entry *entry;
1817 
1818 	entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1819 					  sizeof(struct qlc_83xx_entry_hdr));
1820 
1821 	for (i = 0; i < p_hdr->count; i++, entry++) {
1822 		qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1823 					       entry->arg2);
1824 		if (p_hdr->delay)
1825 			udelay((u32)(p_hdr->delay));
1826 	}
1827 }
1828 
1829 /* Poll HW register command */
1830 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1831 				  struct qlc_83xx_entry_hdr *p_hdr)
1832 {
1833 	long delay;
1834 	struct qlc_83xx_entry *entry;
1835 	struct qlc_83xx_poll *poll;
1836 	int i, err = 0;
1837 	unsigned long arg1, arg2;
1838 
1839 	poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1840 					sizeof(struct qlc_83xx_entry_hdr));
1841 
1842 	entry = (struct qlc_83xx_entry *)((char *)poll +
1843 					  sizeof(struct qlc_83xx_poll));
1844 	delay = (long)p_hdr->delay;
1845 
1846 	if (!delay) {
1847 		for (i = 0; i < p_hdr->count; i++, entry++)
1848 			qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1849 					     delay, poll->mask,
1850 					     poll->status);
1851 	} else {
1852 		for (i = 0; i < p_hdr->count; i++, entry++) {
1853 			arg1 = entry->arg1;
1854 			arg2 = entry->arg2;
1855 			if (delay) {
1856 				if (qlcnic_83xx_poll_reg(p_dev,
1857 							 arg1, delay,
1858 							 poll->mask,
1859 							 poll->status)){
1860 					QLCRD32(p_dev, arg1, &err);
1861 					if (err == -EIO)
1862 						return;
1863 					QLCRD32(p_dev, arg2, &err);
1864 					if (err == -EIO)
1865 						return;
1866 				}
1867 			}
1868 		}
1869 	}
1870 }
1871 
1872 /* Poll and write HW register command */
1873 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1874 					struct qlc_83xx_entry_hdr *p_hdr)
1875 {
1876 	int i;
1877 	long delay;
1878 	struct qlc_83xx_quad_entry *entry;
1879 	struct qlc_83xx_poll *poll;
1880 
1881 	poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1882 					sizeof(struct qlc_83xx_entry_hdr));
1883 	entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1884 					       sizeof(struct qlc_83xx_poll));
1885 	delay = (long)p_hdr->delay;
1886 
1887 	for (i = 0; i < p_hdr->count; i++, entry++) {
1888 		qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1889 					     entry->dr_value);
1890 		qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1891 					     entry->ar_value);
1892 		if (delay)
1893 			qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1894 					     poll->mask, poll->status);
1895 	}
1896 }
1897 
1898 /* Read Modify Write register command */
1899 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1900 					  struct qlc_83xx_entry_hdr *p_hdr)
1901 {
1902 	int i;
1903 	struct qlc_83xx_entry *entry;
1904 	struct qlc_83xx_rmw *rmw_hdr;
1905 
1906 	rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1907 					  sizeof(struct qlc_83xx_entry_hdr));
1908 
1909 	entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1910 					  sizeof(struct qlc_83xx_rmw));
1911 
1912 	for (i = 0; i < p_hdr->count; i++, entry++) {
1913 		qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1914 					entry->arg2, rmw_hdr);
1915 		if (p_hdr->delay)
1916 			udelay((u32)(p_hdr->delay));
1917 	}
1918 }
1919 
1920 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1921 {
1922 	if (p_hdr->delay)
1923 		mdelay((u32)((long)p_hdr->delay));
1924 }
1925 
1926 /* Read and poll register command */
1927 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1928 				       struct qlc_83xx_entry_hdr *p_hdr)
1929 {
1930 	long delay;
1931 	int index, i, j, err;
1932 	struct qlc_83xx_quad_entry *entry;
1933 	struct qlc_83xx_poll *poll;
1934 	unsigned long addr;
1935 
1936 	poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1937 					sizeof(struct qlc_83xx_entry_hdr));
1938 
1939 	entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1940 					       sizeof(struct qlc_83xx_poll));
1941 	delay = (long)p_hdr->delay;
1942 
1943 	for (i = 0; i < p_hdr->count; i++, entry++) {
1944 		qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1945 					     entry->ar_value);
1946 		if (delay) {
1947 			if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1948 						  poll->mask, poll->status)){
1949 				index = p_dev->ahw->reset.array_index;
1950 				addr = entry->dr_addr;
1951 				j = QLCRD32(p_dev, addr, &err);
1952 				if (err == -EIO)
1953 					return;
1954 
1955 				p_dev->ahw->reset.array[index++] = j;
1956 
1957 				if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1958 					p_dev->ahw->reset.array_index = 1;
1959 			}
1960 		}
1961 	}
1962 }
1963 
1964 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1965 {
1966 	p_dev->ahw->reset.seq_end = 1;
1967 }
1968 
1969 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1970 {
1971 	p_dev->ahw->reset.template_end = 1;
1972 	if (p_dev->ahw->reset.seq_error == 0)
1973 		dev_err(&p_dev->pdev->dev,
1974 			"HW restart process completed successfully.\n");
1975 	else
1976 		dev_err(&p_dev->pdev->dev,
1977 			"HW restart completed with timeout errors.\n");
1978 }
1979 
1980 /**
1981 * qlcnic_83xx_exec_template_cmd
1982 *
1983 * @p_dev: adapter structure
1984 * @p_buff: Poiter to instruction template
1985 *
1986 * Template provides instructions to stop, restart and initalize firmware.
1987 * These instructions are abstracted as a series of read, write and
1988 * poll operations on hardware registers. Register information and operation
1989 * specifics are not exposed to the driver. Driver reads the template from
1990 * flash and executes the instructions located at pre-defined offsets.
1991 *
1992 * Returns: None
1993 * */
1994 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1995 					  char *p_buff)
1996 {
1997 	int index, entries;
1998 	struct qlc_83xx_entry_hdr *p_hdr;
1999 	char *entry = p_buff;
2000 
2001 	p_dev->ahw->reset.seq_end = 0;
2002 	p_dev->ahw->reset.template_end = 0;
2003 	entries = p_dev->ahw->reset.hdr->entries;
2004 	index = p_dev->ahw->reset.seq_index;
2005 
2006 	for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
2007 		p_hdr = (struct qlc_83xx_entry_hdr *)entry;
2008 
2009 		switch (p_hdr->cmd) {
2010 		case QLC_83XX_OPCODE_NOP:
2011 			break;
2012 		case QLC_83XX_OPCODE_WRITE_LIST:
2013 			qlcnic_83xx_write_list(p_dev, p_hdr);
2014 			break;
2015 		case QLC_83XX_OPCODE_READ_WRITE_LIST:
2016 			qlcnic_83xx_read_write_list(p_dev, p_hdr);
2017 			break;
2018 		case QLC_83XX_OPCODE_POLL_LIST:
2019 			qlcnic_83xx_poll_list(p_dev, p_hdr);
2020 			break;
2021 		case QLC_83XX_OPCODE_POLL_WRITE_LIST:
2022 			qlcnic_83xx_poll_write_list(p_dev, p_hdr);
2023 			break;
2024 		case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
2025 			qlcnic_83xx_read_modify_write(p_dev, p_hdr);
2026 			break;
2027 		case QLC_83XX_OPCODE_SEQ_PAUSE:
2028 			qlcnic_83xx_pause(p_hdr);
2029 			break;
2030 		case QLC_83XX_OPCODE_SEQ_END:
2031 			qlcnic_83xx_seq_end(p_dev);
2032 			break;
2033 		case QLC_83XX_OPCODE_TMPL_END:
2034 			qlcnic_83xx_template_end(p_dev);
2035 			break;
2036 		case QLC_83XX_OPCODE_POLL_READ_LIST:
2037 			qlcnic_83xx_poll_read_list(p_dev, p_hdr);
2038 			break;
2039 		default:
2040 			dev_err(&p_dev->pdev->dev,
2041 				"%s: Unknown opcode 0x%04x in template %d\n",
2042 				__func__, p_hdr->cmd, index);
2043 			break;
2044 		}
2045 		entry += p_hdr->size;
2046 	}
2047 	p_dev->ahw->reset.seq_index = index;
2048 }
2049 
2050 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
2051 {
2052 	p_dev->ahw->reset.seq_index = 0;
2053 
2054 	qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
2055 	if (p_dev->ahw->reset.seq_end != 1)
2056 		dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
2057 }
2058 
2059 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
2060 {
2061 	qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
2062 	if (p_dev->ahw->reset.template_end != 1)
2063 		dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
2064 }
2065 
2066 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
2067 {
2068 	qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
2069 	if (p_dev->ahw->reset.seq_end != 1)
2070 		dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
2071 }
2072 
2073 /* POST FW related definations*/
2074 #define QLC_83XX_POST_SIGNATURE_REG	0x41602014
2075 #define QLC_83XX_POST_MODE_REG		0x41602018
2076 #define QLC_83XX_POST_FAST_MODE		0
2077 #define QLC_83XX_POST_MEDIUM_MODE	1
2078 #define QLC_83XX_POST_SLOW_MODE		2
2079 
2080 /* POST Timeout values in milliseconds */
2081 #define QLC_83XX_POST_FAST_MODE_TIMEOUT	690
2082 #define QLC_83XX_POST_MED_MODE_TIMEOUT	2930
2083 #define QLC_83XX_POST_SLOW_MODE_TIMEOUT	7500
2084 
2085 /* POST result values */
2086 #define QLC_83XX_POST_PASS			0xfffffff0
2087 #define QLC_83XX_POST_ASIC_STRESS_TEST_FAIL	0xffffffff
2088 #define QLC_83XX_POST_DDR_TEST_FAIL		0xfffffffe
2089 #define QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL	0xfffffffc
2090 #define QLC_83XX_POST_FLASH_TEST_FAIL		0xfffffff8
2091 
2092 static int qlcnic_83xx_run_post(struct qlcnic_adapter *adapter)
2093 {
2094 	struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
2095 	struct device *dev = &adapter->pdev->dev;
2096 	int timeout, count, ret = 0;
2097 	u32 signature;
2098 
2099 	/* Set timeout values with extra 2 seconds of buffer */
2100 	switch (adapter->ahw->post_mode) {
2101 	case QLC_83XX_POST_FAST_MODE:
2102 		timeout = QLC_83XX_POST_FAST_MODE_TIMEOUT + 2000;
2103 		break;
2104 	case QLC_83XX_POST_MEDIUM_MODE:
2105 		timeout = QLC_83XX_POST_MED_MODE_TIMEOUT + 2000;
2106 		break;
2107 	case QLC_83XX_POST_SLOW_MODE:
2108 		timeout = QLC_83XX_POST_SLOW_MODE_TIMEOUT + 2000;
2109 		break;
2110 	default:
2111 		return -EINVAL;
2112 	}
2113 
2114 	strncpy(fw_info->fw_file_name, QLC_83XX_POST_FW_FILE_NAME,
2115 		QLC_FW_FILE_NAME_LEN);
2116 
2117 	ret = request_firmware(&fw_info->fw, fw_info->fw_file_name, dev);
2118 	if (ret) {
2119 		dev_err(dev, "POST firmware can not be loaded, skipping POST\n");
2120 		return 0;
2121 	}
2122 
2123 	ret = qlcnic_83xx_copy_fw_file(adapter);
2124 	if (ret)
2125 		return ret;
2126 
2127 	/* clear QLC_83XX_POST_SIGNATURE_REG register */
2128 	qlcnic_ind_wr(adapter, QLC_83XX_POST_SIGNATURE_REG, 0);
2129 
2130 	/* Set POST mode */
2131 	qlcnic_ind_wr(adapter, QLC_83XX_POST_MODE_REG,
2132 		      adapter->ahw->post_mode);
2133 
2134 	QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2135 			    QLC_83XX_BOOT_FROM_FILE);
2136 
2137 	qlcnic_83xx_start_hw(adapter);
2138 
2139 	count = 0;
2140 	do {
2141 		msleep(100);
2142 		count += 100;
2143 
2144 		signature = qlcnic_ind_rd(adapter, QLC_83XX_POST_SIGNATURE_REG);
2145 		if (signature == QLC_83XX_POST_PASS)
2146 			break;
2147 	} while (timeout > count);
2148 
2149 	if (timeout <= count) {
2150 		dev_err(dev, "POST timed out, signature = 0x%08x\n", signature);
2151 		return -EIO;
2152 	}
2153 
2154 	switch (signature) {
2155 	case QLC_83XX_POST_PASS:
2156 		dev_info(dev, "POST passed, Signature = 0x%08x\n", signature);
2157 		break;
2158 	case QLC_83XX_POST_ASIC_STRESS_TEST_FAIL:
2159 		dev_err(dev, "POST failed, Test case : ASIC STRESS TEST, Signature = 0x%08x\n",
2160 			signature);
2161 		ret = -EIO;
2162 		break;
2163 	case QLC_83XX_POST_DDR_TEST_FAIL:
2164 		dev_err(dev, "POST failed, Test case : DDT TEST, Signature = 0x%08x\n",
2165 			signature);
2166 		ret = -EIO;
2167 		break;
2168 	case QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL:
2169 		dev_err(dev, "POST failed, Test case : ASIC MEMORY TEST, Signature = 0x%08x\n",
2170 			signature);
2171 		ret = -EIO;
2172 		break;
2173 	case QLC_83XX_POST_FLASH_TEST_FAIL:
2174 		dev_err(dev, "POST failed, Test case : FLASH TEST, Signature = 0x%08x\n",
2175 			signature);
2176 		ret = -EIO;
2177 		break;
2178 	default:
2179 		dev_err(dev, "POST failed, Test case : INVALID, Signature = 0x%08x\n",
2180 			signature);
2181 		ret = -EIO;
2182 		break;
2183 	}
2184 
2185 	return ret;
2186 }
2187 
2188 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
2189 {
2190 	struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
2191 	int err = -EIO;
2192 
2193 	if (request_firmware(&fw_info->fw, fw_info->fw_file_name,
2194 			     &(adapter->pdev->dev))) {
2195 		dev_err(&adapter->pdev->dev,
2196 			"No file FW image, loading flash FW image.\n");
2197 		QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2198 				    QLC_83XX_BOOT_FROM_FLASH);
2199 	} else {
2200 		if (qlcnic_83xx_copy_fw_file(adapter))
2201 			return err;
2202 		QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2203 				    QLC_83XX_BOOT_FROM_FILE);
2204 	}
2205 
2206 	return 0;
2207 }
2208 
2209 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
2210 {
2211 	u32 val;
2212 	int err = -EIO;
2213 
2214 	qlcnic_83xx_stop_hw(adapter);
2215 
2216 	/* Collect FW register dump if required */
2217 	val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
2218 	if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
2219 		qlcnic_dump_fw(adapter);
2220 
2221 	if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) {
2222 		netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n",
2223 			    __func__);
2224 		qlcnic_83xx_idc_enter_failed_state(adapter, 1);
2225 		return err;
2226 	}
2227 
2228 	qlcnic_83xx_init_hw(adapter);
2229 
2230 	if (qlcnic_83xx_copy_bootloader(adapter))
2231 		return err;
2232 
2233 	/* Check if POST needs to be run */
2234 	if (adapter->ahw->run_post) {
2235 		err = qlcnic_83xx_run_post(adapter);
2236 		if (err)
2237 			return err;
2238 
2239 		/* No need to run POST in next reset sequence */
2240 		adapter->ahw->run_post = false;
2241 
2242 		/* Again reset the adapter to load regular firmware  */
2243 		qlcnic_83xx_stop_hw(adapter);
2244 		qlcnic_83xx_init_hw(adapter);
2245 
2246 		err = qlcnic_83xx_copy_bootloader(adapter);
2247 		if (err)
2248 			return err;
2249 	}
2250 
2251 	/* Boot either flash image or firmware image from host file system */
2252 	if (qlcnic_load_fw_file == 1) {
2253 		if (qlcnic_83xx_load_fw_image_from_host(adapter))
2254 			return err;
2255 	} else {
2256 		QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2257 				    QLC_83XX_BOOT_FROM_FLASH);
2258 	}
2259 
2260 	qlcnic_83xx_start_hw(adapter);
2261 	if (qlcnic_83xx_check_hw_status(adapter))
2262 		return -EIO;
2263 
2264 	return 0;
2265 }
2266 
2267 static int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2268 {
2269 	int err;
2270 	struct qlcnic_info nic_info;
2271 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2272 
2273 	memset(&nic_info, 0, sizeof(struct qlcnic_info));
2274 	err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2275 	if (err)
2276 		return -EIO;
2277 
2278 	ahw->physical_port = (u8) nic_info.phys_port;
2279 	ahw->switch_mode = nic_info.switch_mode;
2280 	ahw->max_tx_ques = nic_info.max_tx_ques;
2281 	ahw->max_rx_ques = nic_info.max_rx_ques;
2282 	ahw->capabilities = nic_info.capabilities;
2283 	ahw->max_mac_filters = nic_info.max_mac_filters;
2284 	ahw->max_mtu = nic_info.max_mtu;
2285 
2286 	/* eSwitch capability indicates vNIC mode.
2287 	 * vNIC and SRIOV are mutually exclusive operational modes.
2288 	 * If SR-IOV capability is detected, SR-IOV physical function
2289 	 * will get initialized in default mode.
2290 	 * SR-IOV virtual function initialization follows a
2291 	 * different code path and opmode.
2292 	 * SRIOV mode has precedence over vNIC mode.
2293 	 */
2294 	if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2295 		return QLC_83XX_DEFAULT_OPMODE;
2296 
2297 	if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY)
2298 		return QLCNIC_VNIC_MODE;
2299 
2300 	return QLC_83XX_DEFAULT_OPMODE;
2301 }
2302 
2303 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2304 {
2305 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2306 	u16 max_sds_rings, max_tx_rings;
2307 	int ret;
2308 
2309 	ret = qlcnic_83xx_get_nic_configuration(adapter);
2310 	if (ret == -EIO)
2311 		return -EIO;
2312 
2313 	if (ret == QLCNIC_VNIC_MODE) {
2314 		ahw->nic_mode = QLCNIC_VNIC_MODE;
2315 
2316 		if (qlcnic_83xx_config_vnic_opmode(adapter))
2317 			return -EIO;
2318 
2319 		max_sds_rings = QLCNIC_MAX_VNIC_SDS_RINGS;
2320 		max_tx_rings = QLCNIC_MAX_VNIC_TX_RINGS;
2321 	} else if (ret == QLC_83XX_DEFAULT_OPMODE) {
2322 		ahw->nic_mode = QLCNIC_DEFAULT_MODE;
2323 		adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2324 		ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
2325 		max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2326 		max_tx_rings = QLCNIC_MAX_TX_RINGS;
2327 	} else {
2328 		dev_err(&adapter->pdev->dev, "%s: Invalid opmode %d\n",
2329 			__func__, ret);
2330 		return -EIO;
2331 	}
2332 
2333 	adapter->max_sds_rings = min(ahw->max_rx_ques, max_sds_rings);
2334 	adapter->max_tx_rings = min(ahw->max_tx_ques, max_tx_rings);
2335 
2336 	return 0;
2337 }
2338 
2339 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2340 {
2341 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2342 
2343 	if (ahw->port_type == QLCNIC_XGBE) {
2344 		adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2345 		adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2346 		adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2347 		adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2348 
2349 	} else if (ahw->port_type == QLCNIC_GBE) {
2350 		adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2351 		adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2352 		adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2353 		adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2354 	}
2355 	adapter->num_txd = MAX_CMD_DESCRIPTORS;
2356 	adapter->max_rds_rings = MAX_RDS_RINGS;
2357 }
2358 
2359 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2360 {
2361 	int err = -EIO;
2362 
2363 	qlcnic_83xx_get_minidump_template(adapter);
2364 	if (qlcnic_83xx_get_port_info(adapter))
2365 		return err;
2366 
2367 	qlcnic_83xx_config_buff_descriptors(adapter);
2368 	adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2369 	adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2370 
2371 	dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2372 		 adapter->ahw->fw_hal_version);
2373 
2374 	return 0;
2375 }
2376 
2377 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2378 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2379 {
2380 	struct qlcnic_cmd_args cmd;
2381 	u32 presence_mask, audit_mask;
2382 	int status;
2383 
2384 	presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2385 	audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2386 
2387 	if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2388 		status = qlcnic_alloc_mbx_args(&cmd, adapter,
2389 					       QLCNIC_CMD_STOP_NIC_FUNC);
2390 		if (status)
2391 			return;
2392 
2393 		cmd.req.arg[1] = BIT_31;
2394 		status = qlcnic_issue_cmd(adapter, &cmd);
2395 		if (status)
2396 			dev_err(&adapter->pdev->dev,
2397 				"Failed to clean up the function resources\n");
2398 		qlcnic_free_mbx_args(&cmd);
2399 	}
2400 }
2401 
2402 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter)
2403 {
2404 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2405 	struct pci_dev *pdev = adapter->pdev;
2406 	struct qlc_83xx_fw_info *fw_info;
2407 	int err = 0;
2408 
2409 	ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL);
2410 	if (!ahw->fw_info) {
2411 		err = -ENOMEM;
2412 	} else {
2413 		fw_info = ahw->fw_info;
2414 		switch (pdev->device) {
2415 		case PCI_DEVICE_ID_QLOGIC_QLE834X:
2416 		case PCI_DEVICE_ID_QLOGIC_QLE8830:
2417 			strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME,
2418 				QLC_FW_FILE_NAME_LEN);
2419 			break;
2420 		case PCI_DEVICE_ID_QLOGIC_QLE844X:
2421 			strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME,
2422 				QLC_FW_FILE_NAME_LEN);
2423 			break;
2424 		default:
2425 			dev_err(&pdev->dev, "%s: Invalid device id\n",
2426 				__func__);
2427 			err = -EINVAL;
2428 			break;
2429 		}
2430 	}
2431 
2432 	return err;
2433 }
2434 
2435 static void qlcnic_83xx_init_rings(struct qlcnic_adapter *adapter)
2436 {
2437 	u8 rx_cnt = QLCNIC_DEF_SDS_RINGS;
2438 	u8 tx_cnt = QLCNIC_DEF_TX_RINGS;
2439 
2440 	adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS;
2441 	adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS;
2442 
2443 	if (!adapter->ahw->msix_supported) {
2444 		rx_cnt = QLCNIC_SINGLE_RING;
2445 		tx_cnt = QLCNIC_SINGLE_RING;
2446 	}
2447 
2448 	/* compute and set drv sds rings */
2449 	qlcnic_set_tx_ring_count(adapter, tx_cnt);
2450 	qlcnic_set_sds_ring_count(adapter, rx_cnt);
2451 }
2452 
2453 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2454 {
2455 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2456 	int err = 0;
2457 
2458 	adapter->rx_mac_learn = false;
2459 	ahw->msix_supported = !!qlcnic_use_msi_x;
2460 
2461 	/* Check if POST needs to be run */
2462 	switch (qlcnic_load_fw_file) {
2463 	case 2:
2464 		ahw->post_mode = QLC_83XX_POST_FAST_MODE;
2465 		ahw->run_post = true;
2466 		break;
2467 	case 3:
2468 		ahw->post_mode = QLC_83XX_POST_MEDIUM_MODE;
2469 		ahw->run_post = true;
2470 		break;
2471 	case 4:
2472 		ahw->post_mode = QLC_83XX_POST_SLOW_MODE;
2473 		ahw->run_post = true;
2474 		break;
2475 	default:
2476 		ahw->run_post = false;
2477 		break;
2478 	}
2479 
2480 	qlcnic_83xx_init_rings(adapter);
2481 
2482 	err = qlcnic_83xx_init_mailbox_work(adapter);
2483 	if (err)
2484 		goto exit;
2485 
2486 	if (qlcnic_sriov_vf_check(adapter)) {
2487 		err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2488 		if (err)
2489 			goto detach_mbx;
2490 		else
2491 			return err;
2492 	}
2493 
2494 	if (qlcnic_83xx_read_flash_descriptor_table(adapter) ||
2495 	    qlcnic_83xx_read_flash_mfg_id(adapter)) {
2496 		dev_err(&adapter->pdev->dev, "Failed reading flash mfg id\n");
2497 		err = -ENOTRECOVERABLE;
2498 		goto detach_mbx;
2499 	}
2500 
2501 	err = qlcnic_83xx_check_hw_status(adapter);
2502 	if (err)
2503 		goto detach_mbx;
2504 
2505 	err = qlcnic_83xx_get_fw_info(adapter);
2506 	if (err)
2507 		goto detach_mbx;
2508 
2509 	err = qlcnic_83xx_idc_init(adapter);
2510 	if (err)
2511 		goto detach_mbx;
2512 
2513 	err = qlcnic_setup_intr(adapter);
2514 	if (err) {
2515 		dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2516 		goto disable_intr;
2517 	}
2518 
2519 	INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2520 
2521 	err = qlcnic_83xx_setup_mbx_intr(adapter);
2522 	if (err)
2523 		goto disable_mbx_intr;
2524 
2525 	qlcnic_83xx_clear_function_resources(adapter);
2526 	qlcnic_dcb_enable(adapter->dcb);
2527 	qlcnic_83xx_initialize_nic(adapter, 1);
2528 	qlcnic_dcb_get_info(adapter->dcb);
2529 
2530 	/* Configure default, SR-IOV or Virtual NIC mode of operation */
2531 	err = qlcnic_83xx_configure_opmode(adapter);
2532 	if (err)
2533 		goto disable_mbx_intr;
2534 
2535 
2536 	/* Perform operating mode specific initialization */
2537 	err = adapter->nic_ops->init_driver(adapter);
2538 	if (err)
2539 		goto disable_mbx_intr;
2540 
2541 	/* Periodically monitor device status */
2542 	qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2543 	return 0;
2544 
2545 disable_mbx_intr:
2546 	qlcnic_83xx_free_mbx_intr(adapter);
2547 
2548 disable_intr:
2549 	qlcnic_teardown_intr(adapter);
2550 
2551 detach_mbx:
2552 	qlcnic_83xx_detach_mailbox_work(adapter);
2553 	qlcnic_83xx_free_mailbox(ahw->mailbox);
2554 	ahw->mailbox = NULL;
2555 exit:
2556 	return err;
2557 }
2558 
2559 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter)
2560 {
2561 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2562 	struct qlc_83xx_idc *idc = &ahw->idc;
2563 
2564 	clear_bit(QLC_83XX_MBX_READY, &idc->status);
2565 	cancel_delayed_work_sync(&adapter->fw_work);
2566 
2567 	if (ahw->nic_mode == QLCNIC_VNIC_MODE)
2568 		qlcnic_83xx_disable_vnic_mode(adapter, 1);
2569 
2570 	qlcnic_83xx_idc_detach_driver(adapter);
2571 	qlcnic_83xx_initialize_nic(adapter, 0);
2572 
2573 	cancel_delayed_work_sync(&adapter->idc_aen_work);
2574 }
2575 
2576 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter)
2577 {
2578 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2579 	struct qlc_83xx_idc *idc = &ahw->idc;
2580 	int ret = 0;
2581 	u32 owner;
2582 
2583 	/* Mark the previous IDC state as NEED_RESET so
2584 	 * that state_entry() will perform the reattachment
2585 	 * and bringup the device
2586 	 */
2587 	idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET;
2588 	owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2589 	if (ahw->pci_func == owner) {
2590 		ret = qlcnic_83xx_restart_hw(adapter);
2591 		if (ret < 0)
2592 			return ret;
2593 		qlcnic_83xx_idc_clear_registers(adapter, 0);
2594 	}
2595 
2596 	ret = idc->state_entry(adapter);
2597 	return ret;
2598 }
2599 
2600 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter)
2601 {
2602 	struct qlcnic_hardware_context *ahw = adapter->ahw;
2603 	struct qlc_83xx_idc *idc = &ahw->idc;
2604 	u32 owner;
2605 
2606 	idc->prev_state = QLC_83XX_IDC_DEV_READY;
2607 	owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2608 	if (ahw->pci_func == owner)
2609 		qlcnic_83xx_idc_enter_ready_state(adapter, 0);
2610 
2611 	qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0);
2612 }
2613