1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic_sriov.h" 9 #include "qlcnic.h" 10 #include "qlcnic_hw.h" 11 12 /* Reset template definitions */ 13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000 14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000 15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101 16 17 #define QLC_83XX_OPCODE_NOP 0x0000 18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001 19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002 20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004 21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008 22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010 23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020 24 #define QLC_83XX_OPCODE_SEQ_END 0x0040 25 #define QLC_83XX_OPCODE_TMPL_END 0x0080 26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100 27 28 /* EPORT control registers */ 29 #define QLC_83XX_RESET_CONTROL 0x28084E50 30 #define QLC_83XX_RESET_REG 0x28084E60 31 #define QLC_83XX_RESET_PORT0 0x28084E70 32 #define QLC_83XX_RESET_PORT1 0x28084E80 33 #define QLC_83XX_RESET_PORT2 0x28084E90 34 #define QLC_83XX_RESET_PORT3 0x28084EA0 35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0 36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0 37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0 38 39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter); 40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev); 41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter); 42 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev); 43 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *); 44 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *); 45 46 /* Template header */ 47 struct qlc_83xx_reset_hdr { 48 #if defined(__LITTLE_ENDIAN) 49 u16 version; 50 u16 signature; 51 u16 size; 52 u16 entries; 53 u16 hdr_size; 54 u16 checksum; 55 u16 init_offset; 56 u16 start_offset; 57 #elif defined(__BIG_ENDIAN) 58 u16 signature; 59 u16 version; 60 u16 entries; 61 u16 size; 62 u16 checksum; 63 u16 hdr_size; 64 u16 start_offset; 65 u16 init_offset; 66 #endif 67 } __packed; 68 69 /* Command entry header. */ 70 struct qlc_83xx_entry_hdr { 71 #if defined(__LITTLE_ENDIAN) 72 u16 cmd; 73 u16 size; 74 u16 count; 75 u16 delay; 76 #elif defined(__BIG_ENDIAN) 77 u16 size; 78 u16 cmd; 79 u16 delay; 80 u16 count; 81 #endif 82 } __packed; 83 84 /* Generic poll command */ 85 struct qlc_83xx_poll { 86 u32 mask; 87 u32 status; 88 } __packed; 89 90 /* Read modify write command */ 91 struct qlc_83xx_rmw { 92 u32 mask; 93 u32 xor_value; 94 u32 or_value; 95 #if defined(__LITTLE_ENDIAN) 96 u8 shl; 97 u8 shr; 98 u8 index_a; 99 u8 rsvd; 100 #elif defined(__BIG_ENDIAN) 101 u8 rsvd; 102 u8 index_a; 103 u8 shr; 104 u8 shl; 105 #endif 106 } __packed; 107 108 /* Generic command with 2 DWORD */ 109 struct qlc_83xx_entry { 110 u32 arg1; 111 u32 arg2; 112 } __packed; 113 114 /* Generic command with 4 DWORD */ 115 struct qlc_83xx_quad_entry { 116 u32 dr_addr; 117 u32 dr_value; 118 u32 ar_addr; 119 u32 ar_value; 120 } __packed; 121 static const char *const qlc_83xx_idc_states[] = { 122 "Unknown", 123 "Cold", 124 "Init", 125 "Ready", 126 "Need Reset", 127 "Need Quiesce", 128 "Failed", 129 "Quiesce" 130 }; 131 132 static int 133 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter) 134 { 135 u32 val; 136 137 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 138 if ((val & 0xFFFF)) 139 return 1; 140 else 141 return 0; 142 } 143 144 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter) 145 { 146 u32 cur, prev; 147 cur = adapter->ahw->idc.curr_state; 148 prev = adapter->ahw->idc.prev_state; 149 150 dev_info(&adapter->pdev->dev, 151 "current state = %s, prev state = %s\n", 152 adapter->ahw->idc.name[cur], 153 adapter->ahw->idc.name[prev]); 154 } 155 156 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter, 157 u8 mode, int lock) 158 { 159 u32 val; 160 int seconds; 161 162 if (lock) { 163 if (qlcnic_83xx_lock_driver(adapter)) 164 return -EBUSY; 165 } 166 167 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 168 val |= (adapter->portnum & 0xf); 169 val |= mode << 7; 170 if (mode) 171 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 172 else 173 seconds = jiffies / HZ; 174 175 val |= seconds << 8; 176 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val); 177 adapter->ahw->idc.sec_counter = jiffies / HZ; 178 179 if (lock) 180 qlcnic_83xx_unlock_driver(adapter); 181 182 return 0; 183 } 184 185 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter) 186 { 187 u32 val; 188 189 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION); 190 val = val & ~(0x3 << (adapter->portnum * 2)); 191 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2)); 192 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val); 193 } 194 195 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter, 196 int lock) 197 { 198 u32 val; 199 200 if (lock) { 201 if (qlcnic_83xx_lock_driver(adapter)) 202 return -EBUSY; 203 } 204 205 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 206 val = val & ~0xFF; 207 val = val | QLC_83XX_IDC_MAJOR_VERSION; 208 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val); 209 210 if (lock) 211 qlcnic_83xx_unlock_driver(adapter); 212 213 return 0; 214 } 215 216 static int 217 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter, 218 int status, int lock) 219 { 220 u32 val; 221 222 if (lock) { 223 if (qlcnic_83xx_lock_driver(adapter)) 224 return -EBUSY; 225 } 226 227 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 228 229 if (status) 230 val = val | (1 << adapter->portnum); 231 else 232 val = val & ~(1 << adapter->portnum); 233 234 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 235 qlcnic_83xx_idc_update_minor_version(adapter); 236 237 if (lock) 238 qlcnic_83xx_unlock_driver(adapter); 239 240 return 0; 241 } 242 243 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter) 244 { 245 u32 val; 246 u8 version; 247 248 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 249 version = val & 0xFF; 250 251 if (version != QLC_83XX_IDC_MAJOR_VERSION) { 252 dev_info(&adapter->pdev->dev, 253 "%s:mismatch. version 0x%x, expected version 0x%x\n", 254 __func__, version, QLC_83XX_IDC_MAJOR_VERSION); 255 return -EIO; 256 } 257 258 return 0; 259 } 260 261 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter, 262 int lock) 263 { 264 u32 val; 265 266 if (lock) { 267 if (qlcnic_83xx_lock_driver(adapter)) 268 return -EBUSY; 269 } 270 271 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0); 272 /* Clear graceful reset bit */ 273 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 274 val &= ~QLC_83XX_IDC_GRACEFULL_RESET; 275 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 276 277 if (lock) 278 qlcnic_83xx_unlock_driver(adapter); 279 280 return 0; 281 } 282 283 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter, 284 int flag, int lock) 285 { 286 u32 val; 287 288 if (lock) { 289 if (qlcnic_83xx_lock_driver(adapter)) 290 return -EBUSY; 291 } 292 293 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 294 if (flag) 295 val = val | (1 << adapter->portnum); 296 else 297 val = val & ~(1 << adapter->portnum); 298 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val); 299 300 if (lock) 301 qlcnic_83xx_unlock_driver(adapter); 302 303 return 0; 304 } 305 306 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter, 307 int time_limit) 308 { 309 u64 seconds; 310 311 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 312 if (seconds <= time_limit) 313 return 0; 314 else 315 return -EBUSY; 316 } 317 318 /** 319 * qlcnic_83xx_idc_check_reset_ack_reg 320 * 321 * @adapter: adapter structure 322 * 323 * Check ACK wait limit and clear the functions which failed to ACK 324 * 325 * Return 0 if all functions have acknowledged the reset request. 326 **/ 327 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter) 328 { 329 int timeout; 330 u32 ack, presence, val; 331 332 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 333 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 334 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 335 dev_info(&adapter->pdev->dev, 336 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence); 337 if (!((ack & presence) == presence)) { 338 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) { 339 /* Clear functions which failed to ACK */ 340 dev_info(&adapter->pdev->dev, 341 "%s: ACK wait exceeds time limit\n", __func__); 342 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 343 val = val & ~(ack ^ presence); 344 if (qlcnic_83xx_lock_driver(adapter)) 345 return -EBUSY; 346 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 347 dev_info(&adapter->pdev->dev, 348 "%s: updated drv presence reg = 0x%x\n", 349 __func__, val); 350 qlcnic_83xx_unlock_driver(adapter); 351 return 0; 352 353 } else { 354 return 1; 355 } 356 } else { 357 dev_info(&adapter->pdev->dev, 358 "%s: Reset ACK received from all functions\n", 359 __func__); 360 return 0; 361 } 362 } 363 364 /** 365 * qlcnic_83xx_idc_tx_soft_reset 366 * 367 * @adapter: adapter structure 368 * 369 * Handle context deletion and recreation request from transmit routine 370 * 371 * Returns -EBUSY or Success (0) 372 * 373 **/ 374 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter) 375 { 376 struct net_device *netdev = adapter->netdev; 377 378 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 379 return -EBUSY; 380 381 netif_device_detach(netdev); 382 qlcnic_down(adapter, netdev); 383 qlcnic_up(adapter, netdev); 384 netif_device_attach(netdev); 385 clear_bit(__QLCNIC_RESETTING, &adapter->state); 386 netdev_info(adapter->netdev, "%s: soft reset complete.\n", __func__); 387 388 return 0; 389 } 390 391 /** 392 * qlcnic_83xx_idc_detach_driver 393 * 394 * @adapter: adapter structure 395 * Detach net interface, stop TX and cleanup resources before the HW reset. 396 * Returns: None 397 * 398 **/ 399 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter) 400 { 401 int i; 402 struct net_device *netdev = adapter->netdev; 403 404 netif_device_detach(netdev); 405 qlcnic_83xx_detach_mailbox_work(adapter); 406 407 /* Disable mailbox interrupt */ 408 qlcnic_83xx_disable_mbx_intr(adapter); 409 qlcnic_down(adapter, netdev); 410 for (i = 0; i < adapter->ahw->num_msix; i++) { 411 adapter->ahw->intr_tbl[i].id = i; 412 adapter->ahw->intr_tbl[i].enabled = 0; 413 adapter->ahw->intr_tbl[i].src = 0; 414 } 415 416 if (qlcnic_sriov_pf_check(adapter)) 417 qlcnic_sriov_pf_reset(adapter); 418 } 419 420 /** 421 * qlcnic_83xx_idc_attach_driver 422 * 423 * @adapter: adapter structure 424 * 425 * Re-attach and re-enable net interface 426 * Returns: None 427 * 428 **/ 429 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter) 430 { 431 struct net_device *netdev = adapter->netdev; 432 433 if (netif_running(netdev)) { 434 if (qlcnic_up(adapter, netdev)) 435 goto done; 436 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 437 } 438 done: 439 netif_device_attach(netdev); 440 } 441 442 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter, 443 int lock) 444 { 445 if (lock) { 446 if (qlcnic_83xx_lock_driver(adapter)) 447 return -EBUSY; 448 } 449 450 qlcnic_83xx_idc_clear_registers(adapter, 0); 451 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED); 452 if (lock) 453 qlcnic_83xx_unlock_driver(adapter); 454 455 qlcnic_83xx_idc_log_state_history(adapter); 456 dev_info(&adapter->pdev->dev, "Device will enter failed state\n"); 457 458 return 0; 459 } 460 461 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter, 462 int lock) 463 { 464 if (lock) { 465 if (qlcnic_83xx_lock_driver(adapter)) 466 return -EBUSY; 467 } 468 469 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT); 470 471 if (lock) 472 qlcnic_83xx_unlock_driver(adapter); 473 474 return 0; 475 } 476 477 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter, 478 int lock) 479 { 480 if (lock) { 481 if (qlcnic_83xx_lock_driver(adapter)) 482 return -EBUSY; 483 } 484 485 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 486 QLC_83XX_IDC_DEV_NEED_QUISCENT); 487 488 if (lock) 489 qlcnic_83xx_unlock_driver(adapter); 490 491 return 0; 492 } 493 494 static int 495 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock) 496 { 497 if (lock) { 498 if (qlcnic_83xx_lock_driver(adapter)) 499 return -EBUSY; 500 } 501 502 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 503 QLC_83XX_IDC_DEV_NEED_RESET); 504 505 if (lock) 506 qlcnic_83xx_unlock_driver(adapter); 507 508 return 0; 509 } 510 511 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter, 512 int lock) 513 { 514 if (lock) { 515 if (qlcnic_83xx_lock_driver(adapter)) 516 return -EBUSY; 517 } 518 519 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY); 520 if (lock) 521 qlcnic_83xx_unlock_driver(adapter); 522 523 return 0; 524 } 525 526 /** 527 * qlcnic_83xx_idc_find_reset_owner_id 528 * 529 * @adapter: adapter structure 530 * 531 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE. 532 * Within the same class, function with lowest PCI ID assumes ownership 533 * 534 * Returns: reset owner id or failure indication (-EIO) 535 * 536 **/ 537 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter) 538 { 539 u32 reg, reg1, reg2, i, j, owner, class; 540 541 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); 542 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2); 543 owner = QLCNIC_TYPE_NIC; 544 i = 0; 545 j = 0; 546 reg = reg1; 547 548 do { 549 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3); 550 if (class == owner) 551 break; 552 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) { 553 reg = reg2; 554 j = 0; 555 } else { 556 j++; 557 } 558 559 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) { 560 if (owner == QLCNIC_TYPE_NIC) 561 owner = QLCNIC_TYPE_ISCSI; 562 else if (owner == QLCNIC_TYPE_ISCSI) 563 owner = QLCNIC_TYPE_FCOE; 564 else if (owner == QLCNIC_TYPE_FCOE) 565 return -EIO; 566 reg = reg1; 567 j = 0; 568 i = 0; 569 } 570 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS); 571 572 return i; 573 } 574 575 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock) 576 { 577 int ret = 0; 578 579 ret = qlcnic_83xx_restart_hw(adapter); 580 581 if (ret) { 582 qlcnic_83xx_idc_enter_failed_state(adapter, lock); 583 } else { 584 qlcnic_83xx_idc_clear_registers(adapter, lock); 585 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock); 586 } 587 588 return ret; 589 } 590 591 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter) 592 { 593 u32 status; 594 595 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1); 596 597 if (status & QLCNIC_RCODE_FATAL_ERROR) { 598 dev_err(&adapter->pdev->dev, 599 "peg halt status1=0x%x\n", status); 600 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) { 601 dev_err(&adapter->pdev->dev, 602 "On board active cooling fan failed. " 603 "Device has been halted.\n"); 604 dev_err(&adapter->pdev->dev, 605 "Replace the adapter.\n"); 606 return -EIO; 607 } 608 } 609 610 return 0; 611 } 612 613 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter) 614 { 615 int err; 616 617 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox); 618 qlcnic_83xx_enable_mbx_interrupt(adapter); 619 620 qlcnic_83xx_initialize_nic(adapter, 1); 621 622 err = qlcnic_sriov_pf_reinit(adapter); 623 if (err) 624 return err; 625 626 qlcnic_83xx_enable_mbx_interrupt(adapter); 627 628 if (qlcnic_83xx_configure_opmode(adapter)) { 629 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 630 return -EIO; 631 } 632 633 if (adapter->nic_ops->init_driver(adapter)) { 634 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 635 return -EIO; 636 } 637 638 if (adapter->portnum == 0) 639 qlcnic_set_drv_version(adapter); 640 641 qlcnic_dcb_get_info(adapter->dcb); 642 qlcnic_83xx_idc_attach_driver(adapter); 643 644 return 0; 645 } 646 647 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter) 648 { 649 struct qlcnic_hardware_context *ahw = adapter->ahw; 650 651 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1); 652 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 653 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 654 655 ahw->idc.quiesce_req = 0; 656 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 657 ahw->idc.err_code = 0; 658 ahw->idc.collect_dump = 0; 659 ahw->reset_context = 0; 660 adapter->tx_timeo_cnt = 0; 661 ahw->idc.delay_reset = 0; 662 663 clear_bit(__QLCNIC_RESETTING, &adapter->state); 664 } 665 666 /** 667 * qlcnic_83xx_idc_ready_state_entry 668 * 669 * @adapter: adapter structure 670 * 671 * Perform ready state initialization, this routine will get invoked only 672 * once from READY state. 673 * 674 * Returns: Error code or Success(0) 675 * 676 **/ 677 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter) 678 { 679 struct qlcnic_hardware_context *ahw = adapter->ahw; 680 681 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) { 682 qlcnic_83xx_idc_update_idc_params(adapter); 683 /* Re-attach the device if required */ 684 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || 685 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) { 686 if (qlcnic_83xx_idc_reattach_driver(adapter)) 687 return -EIO; 688 } 689 } 690 691 return 0; 692 } 693 694 /** 695 * qlcnic_83xx_idc_vnic_pf_entry 696 * 697 * @adapter: adapter structure 698 * 699 * Ensure vNIC mode privileged function starts only after vNIC mode is 700 * enabled by management function. 701 * If vNIC mode is ready, start initialization. 702 * 703 * Returns: -EIO or 0 704 * 705 **/ 706 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter) 707 { 708 u32 state; 709 struct qlcnic_hardware_context *ahw = adapter->ahw; 710 711 /* Privileged function waits till mgmt function enables VNIC mode */ 712 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE); 713 if (state != QLCNIC_DEV_NPAR_OPER) { 714 if (!ahw->idc.vnic_wait_limit--) { 715 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 716 return -EIO; 717 } 718 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n"); 719 return -EIO; 720 721 } else { 722 /* Perform one time initialization from ready state */ 723 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) { 724 qlcnic_83xx_idc_update_idc_params(adapter); 725 726 /* If the previous state is UNKNOWN, device will be 727 already attached properly by Init routine*/ 728 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) { 729 if (qlcnic_83xx_idc_reattach_driver(adapter)) 730 return -EIO; 731 } 732 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER; 733 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n"); 734 } 735 } 736 737 return 0; 738 } 739 740 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter) 741 { 742 adapter->ahw->idc.err_code = -EIO; 743 dev_err(&adapter->pdev->dev, 744 "%s: Device in unknown state\n", __func__); 745 clear_bit(__QLCNIC_RESETTING, &adapter->state); 746 return 0; 747 } 748 749 /** 750 * qlcnic_83xx_idc_cold_state 751 * 752 * @adapter: adapter structure 753 * 754 * If HW is up and running device will enter READY state. 755 * If firmware image from host needs to be loaded, device is 756 * forced to start with the file firmware image. 757 * 758 * Returns: Error code or Success(0) 759 * 760 **/ 761 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter) 762 { 763 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0); 764 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0); 765 766 if (qlcnic_load_fw_file) { 767 qlcnic_83xx_idc_restart_hw(adapter, 0); 768 } else { 769 if (qlcnic_83xx_check_hw_status(adapter)) { 770 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 771 return -EIO; 772 } else { 773 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 774 } 775 } 776 return 0; 777 } 778 779 /** 780 * qlcnic_83xx_idc_init_state 781 * 782 * @adapter: adapter structure 783 * 784 * Reset owner will restart the device from this state. 785 * Device will enter failed state if it remains 786 * in this state for more than DEV_INIT time limit. 787 * 788 * Returns: Error code or Success(0) 789 * 790 **/ 791 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter) 792 { 793 int timeout, ret = 0; 794 u32 owner; 795 796 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 797 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) { 798 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 799 if (adapter->ahw->pci_func == owner) 800 ret = qlcnic_83xx_idc_restart_hw(adapter, 1); 801 } else { 802 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout); 803 } 804 805 return ret; 806 } 807 808 /** 809 * qlcnic_83xx_idc_ready_state 810 * 811 * @adapter: adapter structure 812 * 813 * Perform IDC protocol specicifed actions after monitoring device state and 814 * events. 815 * 816 * Returns: Error code or Success(0) 817 * 818 **/ 819 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter) 820 { 821 struct qlcnic_hardware_context *ahw = adapter->ahw; 822 struct qlcnic_mailbox *mbx = ahw->mailbox; 823 int ret = 0; 824 u32 val; 825 826 /* Perform NIC configuration based ready state entry actions */ 827 if (ahw->idc.state_entry(adapter)) 828 return -EIO; 829 830 if (qlcnic_check_temp(adapter)) { 831 if (ahw->temp == QLCNIC_TEMP_PANIC) { 832 qlcnic_83xx_idc_check_fan_failure(adapter); 833 dev_err(&adapter->pdev->dev, 834 "Error: device temperature %d above limits\n", 835 adapter->ahw->temp); 836 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 837 set_bit(__QLCNIC_RESETTING, &adapter->state); 838 qlcnic_83xx_idc_detach_driver(adapter); 839 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 840 return -EIO; 841 } 842 } 843 844 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 845 ret = qlcnic_83xx_check_heartbeat(adapter); 846 if (ret) { 847 adapter->flags |= QLCNIC_FW_HANG; 848 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 849 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 850 set_bit(__QLCNIC_RESETTING, &adapter->state); 851 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 852 } else { 853 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 854 __func__); 855 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 856 } 857 return -EIO; 858 } 859 860 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) { 861 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 862 863 /* Move to need reset state and prepare for reset */ 864 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 865 return ret; 866 } 867 868 /* Check for soft reset request */ 869 if (ahw->reset_context && 870 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 871 adapter->ahw->reset_context = 0; 872 qlcnic_83xx_idc_tx_soft_reset(adapter); 873 return ret; 874 } 875 876 /* Move to need quiesce state if requested */ 877 if (adapter->ahw->idc.quiesce_req) { 878 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1); 879 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 880 return ret; 881 } 882 883 return ret; 884 } 885 886 /** 887 * qlcnic_83xx_idc_need_reset_state 888 * 889 * @adapter: adapter structure 890 * 891 * Device will remain in this state until: 892 * Reset request ACK's are received from all the functions 893 * Wait time exceeds max time limit 894 * 895 * Returns: Error code or Success(0) 896 * 897 **/ 898 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter) 899 { 900 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 901 int ret = 0; 902 903 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) { 904 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 905 set_bit(__QLCNIC_RESETTING, &adapter->state); 906 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 907 if (adapter->ahw->nic_mode == QLCNIC_VNIC_MODE) 908 qlcnic_83xx_disable_vnic_mode(adapter, 1); 909 910 if (qlcnic_check_diag_status(adapter)) { 911 dev_info(&adapter->pdev->dev, 912 "%s: Wait for diag completion\n", __func__); 913 adapter->ahw->idc.delay_reset = 1; 914 return 0; 915 } else { 916 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 917 qlcnic_83xx_idc_detach_driver(adapter); 918 } 919 } 920 921 if (qlcnic_check_diag_status(adapter)) { 922 dev_info(&adapter->pdev->dev, 923 "%s: Wait for diag completion\n", __func__); 924 return -1; 925 } else { 926 if (adapter->ahw->idc.delay_reset) { 927 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 928 qlcnic_83xx_idc_detach_driver(adapter); 929 adapter->ahw->idc.delay_reset = 0; 930 } 931 932 /* Check for ACK from other functions */ 933 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter); 934 if (ret) { 935 dev_info(&adapter->pdev->dev, 936 "%s: Waiting for reset ACK\n", __func__); 937 return -1; 938 } 939 } 940 941 /* Transit to INIT state and restart the HW */ 942 qlcnic_83xx_idc_enter_init_state(adapter, 1); 943 944 return ret; 945 } 946 947 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter) 948 { 949 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__); 950 return 0; 951 } 952 953 static void qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter) 954 { 955 struct qlcnic_hardware_context *ahw = adapter->ahw; 956 u32 val, owner; 957 958 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 959 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 960 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 961 if (ahw->pci_func == owner) { 962 qlcnic_83xx_stop_hw(adapter); 963 qlcnic_dump_fw(adapter); 964 } 965 } 966 967 netdev_warn(adapter->netdev, "%s: Reboot will be required to recover the adapter!!\n", 968 __func__); 969 clear_bit(__QLCNIC_RESETTING, &adapter->state); 970 ahw->idc.err_code = -EIO; 971 972 return; 973 } 974 975 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter) 976 { 977 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__); 978 return 0; 979 } 980 981 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter, 982 u32 state) 983 { 984 u32 cur, prev, next; 985 986 cur = adapter->ahw->idc.curr_state; 987 prev = adapter->ahw->idc.prev_state; 988 next = state; 989 990 if ((next < QLC_83XX_IDC_DEV_COLD) || 991 (next > QLC_83XX_IDC_DEV_QUISCENT)) { 992 dev_err(&adapter->pdev->dev, 993 "%s: curr %d, prev %d, next state %d is invalid\n", 994 __func__, cur, prev, state); 995 return 1; 996 } 997 998 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) && 999 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) { 1000 if ((next != QLC_83XX_IDC_DEV_COLD) && 1001 (next != QLC_83XX_IDC_DEV_READY)) { 1002 dev_err(&adapter->pdev->dev, 1003 "%s: failed, cur %d prev %d next %d\n", 1004 __func__, cur, prev, next); 1005 return 1; 1006 } 1007 } 1008 1009 if (next == QLC_83XX_IDC_DEV_INIT) { 1010 if ((prev != QLC_83XX_IDC_DEV_INIT) && 1011 (prev != QLC_83XX_IDC_DEV_COLD) && 1012 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) { 1013 dev_err(&adapter->pdev->dev, 1014 "%s: failed, cur %d prev %d next %d\n", 1015 __func__, cur, prev, next); 1016 return 1; 1017 } 1018 } 1019 1020 return 0; 1021 } 1022 1023 #define QLC_83XX_ENCAP_TYPE_VXLAN BIT_1 1024 #define QLC_83XX_MATCH_ENCAP_ID BIT_2 1025 #define QLC_83XX_SET_VXLAN_UDP_DPORT BIT_3 1026 #define QLC_83XX_VXLAN_UDP_DPORT(PORT) ((PORT & 0xffff) << 16) 1027 1028 #define QLCNIC_ENABLE_INGRESS_ENCAP_PARSING 1 1029 #define QLCNIC_DISABLE_INGRESS_ENCAP_PARSING 0 1030 1031 int qlcnic_set_vxlan_port(struct qlcnic_adapter *adapter, u16 port) 1032 { 1033 struct qlcnic_cmd_args cmd; 1034 int ret = 0; 1035 1036 memset(&cmd, 0, sizeof(cmd)); 1037 1038 ret = qlcnic_alloc_mbx_args(&cmd, adapter, 1039 QLCNIC_CMD_INIT_NIC_FUNC); 1040 if (ret) 1041 return ret; 1042 1043 cmd.req.arg[1] = QLC_83XX_MULTI_TENANCY_INFO; 1044 cmd.req.arg[2] = QLC_83XX_ENCAP_TYPE_VXLAN | 1045 QLC_83XX_SET_VXLAN_UDP_DPORT | 1046 QLC_83XX_VXLAN_UDP_DPORT(port); 1047 1048 ret = qlcnic_issue_cmd(adapter, &cmd); 1049 if (ret) 1050 netdev_err(adapter->netdev, 1051 "Failed to set VXLAN port %d in adapter\n", 1052 port); 1053 1054 qlcnic_free_mbx_args(&cmd); 1055 1056 return ret; 1057 } 1058 1059 int qlcnic_set_vxlan_parsing(struct qlcnic_adapter *adapter, u16 port) 1060 { 1061 struct qlcnic_cmd_args cmd; 1062 int ret = 0; 1063 1064 memset(&cmd, 0, sizeof(cmd)); 1065 1066 ret = qlcnic_alloc_mbx_args(&cmd, adapter, 1067 QLCNIC_CMD_SET_INGRESS_ENCAP); 1068 if (ret) 1069 return ret; 1070 1071 cmd.req.arg[1] = port ? QLCNIC_ENABLE_INGRESS_ENCAP_PARSING : 1072 QLCNIC_DISABLE_INGRESS_ENCAP_PARSING; 1073 1074 ret = qlcnic_issue_cmd(adapter, &cmd); 1075 if (ret) 1076 netdev_err(adapter->netdev, 1077 "Failed to %s VXLAN parsing for port %d\n", 1078 port ? "enable" : "disable", port); 1079 else 1080 netdev_info(adapter->netdev, 1081 "%s VXLAN parsing for port %d\n", 1082 port ? "Enabled" : "Disabled", port); 1083 1084 qlcnic_free_mbx_args(&cmd); 1085 1086 return ret; 1087 } 1088 1089 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter) 1090 { 1091 if (adapter->fhash.fnum) 1092 qlcnic_prune_lb_filters(adapter); 1093 } 1094 1095 /** 1096 * qlcnic_83xx_idc_poll_dev_state 1097 * 1098 * @work: kernel work queue structure used to schedule the function 1099 * 1100 * Poll device state periodically and perform state specific 1101 * actions defined by Inter Driver Communication (IDC) protocol. 1102 * 1103 * Returns: None 1104 * 1105 **/ 1106 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work) 1107 { 1108 struct qlcnic_adapter *adapter; 1109 u32 state; 1110 1111 adapter = container_of(work, struct qlcnic_adapter, fw_work.work); 1112 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1113 1114 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1115 qlcnic_83xx_idc_log_state_history(adapter); 1116 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1117 } else { 1118 adapter->ahw->idc.curr_state = state; 1119 } 1120 1121 switch (adapter->ahw->idc.curr_state) { 1122 case QLC_83XX_IDC_DEV_READY: 1123 qlcnic_83xx_idc_ready_state(adapter); 1124 break; 1125 case QLC_83XX_IDC_DEV_NEED_RESET: 1126 qlcnic_83xx_idc_need_reset_state(adapter); 1127 break; 1128 case QLC_83XX_IDC_DEV_NEED_QUISCENT: 1129 qlcnic_83xx_idc_need_quiesce_state(adapter); 1130 break; 1131 case QLC_83XX_IDC_DEV_FAILED: 1132 qlcnic_83xx_idc_failed_state(adapter); 1133 return; 1134 case QLC_83XX_IDC_DEV_INIT: 1135 qlcnic_83xx_idc_init_state(adapter); 1136 break; 1137 case QLC_83XX_IDC_DEV_QUISCENT: 1138 qlcnic_83xx_idc_quiesce_state(adapter); 1139 break; 1140 default: 1141 qlcnic_83xx_idc_unknown_state(adapter); 1142 return; 1143 } 1144 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state; 1145 qlcnic_83xx_periodic_tasks(adapter); 1146 1147 /* Re-schedule the function */ 1148 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status)) 1149 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 1150 adapter->ahw->idc.delay); 1151 } 1152 1153 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter) 1154 { 1155 u32 idc_params, val; 1156 1157 if (qlcnic_83xx_flash_read32(adapter, QLC_83XX_IDC_FLASH_PARAM_ADDR, 1158 (u8 *)&idc_params, 1)) { 1159 dev_info(&adapter->pdev->dev, 1160 "%s:failed to get IDC params from flash\n", __func__); 1161 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 1162 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 1163 } else { 1164 adapter->dev_init_timeo = idc_params & 0xFFFF; 1165 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF); 1166 } 1167 1168 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1169 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN; 1170 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 1171 adapter->ahw->idc.err_code = 0; 1172 adapter->ahw->idc.collect_dump = 0; 1173 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states; 1174 1175 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1176 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1177 1178 /* Check if reset recovery is disabled */ 1179 if (!qlcnic_auto_fw_reset) { 1180 /* Propagate do not reset request to other functions */ 1181 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1182 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1183 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1184 } 1185 } 1186 1187 static int 1188 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter) 1189 { 1190 u32 state, val; 1191 1192 if (qlcnic_83xx_lock_driver(adapter)) 1193 return -EIO; 1194 1195 /* Clear driver lock register */ 1196 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0); 1197 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) { 1198 qlcnic_83xx_unlock_driver(adapter); 1199 return -EIO; 1200 } 1201 1202 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1203 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1204 qlcnic_83xx_unlock_driver(adapter); 1205 return -EIO; 1206 } 1207 1208 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) { 1209 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 1210 QLC_83XX_IDC_DEV_COLD); 1211 state = QLC_83XX_IDC_DEV_COLD; 1212 } 1213 1214 adapter->ahw->idc.curr_state = state; 1215 /* First to load function should cold boot the device */ 1216 if (state == QLC_83XX_IDC_DEV_COLD) 1217 qlcnic_83xx_idc_cold_state_handler(adapter); 1218 1219 /* Check if reset recovery is enabled */ 1220 if (qlcnic_auto_fw_reset) { 1221 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1222 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1223 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1224 } 1225 1226 qlcnic_83xx_unlock_driver(adapter); 1227 1228 return 0; 1229 } 1230 1231 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter) 1232 { 1233 int ret = -EIO; 1234 1235 qlcnic_83xx_setup_idc_parameters(adapter); 1236 1237 if (qlcnic_83xx_get_reset_instruction_template(adapter)) 1238 return ret; 1239 1240 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) { 1241 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter)) 1242 return -EIO; 1243 } else { 1244 if (qlcnic_83xx_idc_check_major_version(adapter)) 1245 return -EIO; 1246 } 1247 1248 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 1249 1250 return 0; 1251 } 1252 1253 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter) 1254 { 1255 int id; 1256 u32 val; 1257 1258 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 1259 usleep_range(10000, 11000); 1260 1261 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1262 id = id & 0xFF; 1263 1264 if (id == adapter->portnum) { 1265 dev_err(&adapter->pdev->dev, 1266 "%s: wait for lock recovery.. %d\n", __func__, id); 1267 msleep(20); 1268 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1269 id = id & 0xFF; 1270 } 1271 1272 /* Clear driver presence bit */ 1273 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 1274 val = val & ~(1 << adapter->portnum); 1275 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 1276 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1277 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1278 1279 cancel_delayed_work_sync(&adapter->fw_work); 1280 } 1281 1282 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key) 1283 { 1284 u32 val; 1285 1286 if (qlcnic_sriov_vf_check(adapter)) 1287 return; 1288 1289 if (qlcnic_83xx_lock_driver(adapter)) { 1290 dev_err(&adapter->pdev->dev, 1291 "%s:failed, please retry\n", __func__); 1292 return; 1293 } 1294 1295 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1296 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 1297 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 1298 __func__); 1299 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 1300 qlcnic_83xx_unlock_driver(adapter); 1301 return; 1302 } 1303 1304 if (key == QLCNIC_FORCE_FW_RESET) { 1305 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1306 val = val | QLC_83XX_IDC_GRACEFULL_RESET; 1307 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1308 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) { 1309 adapter->ahw->idc.collect_dump = 1; 1310 } 1311 1312 qlcnic_83xx_unlock_driver(adapter); 1313 return; 1314 } 1315 1316 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter) 1317 { 1318 u8 *p_cache; 1319 u32 src, size; 1320 u64 dest; 1321 int ret = -EIO; 1322 1323 src = QLC_83XX_BOOTLOADER_FLASH_ADDR; 1324 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR); 1325 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE); 1326 1327 /* alignment check */ 1328 if (size & 0xF) 1329 size = (size + 16) & ~0xF; 1330 1331 p_cache = vzalloc(size); 1332 if (p_cache == NULL) 1333 return -ENOMEM; 1334 1335 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache, 1336 size / sizeof(u32)); 1337 if (ret) { 1338 vfree(p_cache); 1339 return ret; 1340 } 1341 /* 16 byte write to MS memory */ 1342 ret = qlcnic_ms_mem_write128(adapter, dest, (u32 *)p_cache, 1343 size / 16); 1344 if (ret) { 1345 vfree(p_cache); 1346 return ret; 1347 } 1348 vfree(p_cache); 1349 1350 return ret; 1351 } 1352 1353 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter) 1354 { 1355 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 1356 const struct firmware *fw = fw_info->fw; 1357 u32 dest, *p_cache, *temp; 1358 int i, ret = -EIO; 1359 __le32 *temp_le; 1360 u8 data[16]; 1361 size_t size; 1362 u64 addr; 1363 1364 temp = vzalloc(fw->size); 1365 if (!temp) { 1366 release_firmware(fw); 1367 fw_info->fw = NULL; 1368 return -ENOMEM; 1369 } 1370 1371 temp_le = (__le32 *)fw->data; 1372 1373 /* FW image in file is in little endian, swap the data to nullify 1374 * the effect of writel() operation on big endian platform. 1375 */ 1376 for (i = 0; i < fw->size / sizeof(u32); i++) 1377 temp[i] = __le32_to_cpu(temp_le[i]); 1378 1379 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR); 1380 size = (fw->size & ~0xF); 1381 p_cache = temp; 1382 addr = (u64)dest; 1383 1384 ret = qlcnic_ms_mem_write128(adapter, addr, 1385 p_cache, size / 16); 1386 if (ret) { 1387 dev_err(&adapter->pdev->dev, "MS memory write failed\n"); 1388 goto exit; 1389 } 1390 1391 /* alignment check */ 1392 if (fw->size & 0xF) { 1393 addr = dest + size; 1394 for (i = 0; i < (fw->size & 0xF); i++) 1395 data[i] = ((u8 *)temp)[size + i]; 1396 for (; i < 16; i++) 1397 data[i] = 0; 1398 ret = qlcnic_ms_mem_write128(adapter, addr, 1399 (u32 *)data, 1); 1400 if (ret) { 1401 dev_err(&adapter->pdev->dev, 1402 "MS memory write failed\n"); 1403 goto exit; 1404 } 1405 } 1406 1407 exit: 1408 release_firmware(fw); 1409 fw_info->fw = NULL; 1410 vfree(temp); 1411 1412 return ret; 1413 } 1414 1415 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) 1416 { 1417 int i, j; 1418 u32 val = 0, val1 = 0, reg = 0; 1419 int err = 0; 1420 1421 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err); 1422 if (err == -EIO) 1423 return; 1424 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); 1425 1426 for (j = 0; j < 2; j++) { 1427 if (j == 0) { 1428 dev_info(&adapter->pdev->dev, 1429 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:"); 1430 reg = QLC_83XX_PORT0_THRESHOLD; 1431 } else if (j == 1) { 1432 dev_info(&adapter->pdev->dev, 1433 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:"); 1434 reg = QLC_83XX_PORT1_THRESHOLD; 1435 } 1436 for (i = 0; i < 8; i++) { 1437 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1438 if (err == -EIO) 1439 return; 1440 dev_info(&adapter->pdev->dev, "0x%x ", val); 1441 } 1442 dev_info(&adapter->pdev->dev, "\n"); 1443 } 1444 1445 for (j = 0; j < 2; j++) { 1446 if (j == 0) { 1447 dev_info(&adapter->pdev->dev, 1448 "Port 0 RxB TC Max Cell Registers[4..1]:"); 1449 reg = QLC_83XX_PORT0_TC_MC_REG; 1450 } else if (j == 1) { 1451 dev_info(&adapter->pdev->dev, 1452 "Port 1 RxB TC Max Cell Registers[4..1]:"); 1453 reg = QLC_83XX_PORT1_TC_MC_REG; 1454 } 1455 for (i = 0; i < 4; i++) { 1456 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1457 if (err == -EIO) 1458 return; 1459 dev_info(&adapter->pdev->dev, "0x%x ", val); 1460 } 1461 dev_info(&adapter->pdev->dev, "\n"); 1462 } 1463 1464 for (j = 0; j < 2; j++) { 1465 if (j == 0) { 1466 dev_info(&adapter->pdev->dev, 1467 "Port 0 RxB Rx TC Stats[TC7..TC0]:"); 1468 reg = QLC_83XX_PORT0_TC_STATS; 1469 } else if (j == 1) { 1470 dev_info(&adapter->pdev->dev, 1471 "Port 1 RxB Rx TC Stats[TC7..TC0]:"); 1472 reg = QLC_83XX_PORT1_TC_STATS; 1473 } 1474 for (i = 7; i >= 0; i--) { 1475 val = QLCRD32(adapter, reg, &err); 1476 if (err == -EIO) 1477 return; 1478 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ 1479 QLCWR32(adapter, reg, (val | (i << 29))); 1480 val = QLCRD32(adapter, reg, &err); 1481 if (err == -EIO) 1482 return; 1483 dev_info(&adapter->pdev->dev, "0x%x ", val); 1484 } 1485 dev_info(&adapter->pdev->dev, "\n"); 1486 } 1487 1488 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err); 1489 if (err == -EIO) 1490 return; 1491 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err); 1492 if (err == -EIO) 1493 return; 1494 dev_info(&adapter->pdev->dev, 1495 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", 1496 val, val1); 1497 } 1498 1499 1500 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter) 1501 { 1502 u32 reg = 0, i, j; 1503 1504 if (qlcnic_83xx_lock_driver(adapter)) { 1505 dev_err(&adapter->pdev->dev, 1506 "%s:failed to acquire driver lock\n", __func__); 1507 return; 1508 } 1509 1510 qlcnic_83xx_dump_pause_control_regs(adapter); 1511 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0); 1512 1513 for (j = 0; j < 2; j++) { 1514 if (j == 0) 1515 reg = QLC_83XX_PORT0_THRESHOLD; 1516 else if (j == 1) 1517 reg = QLC_83XX_PORT1_THRESHOLD; 1518 1519 for (i = 0; i < 8; i++) 1520 QLCWR32(adapter, reg + (i * 0x4), 0x0); 1521 } 1522 1523 for (j = 0; j < 2; j++) { 1524 if (j == 0) 1525 reg = QLC_83XX_PORT0_TC_MC_REG; 1526 else if (j == 1) 1527 reg = QLC_83XX_PORT1_TC_MC_REG; 1528 1529 for (i = 0; i < 4; i++) 1530 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF); 1531 } 1532 1533 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0); 1534 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0); 1535 dev_info(&adapter->pdev->dev, 1536 "Disabled pause frames successfully on all ports\n"); 1537 qlcnic_83xx_unlock_driver(adapter); 1538 } 1539 1540 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter) 1541 { 1542 QLCWR32(adapter, QLC_83XX_RESET_REG, 0); 1543 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0); 1544 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0); 1545 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0); 1546 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0); 1547 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0); 1548 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0); 1549 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0); 1550 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1); 1551 } 1552 1553 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) 1554 { 1555 u32 heartbeat, peg_status; 1556 int retries, ret = -EIO, err = 0; 1557 1558 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT; 1559 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev, 1560 QLCNIC_PEG_ALIVE_COUNTER); 1561 1562 do { 1563 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS); 1564 heartbeat = QLC_SHARED_REG_RD32(p_dev, 1565 QLCNIC_PEG_ALIVE_COUNTER); 1566 if (heartbeat != p_dev->heartbeat) { 1567 ret = QLCNIC_RCODE_SUCCESS; 1568 break; 1569 } 1570 } while (--retries); 1571 1572 if (ret) { 1573 dev_err(&p_dev->pdev->dev, "firmware hang detected\n"); 1574 qlcnic_83xx_take_eport_out_of_reset(p_dev); 1575 qlcnic_83xx_disable_pause_frames(p_dev); 1576 peg_status = QLC_SHARED_REG_RD32(p_dev, 1577 QLCNIC_PEG_HALT_STATUS1); 1578 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n" 1579 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" 1580 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n" 1581 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" 1582 "PEG_NET_4_PC: 0x%x\n", peg_status, 1583 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2), 1584 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err), 1585 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err), 1586 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err), 1587 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err), 1588 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err)); 1589 1590 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) 1591 dev_err(&p_dev->pdev->dev, 1592 "Device is being reset err code 0x00006700.\n"); 1593 } 1594 1595 return ret; 1596 } 1597 1598 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev) 1599 { 1600 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT; 1601 u32 val; 1602 1603 do { 1604 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE); 1605 if (val == QLC_83XX_CMDPEG_COMPLETE) 1606 return 0; 1607 msleep(QLCNIC_CMDPEG_CHECK_DELAY); 1608 } while (--retries); 1609 1610 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val); 1611 return -EIO; 1612 } 1613 1614 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev) 1615 { 1616 int err; 1617 1618 err = qlcnic_83xx_check_cmd_peg_status(p_dev); 1619 if (err) 1620 return err; 1621 1622 err = qlcnic_83xx_check_heartbeat(p_dev); 1623 if (err) 1624 return err; 1625 1626 return err; 1627 } 1628 1629 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr, 1630 int duration, u32 mask, u32 status) 1631 { 1632 int timeout_error, err = 0; 1633 u32 value; 1634 u8 retries; 1635 1636 value = QLCRD32(p_dev, addr, &err); 1637 if (err == -EIO) 1638 return err; 1639 retries = duration / 10; 1640 1641 do { 1642 if ((value & mask) != status) { 1643 timeout_error = 1; 1644 msleep(duration / 10); 1645 value = QLCRD32(p_dev, addr, &err); 1646 if (err == -EIO) 1647 return err; 1648 } else { 1649 timeout_error = 0; 1650 break; 1651 } 1652 } while (retries--); 1653 1654 if (timeout_error) { 1655 p_dev->ahw->reset.seq_error++; 1656 dev_err(&p_dev->pdev->dev, 1657 "%s: Timeout Err, entry_num = %d\n", 1658 __func__, p_dev->ahw->reset.seq_index); 1659 dev_err(&p_dev->pdev->dev, 1660 "0x%08x 0x%08x 0x%08x\n", 1661 value, mask, status); 1662 } 1663 1664 return timeout_error; 1665 } 1666 1667 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev) 1668 { 1669 u32 sum = 0; 1670 u16 *buff = (u16 *)p_dev->ahw->reset.buff; 1671 int count = p_dev->ahw->reset.hdr->size / sizeof(u16); 1672 1673 while (count-- > 0) 1674 sum += *buff++; 1675 1676 while (sum >> 16) 1677 sum = (sum & 0xFFFF) + (sum >> 16); 1678 1679 if (~sum) { 1680 return 0; 1681 } else { 1682 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1683 return -1; 1684 } 1685 } 1686 1687 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev) 1688 { 1689 struct qlcnic_hardware_context *ahw = p_dev->ahw; 1690 u32 addr, count, prev_ver, curr_ver; 1691 u8 *p_buff; 1692 1693 if (ahw->reset.buff != NULL) { 1694 prev_ver = p_dev->fw_version; 1695 curr_ver = qlcnic_83xx_get_fw_version(p_dev); 1696 if (curr_ver > prev_ver) 1697 kfree(ahw->reset.buff); 1698 else 1699 return 0; 1700 } 1701 1702 ahw->reset.seq_error = 0; 1703 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL); 1704 if (ahw->reset.buff == NULL) 1705 return -ENOMEM; 1706 1707 p_buff = p_dev->ahw->reset.buff; 1708 addr = QLC_83XX_RESET_TEMPLATE_ADDR; 1709 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32); 1710 1711 /* Copy template header from flash */ 1712 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1713 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1714 return -EIO; 1715 } 1716 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff; 1717 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size; 1718 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1719 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32); 1720 1721 /* Copy rest of the template */ 1722 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1723 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1724 return -EIO; 1725 } 1726 1727 if (qlcnic_83xx_reset_template_checksum(p_dev)) 1728 return -EIO; 1729 /* Get Stop, Start and Init command offsets */ 1730 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset; 1731 ahw->reset.start_offset = ahw->reset.buff + 1732 ahw->reset.hdr->start_offset; 1733 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1734 return 0; 1735 } 1736 1737 /* Read Write HW register command */ 1738 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev, 1739 u32 raddr, u32 waddr) 1740 { 1741 int err = 0; 1742 u32 value; 1743 1744 value = QLCRD32(p_dev, raddr, &err); 1745 if (err == -EIO) 1746 return; 1747 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1748 } 1749 1750 /* Read Modify Write HW register command */ 1751 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev, 1752 u32 raddr, u32 waddr, 1753 struct qlc_83xx_rmw *p_rmw_hdr) 1754 { 1755 int err = 0; 1756 u32 value; 1757 1758 if (p_rmw_hdr->index_a) { 1759 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; 1760 } else { 1761 value = QLCRD32(p_dev, raddr, &err); 1762 if (err == -EIO) 1763 return; 1764 } 1765 1766 value &= p_rmw_hdr->mask; 1767 value <<= p_rmw_hdr->shl; 1768 value >>= p_rmw_hdr->shr; 1769 value |= p_rmw_hdr->or_value; 1770 value ^= p_rmw_hdr->xor_value; 1771 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1772 } 1773 1774 /* Write HW register command */ 1775 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev, 1776 struct qlc_83xx_entry_hdr *p_hdr) 1777 { 1778 int i; 1779 struct qlc_83xx_entry *entry; 1780 1781 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1782 sizeof(struct qlc_83xx_entry_hdr)); 1783 1784 for (i = 0; i < p_hdr->count; i++, entry++) { 1785 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1, 1786 entry->arg2); 1787 if (p_hdr->delay) 1788 udelay((u32)(p_hdr->delay)); 1789 } 1790 } 1791 1792 /* Read and Write instruction */ 1793 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev, 1794 struct qlc_83xx_entry_hdr *p_hdr) 1795 { 1796 int i; 1797 struct qlc_83xx_entry *entry; 1798 1799 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1800 sizeof(struct qlc_83xx_entry_hdr)); 1801 1802 for (i = 0; i < p_hdr->count; i++, entry++) { 1803 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1, 1804 entry->arg2); 1805 if (p_hdr->delay) 1806 udelay((u32)(p_hdr->delay)); 1807 } 1808 } 1809 1810 /* Poll HW register command */ 1811 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, 1812 struct qlc_83xx_entry_hdr *p_hdr) 1813 { 1814 long delay; 1815 struct qlc_83xx_entry *entry; 1816 struct qlc_83xx_poll *poll; 1817 int i, err = 0; 1818 unsigned long arg1, arg2; 1819 1820 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1821 sizeof(struct qlc_83xx_entry_hdr)); 1822 1823 entry = (struct qlc_83xx_entry *)((char *)poll + 1824 sizeof(struct qlc_83xx_poll)); 1825 delay = (long)p_hdr->delay; 1826 1827 if (!delay) { 1828 for (i = 0; i < p_hdr->count; i++, entry++) 1829 qlcnic_83xx_poll_reg(p_dev, entry->arg1, 1830 delay, poll->mask, 1831 poll->status); 1832 } else { 1833 for (i = 0; i < p_hdr->count; i++, entry++) { 1834 arg1 = entry->arg1; 1835 arg2 = entry->arg2; 1836 if (delay) { 1837 if (qlcnic_83xx_poll_reg(p_dev, 1838 arg1, delay, 1839 poll->mask, 1840 poll->status)){ 1841 QLCRD32(p_dev, arg1, &err); 1842 if (err == -EIO) 1843 return; 1844 QLCRD32(p_dev, arg2, &err); 1845 if (err == -EIO) 1846 return; 1847 } 1848 } 1849 } 1850 } 1851 } 1852 1853 /* Poll and write HW register command */ 1854 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev, 1855 struct qlc_83xx_entry_hdr *p_hdr) 1856 { 1857 int i; 1858 long delay; 1859 struct qlc_83xx_quad_entry *entry; 1860 struct qlc_83xx_poll *poll; 1861 1862 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1863 sizeof(struct qlc_83xx_entry_hdr)); 1864 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1865 sizeof(struct qlc_83xx_poll)); 1866 delay = (long)p_hdr->delay; 1867 1868 for (i = 0; i < p_hdr->count; i++, entry++) { 1869 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr, 1870 entry->dr_value); 1871 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1872 entry->ar_value); 1873 if (delay) 1874 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1875 poll->mask, poll->status); 1876 } 1877 } 1878 1879 /* Read Modify Write register command */ 1880 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev, 1881 struct qlc_83xx_entry_hdr *p_hdr) 1882 { 1883 int i; 1884 struct qlc_83xx_entry *entry; 1885 struct qlc_83xx_rmw *rmw_hdr; 1886 1887 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr + 1888 sizeof(struct qlc_83xx_entry_hdr)); 1889 1890 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr + 1891 sizeof(struct qlc_83xx_rmw)); 1892 1893 for (i = 0; i < p_hdr->count; i++, entry++) { 1894 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1, 1895 entry->arg2, rmw_hdr); 1896 if (p_hdr->delay) 1897 udelay((u32)(p_hdr->delay)); 1898 } 1899 } 1900 1901 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr) 1902 { 1903 if (p_hdr->delay) 1904 mdelay((u32)((long)p_hdr->delay)); 1905 } 1906 1907 /* Read and poll register command */ 1908 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, 1909 struct qlc_83xx_entry_hdr *p_hdr) 1910 { 1911 long delay; 1912 int index, i, j, err; 1913 struct qlc_83xx_quad_entry *entry; 1914 struct qlc_83xx_poll *poll; 1915 unsigned long addr; 1916 1917 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1918 sizeof(struct qlc_83xx_entry_hdr)); 1919 1920 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1921 sizeof(struct qlc_83xx_poll)); 1922 delay = (long)p_hdr->delay; 1923 1924 for (i = 0; i < p_hdr->count; i++, entry++) { 1925 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1926 entry->ar_value); 1927 if (delay) { 1928 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1929 poll->mask, poll->status)){ 1930 index = p_dev->ahw->reset.array_index; 1931 addr = entry->dr_addr; 1932 j = QLCRD32(p_dev, addr, &err); 1933 if (err == -EIO) 1934 return; 1935 1936 p_dev->ahw->reset.array[index++] = j; 1937 1938 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES) 1939 p_dev->ahw->reset.array_index = 1; 1940 } 1941 } 1942 } 1943 } 1944 1945 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev) 1946 { 1947 p_dev->ahw->reset.seq_end = 1; 1948 } 1949 1950 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev) 1951 { 1952 p_dev->ahw->reset.template_end = 1; 1953 if (p_dev->ahw->reset.seq_error == 0) 1954 dev_err(&p_dev->pdev->dev, 1955 "HW restart process completed successfully.\n"); 1956 else 1957 dev_err(&p_dev->pdev->dev, 1958 "HW restart completed with timeout errors.\n"); 1959 } 1960 1961 /** 1962 * qlcnic_83xx_exec_template_cmd 1963 * 1964 * @p_dev: adapter structure 1965 * @p_buff: Poiter to instruction template 1966 * 1967 * Template provides instructions to stop, restart and initalize firmware. 1968 * These instructions are abstracted as a series of read, write and 1969 * poll operations on hardware registers. Register information and operation 1970 * specifics are not exposed to the driver. Driver reads the template from 1971 * flash and executes the instructions located at pre-defined offsets. 1972 * 1973 * Returns: None 1974 * */ 1975 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev, 1976 char *p_buff) 1977 { 1978 int index, entries; 1979 struct qlc_83xx_entry_hdr *p_hdr; 1980 char *entry = p_buff; 1981 1982 p_dev->ahw->reset.seq_end = 0; 1983 p_dev->ahw->reset.template_end = 0; 1984 entries = p_dev->ahw->reset.hdr->entries; 1985 index = p_dev->ahw->reset.seq_index; 1986 1987 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) { 1988 p_hdr = (struct qlc_83xx_entry_hdr *)entry; 1989 1990 switch (p_hdr->cmd) { 1991 case QLC_83XX_OPCODE_NOP: 1992 break; 1993 case QLC_83XX_OPCODE_WRITE_LIST: 1994 qlcnic_83xx_write_list(p_dev, p_hdr); 1995 break; 1996 case QLC_83XX_OPCODE_READ_WRITE_LIST: 1997 qlcnic_83xx_read_write_list(p_dev, p_hdr); 1998 break; 1999 case QLC_83XX_OPCODE_POLL_LIST: 2000 qlcnic_83xx_poll_list(p_dev, p_hdr); 2001 break; 2002 case QLC_83XX_OPCODE_POLL_WRITE_LIST: 2003 qlcnic_83xx_poll_write_list(p_dev, p_hdr); 2004 break; 2005 case QLC_83XX_OPCODE_READ_MODIFY_WRITE: 2006 qlcnic_83xx_read_modify_write(p_dev, p_hdr); 2007 break; 2008 case QLC_83XX_OPCODE_SEQ_PAUSE: 2009 qlcnic_83xx_pause(p_hdr); 2010 break; 2011 case QLC_83XX_OPCODE_SEQ_END: 2012 qlcnic_83xx_seq_end(p_dev); 2013 break; 2014 case QLC_83XX_OPCODE_TMPL_END: 2015 qlcnic_83xx_template_end(p_dev); 2016 break; 2017 case QLC_83XX_OPCODE_POLL_READ_LIST: 2018 qlcnic_83xx_poll_read_list(p_dev, p_hdr); 2019 break; 2020 default: 2021 dev_err(&p_dev->pdev->dev, 2022 "%s: Unknown opcode 0x%04x in template %d\n", 2023 __func__, p_hdr->cmd, index); 2024 break; 2025 } 2026 entry += p_hdr->size; 2027 cond_resched(); 2028 } 2029 p_dev->ahw->reset.seq_index = index; 2030 } 2031 2032 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev) 2033 { 2034 p_dev->ahw->reset.seq_index = 0; 2035 2036 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset); 2037 if (p_dev->ahw->reset.seq_end != 1) 2038 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 2039 } 2040 2041 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev) 2042 { 2043 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset); 2044 if (p_dev->ahw->reset.template_end != 1) 2045 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 2046 } 2047 2048 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev) 2049 { 2050 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset); 2051 if (p_dev->ahw->reset.seq_end != 1) 2052 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 2053 } 2054 2055 /* POST FW related definations*/ 2056 #define QLC_83XX_POST_SIGNATURE_REG 0x41602014 2057 #define QLC_83XX_POST_MODE_REG 0x41602018 2058 #define QLC_83XX_POST_FAST_MODE 0 2059 #define QLC_83XX_POST_MEDIUM_MODE 1 2060 #define QLC_83XX_POST_SLOW_MODE 2 2061 2062 /* POST Timeout values in milliseconds */ 2063 #define QLC_83XX_POST_FAST_MODE_TIMEOUT 690 2064 #define QLC_83XX_POST_MED_MODE_TIMEOUT 2930 2065 #define QLC_83XX_POST_SLOW_MODE_TIMEOUT 7500 2066 2067 /* POST result values */ 2068 #define QLC_83XX_POST_PASS 0xfffffff0 2069 #define QLC_83XX_POST_ASIC_STRESS_TEST_FAIL 0xffffffff 2070 #define QLC_83XX_POST_DDR_TEST_FAIL 0xfffffffe 2071 #define QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL 0xfffffffc 2072 #define QLC_83XX_POST_FLASH_TEST_FAIL 0xfffffff8 2073 2074 static int qlcnic_83xx_run_post(struct qlcnic_adapter *adapter) 2075 { 2076 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 2077 struct device *dev = &adapter->pdev->dev; 2078 int timeout, count, ret = 0; 2079 u32 signature; 2080 2081 /* Set timeout values with extra 2 seconds of buffer */ 2082 switch (adapter->ahw->post_mode) { 2083 case QLC_83XX_POST_FAST_MODE: 2084 timeout = QLC_83XX_POST_FAST_MODE_TIMEOUT + 2000; 2085 break; 2086 case QLC_83XX_POST_MEDIUM_MODE: 2087 timeout = QLC_83XX_POST_MED_MODE_TIMEOUT + 2000; 2088 break; 2089 case QLC_83XX_POST_SLOW_MODE: 2090 timeout = QLC_83XX_POST_SLOW_MODE_TIMEOUT + 2000; 2091 break; 2092 default: 2093 return -EINVAL; 2094 } 2095 2096 strncpy(fw_info->fw_file_name, QLC_83XX_POST_FW_FILE_NAME, 2097 QLC_FW_FILE_NAME_LEN); 2098 2099 ret = request_firmware(&fw_info->fw, fw_info->fw_file_name, dev); 2100 if (ret) { 2101 dev_err(dev, "POST firmware can not be loaded, skipping POST\n"); 2102 return 0; 2103 } 2104 2105 ret = qlcnic_83xx_copy_fw_file(adapter); 2106 if (ret) 2107 return ret; 2108 2109 /* clear QLC_83XX_POST_SIGNATURE_REG register */ 2110 qlcnic_ind_wr(adapter, QLC_83XX_POST_SIGNATURE_REG, 0); 2111 2112 /* Set POST mode */ 2113 qlcnic_ind_wr(adapter, QLC_83XX_POST_MODE_REG, 2114 adapter->ahw->post_mode); 2115 2116 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 2117 QLC_83XX_BOOT_FROM_FILE); 2118 2119 qlcnic_83xx_start_hw(adapter); 2120 2121 count = 0; 2122 do { 2123 msleep(100); 2124 count += 100; 2125 2126 signature = qlcnic_ind_rd(adapter, QLC_83XX_POST_SIGNATURE_REG); 2127 if (signature == QLC_83XX_POST_PASS) 2128 break; 2129 } while (timeout > count); 2130 2131 if (timeout <= count) { 2132 dev_err(dev, "POST timed out, signature = 0x%08x\n", signature); 2133 return -EIO; 2134 } 2135 2136 switch (signature) { 2137 case QLC_83XX_POST_PASS: 2138 dev_info(dev, "POST passed, Signature = 0x%08x\n", signature); 2139 break; 2140 case QLC_83XX_POST_ASIC_STRESS_TEST_FAIL: 2141 dev_err(dev, "POST failed, Test case : ASIC STRESS TEST, Signature = 0x%08x\n", 2142 signature); 2143 ret = -EIO; 2144 break; 2145 case QLC_83XX_POST_DDR_TEST_FAIL: 2146 dev_err(dev, "POST failed, Test case : DDT TEST, Signature = 0x%08x\n", 2147 signature); 2148 ret = -EIO; 2149 break; 2150 case QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL: 2151 dev_err(dev, "POST failed, Test case : ASIC MEMORY TEST, Signature = 0x%08x\n", 2152 signature); 2153 ret = -EIO; 2154 break; 2155 case QLC_83XX_POST_FLASH_TEST_FAIL: 2156 dev_err(dev, "POST failed, Test case : FLASH TEST, Signature = 0x%08x\n", 2157 signature); 2158 ret = -EIO; 2159 break; 2160 default: 2161 dev_err(dev, "POST failed, Test case : INVALID, Signature = 0x%08x\n", 2162 signature); 2163 ret = -EIO; 2164 break; 2165 } 2166 2167 return ret; 2168 } 2169 2170 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter) 2171 { 2172 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 2173 int err = -EIO; 2174 2175 if (request_firmware(&fw_info->fw, fw_info->fw_file_name, 2176 &(adapter->pdev->dev))) { 2177 dev_err(&adapter->pdev->dev, 2178 "No file FW image, loading flash FW image.\n"); 2179 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 2180 QLC_83XX_BOOT_FROM_FLASH); 2181 } else { 2182 if (qlcnic_83xx_copy_fw_file(adapter)) 2183 return err; 2184 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 2185 QLC_83XX_BOOT_FROM_FILE); 2186 } 2187 2188 return 0; 2189 } 2190 2191 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter) 2192 { 2193 u32 val; 2194 int err = -EIO; 2195 2196 qlcnic_83xx_stop_hw(adapter); 2197 2198 /* Collect FW register dump if required */ 2199 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 2200 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET)) 2201 qlcnic_dump_fw(adapter); 2202 2203 if (val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) { 2204 netdev_info(adapter->netdev, "%s: Auto firmware recovery is disabled\n", 2205 __func__); 2206 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 2207 return err; 2208 } 2209 2210 qlcnic_83xx_init_hw(adapter); 2211 2212 if (qlcnic_83xx_copy_bootloader(adapter)) 2213 return err; 2214 2215 /* Check if POST needs to be run */ 2216 if (adapter->ahw->run_post) { 2217 err = qlcnic_83xx_run_post(adapter); 2218 if (err) 2219 return err; 2220 2221 /* No need to run POST in next reset sequence */ 2222 adapter->ahw->run_post = false; 2223 2224 /* Again reset the adapter to load regular firmware */ 2225 qlcnic_83xx_stop_hw(adapter); 2226 qlcnic_83xx_init_hw(adapter); 2227 2228 err = qlcnic_83xx_copy_bootloader(adapter); 2229 if (err) 2230 return err; 2231 } 2232 2233 /* Boot either flash image or firmware image from host file system */ 2234 if (qlcnic_load_fw_file == 1) { 2235 if (qlcnic_83xx_load_fw_image_from_host(adapter)) 2236 return err; 2237 } else { 2238 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 2239 QLC_83XX_BOOT_FROM_FLASH); 2240 } 2241 2242 qlcnic_83xx_start_hw(adapter); 2243 if (qlcnic_83xx_check_hw_status(adapter)) 2244 return -EIO; 2245 2246 return 0; 2247 } 2248 2249 static int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter) 2250 { 2251 int err; 2252 struct qlcnic_info nic_info; 2253 struct qlcnic_hardware_context *ahw = adapter->ahw; 2254 2255 memset(&nic_info, 0, sizeof(struct qlcnic_info)); 2256 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func); 2257 if (err) 2258 return -EIO; 2259 2260 ahw->physical_port = (u8) nic_info.phys_port; 2261 ahw->switch_mode = nic_info.switch_mode; 2262 ahw->max_tx_ques = nic_info.max_tx_ques; 2263 ahw->max_rx_ques = nic_info.max_rx_ques; 2264 ahw->capabilities = nic_info.capabilities; 2265 ahw->max_mac_filters = nic_info.max_mac_filters; 2266 ahw->max_mtu = nic_info.max_mtu; 2267 2268 /* eSwitch capability indicates vNIC mode. 2269 * vNIC and SRIOV are mutually exclusive operational modes. 2270 * If SR-IOV capability is detected, SR-IOV physical function 2271 * will get initialized in default mode. 2272 * SR-IOV virtual function initialization follows a 2273 * different code path and opmode. 2274 * SRIOV mode has precedence over vNIC mode. 2275 */ 2276 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) 2277 return QLC_83XX_DEFAULT_OPMODE; 2278 2279 if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY) 2280 return QLCNIC_VNIC_MODE; 2281 2282 return QLC_83XX_DEFAULT_OPMODE; 2283 } 2284 2285 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter) 2286 { 2287 struct qlcnic_hardware_context *ahw = adapter->ahw; 2288 u16 max_sds_rings, max_tx_rings; 2289 int ret; 2290 2291 ret = qlcnic_83xx_get_nic_configuration(adapter); 2292 if (ret == -EIO) 2293 return -EIO; 2294 2295 if (ret == QLCNIC_VNIC_MODE) { 2296 ahw->nic_mode = QLCNIC_VNIC_MODE; 2297 2298 if (qlcnic_83xx_config_vnic_opmode(adapter)) 2299 return -EIO; 2300 2301 max_sds_rings = QLCNIC_MAX_VNIC_SDS_RINGS; 2302 max_tx_rings = QLCNIC_MAX_VNIC_TX_RINGS; 2303 } else if (ret == QLC_83XX_DEFAULT_OPMODE) { 2304 ahw->nic_mode = QLCNIC_DEFAULT_MODE; 2305 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver; 2306 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; 2307 max_sds_rings = QLCNIC_MAX_SDS_RINGS; 2308 max_tx_rings = QLCNIC_MAX_TX_RINGS; 2309 } else { 2310 dev_err(&adapter->pdev->dev, "%s: Invalid opmode %d\n", 2311 __func__, ret); 2312 return -EIO; 2313 } 2314 2315 adapter->max_sds_rings = min(ahw->max_rx_ques, max_sds_rings); 2316 adapter->max_tx_rings = min(ahw->max_tx_ques, max_tx_rings); 2317 2318 return 0; 2319 } 2320 2321 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter) 2322 { 2323 struct qlcnic_hardware_context *ahw = adapter->ahw; 2324 2325 if (ahw->port_type == QLCNIC_XGBE) { 2326 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G; 2327 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G; 2328 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2329 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2330 2331 } else if (ahw->port_type == QLCNIC_GBE) { 2332 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G; 2333 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2334 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2335 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G; 2336 } 2337 adapter->num_txd = MAX_CMD_DESCRIPTORS; 2338 adapter->max_rds_rings = MAX_RDS_RINGS; 2339 } 2340 2341 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter) 2342 { 2343 int err = -EIO; 2344 2345 qlcnic_83xx_get_minidump_template(adapter); 2346 if (qlcnic_83xx_get_port_info(adapter)) 2347 return err; 2348 2349 qlcnic_83xx_config_buff_descriptors(adapter); 2350 adapter->ahw->msix_supported = !!qlcnic_use_msi_x; 2351 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED; 2352 2353 dev_info(&adapter->pdev->dev, "HAL Version: %d\n", 2354 adapter->ahw->fw_hal_version); 2355 2356 return 0; 2357 } 2358 2359 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1)) 2360 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter) 2361 { 2362 struct qlcnic_cmd_args cmd; 2363 u32 presence_mask, audit_mask; 2364 int status; 2365 2366 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 2367 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 2368 2369 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) { 2370 status = qlcnic_alloc_mbx_args(&cmd, adapter, 2371 QLCNIC_CMD_STOP_NIC_FUNC); 2372 if (status) 2373 return; 2374 2375 cmd.req.arg[1] = BIT_31; 2376 status = qlcnic_issue_cmd(adapter, &cmd); 2377 if (status) 2378 dev_err(&adapter->pdev->dev, 2379 "Failed to clean up the function resources\n"); 2380 qlcnic_free_mbx_args(&cmd); 2381 } 2382 } 2383 2384 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter) 2385 { 2386 struct qlcnic_hardware_context *ahw = adapter->ahw; 2387 struct pci_dev *pdev = adapter->pdev; 2388 struct qlc_83xx_fw_info *fw_info; 2389 int err = 0; 2390 2391 ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL); 2392 if (!ahw->fw_info) { 2393 err = -ENOMEM; 2394 } else { 2395 fw_info = ahw->fw_info; 2396 switch (pdev->device) { 2397 case PCI_DEVICE_ID_QLOGIC_QLE834X: 2398 case PCI_DEVICE_ID_QLOGIC_QLE8830: 2399 strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME, 2400 QLC_FW_FILE_NAME_LEN); 2401 break; 2402 case PCI_DEVICE_ID_QLOGIC_QLE844X: 2403 strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME, 2404 QLC_FW_FILE_NAME_LEN); 2405 break; 2406 default: 2407 dev_err(&pdev->dev, "%s: Invalid device id\n", 2408 __func__); 2409 err = -EINVAL; 2410 break; 2411 } 2412 } 2413 2414 return err; 2415 } 2416 2417 static void qlcnic_83xx_init_rings(struct qlcnic_adapter *adapter) 2418 { 2419 u8 rx_cnt = QLCNIC_DEF_SDS_RINGS; 2420 u8 tx_cnt = QLCNIC_DEF_TX_RINGS; 2421 2422 adapter->max_tx_rings = QLCNIC_MAX_TX_RINGS; 2423 adapter->max_sds_rings = QLCNIC_MAX_SDS_RINGS; 2424 2425 if (!adapter->ahw->msix_supported) { 2426 rx_cnt = QLCNIC_SINGLE_RING; 2427 tx_cnt = QLCNIC_SINGLE_RING; 2428 } 2429 2430 /* compute and set drv sds rings */ 2431 qlcnic_set_tx_ring_count(adapter, tx_cnt); 2432 qlcnic_set_sds_ring_count(adapter, rx_cnt); 2433 } 2434 2435 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac) 2436 { 2437 struct qlcnic_hardware_context *ahw = adapter->ahw; 2438 int err = 0; 2439 2440 adapter->rx_mac_learn = false; 2441 ahw->msix_supported = !!qlcnic_use_msi_x; 2442 2443 /* Check if POST needs to be run */ 2444 switch (qlcnic_load_fw_file) { 2445 case 2: 2446 ahw->post_mode = QLC_83XX_POST_FAST_MODE; 2447 ahw->run_post = true; 2448 break; 2449 case 3: 2450 ahw->post_mode = QLC_83XX_POST_MEDIUM_MODE; 2451 ahw->run_post = true; 2452 break; 2453 case 4: 2454 ahw->post_mode = QLC_83XX_POST_SLOW_MODE; 2455 ahw->run_post = true; 2456 break; 2457 default: 2458 ahw->run_post = false; 2459 break; 2460 } 2461 2462 qlcnic_83xx_init_rings(adapter); 2463 2464 err = qlcnic_83xx_init_mailbox_work(adapter); 2465 if (err) 2466 goto exit; 2467 2468 if (qlcnic_sriov_vf_check(adapter)) { 2469 err = qlcnic_sriov_vf_init(adapter, pci_using_dac); 2470 if (err) 2471 goto detach_mbx; 2472 else 2473 return err; 2474 } 2475 2476 if (qlcnic_83xx_read_flash_descriptor_table(adapter) || 2477 qlcnic_83xx_read_flash_mfg_id(adapter)) { 2478 dev_err(&adapter->pdev->dev, "Failed reading flash mfg id\n"); 2479 err = -ENOTRECOVERABLE; 2480 goto detach_mbx; 2481 } 2482 2483 err = qlcnic_83xx_check_hw_status(adapter); 2484 if (err) 2485 goto detach_mbx; 2486 2487 err = qlcnic_83xx_get_fw_info(adapter); 2488 if (err) 2489 goto detach_mbx; 2490 2491 err = qlcnic_83xx_idc_init(adapter); 2492 if (err) 2493 goto detach_mbx; 2494 2495 err = qlcnic_setup_intr(adapter); 2496 if (err) { 2497 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n"); 2498 goto disable_intr; 2499 } 2500 2501 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work); 2502 2503 err = qlcnic_83xx_setup_mbx_intr(adapter); 2504 if (err) 2505 goto disable_mbx_intr; 2506 2507 qlcnic_83xx_clear_function_resources(adapter); 2508 qlcnic_dcb_enable(adapter->dcb); 2509 qlcnic_83xx_initialize_nic(adapter, 1); 2510 qlcnic_dcb_get_info(adapter->dcb); 2511 2512 /* Configure default, SR-IOV or Virtual NIC mode of operation */ 2513 err = qlcnic_83xx_configure_opmode(adapter); 2514 if (err) 2515 goto disable_mbx_intr; 2516 2517 2518 /* Perform operating mode specific initialization */ 2519 err = adapter->nic_ops->init_driver(adapter); 2520 if (err) 2521 goto disable_mbx_intr; 2522 2523 /* Periodically monitor device status */ 2524 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work); 2525 return 0; 2526 2527 disable_mbx_intr: 2528 qlcnic_83xx_free_mbx_intr(adapter); 2529 2530 disable_intr: 2531 qlcnic_teardown_intr(adapter); 2532 2533 detach_mbx: 2534 qlcnic_83xx_detach_mailbox_work(adapter); 2535 qlcnic_83xx_free_mailbox(ahw->mailbox); 2536 ahw->mailbox = NULL; 2537 exit: 2538 return err; 2539 } 2540 2541 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter) 2542 { 2543 struct qlcnic_hardware_context *ahw = adapter->ahw; 2544 struct qlc_83xx_idc *idc = &ahw->idc; 2545 2546 clear_bit(QLC_83XX_MBX_READY, &idc->status); 2547 cancel_delayed_work_sync(&adapter->fw_work); 2548 2549 if (ahw->nic_mode == QLCNIC_VNIC_MODE) 2550 qlcnic_83xx_disable_vnic_mode(adapter, 1); 2551 2552 qlcnic_83xx_idc_detach_driver(adapter); 2553 qlcnic_83xx_initialize_nic(adapter, 0); 2554 2555 cancel_delayed_work_sync(&adapter->idc_aen_work); 2556 } 2557 2558 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter) 2559 { 2560 struct qlcnic_hardware_context *ahw = adapter->ahw; 2561 struct qlc_83xx_idc *idc = &ahw->idc; 2562 int ret = 0; 2563 u32 owner; 2564 2565 /* Mark the previous IDC state as NEED_RESET so 2566 * that state_entry() will perform the reattachment 2567 * and bringup the device 2568 */ 2569 idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET; 2570 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2571 if (ahw->pci_func == owner) { 2572 ret = qlcnic_83xx_restart_hw(adapter); 2573 if (ret < 0) 2574 return ret; 2575 qlcnic_83xx_idc_clear_registers(adapter, 0); 2576 } 2577 2578 ret = idc->state_entry(adapter); 2579 return ret; 2580 } 2581 2582 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter) 2583 { 2584 struct qlcnic_hardware_context *ahw = adapter->ahw; 2585 struct qlc_83xx_idc *idc = &ahw->idc; 2586 u32 owner; 2587 2588 idc->prev_state = QLC_83XX_IDC_DEV_READY; 2589 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2590 if (ahw->pci_func == owner) 2591 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 2592 2593 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0); 2594 } 2595