1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #include "qlcnic_sriov.h" 9 #include "qlcnic.h" 10 #include "qlcnic_hw.h" 11 12 /* Reset template definitions */ 13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000 14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000 15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101 16 17 #define QLC_83XX_OPCODE_NOP 0x0000 18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001 19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002 20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004 21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008 22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010 23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020 24 #define QLC_83XX_OPCODE_SEQ_END 0x0040 25 #define QLC_83XX_OPCODE_TMPL_END 0x0080 26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100 27 28 /* EPORT control registers */ 29 #define QLC_83XX_RESET_CONTROL 0x28084E50 30 #define QLC_83XX_RESET_REG 0x28084E60 31 #define QLC_83XX_RESET_PORT0 0x28084E70 32 #define QLC_83XX_RESET_PORT1 0x28084E80 33 #define QLC_83XX_RESET_PORT2 0x28084E90 34 #define QLC_83XX_RESET_PORT3 0x28084EA0 35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0 36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0 37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0 38 39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter); 40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev); 41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter); 42 43 /* Template header */ 44 struct qlc_83xx_reset_hdr { 45 #if defined(__LITTLE_ENDIAN) 46 u16 version; 47 u16 signature; 48 u16 size; 49 u16 entries; 50 u16 hdr_size; 51 u16 checksum; 52 u16 init_offset; 53 u16 start_offset; 54 #elif defined(__BIG_ENDIAN) 55 u16 signature; 56 u16 version; 57 u16 entries; 58 u16 size; 59 u16 checksum; 60 u16 hdr_size; 61 u16 start_offset; 62 u16 init_offset; 63 #endif 64 } __packed; 65 66 /* Command entry header. */ 67 struct qlc_83xx_entry_hdr { 68 #if defined(__LITTLE_ENDIAN) 69 u16 cmd; 70 u16 size; 71 u16 count; 72 u16 delay; 73 #elif defined(__BIG_ENDIAN) 74 u16 size; 75 u16 cmd; 76 u16 delay; 77 u16 count; 78 #endif 79 } __packed; 80 81 /* Generic poll command */ 82 struct qlc_83xx_poll { 83 u32 mask; 84 u32 status; 85 } __packed; 86 87 /* Read modify write command */ 88 struct qlc_83xx_rmw { 89 u32 mask; 90 u32 xor_value; 91 u32 or_value; 92 #if defined(__LITTLE_ENDIAN) 93 u8 shl; 94 u8 shr; 95 u8 index_a; 96 u8 rsvd; 97 #elif defined(__BIG_ENDIAN) 98 u8 rsvd; 99 u8 index_a; 100 u8 shr; 101 u8 shl; 102 #endif 103 } __packed; 104 105 /* Generic command with 2 DWORD */ 106 struct qlc_83xx_entry { 107 u32 arg1; 108 u32 arg2; 109 } __packed; 110 111 /* Generic command with 4 DWORD */ 112 struct qlc_83xx_quad_entry { 113 u32 dr_addr; 114 u32 dr_value; 115 u32 ar_addr; 116 u32 ar_value; 117 } __packed; 118 static const char *const qlc_83xx_idc_states[] = { 119 "Unknown", 120 "Cold", 121 "Init", 122 "Ready", 123 "Need Reset", 124 "Need Quiesce", 125 "Failed", 126 "Quiesce" 127 }; 128 129 static int 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter) 131 { 132 u32 val; 133 134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 135 if ((val & 0xFFFF)) 136 return 1; 137 else 138 return 0; 139 } 140 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter) 142 { 143 u32 cur, prev; 144 cur = adapter->ahw->idc.curr_state; 145 prev = adapter->ahw->idc.prev_state; 146 147 dev_info(&adapter->pdev->dev, 148 "current state = %s, prev state = %s\n", 149 adapter->ahw->idc.name[cur], 150 adapter->ahw->idc.name[prev]); 151 } 152 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter, 154 u8 mode, int lock) 155 { 156 u32 val; 157 int seconds; 158 159 if (lock) { 160 if (qlcnic_83xx_lock_driver(adapter)) 161 return -EBUSY; 162 } 163 164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 165 val |= (adapter->portnum & 0xf); 166 val |= mode << 7; 167 if (mode) 168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 169 else 170 seconds = jiffies / HZ; 171 172 val |= seconds << 8; 173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val); 174 adapter->ahw->idc.sec_counter = jiffies / HZ; 175 176 if (lock) 177 qlcnic_83xx_unlock_driver(adapter); 178 179 return 0; 180 } 181 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter) 183 { 184 u32 val; 185 186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION); 187 val = val & ~(0x3 << (adapter->portnum * 2)); 188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2)); 189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val); 190 } 191 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter, 193 int lock) 194 { 195 u32 val; 196 197 if (lock) { 198 if (qlcnic_83xx_lock_driver(adapter)) 199 return -EBUSY; 200 } 201 202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 203 val = val & ~0xFF; 204 val = val | QLC_83XX_IDC_MAJOR_VERSION; 205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val); 206 207 if (lock) 208 qlcnic_83xx_unlock_driver(adapter); 209 210 return 0; 211 } 212 213 static int 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter, 215 int status, int lock) 216 { 217 u32 val; 218 219 if (lock) { 220 if (qlcnic_83xx_lock_driver(adapter)) 221 return -EBUSY; 222 } 223 224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 225 226 if (status) 227 val = val | (1 << adapter->portnum); 228 else 229 val = val & ~(1 << adapter->portnum); 230 231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 232 qlcnic_83xx_idc_update_minor_version(adapter); 233 234 if (lock) 235 qlcnic_83xx_unlock_driver(adapter); 236 237 return 0; 238 } 239 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter) 241 { 242 u32 val; 243 u8 version; 244 245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION); 246 version = val & 0xFF; 247 248 if (version != QLC_83XX_IDC_MAJOR_VERSION) { 249 dev_info(&adapter->pdev->dev, 250 "%s:mismatch. version 0x%x, expected version 0x%x\n", 251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION); 252 return -EIO; 253 } 254 255 return 0; 256 } 257 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter, 259 int lock) 260 { 261 u32 val; 262 263 if (lock) { 264 if (qlcnic_83xx_lock_driver(adapter)) 265 return -EBUSY; 266 } 267 268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0); 269 /* Clear gracefull reset bit */ 270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET; 272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 273 274 if (lock) 275 qlcnic_83xx_unlock_driver(adapter); 276 277 return 0; 278 } 279 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter, 281 int flag, int lock) 282 { 283 u32 val; 284 285 if (lock) { 286 if (qlcnic_83xx_lock_driver(adapter)) 287 return -EBUSY; 288 } 289 290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 291 if (flag) 292 val = val | (1 << adapter->portnum); 293 else 294 val = val & ~(1 << adapter->portnum); 295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val); 296 297 if (lock) 298 qlcnic_83xx_unlock_driver(adapter); 299 300 return 0; 301 } 302 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter, 304 int time_limit) 305 { 306 u64 seconds; 307 308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; 309 if (seconds <= time_limit) 310 return 0; 311 else 312 return -EBUSY; 313 } 314 315 /** 316 * qlcnic_83xx_idc_check_reset_ack_reg 317 * 318 * @adapter: adapter structure 319 * 320 * Check ACK wait limit and clear the functions which failed to ACK 321 * 322 * Return 0 if all functions have acknowledged the reset request. 323 **/ 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter) 325 { 326 int timeout; 327 u32 ack, presence, val; 328 329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK); 331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 332 dev_info(&adapter->pdev->dev, 333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence); 334 if (!((ack & presence) == presence)) { 335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) { 336 /* Clear functions which failed to ACK */ 337 dev_info(&adapter->pdev->dev, 338 "%s: ACK wait exceeds time limit\n", __func__); 339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 340 val = val & ~(ack ^ presence); 341 if (qlcnic_83xx_lock_driver(adapter)) 342 return -EBUSY; 343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 344 dev_info(&adapter->pdev->dev, 345 "%s: updated drv presence reg = 0x%x\n", 346 __func__, val); 347 qlcnic_83xx_unlock_driver(adapter); 348 return 0; 349 350 } else { 351 return 1; 352 } 353 } else { 354 dev_info(&adapter->pdev->dev, 355 "%s: Reset ACK received from all functions\n", 356 __func__); 357 return 0; 358 } 359 } 360 361 /** 362 * qlcnic_83xx_idc_tx_soft_reset 363 * 364 * @adapter: adapter structure 365 * 366 * Handle context deletion and recreation request from transmit routine 367 * 368 * Returns -EBUSY or Success (0) 369 * 370 **/ 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter) 372 { 373 struct net_device *netdev = adapter->netdev; 374 375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 376 return -EBUSY; 377 378 netif_device_detach(netdev); 379 qlcnic_down(adapter, netdev); 380 qlcnic_up(adapter, netdev); 381 netif_device_attach(netdev); 382 clear_bit(__QLCNIC_RESETTING, &adapter->state); 383 dev_err(&adapter->pdev->dev, "%s:\n", __func__); 384 385 return 0; 386 } 387 388 /** 389 * qlcnic_83xx_idc_detach_driver 390 * 391 * @adapter: adapter structure 392 * Detach net interface, stop TX and cleanup resources before the HW reset. 393 * Returns: None 394 * 395 **/ 396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter) 397 { 398 int i; 399 struct net_device *netdev = adapter->netdev; 400 401 netif_device_detach(netdev); 402 qlcnic_83xx_detach_mailbox_work(adapter); 403 404 /* Disable mailbox interrupt */ 405 qlcnic_83xx_disable_mbx_intr(adapter); 406 qlcnic_down(adapter, netdev); 407 for (i = 0; i < adapter->ahw->num_msix; i++) { 408 adapter->ahw->intr_tbl[i].id = i; 409 adapter->ahw->intr_tbl[i].enabled = 0; 410 adapter->ahw->intr_tbl[i].src = 0; 411 } 412 413 if (qlcnic_sriov_pf_check(adapter)) 414 qlcnic_sriov_pf_reset(adapter); 415 } 416 417 /** 418 * qlcnic_83xx_idc_attach_driver 419 * 420 * @adapter: adapter structure 421 * 422 * Re-attach and re-enable net interface 423 * Returns: None 424 * 425 **/ 426 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter) 427 { 428 struct net_device *netdev = adapter->netdev; 429 430 if (netif_running(netdev)) { 431 if (qlcnic_up(adapter, netdev)) 432 goto done; 433 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 434 } 435 done: 436 netif_device_attach(netdev); 437 } 438 439 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter, 440 int lock) 441 { 442 if (lock) { 443 if (qlcnic_83xx_lock_driver(adapter)) 444 return -EBUSY; 445 } 446 447 qlcnic_83xx_idc_clear_registers(adapter, 0); 448 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED); 449 if (lock) 450 qlcnic_83xx_unlock_driver(adapter); 451 452 qlcnic_83xx_idc_log_state_history(adapter); 453 dev_info(&adapter->pdev->dev, "Device will enter failed state\n"); 454 455 return 0; 456 } 457 458 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter, 459 int lock) 460 { 461 if (lock) { 462 if (qlcnic_83xx_lock_driver(adapter)) 463 return -EBUSY; 464 } 465 466 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT); 467 468 if (lock) 469 qlcnic_83xx_unlock_driver(adapter); 470 471 return 0; 472 } 473 474 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter, 475 int lock) 476 { 477 if (lock) { 478 if (qlcnic_83xx_lock_driver(adapter)) 479 return -EBUSY; 480 } 481 482 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 483 QLC_83XX_IDC_DEV_NEED_QUISCENT); 484 485 if (lock) 486 qlcnic_83xx_unlock_driver(adapter); 487 488 return 0; 489 } 490 491 static int 492 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock) 493 { 494 if (lock) { 495 if (qlcnic_83xx_lock_driver(adapter)) 496 return -EBUSY; 497 } 498 499 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 500 QLC_83XX_IDC_DEV_NEED_RESET); 501 502 if (lock) 503 qlcnic_83xx_unlock_driver(adapter); 504 505 return 0; 506 } 507 508 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter, 509 int lock) 510 { 511 if (lock) { 512 if (qlcnic_83xx_lock_driver(adapter)) 513 return -EBUSY; 514 } 515 516 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY); 517 if (lock) 518 qlcnic_83xx_unlock_driver(adapter); 519 520 return 0; 521 } 522 523 /** 524 * qlcnic_83xx_idc_find_reset_owner_id 525 * 526 * @adapter: adapter structure 527 * 528 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE. 529 * Within the same class, function with lowest PCI ID assumes ownership 530 * 531 * Returns: reset owner id or failure indication (-EIO) 532 * 533 **/ 534 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter) 535 { 536 u32 reg, reg1, reg2, i, j, owner, class; 537 538 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); 539 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2); 540 owner = QLCNIC_TYPE_NIC; 541 i = 0; 542 j = 0; 543 reg = reg1; 544 545 do { 546 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3); 547 if (class == owner) 548 break; 549 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) { 550 reg = reg2; 551 j = 0; 552 } else { 553 j++; 554 } 555 556 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) { 557 if (owner == QLCNIC_TYPE_NIC) 558 owner = QLCNIC_TYPE_ISCSI; 559 else if (owner == QLCNIC_TYPE_ISCSI) 560 owner = QLCNIC_TYPE_FCOE; 561 else if (owner == QLCNIC_TYPE_FCOE) 562 return -EIO; 563 reg = reg1; 564 j = 0; 565 i = 0; 566 } 567 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS); 568 569 return i; 570 } 571 572 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock) 573 { 574 int ret = 0; 575 576 ret = qlcnic_83xx_restart_hw(adapter); 577 578 if (ret) { 579 qlcnic_83xx_idc_enter_failed_state(adapter, lock); 580 } else { 581 qlcnic_83xx_idc_clear_registers(adapter, lock); 582 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock); 583 } 584 585 return ret; 586 } 587 588 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter) 589 { 590 u32 status; 591 592 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1); 593 594 if (status & QLCNIC_RCODE_FATAL_ERROR) { 595 dev_err(&adapter->pdev->dev, 596 "peg halt status1=0x%x\n", status); 597 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) { 598 dev_err(&adapter->pdev->dev, 599 "On board active cooling fan failed. " 600 "Device has been halted.\n"); 601 dev_err(&adapter->pdev->dev, 602 "Replace the adapter.\n"); 603 return -EIO; 604 } 605 } 606 607 return 0; 608 } 609 610 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter) 611 { 612 int err; 613 614 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox); 615 qlcnic_83xx_enable_mbx_interrupt(adapter); 616 617 /* register for NIC IDC AEN Events */ 618 qlcnic_83xx_register_nic_idc_func(adapter, 1); 619 620 err = qlcnic_sriov_pf_reinit(adapter); 621 if (err) 622 return err; 623 624 qlcnic_83xx_enable_mbx_interrupt(adapter); 625 626 if (qlcnic_83xx_configure_opmode(adapter)) { 627 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 628 return -EIO; 629 } 630 631 if (adapter->nic_ops->init_driver(adapter)) { 632 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 633 return -EIO; 634 } 635 636 if (adapter->portnum == 0) 637 qlcnic_set_drv_version(adapter); 638 639 qlcnic_dcb_get_info(adapter); 640 qlcnic_83xx_idc_attach_driver(adapter); 641 642 return 0; 643 } 644 645 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter) 646 { 647 struct qlcnic_hardware_context *ahw = adapter->ahw; 648 649 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1); 650 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 651 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 652 653 ahw->idc.quiesce_req = 0; 654 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 655 ahw->idc.err_code = 0; 656 ahw->idc.collect_dump = 0; 657 ahw->reset_context = 0; 658 adapter->tx_timeo_cnt = 0; 659 ahw->idc.delay_reset = 0; 660 661 clear_bit(__QLCNIC_RESETTING, &adapter->state); 662 } 663 664 /** 665 * qlcnic_83xx_idc_ready_state_entry 666 * 667 * @adapter: adapter structure 668 * 669 * Perform ready state initialization, this routine will get invoked only 670 * once from READY state. 671 * 672 * Returns: Error code or Success(0) 673 * 674 **/ 675 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter) 676 { 677 struct qlcnic_hardware_context *ahw = adapter->ahw; 678 679 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) { 680 qlcnic_83xx_idc_update_idc_params(adapter); 681 /* Re-attach the device if required */ 682 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || 683 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) { 684 if (qlcnic_83xx_idc_reattach_driver(adapter)) 685 return -EIO; 686 } 687 } 688 689 return 0; 690 } 691 692 /** 693 * qlcnic_83xx_idc_vnic_pf_entry 694 * 695 * @adapter: adapter structure 696 * 697 * Ensure vNIC mode privileged function starts only after vNIC mode is 698 * enabled by management function. 699 * If vNIC mode is ready, start initialization. 700 * 701 * Returns: -EIO or 0 702 * 703 **/ 704 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter) 705 { 706 u32 state; 707 struct qlcnic_hardware_context *ahw = adapter->ahw; 708 709 /* Privileged function waits till mgmt function enables VNIC mode */ 710 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE); 711 if (state != QLCNIC_DEV_NPAR_OPER) { 712 if (!ahw->idc.vnic_wait_limit--) { 713 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 714 return -EIO; 715 } 716 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n"); 717 return -EIO; 718 719 } else { 720 /* Perform one time initialization from ready state */ 721 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) { 722 qlcnic_83xx_idc_update_idc_params(adapter); 723 724 /* If the previous state is UNKNOWN, device will be 725 already attached properly by Init routine*/ 726 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) { 727 if (qlcnic_83xx_idc_reattach_driver(adapter)) 728 return -EIO; 729 } 730 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER; 731 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n"); 732 } 733 } 734 735 return 0; 736 } 737 738 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter) 739 { 740 adapter->ahw->idc.err_code = -EIO; 741 dev_err(&adapter->pdev->dev, 742 "%s: Device in unknown state\n", __func__); 743 return 0; 744 } 745 746 /** 747 * qlcnic_83xx_idc_cold_state 748 * 749 * @adapter: adapter structure 750 * 751 * If HW is up and running device will enter READY state. 752 * If firmware image from host needs to be loaded, device is 753 * forced to start with the file firmware image. 754 * 755 * Returns: Error code or Success(0) 756 * 757 **/ 758 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter) 759 { 760 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0); 761 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0); 762 763 if (qlcnic_load_fw_file) { 764 qlcnic_83xx_idc_restart_hw(adapter, 0); 765 } else { 766 if (qlcnic_83xx_check_hw_status(adapter)) { 767 qlcnic_83xx_idc_enter_failed_state(adapter, 0); 768 return -EIO; 769 } else { 770 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 771 } 772 } 773 return 0; 774 } 775 776 /** 777 * qlcnic_83xx_idc_init_state 778 * 779 * @adapter: adapter structure 780 * 781 * Reset owner will restart the device from this state. 782 * Device will enter failed state if it remains 783 * in this state for more than DEV_INIT time limit. 784 * 785 * Returns: Error code or Success(0) 786 * 787 **/ 788 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter) 789 { 790 int timeout, ret = 0; 791 u32 owner; 792 793 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 794 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) { 795 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 796 if (adapter->ahw->pci_func == owner) 797 ret = qlcnic_83xx_idc_restart_hw(adapter, 1); 798 } else { 799 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout); 800 } 801 802 return ret; 803 } 804 805 /** 806 * qlcnic_83xx_idc_ready_state 807 * 808 * @adapter: adapter structure 809 * 810 * Perform IDC protocol specicifed actions after monitoring device state and 811 * events. 812 * 813 * Returns: Error code or Success(0) 814 * 815 **/ 816 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter) 817 { 818 struct qlcnic_hardware_context *ahw = adapter->ahw; 819 struct qlcnic_mailbox *mbx = ahw->mailbox; 820 int ret = 0; 821 u32 val; 822 823 /* Perform NIC configuration based ready state entry actions */ 824 if (ahw->idc.state_entry(adapter)) 825 return -EIO; 826 827 if (qlcnic_check_temp(adapter)) { 828 if (ahw->temp == QLCNIC_TEMP_PANIC) { 829 qlcnic_83xx_idc_check_fan_failure(adapter); 830 dev_err(&adapter->pdev->dev, 831 "Error: device temperature %d above limits\n", 832 adapter->ahw->temp); 833 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 834 set_bit(__QLCNIC_RESETTING, &adapter->state); 835 qlcnic_83xx_idc_detach_driver(adapter); 836 qlcnic_83xx_idc_enter_failed_state(adapter, 1); 837 return -EIO; 838 } 839 } 840 841 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 842 ret = qlcnic_83xx_check_heartbeat(adapter); 843 if (ret) { 844 adapter->flags |= QLCNIC_FW_HANG; 845 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 846 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 847 set_bit(__QLCNIC_RESETTING, &adapter->state); 848 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 849 } 850 return -EIO; 851 } 852 853 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) { 854 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 855 856 /* Move to need reset state and prepare for reset */ 857 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1); 858 return ret; 859 } 860 861 /* Check for soft reset request */ 862 if (ahw->reset_context && 863 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) { 864 adapter->ahw->reset_context = 0; 865 qlcnic_83xx_idc_tx_soft_reset(adapter); 866 return ret; 867 } 868 869 /* Move to need quiesce state if requested */ 870 if (adapter->ahw->idc.quiesce_req) { 871 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1); 872 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 873 return ret; 874 } 875 876 return ret; 877 } 878 879 /** 880 * qlcnic_83xx_idc_need_reset_state 881 * 882 * @adapter: adapter structure 883 * 884 * Device will remain in this state until: 885 * Reset request ACK's are recieved from all the functions 886 * Wait time exceeds max time limit 887 * 888 * Returns: Error code or Success(0) 889 * 890 **/ 891 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter) 892 { 893 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 894 int ret = 0; 895 896 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) { 897 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 898 set_bit(__QLCNIC_RESETTING, &adapter->state); 899 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 900 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) 901 qlcnic_83xx_disable_vnic_mode(adapter, 1); 902 903 if (qlcnic_check_diag_status(adapter)) { 904 dev_info(&adapter->pdev->dev, 905 "%s: Wait for diag completion\n", __func__); 906 adapter->ahw->idc.delay_reset = 1; 907 return 0; 908 } else { 909 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 910 qlcnic_83xx_idc_detach_driver(adapter); 911 } 912 } 913 914 if (qlcnic_check_diag_status(adapter)) { 915 dev_info(&adapter->pdev->dev, 916 "%s: Wait for diag completion\n", __func__); 917 return -1; 918 } else { 919 if (adapter->ahw->idc.delay_reset) { 920 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1); 921 qlcnic_83xx_idc_detach_driver(adapter); 922 adapter->ahw->idc.delay_reset = 0; 923 } 924 925 /* Check for ACK from other functions */ 926 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter); 927 if (ret) { 928 dev_info(&adapter->pdev->dev, 929 "%s: Waiting for reset ACK\n", __func__); 930 return -1; 931 } 932 } 933 934 /* Transit to INIT state and restart the HW */ 935 qlcnic_83xx_idc_enter_init_state(adapter, 1); 936 937 return ret; 938 } 939 940 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter) 941 { 942 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__); 943 return 0; 944 } 945 946 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter) 947 { 948 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__); 949 clear_bit(__QLCNIC_RESETTING, &adapter->state); 950 adapter->ahw->idc.err_code = -EIO; 951 952 return 0; 953 } 954 955 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter) 956 { 957 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__); 958 return 0; 959 } 960 961 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter, 962 u32 state) 963 { 964 u32 cur, prev, next; 965 966 cur = adapter->ahw->idc.curr_state; 967 prev = adapter->ahw->idc.prev_state; 968 next = state; 969 970 if ((next < QLC_83XX_IDC_DEV_COLD) || 971 (next > QLC_83XX_IDC_DEV_QUISCENT)) { 972 dev_err(&adapter->pdev->dev, 973 "%s: curr %d, prev %d, next state %d is invalid\n", 974 __func__, cur, prev, state); 975 return 1; 976 } 977 978 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) && 979 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) { 980 if ((next != QLC_83XX_IDC_DEV_COLD) && 981 (next != QLC_83XX_IDC_DEV_READY)) { 982 dev_err(&adapter->pdev->dev, 983 "%s: failed, cur %d prev %d next %d\n", 984 __func__, cur, prev, next); 985 return 1; 986 } 987 } 988 989 if (next == QLC_83XX_IDC_DEV_INIT) { 990 if ((prev != QLC_83XX_IDC_DEV_INIT) && 991 (prev != QLC_83XX_IDC_DEV_COLD) && 992 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) { 993 dev_err(&adapter->pdev->dev, 994 "%s: failed, cur %d prev %d next %d\n", 995 __func__, cur, prev, next); 996 return 1; 997 } 998 } 999 1000 return 0; 1001 } 1002 1003 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter) 1004 { 1005 if (adapter->fhash.fnum) 1006 qlcnic_prune_lb_filters(adapter); 1007 } 1008 1009 /** 1010 * qlcnic_83xx_idc_poll_dev_state 1011 * 1012 * @work: kernel work queue structure used to schedule the function 1013 * 1014 * Poll device state periodically and perform state specific 1015 * actions defined by Inter Driver Communication (IDC) protocol. 1016 * 1017 * Returns: None 1018 * 1019 **/ 1020 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work) 1021 { 1022 struct qlcnic_adapter *adapter; 1023 u32 state; 1024 1025 adapter = container_of(work, struct qlcnic_adapter, fw_work.work); 1026 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1027 1028 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1029 qlcnic_83xx_idc_log_state_history(adapter); 1030 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1031 } else { 1032 adapter->ahw->idc.curr_state = state; 1033 } 1034 1035 switch (adapter->ahw->idc.curr_state) { 1036 case QLC_83XX_IDC_DEV_READY: 1037 qlcnic_83xx_idc_ready_state(adapter); 1038 break; 1039 case QLC_83XX_IDC_DEV_NEED_RESET: 1040 qlcnic_83xx_idc_need_reset_state(adapter); 1041 break; 1042 case QLC_83XX_IDC_DEV_NEED_QUISCENT: 1043 qlcnic_83xx_idc_need_quiesce_state(adapter); 1044 break; 1045 case QLC_83XX_IDC_DEV_FAILED: 1046 qlcnic_83xx_idc_failed_state(adapter); 1047 return; 1048 case QLC_83XX_IDC_DEV_INIT: 1049 qlcnic_83xx_idc_init_state(adapter); 1050 break; 1051 case QLC_83XX_IDC_DEV_QUISCENT: 1052 qlcnic_83xx_idc_quiesce_state(adapter); 1053 break; 1054 default: 1055 qlcnic_83xx_idc_unknown_state(adapter); 1056 return; 1057 } 1058 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state; 1059 qlcnic_83xx_periodic_tasks(adapter); 1060 1061 /* Re-schedule the function */ 1062 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status)) 1063 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 1064 adapter->ahw->idc.delay); 1065 } 1066 1067 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter) 1068 { 1069 u32 idc_params, val; 1070 1071 if (qlcnic_83xx_lockless_flash_read32(adapter, 1072 QLC_83XX_IDC_FLASH_PARAM_ADDR, 1073 (u8 *)&idc_params, 1)) { 1074 dev_info(&adapter->pdev->dev, 1075 "%s:failed to get IDC params from flash\n", __func__); 1076 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS; 1077 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS; 1078 } else { 1079 adapter->dev_init_timeo = idc_params & 0xFFFF; 1080 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF); 1081 } 1082 1083 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN; 1084 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN; 1085 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 1086 adapter->ahw->idc.err_code = 0; 1087 adapter->ahw->idc.collect_dump = 0; 1088 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states; 1089 1090 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1091 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1092 1093 /* Check if reset recovery is disabled */ 1094 if (!qlcnic_auto_fw_reset) { 1095 /* Propagate do not reset request to other functions */ 1096 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1097 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1098 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1099 } 1100 } 1101 1102 static int 1103 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter) 1104 { 1105 u32 state, val; 1106 1107 if (qlcnic_83xx_lock_driver(adapter)) 1108 return -EIO; 1109 1110 /* Clear driver lock register */ 1111 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0); 1112 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) { 1113 qlcnic_83xx_unlock_driver(adapter); 1114 return -EIO; 1115 } 1116 1117 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1118 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) { 1119 qlcnic_83xx_unlock_driver(adapter); 1120 return -EIO; 1121 } 1122 1123 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) { 1124 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, 1125 QLC_83XX_IDC_DEV_COLD); 1126 state = QLC_83XX_IDC_DEV_COLD; 1127 } 1128 1129 adapter->ahw->idc.curr_state = state; 1130 /* First to load function should cold boot the device */ 1131 if (state == QLC_83XX_IDC_DEV_COLD) 1132 qlcnic_83xx_idc_cold_state_handler(adapter); 1133 1134 /* Check if reset recovery is enabled */ 1135 if (qlcnic_auto_fw_reset) { 1136 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1137 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY; 1138 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1139 } 1140 1141 qlcnic_83xx_unlock_driver(adapter); 1142 1143 return 0; 1144 } 1145 1146 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter) 1147 { 1148 int ret = -EIO; 1149 1150 qlcnic_83xx_setup_idc_parameters(adapter); 1151 1152 if (qlcnic_83xx_get_reset_instruction_template(adapter)) 1153 return ret; 1154 1155 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) { 1156 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter)) 1157 return -EIO; 1158 } else { 1159 if (qlcnic_83xx_idc_check_major_version(adapter)) 1160 return -EIO; 1161 } 1162 1163 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1); 1164 1165 return 0; 1166 } 1167 1168 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter) 1169 { 1170 int id; 1171 u32 val; 1172 1173 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 1174 usleep_range(10000, 11000); 1175 1176 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1177 id = id & 0xFF; 1178 1179 if (id == adapter->portnum) { 1180 dev_err(&adapter->pdev->dev, 1181 "%s: wait for lock recovery.. %d\n", __func__, id); 1182 msleep(20); 1183 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 1184 id = id & 0xFF; 1185 } 1186 1187 /* Clear driver presence bit */ 1188 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 1189 val = val & ~(1 << adapter->portnum); 1190 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val); 1191 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1192 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1193 1194 cancel_delayed_work_sync(&adapter->fw_work); 1195 } 1196 1197 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key) 1198 { 1199 u32 val; 1200 1201 if (qlcnic_sriov_vf_check(adapter)) 1202 return; 1203 1204 if (qlcnic_83xx_lock_driver(adapter)) { 1205 dev_err(&adapter->pdev->dev, 1206 "%s:failed, please retry\n", __func__); 1207 return; 1208 } 1209 1210 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1211 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) || 1212 !qlcnic_auto_fw_reset) { 1213 dev_err(&adapter->pdev->dev, 1214 "%s:failed, device in non reset mode\n", __func__); 1215 qlcnic_83xx_unlock_driver(adapter); 1216 return; 1217 } 1218 1219 if (key == QLCNIC_FORCE_FW_RESET) { 1220 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1221 val = val | QLC_83XX_IDC_GRACEFULL_RESET; 1222 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val); 1223 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) { 1224 adapter->ahw->idc.collect_dump = 1; 1225 } 1226 1227 qlcnic_83xx_unlock_driver(adapter); 1228 return; 1229 } 1230 1231 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter) 1232 { 1233 u8 *p_cache; 1234 u32 src, size; 1235 u64 dest; 1236 int ret = -EIO; 1237 1238 src = QLC_83XX_BOOTLOADER_FLASH_ADDR; 1239 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR); 1240 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE); 1241 1242 /* alignment check */ 1243 if (size & 0xF) 1244 size = (size + 16) & ~0xF; 1245 1246 p_cache = kzalloc(size, GFP_KERNEL); 1247 if (p_cache == NULL) 1248 return -ENOMEM; 1249 1250 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache, 1251 size / sizeof(u32)); 1252 if (ret) { 1253 kfree(p_cache); 1254 return ret; 1255 } 1256 /* 16 byte write to MS memory */ 1257 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache, 1258 size / 16); 1259 if (ret) { 1260 kfree(p_cache); 1261 return ret; 1262 } 1263 kfree(p_cache); 1264 1265 return ret; 1266 } 1267 1268 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter) 1269 { 1270 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 1271 const struct firmware *fw = fw_info->fw; 1272 u32 dest, *p_cache; 1273 int i, ret = -EIO; 1274 u8 data[16]; 1275 size_t size; 1276 u64 addr; 1277 1278 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR); 1279 size = (fw->size & ~0xF); 1280 p_cache = (u32 *)fw->data; 1281 addr = (u64)dest; 1282 1283 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1284 (u32 *)p_cache, size / 16); 1285 if (ret) { 1286 dev_err(&adapter->pdev->dev, "MS memory write failed\n"); 1287 release_firmware(fw); 1288 fw_info->fw = NULL; 1289 return -EIO; 1290 } 1291 1292 /* alignment check */ 1293 if (fw->size & 0xF) { 1294 addr = dest + size; 1295 for (i = 0; i < (fw->size & 0xF); i++) 1296 data[i] = fw->data[size + i]; 1297 for (; i < 16; i++) 1298 data[i] = 0; 1299 ret = qlcnic_83xx_ms_mem_write128(adapter, addr, 1300 (u32 *)data, 1); 1301 if (ret) { 1302 dev_err(&adapter->pdev->dev, 1303 "MS memory write failed\n"); 1304 release_firmware(fw); 1305 fw_info->fw = NULL; 1306 return -EIO; 1307 } 1308 } 1309 release_firmware(fw); 1310 fw_info->fw = NULL; 1311 1312 return 0; 1313 } 1314 1315 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter) 1316 { 1317 int i, j; 1318 u32 val = 0, val1 = 0, reg = 0; 1319 int err = 0; 1320 1321 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err); 1322 if (err == -EIO) 1323 return; 1324 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val); 1325 1326 for (j = 0; j < 2; j++) { 1327 if (j == 0) { 1328 dev_info(&adapter->pdev->dev, 1329 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:"); 1330 reg = QLC_83XX_PORT0_THRESHOLD; 1331 } else if (j == 1) { 1332 dev_info(&adapter->pdev->dev, 1333 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:"); 1334 reg = QLC_83XX_PORT1_THRESHOLD; 1335 } 1336 for (i = 0; i < 8; i++) { 1337 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1338 if (err == -EIO) 1339 return; 1340 dev_info(&adapter->pdev->dev, "0x%x ", val); 1341 } 1342 dev_info(&adapter->pdev->dev, "\n"); 1343 } 1344 1345 for (j = 0; j < 2; j++) { 1346 if (j == 0) { 1347 dev_info(&adapter->pdev->dev, 1348 "Port 0 RxB TC Max Cell Registers[4..1]:"); 1349 reg = QLC_83XX_PORT0_TC_MC_REG; 1350 } else if (j == 1) { 1351 dev_info(&adapter->pdev->dev, 1352 "Port 1 RxB TC Max Cell Registers[4..1]:"); 1353 reg = QLC_83XX_PORT1_TC_MC_REG; 1354 } 1355 for (i = 0; i < 4; i++) { 1356 val = QLCRD32(adapter, reg + (i * 0x4), &err); 1357 if (err == -EIO) 1358 return; 1359 dev_info(&adapter->pdev->dev, "0x%x ", val); 1360 } 1361 dev_info(&adapter->pdev->dev, "\n"); 1362 } 1363 1364 for (j = 0; j < 2; j++) { 1365 if (j == 0) { 1366 dev_info(&adapter->pdev->dev, 1367 "Port 0 RxB Rx TC Stats[TC7..TC0]:"); 1368 reg = QLC_83XX_PORT0_TC_STATS; 1369 } else if (j == 1) { 1370 dev_info(&adapter->pdev->dev, 1371 "Port 1 RxB Rx TC Stats[TC7..TC0]:"); 1372 reg = QLC_83XX_PORT1_TC_STATS; 1373 } 1374 for (i = 7; i >= 0; i--) { 1375 val = QLCRD32(adapter, reg, &err); 1376 if (err == -EIO) 1377 return; 1378 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ 1379 QLCWR32(adapter, reg, (val | (i << 29))); 1380 val = QLCRD32(adapter, reg, &err); 1381 if (err == -EIO) 1382 return; 1383 dev_info(&adapter->pdev->dev, "0x%x ", val); 1384 } 1385 dev_info(&adapter->pdev->dev, "\n"); 1386 } 1387 1388 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err); 1389 if (err == -EIO) 1390 return; 1391 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err); 1392 if (err == -EIO) 1393 return; 1394 dev_info(&adapter->pdev->dev, 1395 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", 1396 val, val1); 1397 } 1398 1399 1400 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter) 1401 { 1402 u32 reg = 0, i, j; 1403 1404 if (qlcnic_83xx_lock_driver(adapter)) { 1405 dev_err(&adapter->pdev->dev, 1406 "%s:failed to acquire driver lock\n", __func__); 1407 return; 1408 } 1409 1410 qlcnic_83xx_dump_pause_control_regs(adapter); 1411 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0); 1412 1413 for (j = 0; j < 2; j++) { 1414 if (j == 0) 1415 reg = QLC_83XX_PORT0_THRESHOLD; 1416 else if (j == 1) 1417 reg = QLC_83XX_PORT1_THRESHOLD; 1418 1419 for (i = 0; i < 8; i++) 1420 QLCWR32(adapter, reg + (i * 0x4), 0x0); 1421 } 1422 1423 for (j = 0; j < 2; j++) { 1424 if (j == 0) 1425 reg = QLC_83XX_PORT0_TC_MC_REG; 1426 else if (j == 1) 1427 reg = QLC_83XX_PORT1_TC_MC_REG; 1428 1429 for (i = 0; i < 4; i++) 1430 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF); 1431 } 1432 1433 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0); 1434 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0); 1435 dev_info(&adapter->pdev->dev, 1436 "Disabled pause frames successfully on all ports\n"); 1437 qlcnic_83xx_unlock_driver(adapter); 1438 } 1439 1440 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter) 1441 { 1442 QLCWR32(adapter, QLC_83XX_RESET_REG, 0); 1443 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0); 1444 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0); 1445 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0); 1446 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0); 1447 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0); 1448 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0); 1449 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0); 1450 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1); 1451 } 1452 1453 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev) 1454 { 1455 u32 heartbeat, peg_status; 1456 int retries, ret = -EIO, err = 0; 1457 1458 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT; 1459 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev, 1460 QLCNIC_PEG_ALIVE_COUNTER); 1461 1462 do { 1463 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS); 1464 heartbeat = QLC_SHARED_REG_RD32(p_dev, 1465 QLCNIC_PEG_ALIVE_COUNTER); 1466 if (heartbeat != p_dev->heartbeat) { 1467 ret = QLCNIC_RCODE_SUCCESS; 1468 break; 1469 } 1470 } while (--retries); 1471 1472 if (ret) { 1473 dev_err(&p_dev->pdev->dev, "firmware hang detected\n"); 1474 qlcnic_83xx_take_eport_out_of_reset(p_dev); 1475 qlcnic_83xx_disable_pause_frames(p_dev); 1476 peg_status = QLC_SHARED_REG_RD32(p_dev, 1477 QLCNIC_PEG_HALT_STATUS1); 1478 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n" 1479 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n" 1480 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n" 1481 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n" 1482 "PEG_NET_4_PC: 0x%x\n", peg_status, 1483 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2), 1484 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err), 1485 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err), 1486 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err), 1487 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err), 1488 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err)); 1489 1490 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67) 1491 dev_err(&p_dev->pdev->dev, 1492 "Device is being reset err code 0x00006700.\n"); 1493 } 1494 1495 return ret; 1496 } 1497 1498 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev) 1499 { 1500 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT; 1501 u32 val; 1502 1503 do { 1504 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE); 1505 if (val == QLC_83XX_CMDPEG_COMPLETE) 1506 return 0; 1507 msleep(QLCNIC_CMDPEG_CHECK_DELAY); 1508 } while (--retries); 1509 1510 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val); 1511 return -EIO; 1512 } 1513 1514 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev) 1515 { 1516 int err; 1517 1518 err = qlcnic_83xx_check_cmd_peg_status(p_dev); 1519 if (err) 1520 return err; 1521 1522 err = qlcnic_83xx_check_heartbeat(p_dev); 1523 if (err) 1524 return err; 1525 1526 return err; 1527 } 1528 1529 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr, 1530 int duration, u32 mask, u32 status) 1531 { 1532 int timeout_error, err = 0; 1533 u32 value; 1534 u8 retries; 1535 1536 value = QLCRD32(p_dev, addr, &err); 1537 if (err == -EIO) 1538 return err; 1539 retries = duration / 10; 1540 1541 do { 1542 if ((value & mask) != status) { 1543 timeout_error = 1; 1544 msleep(duration / 10); 1545 value = QLCRD32(p_dev, addr, &err); 1546 if (err == -EIO) 1547 return err; 1548 } else { 1549 timeout_error = 0; 1550 break; 1551 } 1552 } while (retries--); 1553 1554 if (timeout_error) { 1555 p_dev->ahw->reset.seq_error++; 1556 dev_err(&p_dev->pdev->dev, 1557 "%s: Timeout Err, entry_num = %d\n", 1558 __func__, p_dev->ahw->reset.seq_index); 1559 dev_err(&p_dev->pdev->dev, 1560 "0x%08x 0x%08x 0x%08x\n", 1561 value, mask, status); 1562 } 1563 1564 return timeout_error; 1565 } 1566 1567 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev) 1568 { 1569 u32 sum = 0; 1570 u16 *buff = (u16 *)p_dev->ahw->reset.buff; 1571 int count = p_dev->ahw->reset.hdr->size / sizeof(u16); 1572 1573 while (count-- > 0) 1574 sum += *buff++; 1575 1576 while (sum >> 16) 1577 sum = (sum & 0xFFFF) + (sum >> 16); 1578 1579 if (~sum) { 1580 return 0; 1581 } else { 1582 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1583 return -1; 1584 } 1585 } 1586 1587 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev) 1588 { 1589 struct qlcnic_hardware_context *ahw = p_dev->ahw; 1590 u32 addr, count, prev_ver, curr_ver; 1591 u8 *p_buff; 1592 1593 if (ahw->reset.buff != NULL) { 1594 prev_ver = p_dev->fw_version; 1595 curr_ver = qlcnic_83xx_get_fw_version(p_dev); 1596 if (curr_ver > prev_ver) 1597 kfree(ahw->reset.buff); 1598 else 1599 return 0; 1600 } 1601 1602 ahw->reset.seq_error = 0; 1603 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL); 1604 if (p_dev->ahw->reset.buff == NULL) 1605 return -ENOMEM; 1606 1607 p_buff = p_dev->ahw->reset.buff; 1608 addr = QLC_83XX_RESET_TEMPLATE_ADDR; 1609 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32); 1610 1611 /* Copy template header from flash */ 1612 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1613 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1614 return -EIO; 1615 } 1616 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff; 1617 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size; 1618 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1619 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32); 1620 1621 /* Copy rest of the template */ 1622 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) { 1623 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__); 1624 return -EIO; 1625 } 1626 1627 if (qlcnic_83xx_reset_template_checksum(p_dev)) 1628 return -EIO; 1629 /* Get Stop, Start and Init command offsets */ 1630 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset; 1631 ahw->reset.start_offset = ahw->reset.buff + 1632 ahw->reset.hdr->start_offset; 1633 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size; 1634 return 0; 1635 } 1636 1637 /* Read Write HW register command */ 1638 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev, 1639 u32 raddr, u32 waddr) 1640 { 1641 int err = 0; 1642 u32 value; 1643 1644 value = QLCRD32(p_dev, raddr, &err); 1645 if (err == -EIO) 1646 return; 1647 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1648 } 1649 1650 /* Read Modify Write HW register command */ 1651 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev, 1652 u32 raddr, u32 waddr, 1653 struct qlc_83xx_rmw *p_rmw_hdr) 1654 { 1655 int err = 0; 1656 u32 value; 1657 1658 if (p_rmw_hdr->index_a) { 1659 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a]; 1660 } else { 1661 value = QLCRD32(p_dev, raddr, &err); 1662 if (err == -EIO) 1663 return; 1664 } 1665 1666 value &= p_rmw_hdr->mask; 1667 value <<= p_rmw_hdr->shl; 1668 value >>= p_rmw_hdr->shr; 1669 value |= p_rmw_hdr->or_value; 1670 value ^= p_rmw_hdr->xor_value; 1671 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); 1672 } 1673 1674 /* Write HW register command */ 1675 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev, 1676 struct qlc_83xx_entry_hdr *p_hdr) 1677 { 1678 int i; 1679 struct qlc_83xx_entry *entry; 1680 1681 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1682 sizeof(struct qlc_83xx_entry_hdr)); 1683 1684 for (i = 0; i < p_hdr->count; i++, entry++) { 1685 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1, 1686 entry->arg2); 1687 if (p_hdr->delay) 1688 udelay((u32)(p_hdr->delay)); 1689 } 1690 } 1691 1692 /* Read and Write instruction */ 1693 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev, 1694 struct qlc_83xx_entry_hdr *p_hdr) 1695 { 1696 int i; 1697 struct qlc_83xx_entry *entry; 1698 1699 entry = (struct qlc_83xx_entry *)((char *)p_hdr + 1700 sizeof(struct qlc_83xx_entry_hdr)); 1701 1702 for (i = 0; i < p_hdr->count; i++, entry++) { 1703 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1, 1704 entry->arg2); 1705 if (p_hdr->delay) 1706 udelay((u32)(p_hdr->delay)); 1707 } 1708 } 1709 1710 /* Poll HW register command */ 1711 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev, 1712 struct qlc_83xx_entry_hdr *p_hdr) 1713 { 1714 long delay; 1715 struct qlc_83xx_entry *entry; 1716 struct qlc_83xx_poll *poll; 1717 int i, err = 0; 1718 unsigned long arg1, arg2; 1719 1720 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1721 sizeof(struct qlc_83xx_entry_hdr)); 1722 1723 entry = (struct qlc_83xx_entry *)((char *)poll + 1724 sizeof(struct qlc_83xx_poll)); 1725 delay = (long)p_hdr->delay; 1726 1727 if (!delay) { 1728 for (i = 0; i < p_hdr->count; i++, entry++) 1729 qlcnic_83xx_poll_reg(p_dev, entry->arg1, 1730 delay, poll->mask, 1731 poll->status); 1732 } else { 1733 for (i = 0; i < p_hdr->count; i++, entry++) { 1734 arg1 = entry->arg1; 1735 arg2 = entry->arg2; 1736 if (delay) { 1737 if (qlcnic_83xx_poll_reg(p_dev, 1738 arg1, delay, 1739 poll->mask, 1740 poll->status)){ 1741 QLCRD32(p_dev, arg1, &err); 1742 if (err == -EIO) 1743 return; 1744 QLCRD32(p_dev, arg2, &err); 1745 if (err == -EIO) 1746 return; 1747 } 1748 } 1749 } 1750 } 1751 } 1752 1753 /* Poll and write HW register command */ 1754 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev, 1755 struct qlc_83xx_entry_hdr *p_hdr) 1756 { 1757 int i; 1758 long delay; 1759 struct qlc_83xx_quad_entry *entry; 1760 struct qlc_83xx_poll *poll; 1761 1762 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1763 sizeof(struct qlc_83xx_entry_hdr)); 1764 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1765 sizeof(struct qlc_83xx_poll)); 1766 delay = (long)p_hdr->delay; 1767 1768 for (i = 0; i < p_hdr->count; i++, entry++) { 1769 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr, 1770 entry->dr_value); 1771 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1772 entry->ar_value); 1773 if (delay) 1774 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1775 poll->mask, poll->status); 1776 } 1777 } 1778 1779 /* Read Modify Write register command */ 1780 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev, 1781 struct qlc_83xx_entry_hdr *p_hdr) 1782 { 1783 int i; 1784 struct qlc_83xx_entry *entry; 1785 struct qlc_83xx_rmw *rmw_hdr; 1786 1787 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr + 1788 sizeof(struct qlc_83xx_entry_hdr)); 1789 1790 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr + 1791 sizeof(struct qlc_83xx_rmw)); 1792 1793 for (i = 0; i < p_hdr->count; i++, entry++) { 1794 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1, 1795 entry->arg2, rmw_hdr); 1796 if (p_hdr->delay) 1797 udelay((u32)(p_hdr->delay)); 1798 } 1799 } 1800 1801 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr) 1802 { 1803 if (p_hdr->delay) 1804 mdelay((u32)((long)p_hdr->delay)); 1805 } 1806 1807 /* Read and poll register command */ 1808 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev, 1809 struct qlc_83xx_entry_hdr *p_hdr) 1810 { 1811 long delay; 1812 int index, i, j, err; 1813 struct qlc_83xx_quad_entry *entry; 1814 struct qlc_83xx_poll *poll; 1815 unsigned long addr; 1816 1817 poll = (struct qlc_83xx_poll *)((char *)p_hdr + 1818 sizeof(struct qlc_83xx_entry_hdr)); 1819 1820 entry = (struct qlc_83xx_quad_entry *)((char *)poll + 1821 sizeof(struct qlc_83xx_poll)); 1822 delay = (long)p_hdr->delay; 1823 1824 for (i = 0; i < p_hdr->count; i++, entry++) { 1825 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr, 1826 entry->ar_value); 1827 if (delay) { 1828 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay, 1829 poll->mask, poll->status)){ 1830 index = p_dev->ahw->reset.array_index; 1831 addr = entry->dr_addr; 1832 j = QLCRD32(p_dev, addr, &err); 1833 if (err == -EIO) 1834 return; 1835 1836 p_dev->ahw->reset.array[index++] = j; 1837 1838 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES) 1839 p_dev->ahw->reset.array_index = 1; 1840 } 1841 } 1842 } 1843 } 1844 1845 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev) 1846 { 1847 p_dev->ahw->reset.seq_end = 1; 1848 } 1849 1850 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev) 1851 { 1852 p_dev->ahw->reset.template_end = 1; 1853 if (p_dev->ahw->reset.seq_error == 0) 1854 dev_err(&p_dev->pdev->dev, 1855 "HW restart process completed successfully.\n"); 1856 else 1857 dev_err(&p_dev->pdev->dev, 1858 "HW restart completed with timeout errors.\n"); 1859 } 1860 1861 /** 1862 * qlcnic_83xx_exec_template_cmd 1863 * 1864 * @p_dev: adapter structure 1865 * @p_buff: Poiter to instruction template 1866 * 1867 * Template provides instructions to stop, restart and initalize firmware. 1868 * These instructions are abstracted as a series of read, write and 1869 * poll operations on hardware registers. Register information and operation 1870 * specifics are not exposed to the driver. Driver reads the template from 1871 * flash and executes the instructions located at pre-defined offsets. 1872 * 1873 * Returns: None 1874 * */ 1875 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev, 1876 char *p_buff) 1877 { 1878 int index, entries; 1879 struct qlc_83xx_entry_hdr *p_hdr; 1880 char *entry = p_buff; 1881 1882 p_dev->ahw->reset.seq_end = 0; 1883 p_dev->ahw->reset.template_end = 0; 1884 entries = p_dev->ahw->reset.hdr->entries; 1885 index = p_dev->ahw->reset.seq_index; 1886 1887 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) { 1888 p_hdr = (struct qlc_83xx_entry_hdr *)entry; 1889 1890 switch (p_hdr->cmd) { 1891 case QLC_83XX_OPCODE_NOP: 1892 break; 1893 case QLC_83XX_OPCODE_WRITE_LIST: 1894 qlcnic_83xx_write_list(p_dev, p_hdr); 1895 break; 1896 case QLC_83XX_OPCODE_READ_WRITE_LIST: 1897 qlcnic_83xx_read_write_list(p_dev, p_hdr); 1898 break; 1899 case QLC_83XX_OPCODE_POLL_LIST: 1900 qlcnic_83xx_poll_list(p_dev, p_hdr); 1901 break; 1902 case QLC_83XX_OPCODE_POLL_WRITE_LIST: 1903 qlcnic_83xx_poll_write_list(p_dev, p_hdr); 1904 break; 1905 case QLC_83XX_OPCODE_READ_MODIFY_WRITE: 1906 qlcnic_83xx_read_modify_write(p_dev, p_hdr); 1907 break; 1908 case QLC_83XX_OPCODE_SEQ_PAUSE: 1909 qlcnic_83xx_pause(p_hdr); 1910 break; 1911 case QLC_83XX_OPCODE_SEQ_END: 1912 qlcnic_83xx_seq_end(p_dev); 1913 break; 1914 case QLC_83XX_OPCODE_TMPL_END: 1915 qlcnic_83xx_template_end(p_dev); 1916 break; 1917 case QLC_83XX_OPCODE_POLL_READ_LIST: 1918 qlcnic_83xx_poll_read_list(p_dev, p_hdr); 1919 break; 1920 default: 1921 dev_err(&p_dev->pdev->dev, 1922 "%s: Unknown opcode 0x%04x in template %d\n", 1923 __func__, p_hdr->cmd, index); 1924 break; 1925 } 1926 entry += p_hdr->size; 1927 } 1928 p_dev->ahw->reset.seq_index = index; 1929 } 1930 1931 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev) 1932 { 1933 p_dev->ahw->reset.seq_index = 0; 1934 1935 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset); 1936 if (p_dev->ahw->reset.seq_end != 1) 1937 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1938 } 1939 1940 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev) 1941 { 1942 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset); 1943 if (p_dev->ahw->reset.template_end != 1) 1944 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1945 } 1946 1947 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev) 1948 { 1949 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset); 1950 if (p_dev->ahw->reset.seq_end != 1) 1951 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__); 1952 } 1953 1954 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter) 1955 { 1956 struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info; 1957 int err = -EIO; 1958 1959 if (request_firmware(&fw_info->fw, fw_info->fw_file_name, 1960 &(adapter->pdev->dev))) { 1961 dev_err(&adapter->pdev->dev, 1962 "No file FW image, loading flash FW image.\n"); 1963 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1964 QLC_83XX_BOOT_FROM_FLASH); 1965 } else { 1966 if (qlcnic_83xx_copy_fw_file(adapter)) 1967 return err; 1968 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1969 QLC_83XX_BOOT_FROM_FILE); 1970 } 1971 1972 return 0; 1973 } 1974 1975 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter) 1976 { 1977 u32 val; 1978 int err = -EIO; 1979 1980 qlcnic_83xx_stop_hw(adapter); 1981 1982 /* Collect FW register dump if required */ 1983 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL); 1984 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET)) 1985 qlcnic_dump_fw(adapter); 1986 qlcnic_83xx_init_hw(adapter); 1987 1988 if (qlcnic_83xx_copy_bootloader(adapter)) 1989 return err; 1990 /* Boot either flash image or firmware image from host file system */ 1991 if (qlcnic_load_fw_file) { 1992 if (qlcnic_83xx_load_fw_image_from_host(adapter)) 1993 return err; 1994 } else { 1995 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID, 1996 QLC_83XX_BOOT_FROM_FLASH); 1997 } 1998 1999 qlcnic_83xx_start_hw(adapter); 2000 if (qlcnic_83xx_check_hw_status(adapter)) 2001 return -EIO; 2002 2003 return 0; 2004 } 2005 2006 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter) 2007 { 2008 int err; 2009 struct qlcnic_info nic_info; 2010 struct qlcnic_hardware_context *ahw = adapter->ahw; 2011 2012 memset(&nic_info, 0, sizeof(struct qlcnic_info)); 2013 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func); 2014 if (err) 2015 return -EIO; 2016 2017 ahw->physical_port = (u8) nic_info.phys_port; 2018 ahw->switch_mode = nic_info.switch_mode; 2019 ahw->max_tx_ques = nic_info.max_tx_ques; 2020 ahw->max_rx_ques = nic_info.max_rx_ques; 2021 ahw->capabilities = nic_info.capabilities; 2022 ahw->max_mac_filters = nic_info.max_mac_filters; 2023 ahw->max_mtu = nic_info.max_mtu; 2024 2025 /* eSwitch capability indicates vNIC mode. 2026 * vNIC and SRIOV are mutually exclusive operational modes. 2027 * If SR-IOV capability is detected, SR-IOV physical function 2028 * will get initialized in default mode. 2029 * SR-IOV virtual function initialization follows a 2030 * different code path and opmode. 2031 * SRIOV mode has precedence over vNIC mode. 2032 */ 2033 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) 2034 return QLC_83XX_DEFAULT_OPMODE; 2035 2036 if (ahw->capabilities & QLC_83XX_ESWITCH_CAPABILITY) 2037 return QLC_83XX_VIRTUAL_NIC_MODE; 2038 2039 return QLC_83XX_DEFAULT_OPMODE; 2040 } 2041 2042 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter) 2043 { 2044 struct qlcnic_hardware_context *ahw = adapter->ahw; 2045 int ret; 2046 2047 ret = qlcnic_83xx_get_nic_configuration(adapter); 2048 if (ret == -EIO) 2049 return -EIO; 2050 2051 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) { 2052 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE; 2053 if (qlcnic_83xx_config_vnic_opmode(adapter)) 2054 return -EIO; 2055 2056 } else if (ret == QLC_83XX_DEFAULT_OPMODE) { 2057 ahw->nic_mode = QLC_83XX_DEFAULT_MODE; 2058 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver; 2059 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; 2060 } else { 2061 return -EIO; 2062 } 2063 2064 return 0; 2065 } 2066 2067 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter) 2068 { 2069 struct qlcnic_hardware_context *ahw = adapter->ahw; 2070 2071 if (ahw->port_type == QLCNIC_XGBE) { 2072 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G; 2073 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G; 2074 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2075 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 2076 2077 } else if (ahw->port_type == QLCNIC_GBE) { 2078 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G; 2079 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2080 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G; 2081 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G; 2082 } 2083 adapter->num_txd = MAX_CMD_DESCRIPTORS; 2084 adapter->max_rds_rings = MAX_RDS_RINGS; 2085 } 2086 2087 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter) 2088 { 2089 int err = -EIO; 2090 2091 qlcnic_83xx_get_minidump_template(adapter); 2092 if (qlcnic_83xx_get_port_info(adapter)) 2093 return err; 2094 2095 qlcnic_83xx_config_buff_descriptors(adapter); 2096 adapter->ahw->msix_supported = !!qlcnic_use_msi_x; 2097 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED; 2098 2099 dev_info(&adapter->pdev->dev, "HAL Version: %d\n", 2100 adapter->ahw->fw_hal_version); 2101 2102 return 0; 2103 } 2104 2105 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1)) 2106 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter) 2107 { 2108 struct qlcnic_cmd_args cmd; 2109 u32 presence_mask, audit_mask; 2110 int status; 2111 2112 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); 2113 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT); 2114 2115 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) { 2116 status = qlcnic_alloc_mbx_args(&cmd, adapter, 2117 QLCNIC_CMD_STOP_NIC_FUNC); 2118 if (status) 2119 return; 2120 2121 cmd.req.arg[1] = BIT_31; 2122 status = qlcnic_issue_cmd(adapter, &cmd); 2123 if (status) 2124 dev_err(&adapter->pdev->dev, 2125 "Failed to clean up the function resources\n"); 2126 qlcnic_free_mbx_args(&cmd); 2127 } 2128 } 2129 2130 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter) 2131 { 2132 struct qlcnic_hardware_context *ahw = adapter->ahw; 2133 struct pci_dev *pdev = adapter->pdev; 2134 struct qlc_83xx_fw_info *fw_info; 2135 int err = 0; 2136 2137 ahw->fw_info = kzalloc(sizeof(*fw_info), GFP_KERNEL); 2138 if (!ahw->fw_info) { 2139 err = -ENOMEM; 2140 } else { 2141 fw_info = ahw->fw_info; 2142 switch (pdev->device) { 2143 case PCI_DEVICE_ID_QLOGIC_QLE834X: 2144 strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME, 2145 QLC_FW_FILE_NAME_LEN); 2146 break; 2147 case PCI_DEVICE_ID_QLOGIC_QLE844X: 2148 strncpy(fw_info->fw_file_name, QLC_84XX_FW_FILE_NAME, 2149 QLC_FW_FILE_NAME_LEN); 2150 break; 2151 default: 2152 dev_err(&pdev->dev, "%s: Invalid device id\n", 2153 __func__); 2154 err = -EINVAL; 2155 break; 2156 } 2157 } 2158 2159 return err; 2160 } 2161 2162 2163 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac) 2164 { 2165 struct qlcnic_hardware_context *ahw = adapter->ahw; 2166 int err = 0; 2167 2168 ahw->msix_supported = !!qlcnic_use_msi_x; 2169 err = qlcnic_83xx_init_mailbox_work(adapter); 2170 if (err) 2171 goto exit; 2172 2173 if (qlcnic_sriov_vf_check(adapter)) { 2174 err = qlcnic_sriov_vf_init(adapter, pci_using_dac); 2175 if (err) 2176 goto detach_mbx; 2177 else 2178 return err; 2179 } 2180 2181 err = qlcnic_83xx_check_hw_status(adapter); 2182 if (err) 2183 goto detach_mbx; 2184 2185 if (!qlcnic_83xx_read_flash_descriptor_table(adapter)) 2186 qlcnic_83xx_read_flash_mfg_id(adapter); 2187 2188 err = qlcnic_83xx_get_fw_info(adapter); 2189 if (err) 2190 goto detach_mbx; 2191 2192 err = qlcnic_83xx_idc_init(adapter); 2193 if (err) 2194 goto clear_fw_info; 2195 2196 err = qlcnic_setup_intr(adapter, 0, 0); 2197 if (err) { 2198 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n"); 2199 goto disable_intr; 2200 } 2201 2202 err = qlcnic_83xx_setup_mbx_intr(adapter); 2203 if (err) 2204 goto disable_mbx_intr; 2205 2206 qlcnic_83xx_clear_function_resources(adapter); 2207 2208 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work); 2209 2210 /* register for NIC IDC AEN Events */ 2211 qlcnic_83xx_register_nic_idc_func(adapter, 1); 2212 2213 /* Configure default, SR-IOV or Virtual NIC mode of operation */ 2214 err = qlcnic_83xx_configure_opmode(adapter); 2215 if (err) 2216 goto disable_mbx_intr; 2217 2218 /* Perform operating mode specific initialization */ 2219 err = adapter->nic_ops->init_driver(adapter); 2220 if (err) 2221 goto disable_mbx_intr; 2222 2223 if (adapter->dcb && qlcnic_dcb_attach(adapter)) 2224 qlcnic_clear_dcb_ops(adapter); 2225 2226 /* Periodically monitor device status */ 2227 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work); 2228 return 0; 2229 2230 disable_mbx_intr: 2231 qlcnic_83xx_free_mbx_intr(adapter); 2232 2233 disable_intr: 2234 qlcnic_teardown_intr(adapter); 2235 2236 clear_fw_info: 2237 kfree(ahw->fw_info); 2238 2239 detach_mbx: 2240 qlcnic_83xx_detach_mailbox_work(adapter); 2241 qlcnic_83xx_free_mailbox(ahw->mailbox); 2242 exit: 2243 return err; 2244 } 2245 2246 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter) 2247 { 2248 struct qlcnic_hardware_context *ahw = adapter->ahw; 2249 struct qlc_83xx_idc *idc = &ahw->idc; 2250 2251 clear_bit(QLC_83XX_MBX_READY, &idc->status); 2252 cancel_delayed_work_sync(&adapter->fw_work); 2253 2254 if (ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) 2255 qlcnic_83xx_disable_vnic_mode(adapter, 1); 2256 2257 qlcnic_83xx_idc_detach_driver(adapter); 2258 qlcnic_83xx_register_nic_idc_func(adapter, 0); 2259 2260 cancel_delayed_work_sync(&adapter->idc_aen_work); 2261 } 2262 2263 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter) 2264 { 2265 struct qlcnic_hardware_context *ahw = adapter->ahw; 2266 struct qlc_83xx_idc *idc = &ahw->idc; 2267 int ret = 0; 2268 u32 owner; 2269 2270 /* Mark the previous IDC state as NEED_RESET so 2271 * that state_entry() will perform the reattachment 2272 * and bringup the device 2273 */ 2274 idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET; 2275 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2276 if (ahw->pci_func == owner) { 2277 ret = qlcnic_83xx_restart_hw(adapter); 2278 if (ret < 0) 2279 return ret; 2280 qlcnic_83xx_idc_clear_registers(adapter, 0); 2281 } 2282 2283 ret = idc->state_entry(adapter); 2284 return ret; 2285 } 2286 2287 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter) 2288 { 2289 struct qlcnic_hardware_context *ahw = adapter->ahw; 2290 struct qlc_83xx_idc *idc = &ahw->idc; 2291 u32 owner; 2292 2293 idc->prev_state = QLC_83XX_IDC_DEV_READY; 2294 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter); 2295 if (ahw->pci_func == owner) 2296 qlcnic_83xx_idc_enter_ready_state(adapter, 0); 2297 2298 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0); 2299 } 2300